[ { "path": ".gitignore", "content": "# Object files\n*.o\n\n# system Directories\n/Debug\n/Release\n/.settings\n/out\n\n.cproject\n.cproject.backup\n" }, { "path": ".project", "content": "\n\n\tEvvGC\n\t\n\t\n\t\n\t\n\t\t\n\t\t\torg.eclipse.cdt.managedbuilder.core.genmakebuilder\n\t\t\tclean,full,incremental,\n\t\t\t\n\t\t\t\n\t\t\n\t\t\n\t\t\torg.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder\n\t\t\tfull,incremental,\n\t\t\t\n\t\t\t\n\t\t\n\t\n\t\n\t\torg.eclipse.cdt.core.cnature\n\t\torg.eclipse.cdt.managedbuilder.core.managedBuildNature\n\t\torg.eclipse.cdt.managedbuilder.core.ScannerConfigNature\n\t\n\n" }, { "path": "ArmGCC47.bat", "content": "@echo off\nrem This file is the script to set path for ARM eabi tool chain.\n\nrem set PATH=C:\\Program Files (x86)\\GNU Tools ARM Embedded\\4.7 2012q4\\bin;%PATH%\nset PATH=C:\\Program Files (x86)\\GNU Tools ARM Embedded\\4.7 2013q2\\bin;%PATH%\nstart\n" }, { "path": "Documentation/devEnvSetupEclipse.md", "content": "# Setting Up Build Environment (Windows)\r\n\r\n#### *Note: This tutorial was written using Windows 7, so there may be slight differences for your version*\r\n\r\n1. \tDownload [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded) \r\n\t1.\t**Save Windows Zip Package (gcc-arm-non...4-win32.zip) to computer**\r\n\t1.\tUnzip package\r\n\t1.\tCopy \"GNU Tools ARM Embedded\" folder out of zip archive\r\n\t\t*\tAssumed copy location for tutorial **C:\\Program Files (x86)\\GNU Tools ARM Embedded\\**\r\n2. \tDownload [Cygwin](http://cygwin.com/install.html)\r\n\t1.\tDownload setup.exe and run\r\n\t\t* \tAssuming install location of **C:\\cygwin** for this tutorial\r\n\t2. \tWhen prompted to select packages make sure you select the devel package (click \"Default\" so it says \"Install\")\r\n\t\t*Note: The whole packages is not required but easiest for this writeup this will give you make and git (required), plus much more*\r\n\t3.\tOn next screen check box to \"Select required packages\"\r\n\t4.\tWait for install to finish (insert long coffee/beer break here!)\r\n3.\tDownload [Eclipse Standard](http://www.eclipse.org/downloads/)\r\n\t*\t32 and 64 bit version are available\r\n\t*\tYou may need to install a Java [JRE](http://www.oracle.com/technetwork/java/javase/downloads/index.html) (*make sure you select the JRE to download*)\r\n\t*\tThis does not need to be installed just run the exe (I prefer to extract to C:\\Program Files\\eclipse)\r\n\t*\t**You must run eclipse now to setup workspace (take note of location) for later steps**\r\n4.\tMake copies of necessary .exe files for eclipese\r\n\t1.\tOpen Cygwin\r\n\t2.\tNavigate to **/cygdrive/c/cygwin/bin**\r\n\r\n\t\t\t$ cd /cygdrive/c/cygwin/bin\r\n\t3.\tCopy rm to cs-rm\r\n\t\r\n\t\t\t$ cp ./rm ./cs-rm\r\n\t4.\tCopy make to cs-make\r\n\t\t\r\n\t\t\t$ cp ./make ./cs-make\r\n5.\tUpdate PATH Variable\r\n\t1. \tSelect Start\r\n\t2.\tRight Click on Computer\r\n\t3.\tSelect Properties\r\n\t4.\tSelect Advanced System Settings\r\n\t5.\tSelect Advanced Tab\r\n\t6.\tSelect Environment Variables...\r\n\t7.\tIn the System Variables pane scroll down and select PATH\r\n\t8.\tSelect Edit\r\n\t9.\tScroll to end of text\r\n\t10. Insert the follow at the END of the current path\r\n\t\r\n\t\t`;C:\\cygwin\\bin\\;C:\\Program Files (x86)\\GNU Tools ARM Embedded\\4.7 2013q2\\bin`\r\n\t\t\r\n\t\t**Note:** *version of GNU Tools ARM may have changed for you (ie. 4.7 2013q2), please verify*\r\n\t11.\tClick OK\r\n5.\tClone git repo\r\n\t1.\tIn cygwin navigate to your eclipse workspace (selected during Cygwin install)\r\n\t2.\tClone Repo\r\n\t\t\r\n\t\t\t$ git clone https://github.com/EvvGC/Firmware.git\r\n6.\tSetup Eclipse\r\n\t1.\tMove template .cproject file so eclipse will see it for importing\r\n\t\t\r\n\t\t\t$ cd Firmware\r\n\t\t\t$ cp setup/.cproject.orig .cproject\r\n\t2.\tOpen Eclipse\r\n\t3.\tClose Welcome screen\r\n\t3.\tInstall GNU Arm Plugin\r\n\t\t*\tSee eclipseSetup.pdf steps 3 - 10\r\n\t4.\tImport Project\r\n\t\t*\tSee eclipseSetup.pdf steps 12 - 14 Substituting 'Firmware' for 'aq32plus'\r\n\t5.\tConfigure Project\r\n\t\t1.\tEnsure build variables are correct.\r\n\t\t\t1. In the Project Explorer tab, right click on Firmware, select properties\r\n 2. Expand C/C++ Build in the left panel\r\n\t\t\t3.\tSelect Build Variables in left panel\r\n\t\t\t4.\tCheck to make sure GCCPATH and GCCVERSION is correct.\r\n\t\t\t\t*\tBoth these values can be figured by looking at directory structure from download of step 1\r\n\t\t\t\t*\tGCCPATH will probably need '4.7 2013q2' updated to newer version as this was the version at time of writing\r\n\t\t\t\t*\tGCCVERSION will probably need to be updated as 4.7.4 was current at time of writing\r\n\t\t\t7.\tClose Properties Panel\r\n7.\tClean Project\r\n\t1. \tSelect Project from menu bar\r\n\t2.\tSelect Clean...\r\n\t3.\tSelect Clean All Projects and then OK\r\n8.\tBuild Project\r\n\t1.\tSelect Project from the menu bar\r\n\t2.\tSelect Build All\r\n\t3.\tVerify success by seeing \"Finished building: EvvGC.hex\" as the third to last line of the Console output on the lower right of eclipse.\r\n\t\r\n\t\r\n## DONE\r\n\r\n9.\tIf you are getting build error because of the USB source. Exclude unneeded source. For \"Libraries>STM32\\_USB\\_Library\", \"Libraries>STM32\\_OTG\\_Driver\"\r\n\t1.\tRight click on the directory in the project explorer\r\n\t2. Select Resource Configuration > Exclude from Build...\r\n\t3. Select Debug and Release\r\n\t4. Select OK\r\n\t5. Right click on project in the project Explorer\r\n\t6.\tSelect Index > Rebuild\r\n\t\r\n\t\r\n" }, { "path": "Documentation/devEnvSetupNoCygwin.md", "content": "# Setting Up Build Environment (Windows)\r\n\r\n#### *Note: This tutorial was written using Windows 7, so there may be slight differences for your version*\r\n\r\n1. \tDownload [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded) \r\n\t1.\t**Save Windows Zip Package (gcc-arm-non...4-win32.zip) to computer**\r\n\t1.\tUnzip package\r\n\t1.\tCopy \"GNU Tools ARM Embedded\" folder out of zip archive\r\n\t\t*\tAssumed copy location for tutorial **C:\\Program Files (x86)\\GNU Tools ARM Embedded\\**\r\n2.\tInstall [GNU Make for Windows](http://gnuwin32.sourceforge.net/packages/make.htm)\r\n\t1.\tDownload \"Complete package, except sources\"\r\n\t2.\tRun Installer\r\n\t3.\tSelect default install location **C:\\Program Files (x86)\\GnuWin32**\r\n\t4.\tUnder Select Components select either \"Full Installation\" or \"Compact Installation\" as both contain binaries needed\r\n\t5.\tSelect defaults for the rest of the installer and finish installation\r\n3.\tInstall [GNU CoreUtils for Windows](http://gnuwin32.sourceforge.net/packages/coreutils.htm)\r\n\t1.\tDownload \"Complete package, except sources\"\r\n\t2.\tRun Installer\r\n\t3.\tSelect default install location **C:\\Program Files (x86)\\GnuWin32**\r\n\t4.\tUnder Select Components select either \"Full Installation\" or \"Compact Installation\" as both contain binaries needed\r\n\t5.\tSelect defaults for the rest of the installer and finish installation\r\n4.\tMake copies of necessary .exe files for eclipse\r\n\t1.\tOpen **C:\\Program Files (x86)\\GnuWin32\\bin** in Windows Explorer\r\n\t2.\tcopy make.exe to cs-make.exe\r\n\t3.\tcopy rm.exe to cs-rm.exe\r\n\t\r\n\t**NOTE: you may not see the .exe in your window if you have extensions hidden (default)**\r\n5.\tUpdate PATH Variable\r\n\t1. \tSelect Start\r\n\t2.\tRight Click on Computer\r\n\t3.\tSelect Properties\r\n\t4.\tSelect Advanced System Settings\r\n\t5.\tSelect Advanced Tab\r\n\t6.\tSelect Environment Variables...\r\n\t7.\tIn the System Variables pane scroll down and select PATH\r\n\t8.\tSelect Edit\r\n\t9.\tScroll to end of text\r\n\t10. Insert the follow at the END of the current path\r\n\t\r\n\t\t`;C:\\Program Files (x86)\\GnuWin32\\bin;C:\\Program Files (x86)\\GNU Tools ARM Embedded\\4.7 2013q2\\bin`\r\n\t\t\r\n\t\t**Note:** *version of GNU Tools ARM may have changed for you (ie. 4.7 2013q2), please verify*\r\n\t11.\tClick OK\r\n5.\tGet source code\r\n\t1.\tDownload [Firmware Source Code](https://github.com/EvvGC/Firmware/archive/master.zip)\r\n\t2.\tExtract zip to Eclipse Workspace\r\n\t\t*\tDirectory Structure will look something like C:\\Users\\{Username}\\workspace\\Firmware-master once extracted\r\n6.\tDownload [Eclipse Standard](http://www.eclipse.org/downloads/)\r\n\t*\t32 and 64 bit version are available\r\n\t*\tYou may need to install a Java [JRE](http://www.oracle.com/technetwork/java/javase/downloads/index.html) (*make sure you select the JRE to download*)\r\n\t*\tThis does not need to be installed just run the exe (I prefer to extract to C:\\Program Files\\eclipse)\r\n\t*\t**You must run eclipse now to setup workspace (take note of location) for later steps**\r\n7.\tSetup Eclipse\r\n\t1.\tMove template .cproject file so Eclipse will see it for importing\r\n\t\t1.\tOpen Command Prompt and navigate to git repository directory from last step\r\n\t\t\t*\tClick Start\r\n\t\t\t*\ttype \"cmd\" in search box to open DOS prompt\r\n\t\t\t*\tcd to workspace directory\r\n\t\t\t\t\r\n\t\t\t\t`> cd workspace`\r\n\t\t\t*\tcd into extracted source directory\r\n\t\t\t\r\n\t\t\t\t`> cd Firmware-master`\r\n\t\t\t\t\r\n\t\t1.\tMove setup/.cproject.org to .cproject\r\n\t\t\r\n\t\t\t`> copy setup/.cproject.orig .cproject`\r\n\t2.\tOpen Eclipse\r\n\t3.\tClose Welcome screen\r\n\t3.\tInstall GNU Arm Plugin\r\n\t\t*\tSee eclipseSetup.pdf steps 3 - 10\r\n\t4.\tImport Project\r\n\t\t*\tSee eclipseSetup.pdf steps 12 - 14 Substituting 'Firmware-master' for 'aq32plus'\r\n\t5.\tConfigure Project\r\n\t\t1.\tEnsure build variables are correct.\r\n\t\t\t1. In the Project Explorer tab, right click on Firmware-master, select properties\r\n 2. Expand C/C++ Build in the left panel\r\n\t\t\t3.\tSelect Build Variables in left panel\r\n\t\t\t4.\tCheck to make sure GCCPATH and GCCVERSION is correct.\r\n\t\t\t\t*\tBoth these values can be figured by looking at directory structure from download of step 1\r\n\t\t\t\t*\tGCCPATH will probably need '4.7 2013q2' updated to newer version as this was the version at time of writing\r\n\t\t\t\t*\tGCCVERSION will probably need to be updated as 4.7.4 was current at time of writing\r\n\t\t\t7.\tClose Properties Panel\r\n8.\tClean Project\r\n\t1. \tSelect Project from menu bar\r\n\t2.\tSelect Clean...\r\n\t3.\tSelect Clean All Projects and then OK\r\n9.\tBuild Project\r\n\t1.\tSelect Project from the menu bar\r\n\t2.\tSelect Build All\r\n\t3.\tVerify success by seeing \"Finished building: EvvGC.hex\" as the third to last line of the Console output on the lower right of eclipse.\r\n\t\r\n\t\r\n## DONE\r\n\r\n10.\tIf you are getting build error because of the USB source. Exclude unneeded source. For \"Libraries>STM32\\_USB\\_Library\", \"Libraries>STM32\\_OTG\\_Driver\"\r\n\t1.\tRight click on the directory in the project explorer\r\n\t2. Select Resource Configuration > Exclude from Build...\r\n\t3. Select Debug and Release\r\n\t4. Select OK\r\n\t5. Right click on project in the project Explorer\r\n\t6.\tSelect Index > Rebuild\r\n\t\r\n\t\r\n" }, { "path": "FlashDFUSe.bat", "content": "@echo off\nset filename=%1%\nset FLASHTOOL=setup\\dfu-util-static.exe\n\nif \"%filename%\" == \"\" set filename=out\\STM32Gimbal.USB.bin\n\necho taking board into boot mode ...\nREM boot loader hack by ala42\nREM let dfu-util talk to the USB VCP address. This is detected by the VCP handler\nREM which takes the board into the boot loader\n%FLASHTOOL% --device 0483:5740 -D dummyname 2>1 >nul\ncall :sleep 4\n\necho starting upload ...\necho.\n:loop\n %FLASHTOOL% --reset --device 1eaf:0003 --alt 1 --download %filename% && goto :end\n call :sleep 2\n goto :loop\n\n:sleep\n ping -n %1 localhost >nul\n goto :EOF\n\n:end\n pause\n" }, { "path": "FlashV2.bat", "content": "@echo off\nset flasher=\"%ProgramFiles%\\STMicroelectronics\\STM32 ST-LINK Utility\\ST-LINK Utility\\ST-LINK_CLI.exe\"\nif exist %flasher% goto :flash\nset flasher=\"%ProgramFiles(x86)%\\STMicroelectronics\\STM32 ST-LINK Utility\\ST-LINK Utility\\ST-LINK_CLI.exe\"\n\n:flash\nset filename=%1%\nif \"%filename%\" == \"\" set filename=out\\STM32Gimbal.USB.bin\n\n%flasher% -c SWD -P %filename% 0x08004000 -V -Rst\npause" }, { "path": "FlashV2_LowMem.bat", "content": "@echo off\nset flasher=\"%ProgramFiles%\\STMicroelectronics\\STM32 ST-LINK Utility\\ST-LINK Utility\\ST-LINK_CLI.exe\"\nif exist %flasher% goto :flash\nset flasher=\"%ProgramFiles(x86)%\\STMicroelectronics\\STM32 ST-LINK Utility\\ST-LINK Utility\\ST-LINK_CLI.exe\"\n\n:flash\nset filename=%1%\nif \"%filename%\" == \"\" set filename=out\\STM32Gimbal.bin\n\n%flasher% -c SWD -P %filename% 0x08000000 -V -Rst\npause" }, { "path": "ForceBootloader.bat", "content": "@echo off\nset filename=%1%\nset FLASHTOOL=setup\\dfu-util-static.exe\n\nif \"%filename%\" == \"\" set filename=out\\STM32Gimbal.USB.bin\n\necho taking board into boot mode ...\nREM boot loader hack by ala42\nREM let dfu-util talk to the USB VCP address. This is detected by the VCP handler\nREM which takes the board into the boot loader\n%FLASHTOOL% --device 0483:5740 -D dummyname 2>1 >nul\n" }, { "path": "GUI/EvvGC_GUI_v0_4/EvvGC_GUI_v0_4.pde", "content": "import processing.serial.*;\nimport controlP5.*; // controlP5 library\nimport processing.opengl.*;\n\nControlP5 controlP5;\n//The serial port:\nSerial myPort;\n\nint xPP = 80;\nint yPP = 100;\nint xPD = 200;\nint yPD = 100;\nint xRP = 80;\nint yRP = 150;\nint xRD = 200;\nint yRD = 150;\nint xYP = 80;\nint yYP = 200;\nint xYD = 200;\nint yYD = 200;\nint xPPWR = 375;\nint yPPWR = 100;\nint xRPWR = 375;\nint yRPWR = 150;\nint xYPWR = 375;\nint yYPWR = 200;\nint xRollCal = 480;\nint yRollCal = 200;\nint xRollZero = 540;\nint yRollZero = 200;\n\n// Constants\nint Y_AXIS = 1;\nint X_AXIS = 2;\ncolor b1, b2, c1, c2;\n\n\nNumberbox PitchP;\nNumberbox PitchD;\nNumberbox RollP;\nNumberbox RollD;\nNumberbox YawP;\nNumberbox YawD;\nNumberbox PitchPWR;\nNumberbox RollPWR;\nNumberbox YawPWR;\nNumberbox RollCal;\nButton buttonREAD,buttonWRITE, buttonCONFon, buttonCONFoff, buttonP0, buttonP1, buttonP2, buttonRCOff, buttonRCOn, buttonYawRC, buttonYawAut;\nButton buttonZeroRoll;\nint m=10, i, commListMax;\n\ncolor green_ = color(0, 120, 170), gray_ = color(60, 60, 60); ///30 120 30\nboolean writeEnable = false;\nboolean readEnable = false;\nboolean printlist = true;\nboolean portopen = false;\nchar RCcontrol = '0';\nchar YawRCon = '0';\nString readStatus = \"\";\nString Version = \"0.4.1.2\";\n\ncontrolP5.Controller hideLabel(controlP5.Controller c) {\n c.setLabel(\"\");\n c.setLabelVisible(false);\n return c;\n}\n\n\nvoid setup()\n{\n\n size(600, 280);\n background(75);\n\n textSize(28);\n fill(0, 120, 170);//blue\n text(\"EvvGC GUI\",20,50); text(Version, 170,50);\n\n\n // Define colors\n b1 = color(80);\n b2 = color(60);\n c1 = color(80, 80, 80);\n c2 = color(60, 61, 59);\n\n controlP5 = new ControlP5(this); // initialize the GUI controls\n\n //List all the available serial ports:\n println(Serial.list());\n\n\n\n commListMax = -1;\n for(int i=0;i>> ------------------\n;*/\n\n\n; Stack Configuration\n; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nStack_Size EQU 0x00000400\n\n AREA STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem SPACE Stack_Size\n__initial_sp\n\n\n; Heap Configuration\n; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nHeap_Size EQU 0x00000C00\n\n AREA HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem SPACE Heap_Size\n__heap_limit\n\n\n PRESERVE8\n THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n AREA RESET, DATA, READONLY\n EXPORT __Vectors\n EXPORT __Vectors_End\n EXPORT __Vectors_Size\n\n__Vectors DCD __initial_sp ; Top of Stack\n DCD Reset_Handler ; Reset Handler\n DCD NMI_Handler ; NMI Handler\n DCD HardFault_Handler ; Hard Fault Handler\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD SVC_Handler ; SVCall Handler\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD PendSV_Handler ; PendSV Handler\n DCD SysTick_Handler ; SysTick Handler\n\n ; External Interrupts\n DCD WDT_IRQHandler ; 0: Watchdog Timer\n DCD RTC_IRQHandler ; 1: Real Time Clock\n DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\n DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\n DCD MCIA_IRQHandler ; 4: MCIa\n DCD MCIB_IRQHandler ; 5: MCIb\n DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\n DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\n DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\n DCD UART4_IRQHandler ; 9: UART4 - not connected\n DCD AACI_IRQHandler ; 10: AACI / AC97\n DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\n DCD ENET_IRQHandler ; 12: Ethernet\n DCD USBDC_IRQHandler ; 13: USB Device\n DCD USBHC_IRQHandler ; 14: USB Host Controller\n DCD CHLCD_IRQHandler ; 15: Character LCD\n DCD FLEXRAY_IRQHandler ; 16: Flexray\n DCD CAN_IRQHandler ; 17: CAN\n DCD LIN_IRQHandler ; 18: LIN\n DCD I2C_IRQHandler ; 19: I2C ADC/DAC\n DCD 0 ; 20: Reserved\n DCD 0 ; 21: Reserved\n DCD 0 ; 22: Reserved\n DCD 0 ; 23: Reserved\n DCD 0 ; 24: Reserved\n DCD 0 ; 25: Reserved\n DCD 0 ; 26: Reserved\n DCD 0 ; 27: Reserved\n DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\n DCD 0 ; 29: Reserved - CPU FPGA\n DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\n DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\n__Vectors_End\n\n__Vectors_Size EQU __Vectors_End - __Vectors\n\n AREA |.text|, CODE, READONLY\n\n\n; Reset Handler\n\nReset_Handler PROC\n EXPORT Reset_Handler [WEAK]\n IMPORT SystemInit\n IMPORT __main\n LDR R0, =SystemInit\n BLX R0\n LDR R0, =__main\n BX R0\n ENDP\n\n\n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler PROC\n EXPORT NMI_Handler [WEAK]\n B .\n ENDP\nHardFault_Handler\\\n PROC\n EXPORT HardFault_Handler [WEAK]\n B .\n ENDP\nSVC_Handler PROC\n EXPORT SVC_Handler [WEAK]\n B .\n ENDP\nPendSV_Handler PROC\n EXPORT PendSV_Handler [WEAK]\n B .\n ENDP\nSysTick_Handler PROC\n EXPORT SysTick_Handler [WEAK]\n B .\n ENDP\n\nDefault_Handler PROC\n\n EXPORT WDT_IRQHandler [WEAK]\n EXPORT RTC_IRQHandler [WEAK]\n EXPORT TIM0_IRQHandler [WEAK]\n EXPORT TIM2_IRQHandler [WEAK]\n EXPORT MCIA_IRQHandler [WEAK]\n EXPORT MCIB_IRQHandler [WEAK]\n EXPORT UART0_IRQHandler [WEAK]\n EXPORT UART1_IRQHandler [WEAK]\n EXPORT UART2_IRQHandler [WEAK]\n EXPORT UART3_IRQHandler [WEAK]\n EXPORT UART4_IRQHandler [WEAK]\n EXPORT AACI_IRQHandler [WEAK]\n EXPORT CLCD_IRQHandler [WEAK]\n EXPORT ENET_IRQHandler [WEAK]\n EXPORT USBDC_IRQHandler [WEAK]\n EXPORT USBHC_IRQHandler [WEAK]\n EXPORT CHLCD_IRQHandler [WEAK]\n EXPORT FLEXRAY_IRQHandler [WEAK]\n EXPORT CAN_IRQHandler [WEAK]\n EXPORT LIN_IRQHandler [WEAK]\n EXPORT I2C_IRQHandler [WEAK]\n EXPORT CPU_CLCD_IRQHandler [WEAK]\n EXPORT SPI_IRQHandler [WEAK]\n\nWDT_IRQHandler\nRTC_IRQHandler\nTIM0_IRQHandler\nTIM2_IRQHandler\nMCIA_IRQHandler\nMCIB_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nUART2_IRQHandler\nUART3_IRQHandler\nUART4_IRQHandler\nAACI_IRQHandler\nCLCD_IRQHandler\nENET_IRQHandler\nUSBDC_IRQHandler\nUSBHC_IRQHandler\nCHLCD_IRQHandler\nFLEXRAY_IRQHandler\nCAN_IRQHandler\nLIN_IRQHandler\nI2C_IRQHandler\nCPU_CLCD_IRQHandler\nSPI_IRQHandler\n B .\n\n ENDP\n\n\n ALIGN\n\n\n; User Initial Stack & Heap\n\n IF :DEF:__MICROLIB\n\n EXPORT __initial_sp\n EXPORT __heap_base\n EXPORT __heap_limit\n\n ELSE\n\n IMPORT __use_two_region_memory\n EXPORT __user_initial_stackheap\n\n__user_initial_stackheap PROC\n LDR R0, = Heap_Mem\n LDR R1, =(Stack_Mem + Stack_Size)\n LDR R2, = (Heap_Mem + Heap_Size)\n LDR R3, = Stack_Mem\n BX LR\n ENDP\n\n ALIGN\n\n ENDIF\n\n\n END\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM3.s", "content": ";/**************************************************************************//**\n; * @file startup_ARMCM3.s\n; * @brief CMSIS Core Device Startup File for\n; * ARMCM3 Device Series\n; * @version V1.08\n; * @date 23. November 2012\n; *\n; * @note\n; *\n; ******************************************************************************/\n;/* Copyright (c) 2011 - 2012 ARM LIMITED\n;\n; All rights reserved.\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n; - Redistributions of source code must retain the above copyright\n; notice, this list of conditions and the following disclaimer.\n; - Redistributions in binary form must reproduce the above copyright\n; notice, this list of conditions and the following disclaimer in the\n; documentation and/or other materials provided with the distribution.\n; - Neither the name of ARM nor the names of its contributors may be used\n; to endorse or promote products derived from this software without\n; specific prior written permission.\n; *\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n; POSSIBILITY OF SUCH DAMAGE.\n; ---------------------------------------------------------------------------*/\n;/*\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n;*/\n\n\n; Stack Configuration\n; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nStack_Size EQU 0x00000400\n\n AREA STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem SPACE Stack_Size\n__initial_sp\n\n\n; Heap Configuration\n; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nHeap_Size EQU 0x00000C00\n\n AREA HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem SPACE Heap_Size\n__heap_limit\n\n\n PRESERVE8\n THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n AREA RESET, DATA, READONLY\n EXPORT __Vectors\n EXPORT __Vectors_End\n EXPORT __Vectors_Size\n\n__Vectors DCD __initial_sp ; Top of Stack\n DCD Reset_Handler ; Reset Handler\n DCD NMI_Handler ; NMI Handler\n DCD HardFault_Handler ; Hard Fault Handler\n DCD MemManage_Handler ; MPU Fault Handler\n DCD BusFault_Handler ; Bus Fault Handler\n DCD UsageFault_Handler ; Usage Fault Handler\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD SVC_Handler ; SVCall Handler\n DCD DebugMon_Handler ; Debug Monitor Handler\n DCD 0 ; Reserved\n DCD PendSV_Handler ; PendSV Handler\n DCD SysTick_Handler ; SysTick Handler\n\n ; External Interrupts\n DCD WDT_IRQHandler ; 0: Watchdog Timer\n DCD RTC_IRQHandler ; 1: Real Time Clock\n DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\n DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\n DCD MCIA_IRQHandler ; 4: MCIa\n DCD MCIB_IRQHandler ; 5: MCIb\n DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\n DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\n DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\n DCD UART4_IRQHandler ; 9: UART4 - not connected\n DCD AACI_IRQHandler ; 10: AACI / AC97\n DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\n DCD ENET_IRQHandler ; 12: Ethernet\n DCD USBDC_IRQHandler ; 13: USB Device\n DCD USBHC_IRQHandler ; 14: USB Host Controller\n DCD CHLCD_IRQHandler ; 15: Character LCD\n DCD FLEXRAY_IRQHandler ; 16: Flexray\n DCD CAN_IRQHandler ; 17: CAN\n DCD LIN_IRQHandler ; 18: LIN\n DCD I2C_IRQHandler ; 19: I2C ADC/DAC\n DCD 0 ; 20: Reserved\n DCD 0 ; 21: Reserved\n DCD 0 ; 22: Reserved\n DCD 0 ; 23: Reserved\n DCD 0 ; 24: Reserved\n DCD 0 ; 25: Reserved\n DCD 0 ; 26: Reserved\n DCD 0 ; 27: Reserved\n DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\n DCD 0 ; 29: Reserved - CPU FPGA\n DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\n DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\n__Vectors_End\n\n__Vectors_Size EQU __Vectors_End - __Vectors\n\n AREA |.text|, CODE, READONLY\n\n\n; Reset Handler\n\nReset_Handler PROC\n EXPORT Reset_Handler [WEAK]\n IMPORT SystemInit\n IMPORT __main\n LDR R0, =SystemInit\n BLX R0\n LDR R0, =__main\n BX R0\n ENDP\n\n\n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler PROC\n EXPORT NMI_Handler [WEAK]\n B .\n ENDP\nHardFault_Handler\\\n PROC\n EXPORT HardFault_Handler [WEAK]\n B .\n ENDP\nMemManage_Handler\\\n PROC\n EXPORT MemManage_Handler [WEAK]\n B .\n ENDP\nBusFault_Handler\\\n PROC\n EXPORT BusFault_Handler [WEAK]\n B .\n ENDP\nUsageFault_Handler\\\n PROC\n EXPORT UsageFault_Handler [WEAK]\n B .\n ENDP\nSVC_Handler PROC\n EXPORT SVC_Handler [WEAK]\n B .\n ENDP\nDebugMon_Handler\\\n PROC\n EXPORT DebugMon_Handler [WEAK]\n B .\n ENDP\nPendSV_Handler PROC\n EXPORT PendSV_Handler [WEAK]\n B .\n ENDP\nSysTick_Handler PROC\n EXPORT SysTick_Handler [WEAK]\n B .\n ENDP\n\nDefault_Handler PROC\n\n EXPORT WDT_IRQHandler [WEAK]\n EXPORT RTC_IRQHandler [WEAK]\n EXPORT TIM0_IRQHandler [WEAK]\n EXPORT TIM2_IRQHandler [WEAK]\n EXPORT MCIA_IRQHandler [WEAK]\n EXPORT MCIB_IRQHandler [WEAK]\n EXPORT UART0_IRQHandler [WEAK]\n EXPORT UART1_IRQHandler [WEAK]\n EXPORT UART2_IRQHandler [WEAK]\n EXPORT UART3_IRQHandler [WEAK]\n EXPORT UART4_IRQHandler [WEAK]\n EXPORT AACI_IRQHandler [WEAK]\n EXPORT CLCD_IRQHandler [WEAK]\n EXPORT ENET_IRQHandler [WEAK]\n EXPORT USBDC_IRQHandler [WEAK]\n EXPORT USBHC_IRQHandler [WEAK]\n EXPORT CHLCD_IRQHandler [WEAK]\n EXPORT FLEXRAY_IRQHandler [WEAK]\n EXPORT CAN_IRQHandler [WEAK]\n EXPORT LIN_IRQHandler [WEAK]\n EXPORT I2C_IRQHandler [WEAK]\n EXPORT CPU_CLCD_IRQHandler [WEAK]\n EXPORT SPI_IRQHandler [WEAK]\n\nWDT_IRQHandler\nRTC_IRQHandler\nTIM0_IRQHandler\nTIM2_IRQHandler\nMCIA_IRQHandler\nMCIB_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nUART2_IRQHandler\nUART3_IRQHandler\nUART4_IRQHandler\nAACI_IRQHandler\nCLCD_IRQHandler\nENET_IRQHandler\nUSBDC_IRQHandler\nUSBHC_IRQHandler\nCHLCD_IRQHandler\nFLEXRAY_IRQHandler\nCAN_IRQHandler\nLIN_IRQHandler\nI2C_IRQHandler\nCPU_CLCD_IRQHandler\nSPI_IRQHandler\n B .\n\n ENDP\n\n\n ALIGN\n\n\n; User Initial Stack & Heap\n\n IF :DEF:__MICROLIB\n\n EXPORT __initial_sp\n EXPORT __heap_base\n EXPORT __heap_limit\n\n ELSE\n\n IMPORT __use_two_region_memory\n EXPORT __user_initial_stackheap\n\n__user_initial_stackheap PROC\n LDR R0, = Heap_Mem\n LDR R1, =(Stack_Mem + Stack_Size)\n LDR R2, = (Heap_Mem + Heap_Size)\n LDR R3, = Stack_Mem\n BX LR\n ENDP\n\n ALIGN\n\n ENDIF\n\n\n END\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/ARM/startup_ARMCM4.s", "content": ";/**************************************************************************//**\n; * @file startup_ARMCM4.s\n; * @brief CMSIS Core Device Startup File for\n; * ARMCM4 Device Series\n; * @version V1.08\n; * @date 23. November 2012\n; *\n; * @note\n; *\n; ******************************************************************************/\n;/* Copyright (c) 2011 - 2012 ARM LIMITED\n;\n; All rights reserved.\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions are met:\n; - Redistributions of source code must retain the above copyright\n; notice, this list of conditions and the following disclaimer.\n; - Redistributions in binary form must reproduce the above copyright\n; notice, this list of conditions and the following disclaimer in the\n; documentation and/or other materials provided with the distribution.\n; - Neither the name of ARM nor the names of its contributors may be used\n; to endorse or promote products derived from this software without\n; specific prior written permission.\n; *\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n; POSSIBILITY OF SUCH DAMAGE.\n; ---------------------------------------------------------------------------*/\n;/*\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n;*/\n\n\n; Stack Configuration\n; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nStack_Size EQU 0x00000400\n\n AREA STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem SPACE Stack_Size\n__initial_sp\n\n\n; Heap Configuration\n; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nHeap_Size EQU 0x00000C00\n\n AREA HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem SPACE Heap_Size\n__heap_limit\n\n\n PRESERVE8\n THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n AREA RESET, DATA, READONLY\n EXPORT __Vectors\n EXPORT __Vectors_End\n EXPORT __Vectors_Size\n\n__Vectors DCD __initial_sp ; Top of Stack\n DCD Reset_Handler ; Reset Handler\n DCD NMI_Handler ; NMI Handler\n DCD HardFault_Handler ; Hard Fault Handler\n DCD MemManage_Handler ; MPU Fault Handler\n DCD BusFault_Handler ; Bus Fault Handler\n DCD UsageFault_Handler ; Usage Fault Handler\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD SVC_Handler ; SVCall Handler\n DCD DebugMon_Handler ; Debug Monitor Handler\n DCD 0 ; Reserved\n DCD PendSV_Handler ; PendSV Handler\n DCD SysTick_Handler ; SysTick Handler\n\n ; External Interrupts\n DCD WDT_IRQHandler ; 0: Watchdog Timer\n DCD RTC_IRQHandler ; 1: Real Time Clock\n DCD TIM0_IRQHandler ; 2: Timer0 / Timer1\n DCD TIM2_IRQHandler ; 3: Timer2 / Timer3\n DCD MCIA_IRQHandler ; 4: MCIa\n DCD MCIB_IRQHandler ; 5: MCIb\n DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA\n DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA\n DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA\n DCD UART4_IRQHandler ; 9: UART4 - not connected\n DCD AACI_IRQHandler ; 10: AACI / AC97\n DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt\n DCD ENET_IRQHandler ; 12: Ethernet\n DCD USBDC_IRQHandler ; 13: USB Device\n DCD USBHC_IRQHandler ; 14: USB Host Controller\n DCD CHLCD_IRQHandler ; 15: Character LCD\n DCD FLEXRAY_IRQHandler ; 16: Flexray\n DCD CAN_IRQHandler ; 17: CAN\n DCD LIN_IRQHandler ; 18: LIN\n DCD I2C_IRQHandler ; 19: I2C ADC/DAC\n DCD 0 ; 20: Reserved\n DCD 0 ; 21: Reserved\n DCD 0 ; 22: Reserved\n DCD 0 ; 23: Reserved\n DCD 0 ; 24: Reserved\n DCD 0 ; 25: Reserved\n DCD 0 ; 26: Reserved\n DCD 0 ; 27: Reserved\n DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD\n DCD 0 ; 29: Reserved - CPU FPGA\n DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA\n DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA\n__Vectors_End\n\n__Vectors_Size EQU __Vectors_End - __Vectors\n\n AREA |.text|, CODE, READONLY\n\n\n; Reset Handler\n\nReset_Handler PROC\n EXPORT Reset_Handler [WEAK]\n IMPORT SystemInit\n IMPORT __main\n LDR R0, =SystemInit\n BLX R0\n LDR R0, =__main\n BX R0\n ENDP\n\n\n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler PROC\n EXPORT NMI_Handler [WEAK]\n B .\n ENDP\nHardFault_Handler\\\n PROC\n EXPORT HardFault_Handler [WEAK]\n B .\n ENDP\nMemManage_Handler\\\n PROC\n EXPORT MemManage_Handler [WEAK]\n B .\n ENDP\nBusFault_Handler\\\n PROC\n EXPORT BusFault_Handler [WEAK]\n B .\n ENDP\nUsageFault_Handler\\\n PROC\n EXPORT UsageFault_Handler [WEAK]\n B .\n ENDP\nSVC_Handler PROC\n EXPORT SVC_Handler [WEAK]\n B .\n ENDP\nDebugMon_Handler\\\n PROC\n EXPORT DebugMon_Handler [WEAK]\n B .\n ENDP\nPendSV_Handler PROC\n EXPORT PendSV_Handler [WEAK]\n B .\n ENDP\nSysTick_Handler PROC\n EXPORT SysTick_Handler [WEAK]\n B .\n ENDP\n\nDefault_Handler PROC\n\n EXPORT WDT_IRQHandler [WEAK]\n EXPORT RTC_IRQHandler [WEAK]\n EXPORT TIM0_IRQHandler [WEAK]\n EXPORT TIM2_IRQHandler [WEAK]\n EXPORT MCIA_IRQHandler [WEAK]\n EXPORT MCIB_IRQHandler [WEAK]\n EXPORT UART0_IRQHandler [WEAK]\n EXPORT UART1_IRQHandler [WEAK]\n EXPORT UART2_IRQHandler [WEAK]\n EXPORT UART3_IRQHandler [WEAK]\n EXPORT UART4_IRQHandler [WEAK]\n EXPORT AACI_IRQHandler [WEAK]\n EXPORT CLCD_IRQHandler [WEAK]\n EXPORT ENET_IRQHandler [WEAK]\n EXPORT USBDC_IRQHandler [WEAK]\n EXPORT USBHC_IRQHandler [WEAK]\n EXPORT CHLCD_IRQHandler [WEAK]\n EXPORT FLEXRAY_IRQHandler [WEAK]\n EXPORT CAN_IRQHandler [WEAK]\n EXPORT LIN_IRQHandler [WEAK]\n EXPORT I2C_IRQHandler [WEAK]\n EXPORT CPU_CLCD_IRQHandler [WEAK]\n EXPORT SPI_IRQHandler [WEAK]\n\nWDT_IRQHandler\nRTC_IRQHandler\nTIM0_IRQHandler\nTIM2_IRQHandler\nMCIA_IRQHandler\nMCIB_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nUART2_IRQHandler\nUART3_IRQHandler\nUART4_IRQHandler\nAACI_IRQHandler\nCLCD_IRQHandler\nENET_IRQHandler\nUSBDC_IRQHandler\nUSBHC_IRQHandler\nCHLCD_IRQHandler\nFLEXRAY_IRQHandler\nCAN_IRQHandler\nLIN_IRQHandler\nI2C_IRQHandler\nCPU_CLCD_IRQHandler\nSPI_IRQHandler\n B .\n\n ENDP\n\n\n ALIGN\n\n\n; User Initial Stack & Heap\n\n IF :DEF:__MICROLIB\n\n EXPORT __initial_sp\n EXPORT __heap_base\n EXPORT __heap_limit\n\n ELSE\n\n IMPORT __use_two_region_memory\n EXPORT __user_initial_stackheap\n\n__user_initial_stackheap PROC\n LDR R0, = Heap_Mem\n LDR R1, =(Stack_Mem + Stack_Size)\n LDR R2, = (Heap_Mem + Heap_Size)\n LDR R3, = Stack_Mem\n BX LR\n ENDP\n\n ALIGN\n\n ENDIF\n\n\n END\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/G++/ARMCMx.ld", "content": "/* Linker script to configure memory regions\n *\n * Version:CodeSourcery Sourcery G++ Lite 2007q3-53\n * BugURL:https://support.codesourcery.com/GNUToolchain/\n *\n * Copyright 2007 CodeSourcery.\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply. */\n\nOUTPUT_FORMAT (\"elf32-littlearm\", \"elf32-bigarm\", \"elf32-littlearm\")\nENTRY(_start)\nSEARCH_DIR(.)\nGROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)\n\nMEMORY\n{\n rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */\n ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */\n}\n\n/* These force the linker to search for particular symbols from\n * the start of the link process and thus ensure the user's\n * overrides are picked up\n */\nEXTERN(__cs3_reset_cortex_m)\nEXTERN(__cs3_interrupt_vector_cortex_m)\nEXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)\n\nPROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);\nPROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);\nPROVIDE(__cs3_heap_start = _end);\nPROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);\n\nSECTIONS\n{\n .text :\n {\n CREATE_OBJECT_SYMBOLS\n __cs3_region_start_rom = .;\n *(.cs3.region-head.rom)\n __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;\n *(.cs3.interrupt_vector)\n /* Make sure we pulled in an interrupt vector. */\n ASSERT (. != __cs3_interrupt_vector_cortex_m, \"No interrupt vector\");\n *(.rom)\n *(.rom.b)\n\n __cs3_reset = __cs3_reset_cortex_m;\n *(.cs3.reset)\n /* Make sure we pulled in some reset code. */\n ASSERT (. != __cs3_reset, \"No reset code\");\n\n *(.text .text.* .gnu.linkonce.t.*)\n *(.plt)\n *(.gnu.warning)\n *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\n\n *(.rodata .rodata.* .gnu.linkonce.r.*)\n\n *(.ARM.extab* .gnu.linkonce.armextab.*)\n *(.gcc_except_table)\n *(.eh_frame_hdr)\n *(.eh_frame)\n\n . = ALIGN(4);\n KEEP(*(.init))\n\n . = ALIGN(4);\n __preinit_array_start = .;\n KEEP (*(.preinit_array))\n __preinit_array_end = .;\n\n . = ALIGN(4);\n __init_array_start = .;\n KEEP (*(SORT(.init_array.*)))\n KEEP (*(.init_array))\n __init_array_end = .;\n\n . = ALIGN(0x4);\n KEEP (*crtbegin.o(.ctors))\n KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\n KEEP (*(SORT(.ctors.*)))\n KEEP (*crtend.o(.ctors))\n\n . = ALIGN(4);\n KEEP(*(.fini))\n\n . = ALIGN(4);\n __fini_array_start = .;\n KEEP (*(.fini_array))\n KEEP (*(SORT(.fini_array.*)))\n __fini_array_end = .;\n\n KEEP (*crtbegin.o(.dtors))\n KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\n KEEP (*(SORT(.dtors.*)))\n KEEP (*crtend.o(.dtors))\n\n . = ALIGN(4);\n __cs3_regions = .;\n LONG (0)\n LONG (__cs3_region_init_ram)\n LONG (__cs3_region_start_ram)\n LONG (__cs3_region_init_size_ram)\n LONG (__cs3_region_zero_size_ram)\n }\n\n /* .ARM.exidx is sorted, so has to go in its own output section. */\n __exidx_start = .;\n .ARM.exidx :\n {\n *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n } >rom\n __exidx_end = .;\n .text.align :\n {\n . = ALIGN(8);\n _etext = .;\n } >rom\n __cs3_region_size_rom = LENGTH(rom);\n __cs3_region_num = 1;\n\n .data :\n {\n __cs3_region_start_ram = .;\n *(.cs3.region-head.ram)\n KEEP(*(.jcr))\n *(.got.plt) *(.got)\n *(.shdata)\n *(.data .data.* .gnu.linkonce.d.*)\n *(.ram)\n . = ALIGN (8);\n _edata = .;\n } >ram AT>rom\n .bss :\n {\n *(.shbss)\n *(.bss .bss.* .gnu.linkonce.b.*)\n *(COMMON)\n *(.ram.b)\n . = ALIGN (8);\n _end = .;\n __end = .;\n } >ram AT>rom\n .heap :\n {\n *(.heap)\n } >ram\n .stack (__cs3_stack - __cs3_stack_size) :\n {\n *(.stack)\n } >ram\n __cs3_region_init_ram = LOADADDR (.data);\n __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;\n __cs3_region_zero_size_ram = _end - _edata;\n __cs3_region_size_ram = LENGTH(ram);\n __cs3_region_num = 1;\n\n .stab 0 (NOLOAD) : { *(.stab) }\n .stabstr 0 (NOLOAD) : { *(.stabstr) }\n /* DWARF debug sections.\n * Symbols in the DWARF debugging sections are relative to the beginning\n * of the section so we begin them at 0. */\n /* DWARF 1 */\n .debug 0 : { *(.debug) }\n .line 0 : { *(.line) }\n /* GNU DWARF 1 extensions */\n .debug_srcinfo 0 : { *(.debug_srcinfo) }\n .debug_sfnames 0 : { *(.debug_sfnames) }\n /* DWARF 1.1 and DWARF 2 */\n .debug_aranges 0 : { *(.debug_aranges) }\n .debug_pubnames 0 : { *(.debug_pubnames) }\n /* DWARF 2 */\n .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\n .debug_abbrev 0 : { *(.debug_abbrev) }\n .debug_line 0 : { *(.debug_line) }\n .debug_frame 0 : { *(.debug_frame) }\n .debug_str 0 : { *(.debug_str) }\n .debug_loc 0 : { *(.debug_loc) }\n .debug_macinfo 0 : { *(.debug_macinfo) }\n /* SGI/MIPS DWARF 2 extensions */\n .debug_weaknames 0 : { *(.debug_weaknames) }\n .debug_funcnames 0 : { *(.debug_funcnames) }\n .debug_typenames 0 : { *(.debug_typenames) }\n .debug_varnames 0 : { *(.debug_varnames) }\n\n .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\n .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\n /DISCARD/ : { *(.note.GNU-stack) }\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM0.s", "content": "/**************************************************************************//**\n * @file startup_ARMCM0.s\n * @brief CMSIS Core Device Startup File for\n * ARMCM0 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note Version CodeSourcery Sourcery G++ Lite (with CS3)\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n\n/*\n// Stack Configuration\n// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Stack_Size, 0x00000400\n .section \".stack\", \"w\"\n .align 3\n .globl __cs3_stack_mem\n .globl __cs3_stack_size\n__cs3_stack_mem:\n .if Stack_Size\n .space Stack_Size\n .endif\n .size __cs3_stack_mem, . - __cs3_stack_mem\n .set __cs3_stack_size, . - __cs3_stack_mem\n\n\n/*\n// Heap Configuration\n// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Heap_Size, 0x00000C00\n .section \".heap\", \"w\"\n .align 3\n .globl __cs3_heap_start\n .globl __cs3_heap_end\n__cs3_heap_start:\n .if Heap_Size\n .space Heap_Size\n .endif\n__cs3_heap_end:\n\n\n/* Vector Table */\n\n .section \".cs3.interrupt_vector\"\n .globl __cs3_interrupt_vector_cortex_m\n .type __cs3_interrupt_vector_cortex_m, %object\n\n__cs3_interrupt_vector_cortex_m:\n .long __cs3_stack /* Top of Stack */\n .long __cs3_reset /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External Interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m\n\n\n .thumb\n\n\n/* Reset Handler */\n\n .section .cs3.reset,\"x\",%progbits\n .thumb_func\n .globl __cs3_reset_cortex_m\n .type __cs3_reset_cortex_m, %function\n__cs3_reset_cortex_m:\n .fnstart\n LDR R0, =SystemInit\n BLX R0\n LDR R0,=_start\n BX R0\n .pool\n .cantunwind\n .fnend\n .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m\n\n .section \".text\"\n\n/* Exception Handlers */\n\n .weak NMI_Handler\n .type NMI_Handler, %function\nNMI_Handler:\n B .\n .size NMI_Handler, . - NMI_Handler\n\n .weak HardFault_Handler\n .type HardFault_Handler, %function\nHardFault_Handler:\n B .\n .size HardFault_Handler, . - HardFault_Handler\n\n .weak SVC_Handler\n .type SVC_Handler, %function\nSVC_Handler:\n B .\n .size SVC_Handler, . - SVC_Handler\n\n .weak PendSV_Handler\n .type PendSV_Handler, %function\nPendSV_Handler:\n B .\n .size PendSV_Handler, . - PendSV_Handler\n\n .weak SysTick_Handler\n .type SysTick_Handler, %function\nSysTick_Handler:\n B .\n .size SysTick_Handler, . - SysTick_Handler\n\n\n/* IRQ Handlers */\n\n .globl Default_Handler\n .type Default_Handler, %function\nDefault_Handler:\n B .\n .size Default_Handler, . - Default_Handler\n\n .macro def_irq_handler handler\n .weak \\handler\n .set \\handler, Default_Handler\n .endm\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM3.s", "content": "/**************************************************************************//**\n * @file startup_ARMCM3.s\n * @brief CMSIS Core Device Startup File for\n * ARMCM3 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note Version CodeSourcery Sourcery G++ Lite (with CS3)\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n\n/*\n// Stack Configuration\n// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Stack_Size, 0x00000400\n .section \".stack\", \"w\"\n .align 3\n .globl __cs3_stack_mem\n .globl __cs3_stack_size\n__cs3_stack_mem:\n .if Stack_Size\n .space Stack_Size\n .endif\n .size __cs3_stack_mem, . - __cs3_stack_mem\n .set __cs3_stack_size, . - __cs3_stack_mem\n\n\n/*\n// Heap Configuration\n// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Heap_Size, 0x00000C00\n .section \".heap\", \"w\"\n .align 3\n .globl __cs3_heap_start\n .globl __cs3_heap_end\n__cs3_heap_start:\n .if Heap_Size\n .space Heap_Size\n .endif\n__cs3_heap_end:\n\n\n/* Vector Table */\n\n .section \".cs3.interrupt_vector\"\n .globl __cs3_interrupt_vector_cortex_m\n .type __cs3_interrupt_vector_cortex_m, %object\n\n__cs3_interrupt_vector_cortex_m:\n .long __cs3_stack /* Top of Stack */\n .long __cs3_reset /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long MemManage_Handler /* MPU Fault Handler */\n .long BusFault_Handler /* Bus Fault Handler */\n .long UsageFault_Handler /* Usage Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long DebugMon_Handler /* Debug Monitor Handler */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External Interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m\n\n\n .thumb\n\n\n/* Reset Handler */\n\n .section .cs3.reset,\"x\",%progbits\n .thumb_func\n .globl __cs3_reset_cortex_m\n .type __cs3_reset_cortex_m, %function\n__cs3_reset_cortex_m:\n .fnstart\n LDR R0, =SystemInit\n BLX R0\n LDR R0,=_start\n BX R0\n .pool\n .cantunwind\n .fnend\n .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m\n\n .section \".text\"\n\n/* Exception Handlers */\n\n .weak NMI_Handler\n .type NMI_Handler, %function\nNMI_Handler:\n B .\n .size NMI_Handler, . - NMI_Handler\n\n .weak HardFault_Handler\n .type HardFault_Handler, %function\nHardFault_Handler:\n B .\n .size HardFault_Handler, . - HardFault_Handler\n\n .weak MemManage_Handler\n .type MemManage_Handler, %function\nMemManage_Handler:\n B .\n .size MemManage_Handler, . - MemManage_Handler\n\n .weak BusFault_Handler\n .type BusFault_Handler, %function\nBusFault_Handler:\n B .\n .size BusFault_Handler, . - BusFault_Handler\n\n .weak UsageFault_Handler\n .type UsageFault_Handler, %function\nUsageFault_Handler:\n B .\n .size UsageFault_Handler, . - UsageFault_Handler\n\n .weak SVC_Handler\n .type SVC_Handler, %function\nSVC_Handler:\n B .\n .size SVC_Handler, . - SVC_Handler\n\n .weak DebugMon_Handler\n .type DebugMon_Handler, %function\nDebugMon_Handler:\n B .\n .size DebugMon_Handler, . - DebugMon_Handler\n\n .weak PendSV_Handler\n .type PendSV_Handler, %function\nPendSV_Handler:\n B .\n .size PendSV_Handler, . - PendSV_Handler\n\n .weak SysTick_Handler\n .type SysTick_Handler, %function\nSysTick_Handler:\n B .\n .size SysTick_Handler, . - SysTick_Handler\n\n\n/* IRQ Handlers */\n\n .globl Default_Handler\n .type Default_Handler, %function\nDefault_Handler:\n B .\n .size Default_Handler, . - Default_Handler\n\n .macro def_irq_handler handler\n .weak \\handler\n .set \\handler, Default_Handler\n .endm\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/G++/startup_ARMCM4.s", "content": "/**************************************************************************//**\n * @file startup_ARMCM4.s\n * @brief CMSIS Core Device Startup File for\n * ARMCM4 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note Version CodeSourcery Sourcery G++ Lite (with CS3)\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n\n/*\n// Stack Configuration\n// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Stack_Size, 0x00000400\n .section \".stack\", \"w\"\n .align 3\n .globl __cs3_stack_mem\n .globl __cs3_stack_size\n__cs3_stack_mem:\n .if Stack_Size\n .space Stack_Size\n .endif\n .size __cs3_stack_mem, . - __cs3_stack_mem\n .set __cs3_stack_size, . - __cs3_stack_mem\n\n\n/*\n// Heap Configuration\n// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// \n*/\n\n .equ Heap_Size, 0x00000C00\n .section \".heap\", \"w\"\n .align 3\n .globl __cs3_heap_start\n .globl __cs3_heap_end\n__cs3_heap_start:\n .if Heap_Size\n .space Heap_Size\n .endif\n__cs3_heap_end:\n\n\n/* Vector Table */\n\n .section \".cs3.interrupt_vector\"\n .globl __cs3_interrupt_vector_cortex_m\n .type __cs3_interrupt_vector_cortex_m, %object\n\n__cs3_interrupt_vector_cortex_m:\n .long __cs3_stack /* Top of Stack */\n .long __cs3_reset /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long MemManage_Handler /* MPU Fault Handler */\n .long BusFault_Handler /* Bus Fault Handler */\n .long UsageFault_Handler /* Usage Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long DebugMon_Handler /* Debug Monitor Handler */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External Interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m\n\n\n .thumb\n\n\n/* Reset Handler */\n\n .section .cs3.reset,\"x\",%progbits\n .thumb_func\n .globl __cs3_reset_cortex_m\n .type __cs3_reset_cortex_m, %function\n__cs3_reset_cortex_m:\n .fnstart\n LDR R0, =SystemInit\n BLX R0\n LDR R0,=_start\n BX R0\n .pool\n .cantunwind\n .fnend\n .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m\n\n .section \".text\"\n\n/* Exception Handlers */\n\n .weak NMI_Handler\n .type NMI_Handler, %function\nNMI_Handler:\n B .\n .size NMI_Handler, . - NMI_Handler\n\n .weak HardFault_Handler\n .type HardFault_Handler, %function\nHardFault_Handler:\n B .\n .size HardFault_Handler, . - HardFault_Handler\n\n .weak MemManage_Handler\n .type MemManage_Handler, %function\nMemManage_Handler:\n B .\n .size MemManage_Handler, . - MemManage_Handler\n\n .weak BusFault_Handler\n .type BusFault_Handler, %function\nBusFault_Handler:\n B .\n .size BusFault_Handler, . - BusFault_Handler\n\n .weak UsageFault_Handler\n .type UsageFault_Handler, %function\nUsageFault_Handler:\n B .\n .size UsageFault_Handler, . - UsageFault_Handler\n\n .weak SVC_Handler\n .type SVC_Handler, %function\nSVC_Handler:\n B .\n .size SVC_Handler, . - SVC_Handler\n\n .weak DebugMon_Handler\n .type DebugMon_Handler, %function\nDebugMon_Handler:\n B .\n .size DebugMon_Handler, . - DebugMon_Handler\n\n .weak PendSV_Handler\n .type PendSV_Handler, %function\nPendSV_Handler:\n B .\n .size PendSV_Handler, . - PendSV_Handler\n\n .weak SysTick_Handler\n .type SysTick_Handler, %function\nSysTick_Handler:\n B .\n .size SysTick_Handler, . - SysTick_Handler\n\n\n/* IRQ Handlers */\n\n .globl Default_Handler\n .type Default_Handler, %function\nDefault_Handler:\n B .\n .size Default_Handler, . - Default_Handler\n\n .macro def_irq_handler handler\n .weak \\handler\n .set \\handler, Default_Handler\n .endm\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/GCC/ARMCMx.ld", "content": "/* Linker script to configure memory regions. */\nMEMORY\n{\n FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */\n RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x08000 /* 32k */\n}\n\n/* Library configurations */\nGROUP(libgcc.a libc.a libm.a libnosys.a)\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n * Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n * __exidx_start\n * __exidx_end\n * __etext\n * __data_start__\n * __preinit_array_start\n * __preinit_array_end\n * __init_array_start\n * __init_array_end\n * __fini_array_start\n * __fini_array_end\n * __data_end__\n * __bss_start__\n * __bss_end__\n * __end__\n * end\n * __HeapLimit\n * __StackLimit\n * __StackTop\n * __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n\t.text :\n\t{\n\t\tKEEP(*(.isr_vector))\n\t\t*(.text*)\n\n\t\tKEEP(*(.init))\n\t\tKEEP(*(.fini))\n\n\t\t/* .ctors */\n\t\t*crtbegin.o(.ctors)\n\t\t*crtbegin?.o(.ctors)\n\t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n\t\t*(SORT(.ctors.*))\n\t\t*(.ctors)\n\n\t\t/* .dtors */\n \t\t*crtbegin.o(.dtors)\n \t\t*crtbegin?.o(.dtors)\n \t\t*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n \t\t*(SORT(.dtors.*))\n \t\t*(.dtors)\n\n\t\t*(.rodata*)\n\n\t\tKEEP(*(.eh_frame*))\n\t} > FLASH\n\n\t.ARM.extab :\n\t{\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t__exidx_start = .;\n\t.ARM.exidx :\n\t{\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t} > FLASH\n\t__exidx_end = .;\n\n\t__etext = .;\n\n\t.data : AT (__etext)\n\t{\n\t\t__data_start__ = .;\n\t\t*(vtable)\n\t\t*(.data*)\n\n\t\t. = ALIGN(4);\n\t\t/* preinit data */\n\t\tPROVIDE_HIDDEN (__preinit_array_start = .);\n\t\tKEEP(*(.preinit_array))\n\t\tPROVIDE_HIDDEN (__preinit_array_end = .);\n\n\t\t. = ALIGN(4);\n\t\t/* init data */\n\t\tPROVIDE_HIDDEN (__init_array_start = .);\n\t\tKEEP(*(SORT(.init_array.*)))\n\t\tKEEP(*(.init_array))\n\t\tPROVIDE_HIDDEN (__init_array_end = .);\n\n\n\t\t. = ALIGN(4);\n\t\t/* finit data */\n\t\tPROVIDE_HIDDEN (__fini_array_start = .);\n\t\tKEEP(*(SORT(.fini_array.*)))\n\t\tKEEP(*(.fini_array))\n\t\tPROVIDE_HIDDEN (__fini_array_end = .);\n\n\t\tKEEP(*(.jcr*))\n\t\t. = ALIGN(4);\n\t\t/* All data end */\n\t\t__data_end__ = .;\n\n\t} > RAM\n\n\t.bss :\n\t{\n\t\t. = ALIGN(4);\n\t\t__bss_start__ = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(4);\n\t\t__bss_end__ = .;\n\t} > RAM\n\n\t.heap (COPY):\n\t{\n\t\t__end__ = .;\n\t\tend = __end__;\n\t\t*(.heap*)\n\t\t__HeapLimit = .;\n\t} > RAM\n\n\t/* .stack_dummy section doesn't contains any symbols. It is only\n\t * used for linker to calculate size of stack sections, and assign\n\t * values to stack symbols later */\n\t.stack_dummy (COPY):\n\t{\n\t\t*(.stack*)\n\t} > RAM\n\n\t/* Set stack top to end of RAM, and stack limit move down by\n\t * size of stack_dummy section */\n\t__StackTop = ORIGIN(RAM) + LENGTH(RAM);\n\t__StackLimit = __StackTop - SIZEOF(.stack_dummy);\n\tPROVIDE(__stack = __StackTop);\n\n\t/* Check if data + heap + stack exceeds RAM limit */\n\tASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM0.S", "content": "/* File: startup_ARMCM0.S\n * Purpose: startup file for Cortex-M0 devices. Should use with\n * GCC for ARM Embedded Processors\n * Version: V1.4\n * Date: 20 Dezember 2012\n *\n */\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n .syntax unified\n .arch armv6-m\n\n .section .stack\n .align 3\n#ifdef __STACK_SIZE\n .equ Stack_Size, __STACK_SIZE\n#else\n .equ Stack_Size, 0x00000400\n#endif\n .globl __StackTop\n .globl __StackLimit\n__StackLimit:\n .space Stack_Size\n .size __StackLimit, . - __StackLimit\n__StackTop:\n .size __StackTop, . - __StackTop\n\n .section .heap\n .align 3\n#ifdef __HEAP_SIZE\n .equ Heap_Size, __HEAP_SIZE\n#else\n .equ Heap_Size, 0x00000C00\n#endif\n .globl __HeapBase\n .globl __HeapLimit\n__HeapBase:\n .if Heap_Size\n .space Heap_Size\n .endif\n .size __HeapBase, . - __HeapBase\n__HeapLimit:\n .size __HeapLimit, . - __HeapLimit\n\n .section .isr_vector\n .align 2\n .globl __isr_vector\n__isr_vector:\n .long __StackTop /* Top of Stack */\n .long Reset_Handler /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __isr_vector, . - __isr_vector\n\n .text\n .thumb\n .thumb_func\n .align 1\n .globl Reset_Handler\n .type Reset_Handler, %function\nReset_Handler:\n/* Loop to copy data from read only memory to RAM. The ranges\n * of copy from/to are specified by following symbols evaluated in\n * linker script.\n * __etext: End of code section, i.e., begin of data sections to copy from.\n * __data_start__/__data_end__: RAM address range that data should be\n * copied to. Both must be aligned to 4 bytes boundary. */\n\n ldr r1, =__etext\n ldr r2, =__data_start__\n ldr r3, =__data_end__\n\n subs r3, r2\n ble .LC0\n\n.LC1:\n subs r3, 4\n ldr r0, [r1,r3]\n str r0, [r2,r3]\n bgt .LC1\n.LC0:\n\n#ifdef __STARTUP_CLEAR_BSS\n/* This part of work usually is done in C library startup code. Otherwise,\n * define this macro to enable it in this startup.\n *\n * Loop to zero out BSS section, which uses following symbols\n * in linker script:\n * __bss_start__: start of BSS section. Must align to 4\n * __bss_end__: end of BSS section. Must align to 4\n */\n ldr r1, =__bss_start__\n ldr r2, =__bss_end__\n\n subs r2, r1\n ble .LC3\n\n movs r0, 0\n.LC2:\n str r0, [r1, r2]\n subs r2, 4\n bge .LC2\n.LC3:\n#endif\n\n#ifndef __NO_SYSTEM_INIT\n bl\tSystemInit\n#endif\n\n#ifndef __START\n#define __START _start\n#endif\n bl\t__START\n\n .pool\n .size Reset_Handler, . - Reset_Handler\n\n/* Macro to define default handlers. Default handler\n * will be weak symbol and just dead loops. They can be\n * overwritten by other handlers */\n .macro def_irq_handler handler_name\n .align 1\n .thumb_func\n .weak \\handler_name\n .type \\handler_name, %function\n\\handler_name :\n b .\n .size \\handler_name, . - \\handler_name\n .endm\n\n def_irq_handler NMI_Handler\n def_irq_handler HardFault_Handler\n def_irq_handler SVC_Handler\n def_irq_handler PendSV_Handler\n def_irq_handler SysTick_Handler\n def_irq_handler Default_Handler\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM3.S", "content": "/* File: startup_ARMCM3.S\n * Purpose: startup file for Cortex-M3 devices. Should use with\n * GCC for ARM Embedded Processors\n * Version: V1.4\n * Date: 20 Dezember 2012\n *\n */\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n .syntax unified\n .arch armv7-m\n\n .section .stack\n .align 3\n#ifdef __STACK_SIZE\n .equ Stack_Size, __STACK_SIZE\n#else\n .equ Stack_Size, 0x00000400\n#endif\n .globl __StackTop\n .globl __StackLimit\n__StackLimit:\n .space Stack_Size\n .size __StackLimit, . - __StackLimit\n__StackTop:\n .size __StackTop, . - __StackTop\n\n .section .heap\n .align 3\n#ifdef __HEAP_SIZE\n .equ Heap_Size, __HEAP_SIZE\n#else\n .equ Heap_Size, 0x00000C00\n#endif\n .globl __HeapBase\n .globl __HeapLimit\n__HeapBase:\n .if Heap_Size\n .space Heap_Size\n .endif\n .size __HeapBase, . - __HeapBase\n__HeapLimit:\n .size __HeapLimit, . - __HeapLimit\n\n .section .isr_vector\n .align 2\n .globl __isr_vector\n__isr_vector:\n .long __StackTop /* Top of Stack */\n .long Reset_Handler /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long MemManage_Handler /* MPU Fault Handler */\n .long BusFault_Handler /* Bus Fault Handler */\n .long UsageFault_Handler /* Usage Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long DebugMon_Handler /* Debug Monitor Handler */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __isr_vector, . - __isr_vector\n\n .text\n .thumb\n .thumb_func\n .align 2\n .globl Reset_Handler\n .type Reset_Handler, %function\nReset_Handler:\n/* Loop to copy data from read only memory to RAM. The ranges\n * of copy from/to are specified by following symbols evaluated in\n * linker script.\n * __etext: End of code section, i.e., begin of data sections to copy from.\n * __data_start__/__data_end__: RAM address range that data should be\n * copied to. Both must be aligned to 4 bytes boundary. */\n\n ldr r1, =__etext\n ldr r2, =__data_start__\n ldr r3, =__data_end__\n\n#if 1\n/* Here are two copies of loop implemenations. First one favors code size\n * and the second one favors performance. Default uses the first one.\n * Change to \"#if 0\" to use the second one */\n.LC0:\n cmp r2, r3\n ittt lt\n ldrlt r0, [r1], #4\n strlt r0, [r2], #4\n blt .LC0\n#else\n subs r3, r2\n ble .LC1\n.LC0:\n subs r3, #4\n ldr r0, [r1, r3]\n str r0, [r2, r3]\n bgt .LC0\n.LC1:\n#endif\n\n#ifdef __STARTUP_CLEAR_BSS\n/* This part of work usually is done in C library startup code. Otherwise,\n * define this macro to enable it in this startup.\n *\n * Loop to zero out BSS section, which uses following symbols\n * in linker script:\n * __bss_start__: start of BSS section. Must align to 4\n * __bss_end__: end of BSS section. Must align to 4\n */\n ldr r1, =__bss_start__\n ldr r2, =__bss_end__\n\n movs r0, 0\n.LC2:\n cmp r1, r2\n itt lt\n strlt r0, [r1], #4\n blt .LC2\n#endif /* __STARTUP_CLEAR_BSS */\n\n#ifndef __NO_SYSTEM_INIT\n bl SystemInit\n#endif\n\n#ifndef __START\n#define __START _start\n#endif\n bl __START\n .pool\n .size Reset_Handler, . - Reset_Handler\n\n/* Macro to define default handlers. Default handler\n * will be weak symbol and just dead loops. They can be\n * overwritten by other handlers */\n .macro def_irq_handler handler_name\n .align 1\n .thumb_func\n .weak \\handler_name\n .type \\handler_name, %function\n\\handler_name :\n b .\n .size \\handler_name, . - \\handler_name\n .endm\n\n def_irq_handler NMI_Handler\n def_irq_handler HardFault_Handler\n def_irq_handler MemManage_Handler\n def_irq_handler BusFault_Handler\n def_irq_handler UsageFault_Handler\n def_irq_handler SVC_Handler\n def_irq_handler DebugMon_Handler\n def_irq_handler PendSV_Handler\n def_irq_handler SysTick_Handler\n def_irq_handler Default_Handler\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/GCC/startup_ARMCM4.S", "content": "/* File: startup_ARMCM4.S\n * Purpose: startup file for Cortex-M4 devices. Should use with\n * GCC for ARM Embedded Processors\n * Version: V1.4\n * Date: 20 Dezember 2012\n *\n */\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n .syntax unified\n .arch armv7-m\n\n .section .stack\n .align 3\n#ifdef __STACK_SIZE\n .equ Stack_Size, __STACK_SIZE\n#else\n .equ Stack_Size, 0x00000400\n#endif\n .globl __StackTop\n .globl __StackLimit\n__StackLimit:\n .space Stack_Size\n .size __StackLimit, . - __StackLimit\n__StackTop:\n .size __StackTop, . - __StackTop\n\n .section .heap\n .align 3\n#ifdef __HEAP_SIZE\n .equ Heap_Size, __HEAP_SIZE\n#else\n .equ Heap_Size, 0x00000C00\n#endif\n .globl __HeapBase\n .globl __HeapLimit\n__HeapBase:\n .if Heap_Size\n .space Heap_Size\n .endif\n .size __HeapBase, . - __HeapBase\n__HeapLimit:\n .size __HeapLimit, . - __HeapLimit\n\n .section .isr_vector\n .align 2\n .globl __isr_vector\n__isr_vector:\n .long __StackTop /* Top of Stack */\n .long Reset_Handler /* Reset Handler */\n .long NMI_Handler /* NMI Handler */\n .long HardFault_Handler /* Hard Fault Handler */\n .long MemManage_Handler /* MPU Fault Handler */\n .long BusFault_Handler /* Bus Fault Handler */\n .long UsageFault_Handler /* Usage Fault Handler */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long 0 /* Reserved */\n .long SVC_Handler /* SVCall Handler */\n .long DebugMon_Handler /* Debug Monitor Handler */\n .long 0 /* Reserved */\n .long PendSV_Handler /* PendSV Handler */\n .long SysTick_Handler /* SysTick Handler */\n\n /* External interrupts */\n .long WDT_IRQHandler /* 0: Watchdog Timer */\n .long RTC_IRQHandler /* 1: Real Time Clock */\n .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */\n .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */\n .long MCIA_IRQHandler /* 4: MCIa */\n .long MCIB_IRQHandler /* 5: MCIb */\n .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */\n .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */\n .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */\n .long UART4_IRQHandler /* 9: UART4 - not connected */\n .long AACI_IRQHandler /* 10: AACI / AC97 */\n .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */\n .long ENET_IRQHandler /* 12: Ethernet */\n .long USBDC_IRQHandler /* 13: USB Device */\n .long USBHC_IRQHandler /* 14: USB Host Controller */\n .long CHLCD_IRQHandler /* 15: Character LCD */\n .long FLEXRAY_IRQHandler /* 16: Flexray */\n .long CAN_IRQHandler /* 17: CAN */\n .long LIN_IRQHandler /* 18: LIN */\n .long I2C_IRQHandler /* 19: I2C ADC/DAC */\n .long 0 /* 20: Reserved */\n .long 0 /* 21: Reserved */\n .long 0 /* 22: Reserved */\n .long 0 /* 23: Reserved */\n .long 0 /* 24: Reserved */\n .long 0 /* 25: Reserved */\n .long 0 /* 26: Reserved */\n .long 0 /* 27: Reserved */\n .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */\n .long 0 /* 29: Reserved - CPU FPGA */\n .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */\n .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */\n\n .size __isr_vector, . - __isr_vector\n\n .text\n .thumb\n .thumb_func\n .align 2\n .globl Reset_Handler\n .type Reset_Handler, %function\nReset_Handler:\n/* Loop to copy data from read only memory to RAM. The ranges\n * of copy from/to are specified by following symbols evaluated in\n * linker script.\n * __etext: End of code section, i.e., begin of data sections to copy from.\n * __data_start__/__data_end__: RAM address range that data should be\n * copied to. Both must be aligned to 4 bytes boundary. */\n\n ldr r1, =__etext\n ldr r2, =__data_start__\n ldr r3, =__data_end__\n\n#if 1\n/* Here are two copies of loop implemenations. First one favors code size\n * and the second one favors performance. Default uses the first one.\n * Change to \"#if 0\" to use the second one */\n.LC0:\n cmp r2, r3\n ittt lt\n ldrlt r0, [r1], #4\n strlt r0, [r2], #4\n blt .LC0\n#else\n subs r3, r2\n ble .LC1\n.LC0:\n subs r3, #4\n ldr r0, [r1, r3]\n str r0, [r2, r3]\n bgt .LC0\n.LC1:\n#endif\n\n#ifdef __STARTUP_CLEAR_BSS\n/* This part of work usually is done in C library startup code. Otherwise,\n * define this macro to enable it in this startup.\n *\n * Loop to zero out BSS section, which uses following symbols\n * in linker script:\n * __bss_start__: start of BSS section. Must align to 4\n * __bss_end__: end of BSS section. Must align to 4\n */\n ldr r1, =__bss_start__\n ldr r2, =__bss_end__\n\n movs r0, 0\n.LC2:\n cmp r1, r2\n itt lt\n strlt r0, [r1], #4\n blt .LC2\n#endif /* __STARTUP_CLEAR_BSS */\n\n#ifndef __NO_SYSTEM_INIT\n bl SystemInit\n#endif\n\n#ifndef __START\n#define __START _start\n#endif\n bl __START\n .pool\n .size Reset_Handler, . - Reset_Handler\n\n/* Macro to define default handlers. Default handler\n * will be weak symbol and just dead loops. They can be\n * overwritten by other handlers */\n .macro def_irq_handler handler_name\n .align 1\n .thumb_func\n .weak \\handler_name\n .type \\handler_name, %function\n\\handler_name :\n b .\n .size \\handler_name, . - \\handler_name\n .endm\n\n def_irq_handler NMI_Handler\n def_irq_handler HardFault_Handler\n def_irq_handler MemManage_Handler\n def_irq_handler BusFault_Handler\n def_irq_handler UsageFault_Handler\n def_irq_handler SVC_Handler\n def_irq_handler DebugMon_Handler\n def_irq_handler PendSV_Handler\n def_irq_handler SysTick_Handler\n def_irq_handler Default_Handler\n\n def_irq_handler WDT_IRQHandler\n def_irq_handler RTC_IRQHandler\n def_irq_handler TIM0_IRQHandler\n def_irq_handler TIM2_IRQHandler\n def_irq_handler MCIA_IRQHandler\n def_irq_handler MCIB_IRQHandler\n def_irq_handler UART0_IRQHandler\n def_irq_handler UART1_IRQHandler\n def_irq_handler UART2_IRQHandler\n def_irq_handler UART3_IRQHandler\n def_irq_handler UART4_IRQHandler\n def_irq_handler AACI_IRQHandler\n def_irq_handler CLCD_IRQHandler\n def_irq_handler ENET_IRQHandler\n def_irq_handler USBDC_IRQHandler\n def_irq_handler USBHC_IRQHandler\n def_irq_handler CHLCD_IRQHandler\n def_irq_handler FLEXRAY_IRQHandler\n def_irq_handler CAN_IRQHandler\n def_irq_handler LIN_IRQHandler\n def_irq_handler I2C_IRQHandler\n def_irq_handler CPU_CLCD_IRQHandler\n def_irq_handler SPI_IRQHandler\n\n .end\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n*\n* Title:\t math_helper.h\n* \n* Description:\tPrototypes of all helper functions required. \n*\n* Target Processor: Cortex-M4/Cortex-M3\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n#ifndef MATH_HELPER_H\n#define MATH_HELPER_H\n\nfloat arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); \nvoid arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);\nvoid arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);\nvoid arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);\nvoid arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);\nvoid arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);\nvoid arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);\nvoid arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);\nvoid arm_clip_f32(float *pIn, uint32_t numSamples);\nuint32_t arm_calc_guard_bits(uint32_t num_adds);\nvoid arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);\nuint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);\nuint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);\nuint32_t arm_calc_2pow(uint32_t guard_bits);\n#endif\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n*\n* Title:\t math_helper.c\n*\n* Description:\tDefinition of all helper functions required. \n* \n* Target Processor: Cortex-M4/Cortex-M3\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n/* ----------------------------------------------------------------------\n*\t\tInclude standard header files \n* -------------------------------------------------------------------- */\n#include\n\n/* ----------------------------------------------------------------------\n*\t\tInclude project header files \n* -------------------------------------------------------------------- */\n#include \"math_helper.h\"\n\n/** \n * @brief Caluclation of SNR\n * @param float* \tPointer to the reference buffer\n * @param float*\tPointer to the test buffer\n * @param uint32_t\ttotal number of samples\n * @return float\tSNR\n * The function Caluclates signal to noise ratio for the reference output \n * and test output \n */\n\nfloat arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)\n{\n float EnergySignal = 0.0, EnergyError = 0.0;\n uint32_t i;\n float SNR;\n int temp;\n int *test;\n\n for (i = 0; i < buffSize; i++)\n {\n \t /* Checking for a NAN value in pRef array */\n\t test = (int *)(&pRef[i]);\n temp = *test;\n\n\t if(temp == 0x7FC00000)\n\t {\n\t \t\treturn(0);\n\t }\n\n\t /* Checking for a NAN value in pTest array */\n\t test = (int *)(&pTest[i]);\n temp = *test;\n\n\t if(temp == 0x7FC00000)\n\t {\n\t \t\treturn(0);\n\t }\n EnergySignal += pRef[i] * pRef[i];\n EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); \n }\n\n\t/* Checking for a NAN value in EnergyError */\n\ttest = (int *)(&EnergyError);\n temp = *test;\n\n if(temp == 0x7FC00000)\n {\n \t\treturn(0);\n }\n\t\n\n SNR = 10 * log10 (EnergySignal / EnergyError);\n\n return (SNR);\n\n}\n\n\n/** \n * @brief Provide guard bits for Input buffer\n * @param q15_t* \t Pointer to input buffer\n * @param uint32_t \tblockSize\n * @param uint32_t \tguard_bits\n * @return none\n * The function Provides the guard bits for the buffer \n * to avoid overflow \n */\n\nvoid arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,\n uint32_t guard_bits)\n{\n uint32_t i;\n\n for (i = 0; i < blockSize; i++)\n {\n input_buf[i] = input_buf[i] >> guard_bits;\n }\n}\n\n/** \n * @brief Converts float to fixed in q12.20 format\n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point(q12.20) values \n */\n\nvoid arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n\t /* 1048576.0f corresponds to pow(2, 20) */\n pOut[i] = (q31_t) (pIn[i] * 1048576.0f);\n\n pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;\n\n if (pIn[i] == (float) 1.0)\n {\n pOut[i] = 0x000FFFFF;\n }\n }\n}\n\n/** \n * @brief Compare MATLAB Reference Output and ARM Test output\n * @param q15_t* \tPointer to Ref buffer\n * @param q15_t* \tPointer to Test buffer\n * @param uint32_t \tnumber of samples in the buffer\n * @return none \n */\n\nuint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)\n{\n uint32_t i; \n int32_t diff, diffCrnt = 0;\n uint32_t maxDiff = 0;\n\n for (i = 0; i < numSamples; i++)\n {\n \tdiff = pIn[i] - pOut[i];\n \tdiffCrnt = (diff > 0) ? diff : -diff;\n\n\tif(diffCrnt > maxDiff)\n\t{\n\t\tmaxDiff = diffCrnt;\n\t}\t\n }\n\n return(maxDiff);\n}\n\n/** \n * @brief Compare MATLAB Reference Output and ARM Test output\n * @param q31_t* \tPointer to Ref buffer\n * @param q31_t* \tPointer to Test buffer\n * @param uint32_t \tnumber of samples in the buffer\n * @return none \n */\n\nuint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)\n{\n uint32_t i; \n int32_t diff, diffCrnt = 0;\n uint32_t maxDiff = 0;\n\n for (i = 0; i < numSamples; i++)\n {\n \tdiff = pIn[i] - pOut[i];\n \tdiffCrnt = (diff > 0) ? diff : -diff;\n\n\tif(diffCrnt > maxDiff)\n\t{\n\t\tmaxDiff = diffCrnt;\n\t}\n }\n\n return(maxDiff);\n}\n\n/** \n * @brief Provide guard bits for Input buffer\n * @param q31_t* \tPointer to input buffer\n * @param uint32_t \tblockSize\n * @param uint32_t \tguard_bits\n * @return none\n * The function Provides the guard bits for the buffer \n * to avoid overflow \n */\n\nvoid arm_provide_guard_bits_q31 (q31_t * input_buf, \n\t\t\t\t\t\t\t\t uint32_t blockSize,\n uint32_t guard_bits)\n{\n uint32_t i;\n\n for (i = 0; i < blockSize; i++)\n {\n input_buf[i] = input_buf[i] >> guard_bits;\n }\n}\n\n/** \n * @brief Provide guard bits for Input buffer\n * @param q31_t* \tPointer to input buffer\n * @param uint32_t \tblockSize\n * @param uint32_t \tguard_bits\n * @return none\n * The function Provides the guard bits for the buffer \n * to avoid overflow \n */\n\nvoid arm_provide_guard_bits_q7 (q7_t * input_buf, \n\t\t\t\t\t\t\t\tuint32_t blockSize,\n uint32_t guard_bits)\n{\n uint32_t i;\n\n for (i = 0; i < blockSize; i++)\n {\n input_buf[i] = input_buf[i] >> guard_bits;\n }\n}\n\n\n\n/** \n * @brief Caluclates number of guard bits \n * @param uint32_t \tnumber of additions\n * @return none\n * The function Caluclates the number of guard bits \n * depending on the numtaps \n */\n\nuint32_t arm_calc_guard_bits (uint32_t num_adds)\n{\n uint32_t i = 1, j = 0;\n\n if (num_adds == 1)\n {\n return (0);\n }\n\n while (i < num_adds)\n {\n i = i * 2;\n j++;\n }\n\n return (j);\n}\n\n/** \n * @brief Converts Q15 to floating-point\n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n */\n\nvoid arm_apply_guard_bits (float32_t * pIn, \n\t\t\t\t\t\t uint32_t numSamples, \n\t\t\t\t\t\t uint32_t guard_bits)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);\n }\n}\n\n/** \n * @brief Calculates pow(2, numShifts)\n * @param uint32_t \tnumber of shifts\n * @return pow(2, numShifts)\n */\nuint32_t arm_calc_2pow(uint32_t numShifts)\n{\n\n uint32_t i, val = 1;\n\n for (i = 0; i < numShifts; i++)\n {\n val = val * 2;\n }\t\n\n return(val);\n}\n\n\n\n/** \n * @brief Converts float to fixed q14 \n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point values \n */\n\nvoid arm_float_to_q14 (float *pIn, q15_t * pOut, \n uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n\t /* 16384.0f corresponds to pow(2, 14) */\n pOut[i] = (q15_t) (pIn[i] * 16384.0f);\n\n pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;\n\n if (pIn[i] == (float) 2.0)\n {\n pOut[i] = 0x7FFF;\n }\n\n }\n\n}\n\n \n/** \n * @brief Converts float to fixed q30 format\n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point values \n */\n\nvoid arm_float_to_q30 (float *pIn, q31_t * pOut, \n\t\t\t\t\t uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n\t /* 1073741824.0f corresponds to pow(2, 30) */\n pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);\n\n pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;\n\n if (pIn[i] == (float) 2.0)\n {\n pOut[i] = 0x7FFFFFFF;\n }\n }\n}\n\n/** \n * @brief Converts float to fixed q30 format\n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point values \n */\n\nvoid arm_float_to_q29 (float *pIn, q31_t * pOut, \n\t\t\t\t\t uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n\t /* 1073741824.0f corresponds to pow(2, 30) */\n pOut[i] = (q31_t) (pIn[i] * 536870912.0f);\n\n pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;\n\n if (pIn[i] == (float) 4.0)\n {\n pOut[i] = 0x7FFFFFFF;\n }\n }\n}\n\n\n/** \n * @brief Converts float to fixed q28 format\n * @param uint32_t \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point values \n */\n\nvoid arm_float_to_q28 (float *pIn, q31_t * pOut, \n uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n\t/* 268435456.0f corresponds to pow(2, 28) */\n pOut[i] = (q31_t) (pIn[i] * 268435456.0f);\n\n pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;\n\n if (pIn[i] == (float) 8.0)\n {\n pOut[i] = 0x7FFFFFFF;\n }\n }\n}\n\n/** \n * @brief Clip the float values to +/- 1 \n * @param pIn \tinput buffer\n * @param numSamples \tnumber of samples in the buffer\n * @return none\n * The function converts floating point values to fixed point values \n */\n\nvoid arm_clip_f32 (float *pIn, uint32_t numSamples)\n{\n uint32_t i;\n\n for (i = 0; i < numSamples; i++)\n {\n if(pIn[i] > 1.0f)\n\t {\n\t pIn[i] = 1.0;\n\t }\n\t else if( pIn[i] < -1.0f)\n\t {\n\t pIn[i] = -1.0;\n\t }\n\t \n }\n}\n\n\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/system_ARMCM0.c", "content": "/**************************************************************************//**\n * @file system_ARMCM0.c\n * @brief CMSIS Device System Source File for\n * ARMCM0 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n#include \"ARMCM0.h\"\n\n/*----------------------------------------------------------------------------\n Define clocks\n *----------------------------------------------------------------------------*/\n#define __HSI ( 8000000UL)\n#define __XTAL ( 5000000UL) /* Oscillator frequency */\n\n#define __SYSTEM_CLOCK (5*__XTAL)\n\n\n/*----------------------------------------------------------------------------\n Clock Variable definitions\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\n\n\n/*----------------------------------------------------------------------------\n Clock functions\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\n{\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n\n/**\n * Initialize the system\n *\n * @param none\n * @return none\n *\n * @brief Setup the microcontroller system.\n * Initialize the System.\n */\nvoid SystemInit (void)\n{\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/system_ARMCM3.c", "content": "/**************************************************************************//**\n * @file system_ARMCM3.c\n * @brief CMSIS Device System Source File for\n * ARMCM3 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n Define clocks\n *----------------------------------------------------------------------------*/\n#define __HSI ( 8000000UL)\n#define __XTAL ( 5000000UL) /* Oscillator frequency */\n\n#define __SYSTEM_CLOCK (5*__XTAL)\n\n\n/*----------------------------------------------------------------------------\n Clock Variable definitions\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\n\n\n/*----------------------------------------------------------------------------\n Clock functions\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\n{\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n\n/**\n * Initialize the system\n *\n * @param none\n * @return none\n *\n * @brief Setup the microcontroller system.\n * Initialize the System.\n */\nvoid SystemInit (void)\n{\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/Common/system_ARMCM4.c", "content": "/**************************************************************************//**\n * @file system_ARMCM4.c\n * @brief CMSIS Device System Source File for\n * ARMCM4 Device Series\n * @version V1.08\n * @date 23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2011 - 2012 ARM LIMITED\n\n All rights reserved.\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used\n to endorse or promote products derived from this software without\n specific prior written permission.\n *\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n ---------------------------------------------------------------------------*/\n\n\n#include \"ARMCM4.h\"\n\n/*----------------------------------------------------------------------------\n Define clocks\n *----------------------------------------------------------------------------*/\n#define __HSI ( 8000000UL)\n#define __XTAL ( 5000000UL) /* Oscillator frequency */\n\n#define __SYSTEM_CLOCK (5*__XTAL)\n\n\n/*----------------------------------------------------------------------------\n Clock Variable definitions\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/\n\n\n/*----------------------------------------------------------------------------\n Clock functions\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\n{\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n\n/**\n * Initialize the system\n *\n * @param none\n * @return none\n *\n * @brief Setup the microcontroller system.\n * Initialize the System.\n */\nvoid SystemInit (void)\n{\n #if (__FPU_USED == 1)\n SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */\n (3UL << 11*2) ); /* set CP11 Full Access */\n #endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n SystemCoreClock = __SYSTEM_CLOCK;\n\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_class_marks_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ..\\arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_class_marks_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ..\\arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ..\\arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 37\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_class_marks_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ..\\arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ..\\arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lfclass_marks_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ..\\arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_class_marks_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_class_marks_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM0l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ../../Common/G++/startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM3l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ../../Common/G++/startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/G++/arm_cortexM4lf_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\G++\n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ../../Common/G++/startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_class_marks_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM0.S\n startup_ARMCM0.S\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n startup_ARMCM0.S\n 1\n ../../Common/GCC/startup_ARMCM0.S\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 210\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_class_marks_example\\arm_class_marks_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM3.S\n startup_ARMCM3.S\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n startup_ARMCM3.S\n 1\n ../../Common/GCC/startup_ARMCM3.S\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 152\n 210\n 0\n ../arm_class_marks_example_f32.c\n arm_class_marks_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM4.S\n startup_ARMCM4.S\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_class_marks_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_class_marks_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\GCC\n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_class_marks_example_f32.c\n 1\n ../arm_class_marks_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n startup_ARMCM4.S\n 1\n ../../Common/GCC/startup_ARMCM4.S\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_class_marks_example_f32.c\n*\n* Description: Example code to calculate Minimum, Maximum\n* Mean, std and variance of marks obtained in a class\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup ClassMarks Class Marks Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance\n * and Matrix functions to calculate statistical values of marks obtained in a class.\n *\n * \\note This example also demonstrates the usage of static initialization.\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testMarks_f32 points to the marks scored by 20 students in 4 subjects\n * \\li \\c max_marks Maximum of all marks\n * \\li \\c min_marks Minimum of all marks\n * \\li \\c mean Mean of all marks\n * \\li \\c var Variance of the marks\n * \\li \\c std Standard deviation of the marks\n * \\li \\c numStudents Total number of students in the class\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_mat_init_f32()\n * - arm_mat_mult_f32()\n * - arm_max_f32()\n * - arm_min_f32()\n * - arm_mean_f32()\n * - arm_std_f32()\n * - arm_var_f32()\n *\n * Refer \n * \\link arm_class_marks_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_class_marks_example_f32.c\n */\n#include \"arm_math.h\"\n\n#define USE_STATIC_INIT\n\n /* ----------------------------------------------------------------------\n** Global defines\n** ------------------------------------------------------------------- */\n\n#define TEST_LENGTH_SAMPLES (20*4)\n\n/* ----------------------------------------------------------------------\n** List of Marks scored by 20 students for 4 subjects\n** ------------------------------------------------------------------- */\nconst float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =\n{\n 42.000000, 37.000000, 81.000000, 28.000000,\n 83.000000, 72.000000, 36.000000, 38.000000,\n 32.000000, 51.000000, 63.000000, 64.000000,\n 97.000000, 82.000000, 95.000000, 90.000000,\n 66.000000, 51.000000, 54.000000, 42.000000,\n 67.000000, 56.000000, 45.000000, 57.000000,\n 67.000000, 69.000000, 35.000000, 52.000000,\n 29.000000, 81.000000, 58.000000, 47.000000,\n 38.000000, 76.000000, 100.000000, 29.000000,\n 33.000000, 47.000000, 29.000000, 50.000000,\n 34.000000, 41.000000, 61.000000, 46.000000,\n 52.000000, 50.000000, 48.000000, 36.000000,\n 47.000000, 55.000000, 44.000000, 40.000000,\n 100.000000, 94.000000, 84.000000, 37.000000,\n 32.000000, 71.000000, 47.000000, 77.000000,\n 31.000000, 50.000000, 49.000000, 35.000000,\n 63.000000, 67.000000, 40.000000, 31.000000,\n 29.000000, 68.000000, 61.000000, 38.000000,\n 31.000000, 28.000000, 28.000000, 76.000000,\n 55.000000, 33.000000, 29.000000, 39.000000\n};\n\n\n/* ----------------------------------------------------------------------\n* Number of subjects X 1\n* ------------------------------------------------------------------- */\nconst float32_t testUnity_f32[4] =\n{\n 1.000, 1.000, 1.000, 1.000\n};\n\n\n/* ----------------------------------------------------------------------\n** f32 Output buffer\n** ------------------------------------------------------------------- */\nstatic float32_t testOutput[TEST_LENGTH_SAMPLES];\n\n\n/* ------------------------------------------------------------------\n* Global defines\n*------------------------------------------------------------------- */\n#define NUMSTUDENTS 20\n#define NUMSUBJECTS 4\n\n/* ------------------------------------------------------------------\n* Global variables\n*------------------------------------------------------------------- */\n\n uint32_t numStudents = 20;\n uint32_t numSubjects = 4;\nfloat32_t max_marks, min_marks, mean, std, var;\n uint32_t student_num;\n\n/* ----------------------------------------------------------------------------------\n* Main f32 test function. It returns maximum marks secured and student number\n* ------------------------------------------------------------------------------- */\n\nint32_t main()\n{\n\n#ifndef USE_STATIC_INIT\n\n arm_matrix_instance_f32 srcA;\n arm_matrix_instance_f32 srcB;\n arm_matrix_instance_f32 dstC;\n\n /* Input and output matrices initializations */\n arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);\n arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);\n arm_mat_init_f32(&dstC, numStudents, 1, testOutput);\n\n#else\n\n /* Static Initializations of Input and output matrix sizes and array */\n arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};\n arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};\n arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};\n\n#endif\n\n\n /* ----------------------------------------------------------------------\n *Call the Matrix multiplication process function\n * ------------------------------------------------------------------- */\n arm_mat_mult_f32(&srcA, &srcB, &dstC);\n\n /* ----------------------------------------------------------------------\n ** Call the Max function to calculate max marks among numStudents\n ** ------------------------------------------------------------------- */\n arm_max_f32(testOutput, numStudents, &max_marks, &student_num);\n\n /* ----------------------------------------------------------------------\n ** Call the Min function to calculate min marks among numStudents\n ** ------------------------------------------------------------------- */\n arm_min_f32(testOutput, numStudents, &min_marks, &student_num);\n\n /* ----------------------------------------------------------------------\n ** Call the Mean function to calculate mean\n ** ------------------------------------------------------------------- */\n arm_mean_f32(testOutput, numStudents, &mean);\n\n /* ----------------------------------------------------------------------\n ** Call the std function to calculate standard deviation\n ** ------------------------------------------------------------------- */\n arm_std_f32(testOutput, numStudents, &std);\n\n /* ----------------------------------------------------------------------\n ** Call the var function to calculate variance\n ** ------------------------------------------------------------------- */\n arm_var_f32(testOutput, numStudents, &var);\n\n while(1); /* main function does not return */\n}\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_convolution_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 1\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ..\\arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_convolution_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ..\\arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ..\\arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_convolution_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ..\\arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ..\\arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_convolution_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ..\\arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_convolution_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_convolution_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 1\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM0l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ../../Common/G++/startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM3l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ../../Common/G++/startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/G++/arm_cortexM4lf_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\G++\n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ../../Common/G++/startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_convolution_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 1\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM0.S\n startup_ARMCM0.S\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.S\n 1\n ../../Common/GCC/startup_ARMCM0.S\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM3.S\n startup_ARMCM3.S\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM3l_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.S\n 1\n ../../Common/GCC/startup_ARMCM3.S\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 241\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n 1\n 0\n 244\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_convolution_example\\arm_convolution_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 188\n 244\n 0\n ../arm_convolution_example_f32.c\n arm_convolution_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/Source/math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM4.S\n startup_ARMCM4.S\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM4lf_convolution_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_convolution_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_convolution_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\GCC\n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_convolution_example_f32.c\n 1\n ../arm_convolution_example_f32.c\n \n \n math_helper.c\n 1\n ../../Common/Source/math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.S\n 1\n ../../Common/GCC/startup_ARMCM4.S\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_convolution_example_f32.c\n*\n* Description: Example code demonstrating Convolution of two input signals using fft.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup ConvolutionExample Convolution Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex\n * Multiplication, and Support Functions.\n *\n * \\par Algorithm:\n * \\par\n * The convolution theorem states that convolution in the time domain corresponds to\n * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of\n * two signals is equal to the product of their individual Fourier transforms.\n * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT).\n * \\par\n * Two input signals, a[n] and b[n], with lengths \\c n1 and \\c n2 respectively,\n * are zero padded so that their lengths become \\c N, which is greater than or equal to (n1+n2-1)\n * and is a power of 4 as FFT implementation is radix-4.\n * The convolution of a[n] and b[n] is obtained by taking the FFT of the input\n * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of\n * the multiplied result.\n * \\par\n * This is denoted by the following equations:\n * 
 A[k] = FFT(a[n],N)\n * B[k] = FFT(b[n],N)\n * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
\n * where A[k] and B[k] are the N-point FFTs of the signals a[n]\n * and b[n] respectively.\n * The length of the convolved signal is (n1+n2-1).\n *\n * \\par Block Diagram:\n * \\par\n * \\image html Convolution.gif\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInputA_f32 points to the first input sequence\n * \\li \\c srcALen length of the first input sequence\n * \\li \\c testInputB_f32 points to the second input sequence\n * \\li \\c srcBLen length of the second input sequence\n * \\li \\c outLen length of convolution output sequence, (srcALen + srcBLen - 1)\n * \\li \\c AxB points to the output array where the product of individual FFTs of inputs is stored.\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_fill_f32()\n * - arm_copy_f32()\n * - arm_cfft_radix4_init_f32()\n * - arm_cfft_radix4_f32()\n * - arm_cmplx_mult_cmplx_f32()\n *\n * Refer \n * \\link arm_convolution_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_convolution_example_f32.c\n */\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n/* ----------------------------------------------------------------------\n* Defines each of the tests performed\n* ------------------------------------------------------------------- */\n#define MAX_BLOCKSIZE 128\n#define DELTA (0.000001f)\n#define SNR_THRESHOLD 90\n\n/* ----------------------------------------------------------------------\n* Declare I/O buffers\n* ------------------------------------------------------------------- */\nfloat32_t Ak[MAX_BLOCKSIZE]; /* Input A */\nfloat32_t Bk[MAX_BLOCKSIZE]; /* Input B */\nfloat32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */\n\n/* ----------------------------------------------------------------------\n* Test input data for Floating point Convolution example for 32-blockSize\n* Generated by the MATLAB randn() function\n* ------------------------------------------------------------------- */\nfloat32_t testInputA_f32[64] =\n{\n -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285,\n 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579,\n -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377,\n -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827,\n -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938,\n -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619,\n 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222,\n -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249,\n -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355,\n -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090,\n -0.161050, -0.940794, 0.367961, 0.291907\n\n};\n\nfloat32_t testInputB_f32[64] =\n{\n 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885,\n 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493,\n -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692,\n -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962,\n 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397,\n 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399,\n -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011,\n 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456,\n 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182,\n -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952,\n 0.635474, -0.970468, 1.334057, -0.111370\n};\n\nconst float testRefOutput_f32[126] =\n{\n -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656,\n 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012,\n -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236,\n -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508,\n -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267,\n 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552,\n 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344,\n -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488,\n -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415,\n -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462,\n 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280,\n 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073,\n -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291,\n 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885,\n 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417,\n 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678,\n -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410,\n -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013,\n -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358,\n -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638,\n 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440\n};\n\n\n/* ----------------------------------------------------------------------\n* Declare Global variables\n* ------------------------------------------------------------------- */\nuint32_t srcALen = 64; /* Length of Input A */\nuint32_t srcBLen = 64; /* Length of Input B */\nuint32_t outLen; /* Length of convolution output */\nfloat32_t snr; /* output SNR */\n\nint32_t main(void)\n{\n arm_status status; /* Status of the example */\n arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */\n\n /* CFFT Structure instance pointer */\n arm_cfft_radix4_instance_f32 *cfft_instance_ptr =\n (arm_cfft_radix4_instance_f32*) &cfft_instance;\n\n /* output length of convolution */\n outLen = srcALen + srcBLen - 1;\n\n /* Initialise the fft input buffers with all zeros */\n arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE);\n arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE);\n\n /* Copy the input values to the fft input buffers */\n arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2);\n arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2);\n\n /* Initialize the CFFT function to compute 64 point fft */\n status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);\n\n /* Transform input a[n] from time domain to frequency domain A[k] */\n arm_cfft_radix4_f32(cfft_instance_ptr, Ak);\n /* Transform input b[n] from time domain to frequency domain B[k] */\n arm_cfft_radix4_f32(cfft_instance_ptr, Bk);\n\n /* Complex Multiplication of the two input buffers in frequency domain */\n arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);\n\n /* Initialize the CIFFT function to compute 64 point ifft */\n status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);\n\n /* Transform the multiplication output from frequency domain to time domain,\n that gives the convolved output */\n arm_cfft_radix4_f32(cfft_instance_ptr, AxB);\n\n /* SNR Calculation */\n snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);\n\n /* Compare the SNR with threshold to test whether the\n computed output is matched with the reference output values. */\n if( snr > SNR_THRESHOLD)\n {\n status = ARM_MATH_SUCCESS;\n }\n\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ..\\arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_dotproduct_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ..\\arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ..\\arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_dotProduct_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ..\\arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ..\\arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_dotProduct_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ..\\arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_dotproduct_example.ini\n\n*/\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 1\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM0l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_dotproduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ../../Common/G++/startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM3l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_dotProduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\G++\n -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ../../Common/G++/startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/G++/startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_cortexM4lf_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_dotProduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\G++\n -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections\n ..\\..\\Common\\G++\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ../../Common/G++/startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/G++/arm_dotproduct_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_dotproduct_example.ini\n\n*/\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM0l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 1\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM0.S\n startup_ARMCM0.S\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM0l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_dotproduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M0\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM0l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.S\n 1\n ../../Common/GCC/startup_ARMCM0.S\n \n \n system_ARMCM0.c\n 1\n ../../Common/system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM3l_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM3.S\n startup_ARMCM3.S\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM3l_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_dotProduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotproduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \"Cortex-M3\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM3l_math\n ..\\..\\..\\..\\Lib\\GCC\n -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.S\n 1\n ../../Common/GCC/startup_ARMCM3.S\n \n \n system_ARMCM3.c\n 1\n ../../Common/system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x3\n ARM-GNU\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 120\n 65\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 172\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n 1\n 0\n 175\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_dotproduct_example\\arm_dotproduct_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 119\n 175\n 0\n ../arm_dotproduct_example_f32.c\n arm_dotproduct_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 1\n 0\n 0\n 0\n 0\n 126\n 142\n 0\n ../../Common/GCC/startup_ARMCM4.S\n startup_ARMCM4.S\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ../../Common/system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 0\n 0\n 0\n 0\n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_cortexM4lf_dotproduct_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x3\n ARM-GNU\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_dotProduct_example\n 1\n 0\n 0\n 1\n 0\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_dotProduct_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n \"Cortex-M4\"\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 2\n 1\n \n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections\n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 0\n 0\n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 1\n \n \n \n arm_cortexM4lf_math\n ..\\..\\..\\..\\Lib\\GCC\n -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections\n ..\\..\\Common\\GCC\\ARMCMx.ld\n \n \n \n \n \n Source Group 1\n \n \n arm_dotproduct_example_f32.c\n 1\n ../arm_dotproduct_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.S\n 1\n ../../Common/GCC/startup_ARMCM4.S\n \n \n system_ARMCM4.c\n 1\n ../../Common/system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/GCC/arm_dotproduct_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_dotproduct_example.ini\n\n*/\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_dotproduct_example_f32.c\n*\n* Description: Example code computing dot product of two vectors.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup DotproductExample Dot Product Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the use of the Multiply and Add functions to perform the dot product.\n * The dot product of two vectors is obtained by multiplying corresponding elements\n * and summing the products.\n\n * \\par Algorithm:\n * \\par\n * The two input vectors \\c A and \\c B with length \\c n, are multiplied element-by-element\n * and then added to obtain dot product.\n * \\par\n * This is denoted by the following equation:\n * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
\n *\n * \\par Block Diagram:\n * \\par\n * \\image html dotProduct.gif\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c srcA_buf_f32 points to first input vector\n * \\li \\c srcB_buf_f32 points to second input vector\n * \\li \\c testOutput stores dot product of the two input vectors.\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_mult_f32()\n * - arm_add_f32()\n *\n * Refer \n * \\link arm_dotproduct_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_dotproduct_example_f32.c\n */\n\n#include \n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\n* Defines each of the tests performed\n* ------------------------------------------------------------------- */\n#define MAX_BLOCKSIZE 32\n#define DELTA (0.000001f)\n\n/* ----------------------------------------------------------------------\n* Test input data for Floating point Dot Product example for 32-blockSize\n* Generated by the MATLAB randn() function\n* ------------------------------------------------------------------- */\n/* ----------------------------------------------------------------------\n** Test input data of srcA for blockSize 32\n** ------------------------------------------------------------------- */\nfloat32_t srcA_buf_f32[MAX_BLOCKSIZE] =\n{\n -0.4325648115282207, -1.6655843782380970, 0.1253323064748307,\n 0.2876764203585489, -1.1464713506814637, 1.1909154656429988,\n 1.1891642016521031, -0.0376332765933176, 0.3272923614086541,\n 0.1746391428209245, -0.1867085776814394, 0.7257905482933027,\n -0.5883165430141887, 2.1831858181971011, -0.1363958830865957,\n 0.1139313135208096, 1.0667682113591888, 0.0592814605236053,\n -0.0956484054836690, -0.8323494636500225, 0.2944108163926404,\n -1.3361818579378040, 0.7143245518189522, 1.6235620644462707,\n -0.6917757017022868, 0.8579966728282626, 1.2540014216025324,\n -1.5937295764474768, -1.4409644319010200, 0.5711476236581780,\n -0.3998855777153632, 0.6899973754643451\n};\n\n/* ----------------------------------------------------------------------\n** Test input data of srcB for blockSize 32\n** ------------------------------------------------------------------- */\nfloat32_t srcB_buf_f32[MAX_BLOCKSIZE] =\n{\n 1.7491401329284098, 0.1325982188803279, 0.3252281811989881,\n -0.7938091410349637, 0.3149236145048914, -0.5272704888029532,\n 0.9322666565031119, 1.1646643544607362, -2.0456694357357357,\n -0.6443728590041911, 1.7410657940825480, 0.4867684246821860,\n 1.0488288293660140, 1.4885752747099299, 1.2705014969484090,\n -1.8561241921210170, 2.1343209047321410, 1.4358467535865909,\n -0.9173023332875400, -1.1060770780029008, 0.8105708062681296,\n 0.6985430696369063, -0.4015827425012831, 1.2687512030669628,\n -0.7836083053674872, 0.2132664971465569, 0.7878984786088954,\n 0.8966819356782295, -0.1869172943544062, 1.0131816724341454,\n 0.2484350696132857, 0.0596083377937976\n};\n\n/* Reference dot product output */\nfloat32_t refDotProdOut = 5.9273644806352142;\n\n/* ----------------------------------------------------------------------\n* Declare Global variables\n* ------------------------------------------------------------------- */\nfloat32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */\nfloat32_t testOutput; /* Final ouput */\n\narm_status status; /* Status of the example */\n\nint32_t main(void)\n{\n uint32_t i; /* Loop counter */\n float32_t diff; /* Difference between reference and test outputs */\n\n /* Multiplication of two input buffers */\n arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE);\n\n /* Accumulate the multiplication output values to\n get the dot product of the two inputs */\n for(i=0; i< MAX_BLOCKSIZE; i++)\n {\n arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);\n }\n\n /* absolute value of difference between ref and test */\n diff = fabsf(refDotProdOut - testOutput);\n\n /* Comparison of dot product value with reference */\n if(diff > DELTA)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n if( status == ARM_MATH_TEST_FAILURE)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 151\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fft_bin_example\\arm_fft_bin_example_f32.c\n \n \n \n \n 1\n 0\n 154\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fft_bin_example\\arm_fft_bin_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 98\n 154\n 0\n ..\\arm_fft_bin_example_f32.c\n arm_fft_bin_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 3\n 0\n 0\n 0\n 0\n ..\\arm_fft_bin_data.c\n arm_fft_bin_data.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_fft_bin_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fft_bin_example_f32.c\n 1\n ..\\arm_fft_bin_example_f32.c\n \n \n arm_fft_bin_data.c\n 1\n ..\\arm_fft_bin_data.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 151\n 1\n
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0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fft_bin_example\\arm_fft_bin_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_fft_bin_data.c\n arm_fft_bin_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 98\n 154\n 0\n ..\\arm_fft_bin_example_f32.c\n arm_fft_bin_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_fft_bin_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fft_bin_data.c\n 1\n ..\\arm_fft_bin_data.c\n \n \n arm_fft_bin_example_f32.c\n 1\n ..\\arm_fft_bin_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 151\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fft_bin_example\\arm_fft_bin_example_f32.c\n \n \n \n \n 1\n 0\n 154\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fft_bin_example\\arm_fft_bin_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_fft_bin_data.c\n arm_fft_bin_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 98\n 154\n 0\n ..\\arm_fft_bin_example_f32.c\n arm_fft_bin_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_fft_bin_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fft_bin_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fft_bin_data.c\n 1\n ..\\arm_fft_bin_data.c\n \n \n arm_fft_bin_example_f32.c\n 1\n ..\\arm_fft_bin_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_fft_bin_example.ini\n\n*/\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t \tarm_fft_bin_data.c\n* \n* Description:\t Data file used for example code\n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n * -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\nTest Input signal contains 10KHz signal + Uniformly distributed white noise\n** ------------------------------------------------------------------- */\n\nfloat32_t testInput_f32_10khz[2048] = \n{ \n-0.865129623056441, \t0.000000000000000, \t-2.655020678073846, \t0.000000000000000, \t0.600664612949661, \t0.000000000000000, \t0.080378093886515, \t0.000000000000000, \t\n-2.899160484012034, \t0.000000000000000, \t2.563004262857762, \t0.000000000000000, \t3.078328403304206, \t0.000000000000000, \t0.105906778385130, \t0.000000000000000, \t\n0.048366940168201, \t0.000000000000000, \t-0.145696461188734, \t0.000000000000000, \t-0.023417155362879, \t0.000000000000000, \t2.127729174988954, \t0.000000000000000, \t\n-1.176633086028377, \t0.000000000000000, \t3.690223557991855, \t0.000000000000000, \t-0.622791766173194, \t0.000000000000000, \t0.722837373872203, \t0.000000000000000, \t\n2.739754205367484, \t0.000000000000000, \t-0.062610410524552, \t0.000000000000000, \t-0.891296810967338, \t0.000000000000000, \t-1.845872258871811, \t0.000000000000000, \t\n1.195039415434387, \t0.000000000000000, \t-2.177388969045026, \t0.000000000000000, \t1.078649103637905, \t0.000000000000000, \t2.570976050490193, \t0.000000000000000, \t\n-1.383551403404574, \t0.000000000000000, \t2.392141424058873, \t0.000000000000000, \t2.858002843205065, \t0.000000000000000, \t-3.682433899725536, \t0.000000000000000, \t\n-3.488146646451150, \t0.000000000000000, \t1.323468578888120, \t0.000000000000000, \t-0.099771155430726, \t0.000000000000000, \t1.561168082500454, \t0.000000000000000, \t\n1.025026795103179, \t0.000000000000000, \t0.928841900171200, \t0.000000000000000, \t2.930499509864950, \t0.000000000000000, \t2.013349089766430, \t0.000000000000000, \t\n2.381676148486737, \t0.000000000000000, \t-3.081062307950236, \t0.000000000000000, \t-0.389579115537544, \t0.000000000000000, \t0.181540149166620, \t0.000000000000000, \t\n-2.601953341353208, \t0.000000000000000, \t0.333435137783218, \t0.000000000000000, \t-2.812945856162965, \t0.000000000000000, \t2.649109640172910, \t0.000000000000000, \t\n-1.003963025744654, \t0.000000000000000, \t1.552460768755035, \t0.000000000000000, \t0.088641345335247, \t0.000000000000000, \t-2.519951327113426, \t0.000000000000000, \t\n-4.341348988610527, \t0.000000000000000, \t0.557772429359965, \t0.000000000000000, \t-1.671267412948494, \t0.000000000000000, \t0.733951350960387, \t0.000000000000000, \t\n0.409263788034864, \t0.000000000000000, \t3.566033071952806, \t0.000000000000000, \t1.882565173848352, \t0.000000000000000, \t-1.106017073793287, \t0.000000000000000, \t\n0.154456720778718, \t0.000000000000000, \t-2.513205795512153, \t0.000000000000000, \t0.310978660939421, \t0.000000000000000, \t0.579706500111723, \t0.000000000000000, \t\n0.000086383683251, \t0.000000000000000, \t-1.311866980897721, \t0.000000000000000, \t1.840007477574986, \t0.000000000000000, \t-3.253005768451345, \t0.000000000000000, \t\n1.462584328739432, \t0.000000000000000, \t1.610103610851738, \t0.000000000000000, \t0.761914676858907, \t0.000000000000000, \t0.974541361089834, \t0.000000000000000, \t\n0.686845845885983, \t0.000000000000000, \t1.849153122025191, \t0.000000000000000, \t0.787800410401453, \t0.000000000000000, \t-1.187438909666279, \t0.000000000000000, \t\n-0.754937911044720, \t0.000000000000000, \t0.084373858395232, \t0.000000000000000, \t-2.600269011710521, \t0.000000000000000, \t-0.962982842142644, \t0.000000000000000, \t\n-0.369328108540868, \t0.000000000000000, \t0.810791418361879, \t0.000000000000000, \t3.587016488699641, \t0.000000000000000, \t-0.520776145083723, \t0.000000000000000, \t\n0.640249919627884, \t0.000000000000000, \t1.103122489464969, \t0.000000000000000, \t2.231779881455556, \t0.000000000000000, \t-1.308035392685241, \t0.000000000000000, \t\n0.424070304330106, \t0.000000000000000, \t-0.200383932651189, \t0.000000000000000, \t-2.365526783356541, \t0.000000000000000, \t-0.989114757436628, \t0.000000000000000, \t\n2.770807688959777, \t0.000000000000000, \t-0.444172737462307, \t0.000000000000000, \t0.079760979374078, \t0.000000000000000, \t-0.005199118412183, \t0.000000000000000, \t\n-0.664712668309527, \t0.000000000000000, \t-0.624171857561896, \t0.000000000000000, \t0.537306979007338, \t0.000000000000000, \t-2.575955675497642, \t0.000000000000000, \t\n1.562363235756780, \t0.000000000000000, \t1.814069369848895, \t0.000000000000000, \t-1.293428583392509, \t0.000000000000000, \t-1.026188449495686, \t0.000000000000000, \t\n-2.981771815588717, \t0.000000000000000, \t-4.223468103075124, \t0.000000000000000, \t2.672674782004045, \t0.000000000000000, \t-0.856096801117735, \t0.000000000000000, \t\n0.048517345512563, \t0.000000000000000, \t-0.026860721136222, \t0.000000000000000, \t0.392932277758187, \t0.000000000000000, \t-1.331740855093099, \t0.000000000000000, \t\n-1.894292129477081, \t0.000000000000000, \t-1.425006468460681, \t0.000000000000000, \t-2.721772427617057, \t0.000000000000000, \t-1.616831100216806, \t0.000000000000000, \t\n3.551177651488947, \t0.000000000000000, \t-0.069685667896087, \t0.000000000000000, \t-3.134634907409102, \t0.000000000000000, \t-0.263627598944639, \t0.000000000000000, \t\n-1.650469945991350, \t0.000000000000000, \t-2.203580339374399, \t0.000000000000000, \t-0.872203246123242, \t0.000000000000000, \t1.230782812607287, \t0.000000000000000, \t\n0.257288860093291, \t0.000000000000000, \t1.989083106173137, \t0.000000000000000, \t-1.985638729453261, \t0.000000000000000, \t-1.416185105842892, \t0.000000000000000, \t\n-1.131097688325772, \t0.000000000000000, \t-2.245130805416057, \t0.000000000000000, \t-1.938873996219074, \t0.000000000000000, \t2.043608361562645, \t0.000000000000000, \t\n-0.583727989880841, \t0.000000000000000, \t-1.785266378212929, \t0.000000000000000, \t1.961457586224753, \t0.000000000000000, \t1.139400099963223, \t0.000000000000000, \t\n-1.979519343363991, \t0.000000000000000, \t2.003023322818429, \t0.000000000000000, \t0.229004069076829, \t0.000000000000000, \t3.452808862193135, \t0.000000000000000, \t\n2.882273808365857, \t0.000000000000000, \t-1.549450501844438, \t0.000000000000000, \t-3.283872089931876, \t0.000000000000000, \t-0.327025884099064, \t0.000000000000000, \t\n-0.054979977136430, \t0.000000000000000, \t-1.192280531479012, \t0.000000000000000, \t0.645539328365578, \t0.000000000000000, \t2.300832863404618, \t0.000000000000000, \t\n-1.092951789535240, \t0.000000000000000, \t-1.017368249363773, \t0.000000000000000, \t-0.142673056169787, \t0.000000000000000, \t0.831073544881250, \t0.000000000000000, \t\n-2.314612531587064, \t0.000000000000000, \t-2.221456299106321, \t0.000000000000000, \t0.460261143885226, \t0.000000000000000, \t0.050585301888595, \t0.000000000000000, \t\n0.364373329183988, \t0.000000000000000, \t-1.685956552069538, \t0.000000000000000, \t0.050664512351055, \t0.000000000000000, \t-0.193355783902718, \t0.000000000000000, \t\n-0.158660446046828, \t0.000000000000000, \t2.394156453841953, \t0.000000000000000, \t-1.562965718554525, \t0.000000000000000, \t-2.199750600869900, \t0.000000000000000, \t\n1.544984022381773, \t0.000000000000000, \t-1.988307216807315, \t0.000000000000000, \t-0.628240722541046, \t0.000000000000000, \t-1.436235771505429, \t0.000000000000000, \t\n1.677013691147313, \t0.000000000000000, \t1.600741781678228, \t0.000000000000000, \t-0.757380959134706, \t0.000000000000000, \t-4.784797439515566, \t0.000000000000000, \t\n0.265121462834569, \t0.000000000000000, \t3.862029485934378, \t0.000000000000000, \t2.386823577249430, \t0.000000000000000, \t-3.655779745436893, \t0.000000000000000, \t\n-0.763541621368016, \t0.000000000000000, \t-1.182140388432962, \t0.000000000000000, \t-1.349106114858063, \t0.000000000000000, \t-2.287533624396759, \t0.000000000000000, \t\n-0.028603745188423, \t0.000000000000000, \t-1.353580755934427, \t0.000000000000000, \t0.461602380352937, \t0.000000000000000, \t-0.059599055078928, \t0.000000000000000, \t\n-0.929946734342228, \t0.000000000000000, \t0.065773089295561, \t0.000000000000000, \t1.106565863102982, \t0.000000000000000, \t4.719295086373593, \t0.000000000000000, \t\n-2.108377703544395, \t0.000000000000000, \t-2.226393620240159, \t0.000000000000000, \t1.375668397437521, \t0.000000000000000, \t-0.960772428525443, \t0.000000000000000, \t\n-2.156313465390571, \t0.000000000000000, \t1.126060012375311, \t0.000000000000000, \t2.756485137030720, \t0.000000000000000, \t0.739639690862600, \t0.000000000000000, \t\n3.914769510295006, \t0.000000000000000, \t1.685232785586675, \t0.000000000000000, \t4.079058040970612, \t0.000000000000000, \t-1.174598301660513, \t0.000000000000000, \t\n-2.885776587275580, \t0.000000000000000, \t-0.241073635188767, \t0.000000000000000, \t3.080489872502403, \t0.000000000000000, \t-2.051244183999421, \t0.000000000000000, \t\n0.664330486845139, \t0.000000000000000, \t-1.697798999370016, \t0.000000000000000, \t1.452369423649782, \t0.000000000000000, \t-1.523532831019280, \t0.000000000000000, \t\n0.171981186587481, \t0.000000000000000, \t-4.685274721583927, \t0.000000000000000, \t-1.336175835319380, \t0.000000000000000, \t1.419070770428945, \t0.000000000000000, \t\n-0.035791601713475, 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\t0.000000000000000, \t2.829507048720695, \t0.000000000000000, \t\n-0.859177034120755, \t0.000000000000000, \t-1.969302377743254, \t0.000000000000000, \t0.777437674525362, \t0.000000000000000, \t-0.124910190157646, \t0.000000000000000, \t\n0.129875493115290, \t0.000000000000000, \t-4.192139262163992, \t0.000000000000000, \t3.023496047962126, \t0.000000000000000, \t1.149775163736637, \t0.000000000000000, \t\n2.038151304801731, \t0.000000000000000, \t3.016122489841263, \t0.000000000000000, \t-4.829481812137012, \t0.000000000000000, \t-1.668436615909279, \t0.000000000000000, \t\n0.958586784636918, \t0.000000000000000, \t1.550652410058678, \t0.000000000000000, \t-1.456305257976716, \t0.000000000000000, \t-0.079588392344731, \t0.000000000000000, \t\n-2.453213599392345, \t0.000000000000000, \t0.296795909127105, \t0.000000000000000, \t-0.253426616607643, \t0.000000000000000, \t1.418937160028195, \t0.000000000000000, \t\n-1.672949529066915, \t0.000000000000000, \t-1.620990298572947, \t0.000000000000000, \t-1.085103073196045, \t0.000000000000000, \t0.738606361195386, \t0.000000000000000, \t\n-2.097831202853255, \t0.000000000000000, \t2.711952282071310, \t0.000000000000000, \t1.498539238246888, \t0.000000000000000, \t1.317457282535915, \t0.000000000000000, \t\n-0.302765938349717, \t0.000000000000000, \t-0.044623707947201, \t0.000000000000000, \t2.337405215062395, \t0.000000000000000, \t-3.980689173859100, \t0.000000000000000, \t\n\n\n};\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_example_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* \n* Description: Example code demonstrating calculation of Max energy bin of \n* frequency domain of input signal. \n* \n* Target Processor: Cortex-M4/Cortex-M3 \n*\n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n * -------------------------------------------------------------------- */\n \n/** \n * @ingroup groupExamples \n */ \n \n/** \n * @defgroup FrequencyBin Frequency Bin Example \n * \n * \\par Description\n * \\par\n * Demonstrates the calculation of the maximum energy bin in the frequency \n * domain of the input signal with the use of Complex FFT, Complex \n * Magnitude, and Maximum functions. \n * \n * \\par Algorithm:\n * \\par\n * The input test signal contains a 10 kHz signal with uniformly distributed white noise. \n * Calculating the FFT of the input signal will give us the maximum energy of the \n * bin corresponding to the input frequency of 10 kHz. \n * \n * \\par Block Diagram:\n * \\image html FFTBin.gif \"Block Diagram\"\n * \\par\n * The figure below shows the time domain signal of 10 kHz signal with \n * uniformly distributed white noise, and the next figure shows the input\n * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. \n * \\par\n * \\image html FFTBinInput.gif \"Input signal in Time domain\" \n * \\image html FFTBinOutput.gif \"Input signal in Frequency domain\"\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32_10khz points to the input data\n * \\li \\c testOutput points to the output data\n * \\li \\c fftSize length of FFT\n * \\li \\c ifftFlag flag for the selection of CFFT/CIFFT\n * \\li \\c doBitReverse Flag for selection of normal order or bit reversed order\n * \\li \\c refIndex reference index value at which maximum energy of bin ocuurs\n * \\li \\c testIndex calculated index value at which maximum energy of bin ocuurs\n * \n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_cfft_f32()\n * - arm_cmplx_mag_f32()\n * - arm_max_f32()\n *\n * Refer \n * \\link arm_fft_bin_example_f32.c \\endlink\n * \n */ \n \n \n/** \\example arm_fft_bin_example_f32.c \n */ \n\n \n#include \"arm_math.h\" \n#include \"arm_const_structs.h\"\n \n#define TEST_LENGTH_SAMPLES 2048 \n \n/* ------------------------------------------------------------------- \n* External Input and Output buffer Declarations for FFT Bin Example \n* ------------------------------------------------------------------- */ \nextern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; \nstatic float32_t testOutput[TEST_LENGTH_SAMPLES/2]; \n \n/* ------------------------------------------------------------------ \n* Global variables for FFT Bin Example \n* ------------------------------------------------------------------- */ \nuint32_t fftSize = 1024; \nuint32_t ifftFlag = 0; \nuint32_t doBitReverse = 1; \n \n/* Reference index at which max energy of bin ocuurs */ \nuint32_t refIndex = 213, testIndex = 0; \n \n/* ---------------------------------------------------------------------- \n* Max magnitude FFT Bin test \n* ------------------------------------------------------------------- */ \n \nint32_t main(void) \n{ \n \n arm_status status; \n float32_t maxValue; \n \n status = ARM_MATH_SUCCESS; \n \n /* Process the data through the CFFT/CIFFT module */ \n arm_cfft_f32(&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse);\n \n /* Process the data through the Complex Magnitude Module for \n calculating the magnitude at each bin */ \n arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize); \n \n /* Calculates maxValue and returns corresponding BIN value */ \n arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); \n \n if(testIndex != refIndex) \n { \n status = ARM_MATH_TEST_FAILURE; \n } \n \n /* ---------------------------------------------------------------------- \n ** Loop here if the signals fail the PASS check. \n ** This denotes a test failure \n ** ------------------------------------------------------------------- */ \n \n if( status != ARM_MATH_SUCCESS) \n { \n while(1); \n } \n\n while(1); /* main function does not return */\n} \n \n /** \\endlink */ \n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_fir_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 227\n 1\n
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### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_fir_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fir_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fir_data.c\n 1\n ..\\arm_fir_data.c\n \n \n arm_fir_example_f32.c\n 1\n ..\\arm_fir_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fir_example\\arm_fir_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_fir_data.c\n arm_fir_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 174\n 230\n 0\n ..\\arm_fir_example_f32.c\n arm_fir_example_f32.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_fir_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fir_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fir_data.c\n 1\n ..\\arm_fir_data.c\n \n \n arm_fir_example_f32.c\n 1\n ..\\arm_fir_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_fir_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 227\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fir_example\\arm_fir_example_f32.c\n \n \n \n \n 1\n 0\n 230\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_fir_example\\arm_fir_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 77\n 0\n 0\n 0\n 0\n ..\\arm_fir_data.c\n arm_fir_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 174\n 230\n 0\n ..\\arm_fir_example_f32.c\n arm_fir_example_f32.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 16\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_fir_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_fir_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\Common\\Include;..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_fir_data.c\n 1\n ..\\arm_fir_data.c\n \n \n arm_fir_example_f32.c\n 1\n ..\\arm_fir_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_fir_lpf_example.ini\n\n*/\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t \tarm_fir_data.c\n* \n* Description:\t Data file used for example code\n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n * -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\n** Test input signal contains 1000Hz + 15000 Hz\n** ------------------------------------------------------------------- */\n\nfloat32_t testInput_f32_1kHz_15kHz[320] =\n{\n+0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n+0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n+0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n+0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n+0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n+0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n+0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n+0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, \n-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, \n-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, \n+0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, \n+0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, \n+0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, \n};\n\nfloat32_t refOutput[320] = \n{\n+0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, \n-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, \n+0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, \n+0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, \n+0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, \n-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, \n-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, \n-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, \n+0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, \n+0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f \n};\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c", "content": "/* ----------------------------------------------------------------------\n * Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n *\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n * Title: arm_fir_example_f32.c\n *\n * Description: Example code demonstrating how an FIR filter can be used\n * as a low pass filter.\n *\n * Target Processor: Cortex-M4/Cortex-M3\n *\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup FIRLPF FIR Lowpass Filter Example\n *\n * \\par Description:\n * \\par\n * Removes high frequency signal components from the input using an FIR lowpass filter.\n * The example demonstrates how to configure an FIR filter and then pass data through\n * it in a block-by-block fashion.\n * \\image html FIRLPF_signalflow.gif\n *\n * \\par Algorithm:\n * \\par\n * The input signal is a sum of two sine waves: 1 kHz and 15 kHz.\n * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz.\n * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output.\n * \\par\n * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and\n * a length of 29 points.\n * The MATLAB code to generate the filter coefficients is shown below:\n * 
\n *     h = fir1(28, 6/24);\n *
\n * The first argument is the \"order\" of the filter and is always one less than the desired length.\n * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist).\n * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25.\n * The CMSIS FIR filter function requires the coefficients to be in time reversed order.\n * 
\n *     fliplr(h)\n *
\n * The resulting filter coefficients and are shown below.\n * Note that the filter is symmetric (a property of linear phase FIR filters)\n * and the point of symmetry is sample 14. Thus the filter will have a delay of\n * 14 samples for all frequencies.\n * \\par\n * \\image html FIRLPF_coeffs.gif\n * \\par\n * The frequency response of the filter is shown next.\n * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz.\n * \\par\n * \\image html FIRLPF_response.gif\n * \\par\n * The input signal is shown below.\n * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation.\n * The two sine wave components can be clearly seen.\n * \\par\n * \\image html FIRLPF_input.gif\n * \\par\n * The output of the filter is shown below. The 15 kHz component has been eliminated.\n * \\par\n * \\image html FIRLPF_output.gif\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32_1kHz_15kHz points to the input data\n * \\li \\c refOutput points to the reference output data\n * \\li \\c testOutput points to the test output data\n * \\li \\c firStateF32 points to state buffer\n * \\li \\c firCoeffs32 points to coefficient buffer\n * \\li \\c blockSize number of samples processed at a time\n * \\li \\c numBlocks number of frames\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_fir_init_f32()\n * - arm_fir_f32()\n *\n * Refer \n * \\link arm_fir_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_fir_example_f32.c\n */\n\n/* ----------------------------------------------------------------------\n** Include Files\n** ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n/* ----------------------------------------------------------------------\n** Macro Defines\n** ------------------------------------------------------------------- */\n\n#define TEST_LENGTH_SAMPLES 320\n#define SNR_THRESHOLD_F32 140.0f\n#define BLOCK_SIZE 32\n#define NUM_TAPS 29\n\n/* -------------------------------------------------------------------\n * The input signal and reference output (computed with MATLAB)\n * are defined externally in arm_fir_lpf_data.c.\n * ------------------------------------------------------------------- */\n\nextern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES];\nextern float32_t refOutput[TEST_LENGTH_SAMPLES];\n\n/* -------------------------------------------------------------------\n * Declare Test output buffer\n * ------------------------------------------------------------------- */\n\nstatic float32_t testOutput[TEST_LENGTH_SAMPLES];\n\n/* -------------------------------------------------------------------\n * Declare State buffer of size (numTaps + blockSize - 1)\n * ------------------------------------------------------------------- */\n\nstatic float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1];\n\n/* ----------------------------------------------------------------------\n** FIR Coefficients buffer generated using fir1() MATLAB function.\n** fir1(28, 6/24)\n** ------------------------------------------------------------------- */\n\nconst float32_t firCoeffs32[NUM_TAPS] = {\n -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f,\n -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f,\n +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f,\n +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f\n};\n\n/* ------------------------------------------------------------------\n * Global variables for FIR LPF Example\n * ------------------------------------------------------------------- */\n\nuint32_t blockSize = BLOCK_SIZE;\nuint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE;\n\nfloat32_t snr;\n\n/* ----------------------------------------------------------------------\n * FIR LPF Example\n * ------------------------------------------------------------------- */\n\nint32_t main(void)\n{\n uint32_t i;\n arm_fir_instance_f32 S;\n arm_status status;\n float32_t *inputF32, *outputF32;\n\n /* Initialize input and output buffer pointers */\n inputF32 = &testInput_f32_1kHz_15kHz[0];\n outputF32 = &testOutput[0];\n\n /* Call FIR init function to initialize the instance structure. */\n arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize);\n\n /* ----------------------------------------------------------------------\n ** Call the FIR process function for every blockSize samples\n ** ------------------------------------------------------------------- */\n\n for(i=0; i < numBlocks; i++)\n {\n arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);\n }\n\n /* ----------------------------------------------------------------------\n ** Compare the generated output against the reference output computed\n ** in MATLAB.\n ** ------------------------------------------------------------------- */\n\n snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES);\n\n if (snr < SNR_THRESHOLD_F32)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n else\n {\n status = ARM_MATH_SUCCESS;\n }\n\n /* ----------------------------------------------------------------------\n ** Loop here if the signal does not match the reference output.\n ** ------------------------------------------------------------------- */\n\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n/** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n 1\n 0\n 405\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 352\n 405\n 0\n ..\\arm_graphic_equalizer_example_q31.c\n arm_graphic_equalizer_example_q31.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_graphic_equalizer_data.c\n arm_graphic_equalizer_data.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_graphic_equalizer_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_graphic_equalizer_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_graphic_equalizer_example_q31.c\n 1\n ..\\arm_graphic_equalizer_example_q31.c\n \n \n arm_graphic_equalizer_data.c\n 1\n ..\\arm_graphic_equalizer_data.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_graphic_equalizer_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 402\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n 1\n 0\n 405\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_graphic_equalizer_data.c\n arm_graphic_equalizer_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 352\n 405\n 0\n ..\\arm_graphic_equalizer_example_q31.c\n arm_graphic_equalizer_example_q31.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_graphic_equalizer_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_graphic_equalizer_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_graphic_equalizer_data.c\n 1\n ..\\arm_graphic_equalizer_data.c\n \n \n arm_graphic_equalizer_example_q31.c\n 1\n ..\\arm_graphic_equalizer_example_q31.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_graphic_equalizer_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 402\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n 1\n 0\n 405\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_graphic_equalizer_example\\arm_graphic_equalizer_example_q31.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_graphic_equalizer_data.c\n arm_graphic_equalizer_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 352\n 405\n 0\n ..\\arm_graphic_equalizer_example_q31.c\n arm_graphic_equalizer_example_q31.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_graphic_equalizer_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_graphic_equalizer_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_graphic_equalizer_data.c\n 1\n ..\\arm_graphic_equalizer_data.c\n \n \n arm_graphic_equalizer_example_q31.c\n 1\n ..\\arm_graphic_equalizer_example_q31.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_geq_5band_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t \tarm_graphic_equalizer_data.c\n* \n* Description:\t Data file used for example code\n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n * -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nfloat32_t testRefOutput_f32[320] = {\n\n0.000000000000000000,\t0.001898396760225296,\t0.004215449094772339,\t0.007432077080011368,\t0.010948467999696732,\t0.015026375651359558,\t0.019191544502973557,\t0.023574527353048325,\t\n0.027919445186853409,\t0.032277785241603851,\t0.036551639437675476,\t0.040732793509960175,\t0.044799156486988068,\t0.048710610717535019,\t0.052476800978183746,\t0.056059073656797409,\t\n0.059482168406248093,\t0.062726479023694992,\t0.065821025520563126,\t0.068763464689254761,\t0.071577839553356171,\t0.074270240962505341,\t0.076856281608343124,\t0.079344697296619415,\t\n0.081745062023401260,\t0.084067162126302719,\t0.086318407207727432,\t0.088509257882833481,\t0.090647127479314804,\t0.092742368578910828,\t0.094802625477313995,\t0.096837285906076431,\t\n0.098853722214698792,\t0.100859899073839190,\t0.102862443774938580,\t0.104867763817310330,\t0.106881409883499150,\t0.108908228576183320,\t0.110952425748109820,\t0.113017357885837550,\t\n0.115105822682380680,\t0.117219865322113040,\t0.119361080229282380,\t0.121530555188655850,\t0.123729091137647630,\t0.125957202166318890,\t0.128215309232473370,\t0.130503740161657330,\t\n0.132822841405868530,\t0.135173004120588300,\t0.137554679065942760,\t0.139968376606702800,\t0.142414685338735580,\t0.144894234836101530,\t0.147407654672861100,\t0.149955596774816510,\t\n0.152538605034351350,\t0.155157200992107390,\t0.157811731100082400,\t0.160502441227436070,\t0.163229387253522870,\t0.165992442518472670,\t0.168791320174932480,\t0.171625509858131410,\t\n0.174494370818138120,\t0.177397061139345170,\t0.180332608520984650,\t0.183299910277128220,\t0.186297744512557980,\t0.189324837177991870,\t0.192379791289567950,\t0.195461250841617580,\t\n0.198567759245634080,\t0.201697919517755510,\t0.204850304871797560,\t0.208023533225059510,\t0.211216274648904800,\t0.214427210390567780,\t0.217655111104249950,\t0.220898788422346120,\t\n0.224157124757766720,\t0.227429077029228210,\t0.230713658034801480,\t0.234009962528944020,\t0.237317133694887160,\t0.240634419023990630,\t0.243961080908775330,\t0.247296508401632310,\t\n0.250640105456113820,\t0.253991369158029560,\t0.257349837571382520,\t0.260715119540691380,\t0.264086868613958360,\t0.267464816570281980,\t0.270848698914051060,\t0.274238351732492450,\t\n0.277633611112833020,\t0.281034380197525020,\t0.284440591931343080,\t0.287852220237255100,\t0.291269283741712570,\t0.294691801071166990,\t0.298119872808456420,\t0.301553562283515930,\t\n0.304993014782667160,\t0.308438356965780260,\t0.311889752745628360,\t0.315347377210855480,\t0.318811416625976560,\t0.322282072156667710,\t0.325759567320346830,\t0.329244095832109450,\t\n0.332735907286405560,\t0.336235217750072480,\t0.339742250740528110,\t0.343257248401641850,\t0.346780419349670410,\t0.350311983376741410,\t0.353852160274982450,\t0.357401121407747270,\t\n0.360959105193614960,\t0.364526227116584780,\t0.368102725595235820,\t0.371688675135374070,\t0.375284302979707720,\t0.378889638930559160,\t0.382504884153604510,\t0.386130042374134060,\t\n0.389765247702598570,\t0.393410529941320420,\t0.397065933793783190,\t0.400731507688760760,\t0.404407206922769550,\t0.408093083649873730,\t0.411789052188396450,\t0.415495119988918300,\t\n0.419211201369762420,\t0.422937240451574330,\t0.426673140376806260,\t0.430418811738491060,\t0.434174135327339170,\t0.437938995659351350,\t0.441713258624076840,\t0.445496778935194020,\t\n0.449289388954639430,\t0.453090950846672060,\t0.456901267170906070,\t0.460720170289278030,\t0.464547459036111830,\t0.468382950872182850,\t0.472226426005363460,\t0.476077698171138760,\t\n0.479936532676219940,\t0.483802750706672670,\t0.487676106393337250,\t0.491556398570537570,\t0.495443399995565410,\t0.499336875975131990,\t0.503236617892980580,\t0.507142387330532070,\t\n0.511053957045078280,\t0.514971107244491580,\t0.518893606960773470,\t0.522821225225925450,\t0.526753749698400500,\t0.530690938234329220,\t0.534632585942745210,\t0.538578454405069350,\t\n0.542528338730335240,\t0.546481993049383160,\t0.550439231097698210,\t0.554399792104959490,\t0.558363504707813260,\t0.562330115586519240,\t0.566299438476562500,\t0.570271246135234830,\t\n0.574245333671569820,\t0.578221492469310760,\t0.582199502736330030,\t0.586179181933403020,\t0.590160276740789410,\t0.594142623245716090,\t0.598125983029603960,\t0.602110169827938080,\t\n0.606094967573881150,\t0.610080175101757050,\t0.614065583795309070,\t0.618050977587699890,\t0.622036151587963100,\t0.626020893454551700,\t0.630004994571208950,\t0.633988231420516970,\t\n0.637970402836799620,\t0.641951277852058410,\t0.645930647850036620,\t0.649908289313316350,\t0.653883971273899080,\t0.657857488840818410,\t0.661828581243753430,\t0.665797054767608640,\t\n0.669762641191482540,\t0.673725124448537830,\t0.677684243768453600,\t0.681639779359102250,\t0.685591462999582290,\t0.689539063721895220,\t0.693482317030429840,\t0.697420965880155560,\t\n0.701354760676622390,\t0.705283410847187040,\t0.709206689149141310,\t0.713124278932809830,\t0.717035952955484390,\t0.720941375941038130,\t0.724840316921472550,\t0.728732451796531680,\t\n0.732617516070604320,\t0.736495196819305420,\t0.740365199744701390,\t0.744227230548858640,\t0.748080968856811520,\t0.751926124095916750,\t0.755762357264757160,\t0.759589381515979770,\t\n0.763406842947006230,\t0.767214450985193250,\t0.771011855453252790,\t0.774798732250928880,\t0.778574761003255840,\t0.782339565455913540,\t0.786092851310968400,\t0.789834223687648770,\t\n0.793563373386859890,\t0.797279909253120420,\t0.800983514636754990,\t0.804673787206411360,\t0.808350402861833570,\t0.812012966722249980,\t0.815661124885082240,\t0.819294504821300510,\t\n0.822912722826004030,\t0.826515413820743560,\t0.830102190375328060,\t0.833672653883695600,\t0.837226435542106630,\t0.840763118118047710,\t0.844282336533069610,\t0.847783654928207400,\t\n0.851266715675592420,\t0.854731071740388870,\t0.858176350593566890,\t0.861602116376161580,\t0.865007970482110980,\t0.868393491953611370,\t0.871758259832859040,\t0.875101849436759950,\t\n0.878423850983381270,\t0.881723806262016300,\t0.885001312941312790,\t0.888255912810564040,\t0.891487173736095430,\t0.894694659858942030,\t0.897877920418977740,\t0.901036512106657030,\t\n0.904169965535402300,\t0.907277844846248630,\t0.910359673202037810,\t0.913415014743804930,\t0.916443370282649990,\t0.919444311410188670,\t0.922417331486940380,\t0.925361987203359600,\t\n0.928277771919965740,\t0.931164238601922990,\t0.934020876884460450,\t0.936847217381000520,\t0.939642757177352910,\t0.942407000809907910,\t0.945139460265636440,\t0.947839632630348210,\t\n0.950507018715143200,\t0.953141096979379650,\t0.955741371959447860,\t0.958307322114706040,\t0.960838429629802700,\t0.963334184139966960,\t0.965794049203395840,\t0.968217510730028150,\t\n0.970604017376899720,\t0.972953058779239650,\t0.975264083594083790,\t0.977536566555500030,\t0.979769956320524220,\t0.981963708996772770,\t0.984117280691862110,\t0.986230112612247470,\t\n0.988301653414964680,\t0.990331344306468960,\t0.992318630218505860,\t0.994262944906950000,\t0.996163722127676010,\t0.998020399361848830,\t0.999832402914762500,\t1.001599155366420700,\t\n1.003320086747407900,\t1.004994612187147100,\t1.006622135639190700,\t1.008202098309993700,\t1.009733878076076500,\t1.011216927319765100,\t1.012650609016418500,\t1.014034371823072400,\t\n1.015367589890956900,\t1.016649682074785200,\t1.017880033701658200,\t1.019058048725128200,\t1.020183108747005500,\t1.021254621446132700,\t1.022271949797868700,\t1.023234523832798000,\t\n\n};\n/* ----------------------------------------------------------------------\n** Test input - logarithmic chirp signal\n** ------------------------------------------------------------------- */\n\nfloat32_t testInput_f32[320] =\n {\n 0.000000000000000061,\t0.002622410992047861,\t0.005253663973466970,\t0.007893770384930297,\t0.010542741395035495,\t0.013200587895525877,\t0.015867320496454066,\t0.018542949521290073,\t\n0.021227485001971542,\t0.023920936673895138,\t0.026623313970853074,\t0.029334626019908643,\t0.032054881636210709,\t0.034784089317753723,\t0.037522257240071598,\t0.040269393250875855,\t\n0.043025504864628375,\t0.045790599257054837,\t0.048564683259595690,\t0.051347763353792118,\t0.054139845665610427,\t0.056940935959702531,\t0.059751039633601337,\t0.062570161711849828,\t\n0.065398306840066575,\t0.068235479278943648,\t0.071081682898178900,\t0.073936921170339814,\t0.076801197164660218,\t0.079674513540768196,\t0.082556872542344922,\t0.085448275990715375,\t\n0.088348725278367082,\t0.091258221362398390,\t0.094176764757897533,\t0.097104355531246703,\t0.100040993293358240,\t0.102986677192832010,\t0.105941405909045980,\t0.108905177645166230,\t\n0.111877990121087980,\t0.114859840566297130,\t0.117850725712659680,\t0.120850641787131110,\t0.123859584504392860,\t0.126877549059407400,\t0.129904530119898690,\t0.132940521818751430,\t\n0.135985517746334080,\t0.139039510942737950,\t0.142102493889940090,\t0.145174458503884160,\t0.148255396126476810,\t0.151345297517508140,\t0.154444152846483080,\t0.157551951684374300,\t\n0.160668682995289720,\t0.163794335128054890,\t0.166928895807713030,\t0.170072352126936720,\t0.173224690537355760,\t0.176385896840798810,\t0.179555956180445340,\t0.182734853031894270,\t\n0.185922571194139130,\t0.189119093780459800,\t0.192324403209221870,\t0.195538481194587030,\t0.198761308737133020,\t0.201992866114384050,\t0.205233132871247170,\t0.208482087810360570,\t\n0.211739708982344370,\t0.215005973675965020,\t0.218280858408200220,\t0.221564338914212730,\t0.224856390137231970,\t0.228156986218334190,\t0.231466100486134670,\t0.234783705446379690,\t\n0.238109772771442410,\t0.241444273289723230,\t0.244787176974952890,\t0.248138452935395580,\t0.251498069402956710,\t0.254865993722190930,\t0.258242192339209860,\t0.261626630790492030,\t\n0.265019273691591620,\t0.268420084725748410,\t0.271829026632395280,\t0.275246061195565440,\t0.278671149232197430,\t0.282104250580339830,\t0.285545324087251580,\t0.288994327597401960,\t\n0.292451217940364990,\t0.295915950918612280,\t0.299388481295203350,\t0.302868762781368150,\t0.306356748023990040,\t0.309852388592980640,\t0.313355634968552230,\t0.316866436528383590,\t\n0.320384741534681720,\t0.323910497121136620,\t0.327443649279772870,\t0.330984142847692230,\t0.334531921493712690,\t0.338086927704900790,\t0.341649102772995210,\t0.345218386780727190,\t\n0.348794718588032520,\t0.352378035818156910,\t0.355968274843654950,\t0.359565370772282730,\t0.363169257432780890,\t0.366779867360555120,\t0.370397131783246010,\t0.374020980606193880,\t\n0.377651342397795690,\t0.381288144374756830,\t0.384931312387234990,\t0.388580770903877330,\t0.392236442996751310,\t0.395898250326170650,\t0.399566113125414350,\t0.403239950185338420,\t\n0.406919678838884410,\t0.410605214945482130,\t0.414296472875345100,\t0.417993365493664670,\t0.421695804144698540,\t0.425403698635752780,\t0.429116957221065130,\t0.432835486585582130,\t\n0.436559191828633180,\t0.440287976447505720,\t0.444021742320914510,\t0.447760389692375140,\t0.451503817153472210,\t0.455251921627031540,\t0.459004598350192470,\t0.462761740857380200,\t\n0.466523240963184150,\t0.470288988745136360,\t0.474058872526396560,\t0.477832778858340690,\t0.481610592503056990,\t0.485392196415748600,\t0.489177471727042850,\t0.492966297725213780,\t\n0.496758551838309250,\t0.500554109616195060,\t0.504352844712508190,\t0.508154628866524960,\t0.511959331884944910,\t0.515766821623591440,\t0.519576963969030530,\t0.523389622820107150,\t\n0.527204660069405030,\t0.531021935584629400,\t0.534841307189911630,\t0.538662630647041900,\t0.542485759636628150,\t0.546310545739186690,\t0.550136838416161340,\t0.553964484990880020,\t\n0.557793330629441700,\t0.561623218321546380,\t0.565453988861259300,\t0.569285480827721570,\t0.573117530565801950,\t0.576949972166696630,\t0.580782637448476910,\t0.584615355936589420,\t\n0.588447954844309340,\t0.592280259053150400,\t0.596112091093235260,\t0.599943271123626440,\t0.603773616912622660,\t0.607602943818024150,\t0.611431064767369080,\t0.615257790238142090,\t\n0.619082928237961740,\t0.622906284284749700,\t0.626727661386881850,\t0.630546860023327600,\t0.634363678123782030,\t0.638177911048790960,\t0.641989351569874020,\t0.645797789849653410,\t\n0.649603013421986450,\t0.653404807172108140,\t0.657202953316791350,\t0.660997231384523490,\t0.664787418195706640,\t0.668573287842887610,\t0.672354611671016960,\t0.676131158257749170,\t\n0.679902693393781730,\t0.683668980063242500,\t0.687429778424128110,\t0.691184845788802130,\t0.694933936604551380,\t0.698676802434213370,\t0.702413191936877570,\t0.706142850848662460,\t\n0.709865521963579990,\t0.713580945114492330,\t0.717288857154159800,\t0.720988991936399870,\t0.724681080297347790,\t0.728364850036839040,\t0.732040025899910680,\t0.735706329558433620,\t\n0.739363479592880620,\t0.743011191474238440,\t0.746649177546067850,\t0.750277147006723990,\t0.753894805891742180,\t0.757501857056394940,\t0.761098000158428880,\t0.764682931640995540,\t\n0.768256344715771980,\t0.771817929346292900,\t0.775367372231492210,\t0.778904356789468790,\t0.782428563141483460,\t0.785939668096195860,\t0.789437345134148760,\t0.792921264392515420,\t\n0.796391092650110770,\t0.799846493312681210,\t0.803287126398485760,\t0.806712648524170680,\t0.810122712890953390,\t0.813516969271127150,\t0.816895063994893090,\t0.820256639937531280,\t\n0.823601336506926020,\t0.826928789631450890,\t0.830238631748229430,\t0.833530491791779850,\t0.836803995183058700,\t0.840058763818912760,\t0.843294416061954100,\t0.846510566730867220,\t\n0.849706827091166740,\t0.852882804846411770,\t0.856038104129895340,\t0.859172325496819990,\t0.862285065916973510,\t0.865375918767918860,\t0.868444473828712590,\t0.871490317274166260,\t\n0.874513031669661770,\t0.877512195966544280,\t0.880487385498096800,\t0.883438171976119850,\t0.886364123488128100,\t0.889264804495180530,\t0.892139775830360640,\t0.894988594697921020,\t\n0.897810814673113080,\t0.900605985702712770,\t0.903373654106265470,\t0.906113362578062300,\t0.908824650189867690,\t0.911507052394417540,\t0.914160101029702910,\t0.916783324324059180,\t\n0.919376246902079860,\t0.921938389791372770,\t0.924469270430179120,\t0.926968402675872660,\t0.929435296814361430,\t0.931869459570409790,\t0.934270394118903560,\t0.936637600097074200,\t\n0.938970573617708970,\t0.941268807283364040,\t0.943531790201601380,\t0.945759008001275100,\t0.947949942849885320,\t0.950104073472023970,\t0.952220875168933280,\t0.954299819839202090,\t\n0.956340376000621160,\t0.958342008813221960,\t0.960304180103520260,\t0.962226348389994210,\t0.964107968909812760,\t0.965948493646846980,\t0.967747371360983650,\t0.969504047618768740,\t\n0.971217964825405680,\t0.972888562258134030,\t0.974515276101013520,\t0.976097539481141750,\t0.977634782506330400,\t0.979126432304266880,\t0.980571913063189360,\t0.981970646074102120,\t\n0.983322049774557390,\t0.984625539794035220,\t0.985880529000944810,\t0.987086427551279730,\t0.988242642938953360,\t0.989348580047844540,\t0.990403641205582440,\t0.991407226239099710,\t\n0.992358732531984260,\t0.993257555083659870,\t0.994103086570423680,\t0.994894717408374870,\t0.995631835818261310,\t0.996313827892278070,\t0.996940077662846650,\t0.997509967173408010,\t\n\n };\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_graphic_equalizer_example_q31.c\n*\n* Description: Example showing an audio graphic equalizer constructed\n* out of Biquad filters.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup GEQ5Band Graphic Audio Equalizer Example\n *\n * \\par Description:\n * \\par\n * This example demonstrates how a 5-band graphic equalizer can be constructed\n * using the Biquad cascade functions.\n * A graphic equalizer is used in audio applications to vary the tonal quality\n * of the audio.\n *\n * \\par Block Diagram:\n * \\par\n * The design is based on a cascade of 5 filter sections.\n * \\image html GEQ_signalflow.gif\n * Each filter section is 4th order and consists of a cascade of two Biquads.\n * Each filter has a nominal gain of 0 dB (1.0 in linear units) and\n * boosts or cuts signals within a specific frequency range.\n * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz.\n * Each band has an adjustable boost or cut in the range of +/- 9 dB.\n * For example, the band that extends from 500 to 2000 Hz has the response shown below:\n * \\par\n * \\image html GEQ_bandresponse.gif\n * \\par\n * With 1 dB steps, each filter has a total of 19 different settings.\n * The filter coefficients for all possible 19 settings were precomputed\n * in MATLAB and stored in a table. With 5 different tables, there are\n * a total of 5 x 19 = 95 different 4th order filters.\n * All 95 responses are shown below:\n * \\par\n * \\image html GEQ_allbandresponse.gif\n * \\par\n * Each 4th order filter has 10 coefficents for a grand total of 950 different filter\n * coefficients that must be tabulated. The input and output data is in Q31 format.\n * For better noise performance, the two low frequency bands are implemented using the high\n * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard\n * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp.\n * \\par\n * \\image html GEQ_inputchirp.gif\n * \\par\n * The array bandGains specifies the gain in dB to apply in each band.\n * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be:\n * \\par\n * \\image html GEQ_outputchirp.gif\n * \\par\n * \\note The output chirp signal follows the gain or boost of each band.\n * \\par\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32 points to the input data\n * \\li \\c testRefOutput_f32 points to the reference output data\n * \\li \\c testOutput points to the test output data\n * \\li \\c inputQ31 temporary input buffer\n * \\li \\c outputQ31 temporary output buffer\n * \\li \\c biquadStateBand1Q31 points to state buffer for band1\n * \\li \\c biquadStateBand2Q31 points to state buffer for band2\n * \\li \\c biquadStateBand3Q31 points to state buffer for band3\n * \\li \\c biquadStateBand4Q31 points to state buffer for band4\n * \\li \\c biquadStateBand5Q31 points to state buffer for band5\n * \\li \\c coeffTable points to coefficient buffer for all bands\n * \\li \\c gainDB gain buffer which has gains applied for all the bands\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_biquad_cas_df1_32x64_init_q31()\n * - arm_biquad_cas_df1_32x64_q31()\n * - arm_biquad_cascade_df1_init_q31()\n * - arm_biquad_cascade_df1_q31()\n * - arm_scale_q31()\n * - arm_scale_f32()\n * - arm_float_to_q31()\n * - arm_q31_to_float()\n *\n * Refer \n * \\link arm_graphic_equalizer_example_q31.c \\endlink\n *\n */\n\n\n/** \\example arm_graphic_equalizer_example_q31.c\n */\n\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n/* Length of the overall data in the test */\n#define TESTLENGTH 320\n\n/* Block size for the underlying processing */\n#define BLOCKSIZE 32\n\n/* Total number of blocks to run */\n#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)\n\n/* Number of 2nd order Biquad stages per filter */\n#define NUMSTAGES 2\n\n#define SNR_THRESHOLD_F32 98\n\n/* -------------------------------------------------------------------\n * External Declarations for Input and Output buffers\n * ------------------------------------------------------------------- */\n\nextern float32_t testInput_f32[TESTLENGTH];\nstatic float32_t testOutput[TESTLENGTH];\n\nextern float32_t testRefOutput_f32[TESTLENGTH];\n\n/* ----------------------------------------------------------------------\n** Q31 state buffers for Band1, Band2, Band3, Band4, Band5\n** ------------------------------------------------------------------- */\n\nstatic q63_t biquadStateBand1Q31[4 * 2];\nstatic q63_t biquadStateBand2Q31[4 * 2];\nstatic q31_t biquadStateBand3Q31[4 * 2];\nstatic q31_t biquadStateBand4Q31[4 * 2];\nstatic q31_t biquadStateBand5Q31[4 * 2];\n\n/* ----------------------------------------------------------------------\n** Q31 input and output buffers\n** ------------------------------------------------------------------- */\n\nq31_t inputQ31[BLOCKSIZE];\nq31_t outputQ31[BLOCKSIZE];\n\n/* ----------------------------------------------------------------------\n** Entire coefficient table. There are 10 coefficients per 4th order Biquad\n** cascade filter. The first 10 coefficients correspond to the -9 dB gain\n** setting of band 1; the next 10 coefficient correspond to the -8 dB gain\n** setting of band 1; and so on. There are 10*19=190 coefficients in total\n** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients\n** for band 2.\n**\n** The coefficients are in Q29 format and require a postShift of 2.\n** ------------------------------------------------------------------- */\n\nconst q31_t coeffTable[950] = {\n\n /* Band 1, -9 dB gain */\n 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981,\n /* Band 1, -8 dB gain */\n 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778,\n 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686,\n 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972,\n 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897,\n 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716,\n 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676,\n 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017,\n 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975,\n 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777,\n 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648,\n 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803,\n 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454,\n 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806,\n 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059,\n 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409,\n 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045,\n 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151,\n 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907,\n\n /* Band 2, -9 dB gain */\n 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,\n /* Band 2, -8 dB gain */\n 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122,\n 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090,\n 533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573,\n 534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887,\n 534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373,\n 535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399,\n 535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368,\n 536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724,\n 536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953,\n 537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588,\n 537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208,\n 538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437,\n 539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946,\n 539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450,\n 540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700,\n 540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484,\n 541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621,\n 542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956,\n 518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571,\n 520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158,\n 522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225,\n 524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221,\n 526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897,\n 528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319,\n 530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872,\n 532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254,\n 534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474,\n 536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839,\n 538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937,\n 540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621,\n 542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987,\n 544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351,\n 547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226,\n 549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298,\n 551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401,\n 553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495,\n 555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644,\n 494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750,\n 498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942,\n 503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028,\n 508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289,\n 512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811,\n 517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485,\n 522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012,\n 527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882,\n 531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352,\n 536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420,\n 541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786,\n 546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816,\n 551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495,\n 556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389,\n 562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597,\n 567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710,\n 572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767,\n 577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214,\n 583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865,\n 387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270,\n 401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316,\n 416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319,\n 431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540,\n 447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528,\n 464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141,\n 481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559,\n 499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296,\n 517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221,\n 536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566,\n 556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943,\n 577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360,\n 598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230,\n 620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383,\n 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077,\n 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004,\n 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294,\n 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515,\n 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673\n\n};\n\n/* ----------------------------------------------------------------------\n** Desired gains, in dB, per band\n** ------------------------------------------------------------------- */\n\nint gainDB[5] = {0, -3, 6, 4, -6};\n\nfloat32_t snr;\n\n\n/* ----------------------------------------------------------------------\n * Graphic equalizer Example\n * ------------------------------------------------------------------- */\n\nint32_t main(void)\n{\n float32_t *inputF32, *outputF32;\n arm_biquad_cas_df1_32x64_ins_q31 S1;\n arm_biquad_cas_df1_32x64_ins_q31 S2;\n arm_biquad_casd_df1_inst_q31 S3;\n arm_biquad_casd_df1_inst_q31 S4;\n arm_biquad_casd_df1_inst_q31 S5;\n int i;\n int32_t status;\n\n inputF32 = &testInput_f32[0];\n outputF32 = &testOutput[0];\n\n /* Initialize the state and coefficient buffers for all Biquad sections */\n\n arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES,\n (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],\n &biquadStateBand1Q31[0], 2);\n\n arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES,\n (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],\n &biquadStateBand2Q31[0], 2);\n\n arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES,\n (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],\n &biquadStateBand3Q31[0], 2);\n\n arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES,\n (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],\n &biquadStateBand4Q31[0], 2);\n\n arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES,\n (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],\n &biquadStateBand5Q31[0], 2);\n\n\n /* Call the process functions and needs to change filter coefficients\n for varying the gain of each band */\n\n for(i=0; i < NUMBLOCKS; i++)\n {\n\n /* ----------------------------------------------------------------------\n ** Convert block of input data from float to Q31\n ** ------------------------------------------------------------------- */\n\n arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n ** Scale down by 1/8. This provides additional headroom so that the\n ** graphic EQ can apply gain.\n ** ------------------------------------------------------------------- */\n\n arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2\n ** ------------------------------------------------------------------- */\n\n arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE);\n arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5\n ** ------------------------------------------------------------------- */\n\n arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE);\n arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);\n arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n ** Convert Q31 result back to float\n ** ------------------------------------------------------------------- */\n\n arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n ** Scale back up\n ** ------------------------------------------------------------------- */\n\n arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);\n };\n\n snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);\n\n if (snr < SNR_THRESHOLD_F32)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n else\n {\n status = ARM_MATH_SUCCESS;\n }\n\n /* ----------------------------------------------------------------------\n ** Loop here if the signal does not match the reference output.\n ** ------------------------------------------------------------------- */\n\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n/** \\endlink */\n\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_linear_interp_example\\arm_linear_interp_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_linear_interp_example_f32.c\n arm_linear_interp_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 12\n 0\n 0\n 0\n 0\n ..\\arm_linear_interp_data.c\n arm_linear_interp_data.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_linear_interp_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_linear_interp_example_f32.c\n 1\n ..\\arm_linear_interp_example_f32.c\n \n \n arm_linear_interp_data.c\n 1\n ..\\arm_linear_interp_data.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_linear_interp_example\\arm_linear_interp_example_f32.c\n \n \n \n \n 1\n 0\n 201\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_linear_interp_example\\arm_linear_interp_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_linear_interp_example_f32.c\n arm_linear_interp_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_linear_interp_data.c\n arm_linear_interp_data.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_linear_interp_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_linear_interp_example_f32.c\n 1\n ..\\arm_linear_interp_example_f32.c\n \n \n arm_linear_interp_data.c\n 1\n ..\\arm_linear_interp_data.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_linear_interp_example\\arm_linear_interp_example_f32.c\n \n \n \n \n 1\n 0\n 201\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_linear_interp_example\\arm_linear_interp_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_linear_interp_example_f32.c\n arm_linear_interp_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_linear_interp_data.c\n arm_linear_interp_data.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_linear_interp_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_linear_interp_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_linear_interp_example_f32.c\n 1\n ..\\arm_linear_interp_example_f32.c\n \n \n arm_linear_interp_data.c\n 1\n ..\\arm_linear_interp_data.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_linear_interp_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t \tarm_linear_interp_data.c\n* \n* Description:\t Data file used for example. Generation method described\n* below\n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n * -------------------------------------------------------------------- */\n \n/* ---------------------------------------------------------------------- \n* Table generated from following MATLAB Command\n* x = -pi: 0.00005 : (2*pi - 0.00005);\n* y = sin(x);\n* where pi value is 3.141592653589793\n* --------------------------------------------------------------------*/\n\nfloat arm_linear_interep_table[188495] = {\n\n\n-0.000000000000000122,\t-0.000049999999979173,\t-0.000099999999833667,\t-0.000149999999437717,\t-0.000199999998666767,\t-0.000249999997395817,\t-0.000299999995500311,\t-0.000349999992854362,\t\n-0.000399999989333412,\t-0.000449999984812462,\t-0.000499999979166956,\t-0.000549999972271007,\t-0.000599999964000057,\t-0.000649999954229107,\t-0.000699999942833602,\t-0.000749999929687653,\t\n-0.000799999914666704,\t-0.000849999897645755,\t-0.000899999878500250,\t-0.000949999857104302,\t-0.000999999833333354,\t-0.001049999807062851,\t-0.001099999778166904,\t-0.001149999746520957,\t\n-0.001199999712000011,\t-0.001249999674479510,\t-0.001299999633833566,\t-0.001349999589937622,\t-0.001399999542666680,\t-0.001449999491896183,\t-0.001499999437500243,\t-0.001549999379354304,\t\n-0.001599999317333367,\t-0.001649999251312876,\t-0.001699999181166942,\t-0.001749999106771011,\t-0.001799999028000082,\t-0.001849998944729599,\t-0.001899998856833675,\t-0.001949998764187754,\t\n-0.001999998666666836,\t-0.002049998564146365,\t-0.002099998456500453,\t-0.002149998343604546,\t-0.002199998225334087,\t-0.002249998101563188,\t-0.002299997972167294,\t-0.002349997837021405,\t\n-0.002399997696000966,\t-0.002449997548980088,\t-0.002499997395834216,\t-0.002549997236438351,\t-0.002599997070667937,\t-0.002649996898397086,\t-0.002699996719501243,\t-0.002749996533855408,\t\n-0.002799996341335026,\t-0.002849996141814208,\t-0.002899995935168401,\t-0.002949995721272604,\t-0.002999995500002261,\t-0.003049995271231486,\t-0.003099995034835722,\t-0.003149994790690415,\t\n-0.003199994538669677,\t-0.003249994278648952,\t-0.003299994010503243,\t-0.003349993734107991,\t-0.003399993449337312,\t-0.003449993156066649,\t-0.003499992854171003,\t-0.003549992543525819,\t\n-0.003599992224005209,\t-0.003649991895484619,\t-0.003699991557839049,\t-0.003749991210943944,\t-0.003799990854673418,\t-0.003849990488902914,\t-0.003899990113507434,\t-0.003949989728362423,\t\n-0.003999989333341993,\t-0.004049988928321590,\t-0.004099988513176658,\t-0.004149988087781312,\t-0.004199987652010995,\t-0.004249987205740709,\t-0.004299986748845899,\t-0.004349986281200678,\t\n-0.004399985802680492,\t-0.004449985313160341,\t-0.004499984812515671,\t-0.004549984300620594,\t-0.004599983777350557,\t-0.004649983242580561,\t-0.004699982696186050,\t-0.004749982138041138,\t\n-0.004799981568021272,\t-0.004849980986001451,\t-0.004899980391857122,\t-0.004949979785462398,\t-0.004999979166692725,\t-0.005049978535423547,\t-0.005099977891528979,\t-0.005149977234884466,\t\n-0.005199976565365011,\t-0.005249975882846058,\t-0.005299975187201721,\t-0.005349974478307446,\t-0.005399973756038235,\t-0.005449973020269535,\t-0.005499972270875456,\t-0.005549971507731448,\t\n-0.005599970730712511,\t-0.005649969939694091,\t-0.005699969134550302,\t-0.005749968315156590,\t-0.005799967481387958,\t-0.005849966633119851,\t-0.005899965770226383,\t-0.005949964892583000,\t\n-0.005999964000064706,\t-0.006049963092546945,\t-0.006099962169903833,\t-0.006149961232010816,\t-0.006199960278743339,\t-0.006249959309975518,\t-0.006299958325582797,\t-0.006349957325440182,\t\n-0.006399956309423117,\t-0.006449955277405718,\t-0.006499954229263430,\t-0.006549953164871257,\t-0.006599952084104644,\t-0.006649950986837708,\t-0.006699949872945895,\t-0.006749948742304206,\t\n-0.006799947594788089,\t-0.006849946430271660,\t-0.006899945248630365,\t-0.006949944049739206,\t-0.006999942833473632,\t-0.007049941599707755,\t-0.007099940348317025,\t-0.007149939079176889,\t\n-0.007199937792161461,\t-0.007249936487146187,\t-0.007299935164006074,\t-0.007349933822616566,\t-0.007399932462851779,\t-0.007449931084587162,\t-0.007499929687697716,\t-0.007549928272058891,\t\n-0.007599926837544801,\t-0.007649925384030893,\t-0.007699923911392173,\t-0.007749922419504085,\t-0.007799920908240749,\t-0.007849919377477610,\t-0.007899917827089672,\t-0.007949916256952384,\t\n-0.007999914666939863,\t-0.008049913056927554,\t-0.008099911426790906,\t-0.008149909776404035,\t-0.008199908105642390,\t-0.008249906414380975,\t-0.008299904702495238,\t-0.008349902969859295,\t\n-0.008399901216348595,\t-0.008449899441838141,\t-0.008499897646203384,\t-0.008549895829318437,\t-0.008599893991058752,\t-0.008649892131299332,\t-0.008699890249915625,\t-0.008749888346781748,\t\n-0.008799886421773151,\t-0.008849884474764837,\t-0.008899882505632256,\t-0.008949880514249525,\t-0.008999878500492093,\t-0.009049876464234965,\t-0.009099874405353590,\t-0.009149872323722084,\t\n-0.009199870219215898,\t-0.009249868091710479,\t-0.009299865941079948,\t-0.009349863767199750,\t-0.009399861569944894,\t-0.009449859349190827,\t-0.009499857104811669,\t-0.009549854836682867,\t\n-0.009599852544679429,\t-0.009649850228676803,\t-0.009699847888549109,\t-0.009749845524171793,\t-0.009799843135419864,\t-0.009849840722168771,\t-0.009899838284292632,\t-0.009949835821666898,\t\n-0.009999833334166574,\t-0.010049830821667110,\t-0.010099828284042626,\t-0.010149825721168572,\t-0.010199823132920397,\t-0.010249820519172219,\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}, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_linear_interp_example_f32.c\n*\n* Description: Example code demonstrating usage of sin function\n* and uses linear interpolation to get higher precision\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup LinearInterpExample Linear Interpolate Example\n *\n * CMSIS DSP Software Library -- Linear Interpolate Example \n *\n * Description \n * This example demonstrates usage of linear interpolate modules and fast math modules.\n * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses\n * linear interpolation function and results are compared to reference output.\n * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.\n *\n * \\par Block Diagram:\n * \\par\n * \\image html linearInterpExampleMethod1.gif \"Method 1: Sine caluclation using fast math\"\n * \\par\n * \\image html linearInterpExampleMethod2.gif \"Method 2: Sine caluclation using interpolation function\"\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInputSin_f32 points to the input values for sine calculation\n * \\li \\c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function\n * \\li \\c testOutput points to output buffer calculation from cubic interpolation\n * \\li \\c testLinIntOutput points to output buffer calculation from linear interpolation\n * \\li \\c snr1 Signal to noise ratio for reference and cubic interpolation output\n * \\li \\c snr2 Signal to noise ratio for reference and linear interpolation output\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_sin_f32()\n * - arm_linear_interp_f32()\n *\n * Refer \n * \\link arm_linear_interp_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_linear_interp_example_f32.c\n */\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n#define SNR_THRESHOLD 90\n#define TEST_LENGTH_SAMPLES 10\n#define XSPACING (0.00005f)\n\n/* ----------------------------------------------------------------------\n* Test input data for F32 SIN function\n* Generated by the MATLAB rand() function\n* randn('state', 0)\n* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));\n* --------------------------------------------------------------------*/\nfloat32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =\n{\n -0.649716504673081170, -2.501723745497831200,\n 0.188250329003310100, 0.432092748487532540,\n -1.722010988459680800, 1.788766476323060600,\n 1.786136060975809500, -0.056525543169408797,\n 0.491596272728153760, 0.262309671126153390\n};\n\n/*------------------------------------------------------------------------------\n* Reference out of SIN F32 function for Block Size = 10\n* Calculated from sin(testInputSin_f32)\n*------------------------------------------------------------------------------*/\nfloat32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =\n{\n -0.604960695383043530, -0.597090287967934840,\n 0.187140422442966500, 0.418772124875992690,\n -0.988588831792106880, 0.976338412038794010,\n 0.976903856413481100, -0.056495446835214236,\n 0.472033731854734240, 0.259311907228582830\n};\n\n/*------------------------------------------------------------------------------\n* Method 1: Test out Buffer Calculated from Cubic Interpolation\n*------------------------------------------------------------------------------*/\nfloat32_t testOutput[TEST_LENGTH_SAMPLES];\n\n/*------------------------------------------------------------------------------\n* Method 2: Test out buffer Calculated from Linear Interpolation\n*------------------------------------------------------------------------------*/\nfloat32_t testLinIntOutput[TEST_LENGTH_SAMPLES];\n\n/*------------------------------------------------------------------------------\n* External table used for linear interpolation\n*------------------------------------------------------------------------------*/\nextern float arm_linear_interep_table[188495];\n\n/* ----------------------------------------------------------------------\n* Global Variables for caluclating SNR's for Method1 & Method 2\n* ------------------------------------------------------------------- */\nfloat32_t snr1;\nfloat32_t snr2;\n\n/* ----------------------------------------------------------------------------\n* Calculation of Sine values from Cubic Interpolation and Linear interpolation\n* ---------------------------------------------------------------------------- */\nint32_t main(void)\n{\n uint32_t i;\n arm_status status;\n\n arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]};\n\n /*------------------------------------------------------------------------------\n * Method 1: Test out Calculated from Cubic Interpolation\n *------------------------------------------------------------------------------*/\n for(i=0; i< TEST_LENGTH_SAMPLES; i++)\n {\n testOutput[i] = arm_sin_f32(testInputSin_f32[i]);\n }\n\n /*------------------------------------------------------------------------------\n * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation\n *------------------------------------------------------------------------------*/\n\n for(i=0; i< TEST_LENGTH_SAMPLES; i++)\n {\n testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);\n }\n\n /*------------------------------------------------------------------------------\n * SNR calculation for method 1\n *------------------------------------------------------------------------------*/\n snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2);\n\n /*------------------------------------------------------------------------------\n * SNR calculation for method 2\n *------------------------------------------------------------------------------*/\n snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2);\n\n /*------------------------------------------------------------------------------\n * Initialise status depending on SNR calculations\n *------------------------------------------------------------------------------*/\n if( snr2 > snr1)\n {\n status = ARM_MATH_SUCCESS;\n }\n else\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n /* ----------------------------------------------------------------------\n ** Loop here if the signals fail the PASS check.\n ** This denotes a test failure\n ** ------------------------------------------------------------------- */\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 227\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n 1\n 0\n 230\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 174\n 230\n 0\n ..\\arm_matrix_example_f32.c\n arm_matrix_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_matrix_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_matrix_example_f32.c\n 1\n ..\\arm_matrix_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM3l_matrix_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 227\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n 1\n 0\n 230\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 174\n 230\n 0\n ..\\arm_matrix_example_f32.c\n arm_matrix_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM3l_matrix_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_matrix_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_matrix_example_f32.c\n 1\n ..\\arm_matrix_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM4lf_matrix_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 227\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n 1\n 0\n 230\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_matrix_example\\arm_matrix_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 174\n 230\n 0\n ..\\arm_matrix_example_f32.c\n arm_matrix_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 3\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 5\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM4lf_matrix_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_matrix_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_matrix_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_matrix_example_f32.c\n 1\n ..\\arm_matrix_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_matrix_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_matrix_example_f32.c\n*\n* Description: Example code demonstrating least square fit to data\n* using matrix functions\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup MatrixExample Matrix Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse\n * functions to apply least squares fitting to input data. Least squares fitting is\n * the procedure for finding the best-fitting curve that minimizes the sum of the\n * squares of the offsets (least square error) from a given set of data.\n *\n * \\par Algorithm:\n * \\par\n * The linear combination of parameters considered is as follows:\n * \\par\n * A * X = B, where \\c X is the unknown value and can be estimated\n * from \\c A & \\c B.\n * \\par\n * The least squares estimate \\c X is given by the following equation:\n * \\par\n * X = Inverse(AT * A) * AT * B\n *\n * \\par Block Diagram:\n * \\par\n * \\image html matrixExample.gif\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c A_f32 input matrix in the linear combination equation\n * \\li \\c B_f32 output matrix in the linear combination equation\n * \\li \\c X_f32 unknown matrix estimated using \\c A_f32 & \\c B_f32 matrices\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_mat_init_f32()\n * - arm_mat_trans_f32()\n * - arm_mat_mult_f32()\n * - arm_mat_inverse_f32()\n *\n * Refer \n * \\link arm_matrix_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_matrix_example_f32.c\n */\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n#define SNR_THRESHOLD 90\n\n/* --------------------------------------------------------------------------------\n* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize\n* and tapSize\n* --------------------------------------------------------------------------------- */\n\nconst float32_t B_f32[4] =\n{\n 782.0, 7577.0, 470.0, 4505.0\n};\n\n/* --------------------------------------------------------------------------------\n* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize\n* -------------------------------------------------------------------------------- */\n\nconst float32_t A_f32[16] =\n{\n /* Const, numTaps, blockSize, numTaps*blockSize */\n 1.0, 32.0, 4.0, 128.0,\n 1.0, 32.0, 64.0, 2048.0,\n 1.0, 16.0, 4.0, 64.0,\n 1.0, 16.0, 64.0, 1024.0,\n};\n\n\n/* ----------------------------------------------------------------------\n* Temporary buffers for storing intermediate values\n* ------------------------------------------------------------------- */\n/* Transpose of A Buffer */\nfloat32_t AT_f32[16];\n/* (Transpose of A * A) Buffer */\nfloat32_t ATMA_f32[16];\n/* Inverse(Transpose of A * A) Buffer */\nfloat32_t ATMAI_f32[16];\n/* Test Output Buffer */\nfloat32_t X_f32[4];\n\n/* ----------------------------------------------------------------------\n* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB\n* ------------------------------------------------------------------- */\nconst float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875};\n\nfloat32_t snr;\n\n\n/* ----------------------------------------------------------------------\n* Max magnitude FFT Bin test\n* ------------------------------------------------------------------- */\n\nint32_t main(void)\n{\n\n arm_matrix_instance_f32 A; /* Matrix A Instance */\n arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */\n arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */\n arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */\n arm_matrix_instance_f32 B; /* Matrix B instance */\n arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */\n\n uint32_t srcRows, srcColumns; /* Temporary variables */\n arm_status status;\n\n /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */\n srcRows = 4;\n srcColumns = 4;\n arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32);\n\n /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */\n srcRows = 4;\n srcColumns = 4;\n arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32);\n\n /* calculation of A transpose */\n status = arm_mat_trans_f32(&A, &AT);\n\n\n /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */\n srcRows = 4;\n srcColumns = 4;\n arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32);\n\n /* calculation of AT Multiply with A */\n status = arm_mat_mult_f32(&AT, &A, &ATMA);\n\n /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */\n srcRows = 4;\n srcColumns = 4;\n arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32);\n\n /* calculation of Inverse((Transpose(A) * A) */\n status = arm_mat_inverse_f32(&ATMA, &ATMAI);\n\n /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */\n status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA);\n\n /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */\n srcRows = 4;\n srcColumns = 1;\n arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);\n\n /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */\n srcRows = 4;\n srcColumns = 1;\n arm_mat_init_f32(&X, srcRows, srcColumns, X_f32);\n\n /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */\n status = arm_mat_mult_f32(&ATMA, &B, &X);\n\n /* Comparison of reference with test output */\n snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4);\n\n /*------------------------------------------------------------------------------\n * Initialise status depending on SNR calculations\n *------------------------------------------------------------------------------*/\n if( snr > SNR_THRESHOLD)\n {\n status = ARM_MATH_SUCCESS;\n }\n else\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n\n /* ----------------------------------------------------------------------\n ** Loop here if the signals fail the PASS check.\n ** This denotes a test failure\n ** ------------------------------------------------------------------- */\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 253\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n 1\n 0\n 256\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 200\n 256\n 0\n ..\\arm_signal_converge_example_f32.c\n arm_signal_converge_example_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_signal_converge_data.c\n arm_signal_converge_data.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_signal_converge_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_signal_converge_example_f32.c\n 1\n ..\\arm_signal_converge_example_f32.c\n \n \n arm_signal_converge_data.c\n 1\n ..\\arm_signal_converge_data.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 253\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n 1\n 0\n 256\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_signal_converge_data.c\n arm_signal_converge_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 200\n 256\n 0\n ..\\arm_signal_converge_example_f32.c\n arm_signal_converge_example_f32.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_signal_converge_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_signal_converge_data.c\n 1\n ..\\arm_signal_converge_data.c\n \n \n arm_signal_converge_example_f32.c\n 1\n ..\\arm_signal_converge_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 253\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n 1\n 0\n 256\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_signal_converge_example\\arm_signal_converge_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\arm_signal_converge_data.c\n arm_signal_converge_data.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 200\n 256\n 0\n ..\\arm_signal_converge_example_f32.c\n arm_signal_converge_example_f32.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\Source\\math_helper.c\n math_helper.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 4\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 6\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM4lf_signal_converge_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_signal_converge_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_signal_converge_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\Common\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_signal_converge_data.c\n 1\n ..\\arm_signal_converge_data.c\n \n \n arm_signal_converge_example_f32.c\n 1\n ..\\arm_signal_converge_example_f32.c\n \n \n math_helper.c\n 1\n ..\\..\\Common\\Source\\math_helper.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_signal_converge_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2012 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.0 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t \tarm_signal_converge_data.c\n* \n* Description:\t Test input data for Floating point LMS Norm FIR filter\n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\n** Test input data for Floating point LMS Norm FIR filter\n** Generated by the MATLAB randn() function\n** ------------------------------------------------------------------- */\n\nfloat32_t testInput_f32[1536] = \n{ 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----------------------------------------------------------------------\n** Coefficients for 32-tap filter for Floating point LMS FIR filter\n* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) \n** ------------------------------------------------------------------- */ \nfloat32_t lmsNormCoeff_f32[32] = {\n-0.004240,\t0.002301,\t0.008860,\t-0.000000,\t-0.019782,\t-0.010543,\t0.032881,\t0.034736,\t\n-0.037374,\t-0.069586,\t0.022397,\t0.102169,\t0.014185,\t-0.115908,\t-0.061648,\t0.101018,\t\n0.101018,\t-0.061648,\t-0.115908,\t0.014185,\t0.102169,\t0.022397,\t-0.069586,\t-0.037374,\t\n0.034736,\t0.032881,\t-0.010543,\t-0.019782,\t-0.000000,\t0.008860,\t0.002301,\t-0.004240\t\n\n};\n\n/* ----------------------------------------------------------------------\n** Coefficients for 32-tap filter for Floating point FIR filter\n* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) \n** ------------------------------------------------------------------- */ \nconst float32_t FIRCoeff_f32[32] = {\n0.004502,\t0.005074,\t0.006707,\t0.009356,\t0.012933,\t0.017303,\t0.022298,\t0.027717,\t\n0.033338,\t0.038930,\t0.044258,\t0.049098,\t0.053243,\t0.056519,\t0.058784,\t0.059941,\t\n0.059941,\t0.058784,\t0.056519,\t0.053243,\t0.049098,\t0.044258,\t0.038930,\t0.033338,\t\n0.027717,\t0.022298,\t0.017303,\t0.012933,\t0.009356,\t0.006707,\t0.005074,\t0.004502\n\n};\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_signal_converge_example_f32.c\n*\n* Description: Example code demonstrating convergence of an adaptive\n* filter.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup SignalConvergence Signal Convergence Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the ability of an adaptive filter to \"learn\" the transfer function of\n * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse\n * Response (FIR) Filter, and Basic Math Functions.\n *\n * \\par Algorithm:\n * \\par\n * The figure below illustrates the signal flow in this example. Uniformly distributed white\n * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the\n * reference input of the adaptive filter (normalized LMS filter). The white noise is input\n * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter.\n * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and\n * (2) the error signal which is the difference between the adaptive filter and the reference\n * output of the FIR filter. Over time as the adaptive filter learns the transfer function\n * of the FIR filter, the first output approaches the reference output of the FIR filter,\n * and the error signal approaches zero.\n * \\par\n * The adaptive filter converges properly even if the input signal has a large dynamic\n * range (i.e., varies from small to large values). The coefficients of the adaptive filter\n * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge()\n * implements the stopping condition. The function checks if all of the values of the error signal have a\n * magnitude below a threshold DELTA.\n *\n * \\par Block Diagram:\n * \\par\n * \\image html SignalFlow.gif\n *\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32 points to the input data\n * \\li \\c firStateF32 points to FIR state buffer\n * \\li \\c lmsStateF32 points to Normalised Least mean square FIR filter state buffer\n * \\li \\c FIRCoeff_f32 points to coefficient buffer\n * \\li \\c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer\n * \\li \\c wire1, wir2, wire3 temporary buffers\n * \\li \\c errOutput, err_signal temporary error buffers\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_lms_norm_init_f32()\n * - arm_fir_init_f32()\n * - arm_fir_f32()\n * - arm_lms_norm_f32()\n * - arm_scale_f32()\n * - arm_abs_f32()\n * - arm_sub_f32()\n * - arm_min_f32()\n * - arm_copy_f32()\n *\n * Refer \n * \\link arm_signal_converge_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_signal_converge_example_f32.c\n */\n\n#include \"arm_math.h\"\n#include \"math_helper.h\"\n\n/* ----------------------------------------------------------------------\n** Global defines for the simulation\n* ------------------------------------------------------------------- */\n\n#define TEST_LENGTH_SAMPLES 1536\n#define NUMTAPS 32\n#define BLOCKSIZE 32\n#define DELTA_ERROR 0.000001f\n#define DELTA_COEFF 0.0001f\n#define MU 0.5f\n\n#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE)\n\n/* ----------------------------------------------------------------------\n* Declare FIR state buffers and structure\n* ------------------------------------------------------------------- */\n\nfloat32_t firStateF32[NUMTAPS + BLOCKSIZE];\narm_fir_instance_f32 LPF_instance;\n\n/* ----------------------------------------------------------------------\n* Declare LMSNorm state buffers and structure\n* ------------------------------------------------------------------- */\n\nfloat32_t lmsStateF32[NUMTAPS + BLOCKSIZE];\nfloat32_t errOutput[TEST_LENGTH_SAMPLES];\narm_lms_norm_instance_f32 lmsNorm_instance;\n\n\n/* ----------------------------------------------------------------------\n* Function Declarations for Signal Convergence Example\n* ------------------------------------------------------------------- */\n\narm_status test_signal_converge_example( void );\n\n\n/* ----------------------------------------------------------------------\n* Internal functions\n* ------------------------------------------------------------------- */\narm_status test_signal_converge(float32_t* err_signal,\n uint32_t blockSize);\n\nvoid getinput(float32_t* input,\n uint32_t fr_cnt,\n uint32_t blockSize);\n\n/* ----------------------------------------------------------------------\n* External Declarations for FIR F32 module Test\n* ------------------------------------------------------------------- */\nextern float32_t testInput_f32[TEST_LENGTH_SAMPLES];\nextern float32_t lmsNormCoeff_f32[32];\nextern const float32_t FIRCoeff_f32[32];\nextern arm_lms_norm_instance_f32 lmsNorm_instance;\n\n/* ----------------------------------------------------------------------\n* Declare I/O buffers\n* ------------------------------------------------------------------- */\n\nfloat32_t wire1[BLOCKSIZE];\nfloat32_t wire2[BLOCKSIZE];\nfloat32_t wire3[BLOCKSIZE];\nfloat32_t err_signal[BLOCKSIZE];\n\n/* ----------------------------------------------------------------------\n* Signal converge test\n* ------------------------------------------------------------------- */\n\nint32_t main(void)\n{\n uint32_t i;\n arm_status status;\n uint32_t index;\n float32_t minValue;\n\n /* Initialize the LMSNorm data structure */\n arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE);\n\n /* Initialize the FIR data structure */\n arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE);\n\n /* ----------------------------------------------------------------------\n * Loop over the frames of data and execute each of the processing\n * functions in the system.\n * ------------------------------------------------------------------- */\n\n for(i=0; i < NUMFRAMES; i++)\n {\n /* Read the input data - uniformly distributed random noise - into wire1 */\n arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE);\n\n /* Execute the FIR processing function. Input wire1 and output wire2 */\n arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE);\n\n /* Execute the LMS Norm processing function*/\n\n arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */\n wire1, /* Input signal */\n wire2, /* Reference Signal */\n wire3, /* Converged Signal */\n err_signal, /* Error Signal, this will become small as the signal converges */\n BLOCKSIZE); /* BlockSize */\n\n /* apply overall gain */\n arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */\n }\n\n status = ARM_MATH_SUCCESS;\n\n /* -------------------------------------------------------------------------------\n * Test whether the error signal has reached towards 0.\n * ----------------------------------------------------------------------------- */\n\n arm_abs_f32(err_signal, err_signal, BLOCKSIZE);\n arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index);\n\n if (minValue > DELTA_ERROR)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n /* ----------------------------------------------------------------------\n * Test whether the filter coefficients have converged.\n * ------------------------------------------------------------------- */\n\n arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);\n\n arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);\n arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index);\n\n if (minValue > DELTA_COEFF)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n /* ----------------------------------------------------------------------\n * Loop here if the signals did not pass the convergence check.\n * This denotes a test failure\n * ------------------------------------------------------------------- */\n\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 153\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n 1\n 0\n 158\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 102\n 158\n 0\n ..\\arm_sin_cos_example_f32.c\n arm_sin_cos_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_sin_cos_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_sin_cos_example_f32.c\n 1\n ..\\arm_sin_cos_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 153\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n 1\n 0\n 158\n 1\n
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\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 102\n 158\n 0\n ..\\arm_sin_cos_example_f32.c\n arm_sin_cos_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_sin_cos_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_sin_cos_example_f32.c\n 1\n ..\\arm_sin_cos_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 153\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n 1\n 0\n 158\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_sin_cos_example\\arm_sin_cos_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 102\n 158\n 0\n ..\\arm_sin_cos_example_f32.c\n arm_sin_cos_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_sin_cos_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_sin_cos_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_sin_cos_example_f32.c\n 1\n ..\\arm_sin_cos_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_sin_cos_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_sin_cos_example_f32.c\n*\n* Description: Example code demonstrating sin and cos calculation of input signal.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup SinCosExample SineCosine Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector\n * Multiplication, and Vector Addition functions.\n *\n * \\par Algorithm:\n * \\par\n * Mathematically, the Pythagorean trignometric identity is defined by the following equation:\n * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
\n * where \\c x is the angle in radians.\n *\n * \\par Block Diagram:\n * \\par\n * \\image html sinCos.gif\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32 array of input angle in radians\n * \\li \\c testOutput stores sum of the squares of sine and cosine values of input angle\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_cos_f32()\n * - arm_sin_f32()\n * - arm_mult_f32()\n * - arm_add_f32()\n *\n * Refer \n * \\link arm_sin_cos_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_sin_cos_example_f32.c\n */\n\n#include \n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\n* Defines each of the tests performed\n* ------------------------------------------------------------------- */\n#define MAX_BLOCKSIZE 32\n#define DELTA (0.000001f)\n\n\n/* ----------------------------------------------------------------------\n* Test input data for Floating point sin_cos example for 32-blockSize\n* Generated by the MATLAB randn() function\n* ------------------------------------------------------------------- */\n\nconst float32_t testInput_f32[MAX_BLOCKSIZE] =\n{\n -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680,\n 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040,\n 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800,\n -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800\n\n\n};\n\nconst float32_t testRefOutput_f32 = 1.000000000;\n\n/* ----------------------------------------------------------------------\n* Declare Global variables\n* ------------------------------------------------------------------- */\nuint32_t blockSize = 32;\nfloat32_t testOutput;\nfloat32_t cosOutput;\nfloat32_t sinOutput;\nfloat32_t cosSquareOutput;\nfloat32_t sinSquareOutput;\n\n/* ----------------------------------------------------------------------\n* Max magnitude FFT Bin test\n* ------------------------------------------------------------------- */\n\narm_status status;\n\nint32_t main(void)\n{\n float32_t diff;\n uint32_t i;\n\n for(i=0; i< blockSize; i++)\n {\n cosOutput = arm_cos_f32(testInput_f32[i]);\n sinOutput = arm_sin_f32(testInput_f32[i]);\n\n arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1);\n arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1);\n\n arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);\n\n /* absolute value of difference between ref and test */\n diff = fabsf(testRefOutput_f32 - testOutput);\n\n /* Comparison of sin_cos value with reference */\n if(diff > DELTA)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n if( status == ARM_MATH_TEST_FAILURE)\n {\n while(1);\n }\n\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n 1\n 0\n 201\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_variance_example_f32.c\n arm_variance_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n startup_ARMCM0.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM0.c\n system_ARMCM0.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n arm_cortexM0l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM0l_variance_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_variance_example_f32.c\n 1\n ..\\arm_variance_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM0.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM0.s\n \n \n system_ARMCM0.c\n 1\n ..\\..\\Common\\system_ARMCM0.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM0l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM0l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n 1\n 0\n 201\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_variance_example_f32.c\n arm_variance_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n startup_ARMCM3.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM3.c\n system_ARMCM3.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n arm_cortexM3l_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM3l_variance_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM3\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_variance_example_f32.c\n 1\n ..\\arm_variance_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM3.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM3.s\n \n \n system_ARMCM3.c\n 1\n ..\\..\\Common\\system_ARMCM3.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM3l_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM3l_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n Target 1\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\debug\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n 0\n DLGDARM\n (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)\n \n \n 0\n ARMDBGFLAGS\n -T0\n \n \n \n \n 0\n 0\n 198\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n 1\n 0\n 201\n 1\n
0
\n 0\n 0\n 0\n 0\n 0\n 0\n C:\\CMSIS\\CMSIS_Setup\\CMSIS\\DSP_Lib\\Examples\\arm_variance_example\\arm_variance_example_f32.c\n \n \n \n \n \n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n Source Group 1\n 1\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 145\n 201\n 0\n ..\\arm_variance_example_f32.c\n arm_variance_example_f32.c\n 0\n 0\n \n \n\n \n CMSIS Device\n 1\n 0\n 0\n 0\n \n 2\n 2\n 2\n 0\n 0\n 0\n 0\n 124\n 139\n 0\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n startup_ARMCM4.s\n 0\n 0\n \n \n 2\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\Common\\system_ARMCM4.c\n system_ARMCM4.c\n 0\n 0\n \n \n\n \n CMSIS DSP_Library\n 1\n 0\n 0\n 0\n \n 3\n 4\n 4\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n arm_cortexM4lf_math.lib\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n Target 1\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\debug\\\n arm_cortexM4lf_variance_example\n 1\n 0\n 0\n 1\n 1\n .\\debug\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 1\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n .\\arm_variance_example.ini\n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n \n \n ARM_MATH_CM4, __FPU_PRESENT = 1\n \n ..\\..\\..\\..\\Include;..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n Source Group 1\n \n \n arm_variance_example_f32.c\n 1\n ..\\arm_variance_example_f32.c\n \n \n \n \n CMSIS Device\n \n \n startup_ARMCM4.s\n 2\n ..\\..\\Common\\ARM\\startup_ARMCM4.s\n \n \n system_ARMCM4.c\n 1\n ..\\..\\Common\\system_ARMCM4.c\n \n \n \n \n CMSIS DSP_Library\n \n \n arm_cortexM4lf_math.lib\n 4\n ..\\..\\..\\..\\Lib\\ARM\\arm_cortexM4lf_math.lib\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini", "content": "\n/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions\n\n The file can be executed in the following way:\n 1) manually from uVision command window (in debug mode) using command:\n INCLUIDE arm_variance_example.ini\n\n*/\n\n\n// usual initialisation for target setup\nMAP 0x00000000, 0x0003FFFF EXEC READ // 256K Flash\nMAP 0x20000000, 0x20007FFF READ WRITE // 32K RAM\n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c", "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2012 ARM Limited. All rights reserved.\n*\n* $Date: 17. January 2013\n* $Revision: V1.4.0\n*\n* Project: CMSIS DSP Library\n* Title: arm_variance_example_f32.c\n*\n* Description: Example code demonstrating variance calculation of input sequence.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the\n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n/**\n * @ingroup groupExamples\n */\n\n/**\n * @defgroup VarianceExample Variance Example\n *\n * \\par Description:\n * \\par\n * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an\n * input sequence with N samples. Uniformly distributed white noise is taken as input.\n *\n * \\par Algorithm:\n * \\par\n * The variance of a sequence is the mean of the squared deviation of the sequence from its mean.\n * \\par\n * This is denoted by the following equation:\n * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
\n * where, x[n] is the input sequence, N is the number of input samples, and\n * x' is the mean value of the input sequence, x[n].\n * \\par\n * The mean value x' is defined as:\n * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
\n *\n * \\par Block Diagram:\n * \\par\n * \\image html Variance.gif\n *\n *\n * \\par Variables Description:\n * \\par\n * \\li \\c testInput_f32 points to the input data\n * \\li \\c wire1, \\c wir2, \\c wire3 temporary buffers\n * \\li \\c blockSize number of samples processed at a time\n * \\li \\c refVarianceOut reference variance value\n *\n * \\par CMSIS DSP Software Library Functions Used:\n * \\par\n * - arm_dot_prod_f32()\n * - arm_mult_f32()\n * - arm_sub_f32()\n * - arm_fill_f32()\n * - arm_copy_f32()\n *\n * Refer \n * \\link arm_variance_example_f32.c \\endlink\n *\n */\n\n\n/** \\example arm_variance_example_f32.c\n */\n#include \n#include \"arm_math.h\"\n\n/* ----------------------------------------------------------------------\n* Defines each of the tests performed\n* ------------------------------------------------------------------- */\n#define MAX_BLOCKSIZE 32\n#define DELTA (0.000001f)\n\n\n/* ----------------------------------------------------------------------\n* Declare I/O buffers\n* ------------------------------------------------------------------- */\nfloat32_t wire1[MAX_BLOCKSIZE];\nfloat32_t wire2[MAX_BLOCKSIZE];\nfloat32_t wire3[MAX_BLOCKSIZE];\n\n/* ----------------------------------------------------------------------\n* Test input data for Floating point Variance example for 32-blockSize\n* Generated by the MATLAB randn() function\n* ------------------------------------------------------------------- */\n\nfloat32_t testInput_f32[32] =\n{\n -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549,\n -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318,\n 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303,\n -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810,\n 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022,\n 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271,\n -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477,\n -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345\n\n};\n\n/* ----------------------------------------------------------------------\n* Declare Global variables\n* ------------------------------------------------------------------- */\nuint32_t blockSize = 32;\nfloat32_t refVarianceOut = 0.903941793931839;\n\n/* ----------------------------------------------------------------------\n* Variance calculation test\n* ------------------------------------------------------------------- */\n\nint32_t main(void)\n{\n arm_status status;\n float32_t mean, oneByBlockSize;\n float32_t variance;\n float32_t diff;\n\n status = ARM_MATH_SUCCESS;\n\n /* Calculation of mean value of input */\n\n /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */\n\n /* Fill wire1 buffer with 1.0 value */\n arm_fill_f32(1.0, wire1, blockSize);\n\n /* Calculate the dot product of wire1 and wire2 */\n /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */\n arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);\n\n /* Calculation of 1/blockSize */\n oneByBlockSize = 1.0 / (blockSize);\n\n /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */\n arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);\n\n\n /* Calculation of variance value of input */\n\n /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */\n\n /* Fill wire2 with mean value x' */\n arm_fill_f32(mean, wire2, blockSize);\n\n /* wire3 contains (x-x') */\n arm_sub_f32(testInput_f32, wire2, wire3, blockSize);\n\n /* wire2 contains (x-x') */\n arm_copy_f32(wire3, wire2, blockSize);\n\n /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */\n arm_dot_prod_f32(wire2, wire3, blockSize, &variance);\n\n /* Calculation of 1/blockSize */\n oneByBlockSize = 1.0 / (blockSize - 1);\n\n /* Calculation of variance */\n arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);\n\n /* absolute value of difference between ref and test */\n diff = fabsf(refVarianceOut - variance);\n\n /* Comparison of variance value with reference */\n if(diff > DELTA)\n {\n status = ARM_MATH_TEST_FAILURE;\n }\n\n if( status != ARM_MATH_SUCCESS)\n {\n while(1);\n }\n\n while(1); /* main function does not return */\n}\n\n /** \\endlink */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n DSP_Lib CM0 LE\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM0 LE O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n 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0\n 0\n 0\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n arm_mat_trans_q15.c\n 0\n 0\n \n \n 5\n 177\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n arm_mat_trans_q31.c\n 0\n 0\n \n \n\n \n TransformFunctions\n 0\n 0\n 0\n 0\n \n 6\n 178\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_bitreversal.c\n arm_bitreversal.c\n 0\n 0\n \n \n 6\n 179\n 2\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_bitreversal2.S\n arm_bitreversal2.S\n 0\n 0\n \n \n 6\n 180\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_f32.c\n arm_cfft_f32.c\n 0\n 0\n \n \n 6\n 181\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n arm_cfft_radix2_f32.c\n 0\n 0\n \n \n 6\n 182\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n arm_cfft_radix2_init_f32.c\n 0\n 0\n \n \n 6\n 183\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n arm_cfft_radix2_init_q15.c\n 0\n 0\n \n \n 6\n 184\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n arm_cfft_radix2_init_q31.c\n 0\n 0\n \n \n 6\n 185\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n arm_cfft_radix2_q15.c\n 0\n 0\n \n \n 6\n 186\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n arm_cfft_radix2_q31.c\n 0\n 0\n \n \n 6\n 187\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n arm_cfft_radix4_f32.c\n 0\n 0\n \n \n 6\n 188\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n arm_cfft_radix4_init_f32.c\n 0\n 0\n \n \n 6\n 189\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n arm_cfft_radix4_init_q15.c\n 0\n 0\n \n \n 6\n 190\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n arm_cfft_radix4_init_q31.c\n 0\n 0\n \n \n 6\n 191\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n arm_cfft_radix4_q15.c\n 0\n 0\n \n \n 6\n 192\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n arm_cfft_radix4_q31.c\n 0\n 0\n \n \n 6\n 193\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n arm_cfft_radix8_f32.c\n 0\n 0\n \n \n 6\n 194\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_f32.c\n arm_dct4_f32.c\n 0\n 0\n \n \n 6\n 195\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n arm_dct4_init_f32.c\n 0\n 0\n \n \n 6\n 196\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n arm_dct4_init_q15.c\n 0\n 0\n \n \n 6\n 197\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n arm_dct4_init_q31.c\n 0\n 0\n \n \n 6\n 198\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_q15.c\n arm_dct4_q15.c\n 0\n 0\n \n \n 6\n 199\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_dct4_q31.c\n arm_dct4_q31.c\n 0\n 0\n \n \n 6\n 200\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_f32.c\n arm_rfft_f32.c\n 0\n 0\n \n \n 6\n 201\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n arm_rfft_fast_f32.c\n 0\n 0\n \n \n 6\n 202\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n arm_rfft_fast_init_f32.c\n 0\n 0\n \n \n 6\n 203\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n arm_rfft_init_f32.c\n 0\n 0\n \n \n 6\n 204\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n arm_rfft_init_q15.c\n 0\n 0\n \n \n 6\n 205\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n arm_rfft_init_q31.c\n 0\n 0\n \n \n 6\n 206\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_q15.c\n arm_rfft_q15.c\n 0\n 0\n \n \n 6\n 207\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_q31.c\n arm_rfft_q31.c\n 0\n 0\n \n \n\n \n ControllerFunctions\n 0\n 0\n 0\n 0\n \n 7\n 208\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n arm_pid_init_f32.c\n 0\n 0\n \n \n 7\n 209\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n arm_pid_init_q15.c\n 0\n 0\n \n \n 7\n 210\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n arm_pid_init_q31.c\n 0\n 0\n \n \n 7\n 211\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n arm_pid_reset_f32.c\n 0\n 0\n \n \n 7\n 212\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n arm_pid_reset_q15.c\n 0\n 0\n \n \n 7\n 213\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n arm_pid_reset_q31.c\n 0\n 0\n \n \n 7\n 214\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n arm_sin_cos_f32.c\n 0\n 0\n \n \n 7\n 215\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n arm_sin_cos_q31.c\n 0\n 0\n \n \n\n \n StatisticsFunctions\n 0\n 0\n 0\n 0\n \n 8\n 216\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_f32.c\n arm_max_f32.c\n 0\n 0\n \n \n 8\n 217\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q7.c\n arm_max_q7.c\n 0\n 0\n \n \n 8\n 218\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q15.c\n arm_max_q15.c\n 0\n 0\n \n \n 8\n 219\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q31.c\n arm_max_q31.c\n 0\n 0\n \n \n 8\n 220\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_f32.c\n arm_mean_f32.c\n 0\n 0\n \n \n 8\n 221\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q7.c\n arm_mean_q7.c\n 0\n 0\n \n \n 8\n 222\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q15.c\n arm_mean_q15.c\n 0\n 0\n \n \n 8\n 223\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q31.c\n arm_mean_q31.c\n 0\n 0\n \n \n 8\n 224\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_f32.c\n arm_min_f32.c\n 0\n 0\n \n \n 8\n 225\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q7.c\n arm_min_q7.c\n 0\n 0\n \n \n 8\n 226\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q15.c\n arm_min_q15.c\n 0\n 0\n \n \n 8\n 227\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q31.c\n arm_min_q31.c\n 0\n 0\n \n \n 8\n 228\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_f32.c\n arm_power_f32.c\n 0\n 0\n \n \n 8\n 229\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q7.c\n arm_power_q7.c\n 0\n 0\n \n \n 8\n 230\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q15.c\n arm_power_q15.c\n 0\n 0\n \n \n 8\n 231\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q31.c\n arm_power_q31.c\n 0\n 0\n \n \n 8\n 232\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_f32.c\n arm_rms_f32.c\n 0\n 0\n \n \n 8\n 233\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q15.c\n arm_rms_q15.c\n 0\n 0\n \n \n 8\n 234\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q31.c\n arm_rms_q31.c\n 0\n 0\n \n \n 8\n 235\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_f32.c\n arm_std_f32.c\n 0\n 0\n \n \n 8\n 236\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q15.c\n arm_std_q15.c\n 0\n 0\n \n \n 8\n 237\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q31.c\n arm_std_q31.c\n 0\n 0\n \n \n 8\n 238\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_f32.c\n arm_var_f32.c\n 0\n 0\n \n \n 8\n 239\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q15.c\n arm_var_q15.c\n 0\n 0\n \n \n 8\n 240\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q31.c\n arm_var_q31.c\n 0\n 0\n \n \n\n \n SupportFunctions\n 0\n 0\n 0\n 0\n \n 9\n 241\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_f32.c\n arm_copy_f32.c\n 0\n 0\n \n \n 9\n 242\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q7.c\n arm_copy_q7.c\n 0\n 0\n \n \n 9\n 243\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q15.c\n arm_copy_q15.c\n 0\n 0\n \n \n 9\n 244\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q31.c\n arm_copy_q31.c\n 0\n 0\n \n \n 9\n 245\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_f32.c\n arm_fill_f32.c\n 0\n 0\n \n \n 9\n 246\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q7.c\n arm_fill_q7.c\n 0\n 0\n \n \n 9\n 247\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q15.c\n arm_fill_q15.c\n 0\n 0\n \n \n 9\n 248\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q31.c\n arm_fill_q31.c\n 0\n 0\n \n \n 9\n 249\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q7.c\n arm_float_to_q7.c\n 0\n 0\n \n \n 9\n 250\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q15.c\n arm_float_to_q15.c\n 0\n 0\n \n \n 9\n 251\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q31.c\n arm_float_to_q31.c\n 0\n 0\n \n \n 9\n 252\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_float.c\n arm_q7_to_float.c\n 0\n 0\n \n \n 9\n 253\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q15.c\n arm_q7_to_q15.c\n 0\n 0\n \n \n 9\n 254\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q31.c\n arm_q7_to_q31.c\n 0\n 0\n \n \n 9\n 255\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_float.c\n arm_q15_to_float.c\n 0\n 0\n \n \n 9\n 256\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q7.c\n arm_q15_to_q7.c\n 0\n 0\n \n \n 9\n 257\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q31.c\n arm_q15_to_q31.c\n 0\n 0\n \n \n 9\n 258\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_float.c\n arm_q31_to_float.c\n 0\n 0\n \n \n 9\n 259\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q7.c\n arm_q31_to_q7.c\n 0\n 0\n \n \n 9\n 260\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q15.c\n arm_q31_to_q15.c\n 0\n 0\n \n \n\n \n CommonTables\n 0\n 0\n 0\n 0\n \n 10\n 261\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\CommonTables\\arm_common_tables.c\n arm_common_tables.c\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n DSP_Lib CM0 LE\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM0l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM0'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM0 LE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM0l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM0'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM0 BE\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM0b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING,ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM0'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM0 BE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M0\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n \n \n \n 4803\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM0b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DARMCM1.DLL\n -pCM0\n SARMCM3.DLL\n \n TARMCM1.DLL\n -pCM0\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M0\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING,ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM0'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n DSP_Lib CM3 LE\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM3 LE O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM3 BE\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM3 BE O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n BasicMathFunctions\n 0\n 0\n 0\n 0\n \n 1\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_f32.c\n arm_abs_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q7.c\n arm_abs_q7.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q15.c\n arm_abs_q15.c\n 0\n 0\n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q31.c\n arm_abs_q31.c\n 0\n 0\n \n \n 1\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_f32.c\n arm_add_f32.c\n 0\n 0\n \n \n 1\n 6\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q7.c\n arm_add_q7.c\n 0\n 0\n \n \n 1\n 7\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q15.c\n arm_add_q15.c\n 0\n 0\n \n \n 1\n 8\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q31.c\n arm_add_q31.c\n 0\n 0\n \n \n 1\n 9\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n arm_dot_prod_f32.c\n 0\n 0\n \n \n 1\n 10\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n arm_dot_prod_q7.c\n 0\n 0\n \n \n 1\n 11\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n arm_dot_prod_q15.c\n 0\n 0\n \n \n 1\n 12\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n arm_dot_prod_q31.c\n 0\n 0\n \n \n 1\n 13\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_mult_f32.c\n arm_mult_f32.c\n 0\n 0\n \n \n 1\n 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0\n \n \n 6\n 200\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_f32.c\n arm_rfft_f32.c\n 0\n 0\n \n \n 6\n 201\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n arm_rfft_fast_f32.c\n 0\n 0\n \n \n 6\n 202\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n arm_rfft_fast_init_f32.c\n 0\n 0\n \n \n 6\n 203\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n arm_rfft_init_f32.c\n 0\n 0\n \n \n 6\n 204\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n arm_rfft_init_q15.c\n 0\n 0\n \n \n 6\n 205\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n arm_rfft_init_q31.c\n 0\n 0\n \n \n 6\n 206\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_q15.c\n arm_rfft_q15.c\n 0\n 0\n \n \n 6\n 207\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\TransformFunctions\\arm_rfft_q31.c\n arm_rfft_q31.c\n 0\n 0\n \n \n\n \n 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arm_sin_cos_q31.c\n 0\n 0\n \n \n\n \n StatisticsFunctions\n 0\n 0\n 0\n 0\n \n 8\n 216\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_f32.c\n arm_max_f32.c\n 0\n 0\n \n \n 8\n 217\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q7.c\n arm_max_q7.c\n 0\n 0\n \n \n 8\n 218\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q15.c\n arm_max_q15.c\n 0\n 0\n \n \n 8\n 219\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_max_q31.c\n arm_max_q31.c\n 0\n 0\n \n \n 8\n 220\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_f32.c\n arm_mean_f32.c\n 0\n 0\n \n \n 8\n 221\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q7.c\n arm_mean_q7.c\n 0\n 0\n \n \n 8\n 222\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q15.c\n arm_mean_q15.c\n 0\n 0\n \n \n 8\n 223\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_mean_q31.c\n arm_mean_q31.c\n 0\n 0\n \n \n 8\n 224\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_f32.c\n arm_min_f32.c\n 0\n 0\n \n \n 8\n 225\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q7.c\n arm_min_q7.c\n 0\n 0\n \n \n 8\n 226\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q15.c\n arm_min_q15.c\n 0\n 0\n \n \n 8\n 227\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_min_q31.c\n arm_min_q31.c\n 0\n 0\n \n \n 8\n 228\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_f32.c\n arm_power_f32.c\n 0\n 0\n \n \n 8\n 229\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q7.c\n arm_power_q7.c\n 0\n 0\n \n \n 8\n 230\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q15.c\n arm_power_q15.c\n 0\n 0\n \n \n 8\n 231\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q31.c\n arm_power_q31.c\n 0\n 0\n \n \n 8\n 232\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_f32.c\n arm_rms_f32.c\n 0\n 0\n \n \n 8\n 233\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q15.c\n arm_rms_q15.c\n 0\n 0\n \n \n 8\n 234\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q31.c\n arm_rms_q31.c\n 0\n 0\n \n \n 8\n 235\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_f32.c\n arm_std_f32.c\n 0\n 0\n \n \n 8\n 236\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q15.c\n arm_std_q15.c\n 0\n 0\n \n \n 8\n 237\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q31.c\n arm_std_q31.c\n 0\n 0\n \n \n 8\n 238\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_f32.c\n arm_var_f32.c\n 0\n 0\n \n \n 8\n 239\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q15.c\n arm_var_q15.c\n 0\n 0\n \n \n 8\n 240\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q31.c\n arm_var_q31.c\n 0\n 0\n \n \n\n \n SupportFunctions\n 0\n 0\n 0\n 0\n \n 9\n 241\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_f32.c\n arm_copy_f32.c\n 0\n 0\n \n \n 9\n 242\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q7.c\n arm_copy_q7.c\n 0\n 0\n \n \n 9\n 243\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q15.c\n arm_copy_q15.c\n 0\n 0\n \n \n 9\n 244\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q31.c\n arm_copy_q31.c\n 0\n 0\n \n \n 9\n 245\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_f32.c\n arm_fill_f32.c\n 0\n 0\n \n \n 9\n 246\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q7.c\n arm_fill_q7.c\n 0\n 0\n \n \n 9\n 247\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q15.c\n arm_fill_q15.c\n 0\n 0\n \n \n 9\n 248\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q31.c\n arm_fill_q31.c\n 0\n 0\n \n \n 9\n 249\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q7.c\n arm_float_to_q7.c\n 0\n 0\n \n \n 9\n 250\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q15.c\n arm_float_to_q15.c\n 0\n 0\n \n \n 9\n 251\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q31.c\n arm_float_to_q31.c\n 0\n 0\n \n \n 9\n 252\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_float.c\n arm_q7_to_float.c\n 0\n 0\n \n \n 9\n 253\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q15.c\n arm_q7_to_q15.c\n 0\n 0\n \n \n 9\n 254\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q31.c\n arm_q7_to_q31.c\n 0\n 0\n \n \n 9\n 255\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_float.c\n arm_q15_to_float.c\n 0\n 0\n \n \n 9\n 256\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q7.c\n arm_q15_to_q7.c\n 0\n 0\n \n \n 9\n 257\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q31.c\n arm_q15_to_q31.c\n 0\n 0\n \n \n 9\n 258\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_float.c\n arm_q31_to_float.c\n 0\n 0\n \n \n 9\n 259\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q7.c\n arm_q31_to_q7.c\n 0\n 0\n \n \n 9\n 260\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q15.c\n arm_q31_to_q15.c\n 0\n 0\n \n \n\n \n CommonTables\n 0\n 0\n 0\n 0\n \n 10\n 261\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\CommonTables\\arm_common_tables.c\n arm_common_tables.c\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n DSP_Lib CM3 LE\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM3l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM3'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM3 LE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM3l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM3'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM3 BE\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM3b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM3'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM3 BE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M3\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n \n \n \n 4349\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM3b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM3\n SARMCM3.DLL\n \n TCM.DLL\n -pCM3\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M3\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM3'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x20000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvopt", "content": "\n\n\n 1.0\n\n
### uVision Project, (C) Keil Software
\n\n \n *.c\n *.s*; *.src; *.a*\n *.obj\n *.lib\n *.txt; *.h; *.inc\n *.plm\n *.cpp\n \n\n \n 0\n 0\n \n\n \n DSP_Lib CM4 LE\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 1\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 LE O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 LE FPU\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 LE FPU O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 BE\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 BE O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 BE FPU\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n DSP_Lib CM4 BE FPU O2\n 0x4\n ARM-ADS\n \n 12000000\n \n 1\n 1\n 1\n 0\n \n \n 1\n 65535\n 0\n 0\n 0\n \n \n 79\n 66\n 8\n .\\intermediateFiles\\\n \n \n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n 0\n \n \n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \n \n 1\n 0\n 0\n \n 255\n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n 1\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n \n \n \n \n \n\n \n BasicMathFunctions\n 0\n 0\n 0\n 0\n \n 1\n 1\n 1\n 0\n 0\n 15\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_f32.c\n arm_abs_f32.c\n 0\n 0\n \n \n 1\n 2\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q7.c\n arm_abs_q7.c\n 0\n 0\n \n \n 1\n 3\n 1\n 0\n 0\n 13\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q15.c\n arm_abs_q15.c\n 0\n 0\n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_abs_q31.c\n arm_abs_q31.c\n 0\n 0\n \n \n 1\n 5\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_f32.c\n arm_add_f32.c\n 0\n 0\n \n \n 1\n 6\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q7.c\n arm_add_q7.c\n 0\n 0\n \n \n 1\n 7\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q15.c\n arm_add_q15.c\n 0\n 0\n \n \n 1\n 8\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_add_q31.c\n arm_add_q31.c\n 0\n 0\n \n \n 1\n 9\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n arm_dot_prod_f32.c\n 0\n 0\n \n \n 1\n 10\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n arm_dot_prod_q7.c\n 0\n 0\n \n \n 1\n 11\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n arm_dot_prod_q15.c\n 0\n 0\n \n \n 1\n 12\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n arm_dot_prod_q31.c\n 0\n 0\n \n \n 1\n 13\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_mult_f32.c\n arm_mult_f32.c\n 0\n 0\n \n \n 1\n 14\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_mult_q7.c\n arm_mult_q7.c\n 0\n 0\n \n \n 1\n 15\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_mult_q15.c\n arm_mult_q15.c\n 0\n 0\n \n \n 1\n 16\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_mult_q31.c\n arm_mult_q31.c\n 0\n 0\n \n \n 1\n 17\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_negate_f32.c\n arm_negate_f32.c\n 0\n 0\n \n \n 1\n 18\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_negate_q7.c\n arm_negate_q7.c\n 0\n 0\n \n \n 1\n 19\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_negate_q15.c\n arm_negate_q15.c\n 0\n 0\n \n \n 1\n 20\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_negate_q31.c\n arm_negate_q31.c\n 0\n 0\n \n \n 1\n 21\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_offset_f32.c\n arm_offset_f32.c\n 0\n 0\n \n \n 1\n 22\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_offset_q7.c\n arm_offset_q7.c\n 0\n 0\n \n \n 1\n 23\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_offset_q15.c\n arm_offset_q15.c\n 0\n 0\n \n \n 1\n 24\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_offset_q31.c\n arm_offset_q31.c\n 0\n 0\n \n \n 1\n 25\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_scale_f32.c\n arm_scale_f32.c\n 0\n 0\n \n \n 1\n 26\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\BasicMathFunctions\\arm_scale_q7.c\n arm_scale_q7.c\n 0\n 0\n \n \n 1\n 27\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 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8\n 229\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q7.c\n arm_power_q7.c\n 0\n 0\n \n \n 8\n 230\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q15.c\n arm_power_q15.c\n 0\n 0\n \n \n 8\n 231\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_power_q31.c\n arm_power_q31.c\n 0\n 0\n \n \n 8\n 232\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_f32.c\n arm_rms_f32.c\n 0\n 0\n \n \n 8\n 233\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q15.c\n arm_rms_q15.c\n 0\n 0\n \n \n 8\n 234\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_rms_q31.c\n arm_rms_q31.c\n 0\n 0\n \n \n 8\n 235\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_f32.c\n arm_std_f32.c\n 0\n 0\n \n \n 8\n 236\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q15.c\n arm_std_q15.c\n 0\n 0\n \n \n 8\n 237\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_std_q31.c\n arm_std_q31.c\n 0\n 0\n \n \n 8\n 238\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_f32.c\n arm_var_f32.c\n 0\n 0\n \n \n 8\n 239\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q15.c\n arm_var_q15.c\n 0\n 0\n \n \n 8\n 240\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\StatisticsFunctions\\arm_var_q31.c\n arm_var_q31.c\n 0\n 0\n \n \n\n \n SupportFunctions\n 0\n 0\n 0\n 0\n \n 9\n 241\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_f32.c\n arm_copy_f32.c\n 0\n 0\n \n \n 9\n 242\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q7.c\n arm_copy_q7.c\n 0\n 0\n \n \n 9\n 243\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q15.c\n arm_copy_q15.c\n 0\n 0\n \n \n 9\n 244\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_copy_q31.c\n arm_copy_q31.c\n 0\n 0\n \n \n 9\n 245\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_f32.c\n arm_fill_f32.c\n 0\n 0\n \n \n 9\n 246\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q7.c\n arm_fill_q7.c\n 0\n 0\n \n \n 9\n 247\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q15.c\n arm_fill_q15.c\n 0\n 0\n \n \n 9\n 248\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_fill_q31.c\n arm_fill_q31.c\n 0\n 0\n \n \n 9\n 249\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q7.c\n arm_float_to_q7.c\n 0\n 0\n \n \n 9\n 250\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q15.c\n arm_float_to_q15.c\n 0\n 0\n \n \n 9\n 251\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_float_to_q31.c\n arm_float_to_q31.c\n 0\n 0\n \n \n 9\n 252\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_float.c\n arm_q7_to_float.c\n 0\n 0\n \n \n 9\n 253\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q15.c\n arm_q7_to_q15.c\n 0\n 0\n \n \n 9\n 254\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q7_to_q31.c\n arm_q7_to_q31.c\n 0\n 0\n \n \n 9\n 255\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_float.c\n arm_q15_to_float.c\n 0\n 0\n \n \n 9\n 256\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q7.c\n arm_q15_to_q7.c\n 0\n 0\n \n \n 9\n 257\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q15_to_q31.c\n arm_q15_to_q31.c\n 0\n 0\n \n \n 9\n 258\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_float.c\n arm_q31_to_float.c\n 0\n 0\n \n \n 9\n 259\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q7.c\n arm_q31_to_q7.c\n 0\n 0\n \n \n 9\n 260\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\SupportFunctions\\arm_q31_to_q15.c\n arm_q31_to_q15.c\n 0\n 0\n \n \n\n \n CommonTables\n 0\n 0\n 0\n 0\n \n 10\n 261\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n ..\\CommonTables\\arm_common_tables.c\n arm_common_tables.c\n 0\n 0\n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvproj", "content": "\n\n\n 1.1\n\n
### uVision Project, (C) Keil Software
\n\n \n \n DSP_Lib CM4 LE\n 0x4\n ARM-ADS\n \n \n Cortex-M4\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n \n \n \n 5125\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 LE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M4\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n \n \n \n 5125\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4l_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 LE FPU\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4lf_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 LE FPU O2\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4lf_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 0\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 BE\n 0x4\n ARM-ADS\n \n \n Cortex-M4\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n \n \n \n 5125\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING,ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 BE O2\n 0x4\n ARM-ADS\n \n \n Cortex-M4\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n \n \n \n 5125\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4b_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING,ARM_MATH_BIG_ENDIAN\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 BE FPU\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4bf_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 1\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n cmd.exe /C getSizeInfo \"!L\" \"@L_SizeInfo.txt\"\n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 4\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, ARM_MATH_BIG_ENDIAN, __FPU_PRESENT = 1\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n DSP_Lib CM4 BE FPU O2\n 0x4\n ARM-ADS\n \n \n Cortex-M4 FPU\n ARM\n CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n \n \n \n 5237\n \n \n \n \n \n \n \n \n \n \n \n 0\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n \n .\\intermediateFiles\\\n arm_cortexM4bf_math\n 0\n 1\n 0\n 1\n 1\n .\\intermediateFiles\\\n 1\n 0\n 0\n \n 0\n 0\n \n \n 0\n 0\n 0\n 0\n \n \n 0\n 0\n \n \n 0\n 0\n \n \n 1\n 0\n cmd.exe /C copy \"!L\" \"..\\..\\..\\Lib\\ARM\\\"\n \n 0\n 0\n \n 0\n \n \n \n 0\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 0\n 0\n 3\n \n \n \n \n SARMCM3.DLL\n \n DCM.DLL\n -pCM4\n SARMCM3.DLL\n \n TCM.DLL\n -pCM4\n \n \n \n 1\n 0\n 0\n 0\n 16\n \n \n 1\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 0\n \n \n 0\n 0\n 0\n 1\n 1\n 1\n 0\n 1\n 0\n \n 0\n -1\n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n 1\n 0\n 0\n 0\n 0\n -1\n \n \n \"\" ()\n \n \n \n \n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 1\n 1\n 1\n 0\n 0\n 0\n 0\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 1\n 0\n 0\n \"Cortex-M4\"\n \n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 2\n 0\n 0\n 0\n 0\n 1\n 0\n 0\n 5\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 1\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n 0\n 0x0\n 0x0\n \n \n \n \n \n 1\n 3\n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n \n ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, ARM_MATH_BIG_ENDIAN, __FPU_PRESENT = 1\n \n ..\\..\\..\\Include\n \n \n \n 1\n 0\n 0\n 0\n 0\n 0\n 0\n 0\n \n --cpreproc --cpreproc_opts='-DARM_MATH_CM4'\n \n \n \n \n \n \n 0\n 0\n 0\n 0\n 1\n 0\n 0x00000000\n 0x00000000\n \n \n \n \n \n \n \n \n \n \n \n BasicMathFunctions\n \n \n arm_abs_f32.c\n 1\n ..\\BasicMathFunctions\\arm_abs_f32.c\n \n \n arm_abs_q7.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q7.c\n \n \n arm_abs_q15.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q15.c\n \n \n arm_abs_q31.c\n 1\n ..\\BasicMathFunctions\\arm_abs_q31.c\n \n \n arm_add_f32.c\n 1\n ..\\BasicMathFunctions\\arm_add_f32.c\n \n \n arm_add_q7.c\n 1\n ..\\BasicMathFunctions\\arm_add_q7.c\n \n \n arm_add_q15.c\n 1\n ..\\BasicMathFunctions\\arm_add_q15.c\n \n \n arm_add_q31.c\n 1\n ..\\BasicMathFunctions\\arm_add_q31.c\n \n \n arm_dot_prod_f32.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n \n \n arm_dot_prod_q7.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n \n \n arm_dot_prod_q15.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n \n \n arm_dot_prod_q31.c\n 1\n ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n \n \n arm_mult_f32.c\n 1\n ..\\BasicMathFunctions\\arm_mult_f32.c\n \n \n arm_mult_q7.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q7.c\n \n \n arm_mult_q15.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q15.c\n \n \n arm_mult_q31.c\n 1\n ..\\BasicMathFunctions\\arm_mult_q31.c\n \n \n arm_negate_f32.c\n 1\n ..\\BasicMathFunctions\\arm_negate_f32.c\n \n \n arm_negate_q7.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q7.c\n \n \n arm_negate_q15.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q15.c\n \n \n arm_negate_q31.c\n 1\n ..\\BasicMathFunctions\\arm_negate_q31.c\n \n \n arm_offset_f32.c\n 1\n ..\\BasicMathFunctions\\arm_offset_f32.c\n \n \n arm_offset_q7.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q7.c\n \n \n arm_offset_q15.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q15.c\n \n \n arm_offset_q31.c\n 1\n ..\\BasicMathFunctions\\arm_offset_q31.c\n \n \n arm_scale_f32.c\n 1\n ..\\BasicMathFunctions\\arm_scale_f32.c\n \n \n arm_scale_q7.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q7.c\n \n \n arm_scale_q15.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q15.c\n \n \n arm_scale_q31.c\n 1\n ..\\BasicMathFunctions\\arm_scale_q31.c\n \n \n arm_shift_q7.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q7.c\n \n \n arm_shift_q15.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q15.c\n \n \n arm_shift_q31.c\n 1\n ..\\BasicMathFunctions\\arm_shift_q31.c\n \n \n arm_sub_f32.c\n 1\n ..\\BasicMathFunctions\\arm_sub_f32.c\n \n \n arm_sub_q7.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q7.c\n \n \n arm_sub_q15.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q15.c\n \n \n arm_sub_q31.c\n 1\n ..\\BasicMathFunctions\\arm_sub_q31.c\n \n \n \n \n FastMathFunctions\n \n \n arm_cos_f32.c\n 1\n ..\\FastMathFunctions\\arm_cos_f32.c\n \n \n arm_cos_q15.c\n 1\n ..\\FastMathFunctions\\arm_cos_q15.c\n \n \n arm_cos_q31.c\n 1\n ..\\FastMathFunctions\\arm_cos_q31.c\n \n \n arm_sin_f32.c\n 1\n ..\\FastMathFunctions\\arm_sin_f32.c\n \n \n arm_sin_q15.c\n 1\n ..\\FastMathFunctions\\arm_sin_q15.c\n \n \n arm_sin_q31.c\n 1\n ..\\FastMathFunctions\\arm_sin_q31.c\n \n \n arm_sqrt_q15.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q15.c\n \n \n arm_sqrt_q31.c\n 1\n ..\\FastMathFunctions\\arm_sqrt_q31.c\n \n \n \n \n ComplexMathFunctions\n \n \n arm_cmplx_conj_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n \n \n arm_cmplx_conj_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n \n \n arm_cmplx_conj_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n \n \n arm_cmplx_dot_prod_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n \n \n arm_cmplx_dot_prod_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n \n \n arm_cmplx_dot_prod_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n \n \n arm_cmplx_mag_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n \n \n arm_cmplx_mag_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n \n \n arm_cmplx_mag_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n \n \n arm_cmplx_mag_squared_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n \n \n arm_cmplx_mag_squared_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n \n \n arm_cmplx_mag_squared_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n \n \n arm_cmplx_mult_cmplx_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n \n \n arm_cmplx_mult_cmplx_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n \n \n arm_cmplx_mult_cmplx_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n \n \n arm_cmplx_mult_real_f32.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n \n \n arm_cmplx_mult_real_q15.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n \n \n arm_cmplx_mult_real_q31.c\n 1\n ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n \n \n \n \n FilteringFunctions\n \n \n arm_biquad_cascade_df1_32x64_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n \n \n arm_biquad_cascade_df1_32x64_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n \n \n arm_biquad_cascade_df1_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n \n \n arm_biquad_cascade_df1_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n \n \n arm_biquad_cascade_df1_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n \n \n arm_biquad_cascade_df1_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n \n \n arm_biquad_cascade_df1_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n \n \n arm_biquad_cascade_df1_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n \n \n arm_biquad_cascade_df1_q15.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n \n \n arm_biquad_cascade_df1_q31.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n \n \n arm_biquad_cascade_df2T_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n \n \n arm_biquad_cascade_df2T_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n \n \n arm_conv_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_f32.c\n \n \n arm_conv_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n \n \n arm_conv_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q15.c\n \n \n arm_conv_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_fast_q31.c\n \n \n arm_conv_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q7.c\n \n \n arm_conv_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_opt_q15.c\n \n \n arm_conv_partial_f32.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_f32.c\n \n \n arm_conv_partial_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n \n \n arm_conv_partial_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n \n \n arm_conv_partial_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n \n \n arm_conv_partial_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n \n \n arm_conv_partial_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n \n \n arm_conv_partial_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q7.c\n \n \n arm_conv_partial_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q15.c\n \n \n arm_conv_partial_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_partial_q31.c\n \n \n arm_conv_q7.c\n 1\n ..\\FilteringFunctions\\arm_conv_q7.c\n \n \n arm_conv_q15.c\n 1\n ..\\FilteringFunctions\\arm_conv_q15.c\n \n \n arm_conv_q31.c\n 1\n ..\\FilteringFunctions\\arm_conv_q31.c\n \n \n arm_correlate_f32.c\n 1\n ..\\FilteringFunctions\\arm_correlate_f32.c\n \n \n arm_correlate_fast_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n \n \n arm_correlate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n \n \n arm_correlate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n \n \n arm_correlate_opt_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n \n \n arm_correlate_opt_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n \n \n arm_correlate_q7.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q7.c\n \n \n arm_correlate_q15.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q15.c\n \n \n arm_correlate_q31.c\n 1\n ..\\FilteringFunctions\\arm_correlate_q31.c\n \n \n arm_fir_decimate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n \n \n arm_fir_decimate_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n \n \n arm_fir_decimate_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n \n \n arm_fir_decimate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n \n \n arm_fir_decimate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n \n \n arm_fir_decimate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n \n \n arm_fir_decimate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n \n \n arm_fir_decimate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n \n \n arm_fir_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_f32.c\n \n \n arm_fir_fast_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q15.c\n \n \n arm_fir_fast_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_fast_q31.c\n \n \n arm_fir_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_f32.c\n \n \n arm_fir_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q7.c\n \n \n arm_fir_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q15.c\n \n \n arm_fir_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_init_q31.c\n \n \n arm_fir_interpolate_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n \n \n arm_fir_interpolate_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n \n \n arm_fir_interpolate_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n \n \n arm_fir_interpolate_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n \n \n arm_fir_interpolate_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n \n \n arm_fir_interpolate_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n \n \n arm_fir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n \n \n arm_fir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n \n \n arm_fir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n \n \n arm_fir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n \n \n arm_fir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n \n \n arm_fir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n \n \n arm_fir_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_q7.c\n \n \n arm_fir_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_q15.c\n \n \n arm_fir_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_q31.c\n \n \n arm_fir_sparse_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n \n \n arm_fir_sparse_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n \n \n arm_fir_sparse_init_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n \n \n arm_fir_sparse_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n \n \n arm_fir_sparse_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n \n \n arm_fir_sparse_q7.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n \n \n arm_fir_sparse_q15.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n \n \n arm_fir_sparse_q31.c\n 1\n ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n \n \n arm_iir_lattice_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n \n \n arm_iir_lattice_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n \n \n arm_iir_lattice_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n \n \n arm_iir_lattice_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n \n \n arm_iir_lattice_q15.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n \n \n arm_iir_lattice_q31.c\n 1\n ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n \n \n arm_lms_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_f32.c\n \n \n arm_lms_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_f32.c\n \n \n arm_lms_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q15.c\n \n \n arm_lms_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_init_q31.c\n \n \n arm_lms_norm_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_f32.c\n \n \n arm_lms_norm_init_f32.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n \n \n arm_lms_norm_init_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n \n \n arm_lms_norm_init_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n \n \n arm_lms_norm_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q15.c\n \n \n arm_lms_norm_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_norm_q31.c\n \n \n arm_lms_q15.c\n 1\n ..\\FilteringFunctions\\arm_lms_q15.c\n \n \n arm_lms_q31.c\n 1\n ..\\FilteringFunctions\\arm_lms_q31.c\n \n \n \n \n MatrixFunctions\n \n \n arm_mat_add_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_f32.c\n \n \n arm_mat_add_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q15.c\n \n \n arm_mat_add_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_add_q31.c\n \n \n arm_mat_init_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_f32.c\n \n \n arm_mat_init_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q15.c\n \n \n arm_mat_init_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_init_q31.c\n \n \n arm_mat_inverse_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n \n \n arm_mat_mult_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_f32.c\n \n \n arm_mat_mult_fast_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n \n \n arm_mat_mult_fast_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n \n \n arm_mat_mult_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q15.c\n \n \n arm_mat_mult_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_mult_q31.c\n \n \n arm_mat_scale_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_f32.c\n \n \n arm_mat_scale_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q15.c\n \n \n arm_mat_scale_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_scale_q31.c\n \n \n arm_mat_sub_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_f32.c\n \n \n arm_mat_sub_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q15.c\n \n \n arm_mat_sub_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_sub_q31.c\n \n \n arm_mat_trans_f32.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_f32.c\n \n \n arm_mat_trans_q15.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q15.c\n \n \n arm_mat_trans_q31.c\n 1\n ..\\MatrixFunctions\\arm_mat_trans_q31.c\n \n \n \n \n TransformFunctions\n \n \n arm_bitreversal.c\n 1\n ..\\TransformFunctions\\arm_bitreversal.c\n \n \n arm_bitreversal2.S\n 2\n ..\\TransformFunctions\\arm_bitreversal2.S\n \n \n arm_cfft_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_f32.c\n \n \n arm_cfft_radix2_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n \n \n arm_cfft_radix2_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n \n \n arm_cfft_radix2_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n \n \n arm_cfft_radix2_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n \n \n arm_cfft_radix2_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n \n \n arm_cfft_radix2_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n \n \n arm_cfft_radix4_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n \n \n arm_cfft_radix4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n \n \n arm_cfft_radix4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n \n \n arm_cfft_radix4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n \n \n arm_cfft_radix4_q15.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n \n \n arm_cfft_radix4_q31.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n \n \n arm_cfft_radix8_f32.c\n 1\n ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n \n \n arm_dct4_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_f32.c\n \n \n arm_dct4_init_f32.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_f32.c\n \n \n arm_dct4_init_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q15.c\n \n \n arm_dct4_init_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_init_q31.c\n \n \n arm_dct4_q15.c\n 1\n ..\\TransformFunctions\\arm_dct4_q15.c\n \n \n arm_dct4_q31.c\n 1\n ..\\TransformFunctions\\arm_dct4_q31.c\n \n \n arm_rfft_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_f32.c\n \n \n arm_rfft_fast_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_f32.c\n \n \n arm_rfft_fast_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n \n \n arm_rfft_init_f32.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_f32.c\n \n \n arm_rfft_init_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q15.c\n \n \n arm_rfft_init_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_init_q31.c\n \n \n arm_rfft_q15.c\n 1\n ..\\TransformFunctions\\arm_rfft_q15.c\n \n \n arm_rfft_q31.c\n 1\n ..\\TransformFunctions\\arm_rfft_q31.c\n \n \n \n \n ControllerFunctions\n \n \n arm_pid_init_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_f32.c\n \n \n arm_pid_init_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q15.c\n \n \n arm_pid_init_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_init_q31.c\n \n \n arm_pid_reset_f32.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_f32.c\n \n \n arm_pid_reset_q15.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q15.c\n \n \n arm_pid_reset_q31.c\n 1\n ..\\ControllerFunctions\\arm_pid_reset_q31.c\n \n \n arm_sin_cos_f32.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_f32.c\n \n \n arm_sin_cos_q31.c\n 1\n ..\\ControllerFunctions\\arm_sin_cos_q31.c\n \n \n \n \n StatisticsFunctions\n \n \n arm_max_f32.c\n 1\n ..\\StatisticsFunctions\\arm_max_f32.c\n \n \n arm_max_q7.c\n 1\n ..\\StatisticsFunctions\\arm_max_q7.c\n \n \n arm_max_q15.c\n 1\n ..\\StatisticsFunctions\\arm_max_q15.c\n \n \n arm_max_q31.c\n 1\n ..\\StatisticsFunctions\\arm_max_q31.c\n \n \n arm_mean_f32.c\n 1\n ..\\StatisticsFunctions\\arm_mean_f32.c\n \n \n arm_mean_q7.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q7.c\n \n \n arm_mean_q15.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q15.c\n \n \n arm_mean_q31.c\n 1\n ..\\StatisticsFunctions\\arm_mean_q31.c\n \n \n arm_min_f32.c\n 1\n ..\\StatisticsFunctions\\arm_min_f32.c\n \n \n arm_min_q7.c\n 1\n ..\\StatisticsFunctions\\arm_min_q7.c\n \n \n arm_min_q15.c\n 1\n ..\\StatisticsFunctions\\arm_min_q15.c\n \n \n arm_min_q31.c\n 1\n ..\\StatisticsFunctions\\arm_min_q31.c\n \n \n arm_power_f32.c\n 1\n ..\\StatisticsFunctions\\arm_power_f32.c\n \n \n arm_power_q7.c\n 1\n ..\\StatisticsFunctions\\arm_power_q7.c\n \n \n arm_power_q15.c\n 1\n ..\\StatisticsFunctions\\arm_power_q15.c\n \n \n arm_power_q31.c\n 1\n ..\\StatisticsFunctions\\arm_power_q31.c\n \n \n arm_rms_f32.c\n 1\n ..\\StatisticsFunctions\\arm_rms_f32.c\n \n \n arm_rms_q15.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q15.c\n \n \n arm_rms_q31.c\n 1\n ..\\StatisticsFunctions\\arm_rms_q31.c\n \n \n arm_std_f32.c\n 1\n ..\\StatisticsFunctions\\arm_std_f32.c\n \n \n arm_std_q15.c\n 1\n ..\\StatisticsFunctions\\arm_std_q15.c\n \n \n arm_std_q31.c\n 1\n ..\\StatisticsFunctions\\arm_std_q31.c\n \n \n arm_var_f32.c\n 1\n ..\\StatisticsFunctions\\arm_var_f32.c\n \n \n arm_var_q15.c\n 1\n ..\\StatisticsFunctions\\arm_var_q15.c\n \n \n arm_var_q31.c\n 1\n ..\\StatisticsFunctions\\arm_var_q31.c\n \n \n \n \n SupportFunctions\n \n \n arm_copy_f32.c\n 1\n ..\\SupportFunctions\\arm_copy_f32.c\n \n \n arm_copy_q7.c\n 1\n ..\\SupportFunctions\\arm_copy_q7.c\n \n \n arm_copy_q15.c\n 1\n ..\\SupportFunctions\\arm_copy_q15.c\n \n \n arm_copy_q31.c\n 1\n ..\\SupportFunctions\\arm_copy_q31.c\n \n \n arm_fill_f32.c\n 1\n ..\\SupportFunctions\\arm_fill_f32.c\n \n \n arm_fill_q7.c\n 1\n ..\\SupportFunctions\\arm_fill_q7.c\n \n \n arm_fill_q15.c\n 1\n ..\\SupportFunctions\\arm_fill_q15.c\n \n \n arm_fill_q31.c\n 1\n ..\\SupportFunctions\\arm_fill_q31.c\n \n \n arm_float_to_q7.c\n 1\n ..\\SupportFunctions\\arm_float_to_q7.c\n \n \n arm_float_to_q15.c\n 1\n ..\\SupportFunctions\\arm_float_to_q15.c\n \n \n arm_float_to_q31.c\n 1\n ..\\SupportFunctions\\arm_float_to_q31.c\n \n \n arm_q7_to_float.c\n 1\n ..\\SupportFunctions\\arm_q7_to_float.c\n \n \n arm_q7_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q15.c\n \n \n arm_q7_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q7_to_q31.c\n \n \n arm_q15_to_float.c\n 1\n ..\\SupportFunctions\\arm_q15_to_float.c\n \n \n arm_q15_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q7.c\n \n \n arm_q15_to_q31.c\n 1\n ..\\SupportFunctions\\arm_q15_to_q31.c\n \n \n arm_q31_to_float.c\n 1\n ..\\SupportFunctions\\arm_q31_to_float.c\n \n \n arm_q31_to_q7.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q7.c\n \n \n arm_q31_to_q15.c\n 1\n ..\\SupportFunctions\\arm_q31_to_q15.c\n \n \n \n \n CommonTables\n \n \n arm_common_tables.c\n 1\n ..\\CommonTables\\arm_common_tables.c\n \n \n \n \n \n \n\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat", "content": "@echo off\n\nSET TMP=C:\\Temp\nSET TEMP=C:\\Temp\n\nSET UVEXE=C:\\Keil\\UV4\\UV4.EXE\n\necho.\necho Building DSP Library for Cortex-M0 Little Endian\n%UVEXE% -rb arm_cortexM0x_math.uvproj -t\"DSP_Lib CM0 LE\" -o\"DSP_Lib CM0 LE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M0 Big Endian\n%UVEXE% -rb arm_cortexM0x_math.uvproj -t\"DSP_Lib CM0 BE\" -o\"DSP_Lib CM0 BE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M3 Little Endian\n%UVEXE% -rb arm_cortexM3x_math.uvproj -t\"DSP_Lib CM3 LE\" -o\"DSP_Lib CM3 LE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M3 Big Endian\n%UVEXE% -rb arm_cortexM3x_math.uvproj -t\"DSP_Lib CM3 BE\" -o\"DSP_Lib CM3 BE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M4 Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE\" -o\"DSP_Lib CM4 LE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M4 Big Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 BE\" -o\"DSP_Lib CM4 BE.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M4 with FPU Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE FPU\" -o\"DSP_Lib CM4 LE FPU.txt\" -j0\n\necho.\necho Building DSP Library for Cortex-M4 with FPU Big Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 BE FPU\" -o\"DSP_Lib CM4 BE FPU.txt\" -j0" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ARM/getSizeInfo.bat", "content": "@echo off\n\nif .%1==. goto help\nif exist %1 goto getSizeInfo\ngoto help\n\n:getSizeInfo\nC:\\Keil\\ARM\\ARMCC\\bin\\armar --sizes %1 > %2\ngoto end\n\n:help\necho Syntax: getSizeInfo inFile outFile\necho.\necho e.g.: getSizeInfo .\\intermediateFiles\\arm_cortexM0l_math.lib arm_cortexM0l_math.txt\n\n:end\n\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_abs_f32.c \n* \n* Description:\tVector absolute value. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup BasicAbs Vector Absolute Value \n * \n * Computes the absolute value of a vector on an element-by-element basis. \n * \n * 
        \n *     pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.        \n *
\n * \n * The functions support in-place computation allowing the source and\n * destination pointers to reference the same memory buffer.\n * There are separate functions for floating-point, Q7, Q15, and Q31 data types.\n */\n\n/** \n * @addtogroup BasicAbs \n * @{ \n */\n\n/** \n * @brief Floating-point vector absolute value. \n * @param[in] *pSrc points to the input buffer \n * @param[out] *pDst points to the output buffer \n * @param[in] blockSize number of samples in each vector \n * @return none. \n */\n\nvoid arm_abs_f32(\n float32_t * pSrc,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n /* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t in1, in2, in3, in4; /* temporary variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Calculate absolute and then store the results in the destination buffer. */\n /* read sample from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n\n /* find absolute value */\n in1 = fabsf(in1);\n\n /* read sample from source */\n in4 = *(pSrc + 3);\n\n /* find absolute value */\n in2 = fabsf(in2);\n\n /* read sample from source */\n *pDst = in1;\n\n /* find absolute value */\n in3 = fabsf(in3);\n\n /* find absolute value */\n in4 = fabsf(in4);\n\n /* store result to destination */\n *(pDst + 1) = in2;\n\n /* store result to destination */\n *(pDst + 2) = in3;\n\n /* store result to destination */\n *(pDst + 3) = in4;\n\n\n /* Update source pointer to process next sampels */\n pSrc += 4u;\n\n /* Update destination pointer to process next sampels */\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Calculate absolute and then store the results in the destination buffer. */\n *pDst++ = fabsf(*pSrc++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicAbs group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_abs_q15.c \n* \n* Description:\tQ15 vector absolute value. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAbs \n * @{ \n */\n\n/** \n * @brief Q15 vector absolute value. \n * @param[in] *pSrc points to the input buffer \n * @param[out] *pDst points to the output buffer \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. \n */\n\nvoid arm_abs_q15(\n q15_t * pSrc,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n __SIMD32_TYPE *simd;\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n q15_t in1; /* Input value1 */\n q15_t in2; /* Input value2 */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n simd = __SIMD32_CONST(pDst);\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Read two inputs */\n in1 = *pSrc++;\n in2 = *pSrc++;\n\n\n /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */\n#ifndef ARM_MATH_BIG_ENDIAN\n *simd++ =\n __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),\n ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);\n\n#else\n\n\n *simd++ =\n __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),\n ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n in1 = *pSrc++;\n in2 = *pSrc++;\n\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *simd++ =\n __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),\n ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);\n\n#else\n\n\n *simd++ =\n __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),\n ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n pDst = (q15_t *)simd;\n\t\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Read the input */\n in1 = *pSrc++;\n\n /* Calculate absolute value of input and then store the result in the destination buffer. */\n *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n q15_t in; /* Temporary input variable */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Read the input */\n in = *pSrc++;\n\n /* Calculate absolute value of input and then store the result in the destination buffer. */\n *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of BasicAbs group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_abs_q31.c \n* \n* Description:\tQ31 vector absolute value. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAbs \n * @{ \n */\n\n\n/** \n * @brief Q31 vector absolute value. \n * @param[in] *pSrc points to the input buffer \n * @param[out] *pDst points to the output buffer \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. \n */\n\nvoid arm_abs_q31(\n q31_t * pSrc,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n q31_t in; /* Input value */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n /* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t in1, in2, in3, in4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */\n in1 = *pSrc++;\n in2 = *pSrc++;\n in3 = *pSrc++;\n in4 = *pSrc++;\n\n *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);\n *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);\n *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);\n *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */\n in = *pSrc++;\n *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n}\n\n/** \n * @} end of BasicAbs group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_abs_q7.c \n* \n* Description:\tQ7 vector absolute value. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAbs \n * @{ \n */\n\n/** \n * @brief Q7 vector absolute value. \n * @param[in] *pSrc points to the input buffer \n * @param[out] *pDst points to the output buffer \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * \\par Conditions for optimum performance \n * Input and output buffers should be aligned by 32-bit \n * \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. \n */\n\nvoid arm_abs_q7(\n q7_t * pSrc,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n q7_t in; /* Input value1 */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n /* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t in1, in2, in3, in4; /* temporary input variables */\n q31_t out1, out2, out3, out4; /* temporary output variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Read inputs */\n in1 = (q31_t) * pSrc;\n in2 = (q31_t) * (pSrc + 1);\n in3 = (q31_t) * (pSrc + 2);\n\n /* find absolute value */\n out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);\n\n /* read input */\n in4 = (q31_t) * (pSrc + 3);\n\n /* find absolute value */\n out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);\n\n /* store result to destination */\n *pDst = (q7_t) out1;\n\n /* find absolute value */\n out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);\n\n /* find absolute value */\n out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);\n\n /* store result to destination */\n *(pDst + 1) = (q7_t) out2;\n\n /* store result to destination */\n *(pDst + 2) = (q7_t) out3;\n\n /* store result to destination */\n *(pDst + 3) = (q7_t) out4;\n\n /* update pointers to process next samples */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n#else\n\n /* Run the below code for Cortex-M0 */\n blkCnt = blockSize;\n\n#endif // #define ARM_MATH_CM0_FAMILY\n\n while(blkCnt > 0u)\n {\n /* C = |A| */\n /* Read the input */\n in = *pSrc++;\n\n /* Store the Absolute result in the destination buffer */\n *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicAbs group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_add_f32.c \n* \n* Description:\tFloating-point vector addition. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup BasicAdd Vector Addition \n * \n * Element-by-element addition of two vectors. \n * \n * 
        \n *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        \n *
\n * \n * There are separate functions for floating-point, Q7, Q15, and Q31 data types. \n */\n\n/** \n * @addtogroup BasicAdd \n * @{ \n */\n\n/** \n * @brief Floating-point vector addition. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n */\n\nvoid arm_add_f32(\n float32_t * pSrcA,\n float32_t * pSrcB,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */\n float32_t inB1, inB2, inB3, inB4; /* temporary input variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n\n /* read four inputs from sourceA and four inputs from sourceB */\n inA1 = *pSrcA;\n inB1 = *pSrcB;\n inA2 = *(pSrcA + 1);\n inB2 = *(pSrcB + 1);\n inA3 = *(pSrcA + 2);\n inB3 = *(pSrcB + 2);\n inA4 = *(pSrcA + 3);\n inB4 = *(pSrcB + 3);\n\n /* C = A + B */\n /* add and store result to destination */\n *pDst = inA1 + inB1;\n *(pDst + 1) = inA2 + inB2;\n *(pDst + 2) = inA3 + inB3;\n *(pDst + 3) = inA4 + inB4;\n\n /* update pointers to process next samples */\n pSrcA += 4u;\n pSrcB += 4u;\n pDst += 4u;\n\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (*pSrcA++) + (*pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicAdd group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_add_q15.c \n* \n* Description:\tQ15 vector addition \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAdd \n * @{ \n */\n\n/** \n * @brief Q15 vector addition. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. \n */\n\nvoid arm_add_q15(\n q15_t * pSrcA,\n q15_t * pSrcB,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inB1, inB2;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n inA1 = *__SIMD32(pSrcA)++;\n inA2 = *__SIMD32(pSrcA)++;\n inB1 = *__SIMD32(pSrcB)++;\n inB2 = *__SIMD32(pSrcB)++;\n\n *__SIMD32(pDst)++ = __QADD16(inA1, inB1);\n *__SIMD32(pDst)++ = __QADD16(inA2, inB2);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n}\n\n/** \n * @} end of BasicAdd group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_add_q31.c \n* \n* Description:\tQ31 vector addition. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAdd \n * @{ \n */\n\n\n/** \n * @brief Q31 vector addition. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. \n */\n\nvoid arm_add_q31(\n q31_t * pSrcA,\n q31_t * pSrcB,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inA3, inA4;\n q31_t inB1, inB2, inB3, inB4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n inA1 = *pSrcA++;\n inA2 = *pSrcA++;\n inB1 = *pSrcB++;\n inB2 = *pSrcB++;\n\n inA3 = *pSrcA++;\n inA4 = *pSrcA++;\n inB3 = *pSrcB++;\n inB4 = *pSrcB++;\n\n *pDst++ = __QADD(inA1, inB1);\n *pDst++ = __QADD(inA2, inB2);\n *pDst++ = __QADD(inA3, inB3);\n *pDst++ = __QADD(inA4, inB4);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = __QADD(*pSrcA++, *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of BasicAdd group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_add_q7.c \n* \n* Description:\tQ7 vector addition. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicAdd \n * @{ \n */\n\n/** \n * @brief Q7 vector addition. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. \n */\n\nvoid arm_add_q7(\n q7_t * pSrcA,\n q7_t * pSrcB,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + B */\n /* Add and then store the results in the destination buffer. */\n *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n}\n\n/** \n * @} end of BasicAdd group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_dot_prod_f32.c \n* \n* Description:\tFloating-point dot product. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath\n */\n\n/**\n * @defgroup dot_prod Vector Dot Product\n *\n * Computes the dot product of two vectors.\n * The vectors are multiplied element-by-element and then summed.\n *\n * 
\n *     sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]\n *
\n *\n * There are separate functions for floating-point, Q7, Q15, and Q31 data types. \n */\n\n/** \n * @addtogroup dot_prod \n * @{ \n */\n\n/** \n * @brief Dot product of floating-point vectors. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[in] blockSize number of samples in each vector \n * @param[out] *result output result returned here \n * @return none. \n */\n\n\nvoid arm_dot_prod_f32(\n float32_t * pSrcA,\n float32_t * pSrcB,\n uint32_t blockSize,\n float32_t * result)\n{\n float32_t sum = 0.0f; /* Temporary result storage */\n uint32_t blkCnt; /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the result in a temporary buffer */\n sum += (*pSrcA++) * (*pSrcB++);\n sum += (*pSrcA++) * (*pSrcB++);\n sum += (*pSrcA++) * (*pSrcB++);\n sum += (*pSrcA++) * (*pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the result in a temporary buffer. */\n sum += (*pSrcA++) * (*pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n /* Store the result back in the destination buffer */\n *result = sum;\n}\n\n/** \n * @} end of dot_prod group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_dot_prod_q15.c \n* \n* Description:\tQ15 dot product. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup dot_prod \n * @{ \n */\n\n/** \n * @brief Dot product of Q15 vectors. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[in] blockSize number of samples in each vector \n * @param[out] *result output result returned here \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these \n * results are added to a 64-bit accumulator in 34.30 format. \n * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator \n * there is no risk of overflow. \n * The return result is in 34.30 format. \n */\n\nvoid arm_dot_prod_q15(\n q15_t * pSrcA,\n q15_t * pSrcB,\n uint32_t blockSize,\n q63_t * result)\n{\n q63_t sum = 0; /* Temporary result storage */\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the result in a temporary buffer. */\n sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);\n sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the results in a temporary buffer. */\n sum = __SMLALD(*pSrcA++, *pSrcB++, sum);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the results in a temporary buffer. */\n sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n /* Store the result in the destination buffer in 34.30 format */\n *result = sum;\n\n}\n\n/** \n * @} end of dot_prod group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_dot_prod_q31.c \n* \n* Description:\tQ31 dot product. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup dot_prod \n * @{ \n */\n\n/** \n * @brief Dot product of Q31 vectors. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[in] blockSize number of samples in each vector \n * @param[out] *result output result returned here \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these \n * are truncated to 2.48 format by discarding the lower 14 bits. \n * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. \n * There are 15 guard bits in the accumulator and there is no risk of overflow as long as \n * the length of the vectors is less than 2^16 elements. \n * The return result is in 16.48 format. \n */\n\nvoid arm_dot_prod_q31(\n q31_t * pSrcA,\n q31_t * pSrcB,\n uint32_t blockSize,\n q63_t * result)\n{\n q63_t sum = 0; /* Temporary result storage */\n uint32_t blkCnt; /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inA3, inA4;\n q31_t inB1, inB2, inB3, inB4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the result in a temporary buffer. */\n inA1 = *pSrcA++;\n inA2 = *pSrcA++;\n inA3 = *pSrcA++;\n inA4 = *pSrcA++;\n inB1 = *pSrcB++;\n inB2 = *pSrcB++;\n inB3 = *pSrcB++;\n inB4 = *pSrcB++;\n\n sum += ((q63_t) inA1 * inB1) >> 14u;\n sum += ((q63_t) inA2 * inB2) >> 14u;\n sum += ((q63_t) inA3 * inB3) >> 14u;\n sum += ((q63_t) inA4 * inB4) >> 14u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Calculate dot product and then store the result in a temporary buffer. */\n sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* Store the result in the destination buffer in 16.48 format */\n *result = sum;\n}\n\n/** \n * @} end of dot_prod group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_dot_prod_q7.c \n* \n* Description:\tQ7 dot product. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup dot_prod \n * @{ \n */\n\n/** \n * @brief Dot product of Q7 vectors. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[in] blockSize number of samples in each vector \n * @param[out] *result output result returned here \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these \n * results are added to an accumulator in 18.14 format. \n * Nonsaturating additions are used and there is no danger of wrap around as long as \n * the vectors are less than 2^18 elements long. \n * The return result is in 18.14 format. \n */\n\nvoid arm_dot_prod_q7(\n q7_t * pSrcA,\n q7_t * pSrcB,\n uint32_t blockSize,\n q31_t * result)\n{\n uint32_t blkCnt; /* loop counter */\n\n q31_t sum = 0; /* Temporary variables to store output */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n q31_t input1, input2; /* Temporary variables to store input */\n q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */\n\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* read 4 samples at a time from sourceA */\n input1 = *__SIMD32(pSrcA)++;\n /* read 4 samples at a time from sourceB */\n input2 = *__SIMD32(pSrcB)++;\n\n /* extract two q7_t samples to q15_t samples */\n inA1 = __SXTB16(__ROR(input1, 8));\n /* extract reminaing two samples */\n inA2 = __SXTB16(input1);\n /* extract two q7_t samples to q15_t samples */\n inB1 = __SXTB16(__ROR(input2, 8));\n /* extract reminaing two samples */\n inB2 = __SXTB16(input2);\n\n /* multiply and accumulate two samples at a time */\n sum = __SMLAD(inA1, inB1, sum);\n sum = __SMLAD(inA2, inB2, sum);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Dot product and then store the results in a temporary buffer. */\n sum = __SMLAD(*pSrcA++, *pSrcB++, sum);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */\n /* Dot product and then store the results in a temporary buffer. */\n sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n /* Store the result in the destination buffer in 18.14 format */\n *result = sum;\n}\n\n/** \n * @} end of dot_prod group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t arm_mult_f32.c \n* \n* Description:\tFloating-point vector multiplication. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup BasicMult Vector Multiplication \n * \n * Element-by-element multiplication of two vectors. \n * \n * 
        \n *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        \n *
\n * \n * There are separate functions for floating-point, Q7, Q15, and Q31 data types. \n */\n\n/** \n * @addtogroup BasicMult \n * @{ \n */\n\n/** \n * @brief Floating-point vector multiplication. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n */\n\nvoid arm_mult_f32(\n float32_t * pSrcA,\n float32_t * pSrcB,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counters */\n#ifndef ARM_MATH_CM0_FAMILY\n\n /* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t inA1, inA2, inA3, inA4; /* temporary input variables */\n float32_t inB1, inB2, inB3, inB4; /* temporary input variables */\n float32_t out1, out2, out3, out4; /* temporary output variables */\n\n /* loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and store the results in output buffer */\n /* read sample from sourceA */\n inA1 = *pSrcA;\n /* read sample from sourceB */\n inB1 = *pSrcB;\n /* read sample from sourceA */\n inA2 = *(pSrcA + 1);\n /* read sample from sourceB */\n inB2 = *(pSrcB + 1);\n\n /* out = sourceA * sourceB */\n out1 = inA1 * inB1;\n\n /* read sample from sourceA */\n inA3 = *(pSrcA + 2);\n /* read sample from sourceB */\n inB3 = *(pSrcB + 2);\n\n /* out = sourceA * sourceB */\n out2 = inA2 * inB2;\n\n /* read sample from sourceA */\n inA4 = *(pSrcA + 3);\n\n /* store result to destination buffer */\n *pDst = out1;\n\n /* read sample from sourceB */\n inB4 = *(pSrcB + 3);\n\n /* out = sourceA * sourceB */\n out3 = inA3 * inB3;\n\n /* store result to destination buffer */\n *(pDst + 1) = out2;\n\n /* out = sourceA * sourceB */\n out4 = inA4 * inB4;\n /* store result to destination buffer */\n *(pDst + 2) = out3;\n /* store result to destination buffer */\n *(pDst + 3) = out4;\n\n\n /* update pointers to process next samples */\n pSrcA += 4u;\n pSrcB += 4u;\n pDst += 4u;\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and store the results in output buffer */\n *pDst++ = (*pSrcA++) * (*pSrcB++);\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicMult group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t arm_mult_q15.c \n* \n* Description:\tQ15 vector multiplication. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicMult \n * @{ \n */\n\n\n/** \n * @brief Q15 vector multiplication \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. \n */\n\nvoid arm_mult_q15(\n q15_t * pSrcA,\n q15_t * pSrcB,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inB1, inB2; /* temporary input variables */\n q15_t out1, out2, out3, out4; /* temporary output variables */\n q31_t mul1, mul2, mul3, mul4; /* temporary variables */\n\n /* loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* read two samples at a time from sourceA */\n inA1 = *__SIMD32(pSrcA)++;\n /* read two samples at a time from sourceB */\n inB1 = *__SIMD32(pSrcB)++;\n /* read two samples at a time from sourceA */\n inA2 = *__SIMD32(pSrcA)++;\n /* read two samples at a time from sourceB */\n inB2 = *__SIMD32(pSrcB)++;\n\n /* multiply mul = sourceA * sourceB */\n mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));\n mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);\n mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));\n mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);\n\n /* saturate result to 16 bit */\n out1 = (q15_t) __SSAT(mul1 >> 15, 16);\n out2 = (q15_t) __SSAT(mul2 >> 15, 16);\n out3 = (q15_t) __SSAT(mul3 >> 15, 16);\n out4 = (q15_t) __SSAT(mul4 >> 15, 16);\n\n /* store the result */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);\n *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);\n\n#else\n\n *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);\n *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);\n\n#endif // #ifndef ARM_MATH_BIG_ENDIAN\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and store the result in the destination buffer */\n *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicMult group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t arm_mult_q31.c \n* \n* Description:\tQ31 vector multiplication. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicMult \n * @{ \n */\n\n/** \n * @brief Q31 vector multiplication. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. \n */\n\nvoid arm_mult_q31(\n q31_t * pSrcA,\n q31_t * pSrcB,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inA3, inA4; /* temporary input variables */\n q31_t inB1, inB2, inB3, inB4; /* temporary input variables */\n q31_t out1, out2, out3, out4; /* temporary output variables */\n\n /* loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and then store the results in the destination buffer. */\n inA1 = *pSrcA++;\n inA2 = *pSrcA++;\n inA3 = *pSrcA++;\n inA4 = *pSrcA++;\n inB1 = *pSrcB++;\n inB2 = *pSrcB++;\n inB3 = *pSrcB++;\n inB4 = *pSrcB++;\n\n out1 = ((q63_t) inA1 * inB1) >> 32;\n out2 = ((q63_t) inA2 * inB2) >> 32;\n out3 = ((q63_t) inA3 * inB3) >> 32;\n out4 = ((q63_t) inA4 * inB4) >> 32;\n\n out1 = __SSAT(out1, 31);\n out2 = __SSAT(out2, 31);\n out3 = __SSAT(out3, 31);\n out4 = __SSAT(out4, 31);\n\n *pDst++ = out1 << 1u;\n *pDst++ = out2 << 1u;\n *pDst++ = out3 << 1u;\n *pDst++ = out4 << 1u;\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and then store the results in the destination buffer. */\n *pDst++ =\n (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicMult group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t arm_mult_q7.c \n* \n* Description:\tQ7 vector multiplication. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicMult \n * @{ \n */\n\n/** \n * @brief Q7 vector multiplication \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. \n */\n\nvoid arm_mult_q7(\n q7_t * pSrcA,\n q7_t * pSrcB,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q7_t out1, out2, out3, out4; /* Temporary variables to store the product */\n\n /* loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and store the results in temporary variables */\n out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);\n out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);\n out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);\n out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);\n\n /* Store the results of 4 inputs in the destination buffer in single cycle by packing */\n *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = A * B */\n /* Multiply the inputs and store the result in the destination buffer */\n *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);\n\n /* Decrement the blockSize loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicMult group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_negate_f32.c \n* \n* Description:\tNegates floating-point vectors. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup negate Vector Negate \n * \n * Negates the elements of a vector. \n * \n * 
        \n *     pDst[n] = -pSrc[n],   0 <= n < blockSize.        \n *
\n *\n * The functions support in-place computation allowing the source and\n * destination pointers to reference the same memory buffer.\n * There are separate functions for floating-point, Q7, Q15, and Q31 data types.\n */\n\n/** \n * @addtogroup negate \n * @{ \n */\n\n/** \n * @brief Negates the elements of a floating-point vector. \n * @param[in] *pSrc points to the input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n */\n\nvoid arm_negate_f32(\n float32_t * pSrc,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t in1, in2, in3, in4; /* temporary variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* read inputs from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n /* negate the input */\n in1 = -in1;\n in2 = -in2;\n in3 = -in3;\n in4 = -in4;\n\n /* store the result to destination */\n *pDst = in1;\n *(pDst + 1) = in2;\n *(pDst + 2) = in3;\n *(pDst + 3) = in4;\n\n /* update pointers to process next samples */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Negate and then store the results in the destination buffer. */\n *pDst++ = -*pSrc++;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of negate group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_negate_q15.c \n* \n* Description:\tNegates Q15 vectors. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup negate \n * @{ \n */\n\n/** \n * @brief Negates the elements of a Q15 vector. \n * @param[in] *pSrc points to the input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * \\par Conditions for optimum performance \n * Input and output buffers should be aligned by 32-bit \n * \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. \n */\n\nvoid arm_negate_q15(\n q15_t * pSrc,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n q15_t in;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n q31_t in1, in2; /* Temporary variables */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Read two inputs at a time */\n in1 = _SIMD32_OFFSET(pSrc);\n in2 = _SIMD32_OFFSET(pSrc + 2);\n\n /* negate two samples at a time */\n in1 = __QSUB16(0, in1);\n\n /* negate two samples at a time */\n in2 = __QSUB16(0, in2);\n\n /* store the result to destination 2 samples at a time */\n _SIMD32_OFFSET(pDst) = in1;\n /* store the result to destination 2 samples at a time */\n _SIMD32_OFFSET(pDst + 2) = in2;\n\n\n /* update pointers to process next samples */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Negate and then store the result in the destination buffer. */\n in = *pSrc++;\n *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of negate group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_negate_q31.c \n* \n* Description:\tNegates Q31 vectors. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup negate \n * @{ \n */\n\n/** \n * @brief Negates the elements of a Q31 vector. \n * @param[in] *pSrc points to the input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. \n */\n\nvoid arm_negate_q31(\n q31_t * pSrc,\n q31_t * pDst,\n uint32_t blockSize)\n{\n q31_t in; /* Temporary variable */\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t in1, in2, in3, in4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Negate and then store the results in the destination buffer. */\n in1 = *pSrc++;\n in2 = *pSrc++;\n in3 = *pSrc++;\n in4 = *pSrc++;\n\n *pDst++ = __QSUB(0, in1);\n *pDst++ = __QSUB(0, in2);\n *pDst++ = __QSUB(0, in3);\n *pDst++ = __QSUB(0, in4);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Negate and then store the result in the destination buffer. */\n in = *pSrc++;\n *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of negate group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_negate_q7.c \n* \n* Description:\tNegates Q7 vectors. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup negate \n * @{ \n */\n\n/** \n * @brief Negates the elements of a Q7 vector. \n * @param[in] *pSrc points to the input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. \n */\n\nvoid arm_negate_q7(\n q7_t * pSrc,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n q7_t in;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t input; /* Input values1-4 */\n q31_t zero = 0x00000000;\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Read four inputs */\n input = *__SIMD32(pSrc)++;\n\n /* Store the Negated results in the destination buffer in a single cycle by packing the results */\n *__SIMD32(pDst)++ = __QSUB8(zero, input);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = -A */\n /* Negate and then store the results in the destination buffer. */ \\\n in = *pSrc++;\n *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of negate group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_offset_f32.c \n* \n* Description:\tFloating-point vector offset. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup offset Vector Offset \n * \n * Adds a constant offset to each element of a vector. \n * \n * 
        \n *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        \n *
\n * \n * The functions support in-place computation allowing the source and\n * destination pointers to reference the same memory buffer.\n * There are separate functions for floating-point, Q7, Q15, and Q31 data types.\n */\n\n/** \n * @addtogroup offset \n * @{ \n */\n\n/** \n * @brief Adds a constant offset to a floating-point vector. \n * @param[in] *pSrc points to the input vector \n * @param[in] offset is the offset to be added \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n */\n\n\nvoid arm_offset_f32(\n float32_t * pSrc,\n float32_t offset,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t in1, in2, in3, in4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination buffer. */\n /* read samples from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n\n /* add offset to input */\n in1 = in1 + offset;\n\n /* read samples from source */\n in3 = *(pSrc + 2);\n\n /* add offset to input */\n in2 = in2 + offset;\n\n /* read samples from source */\n in4 = *(pSrc + 3);\n\n /* add offset to input */\n in3 = in3 + offset;\n\n /* store result to destination */\n *pDst = in1;\n\n /* add offset to input */\n in4 = in4 + offset;\n\n /* store result to destination */\n *(pDst + 1) = in2;\n\n /* store result to destination */\n *(pDst + 2) = in3;\n\n /* store result to destination */\n *(pDst + 3) = in4;\n\n /* update pointers to process next samples */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the result in the destination buffer. */\n *pDst++ = (*pSrc++) + offset;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of offset group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_offset_q15.c \n* \n* Description:\tQ15 vector offset. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup offset \n * @{ \n */\n\n/** \n * @brief Adds a constant offset to a Q15 vector. \n * @param[in] *pSrc points to the input vector \n * @param[in] offset is the offset to be added \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. \n */\n\nvoid arm_offset_q15(\n q15_t * pSrc,\n q15_t offset,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t offset_packed; /* Offset packed to 32 bit */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* Offset is packed to 32 bit in order to use SIMD32 for addition */\n offset_packed = __PKHBT(offset, offset, 16);\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination buffer, 2 samples at a time. */\n *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);\n *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination buffer. */\n *pDst++ = (q15_t) __QADD16(*pSrc++, offset);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination buffer. */\n *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of offset group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_offset_q31.c \n* \n* Description:\tQ31 vector offset. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup offset \n * @{ \n */\n\n/** \n * @brief Adds a constant offset to a Q31 vector. \n * @param[in] *pSrc points to the input vector \n * @param[in] offset is the offset to be added \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. \n */\n\nvoid arm_offset_q31(\n q31_t * pSrc,\n q31_t offset,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t in1, in2, in3, in4;\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination buffer. */\n in1 = *pSrc++;\n in2 = *pSrc++;\n in3 = *pSrc++;\n in4 = *pSrc++;\n\n *pDst++ = __QADD(in1, offset);\n *pDst++ = __QADD(in2, offset);\n *pDst++ = __QADD(in3, offset);\n *pDst++ = __QADD(in4, offset);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the result in the destination buffer. */\n *pDst++ = __QADD(*pSrc++, offset);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the result in the destination buffer. */\n *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of offset group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_offset_q7.c \n* \n* Description:\tQ7 vector offset. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup offset \n * @{ \n */\n\n/** \n * @brief Adds a constant offset to a Q7 vector. \n * @param[in] *pSrc points to the input vector \n * @param[in] offset is the offset to be added \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. \n */\n\nvoid arm_offset_q7(\n q7_t * pSrc,\n q7_t offset,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t offset_packed; /* Offset packed to 32 bit */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* Offset is packed to 32 bit in order to use SIMD32 for addition */\n offset_packed = __PACKq7(offset, offset, offset, offset);\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */\n *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the result in the destination buffer. */\n *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A + offset */\n /* Add offset and then store the result in the destination buffer. */\n *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of offset group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_scale_f32.c \n* \n* Description:\tMultiplies a floating-point vector by a scalar. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup scale Vector Scale \n * \n * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: \n * \n * 
        \n *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        \n *
\n * \n * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by \n * a fractional multiplication scaleFract and an arithmetic shift shift. \n * The shift allows the gain of the scaling operation to exceed 1.0. \n * The algorithm used with fixed-point data is: \n * \n * 
        \n *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        \n *
\n * \n * The overall scale factor applied to the fixed-point data is \n * 
        \n *     scale = scaleFract * 2^shift.        \n *
\n *\n * The functions support in-place computation allowing the source and destination\n * pointers to reference the same memory buffer.\n */\n\n/** \n * @addtogroup scale \n * @{ \n */\n\n/** \n * @brief Multiplies a floating-point vector by a scalar. \n * @param[in] *pSrc points to the input vector \n * @param[in] scale scale factor to be applied \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n */\n\n\nvoid arm_scale_f32(\n float32_t * pSrc,\n float32_t scale,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t in1, in2, in3, in4; /* temporary variabels */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the results in the destination buffer. */\n /* read input samples from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n\n /* multiply with scaling factor */\n in1 = in1 * scale;\n\n /* read input sample from source */\n in3 = *(pSrc + 2);\n\n /* multiply with scaling factor */\n in2 = in2 * scale;\n\n /* read input sample from source */\n in4 = *(pSrc + 3);\n\n /* multiply with scaling factor */\n in3 = in3 * scale;\n in4 = in4 * scale;\n /* store the result to destination */\n *pDst = in1;\n *(pDst + 1) = in2;\n *(pDst + 2) = in3;\n *(pDst + 3) = in4;\n\n /* update pointers to process next samples */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the result in the destination buffer. */\n *pDst++ = (*pSrc++) * scale;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of scale group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_scale_q15.c \n* \n* Description:\tMultiplies a Q15 vector by a scalar. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup scale \n * @{ \n */\n\n/** \n * @brief Multiplies a Q15 vector by a scalar. \n * @param[in] *pSrc points to the input vector \n * @param[in] scaleFract fractional portion of the scale value \n * @param[in] shift number of bits to shift the result by \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The input data *pSrc and scaleFract are in 1.15 format. \n * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. \n */\n\n\nvoid arm_scale_q15(\n q15_t * pSrc,\n q15_t scaleFract,\n int8_t shift,\n q15_t * pDst,\n uint32_t blockSize)\n{\n int8_t kShift = 15 - shift; /* shift to apply after scaling */\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q15_t in1, in2, in3, in4;\n q31_t inA1, inA2; /* Temporary variables */\n q31_t out1, out2, out3, out4;\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* Reading 2 inputs from memory */\n inA1 = *__SIMD32(pSrc)++;\n inA2 = *__SIMD32(pSrc)++;\n\n /* C = A * scale */\n /* Scale the inputs and then store the 2 results in the destination buffer \n * in single cycle by packing the outputs */\n out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);\n out2 = (q31_t) ((q15_t) inA1 * scaleFract);\n out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);\n out4 = (q31_t) ((q15_t) inA2 * scaleFract);\n\n /* apply shifting */\n out1 = out1 >> kShift;\n out2 = out2 >> kShift;\n out3 = out3 >> kShift;\n out4 = out4 >> kShift;\n\n /* saturate the output */\n in1 = (q15_t) (__SSAT(out1, 16));\n in2 = (q15_t) (__SSAT(out2, 16));\n in3 = (q15_t) (__SSAT(out3, 16));\n in4 = (q15_t) (__SSAT(out4, 16));\n\n /* store the result to destination */\n *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);\n *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the result in the destination buffer. */\n *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the result in the destination buffer. */\n *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of scale group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_scale_q31.c \n* \n* Description:\tMultiplies a Q31 vector by a scalar. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup scale \n * @{ \n */\n\n/** \n * @brief Multiplies a Q31 vector by a scalar. \n * @param[in] *pSrc points to the input vector \n * @param[in] scaleFract fractional portion of the scale value \n * @param[in] shift number of bits to shift the result by \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The input data *pSrc and scaleFract are in 1.31 format. \n * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. \n */\n\nvoid arm_scale_q31(\n q31_t * pSrc,\n q31_t scaleFract,\n int8_t shift,\n q31_t * pDst,\n uint32_t blockSize)\n{\n int8_t kShift = shift + 1; /* Shift to apply after scaling */\n int8_t sign = (kShift & 0x80);\n uint32_t blkCnt; /* loop counter */\n q31_t in, out;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n q31_t in1, in2, in3, in4; /* temporary input variables */\n q31_t out1, out2, out3, out4; /* temporary output variabels */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n if(sign == 0u)\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* read four inputs from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n /* multiply input with scaler value */\n in1 = ((q63_t) in1 * scaleFract) >> 32;\n in2 = ((q63_t) in2 * scaleFract) >> 32;\n in3 = ((q63_t) in3 * scaleFract) >> 32;\n in4 = ((q63_t) in4 * scaleFract) >> 32;\n\n /* apply shifting */\n out1 = in1 << kShift;\n out2 = in2 << kShift;\n\n /* saturate the results. */\n if(in1 != (out1 >> kShift))\n out1 = 0x7FFFFFFF ^ (in1 >> 31);\n\n if(in2 != (out2 >> kShift))\n out2 = 0x7FFFFFFF ^ (in2 >> 31);\n\n out3 = in3 << kShift;\n out4 = in4 << kShift;\n\n *pDst = out1;\n *(pDst + 1) = out2;\n\n if(in3 != (out3 >> kShift))\n out3 = 0x7FFFFFFF ^ (in3 >> 31);\n\n if(in4 != (out4 >> kShift))\n out4 = 0x7FFFFFFF ^ (in4 >> 31);\n\n /* Store result destination */\n *(pDst + 2) = out3;\n *(pDst + 3) = out4;\n\n /* Update pointers to process next sampels */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n }\n else\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* read four inputs from source */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n /* multiply input with scaler value */\n in1 = ((q63_t) in1 * scaleFract) >> 32;\n in2 = ((q63_t) in2 * scaleFract) >> 32;\n in3 = ((q63_t) in3 * scaleFract) >> 32;\n in4 = ((q63_t) in4 * scaleFract) >> 32;\n\n /* apply shifting */\n out1 = in1 >> -kShift;\n out2 = in2 >> -kShift;\n\n out3 = in3 >> -kShift;\n out4 = in4 >> -kShift;\n\n /* Store result destination */\n *pDst = out1;\n *(pDst + 1) = out2;\n\n *(pDst + 2) = out3;\n *(pDst + 3) = out4;\n\n /* Update pointers to process next sampels */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n if(sign == 0)\n {\n\t while(blkCnt > 0u)\n\t {\n\t\t/* C = A * scale */\n\t\t/* Scale the input and then store the result in the destination buffer. */\n\t\tin = *pSrc++;\n\t\tin = ((q63_t) in * scaleFract) >> 32;\n\n\t\tout = in << kShift;\n\t\t\n\t\tif(in != (out >> kShift))\n\t\t\tout = 0x7FFFFFFF ^ (in >> 31);\n\n\t\t*pDst++ = out;\n\n\t\t/* Decrement the loop counter */\n\t\tblkCnt--;\n\t }\n }\n else\n {\n\t while(blkCnt > 0u)\n\t {\n\t\t/* C = A * scale */\n\t\t/* Scale the input and then store the result in the destination buffer. */\n\t\tin = *pSrc++;\n\t\tin = ((q63_t) in * scaleFract) >> 32;\n\n\t\tout = in >> -kShift;\n\n\t\t*pDst++ = out;\n\n\t\t/* Decrement the loop counter */\n\t\tblkCnt--;\n\t }\n \n }\n}\n\n/** \n * @} end of scale group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_scale_q7.c \n* \n* Description:\tMultiplies a Q7 vector by a scalar. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup scale \n * @{ \n */\n\n/** \n * @brief Multiplies a Q7 vector by a scalar. \n * @param[in] *pSrc points to the input vector \n * @param[in] scaleFract fractional portion of the scale value \n * @param[in] shift number of bits to shift the result by \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The input data *pSrc and scaleFract are in 1.7 format. \n * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. \n */\n\nvoid arm_scale_q7(\n q7_t * pSrc,\n q7_t scaleFract,\n int8_t shift,\n q7_t * pDst,\n uint32_t blockSize)\n{\n int8_t kShift = 7 - shift; /* shift to apply after scaling */\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* Reading 4 inputs from memory */\n in1 = *pSrc++;\n in2 = *pSrc++;\n in3 = *pSrc++;\n in4 = *pSrc++;\n\n /* C = A * scale */\n /* Scale the inputs and then store the results in the temporary variables. */\n out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));\n out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));\n out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));\n out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));\n\n /* Packing the individual outputs into 32bit and storing in \n * destination buffer in single write */\n *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the result in the destination buffer. */\n *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A * scale */\n /* Scale the input and then store the result in the destination buffer. */\n *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of scale group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_shift_q15.c \n* \n* Description:\tShifts the elements of a Q15 vector by a specified number of bits. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup shift \n * @{ \n */\n\n/** \n * @brief Shifts the elements of a Q15 vector a specified number of bits. \n * @param[in] *pSrc points to the input vector \n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. \n */\n\nvoid arm_shift_q15(\n q15_t * pSrc,\n int8_t shiftBits,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n uint8_t sign; /* Sign of shiftBits */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n q15_t in1, in2; /* Temporary variables */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* Getting the sign of shiftBits */\n sign = (shiftBits & 0x80);\n\n /* If the shift value is positive then do right shift else left shift */\n if(sign == 0u)\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* Read 2 inputs */\n in1 = *pSrc++;\n in2 = *pSrc++;\n /* C = A << shiftBits */\n /* Shift the inputs and then store the results in the destination buffer. */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),\n __SSAT((in2 << shiftBits), 16), 16);\n\n#else\n\n *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),\n __SSAT((in1 << shiftBits), 16), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n in1 = *pSrc++;\n in2 = *pSrc++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),\n __SSAT((in2 << shiftBits), 16), 16);\n\n#else\n\n *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),\n __SSAT((in1 << shiftBits), 16), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Shift and then store the results in the destination buffer. */\n *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n else\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* Read 2 inputs */\n in1 = *pSrc++;\n in2 = *pSrc++;\n\n /* C = A >> shiftBits */\n /* Shift the inputs and then store the results in the destination buffer. */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),\n (in2 >> -shiftBits), 16);\n\n#else\n\n *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),\n (in1 >> -shiftBits), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n in1 = *pSrc++;\n in2 = *pSrc++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),\n (in2 >> -shiftBits), 16);\n\n#else\n\n *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),\n (in1 >> -shiftBits), 16);\n\n#endif /* #ifndef ARM_MATH_BIG_ENDIAN */\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Shift the inputs and then store the results in the destination buffer. */\n *pDst++ = (*pSrc++ >> -shiftBits);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Getting the sign of shiftBits */\n sign = (shiftBits & 0x80);\n\n /* If the shift value is positive then do right shift else left shift */\n if(sign == 0u)\n {\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Shift and then store the results in the destination buffer. */\n *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n else\n {\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Shift the inputs and then store the results in the destination buffer. */\n *pDst++ = (*pSrc++ >> -shiftBits);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of shift group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_shift_q31.c \n* \n* Description:\tShifts the elements of a Q31 vector by a specified number of bits. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n/** \n * @defgroup shift Vector Shift \n * \n * Shifts the elements of a fixed-point vector by a specified number of bits. \n * There are separate functions for Q7, Q15, and Q31 data types. \n * The underlying algorithm used is: \n * \n * 
        \n *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        \n *
\n * \n * If shift is positive then the elements of the vector are shifted to the left. \n * If shift is negative then the elements of the vector are shifted to the right. \n *\n * The functions support in-place computation allowing the source and destination\n * pointers to reference the same memory buffer.\n */\n\n/** \n * @addtogroup shift \n * @{ \n */\n\n/** \n * @brief Shifts the elements of a Q31 vector a specified number of bits. \n * @param[in] *pSrc points to the input vector \n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. \n */\n\nvoid arm_shift_q31(\n q31_t * pSrc,\n int8_t shiftBits,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n q31_t in1, in2, in3, in4; /* Temporary input variables */\n q31_t out1, out2, out3, out4; /* Temporary output variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n\n if(sign == 0u)\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Shift the input and then store the results in the destination buffer. */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n out1 = in1 << shiftBits;\n in3 = *(pSrc + 2);\n out2 = in2 << shiftBits;\n in4 = *(pSrc + 3);\n if(in1 != (out1 >> shiftBits))\n out1 = 0x7FFFFFFF ^ (in1 >> 31);\n\n if(in2 != (out2 >> shiftBits))\n out2 = 0x7FFFFFFF ^ (in2 >> 31);\n\n *pDst = out1;\n out3 = in3 << shiftBits;\n *(pDst + 1) = out2;\n out4 = in4 << shiftBits;\n\n if(in3 != (out3 >> shiftBits))\n out3 = 0x7FFFFFFF ^ (in3 >> 31);\n\n if(in4 != (out4 >> shiftBits))\n out4 = 0x7FFFFFFF ^ (in4 >> 31);\n\n *(pDst + 2) = out3;\n *(pDst + 3) = out4;\n\n /* Update destination pointer to process next sampels */\n pSrc += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n else\n {\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Shift the input and then store the results in the destination buffer. */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n *pDst = (in1 >> -shiftBits);\n *(pDst + 1) = (in2 >> -shiftBits);\n *(pDst + 2) = (in3 >> -shiftBits);\n *(pDst + 3) = (in4 >> -shiftBits);\n\n\n pSrc += 4u;\n pDst += 4u;\n\n blkCnt--;\n }\n\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n while(blkCnt > 0u)\n {\n /* C = A (>> or <<) shiftBits */\n /* Shift the input and then store the result in the destination buffer. */\n *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :\n (*pSrc++ >> -shiftBits);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n\n}\n\n/** \n * @} end of shift group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_shift_q7.c \n* \n* Description:\tProcessing function for the Q7 Shifting \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup shift \n * @{ \n */\n\n\n/** \n * @brief Shifts the elements of a Q7 vector a specified number of bits. \n * @param[in] *pSrc points to the input vector \n * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in the vector \n * @return none. \n * \n * \\par Conditions for optimum performance \n * Input and output buffers should be aligned by 32-bit \n * \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. \n */\n\nvoid arm_shift_q7(\n q7_t * pSrc,\n int8_t shiftBits,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n uint8_t sign; /* Sign of shiftBits */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q7_t in1; /* Input value1 */\n q7_t in2; /* Input value2 */\n q7_t in3; /* Input value3 */\n q7_t in4; /* Input value4 */\n\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* Getting the sign of shiftBits */\n sign = (shiftBits & 0x80);\n\n /* If the shift value is positive then do right shift else left shift */\n if(sign == 0u)\n {\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Read 4 inputs */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */\n *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),\n __SSAT((in2 << shiftBits), 8),\n __SSAT((in3 << shiftBits), 8),\n __SSAT((in4 << shiftBits), 8));\n /* Update source pointer to process next sampels */\n pSrc += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Shift the input and then store the result in the destination buffer. */\n *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n else\n {\n shiftBits = -shiftBits;\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Read 4 inputs */\n in1 = *pSrc;\n in2 = *(pSrc + 1);\n in3 = *(pSrc + 2);\n in4 = *(pSrc + 3);\n\n /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */\n *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),\n (in3 >> shiftBits), (in4 >> shiftBits));\n\n\n pSrc += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Shift the input and then store the result in the destination buffer. */\n in1 = *pSrc++;\n *pDst++ = (in1 >> shiftBits);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Getting the sign of shiftBits */\n sign = (shiftBits & 0x80);\n\n /* If the shift value is positive then do right shift else left shift */\n if(sign == 0u)\n {\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A << shiftBits */\n /* Shift the input and then store the result in the destination buffer. */\n *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n else\n {\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A >> shiftBits */\n /* Shift the input and then store the result in the destination buffer. */\n *pDst++ = (*pSrc++ >> -shiftBits);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n}\n\n/** \n * @} end of shift group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_sub_f32.c \n* \n* Description:\tFloating-point vector subtraction. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @defgroup BasicSub Vector Subtraction \n * \n * Element-by-element subtraction of two vectors. \n * \n * 
        \n *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        \n *
\n * \n * There are separate functions for floating-point, Q7, Q15, and Q31 data types. \n */\n\n/** \n * @addtogroup BasicSub \n * @{ \n */\n\n\n/** \n * @brief Floating-point vector subtraction. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n */\n\nvoid arm_sub_f32(\n float32_t * pSrcA,\n float32_t * pSrcB,\n float32_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n float32_t inA1, inA2, inA3, inA4; /* temporary variables */\n float32_t inB1, inB2, inB3, inB4; /* temporary variables */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the results in the destination buffer. */\n /* Read 4 input samples from sourceA and sourceB */\n inA1 = *pSrcA;\n inB1 = *pSrcB;\n inA2 = *(pSrcA + 1);\n inB2 = *(pSrcB + 1);\n inA3 = *(pSrcA + 2);\n inB3 = *(pSrcB + 2);\n inA4 = *(pSrcA + 3);\n inB4 = *(pSrcB + 3);\n\n /* dst = srcA - srcB */\n /* subtract and store the result */\n *pDst = inA1 - inB1;\n *(pDst + 1) = inA2 - inB2;\n *(pDst + 2) = inA3 - inB3;\n *(pDst + 3) = inA4 - inB4;\n\n\n /* Update pointers to process next sampels */\n pSrcA += 4u;\n pSrcB += 4u;\n pDst += 4u;\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the results in the destination buffer. */\n *pDst++ = (*pSrcA++) - (*pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n}\n\n/** \n * @} end of BasicSub group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_sub_q15.c \n* \n* Description:\tQ15 vector subtraction. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicSub \n * @{ \n */\n\n/** \n * @brief Q15 vector subtraction. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. \n */\n\nvoid arm_sub_q15(\n q15_t * pSrcA,\n q15_t * pSrcB,\n q15_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2;\n q31_t inB1, inB2;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the results in the destination buffer two samples at a time. */\n inA1 = *__SIMD32(pSrcA)++;\n inA2 = *__SIMD32(pSrcA)++;\n inB1 = *__SIMD32(pSrcB)++;\n inB2 = *__SIMD32(pSrcB)++;\n\n *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);\n *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n}\n\n/** \n * @} end of BasicSub group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_sub_q31.c \n* \n* Description:\tQ31 vector subtraction. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicSub \n * @{ \n */\n\n/** \n * @brief Q31 vector subtraction. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. \n */\n\nvoid arm_sub_q31(\n q31_t * pSrcA,\n q31_t * pSrcB,\n q31_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n q31_t inA1, inA2, inA3, inA4;\n q31_t inB1, inB2, inB3, inB4;\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the results in the destination buffer. */\n inA1 = *pSrcA++;\n inA2 = *pSrcA++;\n inB1 = *pSrcB++;\n inB2 = *pSrcB++;\n\n inA3 = *pSrcA++;\n inA4 = *pSrcA++;\n inB3 = *pSrcB++;\n inB4 = *pSrcB++;\n\n *pDst++ = __QSUB(inA1, inB1);\n *pDst++ = __QSUB(inA2, inB2);\n *pDst++ = __QSUB(inA3, inB3);\n *pDst++ = __QSUB(inA4, inB4);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = __QSUB(*pSrcA++, *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/** \n * @} end of BasicSub group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_sub_q7.c \n* \n* Description:\tQ7 vector subtraction. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupMath \n */\n\n/** \n * @addtogroup BasicSub \n * @{ \n */\n\n/** \n * @brief Q7 vector subtraction. \n * @param[in] *pSrcA points to the first input vector \n * @param[in] *pSrcB points to the second input vector \n * @param[out] *pDst points to the output vector \n * @param[in] blockSize number of samples in each vector \n * @return none. \n * \n * Scaling and Overflow Behavior: \n * \\par \n * The function uses saturating arithmetic. \n * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. \n */\n\nvoid arm_sub_q7(\n q7_t * pSrcA,\n q7_t * pSrcB,\n q7_t * pDst,\n uint32_t blockSize)\n{\n uint32_t blkCnt; /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n /*loop Unrolling */\n blkCnt = blockSize >> 2u;\n\n /* First part of the processing with loop unrolling. Compute 4 outputs at a time. \n ** a second loop below computes the remaining 1 to 3 samples. */\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the results in the destination buffer 4 samples at a time. */\n *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n /* If the blockSize is not a multiple of 4, compute any remaining output samples here. \n ** No loop unrolling is used. */\n blkCnt = blockSize % 0x4u;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#else\n\n /* Run the below code for Cortex-M0 */\n\n /* Initialize blkCnt with number of samples */\n blkCnt = blockSize;\n\n while(blkCnt > 0u)\n {\n /* C = A - B */\n /* Subtract and then store the result in the destination buffer. */\n *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);\n\n /* Decrement the loop counter */\n blkCnt--;\n }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n}\n\n/** \n * @} end of BasicSub group \n */\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013 \n* $Revision: \tV1.4.1 \n* \n* Project: \t CMSIS DSP Library \n* Title:\t arm_common_tables.c \n* \n* Description:\tThis file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/** \n * @ingroup groupTransforms \n */\n\n/** \n * @addtogroup CFFT_CIFFT Complex FFT Tables \n * @{ \n */\n\n/** \n* \\par \n* Pseudo code for Generation of Bit reversal Table is \n* \\par \n* 
for(l=1;l <= N/4;l++)    \n* {    \n*   for(i=0;i> 1;    \n*  }
\n* \\par \n* where N = 4096\tlogN2 = 12 \n* \\par \n* N is the maximum FFT Size supported \n*/\n\n/* \n* @brief Table for bit reversal process \n*/\nconst uint16_t armBitRevTable[1024] = {\n 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700,\n 0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380,\n 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540,\n 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0,\n 0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620,\n 0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0,\n 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460,\n 0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0,\n 0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0,\n 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,\n 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590,\n 0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150,\n 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0,\n 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230,\n 0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0,\n 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70,\n 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770,\n 0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0,\n 0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508,\n 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,\n 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648,\n 0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8,\n 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428,\n 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8,\n 0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8,\n 0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368,\n 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8,\n 0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118,\n 0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698,\n 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,\n 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8,\n 0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38,\n 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738,\n 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8,\n 0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578,\n 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8,\n 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604,\n 0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284,\n 0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444,\n 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,\n 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4,\n 0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324,\n 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4,\n 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164,\n 0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4,\n 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214,\n 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494,\n 0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54,\n 0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754,\n 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,\n 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534,\n 0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4,\n 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674,\n 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4,\n 0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c,\n 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c,\n 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c,\n 0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c,\n 0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc,\n 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,\n 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac,\n 0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c,\n 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec,\n 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c,\n 0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c,\n 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c,\n 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c,\n 0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc,\n 0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c,\n 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,\n 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c,\n 0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc,\n 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc,\n 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302,\n 0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582,\n 0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142,\n 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2,\n 0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222,\n 0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2,\n 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,\n 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762,\n 0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2,\n 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512,\n 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192,\n 0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652,\n 0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2,\n 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432,\n 0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2,\n 0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2,\n 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,\n 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2,\n 0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a,\n 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a,\n 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a,\n 0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca,\n 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a,\n 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a,\n 0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa,\n 0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a,\n 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,\n 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a,\n 0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a,\n 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a,\n 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda,\n 0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da,\n 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a,\n 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba,\n 0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a,\n 0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa,\n 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,\n 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486,\n 0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46,\n 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746,\n 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6,\n 0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526,\n 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6,\n 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666,\n 0x166, 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6,\n 0x6e6, 0x1e6, 0x5e6, 0x3e6, 0x7e6, 0x16, 0x416,\n 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,\n 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796,\n 0x56, 0x456, 0x256, 0x656, 0x156, 0x556, 0x356,\n 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 0x5d6,\n 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136,\n 0x536, 0x336, 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6,\n 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 0x476, 0x276,\n 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6,\n 0x2f6, 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe,\n 0x40e, 0x20e, 0x60e, 0x10e, 0x50e, 0x30e, 0x70e,\n 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,\n 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e,\n 0x34e, 0x74e, 0xce, 0x4ce, 0x2ce, 0x6ce, 0x1ce,\n 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 0x62e,\n 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae,\n 0x6ae, 0x1ae, 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e,\n 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 0x76e, 0xee,\n 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee,\n 0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e,\n 0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e,\n 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,\n 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de,\n 0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e,\n 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be,\n 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e,\n 0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e,\n 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe,\n 0x7fe, 0x1\n};\n\n\n/* \n* @brief Floating-point Twiddle factors Table Generation \n*/\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_16[32] = {\n 1.000000000f, 0.000000000f,\n 0.923879533f, 0.382683432f,\n 0.707106781f, 0.707106781f,\n 0.382683432f, 0.923879533f,\n 0.000000000f, 1.000000000f,\n -0.382683432f, 0.923879533f,\n -0.707106781f, 0.707106781f,\n -0.923879533f, 0.382683432f,\n -1.000000000f, 0.000000000f,\n -0.923879533f, -0.382683432f,\n -0.707106781f, -0.707106781f,\n -0.382683432f, -0.923879533f,\n -0.000000000f, -1.000000000f,\n 0.382683432f, -0.923879533f,\n 0.707106781f, -0.707106781f,\n 0.923879533f, -0.382683432f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_32[64] = {\n 1.000000000f, 0.000000000f,\n 0.980785280f, 0.195090322f,\n 0.923879533f, 0.382683432f,\n 0.831469612f, 0.555570233f,\n 0.707106781f, 0.707106781f,\n 0.555570233f, 0.831469612f,\n 0.382683432f, 0.923879533f,\n 0.195090322f, 0.980785280f,\n 0.000000000f, 1.000000000f,\n -0.195090322f, 0.980785280f,\n -0.382683432f, 0.923879533f,\n -0.555570233f, 0.831469612f,\n -0.707106781f, 0.707106781f,\n -0.831469612f, 0.555570233f,\n -0.923879533f, 0.382683432f,\n -0.980785280f, 0.195090322f,\n -1.000000000f, 0.000000000f,\n -0.980785280f, -0.195090322f,\n -0.923879533f, -0.382683432f,\n -0.831469612f, -0.555570233f,\n -0.707106781f, -0.707106781f,\n -0.555570233f, -0.831469612f,\n -0.382683432f, -0.923879533f,\n -0.195090322f, -0.980785280f,\n -0.000000000f, -1.000000000f,\n 0.195090322f, -0.980785280f,\n 0.382683432f, -0.923879533f,\n 0.555570233f, -0.831469612f,\n 0.707106781f, -0.707106781f,\n 0.831469612f, -0.555570233f,\n 0.923879533f, -0.382683432f,\n 0.980785280f, -0.195090322f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_64[128] = {\n 1.000000000f, 0.000000000f,\n 0.995184727f, 0.098017140f,\n 0.980785280f, 0.195090322f,\n 0.956940336f, 0.290284677f,\n 0.923879533f, 0.382683432f,\n 0.881921264f, 0.471396737f,\n 0.831469612f, 0.555570233f,\n 0.773010453f, 0.634393284f,\n 0.707106781f, 0.707106781f,\n 0.634393284f, 0.773010453f,\n 0.555570233f, 0.831469612f,\n 0.471396737f, 0.881921264f,\n 0.382683432f, 0.923879533f,\n 0.290284677f, 0.956940336f,\n 0.195090322f, 0.980785280f,\n 0.098017140f, 0.995184727f,\n 0.000000000f, 1.000000000f,\n -0.098017140f, 0.995184727f,\n -0.195090322f, 0.980785280f,\n -0.290284677f, 0.956940336f,\n -0.382683432f, 0.923879533f,\n -0.471396737f, 0.881921264f,\n -0.555570233f, 0.831469612f,\n -0.634393284f, 0.773010453f,\n -0.707106781f, 0.707106781f,\n -0.773010453f, 0.634393284f,\n -0.831469612f, 0.555570233f,\n -0.881921264f, 0.471396737f,\n -0.923879533f, 0.382683432f,\n -0.956940336f, 0.290284677f,\n -0.980785280f, 0.195090322f,\n -0.995184727f, 0.098017140f,\n -1.000000000f, 0.000000000f,\n -0.995184727f, -0.098017140f,\n -0.980785280f, -0.195090322f,\n -0.956940336f, -0.290284677f,\n -0.923879533f, -0.382683432f,\n -0.881921264f, -0.471396737f,\n -0.831469612f, -0.555570233f,\n -0.773010453f, -0.634393284f,\n -0.707106781f, -0.707106781f,\n -0.634393284f, -0.773010453f,\n -0.555570233f, -0.831469612f,\n -0.471396737f, -0.881921264f,\n -0.382683432f, -0.923879533f,\n -0.290284677f, -0.956940336f,\n -0.195090322f, -0.980785280f,\n -0.098017140f, -0.995184727f,\n -0.000000000f, -1.000000000f,\n 0.098017140f, -0.995184727f,\n 0.195090322f, -0.980785280f,\n 0.290284677f, -0.956940336f,\n 0.382683432f, -0.923879533f,\n 0.471396737f, -0.881921264f,\n 0.555570233f, -0.831469612f,\n 0.634393284f, -0.773010453f,\n 0.707106781f, -0.707106781f,\n 0.773010453f, -0.634393284f,\n 0.831469612f, -0.555570233f,\n 0.881921264f, -0.471396737f,\n 0.923879533f, -0.382683432f,\n 0.956940336f, -0.290284677f,\n 0.980785280f, -0.195090322f,\n 0.995184727f, -0.098017140f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\n\nconst float32_t twiddleCoef_128[256] = {\n1.000000000f\t,\t0.000000000f\t,\n0.998795456f\t,\t0.049067674f\t,\n0.995184727f\t,\t0.098017140f\t,\n0.989176510f\t,\t0.146730474f\t,\n0.980785280f\t,\t0.195090322f\t,\n0.970031253f\t,\t0.242980180f\t,\n0.956940336f\t,\t0.290284677f\t,\n0.941544065f\t,\t0.336889853f\t,\n0.923879533f\t,\t0.382683432f\t,\n0.903989293f\t,\t0.427555093f\t,\n0.881921264f\t,\t0.471396737f\t,\n0.857728610f\t,\t0.514102744f\t,\n0.831469612f\t,\t0.555570233f\t,\n0.803207531f\t,\t0.595699304f\t,\n0.773010453f\t,\t0.634393284f\t,\n0.740951125f\t,\t0.671558955f\t,\n0.707106781f\t,\t0.707106781f\t,\n0.671558955f\t,\t0.740951125f\t,\n0.634393284f\t,\t0.773010453f\t,\n0.595699304f\t,\t0.803207531f\t,\n0.555570233f\t,\t0.831469612f\t,\n0.514102744f\t,\t0.857728610f\t,\n0.471396737f\t,\t0.881921264f\t,\n0.427555093f\t,\t0.903989293f\t,\n0.382683432f\t,\t0.923879533f\t,\n0.336889853f\t,\t0.941544065f\t,\n0.290284677f\t,\t0.956940336f\t,\n0.242980180f\t,\t0.970031253f\t,\n0.195090322f\t,\t0.980785280f\t,\n0.146730474f\t,\t0.989176510f\t,\n0.098017140f\t,\t0.995184727f\t,\n0.049067674f\t,\t0.998795456f\t,\n0.000000000f\t,\t1.000000000f\t,\n-0.049067674f\t,\t0.998795456f\t,\n-0.098017140f\t,\t0.995184727f\t,\n-0.146730474f\t,\t0.989176510f\t,\n-0.195090322f\t,\t0.980785280f\t,\n-0.242980180f\t,\t0.970031253f\t,\n-0.290284677f\t,\t0.956940336f\t,\n-0.336889853f\t,\t0.941544065f\t,\n-0.382683432f\t,\t0.923879533f\t,\n-0.427555093f\t,\t0.903989293f\t,\n-0.471396737f\t,\t0.881921264f\t,\n-0.514102744f\t,\t0.857728610f\t,\n-0.555570233f\t,\t0.831469612f\t,\n-0.595699304f\t,\t0.803207531f\t,\n-0.634393284f\t,\t0.773010453f\t,\n-0.671558955f\t,\t0.740951125f\t,\n-0.707106781f\t,\t0.707106781f\t,\n-0.740951125f\t,\t0.671558955f\t,\n-0.773010453f\t,\t0.634393284f\t,\n-0.803207531f\t,\t0.595699304f\t,\n-0.831469612f\t,\t0.555570233f\t,\n-0.857728610f\t,\t0.514102744f\t,\n-0.881921264f\t,\t0.471396737f\t,\n-0.903989293f\t,\t0.427555093f\t,\n-0.923879533f\t,\t0.382683432f\t,\n-0.941544065f\t,\t0.336889853f\t,\n-0.956940336f\t,\t0.290284677f\t,\n-0.970031253f\t,\t0.242980180f\t,\n-0.980785280f\t,\t0.195090322f\t,\n-0.989176510f\t,\t0.146730474f\t,\n-0.995184727f\t,\t0.098017140f\t,\n-0.998795456f\t,\t0.049067674f\t,\n-1.000000000f\t,\t0.000000000f\t,\n-0.998795456f\t,\t-0.049067674f\t,\n-0.995184727f\t,\t-0.098017140f\t,\n-0.989176510f\t,\t-0.146730474f\t,\n-0.980785280f\t,\t-0.195090322f\t,\n-0.970031253f\t,\t-0.242980180f\t,\n-0.956940336f\t,\t-0.290284677f\t,\n-0.941544065f\t,\t-0.336889853f\t,\n-0.923879533f\t,\t-0.382683432f\t,\n-0.903989293f\t,\t-0.427555093f\t,\n-0.881921264f\t,\t-0.471396737f\t,\n-0.857728610f\t,\t-0.514102744f\t,\n-0.831469612f\t,\t-0.555570233f\t,\n-0.803207531f\t,\t-0.595699304f\t,\n-0.773010453f\t,\t-0.634393284f\t,\n-0.740951125f\t,\t-0.671558955f\t,\n-0.707106781f\t,\t-0.707106781f\t,\n-0.671558955f\t,\t-0.740951125f\t,\n-0.634393284f\t,\t-0.773010453f\t,\n-0.595699304f\t,\t-0.803207531f\t,\n-0.555570233f\t,\t-0.831469612f\t,\n-0.514102744f\t,\t-0.857728610f\t,\n-0.471396737f\t,\t-0.881921264f\t,\n-0.427555093f\t,\t-0.903989293f\t,\n-0.382683432f\t,\t-0.923879533f\t,\n-0.336889853f\t,\t-0.941544065f\t,\n-0.290284677f\t,\t-0.956940336f\t,\n-0.242980180f\t,\t-0.970031253f\t,\n-0.195090322f\t,\t-0.980785280f\t,\n-0.146730474f\t,\t-0.989176510f\t,\n-0.098017140f\t,\t-0.995184727f\t,\n-0.049067674f\t,\t-0.998795456f\t,\n-0.000000000f\t,\t-1.000000000f\t,\n0.049067674f\t,\t-0.998795456f\t,\n0.098017140f\t,\t-0.995184727f\t,\n0.146730474f\t,\t-0.989176510f\t,\n0.195090322f\t,\t-0.980785280f\t,\n0.242980180f\t,\t-0.970031253f\t,\n0.290284677f\t,\t-0.956940336f\t,\n0.336889853f\t,\t-0.941544065f\t,\n0.382683432f\t,\t-0.923879533f\t,\n0.427555093f\t,\t-0.903989293f\t,\n0.471396737f\t,\t-0.881921264f\t,\n0.514102744f\t,\t-0.857728610f\t,\n0.555570233f\t,\t-0.831469612f\t,\n0.595699304f\t,\t-0.803207531f\t,\n0.634393284f\t,\t-0.773010453f\t,\n0.671558955f\t,\t-0.740951125f\t,\n0.707106781f\t,\t-0.707106781f\t,\n0.740951125f\t,\t-0.671558955f\t,\n0.773010453f\t,\t-0.634393284f\t,\n0.803207531f\t,\t-0.595699304f\t,\n0.831469612f\t,\t-0.555570233f\t,\n0.857728610f\t,\t-0.514102744f\t,\n0.881921264f\t,\t-0.471396737f\t,\n0.903989293f\t,\t-0.427555093f\t,\n0.923879533f\t,\t-0.382683432f\t,\n0.941544065f\t,\t-0.336889853f\t,\n0.956940336f\t,\t-0.290284677f\t,\n0.970031253f\t,\t-0.242980180f\t,\n0.980785280f\t,\t-0.195090322f\t,\n0.989176510f\t,\t-0.146730474f\t,\n0.995184727f\t,\t-0.098017140f\t,\n0.998795456f\t,\t-0.049067674f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_256[512] = {\n 1.000000000f, 0.000000000f,\n 0.999698819f, 0.024541229f,\n 0.998795456f, 0.049067674f,\n 0.997290457f, 0.073564564f,\n 0.995184727f, 0.098017140f,\n 0.992479535f, 0.122410675f,\n 0.989176510f, 0.146730474f,\n 0.985277642f, 0.170961889f,\n 0.980785280f, 0.195090322f,\n 0.975702130f, 0.219101240f,\n 0.970031253f, 0.242980180f,\n 0.963776066f, 0.266712757f,\n 0.956940336f, 0.290284677f,\n 0.949528181f, 0.313681740f,\n 0.941544065f, 0.336889853f,\n 0.932992799f, 0.359895037f,\n 0.923879533f, 0.382683432f,\n 0.914209756f, 0.405241314f,\n 0.903989293f, 0.427555093f,\n 0.893224301f, 0.449611330f,\n 0.881921264f, 0.471396737f,\n 0.870086991f, 0.492898192f,\n 0.857728610f, 0.514102744f,\n 0.844853565f, 0.534997620f,\n 0.831469612f, 0.555570233f,\n 0.817584813f, 0.575808191f,\n 0.803207531f, 0.595699304f,\n 0.788346428f, 0.615231591f,\n 0.773010453f, 0.634393284f,\n 0.757208847f, 0.653172843f,\n 0.740951125f, 0.671558955f,\n 0.724247083f, 0.689540545f,\n 0.707106781f, 0.707106781f,\n 0.689540545f, 0.724247083f,\n 0.671558955f, 0.740951125f,\n 0.653172843f, 0.757208847f,\n 0.634393284f, 0.773010453f,\n 0.615231591f, 0.788346428f,\n 0.595699304f, 0.803207531f,\n 0.575808191f, 0.817584813f,\n 0.555570233f, 0.831469612f,\n 0.534997620f, 0.844853565f,\n 0.514102744f, 0.857728610f,\n 0.492898192f, 0.870086991f,\n 0.471396737f, 0.881921264f,\n 0.449611330f, 0.893224301f,\n 0.427555093f, 0.903989293f,\n 0.405241314f, 0.914209756f,\n 0.382683432f, 0.923879533f,\n 0.359895037f, 0.932992799f,\n 0.336889853f, 0.941544065f,\n 0.313681740f, 0.949528181f,\n 0.290284677f, 0.956940336f,\n 0.266712757f, 0.963776066f,\n 0.242980180f, 0.970031253f,\n 0.219101240f, 0.975702130f,\n 0.195090322f, 0.980785280f,\n 0.170961889f, 0.985277642f,\n 0.146730474f, 0.989176510f,\n 0.122410675f, 0.992479535f,\n 0.098017140f, 0.995184727f,\n 0.073564564f, 0.997290457f,\n 0.049067674f, 0.998795456f,\n 0.024541229f, 0.999698819f,\n 0.000000000f, 1.000000000f,\n -0.024541229f, 0.999698819f,\n -0.049067674f, 0.998795456f,\n -0.073564564f, 0.997290457f,\n -0.098017140f, 0.995184727f,\n -0.122410675f, 0.992479535f,\n -0.146730474f, 0.989176510f,\n -0.170961889f, 0.985277642f,\n -0.195090322f, 0.980785280f,\n -0.219101240f, 0.975702130f,\n -0.242980180f, 0.970031253f,\n -0.266712757f, 0.963776066f,\n -0.290284677f, 0.956940336f,\n -0.313681740f, 0.949528181f,\n -0.336889853f, 0.941544065f,\n -0.359895037f, 0.932992799f,\n -0.382683432f, 0.923879533f,\n -0.405241314f, 0.914209756f,\n -0.427555093f, 0.903989293f,\n -0.449611330f, 0.893224301f,\n -0.471396737f, 0.881921264f,\n -0.492898192f, 0.870086991f,\n -0.514102744f, 0.857728610f,\n -0.534997620f, 0.844853565f,\n -0.555570233f, 0.831469612f,\n -0.575808191f, 0.817584813f,\n -0.595699304f, 0.803207531f,\n -0.615231591f, 0.788346428f,\n -0.634393284f, 0.773010453f,\n -0.653172843f, 0.757208847f,\n -0.671558955f, 0.740951125f,\n -0.689540545f, 0.724247083f,\n -0.707106781f, 0.707106781f,\n -0.724247083f, 0.689540545f,\n -0.740951125f, 0.671558955f,\n -0.757208847f, 0.653172843f,\n -0.773010453f, 0.634393284f,\n -0.788346428f, 0.615231591f,\n -0.803207531f, 0.595699304f,\n -0.817584813f, 0.575808191f,\n -0.831469612f, 0.555570233f,\n -0.844853565f, 0.534997620f,\n -0.857728610f, 0.514102744f,\n -0.870086991f, 0.492898192f,\n -0.881921264f, 0.471396737f,\n -0.893224301f, 0.449611330f,\n -0.903989293f, 0.427555093f,\n -0.914209756f, 0.405241314f,\n -0.923879533f, 0.382683432f,\n -0.932992799f, 0.359895037f,\n -0.941544065f, 0.336889853f,\n -0.949528181f, 0.313681740f,\n -0.956940336f, 0.290284677f,\n -0.963776066f, 0.266712757f,\n -0.970031253f, 0.242980180f,\n -0.975702130f, 0.219101240f,\n -0.980785280f, 0.195090322f,\n -0.985277642f, 0.170961889f,\n -0.989176510f, 0.146730474f,\n -0.992479535f, 0.122410675f,\n -0.995184727f, 0.098017140f,\n -0.997290457f, 0.073564564f,\n -0.998795456f, 0.049067674f,\n -0.999698819f, 0.024541229f,\n -1.000000000f, 0.000000000f,\n -0.999698819f, -0.024541229f,\n -0.998795456f, -0.049067674f,\n -0.997290457f, -0.073564564f,\n -0.995184727f, -0.098017140f,\n -0.992479535f, -0.122410675f,\n -0.989176510f, -0.146730474f,\n -0.985277642f, -0.170961889f,\n -0.980785280f, -0.195090322f,\n -0.975702130f, -0.219101240f,\n -0.970031253f, -0.242980180f,\n -0.963776066f, -0.266712757f,\n -0.956940336f, -0.290284677f,\n -0.949528181f, -0.313681740f,\n -0.941544065f, -0.336889853f,\n -0.932992799f, -0.359895037f,\n -0.923879533f, -0.382683432f,\n -0.914209756f, -0.405241314f,\n -0.903989293f, -0.427555093f,\n -0.893224301f, -0.449611330f,\n -0.881921264f, -0.471396737f,\n -0.870086991f, -0.492898192f,\n -0.857728610f, -0.514102744f,\n -0.844853565f, -0.534997620f,\n -0.831469612f, -0.555570233f,\n -0.817584813f, -0.575808191f,\n -0.803207531f, -0.595699304f,\n -0.788346428f, -0.615231591f,\n -0.773010453f, -0.634393284f,\n -0.757208847f, -0.653172843f,\n -0.740951125f, -0.671558955f,\n -0.724247083f, -0.689540545f,\n -0.707106781f, -0.707106781f,\n -0.689540545f, -0.724247083f,\n -0.671558955f, -0.740951125f,\n -0.653172843f, -0.757208847f,\n -0.634393284f, -0.773010453f,\n -0.615231591f, -0.788346428f,\n -0.595699304f, -0.803207531f,\n -0.575808191f, -0.817584813f,\n -0.555570233f, -0.831469612f,\n -0.534997620f, -0.844853565f,\n -0.514102744f, -0.857728610f,\n -0.492898192f, -0.870086991f,\n -0.471396737f, -0.881921264f,\n -0.449611330f, -0.893224301f,\n -0.427555093f, -0.903989293f,\n -0.405241314f, -0.914209756f,\n -0.382683432f, -0.923879533f,\n -0.359895037f, -0.932992799f,\n -0.336889853f, -0.941544065f,\n -0.313681740f, -0.949528181f,\n -0.290284677f, -0.956940336f,\n -0.266712757f, -0.963776066f,\n -0.242980180f, -0.970031253f,\n -0.219101240f, -0.975702130f,\n -0.195090322f, -0.980785280f,\n -0.170961889f, -0.985277642f,\n -0.146730474f, -0.989176510f,\n -0.122410675f, -0.992479535f,\n -0.098017140f, -0.995184727f,\n -0.073564564f, -0.997290457f,\n -0.049067674f, -0.998795456f,\n -0.024541229f, -0.999698819f,\n -0.000000000f, -1.000000000f,\n 0.024541229f, -0.999698819f,\n 0.049067674f, -0.998795456f,\n 0.073564564f, -0.997290457f,\n 0.098017140f, -0.995184727f,\n 0.122410675f, -0.992479535f,\n 0.146730474f, -0.989176510f,\n 0.170961889f, -0.985277642f,\n 0.195090322f, -0.980785280f,\n 0.219101240f, -0.975702130f,\n 0.242980180f, -0.970031253f,\n 0.266712757f, -0.963776066f,\n 0.290284677f, -0.956940336f,\n 0.313681740f, -0.949528181f,\n 0.336889853f, -0.941544065f,\n 0.359895037f, -0.932992799f,\n 0.382683432f, -0.923879533f,\n 0.405241314f, -0.914209756f,\n 0.427555093f, -0.903989293f,\n 0.449611330f, -0.893224301f,\n 0.471396737f, -0.881921264f,\n 0.492898192f, -0.870086991f,\n 0.514102744f, -0.857728610f,\n 0.534997620f, -0.844853565f,\n 0.555570233f, -0.831469612f,\n 0.575808191f, -0.817584813f,\n 0.595699304f, -0.803207531f,\n 0.615231591f, -0.788346428f,\n 0.634393284f, -0.773010453f,\n 0.653172843f, -0.757208847f,\n 0.671558955f, -0.740951125f,\n 0.689540545f, -0.724247083f,\n 0.707106781f, -0.707106781f,\n 0.724247083f, -0.689540545f,\n 0.740951125f, -0.671558955f,\n 0.757208847f, -0.653172843f,\n 0.773010453f, -0.634393284f,\n 0.788346428f, -0.615231591f,\n 0.803207531f, -0.595699304f,\n 0.817584813f, -0.575808191f,\n 0.831469612f, -0.555570233f,\n 0.844853565f, -0.534997620f,\n 0.857728610f, -0.514102744f,\n 0.870086991f, -0.492898192f,\n 0.881921264f, -0.471396737f,\n 0.893224301f, -0.449611330f,\n 0.903989293f, -0.427555093f,\n 0.914209756f, -0.405241314f,\n 0.923879533f, -0.382683432f,\n 0.932992799f, -0.359895037f,\n 0.941544065f, -0.336889853f,\n 0.949528181f, -0.313681740f,\n 0.956940336f, -0.290284677f,\n 0.963776066f, -0.266712757f,\n 0.970031253f, -0.242980180f,\n 0.975702130f, -0.219101240f,\n 0.980785280f, -0.195090322f,\n 0.985277642f, -0.170961889f,\n 0.989176510f, -0.146730474f,\n 0.992479535f, -0.122410675f,\n 0.995184727f, -0.098017140f,\n 0.997290457f, -0.073564564f,\n 0.998795456f, -0.049067674f,\n 0.999698819f, -0.024541229f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_512[1024] = {\n 1.000000000f, 0.000000000f,\n 0.999924702f, 0.012271538f,\n 0.999698819f, 0.024541229f,\n 0.999322385f, 0.036807223f,\n 0.998795456f, 0.049067674f,\n 0.998118113f, 0.061320736f,\n 0.997290457f, 0.073564564f,\n 0.996312612f, 0.085797312f,\n 0.995184727f, 0.098017140f,\n 0.993906970f, 0.110222207f,\n 0.992479535f, 0.122410675f,\n 0.990902635f, 0.134580709f,\n 0.989176510f, 0.146730474f,\n 0.987301418f, 0.158858143f,\n 0.985277642f, 0.170961889f,\n 0.983105487f, 0.183039888f,\n 0.980785280f, 0.195090322f,\n 0.978317371f, 0.207111376f,\n 0.975702130f, 0.219101240f,\n 0.972939952f, 0.231058108f,\n 0.970031253f, 0.242980180f,\n 0.966976471f, 0.254865660f,\n 0.963776066f, 0.266712757f,\n 0.960430519f, 0.278519689f,\n 0.956940336f, 0.290284677f,\n 0.953306040f, 0.302005949f,\n 0.949528181f, 0.313681740f,\n 0.945607325f, 0.325310292f,\n 0.941544065f, 0.336889853f,\n 0.937339012f, 0.348418680f,\n 0.932992799f, 0.359895037f,\n 0.928506080f, 0.371317194f,\n 0.923879533f, 0.382683432f,\n 0.919113852f, 0.393992040f,\n 0.914209756f, 0.405241314f,\n 0.909167983f, 0.416429560f,\n 0.903989293f, 0.427555093f,\n 0.898674466f, 0.438616239f,\n 0.893224301f, 0.449611330f,\n 0.887639620f, 0.460538711f,\n 0.881921264f, 0.471396737f,\n 0.876070094f, 0.482183772f,\n 0.870086991f, 0.492898192f,\n 0.863972856f, 0.503538384f,\n 0.857728610f, 0.514102744f,\n 0.851355193f, 0.524589683f,\n 0.844853565f, 0.534997620f,\n 0.838224706f, 0.545324988f,\n 0.831469612f, 0.555570233f,\n 0.824589303f, 0.565731811f,\n 0.817584813f, 0.575808191f,\n 0.810457198f, 0.585797857f,\n 0.803207531f, 0.595699304f,\n 0.795836905f, 0.605511041f,\n 0.788346428f, 0.615231591f,\n 0.780737229f, 0.624859488f,\n 0.773010453f, 0.634393284f,\n 0.765167266f, 0.643831543f,\n 0.757208847f, 0.653172843f,\n 0.749136395f, 0.662415778f,\n 0.740951125f, 0.671558955f,\n 0.732654272f, 0.680600998f,\n 0.724247083f, 0.689540545f,\n 0.715730825f, 0.698376249f,\n 0.707106781f, 0.707106781f,\n 0.698376249f, 0.715730825f,\n 0.689540545f, 0.724247083f,\n 0.680600998f, 0.732654272f,\n 0.671558955f, 0.740951125f,\n 0.662415778f, 0.749136395f,\n 0.653172843f, 0.757208847f,\n 0.643831543f, 0.765167266f,\n 0.634393284f, 0.773010453f,\n 0.624859488f, 0.780737229f,\n 0.615231591f, 0.788346428f,\n 0.605511041f, 0.795836905f,\n 0.595699304f, 0.803207531f,\n 0.585797857f, 0.810457198f,\n 0.575808191f, 0.817584813f,\n 0.565731811f, 0.824589303f,\n 0.555570233f, 0.831469612f,\n 0.545324988f, 0.838224706f,\n 0.534997620f, 0.844853565f,\n 0.524589683f, 0.851355193f,\n 0.514102744f, 0.857728610f,\n 0.503538384f, 0.863972856f,\n 0.492898192f, 0.870086991f,\n 0.482183772f, 0.876070094f,\n 0.471396737f, 0.881921264f,\n 0.460538711f, 0.887639620f,\n 0.449611330f, 0.893224301f,\n 0.438616239f, 0.898674466f,\n 0.427555093f, 0.903989293f,\n 0.416429560f, 0.909167983f,\n 0.405241314f, 0.914209756f,\n 0.393992040f, 0.919113852f,\n 0.382683432f, 0.923879533f,\n 0.371317194f, 0.928506080f,\n 0.359895037f, 0.932992799f,\n 0.348418680f, 0.937339012f,\n 0.336889853f, 0.941544065f,\n 0.325310292f, 0.945607325f,\n 0.313681740f, 0.949528181f,\n 0.302005949f, 0.953306040f,\n 0.290284677f, 0.956940336f,\n 0.278519689f, 0.960430519f,\n 0.266712757f, 0.963776066f,\n 0.254865660f, 0.966976471f,\n 0.242980180f, 0.970031253f,\n 0.231058108f, 0.972939952f,\n 0.219101240f, 0.975702130f,\n 0.207111376f, 0.978317371f,\n 0.195090322f, 0.980785280f,\n 0.183039888f, 0.983105487f,\n 0.170961889f, 0.985277642f,\n 0.158858143f, 0.987301418f,\n 0.146730474f, 0.989176510f,\n 0.134580709f, 0.990902635f,\n 0.122410675f, 0.992479535f,\n 0.110222207f, 0.993906970f,\n 0.098017140f, 0.995184727f,\n 0.085797312f, 0.996312612f,\n 0.073564564f, 0.997290457f,\n 0.061320736f, 0.998118113f,\n 0.049067674f, 0.998795456f,\n 0.036807223f, 0.999322385f,\n 0.024541229f, 0.999698819f,\n 0.012271538f, 0.999924702f,\n 0.000000000f, 1.000000000f,\n -0.012271538f, 0.999924702f,\n -0.024541229f, 0.999698819f,\n -0.036807223f, 0.999322385f,\n -0.049067674f, 0.998795456f,\n -0.061320736f, 0.998118113f,\n -0.073564564f, 0.997290457f,\n -0.085797312f, 0.996312612f,\n -0.098017140f, 0.995184727f,\n -0.110222207f, 0.993906970f,\n -0.122410675f, 0.992479535f,\n -0.134580709f, 0.990902635f,\n -0.146730474f, 0.989176510f,\n -0.158858143f, 0.987301418f,\n -0.170961889f, 0.985277642f,\n -0.183039888f, 0.983105487f,\n -0.195090322f, 0.980785280f,\n -0.207111376f, 0.978317371f,\n -0.219101240f, 0.975702130f,\n -0.231058108f, 0.972939952f,\n -0.242980180f, 0.970031253f,\n -0.254865660f, 0.966976471f,\n -0.266712757f, 0.963776066f,\n -0.278519689f, 0.960430519f,\n -0.290284677f, 0.956940336f,\n -0.302005949f, 0.953306040f,\n -0.313681740f, 0.949528181f,\n -0.325310292f, 0.945607325f,\n -0.336889853f, 0.941544065f,\n -0.348418680f, 0.937339012f,\n -0.359895037f, 0.932992799f,\n -0.371317194f, 0.928506080f,\n -0.382683432f, 0.923879533f,\n -0.393992040f, 0.919113852f,\n -0.405241314f, 0.914209756f,\n -0.416429560f, 0.909167983f,\n -0.427555093f, 0.903989293f,\n -0.438616239f, 0.898674466f,\n -0.449611330f, 0.893224301f,\n -0.460538711f, 0.887639620f,\n -0.471396737f, 0.881921264f,\n -0.482183772f, 0.876070094f,\n -0.492898192f, 0.870086991f,\n -0.503538384f, 0.863972856f,\n -0.514102744f, 0.857728610f,\n -0.524589683f, 0.851355193f,\n -0.534997620f, 0.844853565f,\n -0.545324988f, 0.838224706f,\n -0.555570233f, 0.831469612f,\n -0.565731811f, 0.824589303f,\n -0.575808191f, 0.817584813f,\n -0.585797857f, 0.810457198f,\n -0.595699304f, 0.803207531f,\n -0.605511041f, 0.795836905f,\n -0.615231591f, 0.788346428f,\n -0.624859488f, 0.780737229f,\n -0.634393284f, 0.773010453f,\n -0.643831543f, 0.765167266f,\n -0.653172843f, 0.757208847f,\n -0.662415778f, 0.749136395f,\n -0.671558955f, 0.740951125f,\n -0.680600998f, 0.732654272f,\n -0.689540545f, 0.724247083f,\n -0.698376249f, 0.715730825f,\n -0.707106781f, 0.707106781f,\n -0.715730825f, 0.698376249f,\n -0.724247083f, 0.689540545f,\n -0.732654272f, 0.680600998f,\n -0.740951125f, 0.671558955f,\n -0.749136395f, 0.662415778f,\n -0.757208847f, 0.653172843f,\n -0.765167266f, 0.643831543f,\n -0.773010453f, 0.634393284f,\n -0.780737229f, 0.624859488f,\n -0.788346428f, 0.615231591f,\n -0.795836905f, 0.605511041f,\n -0.803207531f, 0.595699304f,\n -0.810457198f, 0.585797857f,\n -0.817584813f, 0.575808191f,\n -0.824589303f, 0.565731811f,\n -0.831469612f, 0.555570233f,\n -0.838224706f, 0.545324988f,\n -0.844853565f, 0.534997620f,\n -0.851355193f, 0.524589683f,\n -0.857728610f, 0.514102744f,\n -0.863972856f, 0.503538384f,\n -0.870086991f, 0.492898192f,\n -0.876070094f, 0.482183772f,\n -0.881921264f, 0.471396737f,\n -0.887639620f, 0.460538711f,\n -0.893224301f, 0.449611330f,\n -0.898674466f, 0.438616239f,\n -0.903989293f, 0.427555093f,\n -0.909167983f, 0.416429560f,\n -0.914209756f, 0.405241314f,\n -0.919113852f, 0.393992040f,\n -0.923879533f, 0.382683432f,\n -0.928506080f, 0.371317194f,\n -0.932992799f, 0.359895037f,\n -0.937339012f, 0.348418680f,\n -0.941544065f, 0.336889853f,\n -0.945607325f, 0.325310292f,\n -0.949528181f, 0.313681740f,\n -0.953306040f, 0.302005949f,\n -0.956940336f, 0.290284677f,\n -0.960430519f, 0.278519689f,\n -0.963776066f, 0.266712757f,\n -0.966976471f, 0.254865660f,\n -0.970031253f, 0.242980180f,\n -0.972939952f, 0.231058108f,\n -0.975702130f, 0.219101240f,\n -0.978317371f, 0.207111376f,\n -0.980785280f, 0.195090322f,\n -0.983105487f, 0.183039888f,\n -0.985277642f, 0.170961889f,\n -0.987301418f, 0.158858143f,\n -0.989176510f, 0.146730474f,\n -0.990902635f, 0.134580709f,\n -0.992479535f, 0.122410675f,\n -0.993906970f, 0.110222207f,\n -0.995184727f, 0.098017140f,\n -0.996312612f, 0.085797312f,\n -0.997290457f, 0.073564564f,\n -0.998118113f, 0.061320736f,\n -0.998795456f, 0.049067674f,\n -0.999322385f, 0.036807223f,\n -0.999698819f, 0.024541229f,\n -0.999924702f, 0.012271538f,\n -1.000000000f, 0.000000000f,\n -0.999924702f, -0.012271538f,\n -0.999698819f, -0.024541229f,\n -0.999322385f, -0.036807223f,\n -0.998795456f, -0.049067674f,\n -0.998118113f, -0.061320736f,\n -0.997290457f, -0.073564564f,\n -0.996312612f, -0.085797312f,\n -0.995184727f, -0.098017140f,\n -0.993906970f, -0.110222207f,\n -0.992479535f, -0.122410675f,\n -0.990902635f, -0.134580709f,\n -0.989176510f, -0.146730474f,\n -0.987301418f, -0.158858143f,\n -0.985277642f, -0.170961889f,\n -0.983105487f, -0.183039888f,\n -0.980785280f, -0.195090322f,\n -0.978317371f, -0.207111376f,\n -0.975702130f, -0.219101240f,\n -0.972939952f, -0.231058108f,\n -0.970031253f, -0.242980180f,\n -0.966976471f, -0.254865660f,\n -0.963776066f, -0.266712757f,\n -0.960430519f, -0.278519689f,\n -0.956940336f, -0.290284677f,\n -0.953306040f, -0.302005949f,\n -0.949528181f, -0.313681740f,\n -0.945607325f, -0.325310292f,\n -0.941544065f, -0.336889853f,\n -0.937339012f, -0.348418680f,\n -0.932992799f, -0.359895037f,\n -0.928506080f, -0.371317194f,\n -0.923879533f, -0.382683432f,\n -0.919113852f, -0.393992040f,\n -0.914209756f, -0.405241314f,\n -0.909167983f, -0.416429560f,\n -0.903989293f, -0.427555093f,\n -0.898674466f, -0.438616239f,\n -0.893224301f, -0.449611330f,\n -0.887639620f, -0.460538711f,\n -0.881921264f, -0.471396737f,\n -0.876070094f, -0.482183772f,\n -0.870086991f, -0.492898192f,\n -0.863972856f, -0.503538384f,\n -0.857728610f, -0.514102744f,\n -0.851355193f, -0.524589683f,\n -0.844853565f, -0.534997620f,\n -0.838224706f, -0.545324988f,\n -0.831469612f, -0.555570233f,\n -0.824589303f, -0.565731811f,\n -0.817584813f, -0.575808191f,\n -0.810457198f, -0.585797857f,\n -0.803207531f, -0.595699304f,\n -0.795836905f, -0.605511041f,\n -0.788346428f, -0.615231591f,\n -0.780737229f, -0.624859488f,\n -0.773010453f, -0.634393284f,\n -0.765167266f, -0.643831543f,\n -0.757208847f, -0.653172843f,\n -0.749136395f, -0.662415778f,\n -0.740951125f, -0.671558955f,\n -0.732654272f, -0.680600998f,\n -0.724247083f, -0.689540545f,\n -0.715730825f, -0.698376249f,\n -0.707106781f, -0.707106781f,\n -0.698376249f, -0.715730825f,\n -0.689540545f, -0.724247083f,\n -0.680600998f, -0.732654272f,\n -0.671558955f, -0.740951125f,\n -0.662415778f, -0.749136395f,\n -0.653172843f, -0.757208847f,\n -0.643831543f, -0.765167266f,\n -0.634393284f, -0.773010453f,\n -0.624859488f, -0.780737229f,\n -0.615231591f, -0.788346428f,\n -0.605511041f, -0.795836905f,\n -0.595699304f, -0.803207531f,\n -0.585797857f, -0.810457198f,\n -0.575808191f, -0.817584813f,\n -0.565731811f, -0.824589303f,\n -0.555570233f, -0.831469612f,\n -0.545324988f, -0.838224706f,\n -0.534997620f, -0.844853565f,\n -0.524589683f, -0.851355193f,\n -0.514102744f, -0.857728610f,\n -0.503538384f, -0.863972856f,\n -0.492898192f, -0.870086991f,\n -0.482183772f, -0.876070094f,\n -0.471396737f, -0.881921264f,\n -0.460538711f, -0.887639620f,\n -0.449611330f, -0.893224301f,\n -0.438616239f, -0.898674466f,\n -0.427555093f, -0.903989293f,\n -0.416429560f, -0.909167983f,\n -0.405241314f, -0.914209756f,\n -0.393992040f, -0.919113852f,\n -0.382683432f, -0.923879533f,\n -0.371317194f, -0.928506080f,\n -0.359895037f, -0.932992799f,\n -0.348418680f, -0.937339012f,\n -0.336889853f, -0.941544065f,\n -0.325310292f, -0.945607325f,\n -0.313681740f, -0.949528181f,\n -0.302005949f, -0.953306040f,\n -0.290284677f, -0.956940336f,\n -0.278519689f, -0.960430519f,\n -0.266712757f, -0.963776066f,\n -0.254865660f, -0.966976471f,\n -0.242980180f, -0.970031253f,\n -0.231058108f, -0.972939952f,\n -0.219101240f, -0.975702130f,\n -0.207111376f, -0.978317371f,\n -0.195090322f, -0.980785280f,\n -0.183039888f, -0.983105487f,\n -0.170961889f, -0.985277642f,\n -0.158858143f, -0.987301418f,\n -0.146730474f, -0.989176510f,\n -0.134580709f, -0.990902635f,\n -0.122410675f, -0.992479535f,\n -0.110222207f, -0.993906970f,\n -0.098017140f, -0.995184727f,\n -0.085797312f, -0.996312612f,\n -0.073564564f, -0.997290457f,\n -0.061320736f, -0.998118113f,\n -0.049067674f, -0.998795456f,\n -0.036807223f, -0.999322385f,\n -0.024541229f, -0.999698819f,\n -0.012271538f, -0.999924702f,\n -0.000000000f, -1.000000000f,\n 0.012271538f, -0.999924702f,\n 0.024541229f, -0.999698819f,\n 0.036807223f, -0.999322385f,\n 0.049067674f, -0.998795456f,\n 0.061320736f, -0.998118113f,\n 0.073564564f, -0.997290457f,\n 0.085797312f, -0.996312612f,\n 0.098017140f, -0.995184727f,\n 0.110222207f, -0.993906970f,\n 0.122410675f, -0.992479535f,\n 0.134580709f, -0.990902635f,\n 0.146730474f, -0.989176510f,\n 0.158858143f, -0.987301418f,\n 0.170961889f, -0.985277642f,\n 0.183039888f, -0.983105487f,\n 0.195090322f, -0.980785280f,\n 0.207111376f, -0.978317371f,\n 0.219101240f, -0.975702130f,\n 0.231058108f, -0.972939952f,\n 0.242980180f, -0.970031253f,\n 0.254865660f, -0.966976471f,\n 0.266712757f, -0.963776066f,\n 0.278519689f, -0.960430519f,\n 0.290284677f, -0.956940336f,\n 0.302005949f, -0.953306040f,\n 0.313681740f, -0.949528181f,\n 0.325310292f, -0.945607325f,\n 0.336889853f, -0.941544065f,\n 0.348418680f, -0.937339012f,\n 0.359895037f, -0.932992799f,\n 0.371317194f, -0.928506080f,\n 0.382683432f, -0.923879533f,\n 0.393992040f, -0.919113852f,\n 0.405241314f, -0.914209756f,\n 0.416429560f, -0.909167983f,\n 0.427555093f, -0.903989293f,\n 0.438616239f, -0.898674466f,\n 0.449611330f, -0.893224301f,\n 0.460538711f, -0.887639620f,\n 0.471396737f, -0.881921264f,\n 0.482183772f, -0.876070094f,\n 0.492898192f, -0.870086991f,\n 0.503538384f, -0.863972856f,\n 0.514102744f, -0.857728610f,\n 0.524589683f, -0.851355193f,\n 0.534997620f, -0.844853565f,\n 0.545324988f, -0.838224706f,\n 0.555570233f, -0.831469612f,\n 0.565731811f, -0.824589303f,\n 0.575808191f, -0.817584813f,\n 0.585797857f, -0.810457198f,\n 0.595699304f, -0.803207531f,\n 0.605511041f, -0.795836905f,\n 0.615231591f, -0.788346428f,\n 0.624859488f, -0.780737229f,\n 0.634393284f, -0.773010453f,\n 0.643831543f, -0.765167266f,\n 0.653172843f, -0.757208847f,\n 0.662415778f, -0.749136395f,\n 0.671558955f, -0.740951125f,\n 0.680600998f, -0.732654272f,\n 0.689540545f, -0.724247083f,\n 0.698376249f, -0.715730825f,\n 0.707106781f, -0.707106781f,\n 0.715730825f, -0.698376249f,\n 0.724247083f, -0.689540545f,\n 0.732654272f, -0.680600998f,\n 0.740951125f, -0.671558955f,\n 0.749136395f, -0.662415778f,\n 0.757208847f, -0.653172843f,\n 0.765167266f, -0.643831543f,\n 0.773010453f, -0.634393284f,\n 0.780737229f, -0.624859488f,\n 0.788346428f, -0.615231591f,\n 0.795836905f, -0.605511041f,\n 0.803207531f, -0.595699304f,\n 0.810457198f, -0.585797857f,\n 0.817584813f, -0.575808191f,\n 0.824589303f, -0.565731811f,\n 0.831469612f, -0.555570233f,\n 0.838224706f, -0.545324988f,\n 0.844853565f, -0.534997620f,\n 0.851355193f, -0.524589683f,\n 0.857728610f, -0.514102744f,\n 0.863972856f, -0.503538384f,\n 0.870086991f, -0.492898192f,\n 0.876070094f, -0.482183772f,\n 0.881921264f, -0.471396737f,\n 0.887639620f, -0.460538711f,\n 0.893224301f, -0.449611330f,\n 0.898674466f, -0.438616239f,\n 0.903989293f, -0.427555093f,\n 0.909167983f, -0.416429560f,\n 0.914209756f, -0.405241314f,\n 0.919113852f, -0.393992040f,\n 0.923879533f, -0.382683432f,\n 0.928506080f, -0.371317194f,\n 0.932992799f, -0.359895037f,\n 0.937339012f, -0.348418680f,\n 0.941544065f, -0.336889853f,\n 0.945607325f, -0.325310292f,\n 0.949528181f, -0.313681740f,\n 0.953306040f, -0.302005949f,\n 0.956940336f, -0.290284677f,\n 0.960430519f, -0.278519689f,\n 0.963776066f, -0.266712757f,\n 0.966976471f, -0.254865660f,\n 0.970031253f, -0.242980180f,\n 0.972939952f, -0.231058108f,\n 0.975702130f, -0.219101240f,\n 0.978317371f, -0.207111376f,\n 0.980785280f, -0.195090322f,\n 0.983105487f, -0.183039888f,\n 0.985277642f, -0.170961889f,\n 0.987301418f, -0.158858143f,\n 0.989176510f, -0.146730474f,\n 0.990902635f, -0.134580709f,\n 0.992479535f, -0.122410675f,\n 0.993906970f, -0.110222207f,\n 0.995184727f, -0.098017140f,\n 0.996312612f, -0.085797312f,\n 0.997290457f, -0.073564564f,\n 0.998118113f, -0.061320736f,\n 0.998795456f, -0.049067674f,\n 0.999322385f, -0.036807223f,\n 0.999698819f, -0.024541229f,\n 0.999924702f, -0.012271538f\n};\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_1024[2048] = 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19355990f\t,\t-0.854557988f\t,\n0.524589683f\t,\t-0.851355193f\t,\n0.529803625f\t,\t-0.848120345f\t,\n0.534997620f\t,\t-0.844853565f\t,\n0.540171473f\t,\t-0.841554977f\t,\n0.545324988f\t,\t-0.838224706f\t,\n0.550457973f\t,\t-0.834862875f\t,\n0.555570233f\t,\t-0.831469612f\t,\n0.560661576f\t,\t-0.828045045f\t,\n0.565731811f\t,\t-0.824589303f\t,\n0.570780746f\t,\t-0.821102515f\t,\n0.575808191f\t,\t-0.817584813f\t,\n0.580813958f\t,\t-0.814036330f\t,\n0.585797857f\t,\t-0.810457198f\t,\n0.590759702f\t,\t-0.806847554f\t,\n0.595699304f\t,\t-0.803207531f\t,\n0.600616479f\t,\t-0.799537269f\t,\n0.605511041f\t,\t-0.795836905f\t,\n0.610382806f\t,\t-0.792106577f\t,\n0.615231591f\t,\t-0.788346428f\t,\n0.620057212f\t,\t-0.784556597f\t,\n0.624859488f\t,\t-0.780737229f\t,\n0.629638239f\t,\t-0.776888466f\t,\n0.634393284f\t,\t-0.773010453f\t,\n0.639124445f\t,\t-0.769103338f\t,\n0.643831543f\t,\t-0.765167266f\t,\n0.648514401f\t,\t-0.761202385f\t,\n0.653172843f\t,\t-0.757208847f\t,\n0.657806693f\t,\t-0.753186799f\t,\n0.662415778f\t,\t-0.749136395f\t,\n0.666999922f\t,\t-0.745057785f\t,\n0.671558955f\t,\t-0.740951125f\t,\n0.676092704f\t,\t-0.736816569f\t,\n0.680600998f\t,\t-0.732654272f\t,\n0.685083668f\t,\t-0.728464390f\t,\n0.689540545f\t,\t-0.724247083f\t,\n0.693971461f\t,\t-0.720002508f\t,\n0.698376249f\t,\t-0.715730825f\t,\n0.702754744f\t,\t-0.711432196f\t,\n0.707106781f\t,\t-0.707106781f\t,\n0.711432196f\t,\t-0.702754744f\t,\n0.715730825f\t,\t-0.698376249f\t,\n0.720002508f\t,\t-0.693971461f\t,\n0.724247083f\t,\t-0.689540545f\t,\n0.728464390f\t,\t-0.685083668f\t,\n0.732654272f\t,\t-0.680600998f\t,\n0.736816569f\t,\t-0.676092704f\t,\n0.740951125f\t,\t-0.671558955f\t,\n0.745057785f\t,\t-0.666999922f\t,\n0.749136395f\t,\t-0.662415778f\t,\n0.753186799f\t,\t-0.657806693f\t,\n0.757208847f\t,\t-0.653172843f\t,\n0.761202385f\t,\t-0.648514401f\t,\n0.765167266f\t,\t-0.643831543f\t,\n0.769103338f\t,\t-0.639124445f\t,\n0.773010453f\t,\t-0.634393284f\t,\n0.776888466f\t,\t-0.629638239f\t,\n0.780737229f\t,\t-0.624859488f\t,\n0.784556597f\t,\t-0.620057212f\t,\n0.788346428f\t,\t-0.615231591f\t,\n0.792106577f\t,\t-0.610382806f\t,\n0.795836905f\t,\t-0.605511041f\t,\n0.799537269f\t,\t-0.600616479f\t,\n0.803207531f\t,\t-0.595699304f\t,\n0.806847554f\t,\t-0.590759702f\t,\n0.810457198f\t,\t-0.585797857f\t,\n0.814036330f\t,\t-0.580813958f\t,\n0.817584813f\t,\t-0.575808191f\t,\n0.821102515f\t,\t-0.570780746f\t,\n0.824589303f\t,\t-0.565731811f\t,\n0.828045045f\t,\t-0.560661576f\t,\n0.831469612f\t,\t-0.555570233f\t,\n0.834862875f\t,\t-0.550457973f\t,\n0.838224706f\t,\t-0.545324988f\t,\n0.841554977f\t,\t-0.540171473f\t,\n0.844853565f\t,\t-0.534997620f\t,\n0.848120345f\t,\t-0.529803625f\t,\n0.851355193f\t,\t-0.524589683f\t,\n0.854557988f\t,\t-0.519355990f\t,\n0.857728610f\t,\t-0.514102744f\t,\n0.860866939f\t,\t-0.508830143f\t,\n0.863972856f\t,\t-0.503538384f\t,\n0.867046246f\t,\t-0.498227667f\t,\n0.870086991f\t,\t-0.492898192f\t,\n0.873094978f\t,\t-0.487550160f\t,\n0.876070094f\t,\t-0.482183772f\t,\n0.879012226f\t,\t-0.476799230f\t,\n0.881921264f\t,\t-0.471396737f\t,\n0.884797098f\t,\t-0.465976496f\t,\n0.887639620f\t,\t-0.460538711f\t,\n0.890448723f\t,\t-0.455083587f\t,\n0.893224301f\t,\t-0.449611330f\t,\n0.895966250f\t,\t-0.444122145f\t,\n0.898674466f\t,\t-0.438616239f\t,\n0.901348847f\t,\t-0.433093819f\t,\n0.903989293f\t,\t-0.427555093f\t,\n0.906595705f\t,\t-0.422000271f\t,\n0.909167983f\t,\t-0.416429560f\t,\n0.911706032f\t,\t-0.410843171f\t,\n0.914209756f\t,\t-0.405241314f\t,\n0.916679060f\t,\t-0.399624200f\t,\n0.919113852f\t,\t-0.393992040f\t,\n0.921514039f\t,\t-0.388345047f\t,\n0.923879533f\t,\t-0.382683432f\t,\n0.926210242f\t,\t-0.377007410f\t,\n0.928506080f\t,\t-0.371317194f\t,\n0.930766961f\t,\t-0.365612998f\t,\n0.932992799f\t,\t-0.359895037f\t,\n0.935183510f\t,\t-0.354163525f\t,\n0.937339012f\t,\t-0.348418680f\t,\n0.939459224f\t,\t-0.342660717f\t,\n0.941544065f\t,\t-0.336889853f\t,\n0.943593458f\t,\t-0.331106306f\t,\n0.945607325f\t,\t-0.325310292f\t,\n0.947585591f\t,\t-0.319502031f\t,\n0.949528181f\t,\t-0.313681740f\t,\n0.951435021f\t,\t-0.307849640f\t,\n0.953306040f\t,\t-0.302005949f\t,\n0.955141168f\t,\t-0.296150888f\t,\n0.956940336f\t,\t-0.290284677f\t,\n0.958703475f\t,\t-0.284407537f\t,\n0.960430519f\t,\t-0.278519689f\t,\n0.962121404f\t,\t-0.272621355f\t,\n0.963776066f\t,\t-0.266712757f\t,\n0.965394442f\t,\t-0.260794118f\t,\n0.966976471f\t,\t-0.254865660f\t,\n0.968522094f\t,\t-0.248927606f\t,\n0.970031253f\t,\t-0.242980180f\t,\n0.971503891f\t,\t-0.237023606f\t,\n0.972939952f\t,\t-0.231058108f\t,\n0.974339383f\t,\t-0.225083911f\t,\n0.975702130f\t,\t-0.219101240f\t,\n0.977028143f\t,\t-0.213110320f\t,\n0.978317371f\t,\t-0.207111376f\t,\n0.979569766f\t,\t-0.201104635f\t,\n0.980785280f\t,\t-0.195090322f\t,\n0.981963869f\t,\t-0.189068664f\t,\n0.983105487f\t,\t-0.183039888f\t,\n0.984210092f\t,\t-0.177004220f\t,\n0.985277642f\t,\t-0.170961889f\t,\n0.986308097f\t,\t-0.164913120f\t,\n0.987301418f\t,\t-0.158858143f\t,\n0.988257568f\t,\t-0.152797185f\t,\n0.989176510f\t,\t-0.146730474f\t,\n0.990058210f\t,\t-0.140658239f\t,\n0.990902635f\t,\t-0.134580709f\t,\n0.991709754f\t,\t-0.128498111f\t,\n0.992479535f\t,\t-0.122410675f\t,\n0.993211949f\t,\t-0.116318631f\t,\n0.993906970f\t,\t-0.110222207f\t,\n0.994564571f\t,\t-0.104121634f\t,\n0.995184727f\t,\t-0.098017140f\t,\n0.995767414f\t,\t-0.091908956f\t,\n0.996312612f\t,\t-0.085797312f\t,\n0.996820299f\t,\t-0.079682438f\t,\n0.997290457f\t,\t-0.073564564f\t,\n0.997723067f\t,\t-0.067443920f\t,\n0.998118113f\t,\t-0.061320736f\t,\n0.998475581f\t,\t-0.055195244f\t,\n0.998795456f\t,\t-0.049067674f\t,\n0.999077728f\t,\t-0.042938257f\t,\n0.999322385f\t,\t-0.036807223f\t,\n0.999529418f\t,\t-0.030674803f\t,\n0.999698819f\t,\t-0.024541229f\t,\n0.999830582f\t,\t-0.018406730f\t,\n0.999924702f\t,\t-0.012271538f\t,\n0.999981175f\t,\t-0.006135885f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_2048[4096] = {\n 1.000000000f, 0.000000000f,\n 0.999995294f, 0.003067957f,\n 0.999981175f, 0.006135885f,\n 0.999957645f, 0.009203755f,\n 0.999924702f, 0.012271538f,\n 0.999882347f, 0.015339206f,\n 0.999830582f, 0.018406730f,\n 0.999769405f, 0.021474080f,\n 0.999698819f, 0.024541229f,\n 0.999618822f, 0.027608146f,\n 0.999529418f, 0.030674803f,\n 0.999430605f, 0.033741172f,\n 0.999322385f, 0.036807223f,\n 0.999204759f, 0.039872928f,\n 0.999077728f, 0.042938257f,\n 0.998941293f, 0.046003182f,\n 0.998795456f, 0.049067674f,\n 0.998640218f, 0.052131705f,\n 0.998475581f, 0.055195244f,\n 0.998301545f, 0.058258265f,\n 0.998118113f, 0.061320736f,\n 0.997925286f, 0.064382631f,\n 0.997723067f, 0.067443920f,\n 0.997511456f, 0.070504573f,\n 0.997290457f, 0.073564564f,\n 0.997060070f, 0.076623861f,\n 0.996820299f, 0.079682438f,\n 0.996571146f, 0.082740265f,\n 0.996312612f, 0.085797312f,\n 0.996044701f, 0.088853553f,\n 0.995767414f, 0.091908956f,\n 0.995480755f, 0.094963495f,\n 0.995184727f, 0.098017140f,\n 0.994879331f, 0.101069863f,\n 0.994564571f, 0.104121634f,\n 0.994240449f, 0.107172425f,\n 0.993906970f, 0.110222207f,\n 0.993564136f, 0.113270952f,\n 0.993211949f, 0.116318631f,\n 0.992850414f, 0.119365215f,\n 0.992479535f, 0.122410675f,\n 0.992099313f, 0.125454983f,\n 0.991709754f, 0.128498111f,\n 0.991310860f, 0.131540029f,\n 0.990902635f, 0.134580709f,\n 0.990485084f, 0.137620122f,\n 0.990058210f, 0.140658239f,\n 0.989622017f, 0.143695033f,\n 0.989176510f, 0.146730474f,\n 0.988721692f, 0.149764535f,\n 0.988257568f, 0.152797185f,\n 0.987784142f, 0.155828398f,\n 0.987301418f, 0.158858143f,\n 0.986809402f, 0.161886394f,\n 0.986308097f, 0.164913120f,\n 0.985797509f, 0.167938295f,\n 0.985277642f, 0.170961889f,\n 0.984748502f, 0.173983873f,\n 0.984210092f, 0.177004220f,\n 0.983662419f, 0.180022901f,\n 0.983105487f, 0.183039888f,\n 0.982539302f, 0.186055152f,\n 0.981963869f, 0.189068664f,\n 0.981379193f, 0.192080397f,\n 0.980785280f, 0.195090322f,\n 0.980182136f, 0.198098411f,\n 0.979569766f, 0.201104635f,\n 0.978948175f, 0.204108966f,\n 0.978317371f, 0.207111376f,\n 0.977677358f, 0.210111837f,\n 0.977028143f, 0.213110320f,\n 0.976369731f, 0.216106797f,\n 0.975702130f, 0.219101240f,\n 0.975025345f, 0.222093621f,\n 0.974339383f, 0.225083911f,\n 0.973644250f, 0.228072083f,\n 0.972939952f, 0.231058108f,\n 0.972226497f, 0.234041959f,\n 0.971503891f, 0.237023606f,\n 0.970772141f, 0.240003022f,\n 0.970031253f, 0.242980180f,\n 0.969281235f, 0.245955050f,\n 0.968522094f, 0.248927606f,\n 0.967753837f, 0.251897818f,\n 0.966976471f, 0.254865660f,\n 0.966190003f, 0.257831102f,\n 0.965394442f, 0.260794118f,\n 0.964589793f, 0.263754679f,\n 0.963776066f, 0.266712757f,\n 0.962953267f, 0.269668326f,\n 0.962121404f, 0.272621355f,\n 0.961280486f, 0.275571819f,\n 0.960430519f, 0.278519689f,\n 0.959571513f, 0.281464938f,\n 0.958703475f, 0.284407537f,\n 0.957826413f, 0.287347460f,\n 0.956940336f, 0.290284677f,\n 0.956045251f, 0.293219163f,\n 0.955141168f, 0.296150888f,\n 0.954228095f, 0.299079826f,\n 0.953306040f, 0.302005949f,\n 0.952375013f, 0.304929230f,\n 0.951435021f, 0.307849640f,\n 0.950486074f, 0.310767153f,\n 0.949528181f, 0.313681740f,\n 0.948561350f, 0.316593376f,\n 0.947585591f, 0.319502031f,\n 0.946600913f, 0.322407679f,\n 0.945607325f, 0.325310292f,\n 0.944604837f, 0.328209844f,\n 0.943593458f, 0.331106306f,\n 0.942573198f, 0.333999651f,\n 0.941544065f, 0.336889853f,\n 0.940506071f, 0.339776884f,\n 0.939459224f, 0.342660717f,\n 0.938403534f, 0.345541325f,\n 0.937339012f, 0.348418680f,\n 0.936265667f, 0.351292756f,\n 0.935183510f, 0.354163525f,\n 0.934092550f, 0.357030961f,\n 0.932992799f, 0.359895037f,\n 0.931884266f, 0.362755724f,\n 0.930766961f, 0.365612998f,\n 0.929640896f, 0.368466830f,\n 0.928506080f, 0.371317194f,\n 0.927362526f, 0.374164063f,\n 0.926210242f, 0.377007410f,\n 0.925049241f, 0.379847209f,\n 0.923879533f, 0.382683432f,\n 0.922701128f, 0.385516054f,\n 0.921514039f, 0.388345047f,\n 0.920318277f, 0.391170384f,\n 0.919113852f, 0.393992040f,\n 0.917900776f, 0.396809987f,\n 0.916679060f, 0.399624200f,\n 0.915448716f, 0.402434651f,\n 0.914209756f, 0.405241314f,\n 0.912962190f, 0.408044163f,\n 0.911706032f, 0.410843171f,\n 0.910441292f, 0.413638312f,\n 0.909167983f, 0.416429560f,\n 0.907886116f, 0.419216888f,\n 0.906595705f, 0.422000271f,\n 0.905296759f, 0.424779681f,\n 0.903989293f, 0.427555093f,\n 0.902673318f, 0.430326481f,\n 0.901348847f, 0.433093819f,\n 0.900015892f, 0.435857080f,\n 0.898674466f, 0.438616239f,\n 0.897324581f, 0.441371269f,\n 0.895966250f, 0.444122145f,\n 0.894599486f, 0.446868840f,\n 0.893224301f, 0.449611330f,\n 0.891840709f, 0.452349587f,\n 0.890448723f, 0.455083587f,\n 0.889048356f, 0.457813304f,\n 0.887639620f, 0.460538711f,\n 0.886222530f, 0.463259784f,\n 0.884797098f, 0.465976496f,\n 0.883363339f, 0.468688822f,\n 0.881921264f, 0.471396737f,\n 0.880470889f, 0.474100215f,\n 0.879012226f, 0.476799230f,\n 0.877545290f, 0.479493758f,\n 0.876070094f, 0.482183772f,\n 0.874586652f, 0.484869248f,\n 0.873094978f, 0.487550160f,\n 0.871595087f, 0.490226483f,\n 0.870086991f, 0.492898192f,\n 0.868570706f, 0.495565262f,\n 0.867046246f, 0.498227667f,\n 0.865513624f, 0.500885383f,\n 0.863972856f, 0.503538384f,\n 0.862423956f, 0.506186645f,\n 0.860866939f, 0.508830143f,\n 0.859301818f, 0.511468850f,\n 0.857728610f, 0.514102744f,\n 0.856147328f, 0.516731799f,\n 0.854557988f, 0.519355990f,\n 0.852960605f, 0.521975293f,\n 0.851355193f, 0.524589683f,\n 0.849741768f, 0.527199135f,\n 0.848120345f, 0.529803625f,\n 0.846490939f, 0.532403128f,\n 0.844853565f, 0.534997620f,\n 0.843208240f, 0.537587076f,\n 0.841554977f, 0.540171473f,\n 0.839893794f, 0.542750785f,\n 0.838224706f, 0.545324988f,\n 0.836547727f, 0.547894059f,\n 0.834862875f, 0.550457973f,\n 0.833170165f, 0.553016706f,\n 0.831469612f, 0.555570233f,\n 0.829761234f, 0.558118531f,\n 0.828045045f, 0.560661576f,\n 0.826321063f, 0.563199344f,\n 0.824589303f, 0.565731811f,\n 0.822849781f, 0.568258953f,\n 0.821102515f, 0.570780746f,\n 0.819347520f, 0.573297167f,\n 0.817584813f, 0.575808191f,\n 0.815814411f, 0.578313796f,\n 0.814036330f, 0.580813958f,\n 0.812250587f, 0.583308653f,\n 0.810457198f, 0.585797857f,\n 0.808656182f, 0.588281548f,\n 0.806847554f, 0.590759702f,\n 0.805031331f, 0.593232295f,\n 0.803207531f, 0.595699304f,\n 0.801376172f, 0.598160707f,\n 0.799537269f, 0.600616479f,\n 0.797690841f, 0.603066599f,\n 0.795836905f, 0.605511041f,\n 0.793975478f, 0.607949785f,\n 0.792106577f, 0.610382806f,\n 0.790230221f, 0.612810082f,\n 0.788346428f, 0.615231591f,\n 0.786455214f, 0.617647308f,\n 0.784556597f, 0.620057212f,\n 0.782650596f, 0.622461279f,\n 0.780737229f, 0.624859488f,\n 0.778816512f, 0.627251815f,\n 0.776888466f, 0.629638239f,\n 0.774953107f, 0.632018736f,\n 0.773010453f, 0.634393284f,\n 0.771060524f, 0.636761861f,\n 0.769103338f, 0.639124445f,\n 0.767138912f, 0.641481013f,\n 0.765167266f, 0.643831543f,\n 0.763188417f, 0.646176013f,\n 0.761202385f, 0.648514401f,\n 0.759209189f, 0.650846685f,\n 0.757208847f, 0.653172843f,\n 0.755201377f, 0.655492853f,\n 0.753186799f, 0.657806693f,\n 0.751165132f, 0.660114342f,\n 0.749136395f, 0.662415778f,\n 0.747100606f, 0.664710978f,\n 0.745057785f, 0.666999922f,\n 0.743007952f, 0.669282588f,\n 0.740951125f, 0.671558955f,\n 0.738887324f, 0.673829000f,\n 0.736816569f, 0.676092704f,\n 0.734738878f, 0.678350043f,\n 0.732654272f, 0.680600998f,\n 0.730562769f, 0.682845546f,\n 0.728464390f, 0.685083668f,\n 0.726359155f, 0.687315341f,\n 0.724247083f, 0.689540545f,\n 0.722128194f, 0.691759258f,\n 0.720002508f, 0.693971461f,\n 0.717870045f, 0.696177131f,\n 0.715730825f, 0.698376249f,\n 0.713584869f, 0.700568794f,\n 0.711432196f, 0.702754744f,\n 0.709272826f, 0.704934080f,\n 0.707106781f, 0.707106781f,\n 0.704934080f, 0.709272826f,\n 0.702754744f, 0.711432196f,\n 0.700568794f, 0.713584869f,\n 0.698376249f, 0.715730825f,\n 0.696177131f, 0.717870045f,\n 0.693971461f, 0.720002508f,\n 0.691759258f, 0.722128194f,\n 0.689540545f, 0.724247083f,\n 0.687315341f, 0.726359155f,\n 0.685083668f, 0.728464390f,\n 0.682845546f, 0.730562769f,\n 0.680600998f, 0.732654272f,\n 0.678350043f, 0.734738878f,\n 0.676092704f, 0.736816569f,\n 0.673829000f, 0.738887324f,\n 0.671558955f, 0.740951125f,\n 0.669282588f, 0.743007952f,\n 0.666999922f, 0.745057785f,\n 0.664710978f, 0.747100606f,\n 0.662415778f, 0.749136395f,\n 0.660114342f, 0.751165132f,\n 0.657806693f, 0.753186799f,\n 0.655492853f, 0.755201377f,\n 0.653172843f, 0.757208847f,\n 0.650846685f, 0.759209189f,\n 0.648514401f, 0.761202385f,\n 0.646176013f, 0.763188417f,\n 0.643831543f, 0.765167266f,\n 0.641481013f, 0.767138912f,\n 0.639124445f, 0.769103338f,\n 0.636761861f, 0.771060524f,\n 0.634393284f, 0.773010453f,\n 0.632018736f, 0.774953107f,\n 0.629638239f, 0.776888466f,\n 0.627251815f, 0.778816512f,\n 0.624859488f, 0.780737229f,\n 0.622461279f, 0.782650596f,\n 0.620057212f, 0.784556597f,\n 0.617647308f, 0.786455214f,\n 0.615231591f, 0.788346428f,\n 0.612810082f, 0.790230221f,\n 0.610382806f, 0.792106577f,\n 0.607949785f, 0.793975478f,\n 0.605511041f, 0.795836905f,\n 0.603066599f, 0.797690841f,\n 0.600616479f, 0.799537269f,\n 0.598160707f, 0.801376172f,\n 0.595699304f, 0.803207531f,\n 0.593232295f, 0.805031331f,\n 0.590759702f, 0.806847554f,\n 0.588281548f, 0.808656182f,\n 0.585797857f, 0.810457198f,\n 0.583308653f, 0.812250587f,\n 0.580813958f, 0.814036330f,\n 0.578313796f, 0.815814411f,\n 0.575808191f, 0.817584813f,\n 0.573297167f, 0.819347520f,\n 0.570780746f, 0.821102515f,\n 0.568258953f, 0.822849781f,\n 0.565731811f, 0.824589303f,\n 0.563199344f, 0.826321063f,\n 0.560661576f, 0.828045045f,\n 0.558118531f, 0.829761234f,\n 0.555570233f, 0.831469612f,\n 0.553016706f, 0.833170165f,\n 0.550457973f, 0.834862875f,\n 0.547894059f, 0.836547727f,\n 0.545324988f, 0.838224706f,\n 0.542750785f, 0.839893794f,\n 0.540171473f, 0.841554977f,\n 0.537587076f, 0.843208240f,\n 0.534997620f, 0.844853565f,\n 0.532403128f, 0.846490939f,\n 0.529803625f, 0.848120345f,\n 0.527199135f, 0.849741768f,\n 0.524589683f, 0.851355193f,\n 0.521975293f, 0.852960605f,\n 0.519355990f, 0.854557988f,\n 0.516731799f, 0.856147328f,\n 0.514102744f, 0.857728610f,\n 0.511468850f, 0.859301818f,\n 0.508830143f, 0.860866939f,\n 0.506186645f, 0.862423956f,\n 0.503538384f, 0.863972856f,\n 0.500885383f, 0.865513624f,\n 0.498227667f, 0.867046246f,\n 0.495565262f, 0.868570706f,\n 0.492898192f, 0.870086991f,\n 0.490226483f, 0.871595087f,\n 0.487550160f, 0.873094978f,\n 0.484869248f, 0.874586652f,\n 0.482183772f, 0.876070094f,\n 0.479493758f, 0.877545290f,\n 0.476799230f, 0.879012226f,\n 0.474100215f, 0.880470889f,\n 0.471396737f, 0.881921264f,\n 0.468688822f, 0.883363339f,\n 0.465976496f, 0.884797098f,\n 0.463259784f, 0.886222530f,\n 0.460538711f, 0.887639620f,\n 0.457813304f, 0.889048356f,\n 0.455083587f, 0.890448723f,\n 0.452349587f, 0.891840709f,\n 0.449611330f, 0.893224301f,\n 0.446868840f, 0.894599486f,\n 0.444122145f, 0.895966250f,\n 0.441371269f, 0.897324581f,\n 0.438616239f, 0.898674466f,\n 0.435857080f, 0.900015892f,\n 0.433093819f, 0.901348847f,\n 0.430326481f, 0.902673318f,\n 0.427555093f, 0.903989293f,\n 0.424779681f, 0.905296759f,\n 0.422000271f, 0.906595705f,\n 0.419216888f, 0.907886116f,\n 0.416429560f, 0.909167983f,\n 0.413638312f, 0.910441292f,\n 0.410843171f, 0.911706032f,\n 0.408044163f, 0.912962190f,\n 0.405241314f, 0.914209756f,\n 0.402434651f, 0.915448716f,\n 0.399624200f, 0.916679060f,\n 0.396809987f, 0.917900776f,\n 0.393992040f, 0.919113852f,\n 0.391170384f, 0.920318277f,\n 0.388345047f, 0.921514039f,\n 0.385516054f, 0.922701128f,\n 0.382683432f, 0.923879533f,\n 0.379847209f, 0.925049241f,\n 0.377007410f, 0.926210242f,\n 0.374164063f, 0.927362526f,\n 0.371317194f, 0.928506080f,\n 0.368466830f, 0.929640896f,\n 0.365612998f, 0.930766961f,\n 0.362755724f, 0.931884266f,\n 0.359895037f, 0.932992799f,\n 0.357030961f, 0.934092550f,\n 0.354163525f, 0.935183510f,\n 0.351292756f, 0.936265667f,\n 0.348418680f, 0.937339012f,\n 0.345541325f, 0.938403534f,\n 0.342660717f, 0.939459224f,\n 0.339776884f, 0.940506071f,\n 0.336889853f, 0.941544065f,\n 0.333999651f, 0.942573198f,\n 0.331106306f, 0.943593458f,\n 0.328209844f, 0.944604837f,\n 0.325310292f, 0.945607325f,\n 0.322407679f, 0.946600913f,\n 0.319502031f, 0.947585591f,\n 0.316593376f, 0.948561350f,\n 0.313681740f, 0.949528181f,\n 0.310767153f, 0.950486074f,\n 0.307849640f, 0.951435021f,\n 0.304929230f, 0.952375013f,\n 0.302005949f, 0.953306040f,\n 0.299079826f, 0.954228095f,\n 0.296150888f, 0.955141168f,\n 0.293219163f, 0.956045251f,\n 0.290284677f, 0.956940336f,\n 0.287347460f, 0.957826413f,\n 0.284407537f, 0.958703475f,\n 0.281464938f, 0.959571513f,\n 0.278519689f, 0.960430519f,\n 0.275571819f, 0.961280486f,\n 0.272621355f, 0.962121404f,\n 0.269668326f, 0.962953267f,\n 0.266712757f, 0.963776066f,\n 0.263754679f, 0.964589793f,\n 0.260794118f, 0.965394442f,\n 0.257831102f, 0.966190003f,\n 0.254865660f, 0.966976471f,\n 0.251897818f, 0.967753837f,\n 0.248927606f, 0.968522094f,\n 0.245955050f, 0.969281235f,\n 0.242980180f, 0.970031253f,\n 0.240003022f, 0.970772141f,\n 0.237023606f, 0.971503891f,\n 0.234041959f, 0.972226497f,\n 0.231058108f, 0.972939952f,\n 0.228072083f, 0.973644250f,\n 0.225083911f, 0.974339383f,\n 0.222093621f, 0.975025345f,\n 0.219101240f, 0.975702130f,\n 0.216106797f, 0.976369731f,\n 0.213110320f, 0.977028143f,\n 0.210111837f, 0.977677358f,\n 0.207111376f, 0.978317371f,\n 0.204108966f, 0.978948175f,\n 0.201104635f, 0.979569766f,\n 0.198098411f, 0.980182136f,\n 0.195090322f, 0.980785280f,\n 0.192080397f, 0.981379193f,\n 0.189068664f, 0.981963869f,\n 0.186055152f, 0.982539302f,\n 0.183039888f, 0.983105487f,\n 0.180022901f, 0.983662419f,\n 0.177004220f, 0.984210092f,\n 0.173983873f, 0.984748502f,\n 0.170961889f, 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-0.399624200f,\n 0.917900776f, -0.396809987f,\n 0.919113852f, -0.393992040f,\n 0.920318277f, -0.391170384f,\n 0.921514039f, -0.388345047f,\n 0.922701128f, -0.385516054f,\n 0.923879533f, -0.382683432f,\n 0.925049241f, -0.379847209f,\n 0.926210242f, -0.377007410f,\n 0.927362526f, -0.374164063f,\n 0.928506080f, -0.371317194f,\n 0.929640896f, -0.368466830f,\n 0.930766961f, -0.365612998f,\n 0.931884266f, -0.362755724f,\n 0.932992799f, -0.359895037f,\n 0.934092550f, -0.357030961f,\n 0.935183510f, -0.354163525f,\n 0.936265667f, -0.351292756f,\n 0.937339012f, -0.348418680f,\n 0.938403534f, -0.345541325f,\n 0.939459224f, -0.342660717f,\n 0.940506071f, -0.339776884f,\n 0.941544065f, -0.336889853f,\n 0.942573198f, -0.333999651f,\n 0.943593458f, -0.331106306f,\n 0.944604837f, -0.328209844f,\n 0.945607325f, -0.325310292f,\n 0.946600913f, -0.322407679f,\n 0.947585591f, -0.319502031f,\n 0.948561350f, -0.316593376f,\n 0.949528181f, -0.313681740f,\n 0.950486074f, -0.310767153f,\n 0.951435021f, -0.307849640f,\n 0.952375013f, -0.304929230f,\n 0.953306040f, -0.302005949f,\n 0.954228095f, -0.299079826f,\n 0.955141168f, -0.296150888f,\n 0.956045251f, -0.293219163f,\n 0.956940336f, -0.290284677f,\n 0.957826413f, -0.287347460f,\n 0.958703475f, -0.284407537f,\n 0.959571513f, -0.281464938f,\n 0.960430519f, -0.278519689f,\n 0.961280486f, -0.275571819f,\n 0.962121404f, -0.272621355f,\n 0.962953267f, -0.269668326f,\n 0.963776066f, -0.266712757f,\n 0.964589793f, -0.263754679f,\n 0.965394442f, -0.260794118f,\n 0.966190003f, -0.257831102f,\n 0.966976471f, -0.254865660f,\n 0.967753837f, -0.251897818f,\n 0.968522094f, -0.248927606f,\n 0.969281235f, -0.245955050f,\n 0.970031253f, -0.242980180f,\n 0.970772141f, -0.240003022f,\n 0.971503891f, -0.237023606f,\n 0.972226497f, -0.234041959f,\n 0.972939952f, -0.231058108f,\n 0.973644250f, -0.228072083f,\n 0.974339383f, -0.225083911f,\n 0.975025345f, -0.222093621f,\n 0.975702130f, -0.219101240f,\n 0.976369731f, -0.216106797f,\n 0.977028143f, -0.213110320f,\n 0.977677358f, -0.210111837f,\n 0.978317371f, -0.207111376f,\n 0.978948175f, -0.204108966f,\n 0.979569766f, -0.201104635f,\n 0.980182136f, -0.198098411f,\n 0.980785280f, -0.195090322f,\n 0.981379193f, -0.192080397f,\n 0.981963869f, -0.189068664f,\n 0.982539302f, -0.186055152f,\n 0.983105487f, -0.183039888f,\n 0.983662419f, -0.180022901f,\n 0.984210092f, -0.177004220f,\n 0.984748502f, -0.173983873f,\n 0.985277642f, -0.170961889f,\n 0.985797509f, -0.167938295f,\n 0.986308097f, -0.164913120f,\n 0.986809402f, -0.161886394f,\n 0.987301418f, -0.158858143f,\n 0.987784142f, -0.155828398f,\n 0.988257568f, -0.152797185f,\n 0.988721692f, -0.149764535f,\n 0.989176510f, -0.146730474f,\n 0.989622017f, -0.143695033f,\n 0.990058210f, -0.140658239f,\n 0.990485084f, -0.137620122f,\n 0.990902635f, -0.134580709f,\n 0.991310860f, -0.131540029f,\n 0.991709754f, -0.128498111f,\n 0.992099313f, -0.125454983f,\n 0.992479535f, -0.122410675f,\n 0.992850414f, -0.119365215f,\n 0.993211949f, -0.116318631f,\n 0.993564136f, -0.113270952f,\n 0.993906970f, -0.110222207f,\n 0.994240449f, -0.107172425f,\n 0.994564571f, -0.104121634f,\n 0.994879331f, -0.101069863f,\n 0.995184727f, -0.098017140f,\n 0.995480755f, -0.094963495f,\n 0.995767414f, -0.091908956f,\n 0.996044701f, -0.088853553f,\n 0.996312612f, -0.085797312f,\n 0.996571146f, -0.082740265f,\n 0.996820299f, -0.079682438f,\n 0.997060070f, -0.076623861f,\n 0.997290457f, -0.073564564f,\n 0.997511456f, -0.070504573f,\n 0.997723067f, -0.067443920f,\n 0.997925286f, -0.064382631f,\n 0.998118113f, -0.061320736f,\n 0.998301545f, -0.058258265f,\n 0.998475581f, -0.055195244f,\n 0.998640218f, -0.052131705f,\n 0.998795456f, -0.049067674f,\n 0.998941293f, -0.046003182f,\n 0.999077728f, -0.042938257f,\n 0.999204759f, -0.039872928f,\n 0.999322385f, -0.036807223f,\n 0.999430605f, -0.033741172f,\n 0.999529418f, -0.030674803f,\n 0.999618822f, -0.027608146f,\n 0.999698819f, -0.024541229f,\n 0.999769405f, -0.021474080f,\n 0.999830582f, -0.018406730f,\n 0.999882347f, -0.015339206f,\n 0.999924702f, -0.012271538f,\n 0.999957645f, -0.009203755f,\n 0.999981175f, -0.006135885f,\n 0.999995294f, -0.003067957f\n};\n\n/** \n* \\par \n* Example code for Floating-point Twiddle factors Generation: \n* \\par \n* 
for(i = 0; i< N/; i++)    \n* {    \n*\ttwiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are in interleaved fashion \n* \n*/\nconst float32_t twiddleCoef_4096[8192] = {\n 1.000000000f, 0.000000000f,\n 0.999998823f, 0.001533980f,\n 0.999995294f, 0.003067957f,\n 0.999989411f, 0.004601926f,\n 0.999981175f, 0.006135885f,\n 0.999970586f, 0.007669829f,\n 0.999957645f, 0.009203755f,\n 0.999942350f, 0.010737659f,\n 0.999924702f, 0.012271538f,\n 0.999904701f, 0.013805389f,\n 0.999882347f, 0.015339206f,\n 0.999857641f, 0.016872988f,\n 0.999830582f, 0.018406730f,\n 0.999801170f, 0.019940429f,\n 0.999769405f, 0.021474080f,\n 0.999735288f, 0.023007681f,\n 0.999698819f, 0.024541229f,\n 0.999659997f, 0.026074718f,\n 0.999618822f, 0.027608146f,\n 0.999575296f, 0.029141509f,\n 0.999529418f, 0.030674803f,\n 0.999481187f, 0.032208025f,\n 0.999430605f, 0.033741172f,\n 0.999377670f, 0.035274239f,\n 0.999322385f, 0.036807223f,\n 0.999264747f, 0.038340120f,\n 0.999204759f, 0.039872928f,\n 0.999142419f, 0.041405641f,\n 0.999077728f, 0.042938257f,\n 0.999010686f, 0.044470772f,\n 0.998941293f, 0.046003182f,\n 0.998869550f, 0.047535484f,\n 0.998795456f, 0.049067674f,\n 0.998719012f, 0.050599749f,\n 0.998640218f, 0.052131705f,\n 0.998559074f, 0.053663538f,\n 0.998475581f, 0.055195244f,\n 0.998389737f, 0.056726821f,\n 0.998301545f, 0.058258265f,\n 0.998211003f, 0.059789571f,\n 0.998118113f, 0.061320736f,\n 0.998022874f, 0.062851758f,\n 0.997925286f, 0.064382631f,\n 0.997825350f, 0.065913353f,\n 0.997723067f, 0.067443920f,\n 0.997618435f, 0.068974328f,\n 0.997511456f, 0.070504573f,\n 0.997402130f, 0.072034653f,\n 0.997290457f, 0.073564564f,\n 0.997176437f, 0.075094301f,\n 0.997060070f, 0.076623861f,\n 0.996941358f, 0.078153242f,\n 0.996820299f, 0.079682438f,\n 0.996696895f, 0.081211447f,\n 0.996571146f, 0.082740265f,\n 0.996443051f, 0.084268888f,\n 0.996312612f, 0.085797312f,\n 0.996179829f, 0.087325535f,\n 0.996044701f, 0.088853553f,\n 0.995907229f, 0.090381361f,\n 0.995767414f, 0.091908956f,\n 0.995625256f, 0.093436336f,\n 0.995480755f, 0.094963495f,\n 0.995333912f, 0.096490431f,\n 0.995184727f, 0.098017140f,\n 0.995033199f, 0.099543619f,\n 0.994879331f, 0.101069863f,\n 0.994723121f, 0.102595869f,\n 0.994564571f, 0.104121634f,\n 0.994403680f, 0.105647154f,\n 0.994240449f, 0.107172425f,\n 0.994074879f, 0.108697444f,\n 0.993906970f, 0.110222207f,\n 0.993736722f, 0.111746711f,\n 0.993564136f, 0.113270952f,\n 0.993389211f, 0.114794927f,\n 0.993211949f, 0.116318631f,\n 0.993032350f, 0.117842062f,\n 0.992850414f, 0.119365215f,\n 0.992666142f, 0.120888087f,\n 0.992479535f, 0.122410675f,\n 0.992290591f, 0.123932975f,\n 0.992099313f, 0.125454983f,\n 0.991905700f, 0.126976696f,\n 0.991709754f, 0.128498111f,\n 0.991511473f, 0.130019223f,\n 0.991310860f, 0.131540029f,\n 0.991107914f, 0.133060525f,\n 0.990902635f, 0.134580709f,\n 0.990695025f, 0.136100575f,\n 0.990485084f, 0.137620122f,\n 0.990272812f, 0.139139344f,\n 0.990058210f, 0.140658239f,\n 0.989841278f, 0.142176804f,\n 0.989622017f, 0.143695033f,\n 0.989400428f, 0.145212925f,\n 0.989176510f, 0.146730474f,\n 0.988950265f, 0.148247679f,\n 0.988721692f, 0.149764535f,\n 0.988490793f, 0.151281038f,\n 0.988257568f, 0.152797185f,\n 0.988022017f, 0.154312973f,\n 0.987784142f, 0.155828398f,\n 0.987543942f, 0.157343456f,\n 0.987301418f, 0.158858143f,\n 0.987056571f, 0.160372457f,\n 0.986809402f, 0.161886394f,\n 0.986559910f, 0.163399949f,\n 0.986308097f, 0.164913120f,\n 0.986053963f, 0.166425904f,\n 0.985797509f, 0.167938295f,\n 0.985538735f, 0.169450291f,\n 0.985277642f, 0.170961889f,\n 0.985014231f, 0.172473084f,\n 0.984748502f, 0.173983873f,\n 0.984480455f, 0.175494253f,\n 0.984210092f, 0.177004220f,\n 0.983937413f, 0.178513771f,\n 0.983662419f, 0.180022901f,\n 0.983385110f, 0.181531608f,\n 0.983105487f, 0.183039888f,\n 0.982823551f, 0.184547737f,\n 0.982539302f, 0.186055152f,\n 0.982252741f, 0.187562129f,\n 0.981963869f, 0.189068664f,\n 0.981672686f, 0.190574755f,\n 0.981379193f, 0.192080397f,\n 0.981083391f, 0.193585587f,\n 0.980785280f, 0.195090322f,\n 0.980484862f, 0.196594598f,\n 0.980182136f, 0.198098411f,\n 0.979877104f, 0.199601758f,\n 0.979569766f, 0.201104635f,\n 0.979260123f, 0.202607039f,\n 0.978948175f, 0.204108966f,\n 0.978633924f, 0.205610413f,\n 0.978317371f, 0.207111376f,\n 0.977998515f, 0.208611852f,\n 0.977677358f, 0.210111837f,\n 0.977353900f, 0.211611327f,\n 0.977028143f, 0.213110320f,\n 0.976700086f, 0.214608811f,\n 0.976369731f, 0.216106797f,\n 0.976037079f, 0.217604275f,\n 0.975702130f, 0.219101240f,\n 0.975364885f, 0.220597690f,\n 0.975025345f, 0.222093621f,\n 0.974683511f, 0.223589029f,\n 0.974339383f, 0.225083911f,\n 0.973992962f, 0.226578264f,\n 0.973644250f, 0.228072083f,\n 0.973293246f, 0.229565366f,\n 0.972939952f, 0.231058108f,\n 0.972584369f, 0.232550307f,\n 0.972226497f, 0.234041959f,\n 0.971866337f, 0.235533059f,\n 0.971503891f, 0.237023606f,\n 0.971139158f, 0.238513595f,\n 0.970772141f, 0.240003022f,\n 0.970402839f, 0.241491885f,\n 0.970031253f, 0.242980180f,\n 0.969657385f, 0.244467903f,\n 0.969281235f, 0.245955050f,\n 0.968902805f, 0.247441619f,\n 0.968522094f, 0.248927606f,\n 0.968139105f, 0.250413007f,\n 0.967753837f, 0.251897818f,\n 0.967366292f, 0.253382037f,\n 0.966976471f, 0.254865660f,\n 0.966584374f, 0.256348682f,\n 0.966190003f, 0.257831102f,\n 0.965793359f, 0.259312915f,\n 0.965394442f, 0.260794118f,\n 0.964993253f, 0.262274707f,\n 0.964589793f, 0.263754679f,\n 0.964184064f, 0.265234030f,\n 0.963776066f, 0.266712757f,\n 0.963365800f, 0.268190857f,\n 0.962953267f, 0.269668326f,\n 0.962538468f, 0.271145160f,\n 0.962121404f, 0.272621355f,\n 0.961702077f, 0.274096910f,\n 0.961280486f, 0.275571819f,\n 0.960856633f, 0.277046080f,\n 0.960430519f, 0.278519689f,\n 0.960002146f, 0.279992643f,\n 0.959571513f, 0.281464938f,\n 0.959138622f, 0.282936570f,\n 0.958703475f, 0.284407537f,\n 0.958266071f, 0.285877835f,\n 0.957826413f, 0.287347460f,\n 0.957384501f, 0.288816408f,\n 0.956940336f, 0.290284677f,\n 0.956493919f, 0.291752263f,\n 0.956045251f, 0.293219163f,\n 0.955594334f, 0.294685372f,\n 0.955141168f, 0.296150888f,\n 0.954685755f, 0.297615707f,\n 0.954228095f, 0.299079826f,\n 0.953768190f, 0.300543241f,\n 0.953306040f, 0.302005949f,\n 0.952841648f, 0.303467947f,\n 0.952375013f, 0.304929230f,\n 0.951906137f, 0.306389795f,\n 0.951435021f, 0.307849640f,\n 0.950961666f, 0.309308760f,\n 0.950486074f, 0.310767153f,\n 0.950008245f, 0.312224814f,\n 0.949528181f, 0.313681740f,\n 0.949045882f, 0.315137929f,\n 0.948561350f, 0.316593376f,\n 0.948074586f, 0.318048077f,\n 0.947585591f, 0.319502031f,\n 0.947094366f, 0.320955232f,\n 0.946600913f, 0.322407679f,\n 0.946105232f, 0.323859367f,\n 0.945607325f, 0.325310292f,\n 0.945107193f, 0.326760452f,\n 0.944604837f, 0.328209844f,\n 0.944100258f, 0.329658463f,\n 0.943593458f, 0.331106306f,\n 0.943084437f, 0.332553370f,\n 0.942573198f, 0.333999651f,\n 0.942059740f, 0.335445147f,\n 0.941544065f, 0.336889853f,\n 0.941026175f, 0.338333767f,\n 0.940506071f, 0.339776884f,\n 0.939983753f, 0.341219202f,\n 0.939459224f, 0.342660717f,\n 0.938932484f, 0.344101426f,\n 0.938403534f, 0.345541325f,\n 0.937872376f, 0.346980411f,\n 0.937339012f, 0.348418680f,\n 0.936803442f, 0.349856130f,\n 0.936265667f, 0.351292756f,\n 0.935725689f, 0.352728556f,\n 0.935183510f, 0.354163525f,\n 0.934639130f, 0.355597662f,\n 0.934092550f, 0.357030961f,\n 0.933543773f, 0.358463421f,\n 0.932992799f, 0.359895037f,\n 0.932439629f, 0.361325806f,\n 0.931884266f, 0.362755724f,\n 0.931326709f, 0.364184790f,\n 0.930766961f, 0.365612998f,\n 0.930205023f, 0.367040346f,\n 0.929640896f, 0.368466830f,\n 0.929074581f, 0.369892447f,\n 0.928506080f, 0.371317194f,\n 0.927935395f, 0.372741067f,\n 0.927362526f, 0.374164063f,\n 0.926787474f, 0.375586178f,\n 0.926210242f, 0.377007410f,\n 0.925630831f, 0.378427755f,\n 0.925049241f, 0.379847209f,\n 0.924465474f, 0.381265769f,\n 0.923879533f, 0.382683432f,\n 0.923291417f, 0.384100195f,\n 0.922701128f, 0.385516054f,\n 0.922108669f, 0.386931006f,\n 0.921514039f, 0.388345047f,\n 0.920917242f, 0.389758174f,\n 0.920318277f, 0.391170384f,\n 0.919717146f, 0.392581674f,\n 0.919113852f, 0.393992040f,\n 0.918508394f, 0.395401479f,\n 0.917900776f, 0.396809987f,\n 0.917290997f, 0.398217562f,\n 0.916679060f, 0.399624200f,\n 0.916064966f, 0.401029897f,\n 0.915448716f, 0.402434651f,\n 0.914830312f, 0.403838458f,\n 0.914209756f, 0.405241314f,\n 0.913587048f, 0.406643217f,\n 0.912962190f, 0.408044163f,\n 0.912335185f, 0.409444149f,\n 0.911706032f, 0.410843171f,\n 0.911074734f, 0.412241227f,\n 0.910441292f, 0.413638312f,\n 0.909805708f, 0.415034424f,\n 0.909167983f, 0.416429560f,\n 0.908528119f, 0.417823716f,\n 0.907886116f, 0.419216888f,\n 0.907241978f, 0.420609074f,\n 0.906595705f, 0.422000271f,\n 0.905947298f, 0.423390474f,\n 0.905296759f, 0.424779681f,\n 0.904644091f, 0.426167889f,\n 0.903989293f, 0.427555093f,\n 0.903332368f, 0.428941292f,\n 0.902673318f, 0.430326481f,\n 0.902012144f, 0.431710658f,\n 0.901348847f, 0.433093819f,\n 0.900683429f, 0.434475961f,\n 0.900015892f, 0.435857080f,\n 0.899346237f, 0.437237174f,\n 0.898674466f, 0.438616239f,\n 0.898000580f, 0.439994271f,\n 0.897324581f, 0.441371269f,\n 0.896646470f, 0.442747228f,\n 0.895966250f, 0.444122145f,\n 0.895283921f, 0.445496017f,\n 0.894599486f, 0.446868840f,\n 0.893912945f, 0.448240612f,\n 0.893224301f, 0.449611330f,\n 0.892533555f, 0.450980989f,\n 0.891840709f, 0.452349587f,\n 0.891145765f, 0.453717121f,\n 0.890448723f, 0.455083587f,\n 0.889749586f, 0.456448982f,\n 0.889048356f, 0.457813304f,\n 0.888345033f, 0.459176548f,\n 0.887639620f, 0.460538711f,\n 0.886932119f, 0.461899791f,\n 0.886222530f, 0.463259784f,\n 0.885510856f, 0.464618686f,\n 0.884797098f, 0.465976496f,\n 0.884081259f, 0.467333209f,\n 0.883363339f, 0.468688822f,\n 0.882643340f, 0.470043332f,\n 0.881921264f, 0.471396737f,\n 0.881197113f, 0.472749032f,\n 0.880470889f, 0.474100215f,\n 0.879742593f, 0.475450282f,\n 0.879012226f, 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-0.604289531f,\n 0.797690841f, -0.603066599f,\n 0.798614995f, -0.601842247f,\n 0.799537269f, -0.600616479f,\n 0.800457662f, -0.599389298f,\n 0.801376172f, -0.598160707f,\n 0.802292796f, -0.596930708f,\n 0.803207531f, -0.595699304f,\n 0.804120377f, -0.594466499f,\n 0.805031331f, -0.593232295f,\n 0.805940391f, -0.591996695f,\n 0.806847554f, -0.590759702f,\n 0.807752818f, -0.589521319f,\n 0.808656182f, -0.588281548f,\n 0.809557642f, -0.587040394f,\n 0.810457198f, -0.585797857f,\n 0.811354847f, -0.584553943f,\n 0.812250587f, -0.583308653f,\n 0.813144415f, -0.582061990f,\n 0.814036330f, -0.580813958f,\n 0.814926329f, -0.579564559f,\n 0.815814411f, -0.578313796f,\n 0.816700573f, -0.577061673f,\n 0.817584813f, -0.575808191f,\n 0.818467130f, -0.574553355f,\n 0.819347520f, -0.573297167f,\n 0.820225983f, -0.572039629f,\n 0.821102515f, -0.570780746f,\n 0.821977115f, -0.569520519f,\n 0.822849781f, -0.568258953f,\n 0.823720511f, -0.566996049f,\n 0.824589303f, -0.565731811f,\n 0.825456154f, -0.564466242f,\n 0.826321063f, -0.563199344f,\n 0.827184027f, -0.561931121f,\n 0.828045045f, -0.560661576f,\n 0.828904115f, -0.559390712f,\n 0.829761234f, -0.558118531f,\n 0.830616400f, -0.556845037f,\n 0.831469612f, -0.555570233f,\n 0.832320868f, -0.554294121f,\n 0.833170165f, -0.553016706f,\n 0.834017501f, -0.551737988f,\n 0.834862875f, -0.550457973f,\n 0.835706284f, -0.549176662f,\n 0.836547727f, -0.547894059f,\n 0.837387202f, -0.546610167f,\n 0.838224706f, -0.545324988f,\n 0.839060237f, -0.544038527f,\n 0.839893794f, -0.542750785f,\n 0.840725375f, -0.541461766f,\n 0.841554977f, -0.540171473f,\n 0.842382600f, -0.538879909f,\n 0.843208240f, -0.537587076f,\n 0.844031895f, -0.536292979f,\n 0.844853565f, -0.534997620f,\n 0.845673247f, -0.533701002f,\n 0.846490939f, -0.532403128f,\n 0.847306639f, -0.531104001f,\n 0.848120345f, -0.529803625f,\n 0.848932055f, -0.528502002f,\n 0.849741768f, -0.527199135f,\n 0.850549481f, -0.525895027f,\n 0.851355193f, -0.524589683f,\n 0.852158902f, -0.523283103f,\n 0.852960605f, -0.521975293f,\n 0.853760301f, -0.520666254f,\n 0.854557988f, -0.519355990f,\n 0.855353665f, -0.518044504f,\n 0.856147328f, -0.516731799f,\n 0.856938977f, -0.515417878f,\n 0.857728610f, -0.514102744f,\n 0.858516224f, -0.512786401f,\n 0.859301818f, -0.511468850f,\n 0.860085390f, -0.510150097f,\n 0.860866939f, -0.508830143f,\n 0.861646461f, -0.507508991f,\n 0.862423956f, -0.506186645f,\n 0.863199422f, -0.504863109f,\n 0.863972856f, -0.503538384f,\n 0.864744258f, -0.502212474f,\n 0.865513624f, -0.500885383f,\n 0.866280954f, -0.499557113f,\n 0.867046246f, -0.498227667f,\n 0.867809497f, -0.496897049f,\n 0.868570706f, -0.495565262f,\n 0.869329871f, -0.494232309f,\n 0.870086991f, -0.492898192f,\n 0.870842063f, -0.491562916f,\n 0.871595087f, -0.490226483f,\n 0.872346059f, -0.488888897f,\n 0.873094978f, -0.487550160f,\n 0.873841843f, -0.486210276f,\n 0.874586652f, -0.484869248f,\n 0.875329403f, -0.483527079f,\n 0.876070094f, -0.482183772f,\n 0.876808724f, -0.480839331f,\n 0.877545290f, -0.479493758f,\n 0.878279792f, -0.478147056f,\n 0.879012226f, -0.476799230f,\n 0.879742593f, -0.475450282f,\n 0.880470889f, -0.474100215f,\n 0.881197113f, -0.472749032f,\n 0.881921264f, -0.471396737f,\n 0.882643340f, -0.470043332f,\n 0.883363339f, -0.468688822f,\n 0.884081259f, -0.467333209f,\n 0.884797098f, -0.465976496f,\n 0.885510856f, -0.464618686f,\n 0.886222530f, -0.463259784f,\n 0.886932119f, -0.461899791f,\n 0.887639620f, -0.460538711f,\n 0.888345033f, -0.459176548f,\n 0.889048356f, -0.457813304f,\n 0.889749586f, -0.456448982f,\n 0.890448723f, -0.455083587f,\n 0.891145765f, -0.453717121f,\n 0.891840709f, -0.452349587f,\n 0.892533555f, -0.450980989f,\n 0.893224301f, -0.449611330f,\n 0.893912945f, -0.448240612f,\n 0.894599486f, -0.446868840f,\n 0.895283921f, -0.445496017f,\n 0.895966250f, -0.444122145f,\n 0.896646470f, -0.442747228f,\n 0.897324581f, -0.441371269f,\n 0.898000580f, -0.439994271f,\n 0.898674466f, -0.438616239f,\n 0.899346237f, -0.437237174f,\n 0.900015892f, -0.435857080f,\n 0.900683429f, -0.434475961f,\n 0.901348847f, -0.433093819f,\n 0.902012144f, -0.431710658f,\n 0.902673318f, -0.430326481f,\n 0.903332368f, -0.428941292f,\n 0.903989293f, -0.427555093f,\n 0.904644091f, -0.426167889f,\n 0.905296759f, -0.424779681f,\n 0.905947298f, -0.423390474f,\n 0.906595705f, -0.422000271f,\n 0.907241978f, -0.420609074f,\n 0.907886116f, -0.419216888f,\n 0.908528119f, -0.417823716f,\n 0.909167983f, -0.416429560f,\n 0.909805708f, -0.415034424f,\n 0.910441292f, -0.413638312f,\n 0.911074734f, -0.412241227f,\n 0.911706032f, -0.410843171f,\n 0.912335185f, -0.409444149f,\n 0.912962190f, -0.408044163f,\n 0.913587048f, -0.406643217f,\n 0.914209756f, -0.405241314f,\n 0.914830312f, -0.403838458f,\n 0.915448716f, -0.402434651f,\n 0.916064966f, -0.401029897f,\n 0.916679060f, -0.399624200f,\n 0.917290997f, -0.398217562f,\n 0.917900776f, -0.396809987f,\n 0.918508394f, -0.395401479f,\n 0.919113852f, -0.393992040f,\n 0.919717146f, -0.392581674f,\n 0.920318277f, -0.391170384f,\n 0.920917242f, -0.389758174f,\n 0.921514039f, -0.388345047f,\n 0.922108669f, -0.386931006f,\n 0.922701128f, -0.385516054f,\n 0.923291417f, -0.384100195f,\n 0.923879533f, -0.382683432f,\n 0.924465474f, -0.381265769f,\n 0.925049241f, -0.379847209f,\n 0.925630831f, -0.378427755f,\n 0.926210242f, -0.377007410f,\n 0.926787474f, -0.375586178f,\n 0.927362526f, -0.374164063f,\n 0.927935395f, -0.372741067f,\n 0.928506080f, -0.371317194f,\n 0.929074581f, -0.369892447f,\n 0.929640896f, -0.368466830f,\n 0.930205023f, -0.367040346f,\n 0.930766961f, -0.365612998f,\n 0.931326709f, -0.364184790f,\n 0.931884266f, -0.362755724f,\n 0.932439629f, -0.361325806f,\n 0.932992799f, -0.359895037f,\n 0.933543773f, -0.358463421f,\n 0.934092550f, -0.357030961f,\n 0.934639130f, -0.355597662f,\n 0.935183510f, -0.354163525f,\n 0.935725689f, -0.352728556f,\n 0.936265667f, -0.351292756f,\n 0.936803442f, -0.349856130f,\n 0.937339012f, -0.348418680f,\n 0.937872376f, -0.346980411f,\n 0.938403534f, -0.345541325f,\n 0.938932484f, -0.344101426f,\n 0.939459224f, -0.342660717f,\n 0.939983753f, -0.341219202f,\n 0.940506071f, -0.339776884f,\n 0.941026175f, -0.338333767f,\n 0.941544065f, -0.336889853f,\n 0.942059740f, -0.335445147f,\n 0.942573198f, -0.333999651f,\n 0.943084437f, -0.332553370f,\n 0.943593458f, -0.331106306f,\n 0.944100258f, -0.329658463f,\n 0.944604837f, -0.328209844f,\n 0.945107193f, -0.326760452f,\n 0.945607325f, -0.325310292f,\n 0.946105232f, -0.323859367f,\n 0.946600913f, -0.322407679f,\n 0.947094366f, -0.320955232f,\n 0.947585591f, -0.319502031f,\n 0.948074586f, -0.318048077f,\n 0.948561350f, -0.316593376f,\n 0.949045882f, -0.315137929f,\n 0.949528181f, -0.313681740f,\n 0.950008245f, -0.312224814f,\n 0.950486074f, -0.310767153f,\n 0.950961666f, -0.309308760f,\n 0.951435021f, -0.307849640f,\n 0.951906137f, -0.306389795f,\n 0.952375013f, -0.304929230f,\n 0.952841648f, -0.303467947f,\n 0.953306040f, -0.302005949f,\n 0.953768190f, -0.300543241f,\n 0.954228095f, -0.299079826f,\n 0.954685755f, -0.297615707f,\n 0.955141168f, -0.296150888f,\n 0.955594334f, -0.294685372f,\n 0.956045251f, -0.293219163f,\n 0.956493919f, -0.291752263f,\n 0.956940336f, -0.290284677f,\n 0.957384501f, -0.288816408f,\n 0.957826413f, -0.287347460f,\n 0.958266071f, -0.285877835f,\n 0.958703475f, -0.284407537f,\n 0.959138622f, -0.282936570f,\n 0.959571513f, -0.281464938f,\n 0.960002146f, -0.279992643f,\n 0.960430519f, -0.278519689f,\n 0.960856633f, -0.277046080f,\n 0.961280486f, -0.275571819f,\n 0.961702077f, -0.274096910f,\n 0.962121404f, -0.272621355f,\n 0.962538468f, -0.271145160f,\n 0.962953267f, -0.269668326f,\n 0.963365800f, -0.268190857f,\n 0.963776066f, -0.266712757f,\n 0.964184064f, -0.265234030f,\n 0.964589793f, -0.263754679f,\n 0.964993253f, -0.262274707f,\n 0.965394442f, -0.260794118f,\n 0.965793359f, -0.259312915f,\n 0.966190003f, -0.257831102f,\n 0.966584374f, -0.256348682f,\n 0.966976471f, -0.254865660f,\n 0.967366292f, -0.253382037f,\n 0.967753837f, -0.251897818f,\n 0.968139105f, -0.250413007f,\n 0.968522094f, -0.248927606f,\n 0.968902805f, -0.247441619f,\n 0.969281235f, -0.245955050f,\n 0.969657385f, -0.244467903f,\n 0.970031253f, -0.242980180f,\n 0.970402839f, -0.241491885f,\n 0.970772141f, -0.240003022f,\n 0.971139158f, -0.238513595f,\n 0.971503891f, -0.237023606f,\n 0.971866337f, -0.235533059f,\n 0.972226497f, -0.234041959f,\n 0.972584369f, -0.232550307f,\n 0.972939952f, -0.231058108f,\n 0.973293246f, -0.229565366f,\n 0.973644250f, -0.228072083f,\n 0.973992962f, -0.226578264f,\n 0.974339383f, -0.225083911f,\n 0.974683511f, -0.223589029f,\n 0.975025345f, -0.222093621f,\n 0.975364885f, -0.220597690f,\n 0.975702130f, -0.219101240f,\n 0.976037079f, -0.217604275f,\n 0.976369731f, -0.216106797f,\n 0.976700086f, -0.214608811f,\n 0.977028143f, -0.213110320f,\n 0.977353900f, -0.211611327f,\n 0.977677358f, -0.210111837f,\n 0.977998515f, -0.208611852f,\n 0.978317371f, -0.207111376f,\n 0.978633924f, -0.205610413f,\n 0.978948175f, -0.204108966f,\n 0.979260123f, -0.202607039f,\n 0.979569766f, -0.201104635f,\n 0.979877104f, -0.199601758f,\n 0.980182136f, -0.198098411f,\n 0.980484862f, -0.196594598f,\n 0.980785280f, -0.195090322f,\n 0.981083391f, -0.193585587f,\n 0.981379193f, -0.192080397f,\n 0.981672686f, -0.190574755f,\n 0.981963869f, -0.189068664f,\n 0.982252741f, -0.187562129f,\n 0.982539302f, -0.186055152f,\n 0.982823551f, -0.184547737f,\n 0.983105487f, -0.183039888f,\n 0.983385110f, -0.181531608f,\n 0.983662419f, -0.180022901f,\n 0.983937413f, -0.178513771f,\n 0.984210092f, -0.177004220f,\n 0.984480455f, -0.175494253f,\n 0.984748502f, -0.173983873f,\n 0.985014231f, -0.172473084f,\n 0.985277642f, -0.170961889f,\n 0.985538735f, -0.169450291f,\n 0.985797509f, -0.167938295f,\n 0.986053963f, -0.166425904f,\n 0.986308097f, -0.164913120f,\n 0.986559910f, -0.163399949f,\n 0.986809402f, -0.161886394f,\n 0.987056571f, -0.160372457f,\n 0.987301418f, -0.158858143f,\n 0.987543942f, -0.157343456f,\n 0.987784142f, -0.155828398f,\n 0.988022017f, -0.154312973f,\n 0.988257568f, -0.152797185f,\n 0.988490793f, -0.151281038f,\n 0.988721692f, -0.149764535f,\n 0.988950265f, -0.148247679f,\n 0.989176510f, -0.146730474f,\n 0.989400428f, -0.145212925f,\n 0.989622017f, -0.143695033f,\n 0.989841278f, -0.142176804f,\n 0.990058210f, -0.140658239f,\n 0.990272812f, -0.139139344f,\n 0.990485084f, -0.137620122f,\n 0.990695025f, -0.136100575f,\n 0.990902635f, -0.134580709f,\n 0.991107914f, -0.133060525f,\n 0.991310860f, -0.131540029f,\n 0.991511473f, -0.130019223f,\n 0.991709754f, -0.128498111f,\n 0.991905700f, -0.126976696f,\n 0.992099313f, -0.125454983f,\n 0.992290591f, -0.123932975f,\n 0.992479535f, -0.122410675f,\n 0.992666142f, -0.120888087f,\n 0.992850414f, -0.119365215f,\n 0.993032350f, -0.117842062f,\n 0.993211949f, -0.116318631f,\n 0.993389211f, -0.114794927f,\n 0.993564136f, -0.113270952f,\n 0.993736722f, -0.111746711f,\n 0.993906970f, -0.110222207f,\n 0.994074879f, -0.108697444f,\n 0.994240449f, -0.107172425f,\n 0.994403680f, -0.105647154f,\n 0.994564571f, -0.104121634f,\n 0.994723121f, -0.102595869f,\n 0.994879331f, -0.101069863f,\n 0.995033199f, -0.099543619f,\n 0.995184727f, -0.098017140f,\n 0.995333912f, -0.096490431f,\n 0.995480755f, -0.094963495f,\n 0.995625256f, -0.093436336f,\n 0.995767414f, -0.091908956f,\n 0.995907229f, -0.090381361f,\n 0.996044701f, -0.088853553f,\n 0.996179829f, -0.087325535f,\n 0.996312612f, -0.085797312f,\n 0.996443051f, -0.084268888f,\n 0.996571146f, -0.082740265f,\n 0.996696895f, -0.081211447f,\n 0.996820299f, -0.079682438f,\n 0.996941358f, -0.078153242f,\n 0.997060070f, -0.076623861f,\n 0.997176437f, -0.075094301f,\n 0.997290457f, -0.073564564f,\n 0.997402130f, -0.072034653f,\n 0.997511456f, -0.070504573f,\n 0.997618435f, -0.068974328f,\n 0.997723067f, -0.067443920f,\n 0.997825350f, -0.065913353f,\n 0.997925286f, -0.064382631f,\n 0.998022874f, -0.062851758f,\n 0.998118113f, -0.061320736f,\n 0.998211003f, -0.059789571f,\n 0.998301545f, -0.058258265f,\n 0.998389737f, -0.056726821f,\n 0.998475581f, -0.055195244f,\n 0.998559074f, -0.053663538f,\n 0.998640218f, -0.052131705f,\n 0.998719012f, -0.050599749f,\n 0.998795456f, -0.049067674f,\n 0.998869550f, -0.047535484f,\n 0.998941293f, -0.046003182f,\n 0.999010686f, -0.044470772f,\n 0.999077728f, -0.042938257f,\n 0.999142419f, -0.041405641f,\n 0.999204759f, -0.039872928f,\n 0.999264747f, -0.038340120f,\n 0.999322385f, -0.036807223f,\n 0.999377670f, -0.035274239f,\n 0.999430605f, -0.033741172f,\n 0.999481187f, -0.032208025f,\n 0.999529418f, -0.030674803f,\n 0.999575296f, -0.029141509f,\n 0.999618822f, -0.027608146f,\n 0.999659997f, -0.026074718f,\n 0.999698819f, -0.024541229f,\n 0.999735288f, -0.023007681f,\n 0.999769405f, -0.021474080f,\n 0.999801170f, -0.019940429f,\n 0.999830582f, -0.018406730f,\n 0.999857641f, -0.016872988f,\n 0.999882347f, -0.015339206f,\n 0.999904701f, -0.013805389f,\n 0.999924702f, -0.012271538f,\n 0.999942350f, -0.010737659f,\n 0.999957645f, -0.009203755f,\n 0.999970586f, -0.007669829f,\n 0.999981175f, -0.006135885f,\n 0.999989411f, -0.004601926f,\n 0.999995294f, -0.003067957f,\n 0.999998823f, -0.001533980f\n};\n\n/* \n* @brief Q31 Twiddle factors Table \n*/\n\n/** \n* \\par \n* Example code for Q31 Twiddle factors Generation:: \n* \\par \n* 
for(i = 0; i< 3N/4; i++)    \n* {    \n*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    \n*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are interleaved fashion \n* \\par \n* Convert Floating point to Q31(Fixed point 1.31): \n*\tround(twiddleCoefQ31(i) * pow(2, 31)) \n* \n*/\n\nconst q31_t twiddleCoefQ31[6144] = {\n 0x7fffffff, 0x0, 0x7ffff621, 0x3243f5, 0x7fffd886, 0x6487e3, 0x7fffa72c,\n 0x96cbc1,\n 0x7fff6216, 0xc90f88, 0x7fff0943, 0xfb5330, 0x7ffe9cb2, 0x12d96b1,\n 0x7ffe1c65, 0x15fda03,\n 0x7ffd885a, 0x1921d20, 0x7ffce093, 0x1c45ffe, 0x7ffc250f, 0x1f6a297,\n 0x7ffb55ce, 0x228e4e2,\n 0x7ffa72d1, 0x25b26d7, 0x7ff97c18, 0x28d6870, 0x7ff871a2, 0x2bfa9a4,\n 0x7ff75370, 0x2f1ea6c,\n 0x7ff62182, 0x3242abf, 0x7ff4dbd9, 0x3566a96, 0x7ff38274, 0x388a9ea,\n 0x7ff21553, 0x3bae8b2,\n 0x7ff09478, 0x3ed26e6, 0x7feeffe1, 0x41f6480, 0x7fed5791, 0x451a177,\n 0x7feb9b85, 0x483ddc3,\n 0x7fe9cbc0, 0x4b6195d, 0x7fe7e841, 0x4e8543e, 0x7fe5f108, 0x51a8e5c,\n 0x7fe3e616, 0x54cc7b1,\n 0x7fe1c76b, 0x57f0035, 0x7fdf9508, 0x5b137df, 0x7fdd4eec, 0x5e36ea9,\n 0x7fdaf519, 0x615a48b,\n 0x7fd8878e, 0x647d97c, 0x7fd6064c, 0x67a0d76, 0x7fd37153, 0x6ac406f,\n 0x7fd0c8a3, 0x6de7262,\n 0x7fce0c3e, 0x710a345, 0x7fcb3c23, 0x742d311, 0x7fc85854, 0x77501be,\n 0x7fc560cf, 0x7a72f45,\n 0x7fc25596, 0x7d95b9e, 0x7fbf36aa, 0x80b86c2, 0x7fbc040a, 0x83db0a7,\n 0x7fb8bdb8, 0x86fd947,\n 0x7fb563b3, 0x8a2009a, 0x7fb1f5fc, 0x8d42699, 0x7fae7495, 0x9064b3a,\n 0x7faadf7c, 0x9386e78,\n 0x7fa736b4, 0x96a9049, 0x7fa37a3c, 0x99cb0a7, 0x7f9faa15, 0x9cecf89,\n 0x7f9bc640, 0xa00ece8,\n 0x7f97cebd, 0xa3308bd, 0x7f93c38c, 0xa6522fe, 0x7f8fa4b0, 0xa973ba5,\n 0x7f8b7227, 0xac952aa,\n 0x7f872bf3, 0xafb6805, 0x7f82d214, 0xb2d7baf, 0x7f7e648c, 0xb5f8d9f,\n 0x7f79e35a, 0xb919dcf,\n 0x7f754e80, 0xbc3ac35, 0x7f70a5fe, 0xbf5b8cb, 0x7f6be9d4, 0xc27c389,\n 0x7f671a05, 0xc59cc68,\n 0x7f62368f, 0xc8bd35e, 0x7f5d3f75, 0xcbdd865, 0x7f5834b7, 0xcefdb76,\n 0x7f531655, 0xd21dc87,\n 0x7f4de451, 0xd53db92, 0x7f489eaa, 0xd85d88f, 0x7f434563, 0xdb7d376,\n 0x7f3dd87c, 0xde9cc40,\n 0x7f3857f6, 0xe1bc2e4, 0x7f32c3d1, 0xe4db75b, 0x7f2d1c0e, 0xe7fa99e,\n 0x7f2760af, 0xeb199a4,\n 0x7f2191b4, 0xee38766, 0x7f1baf1e, 0xf1572dc, 0x7f15b8ee, 0xf475bff,\n 0x7f0faf25, 0xf7942c7,\n 0x7f0991c4, 0xfab272b, 0x7f0360cb, 0xfdd0926, 0x7efd1c3c, 0x100ee8ad,\n 0x7ef6c418, 0x1040c5bb,\n 0x7ef05860, 0x1072a048, 0x7ee9d914, 0x10a4784b, 0x7ee34636, 0x10d64dbd,\n 0x7edc9fc6, 0x11082096,\n 0x7ed5e5c6, 0x1139f0cf, 0x7ecf1837, 0x116bbe60, 0x7ec8371a, 0x119d8941,\n 0x7ec14270, 0x11cf516a,\n 0x7eba3a39, 0x120116d5, 0x7eb31e78, 0x1232d979, 0x7eabef2c, 0x1264994e,\n 0x7ea4ac58, 0x1296564d,\n 0x7e9d55fc, 0x12c8106f, 0x7e95ec1a, 0x12f9c7aa, 0x7e8e6eb2, 0x132b7bf9,\n 0x7e86ddc6, 0x135d2d53,\n 0x7e7f3957, 0x138edbb1, 0x7e778166, 0x13c0870a, 0x7e6fb5f4, 0x13f22f58,\n 0x7e67d703, 0x1423d492,\n 0x7e5fe493, 0x145576b1, 0x7e57dea7, 0x148715ae, 0x7e4fc53e, 0x14b8b17f,\n 0x7e47985b, 0x14ea4a1f,\n 0x7e3f57ff, 0x151bdf86, 0x7e37042a, 0x154d71aa, 0x7e2e9cdf, 0x157f0086,\n 0x7e26221f, 0x15b08c12,\n 0x7e1d93ea, 0x15e21445, 0x7e14f242, 0x16139918, 0x7e0c3d29, 0x16451a83,\n 0x7e0374a0, 0x1676987f,\n 0x7dfa98a8, 0x16a81305, 0x7df1a942, 0x16d98a0c, 0x7de8a670, 0x170afd8d,\n 0x7ddf9034, 0x173c6d80,\n 0x7dd6668f, 0x176dd9de, 0x7dcd2981, 0x179f429f, 0x7dc3d90d, 0x17d0a7bc,\n 0x7dba7534, 0x1802092c,\n 0x7db0fdf8, 0x183366e9, 0x7da77359, 0x1864c0ea, 0x7d9dd55a, 0x18961728,\n 0x7d9423fc, 0x18c7699b,\n 0x7d8a5f40, 0x18f8b83c, 0x7d808728, 0x192a0304, 0x7d769bb5, 0x195b49ea,\n 0x7d6c9ce9, 0x198c8ce7,\n 0x7d628ac6, 0x19bdcbf3, 0x7d58654d, 0x19ef0707, 0x7d4e2c7f, 0x1a203e1b,\n 0x7d43e05e, 0x1a517128,\n 0x7d3980ec, 0x1a82a026, 0x7d2f0e2b, 0x1ab3cb0d, 0x7d24881b, 0x1ae4f1d6,\n 0x7d19eebf, 0x1b161479,\n 0x7d0f4218, 0x1b4732ef, 0x7d048228, 0x1b784d30, 0x7cf9aef0, 0x1ba96335,\n 0x7ceec873, 0x1bda74f6,\n 0x7ce3ceb2, 0x1c0b826a, 0x7cd8c1ae, 0x1c3c8b8c, 0x7ccda169, 0x1c6d9053,\n 0x7cc26de5, 0x1c9e90b8,\n 0x7cb72724, 0x1ccf8cb3, 0x7cabcd28, 0x1d00843d, 0x7ca05ff1, 0x1d31774d,\n 0x7c94df83, 0x1d6265dd,\n 0x7c894bde, 0x1d934fe5, 0x7c7da505, 0x1dc4355e, 0x7c71eaf9, 0x1df5163f,\n 0x7c661dbc, 0x1e25f282,\n 0x7c5a3d50, 0x1e56ca1e, 0x7c4e49b7, 0x1e879d0d, 0x7c4242f2, 0x1eb86b46,\n 0x7c362904, 0x1ee934c3,\n 0x7c29fbee, 0x1f19f97b, 0x7c1dbbb3, 0x1f4ab968, 0x7c116853, 0x1f7b7481,\n 0x7c0501d2, 0x1fac2abf,\n 0x7bf88830, 0x1fdcdc1b, 0x7bebfb70, 0x200d888d, 0x7bdf5b94, 0x203e300d,\n 0x7bd2a89e, 0x206ed295,\n 0x7bc5e290, 0x209f701c, 0x7bb9096b, 0x20d0089c, 0x7bac1d31, 0x21009c0c,\n 0x7b9f1de6, 0x21312a65,\n 0x7b920b89, 0x2161b3a0, 0x7b84e61f, 0x219237b5, 0x7b77ada8, 0x21c2b69c,\n 0x7b6a6227, 0x21f3304f,\n 0x7b5d039e, 0x2223a4c5, 0x7b4f920e, 0x225413f8, 0x7b420d7a, 0x22847de0,\n 0x7b3475e5, 0x22b4e274,\n 0x7b26cb4f, 0x22e541af, 0x7b190dbc, 0x23159b88, 0x7b0b3d2c, 0x2345eff8,\n 0x7afd59a4, 0x23763ef7,\n 0x7aef6323, 0x23a6887f, 0x7ae159ae, 0x23d6cc87, 0x7ad33d45, 0x24070b08,\n 0x7ac50dec, 0x243743fa,\n 0x7ab6cba4, 0x24677758, 0x7aa8766f, 0x2497a517, 0x7a9a0e50, 0x24c7cd33,\n 0x7a8b9348, 0x24f7efa2,\n 0x7a7d055b, 0x25280c5e, 0x7a6e648a, 0x2558235f, 0x7a5fb0d8, 0x2588349d,\n 0x7a50ea47, 0x25b84012,\n 0x7a4210d8, 0x25e845b6, 0x7a332490, 0x26184581, 0x7a24256f, 0x26483f6c,\n 0x7a151378, 0x26783370,\n 0x7a05eead, 0x26a82186, 0x79f6b711, 0x26d809a5, 0x79e76ca7, 0x2707ebc7,\n 0x79d80f6f, 0x2737c7e3,\n 0x79c89f6e, 0x27679df4, 0x79b91ca4, 0x27976df1, 0x79a98715, 0x27c737d3,\n 0x7999dec4, 0x27f6fb92,\n 0x798a23b1, 0x2826b928, 0x797a55e0, 0x2856708d, 0x796a7554, 0x288621b9,\n 0x795a820e, 0x28b5cca5,\n 0x794a7c12, 0x28e5714b, 0x793a6361, 0x29150fa1, 0x792a37fe, 0x2944a7a2,\n 0x7919f9ec, 0x29743946,\n 0x7909a92d, 0x29a3c485, 0x78f945c3, 0x29d34958, 0x78e8cfb2, 0x2a02c7b8,\n 0x78d846fb, 0x2a323f9e,\n 0x78c7aba2, 0x2a61b101, 0x78b6fda8, 0x2a911bdc, 0x78a63d11, 0x2ac08026,\n 0x789569df, 0x2aefddd8,\n 0x78848414, 0x2b1f34eb, 0x78738bb3, 0x2b4e8558, 0x786280bf, 0x2b7dcf17,\n 0x7851633b, 0x2bad1221,\n 0x78403329, 0x2bdc4e6f, 0x782ef08b, 0x2c0b83fa, 0x781d9b65, 0x2c3ab2b9,\n 0x780c33b8, 0x2c69daa6,\n 0x77fab989, 0x2c98fbba, 0x77e92cd9, 0x2cc815ee, 0x77d78daa, 0x2cf72939,\n 0x77c5dc01, 0x2d263596,\n 0x77b417df, 0x2d553afc, 0x77a24148, 0x2d843964, 0x7790583e, 0x2db330c7,\n 0x777e5cc3, 0x2de2211e,\n 0x776c4edb, 0x2e110a62, 0x775a2e89, 0x2e3fec8b, 0x7747fbce, 0x2e6ec792,\n 0x7735b6af, 0x2e9d9b70,\n 0x77235f2d, 0x2ecc681e, 0x7710f54c, 0x2efb2d95, 0x76fe790e, 0x2f29ebcc,\n 0x76ebea77, 0x2f58a2be,\n 0x76d94989, 0x2f875262, 0x76c69647, 0x2fb5fab2, 0x76b3d0b4, 0x2fe49ba7,\n 0x76a0f8d2, 0x30133539,\n 0x768e0ea6, 0x3041c761, 0x767b1231, 0x30705217, 0x76680376, 0x309ed556,\n 0x7654e279, 0x30cd5115,\n 0x7641af3d, 0x30fbc54d, 0x762e69c4, 0x312a31f8, 0x761b1211, 0x3158970e,\n 0x7607a828, 0x3186f487,\n 0x75f42c0b, 0x31b54a5e, 0x75e09dbd, 0x31e39889, 0x75ccfd42, 0x3211df04,\n 0x75b94a9c, 0x32401dc6,\n 0x75a585cf, 0x326e54c7, 0x7591aedd, 0x329c8402, 0x757dc5ca, 0x32caab6f,\n 0x7569ca99, 0x32f8cb07,\n 0x7555bd4c, 0x3326e2c3, 0x75419de7, 0x3354f29b, 0x752d6c6c, 0x3382fa88,\n 0x751928e0, 0x33b0fa84,\n 0x7504d345, 0x33def287, 0x74f06b9e, 0x340ce28b, 0x74dbf1ef, 0x343aca87,\n 0x74c7663a, 0x3468aa76,\n 0x74b2c884, 0x34968250, 0x749e18cd, 0x34c4520d, 0x7489571c, 0x34f219a8,\n 0x74748371, 0x351fd918,\n 0x745f9dd1, 0x354d9057, 0x744aa63f, 0x357b3f5d, 0x74359cbd, 0x35a8e625,\n 0x74208150, 0x35d684a6,\n 0x740b53fb, 0x36041ad9, 0x73f614c0, 0x3631a8b8, 0x73e0c3a3, 0x365f2e3b,\n 0x73cb60a8, 0x368cab5c,\n 0x73b5ebd1, 0x36ba2014, 0x73a06522, 0x36e78c5b, 0x738acc9e, 0x3714f02a,\n 0x73752249, 0x37424b7b,\n 0x735f6626, 0x376f9e46, 0x73499838, 0x379ce885, 0x7333b883, 0x37ca2a30,\n 0x731dc70a, 0x37f76341,\n 0x7307c3d0, 0x382493b0, 0x72f1aed9, 0x3851bb77, 0x72db8828, 0x387eda8e,\n 0x72c54fc1, 0x38abf0ef,\n 0x72af05a7, 0x38d8fe93, 0x7298a9dd, 0x39060373, 0x72823c67, 0x3932ff87,\n 0x726bbd48, 0x395ff2c9,\n 0x72552c85, 0x398cdd32, 0x723e8a20, 0x39b9bebc, 0x7227d61c, 0x39e6975e,\n 0x7211107e, 0x3a136712,\n 0x71fa3949, 0x3a402dd2, 0x71e35080, 0x3a6ceb96, 0x71cc5626, 0x3a99a057,\n 0x71b54a41, 0x3ac64c0f,\n 0x719e2cd2, 0x3af2eeb7, 0x7186fdde, 0x3b1f8848, 0x716fbd68, 0x3b4c18ba,\n 0x71586b74, 0x3b78a007,\n 0x71410805, 0x3ba51e29, 0x7129931f, 0x3bd19318, 0x71120cc5, 0x3bfdfecd,\n 0x70fa74fc, 0x3c2a6142,\n 0x70e2cbc6, 0x3c56ba70, 0x70cb1128, 0x3c830a50, 0x70b34525, 0x3caf50da,\n 0x709b67c0, 0x3cdb8e09,\n 0x708378ff, 0x3d07c1d6, 0x706b78e3, 0x3d33ec39, 0x70536771, 0x3d600d2c,\n 0x703b44ad, 0x3d8c24a8,\n 0x7023109a, 0x3db832a6, 0x700acb3c, 0x3de4371f, 0x6ff27497, 0x3e10320d,\n 0x6fda0cae, 0x3e3c2369,\n 0x6fc19385, 0x3e680b2c, 0x6fa90921, 0x3e93e950, 0x6f906d84, 0x3ebfbdcd,\n 0x6f77c0b3, 0x3eeb889c,\n 0x6f5f02b2, 0x3f1749b8, 0x6f463383, 0x3f430119, 0x6f2d532c, 0x3f6eaeb8,\n 0x6f1461b0, 0x3f9a5290,\n 0x6efb5f12, 0x3fc5ec98, 0x6ee24b57, 0x3ff17cca, 0x6ec92683, 0x401d0321,\n 0x6eaff099, 0x40487f94,\n 0x6e96a99d, 0x4073f21d, 0x6e7d5193, 0x409f5ab6, 0x6e63e87f, 0x40cab958,\n 0x6e4a6e66, 0x40f60dfb,\n 0x6e30e34a, 0x4121589b, 0x6e174730, 0x414c992f, 0x6dfd9a1c, 0x4177cfb1,\n 0x6de3dc11, 0x41a2fc1a,\n 0x6dca0d14, 0x41ce1e65, 0x6db02d29, 0x41f93689, 0x6d963c54, 0x42244481,\n 0x6d7c3a98, 0x424f4845,\n 0x6d6227fa, 0x427a41d0, 0x6d48047e, 0x42a5311b, 0x6d2dd027, 0x42d0161e,\n 0x6d138afb, 0x42faf0d4,\n 0x6cf934fc, 0x4325c135, 0x6cdece2f, 0x4350873c, 0x6cc45698, 0x437b42e1,\n 0x6ca9ce3b, 0x43a5f41e,\n 0x6c8f351c, 0x43d09aed, 0x6c748b3f, 0x43fb3746, 0x6c59d0a9, 0x4425c923,\n 0x6c3f055d, 0x4450507e,\n 0x6c242960, 0x447acd50, 0x6c093cb6, 0x44a53f93, 0x6bee3f62, 0x44cfa740,\n 0x6bd3316a, 0x44fa0450,\n 0x6bb812d1, 0x452456bd, 0x6b9ce39b, 0x454e9e80, 0x6b81a3cd, 0x4578db93,\n 0x6b66536b, 0x45a30df0,\n 0x6b4af279, 0x45cd358f, 0x6b2f80fb, 0x45f7526b, 0x6b13fef5, 0x4621647d,\n 0x6af86c6c, 0x464b6bbe,\n 0x6adcc964, 0x46756828, 0x6ac115e2, 0x469f59b4, 0x6aa551e9, 0x46c9405c,\n 0x6a897d7d, 0x46f31c1a,\n 0x6a6d98a4, 0x471cece7, 0x6a51a361, 0x4746b2bc, 0x6a359db9, 0x47706d93,\n 0x6a1987b0, 0x479a1d67,\n 0x69fd614a, 0x47c3c22f, 0x69e12a8c, 0x47ed5be6, 0x69c4e37a, 0x4816ea86,\n 0x69a88c19, 0x48406e08,\n 0x698c246c, 0x4869e665, 0x696fac78, 0x48935397, 0x69532442, 0x48bcb599,\n 0x69368bce, 0x48e60c62,\n 0x6919e320, 0x490f57ee, 0x68fd2a3d, 0x49389836, 0x68e06129, 0x4961cd33,\n 0x68c387e9, 0x498af6df,\n 0x68a69e81, 0x49b41533, 0x6889a4f6, 0x49dd282a, 0x686c9b4b, 0x4a062fbd,\n 0x684f8186, 0x4a2f2be6,\n 0x683257ab, 0x4a581c9e, 0x68151dbe, 0x4a8101de, 0x67f7d3c5, 0x4aa9dba2,\n 0x67da79c3, 0x4ad2a9e2,\n 0x67bd0fbd, 0x4afb6c98, 0x679f95b7, 0x4b2423be, 0x67820bb7, 0x4b4ccf4d,\n 0x676471c0, 0x4b756f40,\n 0x6746c7d8, 0x4b9e0390, 0x67290e02, 0x4bc68c36, 0x670b4444, 0x4bef092d,\n 0x66ed6aa1, 0x4c177a6e,\n 0x66cf8120, 0x4c3fdff4, 0x66b187c3, 0x4c6839b7, 0x66937e91, 0x4c9087b1,\n 0x6675658c, 0x4cb8c9dd,\n 0x66573cbb, 0x4ce10034, 0x66390422, 0x4d092ab0, 0x661abbc5, 0x4d31494b,\n 0x65fc63a9, 0x4d595bfe,\n 0x65ddfbd3, 0x4d8162c4, 0x65bf8447, 0x4da95d96, 0x65a0fd0b, 0x4dd14c6e,\n 0x65826622, 0x4df92f46,\n 0x6563bf92, 0x4e210617, 0x6545095f, 0x4e48d0dd, 0x6526438f, 0x4e708f8f,\n 0x65076e25, 0x4e984229,\n 0x64e88926, 0x4ebfe8a5, 0x64c99498, 0x4ee782fb, 0x64aa907f, 0x4f0f1126,\n 0x648b7ce0, 0x4f369320,\n 0x646c59bf, 0x4f5e08e3, 0x644d2722, 0x4f857269, 0x642de50d, 0x4faccfab,\n 0x640e9386, 0x4fd420a4,\n 0x63ef3290, 0x4ffb654d, 0x63cfc231, 0x50229da1, 0x63b0426d, 0x5049c999,\n 0x6390b34a, 0x5070e92f,\n 0x637114cc, 0x5097fc5e, 0x635166f9, 0x50bf031f, 0x6331a9d4, 0x50e5fd6d,\n 0x6311dd64, 0x510ceb40,\n 0x62f201ac, 0x5133cc94, 0x62d216b3, 0x515aa162, 0x62b21c7b, 0x518169a5,\n 0x6292130c, 0x51a82555,\n 0x6271fa69, 0x51ced46e, 0x6251d298, 0x51f576ea, 0x62319b9d, 0x521c0cc2,\n 0x6211557e, 0x524295f0,\n 0x61f1003f, 0x5269126e, 0x61d09be5, 0x528f8238, 0x61b02876, 0x52b5e546,\n 0x618fa5f7, 0x52dc3b92,\n 0x616f146c, 0x53028518, 0x614e73da, 0x5328c1d0, 0x612dc447, 0x534ef1b5,\n 0x610d05b7, 0x537514c2,\n 0x60ec3830, 0x539b2af0, 0x60cb5bb7, 0x53c13439, 0x60aa7050, 0x53e73097,\n 0x60897601, 0x540d2005,\n 0x60686ccf, 0x5433027d, 0x604754bf, 0x5458d7f9, 0x60262dd6, 0x547ea073,\n 0x6004f819, 0x54a45be6,\n 0x5fe3b38d, 0x54ca0a4b, 0x5fc26038, 0x54efab9c, 0x5fa0fe1f, 0x55153fd4,\n 0x5f7f8d46, 0x553ac6ee,\n 0x5f5e0db3, 0x556040e2, 0x5f3c7f6b, 0x5585adad, 0x5f1ae274, 0x55ab0d46,\n 0x5ef936d1, 0x55d05faa,\n 0x5ed77c8a, 0x55f5a4d2, 0x5eb5b3a2, 0x561adcb9, 0x5e93dc1f, 0x56400758,\n 0x5e71f606, 0x566524aa,\n 0x5e50015d, 0x568a34a9, 0x5e2dfe29, 0x56af3750, 0x5e0bec6e, 0x56d42c99,\n 0x5de9cc33, 0x56f9147e,\n 0x5dc79d7c, 0x571deefa, 0x5da5604f, 0x5742bc06, 0x5d8314b1, 0x57677b9d,\n 0x5d60baa7, 0x578c2dba,\n 0x5d3e5237, 0x57b0d256, 0x5d1bdb65, 0x57d5696d, 0x5cf95638, 0x57f9f2f8,\n 0x5cd6c2b5, 0x581e6ef1,\n 0x5cb420e0, 0x5842dd54, 0x5c9170bf, 0x58673e1b, 0x5c6eb258, 0x588b9140,\n 0x5c4be5b0, 0x58afd6bd,\n 0x5c290acc, 0x58d40e8c, 0x5c0621b2, 0x58f838a9, 0x5be32a67, 0x591c550e,\n 0x5bc024f0, 0x594063b5,\n 0x5b9d1154, 0x59646498, 0x5b79ef96, 0x598857b2, 0x5b56bfbd, 0x59ac3cfd,\n 0x5b3381ce, 0x59d01475,\n 0x5b1035cf, 0x59f3de12, 0x5aecdbc5, 0x5a1799d1, 0x5ac973b5, 0x5a3b47ab,\n 0x5aa5fda5, 0x5a5ee79a,\n 0x5a82799a, 0x5a82799a, 0x5a5ee79a, 0x5aa5fda5, 0x5a3b47ab, 0x5ac973b5,\n 0x5a1799d1, 0x5aecdbc5,\n 0x59f3de12, 0x5b1035cf, 0x59d01475, 0x5b3381ce, 0x59ac3cfd, 0x5b56bfbd,\n 0x598857b2, 0x5b79ef96,\n 0x59646498, 0x5b9d1154, 0x594063b5, 0x5bc024f0, 0x591c550e, 0x5be32a67,\n 0x58f838a9, 0x5c0621b2,\n 0x58d40e8c, 0x5c290acc, 0x58afd6bd, 0x5c4be5b0, 0x588b9140, 0x5c6eb258,\n 0x58673e1b, 0x5c9170bf,\n 0x5842dd54, 0x5cb420e0, 0x581e6ef1, 0x5cd6c2b5, 0x57f9f2f8, 0x5cf95638,\n 0x57d5696d, 0x5d1bdb65,\n 0x57b0d256, 0x5d3e5237, 0x578c2dba, 0x5d60baa7, 0x57677b9d, 0x5d8314b1,\n 0x5742bc06, 0x5da5604f,\n 0x571deefa, 0x5dc79d7c, 0x56f9147e, 0x5de9cc33, 0x56d42c99, 0x5e0bec6e,\n 0x56af3750, 0x5e2dfe29,\n 0x568a34a9, 0x5e50015d, 0x566524aa, 0x5e71f606, 0x56400758, 0x5e93dc1f,\n 0x561adcb9, 0x5eb5b3a2,\n 0x55f5a4d2, 0x5ed77c8a, 0x55d05faa, 0x5ef936d1, 0x55ab0d46, 0x5f1ae274,\n 0x5585adad, 0x5f3c7f6b,\n 0x556040e2, 0x5f5e0db3, 0x553ac6ee, 0x5f7f8d46, 0x55153fd4, 0x5fa0fe1f,\n 0x54efab9c, 0x5fc26038,\n 0x54ca0a4b, 0x5fe3b38d, 0x54a45be6, 0x6004f819, 0x547ea073, 0x60262dd6,\n 0x5458d7f9, 0x604754bf,\n 0x5433027d, 0x60686ccf, 0x540d2005, 0x60897601, 0x53e73097, 0x60aa7050,\n 0x53c13439, 0x60cb5bb7,\n 0x539b2af0, 0x60ec3830, 0x537514c2, 0x610d05b7, 0x534ef1b5, 0x612dc447,\n 0x5328c1d0, 0x614e73da,\n 0x53028518, 0x616f146c, 0x52dc3b92, 0x618fa5f7, 0x52b5e546, 0x61b02876,\n 0x528f8238, 0x61d09be5,\n 0x5269126e, 0x61f1003f, 0x524295f0, 0x6211557e, 0x521c0cc2, 0x62319b9d,\n 0x51f576ea, 0x6251d298,\n 0x51ced46e, 0x6271fa69, 0x51a82555, 0x6292130c, 0x518169a5, 0x62b21c7b,\n 0x515aa162, 0x62d216b3,\n 0x5133cc94, 0x62f201ac, 0x510ceb40, 0x6311dd64, 0x50e5fd6d, 0x6331a9d4,\n 0x50bf031f, 0x635166f9,\n 0x5097fc5e, 0x637114cc, 0x5070e92f, 0x6390b34a, 0x5049c999, 0x63b0426d,\n 0x50229da1, 0x63cfc231,\n 0x4ffb654d, 0x63ef3290, 0x4fd420a4, 0x640e9386, 0x4faccfab, 0x642de50d,\n 0x4f857269, 0x644d2722,\n 0x4f5e08e3, 0x646c59bf, 0x4f369320, 0x648b7ce0, 0x4f0f1126, 0x64aa907f,\n 0x4ee782fb, 0x64c99498,\n 0x4ebfe8a5, 0x64e88926, 0x4e984229, 0x65076e25, 0x4e708f8f, 0x6526438f,\n 0x4e48d0dd, 0x6545095f,\n 0x4e210617, 0x6563bf92, 0x4df92f46, 0x65826622, 0x4dd14c6e, 0x65a0fd0b,\n 0x4da95d96, 0x65bf8447,\n 0x4d8162c4, 0x65ddfbd3, 0x4d595bfe, 0x65fc63a9, 0x4d31494b, 0x661abbc5,\n 0x4d092ab0, 0x66390422,\n 0x4ce10034, 0x66573cbb, 0x4cb8c9dd, 0x6675658c, 0x4c9087b1, 0x66937e91,\n 0x4c6839b7, 0x66b187c3,\n 0x4c3fdff4, 0x66cf8120, 0x4c177a6e, 0x66ed6aa1, 0x4bef092d, 0x670b4444,\n 0x4bc68c36, 0x67290e02,\n 0x4b9e0390, 0x6746c7d8, 0x4b756f40, 0x676471c0, 0x4b4ccf4d, 0x67820bb7,\n 0x4b2423be, 0x679f95b7,\n 0x4afb6c98, 0x67bd0fbd, 0x4ad2a9e2, 0x67da79c3, 0x4aa9dba2, 0x67f7d3c5,\n 0x4a8101de, 0x68151dbe,\n 0x4a581c9e, 0x683257ab, 0x4a2f2be6, 0x684f8186, 0x4a062fbd, 0x686c9b4b,\n 0x49dd282a, 0x6889a4f6,\n 0x49b41533, 0x68a69e81, 0x498af6df, 0x68c387e9, 0x4961cd33, 0x68e06129,\n 0x49389836, 0x68fd2a3d,\n 0x490f57ee, 0x6919e320, 0x48e60c62, 0x69368bce, 0x48bcb599, 0x69532442,\n 0x48935397, 0x696fac78,\n 0x4869e665, 0x698c246c, 0x48406e08, 0x69a88c19, 0x4816ea86, 0x69c4e37a,\n 0x47ed5be6, 0x69e12a8c,\n 0x47c3c22f, 0x69fd614a, 0x479a1d67, 0x6a1987b0, 0x47706d93, 0x6a359db9,\n 0x4746b2bc, 0x6a51a361,\n 0x471cece7, 0x6a6d98a4, 0x46f31c1a, 0x6a897d7d, 0x46c9405c, 0x6aa551e9,\n 0x469f59b4, 0x6ac115e2,\n 0x46756828, 0x6adcc964, 0x464b6bbe, 0x6af86c6c, 0x4621647d, 0x6b13fef5,\n 0x45f7526b, 0x6b2f80fb,\n 0x45cd358f, 0x6b4af279, 0x45a30df0, 0x6b66536b, 0x4578db93, 0x6b81a3cd,\n 0x454e9e80, 0x6b9ce39b,\n 0x452456bd, 0x6bb812d1, 0x44fa0450, 0x6bd3316a, 0x44cfa740, 0x6bee3f62,\n 0x44a53f93, 0x6c093cb6,\n 0x447acd50, 0x6c242960, 0x4450507e, 0x6c3f055d, 0x4425c923, 0x6c59d0a9,\n 0x43fb3746, 0x6c748b3f,\n 0x43d09aed, 0x6c8f351c, 0x43a5f41e, 0x6ca9ce3b, 0x437b42e1, 0x6cc45698,\n 0x4350873c, 0x6cdece2f,\n 0x4325c135, 0x6cf934fc, 0x42faf0d4, 0x6d138afb, 0x42d0161e, 0x6d2dd027,\n 0x42a5311b, 0x6d48047e,\n 0x427a41d0, 0x6d6227fa, 0x424f4845, 0x6d7c3a98, 0x42244481, 0x6d963c54,\n 0x41f93689, 0x6db02d29,\n 0x41ce1e65, 0x6dca0d14, 0x41a2fc1a, 0x6de3dc11, 0x4177cfb1, 0x6dfd9a1c,\n 0x414c992f, 0x6e174730,\n 0x4121589b, 0x6e30e34a, 0x40f60dfb, 0x6e4a6e66, 0x40cab958, 0x6e63e87f,\n 0x409f5ab6, 0x6e7d5193,\n 0x4073f21d, 0x6e96a99d, 0x40487f94, 0x6eaff099, 0x401d0321, 0x6ec92683,\n 0x3ff17cca, 0x6ee24b57,\n 0x3fc5ec98, 0x6efb5f12, 0x3f9a5290, 0x6f1461b0, 0x3f6eaeb8, 0x6f2d532c,\n 0x3f430119, 0x6f463383,\n 0x3f1749b8, 0x6f5f02b2, 0x3eeb889c, 0x6f77c0b3, 0x3ebfbdcd, 0x6f906d84,\n 0x3e93e950, 0x6fa90921,\n 0x3e680b2c, 0x6fc19385, 0x3e3c2369, 0x6fda0cae, 0x3e10320d, 0x6ff27497,\n 0x3de4371f, 0x700acb3c,\n 0x3db832a6, 0x7023109a, 0x3d8c24a8, 0x703b44ad, 0x3d600d2c, 0x70536771,\n 0x3d33ec39, 0x706b78e3,\n 0x3d07c1d6, 0x708378ff, 0x3cdb8e09, 0x709b67c0, 0x3caf50da, 0x70b34525,\n 0x3c830a50, 0x70cb1128,\n 0x3c56ba70, 0x70e2cbc6, 0x3c2a6142, 0x70fa74fc, 0x3bfdfecd, 0x71120cc5,\n 0x3bd19318, 0x7129931f,\n 0x3ba51e29, 0x71410805, 0x3b78a007, 0x71586b74, 0x3b4c18ba, 0x716fbd68,\n 0x3b1f8848, 0x7186fdde,\n 0x3af2eeb7, 0x719e2cd2, 0x3ac64c0f, 0x71b54a41, 0x3a99a057, 0x71cc5626,\n 0x3a6ceb96, 0x71e35080,\n 0x3a402dd2, 0x71fa3949, 0x3a136712, 0x7211107e, 0x39e6975e, 0x7227d61c,\n 0x39b9bebc, 0x723e8a20,\n 0x398cdd32, 0x72552c85, 0x395ff2c9, 0x726bbd48, 0x3932ff87, 0x72823c67,\n 0x39060373, 0x7298a9dd,\n 0x38d8fe93, 0x72af05a7, 0x38abf0ef, 0x72c54fc1, 0x387eda8e, 0x72db8828,\n 0x3851bb77, 0x72f1aed9,\n 0x382493b0, 0x7307c3d0, 0x37f76341, 0x731dc70a, 0x37ca2a30, 0x7333b883,\n 0x379ce885, 0x73499838,\n 0x376f9e46, 0x735f6626, 0x37424b7b, 0x73752249, 0x3714f02a, 0x738acc9e,\n 0x36e78c5b, 0x73a06522,\n 0x36ba2014, 0x73b5ebd1, 0x368cab5c, 0x73cb60a8, 0x365f2e3b, 0x73e0c3a3,\n 0x3631a8b8, 0x73f614c0,\n 0x36041ad9, 0x740b53fb, 0x35d684a6, 0x74208150, 0x35a8e625, 0x74359cbd,\n 0x357b3f5d, 0x744aa63f,\n 0x354d9057, 0x745f9dd1, 0x351fd918, 0x74748371, 0x34f219a8, 0x7489571c,\n 0x34c4520d, 0x749e18cd,\n 0x34968250, 0x74b2c884, 0x3468aa76, 0x74c7663a, 0x343aca87, 0x74dbf1ef,\n 0x340ce28b, 0x74f06b9e,\n 0x33def287, 0x7504d345, 0x33b0fa84, 0x751928e0, 0x3382fa88, 0x752d6c6c,\n 0x3354f29b, 0x75419de7,\n 0x3326e2c3, 0x7555bd4c, 0x32f8cb07, 0x7569ca99, 0x32caab6f, 0x757dc5ca,\n 0x329c8402, 0x7591aedd,\n 0x326e54c7, 0x75a585cf, 0x32401dc6, 0x75b94a9c, 0x3211df04, 0x75ccfd42,\n 0x31e39889, 0x75e09dbd,\n 0x31b54a5e, 0x75f42c0b, 0x3186f487, 0x7607a828, 0x3158970e, 0x761b1211,\n 0x312a31f8, 0x762e69c4,\n 0x30fbc54d, 0x7641af3d, 0x30cd5115, 0x7654e279, 0x309ed556, 0x76680376,\n 0x30705217, 0x767b1231,\n 0x3041c761, 0x768e0ea6, 0x30133539, 0x76a0f8d2, 0x2fe49ba7, 0x76b3d0b4,\n 0x2fb5fab2, 0x76c69647,\n 0x2f875262, 0x76d94989, 0x2f58a2be, 0x76ebea77, 0x2f29ebcc, 0x76fe790e,\n 0x2efb2d95, 0x7710f54c,\n 0x2ecc681e, 0x77235f2d, 0x2e9d9b70, 0x7735b6af, 0x2e6ec792, 0x7747fbce,\n 0x2e3fec8b, 0x775a2e89,\n 0x2e110a62, 0x776c4edb, 0x2de2211e, 0x777e5cc3, 0x2db330c7, 0x7790583e,\n 0x2d843964, 0x77a24148,\n 0x2d553afc, 0x77b417df, 0x2d263596, 0x77c5dc01, 0x2cf72939, 0x77d78daa,\n 0x2cc815ee, 0x77e92cd9,\n 0x2c98fbba, 0x77fab989, 0x2c69daa6, 0x780c33b8, 0x2c3ab2b9, 0x781d9b65,\n 0x2c0b83fa, 0x782ef08b,\n 0x2bdc4e6f, 0x78403329, 0x2bad1221, 0x7851633b, 0x2b7dcf17, 0x786280bf,\n 0x2b4e8558, 0x78738bb3,\n 0x2b1f34eb, 0x78848414, 0x2aefddd8, 0x789569df, 0x2ac08026, 0x78a63d11,\n 0x2a911bdc, 0x78b6fda8,\n 0x2a61b101, 0x78c7aba2, 0x2a323f9e, 0x78d846fb, 0x2a02c7b8, 0x78e8cfb2,\n 0x29d34958, 0x78f945c3,\n 0x29a3c485, 0x7909a92d, 0x29743946, 0x7919f9ec, 0x2944a7a2, 0x792a37fe,\n 0x29150fa1, 0x793a6361,\n 0x28e5714b, 0x794a7c12, 0x28b5cca5, 0x795a820e, 0x288621b9, 0x796a7554,\n 0x2856708d, 0x797a55e0,\n 0x2826b928, 0x798a23b1, 0x27f6fb92, 0x7999dec4, 0x27c737d3, 0x79a98715,\n 0x27976df1, 0x79b91ca4,\n 0x27679df4, 0x79c89f6e, 0x2737c7e3, 0x79d80f6f, 0x2707ebc7, 0x79e76ca7,\n 0x26d809a5, 0x79f6b711,\n 0x26a82186, 0x7a05eead, 0x26783370, 0x7a151378, 0x26483f6c, 0x7a24256f,\n 0x26184581, 0x7a332490,\n 0x25e845b6, 0x7a4210d8, 0x25b84012, 0x7a50ea47, 0x2588349d, 0x7a5fb0d8,\n 0x2558235f, 0x7a6e648a,\n 0x25280c5e, 0x7a7d055b, 0x24f7efa2, 0x7a8b9348, 0x24c7cd33, 0x7a9a0e50,\n 0x2497a517, 0x7aa8766f,\n 0x24677758, 0x7ab6cba4, 0x243743fa, 0x7ac50dec, 0x24070b08, 0x7ad33d45,\n 0x23d6cc87, 0x7ae159ae,\n 0x23a6887f, 0x7aef6323, 0x23763ef7, 0x7afd59a4, 0x2345eff8, 0x7b0b3d2c,\n 0x23159b88, 0x7b190dbc,\n 0x22e541af, 0x7b26cb4f, 0x22b4e274, 0x7b3475e5, 0x22847de0, 0x7b420d7a,\n 0x225413f8, 0x7b4f920e,\n 0x2223a4c5, 0x7b5d039e, 0x21f3304f, 0x7b6a6227, 0x21c2b69c, 0x7b77ada8,\n 0x219237b5, 0x7b84e61f,\n 0x2161b3a0, 0x7b920b89, 0x21312a65, 0x7b9f1de6, 0x21009c0c, 0x7bac1d31,\n 0x20d0089c, 0x7bb9096b,\n 0x209f701c, 0x7bc5e290, 0x206ed295, 0x7bd2a89e, 0x203e300d, 0x7bdf5b94,\n 0x200d888d, 0x7bebfb70,\n 0x1fdcdc1b, 0x7bf88830, 0x1fac2abf, 0x7c0501d2, 0x1f7b7481, 0x7c116853,\n 0x1f4ab968, 0x7c1dbbb3,\n 0x1f19f97b, 0x7c29fbee, 0x1ee934c3, 0x7c362904, 0x1eb86b46, 0x7c4242f2,\n 0x1e879d0d, 0x7c4e49b7,\n 0x1e56ca1e, 0x7c5a3d50, 0x1e25f282, 0x7c661dbc, 0x1df5163f, 0x7c71eaf9,\n 0x1dc4355e, 0x7c7da505,\n 0x1d934fe5, 0x7c894bde, 0x1d6265dd, 0x7c94df83, 0x1d31774d, 0x7ca05ff1,\n 0x1d00843d, 0x7cabcd28,\n 0x1ccf8cb3, 0x7cb72724, 0x1c9e90b8, 0x7cc26de5, 0x1c6d9053, 0x7ccda169,\n 0x1c3c8b8c, 0x7cd8c1ae,\n 0x1c0b826a, 0x7ce3ceb2, 0x1bda74f6, 0x7ceec873, 0x1ba96335, 0x7cf9aef0,\n 0x1b784d30, 0x7d048228,\n 0x1b4732ef, 0x7d0f4218, 0x1b161479, 0x7d19eebf, 0x1ae4f1d6, 0x7d24881b,\n 0x1ab3cb0d, 0x7d2f0e2b,\n 0x1a82a026, 0x7d3980ec, 0x1a517128, 0x7d43e05e, 0x1a203e1b, 0x7d4e2c7f,\n 0x19ef0707, 0x7d58654d,\n 0x19bdcbf3, 0x7d628ac6, 0x198c8ce7, 0x7d6c9ce9, 0x195b49ea, 0x7d769bb5,\n 0x192a0304, 0x7d808728,\n 0x18f8b83c, 0x7d8a5f40, 0x18c7699b, 0x7d9423fc, 0x18961728, 0x7d9dd55a,\n 0x1864c0ea, 0x7da77359,\n 0x183366e9, 0x7db0fdf8, 0x1802092c, 0x7dba7534, 0x17d0a7bc, 0x7dc3d90d,\n 0x179f429f, 0x7dcd2981,\n 0x176dd9de, 0x7dd6668f, 0x173c6d80, 0x7ddf9034, 0x170afd8d, 0x7de8a670,\n 0x16d98a0c, 0x7df1a942,\n 0x16a81305, 0x7dfa98a8, 0x1676987f, 0x7e0374a0, 0x16451a83, 0x7e0c3d29,\n 0x16139918, 0x7e14f242,\n 0x15e21445, 0x7e1d93ea, 0x15b08c12, 0x7e26221f, 0x157f0086, 0x7e2e9cdf,\n 0x154d71aa, 0x7e37042a,\n 0x151bdf86, 0x7e3f57ff, 0x14ea4a1f, 0x7e47985b, 0x14b8b17f, 0x7e4fc53e,\n 0x148715ae, 0x7e57dea7,\n 0x145576b1, 0x7e5fe493, 0x1423d492, 0x7e67d703, 0x13f22f58, 0x7e6fb5f4,\n 0x13c0870a, 0x7e778166,\n 0x138edbb1, 0x7e7f3957, 0x135d2d53, 0x7e86ddc6, 0x132b7bf9, 0x7e8e6eb2,\n 0x12f9c7aa, 0x7e95ec1a,\n 0x12c8106f, 0x7e9d55fc, 0x1296564d, 0x7ea4ac58, 0x1264994e, 0x7eabef2c,\n 0x1232d979, 0x7eb31e78,\n 0x120116d5, 0x7eba3a39, 0x11cf516a, 0x7ec14270, 0x119d8941, 0x7ec8371a,\n 0x116bbe60, 0x7ecf1837,\n 0x1139f0cf, 0x7ed5e5c6, 0x11082096, 0x7edc9fc6, 0x10d64dbd, 0x7ee34636,\n 0x10a4784b, 0x7ee9d914,\n 0x1072a048, 0x7ef05860, 0x1040c5bb, 0x7ef6c418, 0x100ee8ad, 0x7efd1c3c,\n 0xfdd0926, 0x7f0360cb,\n 0xfab272b, 0x7f0991c4, 0xf7942c7, 0x7f0faf25, 0xf475bff, 0x7f15b8ee,\n 0xf1572dc, 0x7f1baf1e,\n 0xee38766, 0x7f2191b4, 0xeb199a4, 0x7f2760af, 0xe7fa99e, 0x7f2d1c0e,\n 0xe4db75b, 0x7f32c3d1,\n 0xe1bc2e4, 0x7f3857f6, 0xde9cc40, 0x7f3dd87c, 0xdb7d376, 0x7f434563,\n 0xd85d88f, 0x7f489eaa,\n 0xd53db92, 0x7f4de451, 0xd21dc87, 0x7f531655, 0xcefdb76, 0x7f5834b7,\n 0xcbdd865, 0x7f5d3f75,\n 0xc8bd35e, 0x7f62368f, 0xc59cc68, 0x7f671a05, 0xc27c389, 0x7f6be9d4,\n 0xbf5b8cb, 0x7f70a5fe,\n 0xbc3ac35, 0x7f754e80, 0xb919dcf, 0x7f79e35a, 0xb5f8d9f, 0x7f7e648c,\n 0xb2d7baf, 0x7f82d214,\n 0xafb6805, 0x7f872bf3, 0xac952aa, 0x7f8b7227, 0xa973ba5, 0x7f8fa4b0,\n 0xa6522fe, 0x7f93c38c,\n 0xa3308bd, 0x7f97cebd, 0xa00ece8, 0x7f9bc640, 0x9cecf89, 0x7f9faa15,\n 0x99cb0a7, 0x7fa37a3c,\n 0x96a9049, 0x7fa736b4, 0x9386e78, 0x7faadf7c, 0x9064b3a, 0x7fae7495,\n 0x8d42699, 0x7fb1f5fc,\n 0x8a2009a, 0x7fb563b3, 0x86fd947, 0x7fb8bdb8, 0x83db0a7, 0x7fbc040a,\n 0x80b86c2, 0x7fbf36aa,\n 0x7d95b9e, 0x7fc25596, 0x7a72f45, 0x7fc560cf, 0x77501be, 0x7fc85854,\n 0x742d311, 0x7fcb3c23,\n 0x710a345, 0x7fce0c3e, 0x6de7262, 0x7fd0c8a3, 0x6ac406f, 0x7fd37153,\n 0x67a0d76, 0x7fd6064c,\n 0x647d97c, 0x7fd8878e, 0x615a48b, 0x7fdaf519, 0x5e36ea9, 0x7fdd4eec,\n 0x5b137df, 0x7fdf9508,\n 0x57f0035, 0x7fe1c76b, 0x54cc7b1, 0x7fe3e616, 0x51a8e5c, 0x7fe5f108,\n 0x4e8543e, 0x7fe7e841,\n 0x4b6195d, 0x7fe9cbc0, 0x483ddc3, 0x7feb9b85, 0x451a177, 0x7fed5791,\n 0x41f6480, 0x7feeffe1,\n 0x3ed26e6, 0x7ff09478, 0x3bae8b2, 0x7ff21553, 0x388a9ea, 0x7ff38274,\n 0x3566a96, 0x7ff4dbd9,\n 0x3242abf, 0x7ff62182, 0x2f1ea6c, 0x7ff75370, 0x2bfa9a4, 0x7ff871a2,\n 0x28d6870, 0x7ff97c18,\n 0x25b26d7, 0x7ffa72d1, 0x228e4e2, 0x7ffb55ce, 0x1f6a297, 0x7ffc250f,\n 0x1c45ffe, 0x7ffce093,\n 0x1921d20, 0x7ffd885a, 0x15fda03, 0x7ffe1c65, 0x12d96b1, 0x7ffe9cb2,\n 0xfb5330, 0x7fff0943,\n 0xc90f88, 0x7fff6216, 0x96cbc1, 0x7fffa72c, 0x6487e3, 0x7fffd886, 0x3243f5,\n 0x7ffff621,\n 0x0, 0x7fffffff, 0xffcdbc0b, 0x7ffff621, 0xff9b781d, 0x7fffd886, 0xff69343f,\n 0x7fffa72c,\n 0xff36f078, 0x7fff6216, 0xff04acd0, 0x7fff0943, 0xfed2694f, 0x7ffe9cb2,\n 0xfea025fd, 0x7ffe1c65,\n 0xfe6de2e0, 0x7ffd885a, 0xfe3ba002, 0x7ffce093, 0xfe095d69, 0x7ffc250f,\n 0xfdd71b1e, 0x7ffb55ce,\n 0xfda4d929, 0x7ffa72d1, 0xfd729790, 0x7ff97c18, 0xfd40565c, 0x7ff871a2,\n 0xfd0e1594, 0x7ff75370,\n 0xfcdbd541, 0x7ff62182, 0xfca9956a, 0x7ff4dbd9, 0xfc775616, 0x7ff38274,\n 0xfc45174e, 0x7ff21553,\n 0xfc12d91a, 0x7ff09478, 0xfbe09b80, 0x7feeffe1, 0xfbae5e89, 0x7fed5791,\n 0xfb7c223d, 0x7feb9b85,\n 0xfb49e6a3, 0x7fe9cbc0, 0xfb17abc2, 0x7fe7e841, 0xfae571a4, 0x7fe5f108,\n 0xfab3384f, 0x7fe3e616,\n 0xfa80ffcb, 0x7fe1c76b, 0xfa4ec821, 0x7fdf9508, 0xfa1c9157, 0x7fdd4eec,\n 0xf9ea5b75, 0x7fdaf519,\n 0xf9b82684, 0x7fd8878e, 0xf985f28a, 0x7fd6064c, 0xf953bf91, 0x7fd37153,\n 0xf9218d9e, 0x7fd0c8a3,\n 0xf8ef5cbb, 0x7fce0c3e, 0xf8bd2cef, 0x7fcb3c23, 0xf88afe42, 0x7fc85854,\n 0xf858d0bb, 0x7fc560cf,\n 0xf826a462, 0x7fc25596, 0xf7f4793e, 0x7fbf36aa, 0xf7c24f59, 0x7fbc040a,\n 0xf79026b9, 0x7fb8bdb8,\n 0xf75dff66, 0x7fb563b3, 0xf72bd967, 0x7fb1f5fc, 0xf6f9b4c6, 0x7fae7495,\n 0xf6c79188, 0x7faadf7c,\n 0xf6956fb7, 0x7fa736b4, 0xf6634f59, 0x7fa37a3c, 0xf6313077, 0x7f9faa15,\n 0xf5ff1318, 0x7f9bc640,\n 0xf5ccf743, 0x7f97cebd, 0xf59add02, 0x7f93c38c, 0xf568c45b, 0x7f8fa4b0,\n 0xf536ad56, 0x7f8b7227,\n 0xf50497fb, 0x7f872bf3, 0xf4d28451, 0x7f82d214, 0xf4a07261, 0x7f7e648c,\n 0xf46e6231, 0x7f79e35a,\n 0xf43c53cb, 0x7f754e80, 0xf40a4735, 0x7f70a5fe, 0xf3d83c77, 0x7f6be9d4,\n 0xf3a63398, 0x7f671a05,\n 0xf3742ca2, 0x7f62368f, 0xf342279b, 0x7f5d3f75, 0xf310248a, 0x7f5834b7,\n 0xf2de2379, 0x7f531655,\n 0xf2ac246e, 0x7f4de451, 0xf27a2771, 0x7f489eaa, 0xf2482c8a, 0x7f434563,\n 0xf21633c0, 0x7f3dd87c,\n 0xf1e43d1c, 0x7f3857f6, 0xf1b248a5, 0x7f32c3d1, 0xf1805662, 0x7f2d1c0e,\n 0xf14e665c, 0x7f2760af,\n 0xf11c789a, 0x7f2191b4, 0xf0ea8d24, 0x7f1baf1e, 0xf0b8a401, 0x7f15b8ee,\n 0xf086bd39, 0x7f0faf25,\n 0xf054d8d5, 0x7f0991c4, 0xf022f6da, 0x7f0360cb, 0xeff11753, 0x7efd1c3c,\n 0xefbf3a45, 0x7ef6c418,\n 0xef8d5fb8, 0x7ef05860, 0xef5b87b5, 0x7ee9d914, 0xef29b243, 0x7ee34636,\n 0xeef7df6a, 0x7edc9fc6,\n 0xeec60f31, 0x7ed5e5c6, 0xee9441a0, 0x7ecf1837, 0xee6276bf, 0x7ec8371a,\n 0xee30ae96, 0x7ec14270,\n 0xedfee92b, 0x7eba3a39, 0xedcd2687, 0x7eb31e78, 0xed9b66b2, 0x7eabef2c,\n 0xed69a9b3, 0x7ea4ac58,\n 0xed37ef91, 0x7e9d55fc, 0xed063856, 0x7e95ec1a, 0xecd48407, 0x7e8e6eb2,\n 0xeca2d2ad, 0x7e86ddc6,\n 0xec71244f, 0x7e7f3957, 0xec3f78f6, 0x7e778166, 0xec0dd0a8, 0x7e6fb5f4,\n 0xebdc2b6e, 0x7e67d703,\n 0xebaa894f, 0x7e5fe493, 0xeb78ea52, 0x7e57dea7, 0xeb474e81, 0x7e4fc53e,\n 0xeb15b5e1, 0x7e47985b,\n 0xeae4207a, 0x7e3f57ff, 0xeab28e56, 0x7e37042a, 0xea80ff7a, 0x7e2e9cdf,\n 0xea4f73ee, 0x7e26221f,\n 0xea1debbb, 0x7e1d93ea, 0xe9ec66e8, 0x7e14f242, 0xe9bae57d, 0x7e0c3d29,\n 0xe9896781, 0x7e0374a0,\n 0xe957ecfb, 0x7dfa98a8, 0xe92675f4, 0x7df1a942, 0xe8f50273, 0x7de8a670,\n 0xe8c39280, 0x7ddf9034,\n 0xe8922622, 0x7dd6668f, 0xe860bd61, 0x7dcd2981, 0xe82f5844, 0x7dc3d90d,\n 0xe7fdf6d4, 0x7dba7534,\n 0xe7cc9917, 0x7db0fdf8, 0xe79b3f16, 0x7da77359, 0xe769e8d8, 0x7d9dd55a,\n 0xe7389665, 0x7d9423fc,\n 0xe70747c4, 0x7d8a5f40, 0xe6d5fcfc, 0x7d808728, 0xe6a4b616, 0x7d769bb5,\n 0xe6737319, 0x7d6c9ce9,\n 0xe642340d, 0x7d628ac6, 0xe610f8f9, 0x7d58654d, 0xe5dfc1e5, 0x7d4e2c7f,\n 0xe5ae8ed8, 0x7d43e05e,\n 0xe57d5fda, 0x7d3980ec, 0xe54c34f3, 0x7d2f0e2b, 0xe51b0e2a, 0x7d24881b,\n 0xe4e9eb87, 0x7d19eebf,\n 0xe4b8cd11, 0x7d0f4218, 0xe487b2d0, 0x7d048228, 0xe4569ccb, 0x7cf9aef0,\n 0xe4258b0a, 0x7ceec873,\n 0xe3f47d96, 0x7ce3ceb2, 0xe3c37474, 0x7cd8c1ae, 0xe3926fad, 0x7ccda169,\n 0xe3616f48, 0x7cc26de5,\n 0xe330734d, 0x7cb72724, 0xe2ff7bc3, 0x7cabcd28, 0xe2ce88b3, 0x7ca05ff1,\n 0xe29d9a23, 0x7c94df83,\n 0xe26cb01b, 0x7c894bde, 0xe23bcaa2, 0x7c7da505, 0xe20ae9c1, 0x7c71eaf9,\n 0xe1da0d7e, 0x7c661dbc,\n 0xe1a935e2, 0x7c5a3d50, 0xe17862f3, 0x7c4e49b7, 0xe14794ba, 0x7c4242f2,\n 0xe116cb3d, 0x7c362904,\n 0xe0e60685, 0x7c29fbee, 0xe0b54698, 0x7c1dbbb3, 0xe0848b7f, 0x7c116853,\n 0xe053d541, 0x7c0501d2,\n 0xe02323e5, 0x7bf88830, 0xdff27773, 0x7bebfb70, 0xdfc1cff3, 0x7bdf5b94,\n 0xdf912d6b, 0x7bd2a89e,\n 0xdf608fe4, 0x7bc5e290, 0xdf2ff764, 0x7bb9096b, 0xdeff63f4, 0x7bac1d31,\n 0xdeced59b, 0x7b9f1de6,\n 0xde9e4c60, 0x7b920b89, 0xde6dc84b, 0x7b84e61f, 0xde3d4964, 0x7b77ada8,\n 0xde0ccfb1, 0x7b6a6227,\n 0xdddc5b3b, 0x7b5d039e, 0xddabec08, 0x7b4f920e, 0xdd7b8220, 0x7b420d7a,\n 0xdd4b1d8c, 0x7b3475e5,\n 0xdd1abe51, 0x7b26cb4f, 0xdcea6478, 0x7b190dbc, 0xdcba1008, 0x7b0b3d2c,\n 0xdc89c109, 0x7afd59a4,\n 0xdc597781, 0x7aef6323, 0xdc293379, 0x7ae159ae, 0xdbf8f4f8, 0x7ad33d45,\n 0xdbc8bc06, 0x7ac50dec,\n 0xdb9888a8, 0x7ab6cba4, 0xdb685ae9, 0x7aa8766f, 0xdb3832cd, 0x7a9a0e50,\n 0xdb08105e, 0x7a8b9348,\n 0xdad7f3a2, 0x7a7d055b, 0xdaa7dca1, 0x7a6e648a, 0xda77cb63, 0x7a5fb0d8,\n 0xda47bfee, 0x7a50ea47,\n 0xda17ba4a, 0x7a4210d8, 0xd9e7ba7f, 0x7a332490, 0xd9b7c094, 0x7a24256f,\n 0xd987cc90, 0x7a151378,\n 0xd957de7a, 0x7a05eead, 0xd927f65b, 0x79f6b711, 0xd8f81439, 0x79e76ca7,\n 0xd8c8381d, 0x79d80f6f,\n 0xd898620c, 0x79c89f6e, 0xd868920f, 0x79b91ca4, 0xd838c82d, 0x79a98715,\n 0xd809046e, 0x7999dec4,\n 0xd7d946d8, 0x798a23b1, 0xd7a98f73, 0x797a55e0, 0xd779de47, 0x796a7554,\n 0xd74a335b, 0x795a820e,\n 0xd71a8eb5, 0x794a7c12, 0xd6eaf05f, 0x793a6361, 0xd6bb585e, 0x792a37fe,\n 0xd68bc6ba, 0x7919f9ec,\n 0xd65c3b7b, 0x7909a92d, 0xd62cb6a8, 0x78f945c3, 0xd5fd3848, 0x78e8cfb2,\n 0xd5cdc062, 0x78d846fb,\n 0xd59e4eff, 0x78c7aba2, 0xd56ee424, 0x78b6fda8, 0xd53f7fda, 0x78a63d11,\n 0xd5102228, 0x789569df,\n 0xd4e0cb15, 0x78848414, 0xd4b17aa8, 0x78738bb3, 0xd48230e9, 0x786280bf,\n 0xd452eddf, 0x7851633b,\n 0xd423b191, 0x78403329, 0xd3f47c06, 0x782ef08b, 0xd3c54d47, 0x781d9b65,\n 0xd396255a, 0x780c33b8,\n 0xd3670446, 0x77fab989, 0xd337ea12, 0x77e92cd9, 0xd308d6c7, 0x77d78daa,\n 0xd2d9ca6a, 0x77c5dc01,\n 0xd2aac504, 0x77b417df, 0xd27bc69c, 0x77a24148, 0xd24ccf39, 0x7790583e,\n 0xd21ddee2, 0x777e5cc3,\n 0xd1eef59e, 0x776c4edb, 0xd1c01375, 0x775a2e89, 0xd191386e, 0x7747fbce,\n 0xd1626490, 0x7735b6af,\n 0xd13397e2, 0x77235f2d, 0xd104d26b, 0x7710f54c, 0xd0d61434, 0x76fe790e,\n 0xd0a75d42, 0x76ebea77,\n 0xd078ad9e, 0x76d94989, 0xd04a054e, 0x76c69647, 0xd01b6459, 0x76b3d0b4,\n 0xcfeccac7, 0x76a0f8d2,\n 0xcfbe389f, 0x768e0ea6, 0xcf8fade9, 0x767b1231, 0xcf612aaa, 0x76680376,\n 0xcf32aeeb, 0x7654e279,\n 0xcf043ab3, 0x7641af3d, 0xced5ce08, 0x762e69c4, 0xcea768f2, 0x761b1211,\n 0xce790b79, 0x7607a828,\n 0xce4ab5a2, 0x75f42c0b, 0xce1c6777, 0x75e09dbd, 0xcdee20fc, 0x75ccfd42,\n 0xcdbfe23a, 0x75b94a9c,\n 0xcd91ab39, 0x75a585cf, 0xcd637bfe, 0x7591aedd, 0xcd355491, 0x757dc5ca,\n 0xcd0734f9, 0x7569ca99,\n 0xccd91d3d, 0x7555bd4c, 0xccab0d65, 0x75419de7, 0xcc7d0578, 0x752d6c6c,\n 0xcc4f057c, 0x751928e0,\n 0xcc210d79, 0x7504d345, 0xcbf31d75, 0x74f06b9e, 0xcbc53579, 0x74dbf1ef,\n 0xcb97558a, 0x74c7663a,\n 0xcb697db0, 0x74b2c884, 0xcb3badf3, 0x749e18cd, 0xcb0de658, 0x7489571c,\n 0xcae026e8, 0x74748371,\n 0xcab26fa9, 0x745f9dd1, 0xca84c0a3, 0x744aa63f, 0xca5719db, 0x74359cbd,\n 0xca297b5a, 0x74208150,\n 0xc9fbe527, 0x740b53fb, 0xc9ce5748, 0x73f614c0, 0xc9a0d1c5, 0x73e0c3a3,\n 0xc97354a4, 0x73cb60a8,\n 0xc945dfec, 0x73b5ebd1, 0xc91873a5, 0x73a06522, 0xc8eb0fd6, 0x738acc9e,\n 0xc8bdb485, 0x73752249,\n 0xc89061ba, 0x735f6626, 0xc863177b, 0x73499838, 0xc835d5d0, 0x7333b883,\n 0xc8089cbf, 0x731dc70a,\n 0xc7db6c50, 0x7307c3d0, 0xc7ae4489, 0x72f1aed9, 0xc7812572, 0x72db8828,\n 0xc7540f11, 0x72c54fc1,\n 0xc727016d, 0x72af05a7, 0xc6f9fc8d, 0x7298a9dd, 0xc6cd0079, 0x72823c67,\n 0xc6a00d37, 0x726bbd48,\n 0xc67322ce, 0x72552c85, 0xc6464144, 0x723e8a20, 0xc61968a2, 0x7227d61c,\n 0xc5ec98ee, 0x7211107e,\n 0xc5bfd22e, 0x71fa3949, 0xc593146a, 0x71e35080, 0xc5665fa9, 0x71cc5626,\n 0xc539b3f1, 0x71b54a41,\n 0xc50d1149, 0x719e2cd2, 0xc4e077b8, 0x7186fdde, 0xc4b3e746, 0x716fbd68,\n 0xc4875ff9, 0x71586b74,\n 0xc45ae1d7, 0x71410805, 0xc42e6ce8, 0x7129931f, 0xc4020133, 0x71120cc5,\n 0xc3d59ebe, 0x70fa74fc,\n 0xc3a94590, 0x70e2cbc6, 0xc37cf5b0, 0x70cb1128, 0xc350af26, 0x70b34525,\n 0xc32471f7, 0x709b67c0,\n 0xc2f83e2a, 0x708378ff, 0xc2cc13c7, 0x706b78e3, 0xc29ff2d4, 0x70536771,\n 0xc273db58, 0x703b44ad,\n 0xc247cd5a, 0x7023109a, 0xc21bc8e1, 0x700acb3c, 0xc1efcdf3, 0x6ff27497,\n 0xc1c3dc97, 0x6fda0cae,\n 0xc197f4d4, 0x6fc19385, 0xc16c16b0, 0x6fa90921, 0xc1404233, 0x6f906d84,\n 0xc1147764, 0x6f77c0b3,\n 0xc0e8b648, 0x6f5f02b2, 0xc0bcfee7, 0x6f463383, 0xc0915148, 0x6f2d532c,\n 0xc065ad70, 0x6f1461b0,\n 0xc03a1368, 0x6efb5f12, 0xc00e8336, 0x6ee24b57, 0xbfe2fcdf, 0x6ec92683,\n 0xbfb7806c, 0x6eaff099,\n 0xbf8c0de3, 0x6e96a99d, 0xbf60a54a, 0x6e7d5193, 0xbf3546a8, 0x6e63e87f,\n 0xbf09f205, 0x6e4a6e66,\n 0xbedea765, 0x6e30e34a, 0xbeb366d1, 0x6e174730, 0xbe88304f, 0x6dfd9a1c,\n 0xbe5d03e6, 0x6de3dc11,\n 0xbe31e19b, 0x6dca0d14, 0xbe06c977, 0x6db02d29, 0xbddbbb7f, 0x6d963c54,\n 0xbdb0b7bb, 0x6d7c3a98,\n 0xbd85be30, 0x6d6227fa, 0xbd5acee5, 0x6d48047e, 0xbd2fe9e2, 0x6d2dd027,\n 0xbd050f2c, 0x6d138afb,\n 0xbcda3ecb, 0x6cf934fc, 0xbcaf78c4, 0x6cdece2f, 0xbc84bd1f, 0x6cc45698,\n 0xbc5a0be2, 0x6ca9ce3b,\n 0xbc2f6513, 0x6c8f351c, 0xbc04c8ba, 0x6c748b3f, 0xbbda36dd, 0x6c59d0a9,\n 0xbbafaf82, 0x6c3f055d,\n 0xbb8532b0, 0x6c242960, 0xbb5ac06d, 0x6c093cb6, 0xbb3058c0, 0x6bee3f62,\n 0xbb05fbb0, 0x6bd3316a,\n 0xbadba943, 0x6bb812d1, 0xbab16180, 0x6b9ce39b, 0xba87246d, 0x6b81a3cd,\n 0xba5cf210, 0x6b66536b,\n 0xba32ca71, 0x6b4af279, 0xba08ad95, 0x6b2f80fb, 0xb9de9b83, 0x6b13fef5,\n 0xb9b49442, 0x6af86c6c,\n 0xb98a97d8, 0x6adcc964, 0xb960a64c, 0x6ac115e2, 0xb936bfa4, 0x6aa551e9,\n 0xb90ce3e6, 0x6a897d7d,\n 0xb8e31319, 0x6a6d98a4, 0xb8b94d44, 0x6a51a361, 0xb88f926d, 0x6a359db9,\n 0xb865e299, 0x6a1987b0,\n 0xb83c3dd1, 0x69fd614a, 0xb812a41a, 0x69e12a8c, 0xb7e9157a, 0x69c4e37a,\n 0xb7bf91f8, 0x69a88c19,\n 0xb796199b, 0x698c246c, 0xb76cac69, 0x696fac78, 0xb7434a67, 0x69532442,\n 0xb719f39e, 0x69368bce,\n 0xb6f0a812, 0x6919e320, 0xb6c767ca, 0x68fd2a3d, 0xb69e32cd, 0x68e06129,\n 0xb6750921, 0x68c387e9,\n 0xb64beacd, 0x68a69e81, 0xb622d7d6, 0x6889a4f6, 0xb5f9d043, 0x686c9b4b,\n 0xb5d0d41a, 0x684f8186,\n 0xb5a7e362, 0x683257ab, 0xb57efe22, 0x68151dbe, 0xb556245e, 0x67f7d3c5,\n 0xb52d561e, 0x67da79c3,\n 0xb5049368, 0x67bd0fbd, 0xb4dbdc42, 0x679f95b7, 0xb4b330b3, 0x67820bb7,\n 0xb48a90c0, 0x676471c0,\n 0xb461fc70, 0x6746c7d8, 0xb43973ca, 0x67290e02, 0xb410f6d3, 0x670b4444,\n 0xb3e88592, 0x66ed6aa1,\n 0xb3c0200c, 0x66cf8120, 0xb397c649, 0x66b187c3, 0xb36f784f, 0x66937e91,\n 0xb3473623, 0x6675658c,\n 0xb31effcc, 0x66573cbb, 0xb2f6d550, 0x66390422, 0xb2ceb6b5, 0x661abbc5,\n 0xb2a6a402, 0x65fc63a9,\n 0xb27e9d3c, 0x65ddfbd3, 0xb256a26a, 0x65bf8447, 0xb22eb392, 0x65a0fd0b,\n 0xb206d0ba, 0x65826622,\n 0xb1def9e9, 0x6563bf92, 0xb1b72f23, 0x6545095f, 0xb18f7071, 0x6526438f,\n 0xb167bdd7, 0x65076e25,\n 0xb140175b, 0x64e88926, 0xb1187d05, 0x64c99498, 0xb0f0eeda, 0x64aa907f,\n 0xb0c96ce0, 0x648b7ce0,\n 0xb0a1f71d, 0x646c59bf, 0xb07a8d97, 0x644d2722, 0xb0533055, 0x642de50d,\n 0xb02bdf5c, 0x640e9386,\n 0xb0049ab3, 0x63ef3290, 0xafdd625f, 0x63cfc231, 0xafb63667, 0x63b0426d,\n 0xaf8f16d1, 0x6390b34a,\n 0xaf6803a2, 0x637114cc, 0xaf40fce1, 0x635166f9, 0xaf1a0293, 0x6331a9d4,\n 0xaef314c0, 0x6311dd64,\n 0xaecc336c, 0x62f201ac, 0xaea55e9e, 0x62d216b3, 0xae7e965b, 0x62b21c7b,\n 0xae57daab, 0x6292130c,\n 0xae312b92, 0x6271fa69, 0xae0a8916, 0x6251d298, 0xade3f33e, 0x62319b9d,\n 0xadbd6a10, 0x6211557e,\n 0xad96ed92, 0x61f1003f, 0xad707dc8, 0x61d09be5, 0xad4a1aba, 0x61b02876,\n 0xad23c46e, 0x618fa5f7,\n 0xacfd7ae8, 0x616f146c, 0xacd73e30, 0x614e73da, 0xacb10e4b, 0x612dc447,\n 0xac8aeb3e, 0x610d05b7,\n 0xac64d510, 0x60ec3830, 0xac3ecbc7, 0x60cb5bb7, 0xac18cf69, 0x60aa7050,\n 0xabf2dffb, 0x60897601,\n 0xabccfd83, 0x60686ccf, 0xaba72807, 0x604754bf, 0xab815f8d, 0x60262dd6,\n 0xab5ba41a, 0x6004f819,\n 0xab35f5b5, 0x5fe3b38d, 0xab105464, 0x5fc26038, 0xaaeac02c, 0x5fa0fe1f,\n 0xaac53912, 0x5f7f8d46,\n 0xaa9fbf1e, 0x5f5e0db3, 0xaa7a5253, 0x5f3c7f6b, 0xaa54f2ba, 0x5f1ae274,\n 0xaa2fa056, 0x5ef936d1,\n 0xaa0a5b2e, 0x5ed77c8a, 0xa9e52347, 0x5eb5b3a2, 0xa9bff8a8, 0x5e93dc1f,\n 0xa99adb56, 0x5e71f606,\n 0xa975cb57, 0x5e50015d, 0xa950c8b0, 0x5e2dfe29, 0xa92bd367, 0x5e0bec6e,\n 0xa906eb82, 0x5de9cc33,\n 0xa8e21106, 0x5dc79d7c, 0xa8bd43fa, 0x5da5604f, 0xa8988463, 0x5d8314b1,\n 0xa873d246, 0x5d60baa7,\n 0xa84f2daa, 0x5d3e5237, 0xa82a9693, 0x5d1bdb65, 0xa8060d08, 0x5cf95638,\n 0xa7e1910f, 0x5cd6c2b5,\n 0xa7bd22ac, 0x5cb420e0, 0xa798c1e5, 0x5c9170bf, 0xa7746ec0, 0x5c6eb258,\n 0xa7502943, 0x5c4be5b0,\n 0xa72bf174, 0x5c290acc, 0xa707c757, 0x5c0621b2, 0xa6e3aaf2, 0x5be32a67,\n 0xa6bf9c4b, 0x5bc024f0,\n 0xa69b9b68, 0x5b9d1154, 0xa677a84e, 0x5b79ef96, 0xa653c303, 0x5b56bfbd,\n 0xa62feb8b, 0x5b3381ce,\n 0xa60c21ee, 0x5b1035cf, 0xa5e8662f, 0x5aecdbc5, 0xa5c4b855, 0x5ac973b5,\n 0xa5a11866, 0x5aa5fda5,\n 0xa57d8666, 0x5a82799a, 0xa55a025b, 0x5a5ee79a, 0xa5368c4b, 0x5a3b47ab,\n 0xa513243b, 0x5a1799d1,\n 0xa4efca31, 0x59f3de12, 0xa4cc7e32, 0x59d01475, 0xa4a94043, 0x59ac3cfd,\n 0xa486106a, 0x598857b2,\n 0xa462eeac, 0x59646498, 0xa43fdb10, 0x594063b5, 0xa41cd599, 0x591c550e,\n 0xa3f9de4e, 0x58f838a9,\n 0xa3d6f534, 0x58d40e8c, 0xa3b41a50, 0x58afd6bd, 0xa3914da8, 0x588b9140,\n 0xa36e8f41, 0x58673e1b,\n 0xa34bdf20, 0x5842dd54, 0xa3293d4b, 0x581e6ef1, 0xa306a9c8, 0x57f9f2f8,\n 0xa2e4249b, 0x57d5696d,\n 0xa2c1adc9, 0x57b0d256, 0xa29f4559, 0x578c2dba, 0xa27ceb4f, 0x57677b9d,\n 0xa25a9fb1, 0x5742bc06,\n 0xa2386284, 0x571deefa, 0xa21633cd, 0x56f9147e, 0xa1f41392, 0x56d42c99,\n 0xa1d201d7, 0x56af3750,\n 0xa1affea3, 0x568a34a9, 0xa18e09fa, 0x566524aa, 0xa16c23e1, 0x56400758,\n 0xa14a4c5e, 0x561adcb9,\n 0xa1288376, 0x55f5a4d2, 0xa106c92f, 0x55d05faa, 0xa0e51d8c, 0x55ab0d46,\n 0xa0c38095, 0x5585adad,\n 0xa0a1f24d, 0x556040e2, 0xa08072ba, 0x553ac6ee, 0xa05f01e1, 0x55153fd4,\n 0xa03d9fc8, 0x54efab9c,\n 0xa01c4c73, 0x54ca0a4b, 0x9ffb07e7, 0x54a45be6, 0x9fd9d22a, 0x547ea073,\n 0x9fb8ab41, 0x5458d7f9,\n 0x9f979331, 0x5433027d, 0x9f7689ff, 0x540d2005, 0x9f558fb0, 0x53e73097,\n 0x9f34a449, 0x53c13439,\n 0x9f13c7d0, 0x539b2af0, 0x9ef2fa49, 0x537514c2, 0x9ed23bb9, 0x534ef1b5,\n 0x9eb18c26, 0x5328c1d0,\n 0x9e90eb94, 0x53028518, 0x9e705a09, 0x52dc3b92, 0x9e4fd78a, 0x52b5e546,\n 0x9e2f641b, 0x528f8238,\n 0x9e0effc1, 0x5269126e, 0x9deeaa82, 0x524295f0, 0x9dce6463, 0x521c0cc2,\n 0x9dae2d68, 0x51f576ea,\n 0x9d8e0597, 0x51ced46e, 0x9d6decf4, 0x51a82555, 0x9d4de385, 0x518169a5,\n 0x9d2de94d, 0x515aa162,\n 0x9d0dfe54, 0x5133cc94, 0x9cee229c, 0x510ceb40, 0x9cce562c, 0x50e5fd6d,\n 0x9cae9907, 0x50bf031f,\n 0x9c8eeb34, 0x5097fc5e, 0x9c6f4cb6, 0x5070e92f, 0x9c4fbd93, 0x5049c999,\n 0x9c303dcf, 0x50229da1,\n 0x9c10cd70, 0x4ffb654d, 0x9bf16c7a, 0x4fd420a4, 0x9bd21af3, 0x4faccfab,\n 0x9bb2d8de, 0x4f857269,\n 0x9b93a641, 0x4f5e08e3, 0x9b748320, 0x4f369320, 0x9b556f81, 0x4f0f1126,\n 0x9b366b68, 0x4ee782fb,\n 0x9b1776da, 0x4ebfe8a5, 0x9af891db, 0x4e984229, 0x9ad9bc71, 0x4e708f8f,\n 0x9abaf6a1, 0x4e48d0dd,\n 0x9a9c406e, 0x4e210617, 0x9a7d99de, 0x4df92f46, 0x9a5f02f5, 0x4dd14c6e,\n 0x9a407bb9, 0x4da95d96,\n 0x9a22042d, 0x4d8162c4, 0x9a039c57, 0x4d595bfe, 0x99e5443b, 0x4d31494b,\n 0x99c6fbde, 0x4d092ab0,\n 0x99a8c345, 0x4ce10034, 0x998a9a74, 0x4cb8c9dd, 0x996c816f, 0x4c9087b1,\n 0x994e783d, 0x4c6839b7,\n 0x99307ee0, 0x4c3fdff4, 0x9912955f, 0x4c177a6e, 0x98f4bbbc, 0x4bef092d,\n 0x98d6f1fe, 0x4bc68c36,\n 0x98b93828, 0x4b9e0390, 0x989b8e40, 0x4b756f40, 0x987df449, 0x4b4ccf4d,\n 0x98606a49, 0x4b2423be,\n 0x9842f043, 0x4afb6c98, 0x9825863d, 0x4ad2a9e2, 0x98082c3b, 0x4aa9dba2,\n 0x97eae242, 0x4a8101de,\n 0x97cda855, 0x4a581c9e, 0x97b07e7a, 0x4a2f2be6, 0x979364b5, 0x4a062fbd,\n 0x97765b0a, 0x49dd282a,\n 0x9759617f, 0x49b41533, 0x973c7817, 0x498af6df, 0x971f9ed7, 0x4961cd33,\n 0x9702d5c3, 0x49389836,\n 0x96e61ce0, 0x490f57ee, 0x96c97432, 0x48e60c62, 0x96acdbbe, 0x48bcb599,\n 0x96905388, 0x48935397,\n 0x9673db94, 0x4869e665, 0x965773e7, 0x48406e08, 0x963b1c86, 0x4816ea86,\n 0x961ed574, 0x47ed5be6,\n 0x96029eb6, 0x47c3c22f, 0x95e67850, 0x479a1d67, 0x95ca6247, 0x47706d93,\n 0x95ae5c9f, 0x4746b2bc,\n 0x9592675c, 0x471cece7, 0x95768283, 0x46f31c1a, 0x955aae17, 0x46c9405c,\n 0x953eea1e, 0x469f59b4,\n 0x9523369c, 0x46756828, 0x95079394, 0x464b6bbe, 0x94ec010b, 0x4621647d,\n 0x94d07f05, 0x45f7526b,\n 0x94b50d87, 0x45cd358f, 0x9499ac95, 0x45a30df0, 0x947e5c33, 0x4578db93,\n 0x94631c65, 0x454e9e80,\n 0x9447ed2f, 0x452456bd, 0x942cce96, 0x44fa0450, 0x9411c09e, 0x44cfa740,\n 0x93f6c34a, 0x44a53f93,\n 0x93dbd6a0, 0x447acd50, 0x93c0faa3, 0x4450507e, 0x93a62f57, 0x4425c923,\n 0x938b74c1, 0x43fb3746,\n 0x9370cae4, 0x43d09aed, 0x935631c5, 0x43a5f41e, 0x933ba968, 0x437b42e1,\n 0x932131d1, 0x4350873c,\n 0x9306cb04, 0x4325c135, 0x92ec7505, 0x42faf0d4, 0x92d22fd9, 0x42d0161e,\n 0x92b7fb82, 0x42a5311b,\n 0x929dd806, 0x427a41d0, 0x9283c568, 0x424f4845, 0x9269c3ac, 0x42244481,\n 0x924fd2d7, 0x41f93689,\n 0x9235f2ec, 0x41ce1e65, 0x921c23ef, 0x41a2fc1a, 0x920265e4, 0x4177cfb1,\n 0x91e8b8d0, 0x414c992f,\n 0x91cf1cb6, 0x4121589b, 0x91b5919a, 0x40f60dfb, 0x919c1781, 0x40cab958,\n 0x9182ae6d, 0x409f5ab6,\n 0x91695663, 0x4073f21d, 0x91500f67, 0x40487f94, 0x9136d97d, 0x401d0321,\n 0x911db4a9, 0x3ff17cca,\n 0x9104a0ee, 0x3fc5ec98, 0x90eb9e50, 0x3f9a5290, 0x90d2acd4, 0x3f6eaeb8,\n 0x90b9cc7d, 0x3f430119,\n 0x90a0fd4e, 0x3f1749b8, 0x90883f4d, 0x3eeb889c, 0x906f927c, 0x3ebfbdcd,\n 0x9056f6df, 0x3e93e950,\n 0x903e6c7b, 0x3e680b2c, 0x9025f352, 0x3e3c2369, 0x900d8b69, 0x3e10320d,\n 0x8ff534c4, 0x3de4371f,\n 0x8fdcef66, 0x3db832a6, 0x8fc4bb53, 0x3d8c24a8, 0x8fac988f, 0x3d600d2c,\n 0x8f94871d, 0x3d33ec39,\n 0x8f7c8701, 0x3d07c1d6, 0x8f649840, 0x3cdb8e09, 0x8f4cbadb, 0x3caf50da,\n 0x8f34eed8, 0x3c830a50,\n 0x8f1d343a, 0x3c56ba70, 0x8f058b04, 0x3c2a6142, 0x8eedf33b, 0x3bfdfecd,\n 0x8ed66ce1, 0x3bd19318,\n 0x8ebef7fb, 0x3ba51e29, 0x8ea7948c, 0x3b78a007, 0x8e904298, 0x3b4c18ba,\n 0x8e790222, 0x3b1f8848,\n 0x8e61d32e, 0x3af2eeb7, 0x8e4ab5bf, 0x3ac64c0f, 0x8e33a9da, 0x3a99a057,\n 0x8e1caf80, 0x3a6ceb96,\n 0x8e05c6b7, 0x3a402dd2, 0x8deeef82, 0x3a136712, 0x8dd829e4, 0x39e6975e,\n 0x8dc175e0, 0x39b9bebc,\n 0x8daad37b, 0x398cdd32, 0x8d9442b8, 0x395ff2c9, 0x8d7dc399, 0x3932ff87,\n 0x8d675623, 0x39060373,\n 0x8d50fa59, 0x38d8fe93, 0x8d3ab03f, 0x38abf0ef, 0x8d2477d8, 0x387eda8e,\n 0x8d0e5127, 0x3851bb77,\n 0x8cf83c30, 0x382493b0, 0x8ce238f6, 0x37f76341, 0x8ccc477d, 0x37ca2a30,\n 0x8cb667c8, 0x379ce885,\n 0x8ca099da, 0x376f9e46, 0x8c8addb7, 0x37424b7b, 0x8c753362, 0x3714f02a,\n 0x8c5f9ade, 0x36e78c5b,\n 0x8c4a142f, 0x36ba2014, 0x8c349f58, 0x368cab5c, 0x8c1f3c5d, 0x365f2e3b,\n 0x8c09eb40, 0x3631a8b8,\n 0x8bf4ac05, 0x36041ad9, 0x8bdf7eb0, 0x35d684a6, 0x8bca6343, 0x35a8e625,\n 0x8bb559c1, 0x357b3f5d,\n 0x8ba0622f, 0x354d9057, 0x8b8b7c8f, 0x351fd918, 0x8b76a8e4, 0x34f219a8,\n 0x8b61e733, 0x34c4520d,\n 0x8b4d377c, 0x34968250, 0x8b3899c6, 0x3468aa76, 0x8b240e11, 0x343aca87,\n 0x8b0f9462, 0x340ce28b,\n 0x8afb2cbb, 0x33def287, 0x8ae6d720, 0x33b0fa84, 0x8ad29394, 0x3382fa88,\n 0x8abe6219, 0x3354f29b,\n 0x8aaa42b4, 0x3326e2c3, 0x8a963567, 0x32f8cb07, 0x8a823a36, 0x32caab6f,\n 0x8a6e5123, 0x329c8402,\n 0x8a5a7a31, 0x326e54c7, 0x8a46b564, 0x32401dc6, 0x8a3302be, 0x3211df04,\n 0x8a1f6243, 0x31e39889,\n 0x8a0bd3f5, 0x31b54a5e, 0x89f857d8, 0x3186f487, 0x89e4edef, 0x3158970e,\n 0x89d1963c, 0x312a31f8,\n 0x89be50c3, 0x30fbc54d, 0x89ab1d87, 0x30cd5115, 0x8997fc8a, 0x309ed556,\n 0x8984edcf, 0x30705217,\n 0x8971f15a, 0x3041c761, 0x895f072e, 0x30133539, 0x894c2f4c, 0x2fe49ba7,\n 0x893969b9, 0x2fb5fab2,\n 0x8926b677, 0x2f875262, 0x89141589, 0x2f58a2be, 0x890186f2, 0x2f29ebcc,\n 0x88ef0ab4, 0x2efb2d95,\n 0x88dca0d3, 0x2ecc681e, 0x88ca4951, 0x2e9d9b70, 0x88b80432, 0x2e6ec792,\n 0x88a5d177, 0x2e3fec8b,\n 0x8893b125, 0x2e110a62, 0x8881a33d, 0x2de2211e, 0x886fa7c2, 0x2db330c7,\n 0x885dbeb8, 0x2d843964,\n 0x884be821, 0x2d553afc, 0x883a23ff, 0x2d263596, 0x88287256, 0x2cf72939,\n 0x8816d327, 0x2cc815ee,\n 0x88054677, 0x2c98fbba, 0x87f3cc48, 0x2c69daa6, 0x87e2649b, 0x2c3ab2b9,\n 0x87d10f75, 0x2c0b83fa,\n 0x87bfccd7, 0x2bdc4e6f, 0x87ae9cc5, 0x2bad1221, 0x879d7f41, 0x2b7dcf17,\n 0x878c744d, 0x2b4e8558,\n 0x877b7bec, 0x2b1f34eb, 0x876a9621, 0x2aefddd8, 0x8759c2ef, 0x2ac08026,\n 0x87490258, 0x2a911bdc,\n 0x8738545e, 0x2a61b101, 0x8727b905, 0x2a323f9e, 0x8717304e, 0x2a02c7b8,\n 0x8706ba3d, 0x29d34958,\n 0x86f656d3, 0x29a3c485, 0x86e60614, 0x29743946, 0x86d5c802, 0x2944a7a2,\n 0x86c59c9f, 0x29150fa1,\n 0x86b583ee, 0x28e5714b, 0x86a57df2, 0x28b5cca5, 0x86958aac, 0x288621b9,\n 0x8685aa20, 0x2856708d,\n 0x8675dc4f, 0x2826b928, 0x8666213c, 0x27f6fb92, 0x865678eb, 0x27c737d3,\n 0x8646e35c, 0x27976df1,\n 0x86376092, 0x27679df4, 0x8627f091, 0x2737c7e3, 0x86189359, 0x2707ebc7,\n 0x860948ef, 0x26d809a5,\n 0x85fa1153, 0x26a82186, 0x85eaec88, 0x26783370, 0x85dbda91, 0x26483f6c,\n 0x85ccdb70, 0x26184581,\n 0x85bdef28, 0x25e845b6, 0x85af15b9, 0x25b84012, 0x85a04f28, 0x2588349d,\n 0x85919b76, 0x2558235f,\n 0x8582faa5, 0x25280c5e, 0x85746cb8, 0x24f7efa2, 0x8565f1b0, 0x24c7cd33,\n 0x85578991, 0x2497a517,\n 0x8549345c, 0x24677758, 0x853af214, 0x243743fa, 0x852cc2bb, 0x24070b08,\n 0x851ea652, 0x23d6cc87,\n 0x85109cdd, 0x23a6887f, 0x8502a65c, 0x23763ef7, 0x84f4c2d4, 0x2345eff8,\n 0x84e6f244, 0x23159b88,\n 0x84d934b1, 0x22e541af, 0x84cb8a1b, 0x22b4e274, 0x84bdf286, 0x22847de0,\n 0x84b06df2, 0x225413f8,\n 0x84a2fc62, 0x2223a4c5, 0x84959dd9, 0x21f3304f, 0x84885258, 0x21c2b69c,\n 0x847b19e1, 0x219237b5,\n 0x846df477, 0x2161b3a0, 0x8460e21a, 0x21312a65, 0x8453e2cf, 0x21009c0c,\n 0x8446f695, 0x20d0089c,\n 0x843a1d70, 0x209f701c, 0x842d5762, 0x206ed295, 0x8420a46c, 0x203e300d,\n 0x84140490, 0x200d888d,\n 0x840777d0, 0x1fdcdc1b, 0x83fafe2e, 0x1fac2abf, 0x83ee97ad, 0x1f7b7481,\n 0x83e2444d, 0x1f4ab968,\n 0x83d60412, 0x1f19f97b, 0x83c9d6fc, 0x1ee934c3, 0x83bdbd0e, 0x1eb86b46,\n 0x83b1b649, 0x1e879d0d,\n 0x83a5c2b0, 0x1e56ca1e, 0x8399e244, 0x1e25f282, 0x838e1507, 0x1df5163f,\n 0x83825afb, 0x1dc4355e,\n 0x8376b422, 0x1d934fe5, 0x836b207d, 0x1d6265dd, 0x835fa00f, 0x1d31774d,\n 0x835432d8, 0x1d00843d,\n 0x8348d8dc, 0x1ccf8cb3, 0x833d921b, 0x1c9e90b8, 0x83325e97, 0x1c6d9053,\n 0x83273e52, 0x1c3c8b8c,\n 0x831c314e, 0x1c0b826a, 0x8311378d, 0x1bda74f6, 0x83065110, 0x1ba96335,\n 0x82fb7dd8, 0x1b784d30,\n 0x82f0bde8, 0x1b4732ef, 0x82e61141, 0x1b161479, 0x82db77e5, 0x1ae4f1d6,\n 0x82d0f1d5, 0x1ab3cb0d,\n 0x82c67f14, 0x1a82a026, 0x82bc1fa2, 0x1a517128, 0x82b1d381, 0x1a203e1b,\n 0x82a79ab3, 0x19ef0707,\n 0x829d753a, 0x19bdcbf3, 0x82936317, 0x198c8ce7, 0x8289644b, 0x195b49ea,\n 0x827f78d8, 0x192a0304,\n 0x8275a0c0, 0x18f8b83c, 0x826bdc04, 0x18c7699b, 0x82622aa6, 0x18961728,\n 0x82588ca7, 0x1864c0ea,\n 0x824f0208, 0x183366e9, 0x82458acc, 0x1802092c, 0x823c26f3, 0x17d0a7bc,\n 0x8232d67f, 0x179f429f,\n 0x82299971, 0x176dd9de, 0x82206fcc, 0x173c6d80, 0x82175990, 0x170afd8d,\n 0x820e56be, 0x16d98a0c,\n 0x82056758, 0x16a81305, 0x81fc8b60, 0x1676987f, 0x81f3c2d7, 0x16451a83,\n 0x81eb0dbe, 0x16139918,\n 0x81e26c16, 0x15e21445, 0x81d9dde1, 0x15b08c12, 0x81d16321, 0x157f0086,\n 0x81c8fbd6, 0x154d71aa,\n 0x81c0a801, 0x151bdf86, 0x81b867a5, 0x14ea4a1f, 0x81b03ac2, 0x14b8b17f,\n 0x81a82159, 0x148715ae,\n 0x81a01b6d, 0x145576b1, 0x819828fd, 0x1423d492, 0x81904a0c, 0x13f22f58,\n 0x81887e9a, 0x13c0870a,\n 0x8180c6a9, 0x138edbb1, 0x8179223a, 0x135d2d53, 0x8171914e, 0x132b7bf9,\n 0x816a13e6, 0x12f9c7aa,\n 0x8162aa04, 0x12c8106f, 0x815b53a8, 0x1296564d, 0x815410d4, 0x1264994e,\n 0x814ce188, 0x1232d979,\n 0x8145c5c7, 0x120116d5, 0x813ebd90, 0x11cf516a, 0x8137c8e6, 0x119d8941,\n 0x8130e7c9, 0x116bbe60,\n 0x812a1a3a, 0x1139f0cf, 0x8123603a, 0x11082096, 0x811cb9ca, 0x10d64dbd,\n 0x811626ec, 0x10a4784b,\n 0x810fa7a0, 0x1072a048, 0x81093be8, 0x1040c5bb, 0x8102e3c4, 0x100ee8ad,\n 0x80fc9f35, 0xfdd0926,\n 0x80f66e3c, 0xfab272b, 0x80f050db, 0xf7942c7, 0x80ea4712, 0xf475bff,\n 0x80e450e2, 0xf1572dc,\n 0x80de6e4c, 0xee38766, 0x80d89f51, 0xeb199a4, 0x80d2e3f2, 0xe7fa99e,\n 0x80cd3c2f, 0xe4db75b,\n 0x80c7a80a, 0xe1bc2e4, 0x80c22784, 0xde9cc40, 0x80bcba9d, 0xdb7d376,\n 0x80b76156, 0xd85d88f,\n 0x80b21baf, 0xd53db92, 0x80ace9ab, 0xd21dc87, 0x80a7cb49, 0xcefdb76,\n 0x80a2c08b, 0xcbdd865,\n 0x809dc971, 0xc8bd35e, 0x8098e5fb, 0xc59cc68, 0x8094162c, 0xc27c389,\n 0x808f5a02, 0xbf5b8cb,\n 0x808ab180, 0xbc3ac35, 0x80861ca6, 0xb919dcf, 0x80819b74, 0xb5f8d9f,\n 0x807d2dec, 0xb2d7baf,\n 0x8078d40d, 0xafb6805, 0x80748dd9, 0xac952aa, 0x80705b50, 0xa973ba5,\n 0x806c3c74, 0xa6522fe,\n 0x80683143, 0xa3308bd, 0x806439c0, 0xa00ece8, 0x806055eb, 0x9cecf89,\n 0x805c85c4, 0x99cb0a7,\n 0x8058c94c, 0x96a9049, 0x80552084, 0x9386e78, 0x80518b6b, 0x9064b3a,\n 0x804e0a04, 0x8d42699,\n 0x804a9c4d, 0x8a2009a, 0x80474248, 0x86fd947, 0x8043fbf6, 0x83db0a7,\n 0x8040c956, 0x80b86c2,\n 0x803daa6a, 0x7d95b9e, 0x803a9f31, 0x7a72f45, 0x8037a7ac, 0x77501be,\n 0x8034c3dd, 0x742d311,\n 0x8031f3c2, 0x710a345, 0x802f375d, 0x6de7262, 0x802c8ead, 0x6ac406f,\n 0x8029f9b4, 0x67a0d76,\n 0x80277872, 0x647d97c, 0x80250ae7, 0x615a48b, 0x8022b114, 0x5e36ea9,\n 0x80206af8, 0x5b137df,\n 0x801e3895, 0x57f0035, 0x801c19ea, 0x54cc7b1, 0x801a0ef8, 0x51a8e5c,\n 0x801817bf, 0x4e8543e,\n 0x80163440, 0x4b6195d, 0x8014647b, 0x483ddc3, 0x8012a86f, 0x451a177,\n 0x8011001f, 0x41f6480,\n 0x800f6b88, 0x3ed26e6, 0x800deaad, 0x3bae8b2, 0x800c7d8c, 0x388a9ea,\n 0x800b2427, 0x3566a96,\n 0x8009de7e, 0x3242abf, 0x8008ac90, 0x2f1ea6c, 0x80078e5e, 0x2bfa9a4,\n 0x800683e8, 0x28d6870,\n 0x80058d2f, 0x25b26d7, 0x8004aa32, 0x228e4e2, 0x8003daf1, 0x1f6a297,\n 0x80031f6d, 0x1c45ffe,\n 0x800277a6, 0x1921d20, 0x8001e39b, 0x15fda03, 0x8001634e, 0x12d96b1,\n 0x8000f6bd, 0xfb5330,\n 0x80009dea, 0xc90f88, 0x800058d4, 0x96cbc1, 0x8000277a, 0x6487e3,\n 0x800009df, 0x3243f5,\n 0x80000000, 0x0, 0x800009df, 0xffcdbc0b, 0x8000277a, 0xff9b781d, 0x800058d4,\n 0xff69343f,\n 0x80009dea, 0xff36f078, 0x8000f6bd, 0xff04acd0, 0x8001634e, 0xfed2694f,\n 0x8001e39b, 0xfea025fd,\n 0x800277a6, 0xfe6de2e0, 0x80031f6d, 0xfe3ba002, 0x8003daf1, 0xfe095d69,\n 0x8004aa32, 0xfdd71b1e,\n 0x80058d2f, 0xfda4d929, 0x800683e8, 0xfd729790, 0x80078e5e, 0xfd40565c,\n 0x8008ac90, 0xfd0e1594,\n 0x8009de7e, 0xfcdbd541, 0x800b2427, 0xfca9956a, 0x800c7d8c, 0xfc775616,\n 0x800deaad, 0xfc45174e,\n 0x800f6b88, 0xfc12d91a, 0x8011001f, 0xfbe09b80, 0x8012a86f, 0xfbae5e89,\n 0x8014647b, 0xfb7c223d,\n 0x80163440, 0xfb49e6a3, 0x801817bf, 0xfb17abc2, 0x801a0ef8, 0xfae571a4,\n 0x801c19ea, 0xfab3384f,\n 0x801e3895, 0xfa80ffcb, 0x80206af8, 0xfa4ec821, 0x8022b114, 0xfa1c9157,\n 0x80250ae7, 0xf9ea5b75,\n 0x80277872, 0xf9b82684, 0x8029f9b4, 0xf985f28a, 0x802c8ead, 0xf953bf91,\n 0x802f375d, 0xf9218d9e,\n 0x8031f3c2, 0xf8ef5cbb, 0x8034c3dd, 0xf8bd2cef, 0x8037a7ac, 0xf88afe42,\n 0x803a9f31, 0xf858d0bb,\n 0x803daa6a, 0xf826a462, 0x8040c956, 0xf7f4793e, 0x8043fbf6, 0xf7c24f59,\n 0x80474248, 0xf79026b9,\n 0x804a9c4d, 0xf75dff66, 0x804e0a04, 0xf72bd967, 0x80518b6b, 0xf6f9b4c6,\n 0x80552084, 0xf6c79188,\n 0x8058c94c, 0xf6956fb7, 0x805c85c4, 0xf6634f59, 0x806055eb, 0xf6313077,\n 0x806439c0, 0xf5ff1318,\n 0x80683143, 0xf5ccf743, 0x806c3c74, 0xf59add02, 0x80705b50, 0xf568c45b,\n 0x80748dd9, 0xf536ad56,\n 0x8078d40d, 0xf50497fb, 0x807d2dec, 0xf4d28451, 0x80819b74, 0xf4a07261,\n 0x80861ca6, 0xf46e6231,\n 0x808ab180, 0xf43c53cb, 0x808f5a02, 0xf40a4735, 0x8094162c, 0xf3d83c77,\n 0x8098e5fb, 0xf3a63398,\n 0x809dc971, 0xf3742ca2, 0x80a2c08b, 0xf342279b, 0x80a7cb49, 0xf310248a,\n 0x80ace9ab, 0xf2de2379,\n 0x80b21baf, 0xf2ac246e, 0x80b76156, 0xf27a2771, 0x80bcba9d, 0xf2482c8a,\n 0x80c22784, 0xf21633c0,\n 0x80c7a80a, 0xf1e43d1c, 0x80cd3c2f, 0xf1b248a5, 0x80d2e3f2, 0xf1805662,\n 0x80d89f51, 0xf14e665c,\n 0x80de6e4c, 0xf11c789a, 0x80e450e2, 0xf0ea8d24, 0x80ea4712, 0xf0b8a401,\n 0x80f050db, 0xf086bd39,\n 0x80f66e3c, 0xf054d8d5, 0x80fc9f35, 0xf022f6da, 0x8102e3c4, 0xeff11753,\n 0x81093be8, 0xefbf3a45,\n 0x810fa7a0, 0xef8d5fb8, 0x811626ec, 0xef5b87b5, 0x811cb9ca, 0xef29b243,\n 0x8123603a, 0xeef7df6a,\n 0x812a1a3a, 0xeec60f31, 0x8130e7c9, 0xee9441a0, 0x8137c8e6, 0xee6276bf,\n 0x813ebd90, 0xee30ae96,\n 0x8145c5c7, 0xedfee92b, 0x814ce188, 0xedcd2687, 0x815410d4, 0xed9b66b2,\n 0x815b53a8, 0xed69a9b3,\n 0x8162aa04, 0xed37ef91, 0x816a13e6, 0xed063856, 0x8171914e, 0xecd48407,\n 0x8179223a, 0xeca2d2ad,\n 0x8180c6a9, 0xec71244f, 0x81887e9a, 0xec3f78f6, 0x81904a0c, 0xec0dd0a8,\n 0x819828fd, 0xebdc2b6e,\n 0x81a01b6d, 0xebaa894f, 0x81a82159, 0xeb78ea52, 0x81b03ac2, 0xeb474e81,\n 0x81b867a5, 0xeb15b5e1,\n 0x81c0a801, 0xeae4207a, 0x81c8fbd6, 0xeab28e56, 0x81d16321, 0xea80ff7a,\n 0x81d9dde1, 0xea4f73ee,\n 0x81e26c16, 0xea1debbb, 0x81eb0dbe, 0xe9ec66e8, 0x81f3c2d7, 0xe9bae57d,\n 0x81fc8b60, 0xe9896781,\n 0x82056758, 0xe957ecfb, 0x820e56be, 0xe92675f4, 0x82175990, 0xe8f50273,\n 0x82206fcc, 0xe8c39280,\n 0x82299971, 0xe8922622, 0x8232d67f, 0xe860bd61, 0x823c26f3, 0xe82f5844,\n 0x82458acc, 0xe7fdf6d4,\n 0x824f0208, 0xe7cc9917, 0x82588ca7, 0xe79b3f16, 0x82622aa6, 0xe769e8d8,\n 0x826bdc04, 0xe7389665,\n 0x8275a0c0, 0xe70747c4, 0x827f78d8, 0xe6d5fcfc, 0x8289644b, 0xe6a4b616,\n 0x82936317, 0xe6737319,\n 0x829d753a, 0xe642340d, 0x82a79ab3, 0xe610f8f9, 0x82b1d381, 0xe5dfc1e5,\n 0x82bc1fa2, 0xe5ae8ed8,\n 0x82c67f14, 0xe57d5fda, 0x82d0f1d5, 0xe54c34f3, 0x82db77e5, 0xe51b0e2a,\n 0x82e61141, 0xe4e9eb87,\n 0x82f0bde8, 0xe4b8cd11, 0x82fb7dd8, 0xe487b2d0, 0x83065110, 0xe4569ccb,\n 0x8311378d, 0xe4258b0a,\n 0x831c314e, 0xe3f47d96, 0x83273e52, 0xe3c37474, 0x83325e97, 0xe3926fad,\n 0x833d921b, 0xe3616f48,\n 0x8348d8dc, 0xe330734d, 0x835432d8, 0xe2ff7bc3, 0x835fa00f, 0xe2ce88b3,\n 0x836b207d, 0xe29d9a23,\n 0x8376b422, 0xe26cb01b, 0x83825afb, 0xe23bcaa2, 0x838e1507, 0xe20ae9c1,\n 0x8399e244, 0xe1da0d7e,\n 0x83a5c2b0, 0xe1a935e2, 0x83b1b649, 0xe17862f3, 0x83bdbd0e, 0xe14794ba,\n 0x83c9d6fc, 0xe116cb3d,\n 0x83d60412, 0xe0e60685, 0x83e2444d, 0xe0b54698, 0x83ee97ad, 0xe0848b7f,\n 0x83fafe2e, 0xe053d541,\n 0x840777d0, 0xe02323e5, 0x84140490, 0xdff27773, 0x8420a46c, 0xdfc1cff3,\n 0x842d5762, 0xdf912d6b,\n 0x843a1d70, 0xdf608fe4, 0x8446f695, 0xdf2ff764, 0x8453e2cf, 0xdeff63f4,\n 0x8460e21a, 0xdeced59b,\n 0x846df477, 0xde9e4c60, 0x847b19e1, 0xde6dc84b, 0x84885258, 0xde3d4964,\n 0x84959dd9, 0xde0ccfb1,\n 0x84a2fc62, 0xdddc5b3b, 0x84b06df2, 0xddabec08, 0x84bdf286, 0xdd7b8220,\n 0x84cb8a1b, 0xdd4b1d8c,\n 0x84d934b1, 0xdd1abe51, 0x84e6f244, 0xdcea6478, 0x84f4c2d4, 0xdcba1008,\n 0x8502a65c, 0xdc89c109,\n 0x85109cdd, 0xdc597781, 0x851ea652, 0xdc293379, 0x852cc2bb, 0xdbf8f4f8,\n 0x853af214, 0xdbc8bc06,\n 0x8549345c, 0xdb9888a8, 0x85578991, 0xdb685ae9, 0x8565f1b0, 0xdb3832cd,\n 0x85746cb8, 0xdb08105e,\n 0x8582faa5, 0xdad7f3a2, 0x85919b76, 0xdaa7dca1, 0x85a04f28, 0xda77cb63,\n 0x85af15b9, 0xda47bfee,\n 0x85bdef28, 0xda17ba4a, 0x85ccdb70, 0xd9e7ba7f, 0x85dbda91, 0xd9b7c094,\n 0x85eaec88, 0xd987cc90,\n 0x85fa1153, 0xd957de7a, 0x860948ef, 0xd927f65b, 0x86189359, 0xd8f81439,\n 0x8627f091, 0xd8c8381d,\n 0x86376092, 0xd898620c, 0x8646e35c, 0xd868920f, 0x865678eb, 0xd838c82d,\n 0x8666213c, 0xd809046e,\n 0x8675dc4f, 0xd7d946d8, 0x8685aa20, 0xd7a98f73, 0x86958aac, 0xd779de47,\n 0x86a57df2, 0xd74a335b,\n 0x86b583ee, 0xd71a8eb5, 0x86c59c9f, 0xd6eaf05f, 0x86d5c802, 0xd6bb585e,\n 0x86e60614, 0xd68bc6ba,\n 0x86f656d3, 0xd65c3b7b, 0x8706ba3d, 0xd62cb6a8, 0x8717304e, 0xd5fd3848,\n 0x8727b905, 0xd5cdc062,\n 0x8738545e, 0xd59e4eff, 0x87490258, 0xd56ee424, 0x8759c2ef, 0xd53f7fda,\n 0x876a9621, 0xd5102228,\n 0x877b7bec, 0xd4e0cb15, 0x878c744d, 0xd4b17aa8, 0x879d7f41, 0xd48230e9,\n 0x87ae9cc5, 0xd452eddf,\n 0x87bfccd7, 0xd423b191, 0x87d10f75, 0xd3f47c06, 0x87e2649b, 0xd3c54d47,\n 0x87f3cc48, 0xd396255a,\n 0x88054677, 0xd3670446, 0x8816d327, 0xd337ea12, 0x88287256, 0xd308d6c7,\n 0x883a23ff, 0xd2d9ca6a,\n 0x884be821, 0xd2aac504, 0x885dbeb8, 0xd27bc69c, 0x886fa7c2, 0xd24ccf39,\n 0x8881a33d, 0xd21ddee2,\n 0x8893b125, 0xd1eef59e, 0x88a5d177, 0xd1c01375, 0x88b80432, 0xd191386e,\n 0x88ca4951, 0xd1626490,\n 0x88dca0d3, 0xd13397e2, 0x88ef0ab4, 0xd104d26b, 0x890186f2, 0xd0d61434,\n 0x89141589, 0xd0a75d42,\n 0x8926b677, 0xd078ad9e, 0x893969b9, 0xd04a054e, 0x894c2f4c, 0xd01b6459,\n 0x895f072e, 0xcfeccac7,\n 0x8971f15a, 0xcfbe389f, 0x8984edcf, 0xcf8fade9, 0x8997fc8a, 0xcf612aaa,\n 0x89ab1d87, 0xcf32aeeb,\n 0x89be50c3, 0xcf043ab3, 0x89d1963c, 0xced5ce08, 0x89e4edef, 0xcea768f2,\n 0x89f857d8, 0xce790b79,\n 0x8a0bd3f5, 0xce4ab5a2, 0x8a1f6243, 0xce1c6777, 0x8a3302be, 0xcdee20fc,\n 0x8a46b564, 0xcdbfe23a,\n 0x8a5a7a31, 0xcd91ab39, 0x8a6e5123, 0xcd637bfe, 0x8a823a36, 0xcd355491,\n 0x8a963567, 0xcd0734f9,\n 0x8aaa42b4, 0xccd91d3d, 0x8abe6219, 0xccab0d65, 0x8ad29394, 0xcc7d0578,\n 0x8ae6d720, 0xcc4f057c,\n 0x8afb2cbb, 0xcc210d79, 0x8b0f9462, 0xcbf31d75, 0x8b240e11, 0xcbc53579,\n 0x8b3899c6, 0xcb97558a,\n 0x8b4d377c, 0xcb697db0, 0x8b61e733, 0xcb3badf3, 0x8b76a8e4, 0xcb0de658,\n 0x8b8b7c8f, 0xcae026e8,\n 0x8ba0622f, 0xcab26fa9, 0x8bb559c1, 0xca84c0a3, 0x8bca6343, 0xca5719db,\n 0x8bdf7eb0, 0xca297b5a,\n 0x8bf4ac05, 0xc9fbe527, 0x8c09eb40, 0xc9ce5748, 0x8c1f3c5d, 0xc9a0d1c5,\n 0x8c349f58, 0xc97354a4,\n 0x8c4a142f, 0xc945dfec, 0x8c5f9ade, 0xc91873a5, 0x8c753362, 0xc8eb0fd6,\n 0x8c8addb7, 0xc8bdb485,\n 0x8ca099da, 0xc89061ba, 0x8cb667c8, 0xc863177b, 0x8ccc477d, 0xc835d5d0,\n 0x8ce238f6, 0xc8089cbf,\n 0x8cf83c30, 0xc7db6c50, 0x8d0e5127, 0xc7ae4489, 0x8d2477d8, 0xc7812572,\n 0x8d3ab03f, 0xc7540f11,\n 0x8d50fa59, 0xc727016d, 0x8d675623, 0xc6f9fc8d, 0x8d7dc399, 0xc6cd0079,\n 0x8d9442b8, 0xc6a00d37,\n 0x8daad37b, 0xc67322ce, 0x8dc175e0, 0xc6464144, 0x8dd829e4, 0xc61968a2,\n 0x8deeef82, 0xc5ec98ee,\n 0x8e05c6b7, 0xc5bfd22e, 0x8e1caf80, 0xc593146a, 0x8e33a9da, 0xc5665fa9,\n 0x8e4ab5bf, 0xc539b3f1,\n 0x8e61d32e, 0xc50d1149, 0x8e790222, 0xc4e077b8, 0x8e904298, 0xc4b3e746,\n 0x8ea7948c, 0xc4875ff9,\n 0x8ebef7fb, 0xc45ae1d7, 0x8ed66ce1, 0xc42e6ce8, 0x8eedf33b, 0xc4020133,\n 0x8f058b04, 0xc3d59ebe,\n 0x8f1d343a, 0xc3a94590, 0x8f34eed8, 0xc37cf5b0, 0x8f4cbadb, 0xc350af26,\n 0x8f649840, 0xc32471f7,\n 0x8f7c8701, 0xc2f83e2a, 0x8f94871d, 0xc2cc13c7, 0x8fac988f, 0xc29ff2d4,\n 0x8fc4bb53, 0xc273db58,\n 0x8fdcef66, 0xc247cd5a, 0x8ff534c4, 0xc21bc8e1, 0x900d8b69, 0xc1efcdf3,\n 0x9025f352, 0xc1c3dc97,\n 0x903e6c7b, 0xc197f4d4, 0x9056f6df, 0xc16c16b0, 0x906f927c, 0xc1404233,\n 0x90883f4d, 0xc1147764,\n 0x90a0fd4e, 0xc0e8b648, 0x90b9cc7d, 0xc0bcfee7, 0x90d2acd4, 0xc0915148,\n 0x90eb9e50, 0xc065ad70,\n 0x9104a0ee, 0xc03a1368, 0x911db4a9, 0xc00e8336, 0x9136d97d, 0xbfe2fcdf,\n 0x91500f67, 0xbfb7806c,\n 0x91695663, 0xbf8c0de3, 0x9182ae6d, 0xbf60a54a, 0x919c1781, 0xbf3546a8,\n 0x91b5919a, 0xbf09f205,\n 0x91cf1cb6, 0xbedea765, 0x91e8b8d0, 0xbeb366d1, 0x920265e4, 0xbe88304f,\n 0x921c23ef, 0xbe5d03e6,\n 0x9235f2ec, 0xbe31e19b, 0x924fd2d7, 0xbe06c977, 0x9269c3ac, 0xbddbbb7f,\n 0x9283c568, 0xbdb0b7bb,\n 0x929dd806, 0xbd85be30, 0x92b7fb82, 0xbd5acee5, 0x92d22fd9, 0xbd2fe9e2,\n 0x92ec7505, 0xbd050f2c,\n 0x9306cb04, 0xbcda3ecb, 0x932131d1, 0xbcaf78c4, 0x933ba968, 0xbc84bd1f,\n 0x935631c5, 0xbc5a0be2,\n 0x9370cae4, 0xbc2f6513, 0x938b74c1, 0xbc04c8ba, 0x93a62f57, 0xbbda36dd,\n 0x93c0faa3, 0xbbafaf82,\n 0x93dbd6a0, 0xbb8532b0, 0x93f6c34a, 0xbb5ac06d, 0x9411c09e, 0xbb3058c0,\n 0x942cce96, 0xbb05fbb0,\n 0x9447ed2f, 0xbadba943, 0x94631c65, 0xbab16180, 0x947e5c33, 0xba87246d,\n 0x9499ac95, 0xba5cf210,\n 0x94b50d87, 0xba32ca71, 0x94d07f05, 0xba08ad95, 0x94ec010b, 0xb9de9b83,\n 0x95079394, 0xb9b49442,\n 0x9523369c, 0xb98a97d8, 0x953eea1e, 0xb960a64c, 0x955aae17, 0xb936bfa4,\n 0x95768283, 0xb90ce3e6,\n 0x9592675c, 0xb8e31319, 0x95ae5c9f, 0xb8b94d44, 0x95ca6247, 0xb88f926d,\n 0x95e67850, 0xb865e299,\n 0x96029eb6, 0xb83c3dd1, 0x961ed574, 0xb812a41a, 0x963b1c86, 0xb7e9157a,\n 0x965773e7, 0xb7bf91f8,\n 0x9673db94, 0xb796199b, 0x96905388, 0xb76cac69, 0x96acdbbe, 0xb7434a67,\n 0x96c97432, 0xb719f39e,\n 0x96e61ce0, 0xb6f0a812, 0x9702d5c3, 0xb6c767ca, 0x971f9ed7, 0xb69e32cd,\n 0x973c7817, 0xb6750921,\n 0x9759617f, 0xb64beacd, 0x97765b0a, 0xb622d7d6, 0x979364b5, 0xb5f9d043,\n 0x97b07e7a, 0xb5d0d41a,\n 0x97cda855, 0xb5a7e362, 0x97eae242, 0xb57efe22, 0x98082c3b, 0xb556245e,\n 0x9825863d, 0xb52d561e,\n 0x9842f043, 0xb5049368, 0x98606a49, 0xb4dbdc42, 0x987df449, 0xb4b330b3,\n 0x989b8e40, 0xb48a90c0,\n 0x98b93828, 0xb461fc70, 0x98d6f1fe, 0xb43973ca, 0x98f4bbbc, 0xb410f6d3,\n 0x9912955f, 0xb3e88592,\n 0x99307ee0, 0xb3c0200c, 0x994e783d, 0xb397c649, 0x996c816f, 0xb36f784f,\n 0x998a9a74, 0xb3473623,\n 0x99a8c345, 0xb31effcc, 0x99c6fbde, 0xb2f6d550, 0x99e5443b, 0xb2ceb6b5,\n 0x9a039c57, 0xb2a6a402,\n 0x9a22042d, 0xb27e9d3c, 0x9a407bb9, 0xb256a26a, 0x9a5f02f5, 0xb22eb392,\n 0x9a7d99de, 0xb206d0ba,\n 0x9a9c406e, 0xb1def9e9, 0x9abaf6a1, 0xb1b72f23, 0x9ad9bc71, 0xb18f7071,\n 0x9af891db, 0xb167bdd7,\n 0x9b1776da, 0xb140175b, 0x9b366b68, 0xb1187d05, 0x9b556f81, 0xb0f0eeda,\n 0x9b748320, 0xb0c96ce0,\n 0x9b93a641, 0xb0a1f71d, 0x9bb2d8de, 0xb07a8d97, 0x9bd21af3, 0xb0533055,\n 0x9bf16c7a, 0xb02bdf5c,\n 0x9c10cd70, 0xb0049ab3, 0x9c303dcf, 0xafdd625f, 0x9c4fbd93, 0xafb63667,\n 0x9c6f4cb6, 0xaf8f16d1,\n 0x9c8eeb34, 0xaf6803a2, 0x9cae9907, 0xaf40fce1, 0x9cce562c, 0xaf1a0293,\n 0x9cee229c, 0xaef314c0,\n 0x9d0dfe54, 0xaecc336c, 0x9d2de94d, 0xaea55e9e, 0x9d4de385, 0xae7e965b,\n 0x9d6decf4, 0xae57daab,\n 0x9d8e0597, 0xae312b92, 0x9dae2d68, 0xae0a8916, 0x9dce6463, 0xade3f33e,\n 0x9deeaa82, 0xadbd6a10,\n 0x9e0effc1, 0xad96ed92, 0x9e2f641b, 0xad707dc8, 0x9e4fd78a, 0xad4a1aba,\n 0x9e705a09, 0xad23c46e,\n 0x9e90eb94, 0xacfd7ae8, 0x9eb18c26, 0xacd73e30, 0x9ed23bb9, 0xacb10e4b,\n 0x9ef2fa49, 0xac8aeb3e,\n 0x9f13c7d0, 0xac64d510, 0x9f34a449, 0xac3ecbc7, 0x9f558fb0, 0xac18cf69,\n 0x9f7689ff, 0xabf2dffb,\n 0x9f979331, 0xabccfd83, 0x9fb8ab41, 0xaba72807, 0x9fd9d22a, 0xab815f8d,\n 0x9ffb07e7, 0xab5ba41a,\n 0xa01c4c73, 0xab35f5b5, 0xa03d9fc8, 0xab105464, 0xa05f01e1, 0xaaeac02c,\n 0xa08072ba, 0xaac53912,\n 0xa0a1f24d, 0xaa9fbf1e, 0xa0c38095, 0xaa7a5253, 0xa0e51d8c, 0xaa54f2ba,\n 0xa106c92f, 0xaa2fa056,\n 0xa1288376, 0xaa0a5b2e, 0xa14a4c5e, 0xa9e52347, 0xa16c23e1, 0xa9bff8a8,\n 0xa18e09fa, 0xa99adb56,\n 0xa1affea3, 0xa975cb57, 0xa1d201d7, 0xa950c8b0, 0xa1f41392, 0xa92bd367,\n 0xa21633cd, 0xa906eb82,\n 0xa2386284, 0xa8e21106, 0xa25a9fb1, 0xa8bd43fa, 0xa27ceb4f, 0xa8988463,\n 0xa29f4559, 0xa873d246,\n 0xa2c1adc9, 0xa84f2daa, 0xa2e4249b, 0xa82a9693, 0xa306a9c8, 0xa8060d08,\n 0xa3293d4b, 0xa7e1910f,\n 0xa34bdf20, 0xa7bd22ac, 0xa36e8f41, 0xa798c1e5, 0xa3914da8, 0xa7746ec0,\n 0xa3b41a50, 0xa7502943,\n 0xa3d6f534, 0xa72bf174, 0xa3f9de4e, 0xa707c757, 0xa41cd599, 0xa6e3aaf2,\n 0xa43fdb10, 0xa6bf9c4b,\n 0xa462eeac, 0xa69b9b68, 0xa486106a, 0xa677a84e, 0xa4a94043, 0xa653c303,\n 0xa4cc7e32, 0xa62feb8b,\n 0xa4efca31, 0xa60c21ee, 0xa513243b, 0xa5e8662f, 0xa5368c4b, 0xa5c4b855,\n 0xa55a025b, 0xa5a11866,\n 0xa57d8666, 0xa57d8666, 0xa5a11866, 0xa55a025b, 0xa5c4b855, 0xa5368c4b,\n 0xa5e8662f, 0xa513243b,\n 0xa60c21ee, 0xa4efca31, 0xa62feb8b, 0xa4cc7e32, 0xa653c303, 0xa4a94043,\n 0xa677a84e, 0xa486106a,\n 0xa69b9b68, 0xa462eeac, 0xa6bf9c4b, 0xa43fdb10, 0xa6e3aaf2, 0xa41cd599,\n 0xa707c757, 0xa3f9de4e,\n 0xa72bf174, 0xa3d6f534, 0xa7502943, 0xa3b41a50, 0xa7746ec0, 0xa3914da8,\n 0xa798c1e5, 0xa36e8f41,\n 0xa7bd22ac, 0xa34bdf20, 0xa7e1910f, 0xa3293d4b, 0xa8060d08, 0xa306a9c8,\n 0xa82a9693, 0xa2e4249b,\n 0xa84f2daa, 0xa2c1adc9, 0xa873d246, 0xa29f4559, 0xa8988463, 0xa27ceb4f,\n 0xa8bd43fa, 0xa25a9fb1,\n 0xa8e21106, 0xa2386284, 0xa906eb82, 0xa21633cd, 0xa92bd367, 0xa1f41392,\n 0xa950c8b0, 0xa1d201d7,\n 0xa975cb57, 0xa1affea3, 0xa99adb56, 0xa18e09fa, 0xa9bff8a8, 0xa16c23e1,\n 0xa9e52347, 0xa14a4c5e,\n 0xaa0a5b2e, 0xa1288376, 0xaa2fa056, 0xa106c92f, 0xaa54f2ba, 0xa0e51d8c,\n 0xaa7a5253, 0xa0c38095,\n 0xaa9fbf1e, 0xa0a1f24d, 0xaac53912, 0xa08072ba, 0xaaeac02c, 0xa05f01e1,\n 0xab105464, 0xa03d9fc8,\n 0xab35f5b5, 0xa01c4c73, 0xab5ba41a, 0x9ffb07e7, 0xab815f8d, 0x9fd9d22a,\n 0xaba72807, 0x9fb8ab41,\n 0xabccfd83, 0x9f979331, 0xabf2dffb, 0x9f7689ff, 0xac18cf69, 0x9f558fb0,\n 0xac3ecbc7, 0x9f34a449,\n 0xac64d510, 0x9f13c7d0, 0xac8aeb3e, 0x9ef2fa49, 0xacb10e4b, 0x9ed23bb9,\n 0xacd73e30, 0x9eb18c26,\n 0xacfd7ae8, 0x9e90eb94, 0xad23c46e, 0x9e705a09, 0xad4a1aba, 0x9e4fd78a,\n 0xad707dc8, 0x9e2f641b,\n 0xad96ed92, 0x9e0effc1, 0xadbd6a10, 0x9deeaa82, 0xade3f33e, 0x9dce6463,\n 0xae0a8916, 0x9dae2d68,\n 0xae312b92, 0x9d8e0597, 0xae57daab, 0x9d6decf4, 0xae7e965b, 0x9d4de385,\n 0xaea55e9e, 0x9d2de94d,\n 0xaecc336c, 0x9d0dfe54, 0xaef314c0, 0x9cee229c, 0xaf1a0293, 0x9cce562c,\n 0xaf40fce1, 0x9cae9907,\n 0xaf6803a2, 0x9c8eeb34, 0xaf8f16d1, 0x9c6f4cb6, 0xafb63667, 0x9c4fbd93,\n 0xafdd625f, 0x9c303dcf,\n 0xb0049ab3, 0x9c10cd70, 0xb02bdf5c, 0x9bf16c7a, 0xb0533055, 0x9bd21af3,\n 0xb07a8d97, 0x9bb2d8de,\n 0xb0a1f71d, 0x9b93a641, 0xb0c96ce0, 0x9b748320, 0xb0f0eeda, 0x9b556f81,\n 0xb1187d05, 0x9b366b68,\n 0xb140175b, 0x9b1776da, 0xb167bdd7, 0x9af891db, 0xb18f7071, 0x9ad9bc71,\n 0xb1b72f23, 0x9abaf6a1,\n 0xb1def9e9, 0x9a9c406e, 0xb206d0ba, 0x9a7d99de, 0xb22eb392, 0x9a5f02f5,\n 0xb256a26a, 0x9a407bb9,\n 0xb27e9d3c, 0x9a22042d, 0xb2a6a402, 0x9a039c57, 0xb2ceb6b5, 0x99e5443b,\n 0xb2f6d550, 0x99c6fbde,\n 0xb31effcc, 0x99a8c345, 0xb3473623, 0x998a9a74, 0xb36f784f, 0x996c816f,\n 0xb397c649, 0x994e783d,\n 0xb3c0200c, 0x99307ee0, 0xb3e88592, 0x9912955f, 0xb410f6d3, 0x98f4bbbc,\n 0xb43973ca, 0x98d6f1fe,\n 0xb461fc70, 0x98b93828, 0xb48a90c0, 0x989b8e40, 0xb4b330b3, 0x987df449,\n 0xb4dbdc42, 0x98606a49,\n 0xb5049368, 0x9842f043, 0xb52d561e, 0x9825863d, 0xb556245e, 0x98082c3b,\n 0xb57efe22, 0x97eae242,\n 0xb5a7e362, 0x97cda855, 0xb5d0d41a, 0x97b07e7a, 0xb5f9d043, 0x979364b5,\n 0xb622d7d6, 0x97765b0a,\n 0xb64beacd, 0x9759617f, 0xb6750921, 0x973c7817, 0xb69e32cd, 0x971f9ed7,\n 0xb6c767ca, 0x9702d5c3,\n 0xb6f0a812, 0x96e61ce0, 0xb719f39e, 0x96c97432, 0xb7434a67, 0x96acdbbe,\n 0xb76cac69, 0x96905388,\n 0xb796199b, 0x9673db94, 0xb7bf91f8, 0x965773e7, 0xb7e9157a, 0x963b1c86,\n 0xb812a41a, 0x961ed574,\n 0xb83c3dd1, 0x96029eb6, 0xb865e299, 0x95e67850, 0xb88f926d, 0x95ca6247,\n 0xb8b94d44, 0x95ae5c9f,\n 0xb8e31319, 0x9592675c, 0xb90ce3e6, 0x95768283, 0xb936bfa4, 0x955aae17,\n 0xb960a64c, 0x953eea1e,\n 0xb98a97d8, 0x9523369c, 0xb9b49442, 0x95079394, 0xb9de9b83, 0x94ec010b,\n 0xba08ad95, 0x94d07f05,\n 0xba32ca71, 0x94b50d87, 0xba5cf210, 0x9499ac95, 0xba87246d, 0x947e5c33,\n 0xbab16180, 0x94631c65,\n 0xbadba943, 0x9447ed2f, 0xbb05fbb0, 0x942cce96, 0xbb3058c0, 0x9411c09e,\n 0xbb5ac06d, 0x93f6c34a,\n 0xbb8532b0, 0x93dbd6a0, 0xbbafaf82, 0x93c0faa3, 0xbbda36dd, 0x93a62f57,\n 0xbc04c8ba, 0x938b74c1,\n 0xbc2f6513, 0x9370cae4, 0xbc5a0be2, 0x935631c5, 0xbc84bd1f, 0x933ba968,\n 0xbcaf78c4, 0x932131d1,\n 0xbcda3ecb, 0x9306cb04, 0xbd050f2c, 0x92ec7505, 0xbd2fe9e2, 0x92d22fd9,\n 0xbd5acee5, 0x92b7fb82,\n 0xbd85be30, 0x929dd806, 0xbdb0b7bb, 0x9283c568, 0xbddbbb7f, 0x9269c3ac,\n 0xbe06c977, 0x924fd2d7,\n 0xbe31e19b, 0x9235f2ec, 0xbe5d03e6, 0x921c23ef, 0xbe88304f, 0x920265e4,\n 0xbeb366d1, 0x91e8b8d0,\n 0xbedea765, 0x91cf1cb6, 0xbf09f205, 0x91b5919a, 0xbf3546a8, 0x919c1781,\n 0xbf60a54a, 0x9182ae6d,\n 0xbf8c0de3, 0x91695663, 0xbfb7806c, 0x91500f67, 0xbfe2fcdf, 0x9136d97d,\n 0xc00e8336, 0x911db4a9,\n 0xc03a1368, 0x9104a0ee, 0xc065ad70, 0x90eb9e50, 0xc0915148, 0x90d2acd4,\n 0xc0bcfee7, 0x90b9cc7d,\n 0xc0e8b648, 0x90a0fd4e, 0xc1147764, 0x90883f4d, 0xc1404233, 0x906f927c,\n 0xc16c16b0, 0x9056f6df,\n 0xc197f4d4, 0x903e6c7b, 0xc1c3dc97, 0x9025f352, 0xc1efcdf3, 0x900d8b69,\n 0xc21bc8e1, 0x8ff534c4,\n 0xc247cd5a, 0x8fdcef66, 0xc273db58, 0x8fc4bb53, 0xc29ff2d4, 0x8fac988f,\n 0xc2cc13c7, 0x8f94871d,\n 0xc2f83e2a, 0x8f7c8701, 0xc32471f7, 0x8f649840, 0xc350af26, 0x8f4cbadb,\n 0xc37cf5b0, 0x8f34eed8,\n 0xc3a94590, 0x8f1d343a, 0xc3d59ebe, 0x8f058b04, 0xc4020133, 0x8eedf33b,\n 0xc42e6ce8, 0x8ed66ce1,\n 0xc45ae1d7, 0x8ebef7fb, 0xc4875ff9, 0x8ea7948c, 0xc4b3e746, 0x8e904298,\n 0xc4e077b8, 0x8e790222,\n 0xc50d1149, 0x8e61d32e, 0xc539b3f1, 0x8e4ab5bf, 0xc5665fa9, 0x8e33a9da,\n 0xc593146a, 0x8e1caf80,\n 0xc5bfd22e, 0x8e05c6b7, 0xc5ec98ee, 0x8deeef82, 0xc61968a2, 0x8dd829e4,\n 0xc6464144, 0x8dc175e0,\n 0xc67322ce, 0x8daad37b, 0xc6a00d37, 0x8d9442b8, 0xc6cd0079, 0x8d7dc399,\n 0xc6f9fc8d, 0x8d675623,\n 0xc727016d, 0x8d50fa59, 0xc7540f11, 0x8d3ab03f, 0xc7812572, 0x8d2477d8,\n 0xc7ae4489, 0x8d0e5127,\n 0xc7db6c50, 0x8cf83c30, 0xc8089cbf, 0x8ce238f6, 0xc835d5d0, 0x8ccc477d,\n 0xc863177b, 0x8cb667c8,\n 0xc89061ba, 0x8ca099da, 0xc8bdb485, 0x8c8addb7, 0xc8eb0fd6, 0x8c753362,\n 0xc91873a5, 0x8c5f9ade,\n 0xc945dfec, 0x8c4a142f, 0xc97354a4, 0x8c349f58, 0xc9a0d1c5, 0x8c1f3c5d,\n 0xc9ce5748, 0x8c09eb40,\n 0xc9fbe527, 0x8bf4ac05, 0xca297b5a, 0x8bdf7eb0, 0xca5719db, 0x8bca6343,\n 0xca84c0a3, 0x8bb559c1,\n 0xcab26fa9, 0x8ba0622f, 0xcae026e8, 0x8b8b7c8f, 0xcb0de658, 0x8b76a8e4,\n 0xcb3badf3, 0x8b61e733,\n 0xcb697db0, 0x8b4d377c, 0xcb97558a, 0x8b3899c6, 0xcbc53579, 0x8b240e11,\n 0xcbf31d75, 0x8b0f9462,\n 0xcc210d79, 0x8afb2cbb, 0xcc4f057c, 0x8ae6d720, 0xcc7d0578, 0x8ad29394,\n 0xccab0d65, 0x8abe6219,\n 0xccd91d3d, 0x8aaa42b4, 0xcd0734f9, 0x8a963567, 0xcd355491, 0x8a823a36,\n 0xcd637bfe, 0x8a6e5123,\n 0xcd91ab39, 0x8a5a7a31, 0xcdbfe23a, 0x8a46b564, 0xcdee20fc, 0x8a3302be,\n 0xce1c6777, 0x8a1f6243,\n 0xce4ab5a2, 0x8a0bd3f5, 0xce790b79, 0x89f857d8, 0xcea768f2, 0x89e4edef,\n 0xced5ce08, 0x89d1963c,\n 0xcf043ab3, 0x89be50c3, 0xcf32aeeb, 0x89ab1d87, 0xcf612aaa, 0x8997fc8a,\n 0xcf8fade9, 0x8984edcf,\n 0xcfbe389f, 0x8971f15a, 0xcfeccac7, 0x895f072e, 0xd01b6459, 0x894c2f4c,\n 0xd04a054e, 0x893969b9,\n 0xd078ad9e, 0x8926b677, 0xd0a75d42, 0x89141589, 0xd0d61434, 0x890186f2,\n 0xd104d26b, 0x88ef0ab4,\n 0xd13397e2, 0x88dca0d3, 0xd1626490, 0x88ca4951, 0xd191386e, 0x88b80432,\n 0xd1c01375, 0x88a5d177,\n 0xd1eef59e, 0x8893b125, 0xd21ddee2, 0x8881a33d, 0xd24ccf39, 0x886fa7c2,\n 0xd27bc69c, 0x885dbeb8,\n 0xd2aac504, 0x884be821, 0xd2d9ca6a, 0x883a23ff, 0xd308d6c7, 0x88287256,\n 0xd337ea12, 0x8816d327,\n 0xd3670446, 0x88054677, 0xd396255a, 0x87f3cc48, 0xd3c54d47, 0x87e2649b,\n 0xd3f47c06, 0x87d10f75,\n 0xd423b191, 0x87bfccd7, 0xd452eddf, 0x87ae9cc5, 0xd48230e9, 0x879d7f41,\n 0xd4b17aa8, 0x878c744d,\n 0xd4e0cb15, 0x877b7bec, 0xd5102228, 0x876a9621, 0xd53f7fda, 0x8759c2ef,\n 0xd56ee424, 0x87490258,\n 0xd59e4eff, 0x8738545e, 0xd5cdc062, 0x8727b905, 0xd5fd3848, 0x8717304e,\n 0xd62cb6a8, 0x8706ba3d,\n 0xd65c3b7b, 0x86f656d3, 0xd68bc6ba, 0x86e60614, 0xd6bb585e, 0x86d5c802,\n 0xd6eaf05f, 0x86c59c9f,\n 0xd71a8eb5, 0x86b583ee, 0xd74a335b, 0x86a57df2, 0xd779de47, 0x86958aac,\n 0xd7a98f73, 0x8685aa20,\n 0xd7d946d8, 0x8675dc4f, 0xd809046e, 0x8666213c, 0xd838c82d, 0x865678eb,\n 0xd868920f, 0x8646e35c,\n 0xd898620c, 0x86376092, 0xd8c8381d, 0x8627f091, 0xd8f81439, 0x86189359,\n 0xd927f65b, 0x860948ef,\n 0xd957de7a, 0x85fa1153, 0xd987cc90, 0x85eaec88, 0xd9b7c094, 0x85dbda91,\n 0xd9e7ba7f, 0x85ccdb70,\n 0xda17ba4a, 0x85bdef28, 0xda47bfee, 0x85af15b9, 0xda77cb63, 0x85a04f28,\n 0xdaa7dca1, 0x85919b76,\n 0xdad7f3a2, 0x8582faa5, 0xdb08105e, 0x85746cb8, 0xdb3832cd, 0x8565f1b0,\n 0xdb685ae9, 0x85578991,\n 0xdb9888a8, 0x8549345c, 0xdbc8bc06, 0x853af214, 0xdbf8f4f8, 0x852cc2bb,\n 0xdc293379, 0x851ea652,\n 0xdc597781, 0x85109cdd, 0xdc89c109, 0x8502a65c, 0xdcba1008, 0x84f4c2d4,\n 0xdcea6478, 0x84e6f244,\n 0xdd1abe51, 0x84d934b1, 0xdd4b1d8c, 0x84cb8a1b, 0xdd7b8220, 0x84bdf286,\n 0xddabec08, 0x84b06df2,\n 0xdddc5b3b, 0x84a2fc62, 0xde0ccfb1, 0x84959dd9, 0xde3d4964, 0x84885258,\n 0xde6dc84b, 0x847b19e1,\n 0xde9e4c60, 0x846df477, 0xdeced59b, 0x8460e21a, 0xdeff63f4, 0x8453e2cf,\n 0xdf2ff764, 0x8446f695,\n 0xdf608fe4, 0x843a1d70, 0xdf912d6b, 0x842d5762, 0xdfc1cff3, 0x8420a46c,\n 0xdff27773, 0x84140490,\n 0xe02323e5, 0x840777d0, 0xe053d541, 0x83fafe2e, 0xe0848b7f, 0x83ee97ad,\n 0xe0b54698, 0x83e2444d,\n 0xe0e60685, 0x83d60412, 0xe116cb3d, 0x83c9d6fc, 0xe14794ba, 0x83bdbd0e,\n 0xe17862f3, 0x83b1b649,\n 0xe1a935e2, 0x83a5c2b0, 0xe1da0d7e, 0x8399e244, 0xe20ae9c1, 0x838e1507,\n 0xe23bcaa2, 0x83825afb,\n 0xe26cb01b, 0x8376b422, 0xe29d9a23, 0x836b207d, 0xe2ce88b3, 0x835fa00f,\n 0xe2ff7bc3, 0x835432d8,\n 0xe330734d, 0x8348d8dc, 0xe3616f48, 0x833d921b, 0xe3926fad, 0x83325e97,\n 0xe3c37474, 0x83273e52,\n 0xe3f47d96, 0x831c314e, 0xe4258b0a, 0x8311378d, 0xe4569ccb, 0x83065110,\n 0xe487b2d0, 0x82fb7dd8,\n 0xe4b8cd11, 0x82f0bde8, 0xe4e9eb87, 0x82e61141, 0xe51b0e2a, 0x82db77e5,\n 0xe54c34f3, 0x82d0f1d5,\n 0xe57d5fda, 0x82c67f14, 0xe5ae8ed8, 0x82bc1fa2, 0xe5dfc1e5, 0x82b1d381,\n 0xe610f8f9, 0x82a79ab3,\n 0xe642340d, 0x829d753a, 0xe6737319, 0x82936317, 0xe6a4b616, 0x8289644b,\n 0xe6d5fcfc, 0x827f78d8,\n 0xe70747c4, 0x8275a0c0, 0xe7389665, 0x826bdc04, 0xe769e8d8, 0x82622aa6,\n 0xe79b3f16, 0x82588ca7,\n 0xe7cc9917, 0x824f0208, 0xe7fdf6d4, 0x82458acc, 0xe82f5844, 0x823c26f3,\n 0xe860bd61, 0x8232d67f,\n 0xe8922622, 0x82299971, 0xe8c39280, 0x82206fcc, 0xe8f50273, 0x82175990,\n 0xe92675f4, 0x820e56be,\n 0xe957ecfb, 0x82056758, 0xe9896781, 0x81fc8b60, 0xe9bae57d, 0x81f3c2d7,\n 0xe9ec66e8, 0x81eb0dbe,\n 0xea1debbb, 0x81e26c16, 0xea4f73ee, 0x81d9dde1, 0xea80ff7a, 0x81d16321,\n 0xeab28e56, 0x81c8fbd6,\n 0xeae4207a, 0x81c0a801, 0xeb15b5e1, 0x81b867a5, 0xeb474e81, 0x81b03ac2,\n 0xeb78ea52, 0x81a82159,\n 0xebaa894f, 0x81a01b6d, 0xebdc2b6e, 0x819828fd, 0xec0dd0a8, 0x81904a0c,\n 0xec3f78f6, 0x81887e9a,\n 0xec71244f, 0x8180c6a9, 0xeca2d2ad, 0x8179223a, 0xecd48407, 0x8171914e,\n 0xed063856, 0x816a13e6,\n 0xed37ef91, 0x8162aa04, 0xed69a9b3, 0x815b53a8, 0xed9b66b2, 0x815410d4,\n 0xedcd2687, 0x814ce188,\n 0xedfee92b, 0x8145c5c7, 0xee30ae96, 0x813ebd90, 0xee6276bf, 0x8137c8e6,\n 0xee9441a0, 0x8130e7c9,\n 0xeec60f31, 0x812a1a3a, 0xeef7df6a, 0x8123603a, 0xef29b243, 0x811cb9ca,\n 0xef5b87b5, 0x811626ec,\n 0xef8d5fb8, 0x810fa7a0, 0xefbf3a45, 0x81093be8, 0xeff11753, 0x8102e3c4,\n 0xf022f6da, 0x80fc9f35,\n 0xf054d8d5, 0x80f66e3c, 0xf086bd39, 0x80f050db, 0xf0b8a401, 0x80ea4712,\n 0xf0ea8d24, 0x80e450e2,\n 0xf11c789a, 0x80de6e4c, 0xf14e665c, 0x80d89f51, 0xf1805662, 0x80d2e3f2,\n 0xf1b248a5, 0x80cd3c2f,\n 0xf1e43d1c, 0x80c7a80a, 0xf21633c0, 0x80c22784, 0xf2482c8a, 0x80bcba9d,\n 0xf27a2771, 0x80b76156,\n 0xf2ac246e, 0x80b21baf, 0xf2de2379, 0x80ace9ab, 0xf310248a, 0x80a7cb49,\n 0xf342279b, 0x80a2c08b,\n 0xf3742ca2, 0x809dc971, 0xf3a63398, 0x8098e5fb, 0xf3d83c77, 0x8094162c,\n 0xf40a4735, 0x808f5a02,\n 0xf43c53cb, 0x808ab180, 0xf46e6231, 0x80861ca6, 0xf4a07261, 0x80819b74,\n 0xf4d28451, 0x807d2dec,\n 0xf50497fb, 0x8078d40d, 0xf536ad56, 0x80748dd9, 0xf568c45b, 0x80705b50,\n 0xf59add02, 0x806c3c74,\n 0xf5ccf743, 0x80683143, 0xf5ff1318, 0x806439c0, 0xf6313077, 0x806055eb,\n 0xf6634f59, 0x805c85c4,\n 0xf6956fb7, 0x8058c94c, 0xf6c79188, 0x80552084, 0xf6f9b4c6, 0x80518b6b,\n 0xf72bd967, 0x804e0a04,\n 0xf75dff66, 0x804a9c4d, 0xf79026b9, 0x80474248, 0xf7c24f59, 0x8043fbf6,\n 0xf7f4793e, 0x8040c956,\n 0xf826a462, 0x803daa6a, 0xf858d0bb, 0x803a9f31, 0xf88afe42, 0x8037a7ac,\n 0xf8bd2cef, 0x8034c3dd,\n 0xf8ef5cbb, 0x8031f3c2, 0xf9218d9e, 0x802f375d, 0xf953bf91, 0x802c8ead,\n 0xf985f28a, 0x8029f9b4,\n 0xf9b82684, 0x80277872, 0xf9ea5b75, 0x80250ae7, 0xfa1c9157, 0x8022b114,\n 0xfa4ec821, 0x80206af8,\n 0xfa80ffcb, 0x801e3895, 0xfab3384f, 0x801c19ea, 0xfae571a4, 0x801a0ef8,\n 0xfb17abc2, 0x801817bf,\n 0xfb49e6a3, 0x80163440, 0xfb7c223d, 0x8014647b, 0xfbae5e89, 0x8012a86f,\n 0xfbe09b80, 0x8011001f,\n 0xfc12d91a, 0x800f6b88, 0xfc45174e, 0x800deaad, 0xfc775616, 0x800c7d8c,\n 0xfca9956a, 0x800b2427,\n 0xfcdbd541, 0x8009de7e, 0xfd0e1594, 0x8008ac90, 0xfd40565c, 0x80078e5e,\n 0xfd729790, 0x800683e8,\n 0xfda4d929, 0x80058d2f, 0xfdd71b1e, 0x8004aa32, 0xfe095d69, 0x8003daf1,\n 0xfe3ba002, 0x80031f6d,\n 0xfe6de2e0, 0x800277a6, 0xfea025fd, 0x8001e39b, 0xfed2694f, 0x8001634e,\n 0xff04acd0, 0x8000f6bd,\n 0xff36f078, 0x80009dea, 0xff69343f, 0x800058d4, 0xff9b781d, 0x8000277a,\n 0xffcdbc0b, 0x800009df,\n\n};\n\n\n/* \n* @brief Q15 Twiddle factors Table \n*/\n\n/** \n* \\par \n* Example code for Q15 Twiddle factors Generation:: \n* \\par \n* 
for(i = 0; i< 3N/4; i++)    \n* {    \n*\ttwiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);    \n*\ttwiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);    \n* }
\n* \\par \n* where N = 4096\tand PI = 3.14159265358979 \n* \\par \n* Cos and Sin values are interleaved fashion \n* \\par \n* Convert Floating point to Q15(Fixed point 1.15): \n*\tround(twiddleCoefQ15(i) * pow(2, 15)) \n* \n*/\n\nconst q15_t ALIGN4 twiddleCoefQ15[6144] = {\n\n 0x7fff, 0x0, 0x7fff, 0x32, 0x7fff, 0x65, 0x7fff, 0x97,\n 0x7fff, 0xc9, 0x7fff, 0xfb, 0x7fff, 0x12e, 0x7ffe, 0x160,\n 0x7ffe, 0x192, 0x7ffd, 0x1c4, 0x7ffc, 0x1f7, 0x7ffb, 0x229,\n 0x7ffa, 0x25b, 0x7ff9, 0x28d, 0x7ff8, 0x2c0, 0x7ff7, 0x2f2,\n 0x7ff6, 0x324, 0x7ff5, 0x356, 0x7ff4, 0x389, 0x7ff2, 0x3bb,\n 0x7ff1, 0x3ed, 0x7fef, 0x41f, 0x7fed, 0x452, 0x7fec, 0x484,\n 0x7fea, 0x4b6, 0x7fe8, 0x4e8, 0x7fe6, 0x51b, 0x7fe4, 0x54d,\n 0x7fe2, 0x57f, 0x7fe0, 0x5b1, 0x7fdd, 0x5e3, 0x7fdb, 0x616,\n 0x7fd9, 0x648, 0x7fd6, 0x67a, 0x7fd3, 0x6ac, 0x7fd1, 0x6de,\n 0x7fce, 0x711, 0x7fcb, 0x743, 0x7fc8, 0x775, 0x7fc5, 0x7a7,\n 0x7fc2, 0x7d9, 0x7fbf, 0x80c, 0x7fbc, 0x83e, 0x7fb9, 0x870,\n 0x7fb5, 0x8a2, 0x7fb2, 0x8d4, 0x7fae, 0x906, 0x7fab, 0x938,\n 0x7fa7, 0x96b, 0x7fa3, 0x99d, 0x7fa0, 0x9cf, 0x7f9c, 0xa01,\n 0x7f98, 0xa33, 0x7f94, 0xa65, 0x7f90, 0xa97, 0x7f8b, 0xac9,\n 0x7f87, 0xafb, 0x7f83, 0xb2d, 0x7f7e, 0xb60, 0x7f7a, 0xb92,\n 0x7f75, 0xbc4, 0x7f71, 0xbf6, 0x7f6c, 0xc28, 0x7f67, 0xc5a,\n 0x7f62, 0xc8c, 0x7f5d, 0xcbe, 0x7f58, 0xcf0, 0x7f53, 0xd22,\n 0x7f4e, 0xd54, 0x7f49, 0xd86, 0x7f43, 0xdb8, 0x7f3e, 0xdea,\n 0x7f38, 0xe1c, 0x7f33, 0xe4e, 0x7f2d, 0xe80, 0x7f27, 0xeb2,\n 0x7f22, 0xee4, 0x7f1c, 0xf15, 0x7f16, 0xf47, 0x7f10, 0xf79,\n 0x7f0a, 0xfab, 0x7f03, 0xfdd, 0x7efd, 0x100f, 0x7ef7, 0x1041,\n 0x7ef0, 0x1073, 0x7eea, 0x10a4, 0x7ee3, 0x10d6, 0x7edd, 0x1108,\n 0x7ed6, 0x113a, 0x7ecf, 0x116c, 0x7ec8, 0x119e, 0x7ec1, 0x11cf,\n 0x7eba, 0x1201, 0x7eb3, 0x1233, 0x7eac, 0x1265, 0x7ea5, 0x1296,\n 0x7e9d, 0x12c8, 0x7e96, 0x12fa, 0x7e8e, 0x132b, 0x7e87, 0x135d,\n 0x7e7f, 0x138f, 0x7e78, 0x13c1, 0x7e70, 0x13f2, 0x7e68, 0x1424,\n 0x7e60, 0x1455, 0x7e58, 0x1487, 0x7e50, 0x14b9, 0x7e48, 0x14ea,\n 0x7e3f, 0x151c, 0x7e37, 0x154d, 0x7e2f, 0x157f, 0x7e26, 0x15b1,\n 0x7e1e, 0x15e2, 0x7e15, 0x1614, 0x7e0c, 0x1645, 0x7e03, 0x1677,\n 0x7dfb, 0x16a8, 0x7df2, 0x16da, 0x7de9, 0x170b, 0x7de0, 0x173c,\n 0x7dd6, 0x176e, 0x7dcd, 0x179f, 0x7dc4, 0x17d1, 0x7dba, 0x1802,\n 0x7db1, 0x1833, 0x7da7, 0x1865, 0x7d9e, 0x1896, 0x7d94, 0x18c7,\n 0x7d8a, 0x18f9, 0x7d81, 0x192a, 0x7d77, 0x195b, 0x7d6d, 0x198d,\n 0x7d63, 0x19be, 0x7d58, 0x19ef, 0x7d4e, 0x1a20, 0x7d44, 0x1a51,\n 0x7d3a, 0x1a83, 0x7d2f, 0x1ab4, 0x7d25, 0x1ae5, 0x7d1a, 0x1b16,\n 0x7d0f, 0x1b47, 0x7d05, 0x1b78, 0x7cfa, 0x1ba9, 0x7cef, 0x1bda,\n 0x7ce4, 0x1c0c, 0x7cd9, 0x1c3d, 0x7cce, 0x1c6e, 0x7cc2, 0x1c9f,\n 0x7cb7, 0x1cd0, 0x7cac, 0x1d01, 0x7ca0, 0x1d31, 0x7c95, 0x1d62,\n 0x7c89, 0x1d93, 0x7c7e, 0x1dc4, 0x7c72, 0x1df5, 0x7c66, 0x1e26,\n 0x7c5a, 0x1e57, 0x7c4e, 0x1e88, 0x7c42, 0x1eb8, 0x7c36, 0x1ee9,\n 0x7c2a, 0x1f1a, 0x7c1e, 0x1f4b, 0x7c11, 0x1f7b, 0x7c05, 0x1fac,\n 0x7bf9, 0x1fdd, 0x7bec, 0x200e, 0x7bdf, 0x203e, 0x7bd3, 0x206f,\n 0x7bc6, 0x209f, 0x7bb9, 0x20d0, 0x7bac, 0x2101, 0x7b9f, 0x2131,\n 0x7b92, 0x2162, 0x7b85, 0x2192, 0x7b78, 0x21c3, 0x7b6a, 0x21f3,\n 0x7b5d, 0x2224, 0x7b50, 0x2254, 0x7b42, 0x2284, 0x7b34, 0x22b5,\n 0x7b27, 0x22e5, 0x7b19, 0x2316, 0x7b0b, 0x2346, 0x7afd, 0x2376,\n 0x7aef, 0x23a7, 0x7ae1, 0x23d7, 0x7ad3, 0x2407, 0x7ac5, 0x2437,\n 0x7ab7, 0x2467, 0x7aa8, 0x2498, 0x7a9a, 0x24c8, 0x7a8c, 0x24f8,\n 0x7a7d, 0x2528, 0x7a6e, 0x2558, 0x7a60, 0x2588, 0x7a51, 0x25b8,\n 0x7a42, 0x25e8, 0x7a33, 0x2618, 0x7a24, 0x2648, 0x7a15, 0x2678,\n 0x7a06, 0x26a8, 0x79f7, 0x26d8, 0x79e7, 0x2708, 0x79d8, 0x2738,\n 0x79c9, 0x2768, 0x79b9, 0x2797, 0x79aa, 0x27c7, 0x799a, 0x27f7,\n 0x798a, 0x2827, 0x797a, 0x2856, 0x796a, 0x2886, 0x795b, 0x28b6,\n 0x794a, 0x28e5, 0x793a, 0x2915, 0x792a, 0x2945, 0x791a, 0x2974,\n 0x790a, 0x29a4, 0x78f9, 0x29d3, 0x78e9, 0x2a03, 0x78d8, 0x2a32,\n 0x78c8, 0x2a62, 0x78b7, 0x2a91, 0x78a6, 0x2ac1, 0x7895, 0x2af0,\n 0x7885, 0x2b1f, 0x7874, 0x2b4f, 0x7863, 0x2b7e, 0x7851, 0x2bad,\n 0x7840, 0x2bdc, 0x782f, 0x2c0c, 0x781e, 0x2c3b, 0x780c, 0x2c6a,\n 0x77fb, 0x2c99, 0x77e9, 0x2cc8, 0x77d8, 0x2cf7, 0x77c6, 0x2d26,\n 0x77b4, 0x2d55, 0x77a2, 0x2d84, 0x7790, 0x2db3, 0x777e, 0x2de2,\n 0x776c, 0x2e11, 0x775a, 0x2e40, 0x7748, 0x2e6f, 0x7736, 0x2e9e,\n 0x7723, 0x2ecc, 0x7711, 0x2efb, 0x76fe, 0x2f2a, 0x76ec, 0x2f59,\n 0x76d9, 0x2f87, 0x76c7, 0x2fb6, 0x76b4, 0x2fe5, 0x76a1, 0x3013,\n 0x768e, 0x3042, 0x767b, 0x3070, 0x7668, 0x309f, 0x7655, 0x30cd,\n 0x7642, 0x30fc, 0x762e, 0x312a, 0x761b, 0x3159, 0x7608, 0x3187,\n 0x75f4, 0x31b5, 0x75e1, 0x31e4, 0x75cd, 0x3212, 0x75b9, 0x3240,\n 0x75a6, 0x326e, 0x7592, 0x329d, 0x757e, 0x32cb, 0x756a, 0x32f9,\n 0x7556, 0x3327, 0x7542, 0x3355, 0x752d, 0x3383, 0x7519, 0x33b1,\n 0x7505, 0x33df, 0x74f0, 0x340d, 0x74dc, 0x343b, 0x74c7, 0x3469,\n 0x74b3, 0x3497, 0x749e, 0x34c4, 0x7489, 0x34f2, 0x7475, 0x3520,\n 0x7460, 0x354e, 0x744b, 0x357b, 0x7436, 0x35a9, 0x7421, 0x35d7,\n 0x740b, 0x3604, 0x73f6, 0x3632, 0x73e1, 0x365f, 0x73cb, 0x368d,\n 0x73b6, 0x36ba, 0x73a0, 0x36e8, 0x738b, 0x3715, 0x7375, 0x3742,\n 0x735f, 0x3770, 0x734a, 0x379d, 0x7334, 0x37ca, 0x731e, 0x37f7,\n 0x7308, 0x3825, 0x72f2, 0x3852, 0x72dc, 0x387f, 0x72c5, 0x38ac,\n 0x72af, 0x38d9, 0x7299, 0x3906, 0x7282, 0x3933, 0x726c, 0x3960,\n 0x7255, 0x398d, 0x723f, 0x39ba, 0x7228, 0x39e7, 0x7211, 0x3a13,\n 0x71fa, 0x3a40, 0x71e3, 0x3a6d, 0x71cc, 0x3a9a, 0x71b5, 0x3ac6,\n 0x719e, 0x3af3, 0x7187, 0x3b20, 0x7170, 0x3b4c, 0x7158, 0x3b79,\n 0x7141, 0x3ba5, 0x712a, 0x3bd2, 0x7112, 0x3bfe, 0x70fa, 0x3c2a,\n 0x70e3, 0x3c57, 0x70cb, 0x3c83, 0x70b3, 0x3caf, 0x709b, 0x3cdc,\n 0x7083, 0x3d08, 0x706b, 0x3d34, 0x7053, 0x3d60, 0x703b, 0x3d8c,\n 0x7023, 0x3db8, 0x700b, 0x3de4, 0x6ff2, 0x3e10, 0x6fda, 0x3e3c,\n 0x6fc2, 0x3e68, 0x6fa9, 0x3e94, 0x6f90, 0x3ec0, 0x6f78, 0x3eec,\n 0x6f5f, 0x3f17, 0x6f46, 0x3f43, 0x6f2d, 0x3f6f, 0x6f14, 0x3f9a,\n 0x6efb, 0x3fc6, 0x6ee2, 0x3ff1, 0x6ec9, 0x401d, 0x6eb0, 0x4048,\n 0x6e97, 0x4074, 0x6e7d, 0x409f, 0x6e64, 0x40cb, 0x6e4a, 0x40f6,\n 0x6e31, 0x4121, 0x6e17, 0x414d, 0x6dfe, 0x4178, 0x6de4, 0x41a3,\n 0x6dca, 0x41ce, 0x6db0, 0x41f9, 0x6d96, 0x4224, 0x6d7c, 0x424f,\n 0x6d62, 0x427a, 0x6d48, 0x42a5, 0x6d2e, 0x42d0, 0x6d14, 0x42fb,\n 0x6cf9, 0x4326, 0x6cdf, 0x4351, 0x6cc4, 0x437b, 0x6caa, 0x43a6,\n 0x6c8f, 0x43d1, 0x6c75, 0x43fb, 0x6c5a, 0x4426, 0x6c3f, 0x4450,\n 0x6c24, 0x447b, 0x6c09, 0x44a5, 0x6bee, 0x44d0, 0x6bd3, 0x44fa,\n 0x6bb8, 0x4524, 0x6b9d, 0x454f, 0x6b82, 0x4579, 0x6b66, 0x45a3,\n 0x6b4b, 0x45cd, 0x6b30, 0x45f7, 0x6b14, 0x4621, 0x6af8, 0x464b,\n 0x6add, 0x4675, 0x6ac1, 0x469f, 0x6aa5, 0x46c9, 0x6a89, 0x46f3,\n 0x6a6e, 0x471d, 0x6a52, 0x4747, 0x6a36, 0x4770, 0x6a1a, 0x479a,\n 0x69fd, 0x47c4, 0x69e1, 0x47ed, 0x69c5, 0x4817, 0x69a9, 0x4840,\n 0x698c, 0x486a, 0x6970, 0x4893, 0x6953, 0x48bd, 0x6937, 0x48e6,\n 0x691a, 0x490f, 0x68fd, 0x4939, 0x68e0, 0x4962, 0x68c4, 0x498b,\n 0x68a7, 0x49b4, 0x688a, 0x49dd, 0x686d, 0x4a06, 0x6850, 0x4a2f,\n 0x6832, 0x4a58, 0x6815, 0x4a81, 0x67f8, 0x4aaa, 0x67da, 0x4ad3,\n 0x67bd, 0x4afb, 0x67a0, 0x4b24, 0x6782, 0x4b4d, 0x6764, 0x4b75,\n 0x6747, 0x4b9e, 0x6729, 0x4bc7, 0x670b, 0x4bef, 0x66ed, 0x4c17,\n 0x66d0, 0x4c40, 0x66b2, 0x4c68, 0x6693, 0x4c91, 0x6675, 0x4cb9,\n 0x6657, 0x4ce1, 0x6639, 0x4d09, 0x661b, 0x4d31, 0x65fc, 0x4d59,\n 0x65de, 0x4d81, 0x65c0, 0x4da9, 0x65a1, 0x4dd1, 0x6582, 0x4df9,\n 0x6564, 0x4e21, 0x6545, 0x4e49, 0x6526, 0x4e71, 0x6507, 0x4e98,\n 0x64e9, 0x4ec0, 0x64ca, 0x4ee8, 0x64ab, 0x4f0f, 0x648b, 0x4f37,\n 0x646c, 0x4f5e, 0x644d, 0x4f85, 0x642e, 0x4fad, 0x640f, 0x4fd4,\n 0x63ef, 0x4ffb, 0x63d0, 0x5023, 0x63b0, 0x504a, 0x6391, 0x5071,\n 0x6371, 0x5098, 0x6351, 0x50bf, 0x6332, 0x50e6, 0x6312, 0x510d,\n 0x62f2, 0x5134, 0x62d2, 0x515b, 0x62b2, 0x5181, 0x6292, 0x51a8,\n 0x6272, 0x51cf, 0x6252, 0x51f5, 0x6232, 0x521c, 0x6211, 0x5243,\n 0x61f1, 0x5269, 0x61d1, 0x5290, 0x61b0, 0x52b6, 0x6190, 0x52dc,\n 0x616f, 0x5303, 0x614e, 0x5329, 0x612e, 0x534f, 0x610d, 0x5375,\n 0x60ec, 0x539b, 0x60cb, 0x53c1, 0x60aa, 0x53e7, 0x6089, 0x540d,\n 0x6068, 0x5433, 0x6047, 0x5459, 0x6026, 0x547f, 0x6005, 0x54a4,\n 0x5fe4, 0x54ca, 0x5fc2, 0x54f0, 0x5fa1, 0x5515, 0x5f80, 0x553b,\n 0x5f5e, 0x5560, 0x5f3c, 0x5586, 0x5f1b, 0x55ab, 0x5ef9, 0x55d0,\n 0x5ed7, 0x55f6, 0x5eb6, 0x561b, 0x5e94, 0x5640, 0x5e72, 0x5665,\n 0x5e50, 0x568a, 0x5e2e, 0x56af, 0x5e0c, 0x56d4, 0x5dea, 0x56f9,\n 0x5dc8, 0x571e, 0x5da5, 0x5743, 0x5d83, 0x5767, 0x5d61, 0x578c,\n 0x5d3e, 0x57b1, 0x5d1c, 0x57d5, 0x5cf9, 0x57fa, 0x5cd7, 0x581e,\n 0x5cb4, 0x5843, 0x5c91, 0x5867, 0x5c6f, 0x588c, 0x5c4c, 0x58b0,\n 0x5c29, 0x58d4, 0x5c06, 0x58f8, 0x5be3, 0x591c, 0x5bc0, 0x5940,\n 0x5b9d, 0x5964, 0x5b7a, 0x5988, 0x5b57, 0x59ac, 0x5b34, 0x59d0,\n 0x5b10, 0x59f4, 0x5aed, 0x5a18, 0x5ac9, 0x5a3b, 0x5aa6, 0x5a5f,\n 0x5a82, 0x5a82, 0x5a5f, 0x5aa6, 0x5a3b, 0x5ac9, 0x5a18, 0x5aed,\n 0x59f4, 0x5b10, 0x59d0, 0x5b34, 0x59ac, 0x5b57, 0x5988, 0x5b7a,\n 0x5964, 0x5b9d, 0x5940, 0x5bc0, 0x591c, 0x5be3, 0x58f8, 0x5c06,\n 0x58d4, 0x5c29, 0x58b0, 0x5c4c, 0x588c, 0x5c6f, 0x5867, 0x5c91,\n 0x5843, 0x5cb4, 0x581e, 0x5cd7, 0x57fa, 0x5cf9, 0x57d5, 0x5d1c,\n 0x57b1, 0x5d3e, 0x578c, 0x5d61, 0x5767, 0x5d83, 0x5743, 0x5da5,\n 0x571e, 0x5dc8, 0x56f9, 0x5dea, 0x56d4, 0x5e0c, 0x56af, 0x5e2e,\n 0x568a, 0x5e50, 0x5665, 0x5e72, 0x5640, 0x5e94, 0x561b, 0x5eb6,\n 0x55f6, 0x5ed7, 0x55d0, 0x5ef9, 0x55ab, 0x5f1b, 0x5586, 0x5f3c,\n 0x5560, 0x5f5e, 0x553b, 0x5f80, 0x5515, 0x5fa1, 0x54f0, 0x5fc2,\n 0x54ca, 0x5fe4, 0x54a4, 0x6005, 0x547f, 0x6026, 0x5459, 0x6047,\n 0x5433, 0x6068, 0x540d, 0x6089, 0x53e7, 0x60aa, 0x53c1, 0x60cb,\n 0x539b, 0x60ec, 0x5375, 0x610d, 0x534f, 0x612e, 0x5329, 0x614e,\n 0x5303, 0x616f, 0x52dc, 0x6190, 0x52b6, 0x61b0, 0x5290, 0x61d1,\n 0x5269, 0x61f1, 0x5243, 0x6211, 0x521c, 0x6232, 0x51f5, 0x6252,\n 0x51cf, 0x6272, 0x51a8, 0x6292, 0x5181, 0x62b2, 0x515b, 0x62d2,\n 0x5134, 0x62f2, 0x510d, 0x6312, 0x50e6, 0x6332, 0x50bf, 0x6351,\n 0x5098, 0x6371, 0x5071, 0x6391, 0x504a, 0x63b0, 0x5023, 0x63d0,\n 0x4ffb, 0x63ef, 0x4fd4, 0x640f, 0x4fad, 0x642e, 0x4f85, 0x644d,\n 0x4f5e, 0x646c, 0x4f37, 0x648b, 0x4f0f, 0x64ab, 0x4ee8, 0x64ca,\n 0x4ec0, 0x64e9, 0x4e98, 0x6507, 0x4e71, 0x6526, 0x4e49, 0x6545,\n 0x4e21, 0x6564, 0x4df9, 0x6582, 0x4dd1, 0x65a1, 0x4da9, 0x65c0,\n 0x4d81, 0x65de, 0x4d59, 0x65fc, 0x4d31, 0x661b, 0x4d09, 0x6639,\n 0x4ce1, 0x6657, 0x4cb9, 0x6675, 0x4c91, 0x6693, 0x4c68, 0x66b2,\n 0x4c40, 0x66d0, 0x4c17, 0x66ed, 0x4bef, 0x670b, 0x4bc7, 0x6729,\n 0x4b9e, 0x6747, 0x4b75, 0x6764, 0x4b4d, 0x6782, 0x4b24, 0x67a0,\n 0x4afb, 0x67bd, 0x4ad3, 0x67da, 0x4aaa, 0x67f8, 0x4a81, 0x6815,\n 0x4a58, 0x6832, 0x4a2f, 0x6850, 0x4a06, 0x686d, 0x49dd, 0x688a,\n 0x49b4, 0x68a7, 0x498b, 0x68c4, 0x4962, 0x68e0, 0x4939, 0x68fd,\n 0x490f, 0x691a, 0x48e6, 0x6937, 0x48bd, 0x6953, 0x4893, 0x6970,\n 0x486a, 0x698c, 0x4840, 0x69a9, 0x4817, 0x69c5, 0x47ed, 0x69e1,\n 0x47c4, 0x69fd, 0x479a, 0x6a1a, 0x4770, 0x6a36, 0x4747, 0x6a52,\n 0x471d, 0x6a6e, 0x46f3, 0x6a89, 0x46c9, 0x6aa5, 0x469f, 0x6ac1,\n 0x4675, 0x6add, 0x464b, 0x6af8, 0x4621, 0x6b14, 0x45f7, 0x6b30,\n 0x45cd, 0x6b4b, 0x45a3, 0x6b66, 0x4579, 0x6b82, 0x454f, 0x6b9d,\n 0x4524, 0x6bb8, 0x44fa, 0x6bd3, 0x44d0, 0x6bee, 0x44a5, 0x6c09,\n 0x447b, 0x6c24, 0x4450, 0x6c3f, 0x4426, 0x6c5a, 0x43fb, 0x6c75,\n 0x43d1, 0x6c8f, 0x43a6, 0x6caa, 0x437b, 0x6cc4, 0x4351, 0x6cdf,\n 0x4326, 0x6cf9, 0x42fb, 0x6d14, 0x42d0, 0x6d2e, 0x42a5, 0x6d48,\n 0x427a, 0x6d62, 0x424f, 0x6d7c, 0x4224, 0x6d96, 0x41f9, 0x6db0,\n 0x41ce, 0x6dca, 0x41a3, 0x6de4, 0x4178, 0x6dfe, 0x414d, 0x6e17,\n 0x4121, 0x6e31, 0x40f6, 0x6e4a, 0x40cb, 0x6e64, 0x409f, 0x6e7d,\n 0x4074, 0x6e97, 0x4048, 0x6eb0, 0x401d, 0x6ec9, 0x3ff1, 0x6ee2,\n 0x3fc6, 0x6efb, 0x3f9a, 0x6f14, 0x3f6f, 0x6f2d, 0x3f43, 0x6f46,\n 0x3f17, 0x6f5f, 0x3eec, 0x6f78, 0x3ec0, 0x6f90, 0x3e94, 0x6fa9,\n 0x3e68, 0x6fc2, 0x3e3c, 0x6fda, 0x3e10, 0x6ff2, 0x3de4, 0x700b,\n 0x3db8, 0x7023, 0x3d8c, 0x703b, 0x3d60, 0x7053, 0x3d34, 0x706b,\n 0x3d08, 0x7083, 0x3cdc, 0x709b, 0x3caf, 0x70b3, 0x3c83, 0x70cb,\n 0x3c57, 0x70e3, 0x3c2a, 0x70fa, 0x3bfe, 0x7112, 0x3bd2, 0x712a,\n 0x3ba5, 0x7141, 0x3b79, 0x7158, 0x3b4c, 0x7170, 0x3b20, 0x7187,\n 0x3af3, 0x719e, 0x3ac6, 0x71b5, 0x3a9a, 0x71cc, 0x3a6d, 0x71e3,\n 0x3a40, 0x71fa, 0x3a13, 0x7211, 0x39e7, 0x7228, 0x39ba, 0x723f,\n 0x398d, 0x7255, 0x3960, 0x726c, 0x3933, 0x7282, 0x3906, 0x7299,\n 0x38d9, 0x72af, 0x38ac, 0x72c5, 0x387f, 0x72dc, 0x3852, 0x72f2,\n 0x3825, 0x7308, 0x37f7, 0x731e, 0x37ca, 0x7334, 0x379d, 0x734a,\n 0x3770, 0x735f, 0x3742, 0x7375, 0x3715, 0x738b, 0x36e8, 0x73a0,\n 0x36ba, 0x73b6, 0x368d, 0x73cb, 0x365f, 0x73e1, 0x3632, 0x73f6,\n 0x3604, 0x740b, 0x35d7, 0x7421, 0x35a9, 0x7436, 0x357b, 0x744b,\n 0x354e, 0x7460, 0x3520, 0x7475, 0x34f2, 0x7489, 0x34c4, 0x749e,\n 0x3497, 0x74b3, 0x3469, 0x74c7, 0x343b, 0x74dc, 0x340d, 0x74f0,\n 0x33df, 0x7505, 0x33b1, 0x7519, 0x3383, 0x752d, 0x3355, 0x7542,\n 0x3327, 0x7556, 0x32f9, 0x756a, 0x32cb, 0x757e, 0x329d, 0x7592,\n 0x326e, 0x75a6, 0x3240, 0x75b9, 0x3212, 0x75cd, 0x31e4, 0x75e1,\n 0x31b5, 0x75f4, 0x3187, 0x7608, 0x3159, 0x761b, 0x312a, 0x762e,\n 0x30fc, 0x7642, 0x30cd, 0x7655, 0x309f, 0x7668, 0x3070, 0x767b,\n 0x3042, 0x768e, 0x3013, 0x76a1, 0x2fe5, 0x76b4, 0x2fb6, 0x76c7,\n 0x2f87, 0x76d9, 0x2f59, 0x76ec, 0x2f2a, 0x76fe, 0x2efb, 0x7711,\n 0x2ecc, 0x7723, 0x2e9e, 0x7736, 0x2e6f, 0x7748, 0x2e40, 0x775a,\n 0x2e11, 0x776c, 0x2de2, 0x777e, 0x2db3, 0x7790, 0x2d84, 0x77a2,\n 0x2d55, 0x77b4, 0x2d26, 0x77c6, 0x2cf7, 0x77d8, 0x2cc8, 0x77e9,\n 0x2c99, 0x77fb, 0x2c6a, 0x780c, 0x2c3b, 0x781e, 0x2c0c, 0x782f,\n 0x2bdc, 0x7840, 0x2bad, 0x7851, 0x2b7e, 0x7863, 0x2b4f, 0x7874,\n 0x2b1f, 0x7885, 0x2af0, 0x7895, 0x2ac1, 0x78a6, 0x2a91, 0x78b7,\n 0x2a62, 0x78c8, 0x2a32, 0x78d8, 0x2a03, 0x78e9, 0x29d3, 0x78f9,\n 0x29a4, 0x790a, 0x2974, 0x791a, 0x2945, 0x792a, 0x2915, 0x793a,\n 0x28e5, 0x794a, 0x28b6, 0x795b, 0x2886, 0x796a, 0x2856, 0x797a,\n 0x2827, 0x798a, 0x27f7, 0x799a, 0x27c7, 0x79aa, 0x2797, 0x79b9,\n 0x2768, 0x79c9, 0x2738, 0x79d8, 0x2708, 0x79e7, 0x26d8, 0x79f7,\n 0x26a8, 0x7a06, 0x2678, 0x7a15, 0x2648, 0x7a24, 0x2618, 0x7a33,\n 0x25e8, 0x7a42, 0x25b8, 0x7a51, 0x2588, 0x7a60, 0x2558, 0x7a6e,\n 0x2528, 0x7a7d, 0x24f8, 0x7a8c, 0x24c8, 0x7a9a, 0x2498, 0x7aa8,\n 0x2467, 0x7ab7, 0x2437, 0x7ac5, 0x2407, 0x7ad3, 0x23d7, 0x7ae1,\n 0x23a7, 0x7aef, 0x2376, 0x7afd, 0x2346, 0x7b0b, 0x2316, 0x7b19,\n 0x22e5, 0x7b27, 0x22b5, 0x7b34, 0x2284, 0x7b42, 0x2254, 0x7b50,\n 0x2224, 0x7b5d, 0x21f3, 0x7b6a, 0x21c3, 0x7b78, 0x2192, 0x7b85,\n 0x2162, 0x7b92, 0x2131, 0x7b9f, 0x2101, 0x7bac, 0x20d0, 0x7bb9,\n 0x209f, 0x7bc6, 0x206f, 0x7bd3, 0x203e, 0x7bdf, 0x200e, 0x7bec,\n 0x1fdd, 0x7bf9, 0x1fac, 0x7c05, 0x1f7b, 0x7c11, 0x1f4b, 0x7c1e,\n 0x1f1a, 0x7c2a, 0x1ee9, 0x7c36, 0x1eb8, 0x7c42, 0x1e88, 0x7c4e,\n 0x1e57, 0x7c5a, 0x1e26, 0x7c66, 0x1df5, 0x7c72, 0x1dc4, 0x7c7e,\n 0x1d93, 0x7c89, 0x1d62, 0x7c95, 0x1d31, 0x7ca0, 0x1d01, 0x7cac,\n 0x1cd0, 0x7cb7, 0x1c9f, 0x7cc2, 0x1c6e, 0x7cce, 0x1c3d, 0x7cd9,\n 0x1c0c, 0x7ce4, 0x1bda, 0x7cef, 0x1ba9, 0x7cfa, 0x1b78, 0x7d05,\n 0x1b47, 0x7d0f, 0x1b16, 0x7d1a, 0x1ae5, 0x7d25, 0x1ab4, 0x7d2f,\n 0x1a83, 0x7d3a, 0x1a51, 0x7d44, 0x1a20, 0x7d4e, 0x19ef, 0x7d58,\n 0x19be, 0x7d63, 0x198d, 0x7d6d, 0x195b, 0x7d77, 0x192a, 0x7d81,\n 0x18f9, 0x7d8a, 0x18c7, 0x7d94, 0x1896, 0x7d9e, 0x1865, 0x7da7,\n 0x1833, 0x7db1, 0x1802, 0x7dba, 0x17d1, 0x7dc4, 0x179f, 0x7dcd,\n 0x176e, 0x7dd6, 0x173c, 0x7de0, 0x170b, 0x7de9, 0x16da, 0x7df2,\n 0x16a8, 0x7dfb, 0x1677, 0x7e03, 0x1645, 0x7e0c, 0x1614, 0x7e15,\n 0x15e2, 0x7e1e, 0x15b1, 0x7e26, 0x157f, 0x7e2f, 0x154d, 0x7e37,\n 0x151c, 0x7e3f, 0x14ea, 0x7e48, 0x14b9, 0x7e50, 0x1487, 0x7e58,\n 0x1455, 0x7e60, 0x1424, 0x7e68, 0x13f2, 0x7e70, 0x13c1, 0x7e78,\n 0x138f, 0x7e7f, 0x135d, 0x7e87, 0x132b, 0x7e8e, 0x12fa, 0x7e96,\n 0x12c8, 0x7e9d, 0x1296, 0x7ea5, 0x1265, 0x7eac, 0x1233, 0x7eb3,\n 0x1201, 0x7eba, 0x11cf, 0x7ec1, 0x119e, 0x7ec8, 0x116c, 0x7ecf,\n 0x113a, 0x7ed6, 0x1108, 0x7edd, 0x10d6, 0x7ee3, 0x10a4, 0x7eea,\n 0x1073, 0x7ef0, 0x1041, 0x7ef7, 0x100f, 0x7efd, 0xfdd, 0x7f03,\n 0xfab, 0x7f0a, 0xf79, 0x7f10, 0xf47, 0x7f16, 0xf15, 0x7f1c,\n 0xee4, 0x7f22, 0xeb2, 0x7f27, 0xe80, 0x7f2d, 0xe4e, 0x7f33,\n 0xe1c, 0x7f38, 0xdea, 0x7f3e, 0xdb8, 0x7f43, 0xd86, 0x7f49,\n 0xd54, 0x7f4e, 0xd22, 0x7f53, 0xcf0, 0x7f58, 0xcbe, 0x7f5d,\n 0xc8c, 0x7f62, 0xc5a, 0x7f67, 0xc28, 0x7f6c, 0xbf6, 0x7f71,\n 0xbc4, 0x7f75, 0xb92, 0x7f7a, 0xb60, 0x7f7e, 0xb2d, 0x7f83,\n 0xafb, 0x7f87, 0xac9, 0x7f8b, 0xa97, 0x7f90, 0xa65, 0x7f94,\n 0xa33, 0x7f98, 0xa01, 0x7f9c, 0x9cf, 0x7fa0, 0x99d, 0x7fa3,\n 0x96b, 0x7fa7, 0x938, 0x7fab, 0x906, 0x7fae, 0x8d4, 0x7fb2,\n 0x8a2, 0x7fb5, 0x870, 0x7fb9, 0x83e, 0x7fbc, 0x80c, 0x7fbf,\n 0x7d9, 0x7fc2, 0x7a7, 0x7fc5, 0x775, 0x7fc8, 0x743, 0x7fcb,\n 0x711, 0x7fce, 0x6de, 0x7fd1, 0x6ac, 0x7fd3, 0x67a, 0x7fd6,\n 0x648, 0x7fd9, 0x616, 0x7fdb, 0x5e3, 0x7fdd, 0x5b1, 0x7fe0,\n 0x57f, 0x7fe2, 0x54d, 0x7fe4, 0x51b, 0x7fe6, 0x4e8, 0x7fe8,\n 0x4b6, 0x7fea, 0x484, 0x7fec, 0x452, 0x7fed, 0x41f, 0x7fef,\n 0x3ed, 0x7ff1, 0x3bb, 0x7ff2, 0x389, 0x7ff4, 0x356, 0x7ff5,\n 0x324, 0x7ff6, 0x2f2, 0x7ff7, 0x2c0, 0x7ff8, 0x28d, 0x7ff9,\n 0x25b, 0x7ffa, 0x229, 0x7ffb, 0x1f7, 0x7ffc, 0x1c4, 0x7ffd,\n 0x192, 0x7ffe, 0x160, 0x7ffe, 0x12e, 0x7fff, 0xfb, 0x7fff,\n 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32, 0x7fff,\n 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69, 0x7fff,\n 0xff37, 0x7fff, 0xff05, 0x7fff, 0xfed2, 0x7fff, 0xfea0, 0x7ffe,\n 0xfe6e, 0x7ffe, 0xfe3c, 0x7ffd, 0xfe09, 0x7ffc, 0xfdd7, 0x7ffb,\n 0xfda5, 0x7ffa, 0xfd73, 0x7ff9, 0xfd40, 0x7ff8, 0xfd0e, 0x7ff7,\n 0xfcdc, 0x7ff6, 0xfcaa, 0x7ff5, 0xfc77, 0x7ff4, 0xfc45, 0x7ff2,\n 0xfc13, 0x7ff1, 0xfbe1, 0x7fef, 0xfbae, 0x7fed, 0xfb7c, 0x7fec,\n 0xfb4a, 0x7fea, 0xfb18, 0x7fe8, 0xfae5, 0x7fe6, 0xfab3, 0x7fe4,\n 0xfa81, 0x7fe2, 0xfa4f, 0x7fe0, 0xfa1d, 0x7fdd, 0xf9ea, 0x7fdb,\n 0xf9b8, 0x7fd9, 0xf986, 0x7fd6, 0xf954, 0x7fd3, 0xf922, 0x7fd1,\n 0xf8ef, 0x7fce, 0xf8bd, 0x7fcb, 0xf88b, 0x7fc8, 0xf859, 0x7fc5,\n 0xf827, 0x7fc2, 0xf7f4, 0x7fbf, 0xf7c2, 0x7fbc, 0xf790, 0x7fb9,\n 0xf75e, 0x7fb5, 0xf72c, 0x7fb2, 0xf6fa, 0x7fae, 0xf6c8, 0x7fab,\n 0xf695, 0x7fa7, 0xf663, 0x7fa3, 0xf631, 0x7fa0, 0xf5ff, 0x7f9c,\n 0xf5cd, 0x7f98, 0xf59b, 0x7f94, 0xf569, 0x7f90, 0xf537, 0x7f8b,\n 0xf505, 0x7f87, 0xf4d3, 0x7f83, 0xf4a0, 0x7f7e, 0xf46e, 0x7f7a,\n 0xf43c, 0x7f75, 0xf40a, 0x7f71, 0xf3d8, 0x7f6c, 0xf3a6, 0x7f67,\n 0xf374, 0x7f62, 0xf342, 0x7f5d, 0xf310, 0x7f58, 0xf2de, 0x7f53,\n 0xf2ac, 0x7f4e, 0xf27a, 0x7f49, 0xf248, 0x7f43, 0xf216, 0x7f3e,\n 0xf1e4, 0x7f38, 0xf1b2, 0x7f33, 0xf180, 0x7f2d, 0xf14e, 0x7f27,\n 0xf11c, 0x7f22, 0xf0eb, 0x7f1c, 0xf0b9, 0x7f16, 0xf087, 0x7f10,\n 0xf055, 0x7f0a, 0xf023, 0x7f03, 0xeff1, 0x7efd, 0xefbf, 0x7ef7,\n 0xef8d, 0x7ef0, 0xef5c, 0x7eea, 0xef2a, 0x7ee3, 0xeef8, 0x7edd,\n 0xeec6, 0x7ed6, 0xee94, 0x7ecf, 0xee62, 0x7ec8, 0xee31, 0x7ec1,\n 0xedff, 0x7eba, 0xedcd, 0x7eb3, 0xed9b, 0x7eac, 0xed6a, 0x7ea5,\n 0xed38, 0x7e9d, 0xed06, 0x7e96, 0xecd5, 0x7e8e, 0xeca3, 0x7e87,\n 0xec71, 0x7e7f, 0xec3f, 0x7e78, 0xec0e, 0x7e70, 0xebdc, 0x7e68,\n 0xebab, 0x7e60, 0xeb79, 0x7e58, 0xeb47, 0x7e50, 0xeb16, 0x7e48,\n 0xeae4, 0x7e3f, 0xeab3, 0x7e37, 0xea81, 0x7e2f, 0xea4f, 0x7e26,\n 0xea1e, 0x7e1e, 0xe9ec, 0x7e15, 0xe9bb, 0x7e0c, 0xe989, 0x7e03,\n 0xe958, 0x7dfb, 0xe926, 0x7df2, 0xe8f5, 0x7de9, 0xe8c4, 0x7de0,\n 0xe892, 0x7dd6, 0xe861, 0x7dcd, 0xe82f, 0x7dc4, 0xe7fe, 0x7dba,\n 0xe7cd, 0x7db1, 0xe79b, 0x7da7, 0xe76a, 0x7d9e, 0xe739, 0x7d94,\n 0xe707, 0x7d8a, 0xe6d6, 0x7d81, 0xe6a5, 0x7d77, 0xe673, 0x7d6d,\n 0xe642, 0x7d63, 0xe611, 0x7d58, 0xe5e0, 0x7d4e, 0xe5af, 0x7d44,\n 0xe57d, 0x7d3a, 0xe54c, 0x7d2f, 0xe51b, 0x7d25, 0xe4ea, 0x7d1a,\n 0xe4b9, 0x7d0f, 0xe488, 0x7d05, 0xe457, 0x7cfa, 0xe426, 0x7cef,\n 0xe3f4, 0x7ce4, 0xe3c3, 0x7cd9, 0xe392, 0x7cce, 0xe361, 0x7cc2,\n 0xe330, 0x7cb7, 0xe2ff, 0x7cac, 0xe2cf, 0x7ca0, 0xe29e, 0x7c95,\n 0xe26d, 0x7c89, 0xe23c, 0x7c7e, 0xe20b, 0x7c72, 0xe1da, 0x7c66,\n 0xe1a9, 0x7c5a, 0xe178, 0x7c4e, 0xe148, 0x7c42, 0xe117, 0x7c36,\n 0xe0e6, 0x7c2a, 0xe0b5, 0x7c1e, 0xe085, 0x7c11, 0xe054, 0x7c05,\n 0xe023, 0x7bf9, 0xdff2, 0x7bec, 0xdfc2, 0x7bdf, 0xdf91, 0x7bd3,\n 0xdf61, 0x7bc6, 0xdf30, 0x7bb9, 0xdeff, 0x7bac, 0xdecf, 0x7b9f,\n 0xde9e, 0x7b92, 0xde6e, 0x7b85, 0xde3d, 0x7b78, 0xde0d, 0x7b6a,\n 0xdddc, 0x7b5d, 0xddac, 0x7b50, 0xdd7c, 0x7b42, 0xdd4b, 0x7b34,\n 0xdd1b, 0x7b27, 0xdcea, 0x7b19, 0xdcba, 0x7b0b, 0xdc8a, 0x7afd,\n 0xdc59, 0x7aef, 0xdc29, 0x7ae1, 0xdbf9, 0x7ad3, 0xdbc9, 0x7ac5,\n 0xdb99, 0x7ab7, 0xdb68, 0x7aa8, 0xdb38, 0x7a9a, 0xdb08, 0x7a8c,\n 0xdad8, 0x7a7d, 0xdaa8, 0x7a6e, 0xda78, 0x7a60, 0xda48, 0x7a51,\n 0xda18, 0x7a42, 0xd9e8, 0x7a33, 0xd9b8, 0x7a24, 0xd988, 0x7a15,\n 0xd958, 0x7a06, 0xd928, 0x79f7, 0xd8f8, 0x79e7, 0xd8c8, 0x79d8,\n 0xd898, 0x79c9, 0xd869, 0x79b9, 0xd839, 0x79aa, 0xd809, 0x799a,\n 0xd7d9, 0x798a, 0xd7aa, 0x797a, 0xd77a, 0x796a, 0xd74a, 0x795b,\n 0xd71b, 0x794a, 0xd6eb, 0x793a, 0xd6bb, 0x792a, 0xd68c, 0x791a,\n 0xd65c, 0x790a, 0xd62d, 0x78f9, 0xd5fd, 0x78e9, 0xd5ce, 0x78d8,\n 0xd59e, 0x78c8, 0xd56f, 0x78b7, 0xd53f, 0x78a6, 0xd510, 0x7895,\n 0xd4e1, 0x7885, 0xd4b1, 0x7874, 0xd482, 0x7863, 0xd453, 0x7851,\n 0xd424, 0x7840, 0xd3f4, 0x782f, 0xd3c5, 0x781e, 0xd396, 0x780c,\n 0xd367, 0x77fb, 0xd338, 0x77e9, 0xd309, 0x77d8, 0xd2da, 0x77c6,\n 0xd2ab, 0x77b4, 0xd27c, 0x77a2, 0xd24d, 0x7790, 0xd21e, 0x777e,\n 0xd1ef, 0x776c, 0xd1c0, 0x775a, 0xd191, 0x7748, 0xd162, 0x7736,\n 0xd134, 0x7723, 0xd105, 0x7711, 0xd0d6, 0x76fe, 0xd0a7, 0x76ec,\n 0xd079, 0x76d9, 0xd04a, 0x76c7, 0xd01b, 0x76b4, 0xcfed, 0x76a1,\n 0xcfbe, 0x768e, 0xcf90, 0x767b, 0xcf61, 0x7668, 0xcf33, 0x7655,\n 0xcf04, 0x7642, 0xced6, 0x762e, 0xcea7, 0x761b, 0xce79, 0x7608,\n 0xce4b, 0x75f4, 0xce1c, 0x75e1, 0xcdee, 0x75cd, 0xcdc0, 0x75b9,\n 0xcd92, 0x75a6, 0xcd63, 0x7592, 0xcd35, 0x757e, 0xcd07, 0x756a,\n 0xccd9, 0x7556, 0xccab, 0x7542, 0xcc7d, 0x752d, 0xcc4f, 0x7519,\n 0xcc21, 0x7505, 0xcbf3, 0x74f0, 0xcbc5, 0x74dc, 0xcb97, 0x74c7,\n 0xcb69, 0x74b3, 0xcb3c, 0x749e, 0xcb0e, 0x7489, 0xcae0, 0x7475,\n 0xcab2, 0x7460, 0xca85, 0x744b, 0xca57, 0x7436, 0xca29, 0x7421,\n 0xc9fc, 0x740b, 0xc9ce, 0x73f6, 0xc9a1, 0x73e1, 0xc973, 0x73cb,\n 0xc946, 0x73b6, 0xc918, 0x73a0, 0xc8eb, 0x738b, 0xc8be, 0x7375,\n 0xc890, 0x735f, 0xc863, 0x734a, 0xc836, 0x7334, 0xc809, 0x731e,\n 0xc7db, 0x7308, 0xc7ae, 0x72f2, 0xc781, 0x72dc, 0xc754, 0x72c5,\n 0xc727, 0x72af, 0xc6fa, 0x7299, 0xc6cd, 0x7282, 0xc6a0, 0x726c,\n 0xc673, 0x7255, 0xc646, 0x723f, 0xc619, 0x7228, 0xc5ed, 0x7211,\n 0xc5c0, 0x71fa, 0xc593, 0x71e3, 0xc566, 0x71cc, 0xc53a, 0x71b5,\n 0xc50d, 0x719e, 0xc4e0, 0x7187, 0xc4b4, 0x7170, 0xc487, 0x7158,\n 0xc45b, 0x7141, 0xc42e, 0x712a, 0xc402, 0x7112, 0xc3d6, 0x70fa,\n 0xc3a9, 0x70e3, 0xc37d, 0x70cb, 0xc351, 0x70b3, 0xc324, 0x709b,\n 0xc2f8, 0x7083, 0xc2cc, 0x706b, 0xc2a0, 0x7053, 0xc274, 0x703b,\n 0xc248, 0x7023, 0xc21c, 0x700b, 0xc1f0, 0x6ff2, 0xc1c4, 0x6fda,\n 0xc198, 0x6fc2, 0xc16c, 0x6fa9, 0xc140, 0x6f90, 0xc114, 0x6f78,\n 0xc0e9, 0x6f5f, 0xc0bd, 0x6f46, 0xc091, 0x6f2d, 0xc066, 0x6f14,\n 0xc03a, 0x6efb, 0xc00f, 0x6ee2, 0xbfe3, 0x6ec9, 0xbfb8, 0x6eb0,\n 0xbf8c, 0x6e97, 0xbf61, 0x6e7d, 0xbf35, 0x6e64, 0xbf0a, 0x6e4a,\n 0xbedf, 0x6e31, 0xbeb3, 0x6e17, 0xbe88, 0x6dfe, 0xbe5d, 0x6de4,\n 0xbe32, 0x6dca, 0xbe07, 0x6db0, 0xbddc, 0x6d96, 0xbdb1, 0x6d7c,\n 0xbd86, 0x6d62, 0xbd5b, 0x6d48, 0xbd30, 0x6d2e, 0xbd05, 0x6d14,\n 0xbcda, 0x6cf9, 0xbcaf, 0x6cdf, 0xbc85, 0x6cc4, 0xbc5a, 0x6caa,\n 0xbc2f, 0x6c8f, 0xbc05, 0x6c75, 0xbbda, 0x6c5a, 0xbbb0, 0x6c3f,\n 0xbb85, 0x6c24, 0xbb5b, 0x6c09, 0xbb30, 0x6bee, 0xbb06, 0x6bd3,\n 0xbadc, 0x6bb8, 0xbab1, 0x6b9d, 0xba87, 0x6b82, 0xba5d, 0x6b66,\n 0xba33, 0x6b4b, 0xba09, 0x6b30, 0xb9df, 0x6b14, 0xb9b5, 0x6af8,\n 0xb98b, 0x6add, 0xb961, 0x6ac1, 0xb937, 0x6aa5, 0xb90d, 0x6a89,\n 0xb8e3, 0x6a6e, 0xb8b9, 0x6a52, 0xb890, 0x6a36, 0xb866, 0x6a1a,\n 0xb83c, 0x69fd, 0xb813, 0x69e1, 0xb7e9, 0x69c5, 0xb7c0, 0x69a9,\n 0xb796, 0x698c, 0xb76d, 0x6970, 0xb743, 0x6953, 0xb71a, 0x6937,\n 0xb6f1, 0x691a, 0xb6c7, 0x68fd, 0xb69e, 0x68e0, 0xb675, 0x68c4,\n 0xb64c, 0x68a7, 0xb623, 0x688a, 0xb5fa, 0x686d, 0xb5d1, 0x6850,\n 0xb5a8, 0x6832, 0xb57f, 0x6815, 0xb556, 0x67f8, 0xb52d, 0x67da,\n 0xb505, 0x67bd, 0xb4dc, 0x67a0, 0xb4b3, 0x6782, 0xb48b, 0x6764,\n 0xb462, 0x6747, 0xb439, 0x6729, 0xb411, 0x670b, 0xb3e9, 0x66ed,\n 0xb3c0, 0x66d0, 0xb398, 0x66b2, 0xb36f, 0x6693, 0xb347, 0x6675,\n 0xb31f, 0x6657, 0xb2f7, 0x6639, 0xb2cf, 0x661b, 0xb2a7, 0x65fc,\n 0xb27f, 0x65de, 0xb257, 0x65c0, 0xb22f, 0x65a1, 0xb207, 0x6582,\n 0xb1df, 0x6564, 0xb1b7, 0x6545, 0xb18f, 0x6526, 0xb168, 0x6507,\n 0xb140, 0x64e9, 0xb118, 0x64ca, 0xb0f1, 0x64ab, 0xb0c9, 0x648b,\n 0xb0a2, 0x646c, 0xb07b, 0x644d, 0xb053, 0x642e, 0xb02c, 0x640f,\n 0xb005, 0x63ef, 0xafdd, 0x63d0, 0xafb6, 0x63b0, 0xaf8f, 0x6391,\n 0xaf68, 0x6371, 0xaf41, 0x6351, 0xaf1a, 0x6332, 0xaef3, 0x6312,\n 0xaecc, 0x62f2, 0xaea5, 0x62d2, 0xae7f, 0x62b2, 0xae58, 0x6292,\n 0xae31, 0x6272, 0xae0b, 0x6252, 0xade4, 0x6232, 0xadbd, 0x6211,\n 0xad97, 0x61f1, 0xad70, 0x61d1, 0xad4a, 0x61b0, 0xad24, 0x6190,\n 0xacfd, 0x616f, 0xacd7, 0x614e, 0xacb1, 0x612e, 0xac8b, 0x610d,\n 0xac65, 0x60ec, 0xac3f, 0x60cb, 0xac19, 0x60aa, 0xabf3, 0x6089,\n 0xabcd, 0x6068, 0xaba7, 0x6047, 0xab81, 0x6026, 0xab5c, 0x6005,\n 0xab36, 0x5fe4, 0xab10, 0x5fc2, 0xaaeb, 0x5fa1, 0xaac5, 0x5f80,\n 0xaaa0, 0x5f5e, 0xaa7a, 0x5f3c, 0xaa55, 0x5f1b, 0xaa30, 0x5ef9,\n 0xaa0a, 0x5ed7, 0xa9e5, 0x5eb6, 0xa9c0, 0x5e94, 0xa99b, 0x5e72,\n 0xa976, 0x5e50, 0xa951, 0x5e2e, 0xa92c, 0x5e0c, 0xa907, 0x5dea,\n 0xa8e2, 0x5dc8, 0xa8bd, 0x5da5, 0xa899, 0x5d83, 0xa874, 0x5d61,\n 0xa84f, 0x5d3e, 0xa82b, 0x5d1c, 0xa806, 0x5cf9, 0xa7e2, 0x5cd7,\n 0xa7bd, 0x5cb4, 0xa799, 0x5c91, 0xa774, 0x5c6f, 0xa750, 0x5c4c,\n 0xa72c, 0x5c29, 0xa708, 0x5c06, 0xa6e4, 0x5be3, 0xa6c0, 0x5bc0,\n 0xa69c, 0x5b9d, 0xa678, 0x5b7a, 0xa654, 0x5b57, 0xa630, 0x5b34,\n 0xa60c, 0x5b10, 0xa5e8, 0x5aed, 0xa5c5, 0x5ac9, 0xa5a1, 0x5aa6,\n 0xa57e, 0x5a82, 0xa55a, 0x5a5f, 0xa537, 0x5a3b, 0xa513, 0x5a18,\n 0xa4f0, 0x59f4, 0xa4cc, 0x59d0, 0xa4a9, 0x59ac, 0xa486, 0x5988,\n 0xa463, 0x5964, 0xa440, 0x5940, 0xa41d, 0x591c, 0xa3fa, 0x58f8,\n 0xa3d7, 0x58d4, 0xa3b4, 0x58b0, 0xa391, 0x588c, 0xa36f, 0x5867,\n 0xa34c, 0x5843, 0xa329, 0x581e, 0xa307, 0x57fa, 0xa2e4, 0x57d5,\n 0xa2c2, 0x57b1, 0xa29f, 0x578c, 0xa27d, 0x5767, 0xa25b, 0x5743,\n 0xa238, 0x571e, 0xa216, 0x56f9, 0xa1f4, 0x56d4, 0xa1d2, 0x56af,\n 0xa1b0, 0x568a, 0xa18e, 0x5665, 0xa16c, 0x5640, 0xa14a, 0x561b,\n 0xa129, 0x55f6, 0xa107, 0x55d0, 0xa0e5, 0x55ab, 0xa0c4, 0x5586,\n 0xa0a2, 0x5560, 0xa080, 0x553b, 0xa05f, 0x5515, 0xa03e, 0x54f0,\n 0xa01c, 0x54ca, 0x9ffb, 0x54a4, 0x9fda, 0x547f, 0x9fb9, 0x5459,\n 0x9f98, 0x5433, 0x9f77, 0x540d, 0x9f56, 0x53e7, 0x9f35, 0x53c1,\n 0x9f14, 0x539b, 0x9ef3, 0x5375, 0x9ed2, 0x534f, 0x9eb2, 0x5329,\n 0x9e91, 0x5303, 0x9e70, 0x52dc, 0x9e50, 0x52b6, 0x9e2f, 0x5290,\n 0x9e0f, 0x5269, 0x9def, 0x5243, 0x9dce, 0x521c, 0x9dae, 0x51f5,\n 0x9d8e, 0x51cf, 0x9d6e, 0x51a8, 0x9d4e, 0x5181, 0x9d2e, 0x515b,\n 0x9d0e, 0x5134, 0x9cee, 0x510d, 0x9cce, 0x50e6, 0x9caf, 0x50bf,\n 0x9c8f, 0x5098, 0x9c6f, 0x5071, 0x9c50, 0x504a, 0x9c30, 0x5023,\n 0x9c11, 0x4ffb, 0x9bf1, 0x4fd4, 0x9bd2, 0x4fad, 0x9bb3, 0x4f85,\n 0x9b94, 0x4f5e, 0x9b75, 0x4f37, 0x9b55, 0x4f0f, 0x9b36, 0x4ee8,\n 0x9b17, 0x4ec0, 0x9af9, 0x4e98, 0x9ada, 0x4e71, 0x9abb, 0x4e49,\n 0x9a9c, 0x4e21, 0x9a7e, 0x4df9, 0x9a5f, 0x4dd1, 0x9a40, 0x4da9,\n 0x9a22, 0x4d81, 0x9a04, 0x4d59, 0x99e5, 0x4d31, 0x99c7, 0x4d09,\n 0x99a9, 0x4ce1, 0x998b, 0x4cb9, 0x996d, 0x4c91, 0x994e, 0x4c68,\n 0x9930, 0x4c40, 0x9913, 0x4c17, 0x98f5, 0x4bef, 0x98d7, 0x4bc7,\n 0x98b9, 0x4b9e, 0x989c, 0x4b75, 0x987e, 0x4b4d, 0x9860, 0x4b24,\n 0x9843, 0x4afb, 0x9826, 0x4ad3, 0x9808, 0x4aaa, 0x97eb, 0x4a81,\n 0x97ce, 0x4a58, 0x97b0, 0x4a2f, 0x9793, 0x4a06, 0x9776, 0x49dd,\n 0x9759, 0x49b4, 0x973c, 0x498b, 0x9720, 0x4962, 0x9703, 0x4939,\n 0x96e6, 0x490f, 0x96c9, 0x48e6, 0x96ad, 0x48bd, 0x9690, 0x4893,\n 0x9674, 0x486a, 0x9657, 0x4840, 0x963b, 0x4817, 0x961f, 0x47ed,\n 0x9603, 0x47c4, 0x95e6, 0x479a, 0x95ca, 0x4770, 0x95ae, 0x4747,\n 0x9592, 0x471d, 0x9577, 0x46f3, 0x955b, 0x46c9, 0x953f, 0x469f,\n 0x9523, 0x4675, 0x9508, 0x464b, 0x94ec, 0x4621, 0x94d0, 0x45f7,\n 0x94b5, 0x45cd, 0x949a, 0x45a3, 0x947e, 0x4579, 0x9463, 0x454f,\n 0x9448, 0x4524, 0x942d, 0x44fa, 0x9412, 0x44d0, 0x93f7, 0x44a5,\n 0x93dc, 0x447b, 0x93c1, 0x4450, 0x93a6, 0x4426, 0x938b, 0x43fb,\n 0x9371, 0x43d1, 0x9356, 0x43a6, 0x933c, 0x437b, 0x9321, 0x4351,\n 0x9307, 0x4326, 0x92ec, 0x42fb, 0x92d2, 0x42d0, 0x92b8, 0x42a5,\n 0x929e, 0x427a, 0x9284, 0x424f, 0x926a, 0x4224, 0x9250, 0x41f9,\n 0x9236, 0x41ce, 0x921c, 0x41a3, 0x9202, 0x4178, 0x91e9, 0x414d,\n 0x91cf, 0x4121, 0x91b6, 0x40f6, 0x919c, 0x40cb, 0x9183, 0x409f,\n 0x9169, 0x4074, 0x9150, 0x4048, 0x9137, 0x401d, 0x911e, 0x3ff1,\n 0x9105, 0x3fc6, 0x90ec, 0x3f9a, 0x90d3, 0x3f6f, 0x90ba, 0x3f43,\n 0x90a1, 0x3f17, 0x9088, 0x3eec, 0x9070, 0x3ec0, 0x9057, 0x3e94,\n 0x903e, 0x3e68, 0x9026, 0x3e3c, 0x900e, 0x3e10, 0x8ff5, 0x3de4,\n 0x8fdd, 0x3db8, 0x8fc5, 0x3d8c, 0x8fad, 0x3d60, 0x8f95, 0x3d34,\n 0x8f7d, 0x3d08, 0x8f65, 0x3cdc, 0x8f4d, 0x3caf, 0x8f35, 0x3c83,\n 0x8f1d, 0x3c57, 0x8f06, 0x3c2a, 0x8eee, 0x3bfe, 0x8ed6, 0x3bd2,\n 0x8ebf, 0x3ba5, 0x8ea8, 0x3b79, 0x8e90, 0x3b4c, 0x8e79, 0x3b20,\n 0x8e62, 0x3af3, 0x8e4b, 0x3ac6, 0x8e34, 0x3a9a, 0x8e1d, 0x3a6d,\n 0x8e06, 0x3a40, 0x8def, 0x3a13, 0x8dd8, 0x39e7, 0x8dc1, 0x39ba,\n 0x8dab, 0x398d, 0x8d94, 0x3960, 0x8d7e, 0x3933, 0x8d67, 0x3906,\n 0x8d51, 0x38d9, 0x8d3b, 0x38ac, 0x8d24, 0x387f, 0x8d0e, 0x3852,\n 0x8cf8, 0x3825, 0x8ce2, 0x37f7, 0x8ccc, 0x37ca, 0x8cb6, 0x379d,\n 0x8ca1, 0x3770, 0x8c8b, 0x3742, 0x8c75, 0x3715, 0x8c60, 0x36e8,\n 0x8c4a, 0x36ba, 0x8c35, 0x368d, 0x8c1f, 0x365f, 0x8c0a, 0x3632,\n 0x8bf5, 0x3604, 0x8bdf, 0x35d7, 0x8bca, 0x35a9, 0x8bb5, 0x357b,\n 0x8ba0, 0x354e, 0x8b8b, 0x3520, 0x8b77, 0x34f2, 0x8b62, 0x34c4,\n 0x8b4d, 0x3497, 0x8b39, 0x3469, 0x8b24, 0x343b, 0x8b10, 0x340d,\n 0x8afb, 0x33df, 0x8ae7, 0x33b1, 0x8ad3, 0x3383, 0x8abe, 0x3355,\n 0x8aaa, 0x3327, 0x8a96, 0x32f9, 0x8a82, 0x32cb, 0x8a6e, 0x329d,\n 0x8a5a, 0x326e, 0x8a47, 0x3240, 0x8a33, 0x3212, 0x8a1f, 0x31e4,\n 0x8a0c, 0x31b5, 0x89f8, 0x3187, 0x89e5, 0x3159, 0x89d2, 0x312a,\n 0x89be, 0x30fc, 0x89ab, 0x30cd, 0x8998, 0x309f, 0x8985, 0x3070,\n 0x8972, 0x3042, 0x895f, 0x3013, 0x894c, 0x2fe5, 0x8939, 0x2fb6,\n 0x8927, 0x2f87, 0x8914, 0x2f59, 0x8902, 0x2f2a, 0x88ef, 0x2efb,\n 0x88dd, 0x2ecc, 0x88ca, 0x2e9e, 0x88b8, 0x2e6f, 0x88a6, 0x2e40,\n 0x8894, 0x2e11, 0x8882, 0x2de2, 0x8870, 0x2db3, 0x885e, 0x2d84,\n 0x884c, 0x2d55, 0x883a, 0x2d26, 0x8828, 0x2cf7, 0x8817, 0x2cc8,\n 0x8805, 0x2c99, 0x87f4, 0x2c6a, 0x87e2, 0x2c3b, 0x87d1, 0x2c0c,\n 0x87c0, 0x2bdc, 0x87af, 0x2bad, 0x879d, 0x2b7e, 0x878c, 0x2b4f,\n 0x877b, 0x2b1f, 0x876b, 0x2af0, 0x875a, 0x2ac1, 0x8749, 0x2a91,\n 0x8738, 0x2a62, 0x8728, 0x2a32, 0x8717, 0x2a03, 0x8707, 0x29d3,\n 0x86f6, 0x29a4, 0x86e6, 0x2974, 0x86d6, 0x2945, 0x86c6, 0x2915,\n 0x86b6, 0x28e5, 0x86a5, 0x28b6, 0x8696, 0x2886, 0x8686, 0x2856,\n 0x8676, 0x2827, 0x8666, 0x27f7, 0x8656, 0x27c7, 0x8647, 0x2797,\n 0x8637, 0x2768, 0x8628, 0x2738, 0x8619, 0x2708, 0x8609, 0x26d8,\n 0x85fa, 0x26a8, 0x85eb, 0x2678, 0x85dc, 0x2648, 0x85cd, 0x2618,\n 0x85be, 0x25e8, 0x85af, 0x25b8, 0x85a0, 0x2588, 0x8592, 0x2558,\n 0x8583, 0x2528, 0x8574, 0x24f8, 0x8566, 0x24c8, 0x8558, 0x2498,\n 0x8549, 0x2467, 0x853b, 0x2437, 0x852d, 0x2407, 0x851f, 0x23d7,\n 0x8511, 0x23a7, 0x8503, 0x2376, 0x84f5, 0x2346, 0x84e7, 0x2316,\n 0x84d9, 0x22e5, 0x84cc, 0x22b5, 0x84be, 0x2284, 0x84b0, 0x2254,\n 0x84a3, 0x2224, 0x8496, 0x21f3, 0x8488, 0x21c3, 0x847b, 0x2192,\n 0x846e, 0x2162, 0x8461, 0x2131, 0x8454, 0x2101, 0x8447, 0x20d0,\n 0x843a, 0x209f, 0x842d, 0x206f, 0x8421, 0x203e, 0x8414, 0x200e,\n 0x8407, 0x1fdd, 0x83fb, 0x1fac, 0x83ef, 0x1f7b, 0x83e2, 0x1f4b,\n 0x83d6, 0x1f1a, 0x83ca, 0x1ee9, 0x83be, 0x1eb8, 0x83b2, 0x1e88,\n 0x83a6, 0x1e57, 0x839a, 0x1e26, 0x838e, 0x1df5, 0x8382, 0x1dc4,\n 0x8377, 0x1d93, 0x836b, 0x1d62, 0x8360, 0x1d31, 0x8354, 0x1d01,\n 0x8349, 0x1cd0, 0x833e, 0x1c9f, 0x8332, 0x1c6e, 0x8327, 0x1c3d,\n 0x831c, 0x1c0c, 0x8311, 0x1bda, 0x8306, 0x1ba9, 0x82fb, 0x1b78,\n 0x82f1, 0x1b47, 0x82e6, 0x1b16, 0x82db, 0x1ae5, 0x82d1, 0x1ab4,\n 0x82c6, 0x1a83, 0x82bc, 0x1a51, 0x82b2, 0x1a20, 0x82a8, 0x19ef,\n 0x829d, 0x19be, 0x8293, 0x198d, 0x8289, 0x195b, 0x827f, 0x192a,\n 0x8276, 0x18f9, 0x826c, 0x18c7, 0x8262, 0x1896, 0x8259, 0x1865,\n 0x824f, 0x1833, 0x8246, 0x1802, 0x823c, 0x17d1, 0x8233, 0x179f,\n 0x822a, 0x176e, 0x8220, 0x173c, 0x8217, 0x170b, 0x820e, 0x16da,\n 0x8205, 0x16a8, 0x81fd, 0x1677, 0x81f4, 0x1645, 0x81eb, 0x1614,\n 0x81e2, 0x15e2, 0x81da, 0x15b1, 0x81d1, 0x157f, 0x81c9, 0x154d,\n 0x81c1, 0x151c, 0x81b8, 0x14ea, 0x81b0, 0x14b9, 0x81a8, 0x1487,\n 0x81a0, 0x1455, 0x8198, 0x1424, 0x8190, 0x13f2, 0x8188, 0x13c1,\n 0x8181, 0x138f, 0x8179, 0x135d, 0x8172, 0x132b, 0x816a, 0x12fa,\n 0x8163, 0x12c8, 0x815b, 0x1296, 0x8154, 0x1265, 0x814d, 0x1233,\n 0x8146, 0x1201, 0x813f, 0x11cf, 0x8138, 0x119e, 0x8131, 0x116c,\n 0x812a, 0x113a, 0x8123, 0x1108, 0x811d, 0x10d6, 0x8116, 0x10a4,\n 0x8110, 0x1073, 0x8109, 0x1041, 0x8103, 0x100f, 0x80fd, 0xfdd,\n 0x80f6, 0xfab, 0x80f0, 0xf79, 0x80ea, 0xf47, 0x80e4, 0xf15,\n 0x80de, 0xee4, 0x80d9, 0xeb2, 0x80d3, 0xe80, 0x80cd, 0xe4e,\n 0x80c8, 0xe1c, 0x80c2, 0xdea, 0x80bd, 0xdb8, 0x80b7, 0xd86,\n 0x80b2, 0xd54, 0x80ad, 0xd22, 0x80a8, 0xcf0, 0x80a3, 0xcbe,\n 0x809e, 0xc8c, 0x8099, 0xc5a, 0x8094, 0xc28, 0x808f, 0xbf6,\n 0x808b, 0xbc4, 0x8086, 0xb92, 0x8082, 0xb60, 0x807d, 0xb2d,\n 0x8079, 0xafb, 0x8075, 0xac9, 0x8070, 0xa97, 0x806c, 0xa65,\n 0x8068, 0xa33, 0x8064, 0xa01, 0x8060, 0x9cf, 0x805d, 0x99d,\n 0x8059, 0x96b, 0x8055, 0x938, 0x8052, 0x906, 0x804e, 0x8d4,\n 0x804b, 0x8a2, 0x8047, 0x870, 0x8044, 0x83e, 0x8041, 0x80c,\n 0x803e, 0x7d9, 0x803b, 0x7a7, 0x8038, 0x775, 0x8035, 0x743,\n 0x8032, 0x711, 0x802f, 0x6de, 0x802d, 0x6ac, 0x802a, 0x67a,\n 0x8027, 0x648, 0x8025, 0x616, 0x8023, 0x5e3, 0x8020, 0x5b1,\n 0x801e, 0x57f, 0x801c, 0x54d, 0x801a, 0x51b, 0x8018, 0x4e8,\n 0x8016, 0x4b6, 0x8014, 0x484, 0x8013, 0x452, 0x8011, 0x41f,\n 0x800f, 0x3ed, 0x800e, 0x3bb, 0x800c, 0x389, 0x800b, 0x356,\n 0x800a, 0x324, 0x8009, 0x2f2, 0x8008, 0x2c0, 0x8007, 0x28d,\n 0x8006, 0x25b, 0x8005, 0x229, 0x8004, 0x1f7, 0x8003, 0x1c4,\n 0x8002, 0x192, 0x8002, 0x160, 0x8001, 0x12e, 0x8001, 0xfb,\n 0x8001, 0xc9, 0x8000, 0x97, 0x8000, 0x65, 0x8000, 0x32,\n 0x8000, 0x0, 0x8000, 0xffce, 0x8000, 0xff9b, 0x8000, 0xff69,\n 0x8001, 0xff37, 0x8001, 0xff05, 0x8001, 0xfed2, 0x8002, 0xfea0,\n 0x8002, 0xfe6e, 0x8003, 0xfe3c, 0x8004, 0xfe09, 0x8005, 0xfdd7,\n 0x8006, 0xfda5, 0x8007, 0xfd73, 0x8008, 0xfd40, 0x8009, 0xfd0e,\n 0x800a, 0xfcdc, 0x800b, 0xfcaa, 0x800c, 0xfc77, 0x800e, 0xfc45,\n 0x800f, 0xfc13, 0x8011, 0xfbe1, 0x8013, 0xfbae, 0x8014, 0xfb7c,\n 0x8016, 0xfb4a, 0x8018, 0xfb18, 0x801a, 0xfae5, 0x801c, 0xfab3,\n 0x801e, 0xfa81, 0x8020, 0xfa4f, 0x8023, 0xfa1d, 0x8025, 0xf9ea,\n 0x8027, 0xf9b8, 0x802a, 0xf986, 0x802d, 0xf954, 0x802f, 0xf922,\n 0x8032, 0xf8ef, 0x8035, 0xf8bd, 0x8038, 0xf88b, 0x803b, 0xf859,\n 0x803e, 0xf827, 0x8041, 0xf7f4, 0x8044, 0xf7c2, 0x8047, 0xf790,\n 0x804b, 0xf75e, 0x804e, 0xf72c, 0x8052, 0xf6fa, 0x8055, 0xf6c8,\n 0x8059, 0xf695, 0x805d, 0xf663, 0x8060, 0xf631, 0x8064, 0xf5ff,\n 0x8068, 0xf5cd, 0x806c, 0xf59b, 0x8070, 0xf569, 0x8075, 0xf537,\n 0x8079, 0xf505, 0x807d, 0xf4d3, 0x8082, 0xf4a0, 0x8086, 0xf46e,\n 0x808b, 0xf43c, 0x808f, 0xf40a, 0x8094, 0xf3d8, 0x8099, 0xf3a6,\n 0x809e, 0xf374, 0x80a3, 0xf342, 0x80a8, 0xf310, 0x80ad, 0xf2de,\n 0x80b2, 0xf2ac, 0x80b7, 0xf27a, 0x80bd, 0xf248, 0x80c2, 0xf216,\n 0x80c8, 0xf1e4, 0x80cd, 0xf1b2, 0x80d3, 0xf180, 0x80d9, 0xf14e,\n 0x80de, 0xf11c, 0x80e4, 0xf0eb, 0x80ea, 0xf0b9, 0x80f0, 0xf087,\n 0x80f6, 0xf055, 0x80fd, 0xf023, 0x8103, 0xeff1, 0x8109, 0xefbf,\n 0x8110, 0xef8d, 0x8116, 0xef5c, 0x811d, 0xef2a, 0x8123, 0xeef8,\n 0x812a, 0xeec6, 0x8131, 0xee94, 0x8138, 0xee62, 0x813f, 0xee31,\n 0x8146, 0xedff, 0x814d, 0xedcd, 0x8154, 0xed9b, 0x815b, 0xed6a,\n 0x8163, 0xed38, 0x816a, 0xed06, 0x8172, 0xecd5, 0x8179, 0xeca3,\n 0x8181, 0xec71, 0x8188, 0xec3f, 0x8190, 0xec0e, 0x8198, 0xebdc,\n 0x81a0, 0xebab, 0x81a8, 0xeb79, 0x81b0, 0xeb47, 0x81b8, 0xeb16,\n 0x81c1, 0xeae4, 0x81c9, 0xeab3, 0x81d1, 0xea81, 0x81da, 0xea4f,\n 0x81e2, 0xea1e, 0x81eb, 0xe9ec, 0x81f4, 0xe9bb, 0x81fd, 0xe989,\n 0x8205, 0xe958, 0x820e, 0xe926, 0x8217, 0xe8f5, 0x8220, 0xe8c4,\n 0x822a, 0xe892, 0x8233, 0xe861, 0x823c, 0xe82f, 0x8246, 0xe7fe,\n 0x824f, 0xe7cd, 0x8259, 0xe79b, 0x8262, 0xe76a, 0x826c, 0xe739,\n 0x8276, 0xe707, 0x827f, 0xe6d6, 0x8289, 0xe6a5, 0x8293, 0xe673,\n 0x829d, 0xe642, 0x82a8, 0xe611, 0x82b2, 0xe5e0, 0x82bc, 0xe5af,\n 0x82c6, 0xe57d, 0x82d1, 0xe54c, 0x82db, 0xe51b, 0x82e6, 0xe4ea,\n 0x82f1, 0xe4b9, 0x82fb, 0xe488, 0x8306, 0xe457, 0x8311, 0xe426,\n 0x831c, 0xe3f4, 0x8327, 0xe3c3, 0x8332, 0xe392, 0x833e, 0xe361,\n 0x8349, 0xe330, 0x8354, 0xe2ff, 0x8360, 0xe2cf, 0x836b, 0xe29e,\n 0x8377, 0xe26d, 0x8382, 0xe23c, 0x838e, 0xe20b, 0x839a, 0xe1da,\n 0x83a6, 0xe1a9, 0x83b2, 0xe178, 0x83be, 0xe148, 0x83ca, 0xe117,\n 0x83d6, 0xe0e6, 0x83e2, 0xe0b5, 0x83ef, 0xe085, 0x83fb, 0xe054,\n 0x8407, 0xe023, 0x8414, 0xdff2, 0x8421, 0xdfc2, 0x842d, 0xdf91,\n 0x843a, 0xdf61, 0x8447, 0xdf30, 0x8454, 0xdeff, 0x8461, 0xdecf,\n 0x846e, 0xde9e, 0x847b, 0xde6e, 0x8488, 0xde3d, 0x8496, 0xde0d,\n 0x84a3, 0xdddc, 0x84b0, 0xddac, 0x84be, 0xdd7c, 0x84cc, 0xdd4b,\n 0x84d9, 0xdd1b, 0x84e7, 0xdcea, 0x84f5, 0xdcba, 0x8503, 0xdc8a,\n 0x8511, 0xdc59, 0x851f, 0xdc29, 0x852d, 0xdbf9, 0x853b, 0xdbc9,\n 0x8549, 0xdb99, 0x8558, 0xdb68, 0x8566, 0xdb38, 0x8574, 0xdb08,\n 0x8583, 0xdad8, 0x8592, 0xdaa8, 0x85a0, 0xda78, 0x85af, 0xda48,\n 0x85be, 0xda18, 0x85cd, 0xd9e8, 0x85dc, 0xd9b8, 0x85eb, 0xd988,\n 0x85fa, 0xd958, 0x8609, 0xd928, 0x8619, 0xd8f8, 0x8628, 0xd8c8,\n 0x8637, 0xd898, 0x8647, 0xd869, 0x8656, 0xd839, 0x8666, 0xd809,\n 0x8676, 0xd7d9, 0x8686, 0xd7aa, 0x8696, 0xd77a, 0x86a5, 0xd74a,\n 0x86b6, 0xd71b, 0x86c6, 0xd6eb, 0x86d6, 0xd6bb, 0x86e6, 0xd68c,\n 0x86f6, 0xd65c, 0x8707, 0xd62d, 0x8717, 0xd5fd, 0x8728, 0xd5ce,\n 0x8738, 0xd59e, 0x8749, 0xd56f, 0x875a, 0xd53f, 0x876b, 0xd510,\n 0x877b, 0xd4e1, 0x878c, 0xd4b1, 0x879d, 0xd482, 0x87af, 0xd453,\n 0x87c0, 0xd424, 0x87d1, 0xd3f4, 0x87e2, 0xd3c5, 0x87f4, 0xd396,\n 0x8805, 0xd367, 0x8817, 0xd338, 0x8828, 0xd309, 0x883a, 0xd2da,\n 0x884c, 0xd2ab, 0x885e, 0xd27c, 0x8870, 0xd24d, 0x8882, 0xd21e,\n 0x8894, 0xd1ef, 0x88a6, 0xd1c0, 0x88b8, 0xd191, 0x88ca, 0xd162,\n 0x88dd, 0xd134, 0x88ef, 0xd105, 0x8902, 0xd0d6, 0x8914, 0xd0a7,\n 0x8927, 0xd079, 0x8939, 0xd04a, 0x894c, 0xd01b, 0x895f, 0xcfed,\n 0x8972, 0xcfbe, 0x8985, 0xcf90, 0x8998, 0xcf61, 0x89ab, 0xcf33,\n 0x89be, 0xcf04, 0x89d2, 0xced6, 0x89e5, 0xcea7, 0x89f8, 0xce79,\n 0x8a0c, 0xce4b, 0x8a1f, 0xce1c, 0x8a33, 0xcdee, 0x8a47, 0xcdc0,\n 0x8a5a, 0xcd92, 0x8a6e, 0xcd63, 0x8a82, 0xcd35, 0x8a96, 0xcd07,\n 0x8aaa, 0xccd9, 0x8abe, 0xccab, 0x8ad3, 0xcc7d, 0x8ae7, 0xcc4f,\n 0x8afb, 0xcc21, 0x8b10, 0xcbf3, 0x8b24, 0xcbc5, 0x8b39, 0xcb97,\n 0x8b4d, 0xcb69, 0x8b62, 0xcb3c, 0x8b77, 0xcb0e, 0x8b8b, 0xcae0,\n 0x8ba0, 0xcab2, 0x8bb5, 0xca85, 0x8bca, 0xca57, 0x8bdf, 0xca29,\n 0x8bf5, 0xc9fc, 0x8c0a, 0xc9ce, 0x8c1f, 0xc9a1, 0x8c35, 0xc973,\n 0x8c4a, 0xc946, 0x8c60, 0xc918, 0x8c75, 0xc8eb, 0x8c8b, 0xc8be,\n 0x8ca1, 0xc890, 0x8cb6, 0xc863, 0x8ccc, 0xc836, 0x8ce2, 0xc809,\n 0x8cf8, 0xc7db, 0x8d0e, 0xc7ae, 0x8d24, 0xc781, 0x8d3b, 0xc754,\n 0x8d51, 0xc727, 0x8d67, 0xc6fa, 0x8d7e, 0xc6cd, 0x8d94, 0xc6a0,\n 0x8dab, 0xc673, 0x8dc1, 0xc646, 0x8dd8, 0xc619, 0x8def, 0xc5ed,\n 0x8e06, 0xc5c0, 0x8e1d, 0xc593, 0x8e34, 0xc566, 0x8e4b, 0xc53a,\n 0x8e62, 0xc50d, 0x8e79, 0xc4e0, 0x8e90, 0xc4b4, 0x8ea8, 0xc487,\n 0x8ebf, 0xc45b, 0x8ed6, 0xc42e, 0x8eee, 0xc402, 0x8f06, 0xc3d6,\n 0x8f1d, 0xc3a9, 0x8f35, 0xc37d, 0x8f4d, 0xc351, 0x8f65, 0xc324,\n 0x8f7d, 0xc2f8, 0x8f95, 0xc2cc, 0x8fad, 0xc2a0, 0x8fc5, 0xc274,\n 0x8fdd, 0xc248, 0x8ff5, 0xc21c, 0x900e, 0xc1f0, 0x9026, 0xc1c4,\n 0x903e, 0xc198, 0x9057, 0xc16c, 0x9070, 0xc140, 0x9088, 0xc114,\n 0x90a1, 0xc0e9, 0x90ba, 0xc0bd, 0x90d3, 0xc091, 0x90ec, 0xc066,\n 0x9105, 0xc03a, 0x911e, 0xc00f, 0x9137, 0xbfe3, 0x9150, 0xbfb8,\n 0x9169, 0xbf8c, 0x9183, 0xbf61, 0x919c, 0xbf35, 0x91b6, 0xbf0a,\n 0x91cf, 0xbedf, 0x91e9, 0xbeb3, 0x9202, 0xbe88, 0x921c, 0xbe5d,\n 0x9236, 0xbe32, 0x9250, 0xbe07, 0x926a, 0xbddc, 0x9284, 0xbdb1,\n 0x929e, 0xbd86, 0x92b8, 0xbd5b, 0x92d2, 0xbd30, 0x92ec, 0xbd05,\n 0x9307, 0xbcda, 0x9321, 0xbcaf, 0x933c, 0xbc85, 0x9356, 0xbc5a,\n 0x9371, 0xbc2f, 0x938b, 0xbc05, 0x93a6, 0xbbda, 0x93c1, 0xbbb0,\n 0x93dc, 0xbb85, 0x93f7, 0xbb5b, 0x9412, 0xbb30, 0x942d, 0xbb06,\n 0x9448, 0xbadc, 0x9463, 0xbab1, 0x947e, 0xba87, 0x949a, 0xba5d,\n 0x94b5, 0xba33, 0x94d0, 0xba09, 0x94ec, 0xb9df, 0x9508, 0xb9b5,\n 0x9523, 0xb98b, 0x953f, 0xb961, 0x955b, 0xb937, 0x9577, 0xb90d,\n 0x9592, 0xb8e3, 0x95ae, 0xb8b9, 0x95ca, 0xb890, 0x95e6, 0xb866,\n 0x9603, 0xb83c, 0x961f, 0xb813, 0x963b, 0xb7e9, 0x9657, 0xb7c0,\n 0x9674, 0xb796, 0x9690, 0xb76d, 0x96ad, 0xb743, 0x96c9, 0xb71a,\n 0x96e6, 0xb6f1, 0x9703, 0xb6c7, 0x9720, 0xb69e, 0x973c, 0xb675,\n 0x9759, 0xb64c, 0x9776, 0xb623, 0x9793, 0xb5fa, 0x97b0, 0xb5d1,\n 0x97ce, 0xb5a8, 0x97eb, 0xb57f, 0x9808, 0xb556, 0x9826, 0xb52d,\n 0x9843, 0xb505, 0x9860, 0xb4dc, 0x987e, 0xb4b3, 0x989c, 0xb48b,\n 0x98b9, 0xb462, 0x98d7, 0xb439, 0x98f5, 0xb411, 0x9913, 0xb3e9,\n 0x9930, 0xb3c0, 0x994e, 0xb398, 0x996d, 0xb36f, 0x998b, 0xb347,\n 0x99a9, 0xb31f, 0x99c7, 0xb2f7, 0x99e5, 0xb2cf, 0x9a04, 0xb2a7,\n 0x9a22, 0xb27f, 0x9a40, 0xb257, 0x9a5f, 0xb22f, 0x9a7e, 0xb207,\n 0x9a9c, 0xb1df, 0x9abb, 0xb1b7, 0x9ada, 0xb18f, 0x9af9, 0xb168,\n 0x9b17, 0xb140, 0x9b36, 0xb118, 0x9b55, 0xb0f1, 0x9b75, 0xb0c9,\n 0x9b94, 0xb0a2, 0x9bb3, 0xb07b, 0x9bd2, 0xb053, 0x9bf1, 0xb02c,\n 0x9c11, 0xb005, 0x9c30, 0xafdd, 0x9c50, 0xafb6, 0x9c6f, 0xaf8f,\n 0x9c8f, 0xaf68, 0x9caf, 0xaf41, 0x9cce, 0xaf1a, 0x9cee, 0xaef3,\n 0x9d0e, 0xaecc, 0x9d2e, 0xaea5, 0x9d4e, 0xae7f, 0x9d6e, 0xae58,\n 0x9d8e, 0xae31, 0x9dae, 0xae0b, 0x9dce, 0xade4, 0x9def, 0xadbd,\n 0x9e0f, 0xad97, 0x9e2f, 0xad70, 0x9e50, 0xad4a, 0x9e70, 0xad24,\n 0x9e91, 0xacfd, 0x9eb2, 0xacd7, 0x9ed2, 0xacb1, 0x9ef3, 0xac8b,\n 0x9f14, 0xac65, 0x9f35, 0xac3f, 0x9f56, 0xac19, 0x9f77, 0xabf3,\n 0x9f98, 0xabcd, 0x9fb9, 0xaba7, 0x9fda, 0xab81, 0x9ffb, 0xab5c,\n 0xa01c, 0xab36, 0xa03e, 0xab10, 0xa05f, 0xaaeb, 0xa080, 0xaac5,\n 0xa0a2, 0xaaa0, 0xa0c4, 0xaa7a, 0xa0e5, 0xaa55, 0xa107, 0xaa30,\n 0xa129, 0xaa0a, 0xa14a, 0xa9e5, 0xa16c, 0xa9c0, 0xa18e, 0xa99b,\n 0xa1b0, 0xa976, 0xa1d2, 0xa951, 0xa1f4, 0xa92c, 0xa216, 0xa907,\n 0xa238, 0xa8e2, 0xa25b, 0xa8bd, 0xa27d, 0xa899, 0xa29f, 0xa874,\n 0xa2c2, 0xa84f, 0xa2e4, 0xa82b, 0xa307, 0xa806, 0xa329, 0xa7e2,\n 0xa34c, 0xa7bd, 0xa36f, 0xa799, 0xa391, 0xa774, 0xa3b4, 0xa750,\n 0xa3d7, 0xa72c, 0xa3fa, 0xa708, 0xa41d, 0xa6e4, 0xa440, 0xa6c0,\n 0xa463, 0xa69c, 0xa486, 0xa678, 0xa4a9, 0xa654, 0xa4cc, 0xa630,\n 0xa4f0, 0xa60c, 0xa513, 0xa5e8, 0xa537, 0xa5c5, 0xa55a, 0xa5a1,\n 0xa57e, 0xa57e, 0xa5a1, 0xa55a, 0xa5c5, 0xa537, 0xa5e8, 0xa513,\n 0xa60c, 0xa4f0, 0xa630, 0xa4cc, 0xa654, 0xa4a9, 0xa678, 0xa486,\n 0xa69c, 0xa463, 0xa6c0, 0xa440, 0xa6e4, 0xa41d, 0xa708, 0xa3fa,\n 0xa72c, 0xa3d7, 0xa750, 0xa3b4, 0xa774, 0xa391, 0xa799, 0xa36f,\n 0xa7bd, 0xa34c, 0xa7e2, 0xa329, 0xa806, 0xa307, 0xa82b, 0xa2e4,\n 0xa84f, 0xa2c2, 0xa874, 0xa29f, 0xa899, 0xa27d, 0xa8bd, 0xa25b,\n 0xa8e2, 0xa238, 0xa907, 0xa216, 0xa92c, 0xa1f4, 0xa951, 0xa1d2,\n 0xa976, 0xa1b0, 0xa99b, 0xa18e, 0xa9c0, 0xa16c, 0xa9e5, 0xa14a,\n 0xaa0a, 0xa129, 0xaa30, 0xa107, 0xaa55, 0xa0e5, 0xaa7a, 0xa0c4,\n 0xaaa0, 0xa0a2, 0xaac5, 0xa080, 0xaaeb, 0xa05f, 0xab10, 0xa03e,\n 0xab36, 0xa01c, 0xab5c, 0x9ffb, 0xab81, 0x9fda, 0xaba7, 0x9fb9,\n 0xabcd, 0x9f98, 0xabf3, 0x9f77, 0xac19, 0x9f56, 0xac3f, 0x9f35,\n 0xac65, 0x9f14, 0xac8b, 0x9ef3, 0xacb1, 0x9ed2, 0xacd7, 0x9eb2,\n 0xacfd, 0x9e91, 0xad24, 0x9e70, 0xad4a, 0x9e50, 0xad70, 0x9e2f,\n 0xad97, 0x9e0f, 0xadbd, 0x9def, 0xade4, 0x9dce, 0xae0b, 0x9dae,\n 0xae31, 0x9d8e, 0xae58, 0x9d6e, 0xae7f, 0x9d4e, 0xaea5, 0x9d2e,\n 0xaecc, 0x9d0e, 0xaef3, 0x9cee, 0xaf1a, 0x9cce, 0xaf41, 0x9caf,\n 0xaf68, 0x9c8f, 0xaf8f, 0x9c6f, 0xafb6, 0x9c50, 0xafdd, 0x9c30,\n 0xb005, 0x9c11, 0xb02c, 0x9bf1, 0xb053, 0x9bd2, 0xb07b, 0x9bb3,\n 0xb0a2, 0x9b94, 0xb0c9, 0x9b75, 0xb0f1, 0x9b55, 0xb118, 0x9b36,\n 0xb140, 0x9b17, 0xb168, 0x9af9, 0xb18f, 0x9ada, 0xb1b7, 0x9abb,\n 0xb1df, 0x9a9c, 0xb207, 0x9a7e, 0xb22f, 0x9a5f, 0xb257, 0x9a40,\n 0xb27f, 0x9a22, 0xb2a7, 0x9a04, 0xb2cf, 0x99e5, 0xb2f7, 0x99c7,\n 0xb31f, 0x99a9, 0xb347, 0x998b, 0xb36f, 0x996d, 0xb398, 0x994e,\n 0xb3c0, 0x9930, 0xb3e9, 0x9913, 0xb411, 0x98f5, 0xb439, 0x98d7,\n 0xb462, 0x98b9, 0xb48b, 0x989c, 0xb4b3, 0x987e, 0xb4dc, 0x9860,\n 0xb505, 0x9843, 0xb52d, 0x9826, 0xb556, 0x9808, 0xb57f, 0x97eb,\n 0xb5a8, 0x97ce, 0xb5d1, 0x97b0, 0xb5fa, 0x9793, 0xb623, 0x9776,\n 0xb64c, 0x9759, 0xb675, 0x973c, 0xb69e, 0x9720, 0xb6c7, 0x9703,\n 0xb6f1, 0x96e6, 0xb71a, 0x96c9, 0xb743, 0x96ad, 0xb76d, 0x9690,\n 0xb796, 0x9674, 0xb7c0, 0x9657, 0xb7e9, 0x963b, 0xb813, 0x961f,\n 0xb83c, 0x9603, 0xb866, 0x95e6, 0xb890, 0x95ca, 0xb8b9, 0x95ae,\n 0xb8e3, 0x9592, 0xb90d, 0x9577, 0xb937, 0x955b, 0xb961, 0x953f,\n 0xb98b, 0x9523, 0xb9b5, 0x9508, 0xb9df, 0x94ec, 0xba09, 0x94d0,\n 0xba33, 0x94b5, 0xba5d, 0x949a, 0xba87, 0x947e, 0xbab1, 0x9463,\n 0xbadc, 0x9448, 0xbb06, 0x942d, 0xbb30, 0x9412, 0xbb5b, 0x93f7,\n 0xbb85, 0x93dc, 0xbbb0, 0x93c1, 0xbbda, 0x93a6, 0xbc05, 0x938b,\n 0xbc2f, 0x9371, 0xbc5a, 0x9356, 0xbc85, 0x933c, 0xbcaf, 0x9321,\n 0xbcda, 0x9307, 0xbd05, 0x92ec, 0xbd30, 0x92d2, 0xbd5b, 0x92b8,\n 0xbd86, 0x929e, 0xbdb1, 0x9284, 0xbddc, 0x926a, 0xbe07, 0x9250,\n 0xbe32, 0x9236, 0xbe5d, 0x921c, 0xbe88, 0x9202, 0xbeb3, 0x91e9,\n 0xbedf, 0x91cf, 0xbf0a, 0x91b6, 0xbf35, 0x919c, 0xbf61, 0x9183,\n 0xbf8c, 0x9169, 0xbfb8, 0x9150, 0xbfe3, 0x9137, 0xc00f, 0x911e,\n 0xc03a, 0x9105, 0xc066, 0x90ec, 0xc091, 0x90d3, 0xc0bd, 0x90ba,\n 0xc0e9, 0x90a1, 0xc114, 0x9088, 0xc140, 0x9070, 0xc16c, 0x9057,\n 0xc198, 0x903e, 0xc1c4, 0x9026, 0xc1f0, 0x900e, 0xc21c, 0x8ff5,\n 0xc248, 0x8fdd, 0xc274, 0x8fc5, 0xc2a0, 0x8fad, 0xc2cc, 0x8f95,\n 0xc2f8, 0x8f7d, 0xc324, 0x8f65, 0xc351, 0x8f4d, 0xc37d, 0x8f35,\n 0xc3a9, 0x8f1d, 0xc3d6, 0x8f06, 0xc402, 0x8eee, 0xc42e, 0x8ed6,\n 0xc45b, 0x8ebf, 0xc487, 0x8ea8, 0xc4b4, 0x8e90, 0xc4e0, 0x8e79,\n 0xc50d, 0x8e62, 0xc53a, 0x8e4b, 0xc566, 0x8e34, 0xc593, 0x8e1d,\n 0xc5c0, 0x8e06, 0xc5ed, 0x8def, 0xc619, 0x8dd8, 0xc646, 0x8dc1,\n 0xc673, 0x8dab, 0xc6a0, 0x8d94, 0xc6cd, 0x8d7e, 0xc6fa, 0x8d67,\n 0xc727, 0x8d51, 0xc754, 0x8d3b, 0xc781, 0x8d24, 0xc7ae, 0x8d0e,\n 0xc7db, 0x8cf8, 0xc809, 0x8ce2, 0xc836, 0x8ccc, 0xc863, 0x8cb6,\n 0xc890, 0x8ca1, 0xc8be, 0x8c8b, 0xc8eb, 0x8c75, 0xc918, 0x8c60,\n 0xc946, 0x8c4a, 0xc973, 0x8c35, 0xc9a1, 0x8c1f, 0xc9ce, 0x8c0a,\n 0xc9fc, 0x8bf5, 0xca29, 0x8bdf, 0xca57, 0x8bca, 0xca85, 0x8bb5,\n 0xcab2, 0x8ba0, 0xcae0, 0x8b8b, 0xcb0e, 0x8b77, 0xcb3c, 0x8b62,\n 0xcb69, 0x8b4d, 0xcb97, 0x8b39, 0xcbc5, 0x8b24, 0xcbf3, 0x8b10,\n 0xcc21, 0x8afb, 0xcc4f, 0x8ae7, 0xcc7d, 0x8ad3, 0xccab, 0x8abe,\n 0xccd9, 0x8aaa, 0xcd07, 0x8a96, 0xcd35, 0x8a82, 0xcd63, 0x8a6e,\n 0xcd92, 0x8a5a, 0xcdc0, 0x8a47, 0xcdee, 0x8a33, 0xce1c, 0x8a1f,\n 0xce4b, 0x8a0c, 0xce79, 0x89f8, 0xcea7, 0x89e5, 0xced6, 0x89d2,\n 0xcf04, 0x89be, 0xcf33, 0x89ab, 0xcf61, 0x8998, 0xcf90, 0x8985,\n 0xcfbe, 0x8972, 0xcfed, 0x895f, 0xd01b, 0x894c, 0xd04a, 0x8939,\n 0xd079, 0x8927, 0xd0a7, 0x8914, 0xd0d6, 0x8902, 0xd105, 0x88ef,\n 0xd134, 0x88dd, 0xd162, 0x88ca, 0xd191, 0x88b8, 0xd1c0, 0x88a6,\n 0xd1ef, 0x8894, 0xd21e, 0x8882, 0xd24d, 0x8870, 0xd27c, 0x885e,\n 0xd2ab, 0x884c, 0xd2da, 0x883a, 0xd309, 0x8828, 0xd338, 0x8817,\n 0xd367, 0x8805, 0xd396, 0x87f4, 0xd3c5, 0x87e2, 0xd3f4, 0x87d1,\n 0xd424, 0x87c0, 0xd453, 0x87af, 0xd482, 0x879d, 0xd4b1, 0x878c,\n 0xd4e1, 0x877b, 0xd510, 0x876b, 0xd53f, 0x875a, 0xd56f, 0x8749,\n 0xd59e, 0x8738, 0xd5ce, 0x8728, 0xd5fd, 0x8717, 0xd62d, 0x8707,\n 0xd65c, 0x86f6, 0xd68c, 0x86e6, 0xd6bb, 0x86d6, 0xd6eb, 0x86c6,\n 0xd71b, 0x86b6, 0xd74a, 0x86a5, 0xd77a, 0x8696, 0xd7aa, 0x8686,\n 0xd7d9, 0x8676, 0xd809, 0x8666, 0xd839, 0x8656, 0xd869, 0x8647,\n 0xd898, 0x8637, 0xd8c8, 0x8628, 0xd8f8, 0x8619, 0xd928, 0x8609,\n 0xd958, 0x85fa, 0xd988, 0x85eb, 0xd9b8, 0x85dc, 0xd9e8, 0x85cd,\n 0xda18, 0x85be, 0xda48, 0x85af, 0xda78, 0x85a0, 0xdaa8, 0x8592,\n 0xdad8, 0x8583, 0xdb08, 0x8574, 0xdb38, 0x8566, 0xdb68, 0x8558,\n 0xdb99, 0x8549, 0xdbc9, 0x853b, 0xdbf9, 0x852d, 0xdc29, 0x851f,\n 0xdc59, 0x8511, 0xdc8a, 0x8503, 0xdcba, 0x84f5, 0xdcea, 0x84e7,\n 0xdd1b, 0x84d9, 0xdd4b, 0x84cc, 0xdd7c, 0x84be, 0xddac, 0x84b0,\n 0xdddc, 0x84a3, 0xde0d, 0x8496, 0xde3d, 0x8488, 0xde6e, 0x847b,\n 0xde9e, 0x846e, 0xdecf, 0x8461, 0xdeff, 0x8454, 0xdf30, 0x8447,\n 0xdf61, 0x843a, 0xdf91, 0x842d, 0xdfc2, 0x8421, 0xdff2, 0x8414,\n 0xe023, 0x8407, 0xe054, 0x83fb, 0xe085, 0x83ef, 0xe0b5, 0x83e2,\n 0xe0e6, 0x83d6, 0xe117, 0x83ca, 0xe148, 0x83be, 0xe178, 0x83b2,\n 0xe1a9, 0x83a6, 0xe1da, 0x839a, 0xe20b, 0x838e, 0xe23c, 0x8382,\n 0xe26d, 0x8377, 0xe29e, 0x836b, 0xe2cf, 0x8360, 0xe2ff, 0x8354,\n 0xe330, 0x8349, 0xe361, 0x833e, 0xe392, 0x8332, 0xe3c3, 0x8327,\n 0xe3f4, 0x831c, 0xe426, 0x8311, 0xe457, 0x8306, 0xe488, 0x82fb,\n 0xe4b9, 0x82f1, 0xe4ea, 0x82e6, 0xe51b, 0x82db, 0xe54c, 0x82d1,\n 0xe57d, 0x82c6, 0xe5af, 0x82bc, 0xe5e0, 0x82b2, 0xe611, 0x82a8,\n 0xe642, 0x829d, 0xe673, 0x8293, 0xe6a5, 0x8289, 0xe6d6, 0x827f,\n 0xe707, 0x8276, 0xe739, 0x826c, 0xe76a, 0x8262, 0xe79b, 0x8259,\n 0xe7cd, 0x824f, 0xe7fe, 0x8246, 0xe82f, 0x823c, 0xe861, 0x8233,\n 0xe892, 0x822a, 0xe8c4, 0x8220, 0xe8f5, 0x8217, 0xe926, 0x820e,\n 0xe958, 0x8205, 0xe989, 0x81fd, 0xe9bb, 0x81f4, 0xe9ec, 0x81eb,\n 0xea1e, 0x81e2, 0xea4f, 0x81da, 0xea81, 0x81d1, 0xeab3, 0x81c9,\n 0xeae4, 0x81c1, 0xeb16, 0x81b8, 0xeb47, 0x81b0, 0xeb79, 0x81a8,\n 0xebab, 0x81a0, 0xebdc, 0x8198, 0xec0e, 0x8190, 0xec3f, 0x8188,\n 0xec71, 0x8181, 0xeca3, 0x8179, 0xecd5, 0x8172, 0xed06, 0x816a,\n 0xed38, 0x8163, 0xed6a, 0x815b, 0xed9b, 0x8154, 0xedcd, 0x814d,\n 0xedff, 0x8146, 0xee31, 0x813f, 0xee62, 0x8138, 0xee94, 0x8131,\n 0xeec6, 0x812a, 0xeef8, 0x8123, 0xef2a, 0x811d, 0xef5c, 0x8116,\n 0xef8d, 0x8110, 0xefbf, 0x8109, 0xeff1, 0x8103, 0xf023, 0x80fd,\n 0xf055, 0x80f6, 0xf087, 0x80f0, 0xf0b9, 0x80ea, 0xf0eb, 0x80e4,\n 0xf11c, 0x80de, 0xf14e, 0x80d9, 0xf180, 0x80d3, 0xf1b2, 0x80cd,\n 0xf1e4, 0x80c8, 0xf216, 0x80c2, 0xf248, 0x80bd, 0xf27a, 0x80b7,\n 0xf2ac, 0x80b2, 0xf2de, 0x80ad, 0xf310, 0x80a8, 0xf342, 0x80a3,\n 0xf374, 0x809e, 0xf3a6, 0x8099, 0xf3d8, 0x8094, 0xf40a, 0x808f,\n 0xf43c, 0x808b, 0xf46e, 0x8086, 0xf4a0, 0x8082, 0xf4d3, 0x807d,\n 0xf505, 0x8079, 0xf537, 0x8075, 0xf569, 0x8070, 0xf59b, 0x806c,\n 0xf5cd, 0x8068, 0xf5ff, 0x8064, 0xf631, 0x8060, 0xf663, 0x805d,\n 0xf695, 0x8059, 0xf6c8, 0x8055, 0xf6fa, 0x8052, 0xf72c, 0x804e,\n 0xf75e, 0x804b, 0xf790, 0x8047, 0xf7c2, 0x8044, 0xf7f4, 0x8041,\n 0xf827, 0x803e, 0xf859, 0x803b, 0xf88b, 0x8038, 0xf8bd, 0x8035,\n 0xf8ef, 0x8032, 0xf922, 0x802f, 0xf954, 0x802d, 0xf986, 0x802a,\n 0xf9b8, 0x8027, 0xf9ea, 0x8025, 0xfa1d, 0x8023, 0xfa4f, 0x8020,\n 0xfa81, 0x801e, 0xfab3, 0x801c, 0xfae5, 0x801a, 0xfb18, 0x8018,\n 0xfb4a, 0x8016, 0xfb7c, 0x8014, 0xfbae, 0x8013, 0xfbe1, 0x8011,\n 0xfc13, 0x800f, 0xfc45, 0x800e, 0xfc77, 0x800c, 0xfcaa, 0x800b,\n 0xfcdc, 0x800a, 0xfd0e, 0x8009, 0xfd40, 0x8008, 0xfd73, 0x8007,\n 0xfda5, 0x8006, 0xfdd7, 0x8005, 0xfe09, 0x8004, 0xfe3c, 0x8003,\n 0xfe6e, 0x8002, 0xfea0, 0x8002, 0xfed2, 0x8001, 0xff05, 0x8001,\n 0xff37, 0x8001, 0xff69, 0x8000, 0xff9b, 0x8000, 0xffce, 0x8000,\n};\n\n/** \n* @} end of CFFT_CIFFT group \n*/\n\n/* \n* @brief Q15 table for reciprocal \n*/\nconst q15_t ALIGN4 armRecipTableQ15[64] = {\n 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,\n 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,\n 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,\n 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,\n 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,\n 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,\n 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,\n 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,\n 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,\n 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,\n 0x41CC, 0x4146, 0x40C2, 0x4040\n};\n\n/* \n* @brief Q31 table for reciprocal \n*/\nconst q31_t armRecipTableQ31[64] = {\n 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,\n 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,\n 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,\n 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,\n 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,\n 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,\n 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,\n 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,\n 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,\n 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,\n 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102\n};\n\nconst uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] = \n{\n //8x2, size 20\n 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112\n};\n\nconst uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] = \n{\n //8x4, size 48\n 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,\n 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,\n 152,224, 176,208, 184,232, 216,240, 200,224, 232,240\n};\n\nconst uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] = \n{ \n //radix 8, size 56\n 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, \n 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, \n 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, \n 368,424, 376,488, 440,496\n};\n\nconst uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = \n{\n //8x2, size 208\n 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, \n 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, \n 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, \n 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, \n 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, \n 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, \n 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, \n 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, \n 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, \n 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, \n 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, \n 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, \n 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008\n};\n\nconst uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = \n{\n //8x4, size 440\n 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, \n 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, \n 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, \n 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, \n 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, \n 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, \n 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, \n 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, \n 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, \n 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, \n 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, \n 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, \n 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, \n 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, \n 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, \n 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, \n 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, \n 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, \n 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, \n 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, \n 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, \n 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, \n 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, \n 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, \n 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, \n 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, \n 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, \n 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, \n 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, \n 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, \n 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, \n 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,\n 1960,1968, 2008,2032, 1992,2016, 2024,2032\n};\n\nconst uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = \n{\n //radix 8, size 448\n 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, \n 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, \n 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, \n 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, \n 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, \n 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, \n 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, \n 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, \n 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, \n 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, \n 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, \n 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, \n 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, \n 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, \n 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, \n 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, \n 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, \n 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, \n 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, \n 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, \n 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, \n 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, \n 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, \n 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, \n 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, \n 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, \n 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, \n 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, \n 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, \n 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, \n 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, \n 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, \n 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, \n 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, \n 3448,3952, 3512,4016, 3576,4080\n};\n\nconst uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] = \n{\n //8x2, size 1800\n 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, \n 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, \n 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, \n 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, \n 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, \n 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, \n 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, \n 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, \n 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, \n 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, \n 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, \n 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, \n 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, \n 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, \n 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, \n 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, \n 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, \n 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, \n 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, \n 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, \n 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, \n 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, \n 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, \n 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, \n 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, \n 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, \n 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, \n 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, \n 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, \n 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, \n 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, \n 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, \n 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, \n 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, \n 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, \n 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, \n 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, \n 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, \n 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, \n 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, \n 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, \n 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, \n 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, \n 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, \n 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, \n 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, \n 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, \n 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, \n 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, \n 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, \n 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, \n 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, \n 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, \n 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, \n 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, \n 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, \n 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, \n 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, \n 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, \n 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, \n 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, \n 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, \n 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, \n 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, \n 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, \n 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, \n 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, \n 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, \n 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, \n 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, \n 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, \n 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, \n 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, \n 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, \n 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, \n 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, \n 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, \n 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, \n 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, \n 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, \n 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, \n 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, \n 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, \n 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, \n 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, \n 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, \n 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, \n 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, \n 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, \n 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, \n 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, \n 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, \n 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, \n 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, \n 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, \n 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, \n 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, \n 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, \n 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, \n 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, \n 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, \n 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, \n 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, \n 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, \n 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, \n 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, \n 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, \n 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, \n 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, \n 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, \n 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, \n 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, \n 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, \n 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, \n 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, \n 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, \n 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, \n 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, \n 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, \n 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, \n 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, \n 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, \n 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, \n 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, \n 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, \n 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, \n 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, \n 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, \n 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, \n 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, \n 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, \n 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, \n 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, \n 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, \n 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, \n 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, \n 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, \n 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, \n 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, \n 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, \n 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, \n 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, \n 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, \n 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, \n 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, \n 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, \n 8112,8136, 8120,8168, 8136,8160, 8152,8176\n};\n\nconst uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] = \n{\n //8x2, size 3808\n 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, \n 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, \n 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, \n 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, \n 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, \n 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, \n 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, \n 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, \n 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, \n 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, \n 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, \n 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, \n 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, \n 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, \n 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, \n 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, \n 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, \n 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, \n 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, \n 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, \n 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, \n 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, \n 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, \n 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, \n 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, \n 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, \n 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, \n 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, \n 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, \n 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, \n 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, \n 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, \n 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, \n 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, \n 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, \n 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, \n 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, \n 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, \n 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, \n 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, \n 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, \n 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, \n 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, \n 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, \n 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, \n 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, \n 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, \n 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, \n 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, \n 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, \n 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, \n 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, \n 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, \n 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, \n 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, \n 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, \n 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, \n 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, \n 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, \n 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, \n 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, \n 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, \n 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, \n 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, \n 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, \n 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, \n 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, \n 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, \n 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, \n 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, \n 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, \n 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, \n 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, \n 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, \n 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, \n 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, \n 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, \n 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, \n 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, \n 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208, \n 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624, \n 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208, \n 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448, \n 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744, \n 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, \n 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, \n 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, \n 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, \n 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, \n 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, \n 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, \n 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, \n 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, \n 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, \n 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, \n 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, \n 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, \n 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, \n 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, \n 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, \n 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, \n 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, \n 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, \n 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, \n 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, \n 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, \n 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, \n 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, \n 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, \n 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, \n 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, \n 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, \n 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, \n 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, \n 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, \n 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, \n 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, \n 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, \n 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, \n 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, \n 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, \n 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, \n 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, \n 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, \n 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, \n 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240, \n 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296, \n 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776, \n 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680, \n 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280, \n 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568, \n 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816, \n 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448, \n 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352, \n 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336, \n 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856, \n 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720, \n 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392, \n 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600, \n 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928, \n 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488, \n 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432, \n 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368, \n 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968, \n 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752, \n 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472, \n 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608, \n 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008, \n 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488, \n 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544, \n 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376, \n 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048, \n 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760, \n 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584, \n 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640, \n 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120, \n 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528, \n 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624, \n 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408, \n 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160, \n 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792, \n 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664, \n 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680, \n 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200, \n 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560, \n 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736, \n 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320, \n 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448, \n 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760, \n 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464, \n 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392, \n 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576, \n 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896, \n 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688, \n 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432, \n 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736, \n 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968, \n 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376, \n 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472, \n 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424, \n 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008, \n 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536, \n 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512, \n 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736, \n 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048, \n 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728, \n 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584, \n 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248, \n 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408, \n 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112, \n 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040, \n 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616, \n 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640, \n 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664, \n 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688, \n 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616, \n 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312, \n 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336, \n 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392, \n 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656, \n 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408, \n 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192, \n 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584, \n 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760, \n 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208, \n 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816, \n 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664, \n 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816, \n 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328, \n 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296, \n 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400, \n 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480, \n 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304, \n 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912, \n 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296, \n 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360, \n 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464, \n 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440, \n 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344, \n 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800, \n 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464, \n 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968, \n 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368, \n 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440, \n 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488, \n 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528, \n 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400, \n 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440, \n 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552, \n 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056, \n 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424, \n 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760, \n 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008, \n 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408, \n 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648, \n 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120, \n 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440, \n 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656, \n 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552, \n 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160, \n 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720, \n 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760, \n 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672, \n 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624, \n 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728, \n 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736, \n 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608, \n 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512, \n 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760, \n 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296, \n 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664, \n 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712, \n 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816, \n 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824, \n 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696, \n 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832, \n 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544, \n 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584, \n 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496, \n 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688, \n 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920, \n 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344, \n 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576, \n 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400, \n 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448, \n 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696, \n 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816, \n 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344, \n 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976, \n 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416, \n 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496, \n 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488, \n 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536, \n 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592, \n 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736, \n 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664, \n 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064, \n 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464, \n 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816, \n 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768, \n 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576, \n 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592, \n 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536, \n 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664, \n 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616, \n 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704, \n 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728, \n 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488, \n 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384, \n 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560, \n 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392, \n 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528, \n 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464, \n 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, \n 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, \n 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, \n 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, \n 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, \n 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, \n 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, \n 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, \n 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, \n 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, \n 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,\n 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, \n 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, \n 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, \n 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, \n 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, \n 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, \n 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, \n 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, \n 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, \n 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, \n 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, \n 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, \n 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, \n 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, \n 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, \n 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, \n 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, \n 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, \n 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, \n 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, \n 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, \n 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, \n 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, \n 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, \n 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, \n 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, \n 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, \n 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, \n 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, \n 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, \n 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, \n 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,\n 16328,16352, 16360,16368\n};\n\nconst uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] = \n{\n //radix 8, size 4032\n 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, \n 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, \n 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, \n 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, \n 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, \n 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, \n 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, \n 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, \n 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, \n 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, \n 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, \n 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, \n 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, \n 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, \n 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, \n 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, \n 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, \n 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, \n 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, \n 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, \n 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, \n 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, \n 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, \n 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, \n 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, \n 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, \n 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, \n 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, \n 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, \n 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, \n 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, \n 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, \n 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, \n 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, \n 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, \n 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, \n 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, \n 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, \n 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, \n 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, \n 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, \n 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, \n 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, \n 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, \n 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, \n 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, \n 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, \n 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, \n 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, \n 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, \n 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, \n 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, \n 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, \n 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, \n 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, \n 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, \n 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, \n 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, \n 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, \n 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, \n 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, \n 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, \n 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, \n 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, \n 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, \n 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, \n 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, \n 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, \n 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, \n 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, \n 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, \n 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, \n 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, \n 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, \n 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, \n 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, \n 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, \n 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, \n 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, \n 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, \n 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152, \n 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728, \n 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144, \n 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560, \n 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976, \n 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456, \n 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968, \n 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384, \n 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800, \n 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216, \n 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792, \n 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208, \n 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624, \n 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040, \n 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520, \n 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032, \n 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544, \n 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960, \n 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376, \n 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792, \n 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368, \n 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784, \n 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200, \n 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680, \n 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192, \n 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704, \n 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216, \n 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632, \n 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048, \n 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464, \n 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880, \n 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456, \n 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936, \n 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448, \n 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960, \n 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472, \n 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984, \n 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400, \n 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816, \n 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232, \n 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712, \n 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224, \n 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736, \n 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248, \n 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760, \n 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272, \n 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688, \n 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104, \n 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584, \n 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096, \n 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608, \n 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120, \n 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632, \n 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144, \n 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656, \n 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072, \n 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648, \n 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128, \n 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640, \n 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152, \n 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664, \n 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176, \n 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688, \n 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200, \n 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712, \n 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720, \n 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232, \n 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744, \n 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256, \n 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768, \n 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280, \n 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792, \n 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368, \n 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976, \n 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488, \n 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000, \n 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512, \n 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024, \n 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536, \n 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048, \n 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624, \n 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232, \n 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840, \n 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352, \n 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864, \n 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376, \n 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888, \n 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400, \n 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008, \n 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616, \n 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224, \n 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736, \n 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152, \n 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568, \n 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984, \n 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464, \n 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944, \n 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456, \n 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968, \n 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480, \n 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992, \n 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408, \n 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824, \n 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240, \n 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720, \n 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232, \n 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744, \n 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256, \n 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768, \n 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280, \n 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696, \n 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112, \n 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592, \n 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072, \n 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584, \n 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096, \n 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608, \n 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120, \n 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632, \n 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144, \n 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560, \n 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040, \n 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552, \n 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064, \n 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576, \n 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088, \n 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600, \n 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112, \n 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624, \n 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696, \n 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208, \n 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720, \n 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232, \n 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744, \n 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256, \n 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768, \n 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280, \n 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984, \n 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496, \n 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008, \n 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520, \n 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032, \n 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544, \n 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056, \n 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632, \n 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240, \n 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848, \n 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360, \n 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872, \n 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384, \n 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896, \n 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408, \n 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112, \n 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720, \n 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328, \n 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840, \n 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352, \n 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864, \n 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376, \n 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952, \n 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688, \n 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296, \n 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904, \n 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416, \n 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928, \n 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440, \n 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016, \n 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752, \n 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360, \n 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968, \n 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576, \n 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, \n 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, \n 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, \n 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, \n 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, \n 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, \n 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, \n 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, \n 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, \n 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, \n 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, \n 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, \n 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, \n 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, \n 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, \n 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, \n 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, \n 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, \n 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, \n 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, \n 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, \n 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, \n 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, \n 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, \n 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, \n 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, \n 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, \n 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, \n 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, \n 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, \n 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, \n 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, \n 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, \n 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, \n 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, \n 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, \n 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, \n 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, \n 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, \n 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, \n 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, \n 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, \n 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, \n 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, \n 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, \n 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, \n 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, \n 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, \n 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, \n 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, \n 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, \n 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, \n 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, \n 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, \n 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, \n 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, \n 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, \n 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, \n 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, \n 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, \n 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, \n 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, \n 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, \n 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, \n 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, \n 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, \n 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, \n 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, \n 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, \n 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, \n 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, \n 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, \n 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, \n 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, \n 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, \n 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, \n 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, \n 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, \n 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, \n 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, \n 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, \n 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, \n 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, \n 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, \n 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, \n 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, \n 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, \n 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, \n 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, \n 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, \n 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, \n 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, \n 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, \n 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, \n 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, \n 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, \n 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, \n 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, \n 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, \n 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, \n 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, \n 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, \n 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, \n 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, \n 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, \n 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, \n 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, \n 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, \n 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, \n 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, \n 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, \n 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, \n 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, \n 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, \n 32248,32696\n};\n\n\n/** \n* \\par \n* Example code for Floating-point RFFT Twiddle factors Generation: \n* \\par \n* 
TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).'
\n* \\par \n* Real and Imag values are in interleaved fashion \n*/\nconst float32_t twiddleCoef_rfft_32[32] = {\n0.0f\t\t\t,\t1.0f\t\t\t,\n0.195090322f\t,\t0.98078528f \t,\n0.382683432f\t,\t0.923879533f\t,\n0.555570233f\t,\t0.831469612f\t,\n0.707106781f\t,\t0.707106781f\t,\n0.831469612f\t,\t0.555570233f\t,\n0.923879533f\t,\t0.382683432f ,\t\n0.98078528f\t\t,\t0.195090322f\t,\n1.0f\t\t\t,\t0.0f\t\t\t,\n0.98078528f\t\t,\t-0.195090322f\t,\n0.923879533f\t,\t-0.382683432f\t,\n0.831469612f\t,\t-0.555570233f\t,\n0.707106781f\t,\t-0.707106781f\t,\n0.555570233f\t,\t-0.831469612f\t,\n0.382683432f\t,\t-0.923879533f\t,\n0.195090322f\t,\t-0.98078528f\t\n};\n\nconst float32_t twiddleCoef_rfft_64[64] = {\n0.0f,\t1.0f,\n0.098017140329561f,\t0.995184726672197f,\n0.195090322016128f,\t0.98078528040323f,\n0.290284677254462f,\t0.956940335732209f,\n0.38268343236509f,\t0.923879532511287f,\n0.471396736825998f,\t0.881921264348355f,\n0.555570233019602f,\t0.831469612302545f,\n0.634393284163645f,\t0.773010453362737f,\n0.707106781186547f,\t0.707106781186548f,\n0.773010453362737f,\t0.634393284163645f,\n0.831469612302545f,\t0.555570233019602f,\n0.881921264348355f,\t0.471396736825998f,\n0.923879532511287f,\t0.38268343236509f,\n0.956940335732209f,\t0.290284677254462f,\n0.98078528040323f,\t0.195090322016128f,\n0.995184726672197f,\t0.098017140329561f,\n1.0f,\t0.0f,\n0.995184726672197f,\t-0.098017140329561f,\n0.98078528040323f,\t-0.195090322016128f,\n0.956940335732209f,\t-0.290284677254462f,\n0.923879532511287f,\t-0.38268343236509f,\n0.881921264348355f,\t-0.471396736825998f,\n0.831469612302545f,\t-0.555570233019602f,\n0.773010453362737f,\t-0.634393284163645f,\n0.707106781186548f,\t-0.707106781186547f,\n0.634393284163645f,\t-0.773010453362737f,\n0.555570233019602f,\t-0.831469612302545f,\n0.471396736825998f,\t-0.881921264348355f,\n0.38268343236509f,\t-0.923879532511287f,\n0.290284677254462f,\t-0.956940335732209f,\n0.195090322016129f,\t-0.98078528040323f,\n0.098017140329561f,\t-0.995184726672197f\n};\n\nconst float32_t twiddleCoef_rfft_128[128] = {\n 0.000000000f, 1.000000000f,\n 0.049067674f, 0.998795456f,\n 0.098017140f, 0.995184727f,\n 0.146730474f, 0.989176510f,\n 0.195090322f, 0.980785280f,\n 0.242980180f, 0.970031253f,\n 0.290284677f, 0.956940336f,\n 0.336889853f, 0.941544065f,\n 0.382683432f, 0.923879533f,\n 0.427555093f, 0.903989293f,\n 0.471396737f, 0.881921264f,\n 0.514102744f, 0.857728610f,\n 0.555570233f, 0.831469612f,\n 0.595699304f, 0.803207531f,\n 0.634393284f, 0.773010453f,\n 0.671558955f, 0.740951125f,\n 0.707106781f, 0.707106781f,\n 0.740951125f, 0.671558955f,\n 0.773010453f, 0.634393284f,\n 0.803207531f, 0.595699304f,\n 0.831469612f, 0.555570233f,\n 0.857728610f, 0.514102744f,\n 0.881921264f, 0.471396737f,\n 0.903989293f, 0.427555093f,\n 0.923879533f, 0.382683432f,\n 0.941544065f, 0.336889853f,\n 0.956940336f, 0.290284677f,\n 0.970031253f, 0.242980180f,\n 0.980785280f, 0.195090322f,\n 0.989176510f, 0.146730474f,\n 0.995184727f, 0.098017140f,\n 0.998795456f, 0.049067674f,\n 1.000000000f, 0.000000000f,\n 0.998795456f, -0.049067674f,\n 0.995184727f, -0.098017140f,\n 0.989176510f, -0.146730474f,\n 0.980785280f, -0.195090322f,\n 0.970031253f, -0.242980180f,\n 0.956940336f, -0.290284677f,\n 0.941544065f, -0.336889853f,\n 0.923879533f, -0.382683432f,\n 0.903989293f, -0.427555093f,\n 0.881921264f, -0.471396737f,\n 0.857728610f, -0.514102744f,\n 0.831469612f, -0.555570233f,\n 0.803207531f, -0.595699304f,\n 0.773010453f, -0.634393284f,\n 0.740951125f, -0.671558955f,\n 0.707106781f, -0.707106781f,\n 0.671558955f, -0.740951125f,\n 0.634393284f, -0.773010453f,\n 0.595699304f, -0.803207531f,\n 0.555570233f, -0.831469612f,\n 0.514102744f, -0.857728610f,\n 0.471396737f, -0.881921264f,\n 0.427555093f, -0.903989293f,\n 0.382683432f, -0.923879533f,\n 0.336889853f, -0.941544065f,\n 0.290284677f, -0.956940336f,\n 0.242980180f, -0.970031253f,\n 0.195090322f, -0.980785280f,\n 0.146730474f, -0.989176510f,\n 0.098017140f, -0.995184727f,\n 0.049067674f, -0.998795456f\n};\n\nconst float32_t twiddleCoef_rfft_256[256] = {\n 0.000000000f, 1.000000000f,\n 0.024541229f, 0.999698819f,\n 0.049067674f, 0.998795456f,\n 0.073564564f, 0.997290457f,\n 0.098017140f, 0.995184727f,\n 0.122410675f, 0.992479535f,\n 0.146730474f, 0.989176510f,\n 0.170961889f, 0.985277642f,\n 0.195090322f, 0.980785280f,\n 0.219101240f, 0.975702130f,\n 0.242980180f, 0.970031253f,\n 0.266712757f, 0.963776066f,\n 0.290284677f, 0.956940336f,\n 0.313681740f, 0.949528181f,\n 0.336889853f, 0.941544065f,\n 0.359895037f, 0.932992799f,\n 0.382683432f, 0.923879533f,\n 0.405241314f, 0.914209756f,\n 0.427555093f, 0.903989293f,\n 0.449611330f, 0.893224301f,\n 0.471396737f, 0.881921264f,\n 0.492898192f, 0.870086991f,\n 0.514102744f, 0.857728610f,\n 0.534997620f, 0.844853565f,\n 0.555570233f, 0.831469612f,\n 0.575808191f, 0.817584813f,\n 0.595699304f, 0.803207531f,\n 0.615231591f, 0.788346428f,\n 0.634393284f, 0.773010453f,\n 0.653172843f, 0.757208847f,\n 0.671558955f, 0.740951125f,\n 0.689540545f, 0.724247083f,\n 0.707106781f, 0.707106781f,\n 0.724247083f, 0.689540545f,\n 0.740951125f, 0.671558955f,\n 0.757208847f, 0.653172843f,\n 0.773010453f, 0.634393284f,\n 0.788346428f, 0.615231591f,\n 0.803207531f, 0.595699304f,\n 0.817584813f, 0.575808191f,\n 0.831469612f, 0.555570233f,\n 0.844853565f, 0.534997620f,\n 0.857728610f, 0.514102744f,\n 0.870086991f, 0.492898192f,\n 0.881921264f, 0.471396737f,\n 0.893224301f, 0.449611330f,\n 0.903989293f, 0.427555093f,\n 0.914209756f, 0.405241314f,\n 0.923879533f, 0.382683432f,\n 0.932992799f, 0.359895037f,\n 0.941544065f, 0.336889853f,\n 0.949528181f, 0.313681740f,\n 0.956940336f, 0.290284677f,\n 0.963776066f, 0.266712757f,\n 0.970031253f, 0.242980180f,\n 0.975702130f, 0.219101240f,\n 0.980785280f, 0.195090322f,\n 0.985277642f, 0.170961889f,\n 0.989176510f, 0.146730474f,\n 0.992479535f, 0.122410675f,\n 0.995184727f, 0.098017140f,\n 0.997290457f, 0.073564564f,\n 0.998795456f, 0.049067674f,\n 0.999698819f, 0.024541229f,\n 1.000000000f, 0.000000000f,\n 0.999698819f, -0.024541229f,\n 0.998795456f, -0.049067674f,\n 0.997290457f, -0.073564564f,\n 0.995184727f, -0.098017140f,\n 0.992479535f, -0.122410675f,\n 0.989176510f, -0.146730474f,\n 0.985277642f, -0.170961889f,\n 0.980785280f, -0.195090322f,\n 0.975702130f, -0.219101240f,\n 0.970031253f, -0.242980180f,\n 0.963776066f, -0.266712757f,\n 0.956940336f, -0.290284677f,\n 0.949528181f, -0.313681740f,\n 0.941544065f, -0.336889853f,\n 0.932992799f, -0.359895037f,\n 0.923879533f, -0.382683432f,\n 0.914209756f, -0.405241314f,\n 0.903989293f, -0.427555093f,\n 0.893224301f, -0.449611330f,\n 0.881921264f, -0.471396737f,\n 0.870086991f, -0.492898192f,\n 0.857728610f, -0.514102744f,\n 0.844853565f, -0.534997620f,\n 0.831469612f, -0.555570233f,\n 0.817584813f, -0.575808191f,\n 0.803207531f, -0.595699304f,\n 0.788346428f, -0.615231591f,\n 0.773010453f, -0.634393284f,\n 0.757208847f, -0.653172843f,\n 0.740951125f, -0.671558955f,\n 0.724247083f, -0.689540545f,\n 0.707106781f, -0.707106781f,\n 0.689540545f, -0.724247083f,\n 0.671558955f, -0.740951125f,\n 0.653172843f, -0.757208847f,\n 0.634393284f, -0.773010453f,\n 0.615231591f, -0.788346428f,\n 0.595699304f, -0.803207531f,\n 0.575808191f, -0.817584813f,\n 0.555570233f, -0.831469612f,\n 0.534997620f, -0.844853565f,\n 0.514102744f, -0.857728610f,\n 0.492898192f, -0.870086991f,\n 0.471396737f, -0.881921264f,\n 0.449611330f, -0.893224301f,\n 0.427555093f, -0.903989293f,\n 0.405241314f, -0.914209756f,\n 0.382683432f, -0.923879533f,\n 0.359895037f, -0.932992799f,\n 0.336889853f, -0.941544065f,\n 0.313681740f, -0.949528181f,\n 0.290284677f, -0.956940336f,\n 0.266712757f, -0.963776066f,\n 0.242980180f, -0.970031253f,\n 0.219101240f, -0.975702130f,\n 0.195090322f, -0.980785280f,\n 0.170961889f, -0.985277642f,\n 0.146730474f, -0.989176510f,\n 0.122410675f, -0.992479535f,\n 0.098017140f, -0.995184727f,\n 0.073564564f, -0.997290457f,\n 0.049067674f, -0.998795456f,\n 0.024541229f, -0.999698819f\n};\n\nconst float32_t twiddleCoef_rfft_512[512] = {\n 0.000000000f, 1.000000000f,\n 0.012271538f, 0.999924702f,\n 0.024541229f, 0.999698819f,\n 0.036807223f, 0.999322385f,\n 0.049067674f, 0.998795456f,\n 0.061320736f, 0.998118113f,\n 0.073564564f, 0.997290457f,\n 0.085797312f, 0.996312612f,\n 0.098017140f, 0.995184727f,\n 0.110222207f, 0.993906970f,\n 0.122410675f, 0.992479535f,\n 0.134580709f, 0.990902635f,\n 0.146730474f, 0.989176510f,\n 0.158858143f, 0.987301418f,\n 0.170961889f, 0.985277642f,\n 0.183039888f, 0.983105487f,\n 0.195090322f, 0.980785280f,\n 0.207111376f, 0.978317371f,\n 0.219101240f, 0.975702130f,\n 0.231058108f, 0.972939952f,\n 0.242980180f, 0.970031253f,\n 0.254865660f, 0.966976471f,\n 0.266712757f, 0.963776066f,\n 0.278519689f, 0.960430519f,\n 0.290284677f, 0.956940336f,\n 0.302005949f, 0.953306040f,\n 0.313681740f, 0.949528181f,\n 0.325310292f, 0.945607325f,\n 0.336889853f, 0.941544065f,\n 0.348418680f, 0.937339012f,\n 0.359895037f, 0.932992799f,\n 0.371317194f, 0.928506080f,\n 0.382683432f, 0.923879533f,\n 0.393992040f, 0.919113852f,\n 0.405241314f, 0.914209756f,\n 0.416429560f, 0.909167983f,\n 0.427555093f, 0.903989293f,\n 0.438616239f, 0.898674466f,\n 0.449611330f, 0.893224301f,\n 0.460538711f, 0.887639620f,\n 0.471396737f, 0.881921264f,\n 0.482183772f, 0.876070094f,\n 0.492898192f, 0.870086991f,\n 0.503538384f, 0.863972856f,\n 0.514102744f, 0.857728610f,\n 0.524589683f, 0.851355193f,\n 0.534997620f, 0.844853565f,\n 0.545324988f, 0.838224706f,\n 0.555570233f, 0.831469612f,\n 0.565731811f, 0.824589303f,\n 0.575808191f, 0.817584813f,\n 0.585797857f, 0.810457198f,\n 0.595699304f, 0.803207531f,\n 0.605511041f, 0.795836905f,\n 0.615231591f, 0.788346428f,\n 0.624859488f, 0.780737229f,\n 0.634393284f, 0.773010453f,\n 0.643831543f, 0.765167266f,\n 0.653172843f, 0.757208847f,\n 0.662415778f, 0.749136395f,\n 0.671558955f, 0.740951125f,\n 0.680600998f, 0.732654272f,\n 0.689540545f, 0.724247083f,\n 0.698376249f, 0.715730825f,\n 0.707106781f, 0.707106781f,\n 0.715730825f, 0.698376249f,\n 0.724247083f, 0.689540545f,\n 0.732654272f, 0.680600998f,\n 0.740951125f, 0.671558955f,\n 0.749136395f, 0.662415778f,\n 0.757208847f, 0.653172843f,\n 0.765167266f, 0.643831543f,\n 0.773010453f, 0.634393284f,\n 0.780737229f, 0.624859488f,\n 0.788346428f, 0.615231591f,\n 0.795836905f, 0.605511041f,\n 0.803207531f, 0.595699304f,\n 0.810457198f, 0.585797857f,\n 0.817584813f, 0.575808191f,\n 0.824589303f, 0.565731811f,\n 0.831469612f, 0.555570233f,\n 0.838224706f, 0.545324988f,\n 0.844853565f, 0.534997620f,\n 0.851355193f, 0.524589683f,\n 0.857728610f, 0.514102744f,\n 0.863972856f, 0.503538384f,\n 0.870086991f, 0.492898192f,\n 0.876070094f, 0.482183772f,\n 0.881921264f, 0.471396737f,\n 0.887639620f, 0.460538711f,\n 0.893224301f, 0.449611330f,\n 0.898674466f, 0.438616239f,\n 0.903989293f, 0.427555093f,\n 0.909167983f, 0.416429560f,\n 0.914209756f, 0.405241314f,\n 0.919113852f, 0.393992040f,\n 0.923879533f, 0.382683432f,\n 0.928506080f, 0.371317194f,\n 0.932992799f, 0.359895037f,\n 0.937339012f, 0.348418680f,\n 0.941544065f, 0.336889853f,\n 0.945607325f, 0.325310292f,\n 0.949528181f, 0.313681740f,\n 0.953306040f, 0.302005949f,\n 0.956940336f, 0.290284677f,\n 0.960430519f, 0.278519689f,\n 0.963776066f, 0.266712757f,\n 0.966976471f, 0.254865660f,\n 0.970031253f, 0.242980180f,\n 0.972939952f, 0.231058108f,\n 0.975702130f, 0.219101240f,\n 0.978317371f, 0.207111376f,\n 0.980785280f, 0.195090322f,\n 0.983105487f, 0.183039888f,\n 0.985277642f, 0.170961889f,\n 0.987301418f, 0.158858143f,\n 0.989176510f, 0.146730474f,\n 0.990902635f, 0.134580709f,\n 0.992479535f, 0.122410675f,\n 0.993906970f, 0.110222207f,\n 0.995184727f, 0.098017140f,\n 0.996312612f, 0.085797312f,\n 0.997290457f, 0.073564564f,\n 0.998118113f, 0.061320736f,\n 0.998795456f, 0.049067674f,\n 0.999322385f, 0.036807223f,\n 0.999698819f, 0.024541229f,\n 0.999924702f, 0.012271538f,\n 1.000000000f, 0.000000000f,\n 0.999924702f, -0.012271538f,\n 0.999698819f, -0.024541229f,\n 0.999322385f, -0.036807223f,\n 0.998795456f, -0.049067674f,\n 0.998118113f, -0.061320736f,\n 0.997290457f, -0.073564564f,\n 0.996312612f, -0.085797312f,\n 0.995184727f, -0.098017140f,\n 0.993906970f, -0.110222207f,\n 0.992479535f, -0.122410675f,\n 0.990902635f, -0.134580709f,\n 0.989176510f, -0.146730474f,\n 0.987301418f, -0.158858143f,\n 0.985277642f, -0.170961889f,\n 0.983105487f, -0.183039888f,\n 0.980785280f, -0.195090322f,\n 0.978317371f, -0.207111376f,\n 0.975702130f, -0.219101240f,\n 0.972939952f, -0.231058108f,\n 0.970031253f, -0.242980180f,\n 0.966976471f, -0.254865660f,\n 0.963776066f, -0.266712757f,\n 0.960430519f, -0.278519689f,\n 0.956940336f, -0.290284677f,\n 0.953306040f, -0.302005949f,\n 0.949528181f, -0.313681740f,\n 0.945607325f, -0.325310292f,\n 0.941544065f, -0.336889853f,\n 0.937339012f, -0.348418680f,\n 0.932992799f, -0.359895037f,\n 0.928506080f, -0.371317194f,\n 0.923879533f, -0.382683432f,\n 0.919113852f, -0.393992040f,\n 0.914209756f, -0.405241314f,\n 0.909167983f, -0.416429560f,\n 0.903989293f, -0.427555093f,\n 0.898674466f, -0.438616239f,\n 0.893224301f, -0.449611330f,\n 0.887639620f, -0.460538711f,\n 0.881921264f, -0.471396737f,\n 0.876070094f, -0.482183772f,\n 0.870086991f, -0.492898192f,\n 0.863972856f, -0.503538384f,\n 0.857728610f, -0.514102744f,\n 0.851355193f, -0.524589683f,\n 0.844853565f, -0.534997620f,\n 0.838224706f, -0.545324988f,\n 0.831469612f, -0.555570233f,\n 0.824589303f, -0.565731811f,\n 0.817584813f, -0.575808191f,\n 0.810457198f, -0.585797857f,\n 0.803207531f, -0.595699304f,\n 0.795836905f, -0.605511041f,\n 0.788346428f, -0.615231591f,\n 0.780737229f, -0.624859488f,\n 0.773010453f, -0.634393284f,\n 0.765167266f, -0.643831543f,\n 0.757208847f, -0.653172843f,\n 0.749136395f, -0.662415778f,\n 0.740951125f, -0.671558955f,\n 0.732654272f, -0.680600998f,\n 0.724247083f, -0.689540545f,\n 0.715730825f, -0.698376249f,\n 0.707106781f, -0.707106781f,\n 0.698376249f, -0.715730825f,\n 0.689540545f, -0.724247083f,\n 0.680600998f, -0.732654272f,\n 0.671558955f, -0.740951125f,\n 0.662415778f, -0.749136395f,\n 0.653172843f, -0.757208847f,\n 0.643831543f, -0.765167266f,\n 0.634393284f, -0.773010453f,\n 0.624859488f, -0.780737229f,\n 0.615231591f, -0.788346428f,\n 0.605511041f, -0.795836905f,\n 0.595699304f, -0.803207531f,\n 0.585797857f, -0.810457198f,\n 0.575808191f, -0.817584813f,\n 0.565731811f, -0.824589303f,\n 0.555570233f, -0.831469612f,\n 0.545324988f, -0.838224706f,\n 0.534997620f, -0.844853565f,\n 0.524589683f, -0.851355193f,\n 0.514102744f, -0.857728610f,\n 0.503538384f, -0.863972856f,\n 0.492898192f, -0.870086991f,\n 0.482183772f, -0.876070094f,\n 0.471396737f, -0.881921264f,\n 0.460538711f, -0.887639620f,\n 0.449611330f, -0.893224301f,\n 0.438616239f, -0.898674466f,\n 0.427555093f, -0.903989293f,\n 0.416429560f, -0.909167983f,\n 0.405241314f, -0.914209756f,\n 0.393992040f, -0.919113852f,\n 0.382683432f, -0.923879533f,\n 0.371317194f, -0.928506080f,\n 0.359895037f, -0.932992799f,\n 0.348418680f, -0.937339012f,\n 0.336889853f, -0.941544065f,\n 0.325310292f, -0.945607325f,\n 0.313681740f, -0.949528181f,\n 0.302005949f, -0.953306040f,\n 0.290284677f, -0.956940336f,\n 0.278519689f, -0.960430519f,\n 0.266712757f, -0.963776066f,\n 0.254865660f, -0.966976471f,\n 0.242980180f, -0.970031253f,\n 0.231058108f, -0.972939952f,\n 0.219101240f, -0.975702130f,\n 0.207111376f, -0.978317371f,\n 0.195090322f, -0.980785280f,\n 0.183039888f, -0.983105487f,\n 0.170961889f, -0.985277642f,\n 0.158858143f, -0.987301418f,\n 0.146730474f, -0.989176510f,\n 0.134580709f, -0.990902635f,\n 0.122410675f, -0.992479535f,\n 0.110222207f, -0.993906970f,\n 0.098017140f, -0.995184727f,\n 0.085797312f, -0.996312612f,\n 0.073564564f, -0.997290457f,\n 0.061320736f, -0.998118113f,\n 0.049067674f, -0.998795456f,\n 0.036807223f, -0.999322385f,\n 0.024541229f, -0.999698819f,\n 0.012271538f, -0.999924702f\n};\n\nconst float32_t twiddleCoef_rfft_1024[1024] = {\n 0.000000000f, 1.000000000f,\n 0.006135885f, 0.999981175f,\n 0.012271538f, 0.999924702f,\n 0.018406730f, 0.999830582f,\n 0.024541229f, 0.999698819f,\n 0.030674803f, 0.999529418f,\n 0.036807223f, 0.999322385f,\n 0.042938257f, 0.999077728f,\n 0.049067674f, 0.998795456f,\n 0.055195244f, 0.998475581f,\n 0.061320736f, 0.998118113f,\n 0.067443920f, 0.997723067f,\n 0.073564564f, 0.997290457f,\n 0.079682438f, 0.996820299f,\n 0.085797312f, 0.996312612f,\n 0.091908956f, 0.995767414f,\n 0.098017140f, 0.995184727f,\n 0.104121634f, 0.994564571f,\n 0.110222207f, 0.993906970f,\n 0.116318631f, 0.993211949f,\n 0.122410675f, 0.992479535f,\n 0.128498111f, 0.991709754f,\n 0.134580709f, 0.990902635f,\n 0.140658239f, 0.990058210f,\n 0.146730474f, 0.989176510f,\n 0.152797185f, 0.988257568f,\n 0.158858143f, 0.987301418f,\n 0.164913120f, 0.986308097f,\n 0.170961889f, 0.985277642f,\n 0.177004220f, 0.984210092f,\n 0.183039888f, 0.983105487f,\n 0.189068664f, 0.981963869f,\n 0.195090322f, 0.980785280f,\n 0.201104635f, 0.979569766f,\n 0.207111376f, 0.978317371f,\n 0.213110320f, 0.977028143f,\n 0.219101240f, 0.975702130f,\n 0.225083911f, 0.974339383f,\n 0.231058108f, 0.972939952f,\n 0.237023606f, 0.971503891f,\n 0.242980180f, 0.970031253f,\n 0.248927606f, 0.968522094f,\n 0.254865660f, 0.966976471f,\n 0.260794118f, 0.965394442f,\n 0.266712757f, 0.963776066f,\n 0.272621355f, 0.962121404f,\n 0.278519689f, 0.960430519f,\n 0.284407537f, 0.958703475f,\n 0.290284677f, 0.956940336f,\n 0.296150888f, 0.955141168f,\n 0.302005949f, 0.953306040f,\n 0.307849640f, 0.951435021f,\n 0.313681740f, 0.949528181f,\n 0.319502031f, 0.947585591f,\n 0.325310292f, 0.945607325f,\n 0.331106306f, 0.943593458f,\n 0.336889853f, 0.941544065f,\n 0.342660717f, 0.939459224f,\n 0.348418680f, 0.937339012f,\n 0.354163525f, 0.935183510f,\n 0.359895037f, 0.932992799f,\n 0.365612998f, 0.930766961f,\n 0.371317194f, 0.928506080f,\n 0.377007410f, 0.926210242f,\n 0.382683432f, 0.923879533f,\n 0.388345047f, 0.921514039f,\n 0.393992040f, 0.919113852f,\n 0.399624200f, 0.916679060f,\n 0.405241314f, 0.914209756f,\n 0.410843171f, 0.911706032f,\n 0.416429560f, 0.909167983f,\n 0.422000271f, 0.906595705f,\n 0.427555093f, 0.903989293f,\n 0.433093819f, 0.901348847f,\n 0.438616239f, 0.898674466f,\n 0.444122145f, 0.895966250f,\n 0.449611330f, 0.893224301f,\n 0.455083587f, 0.890448723f,\n 0.460538711f, 0.887639620f,\n 0.465976496f, 0.884797098f,\n 0.471396737f, 0.881921264f,\n 0.476799230f, 0.879012226f,\n 0.482183772f, 0.876070094f,\n 0.487550160f, 0.873094978f,\n 0.492898192f, 0.870086991f,\n 0.498227667f, 0.867046246f,\n 0.503538384f, 0.863972856f,\n 0.508830143f, 0.860866939f,\n 0.514102744f, 0.857728610f,\n 0.519355990f, 0.854557988f,\n 0.524589683f, 0.851355193f,\n 0.529803625f, 0.848120345f,\n 0.534997620f, 0.844853565f,\n 0.540171473f, 0.841554977f,\n 0.545324988f, 0.838224706f,\n 0.550457973f, 0.834862875f,\n 0.555570233f, 0.831469612f,\n 0.560661576f, 0.828045045f,\n 0.565731811f, 0.824589303f,\n 0.570780746f, 0.821102515f,\n 0.575808191f, 0.817584813f,\n 0.580813958f, 0.814036330f,\n 0.585797857f, 0.810457198f,\n 0.590759702f, 0.806847554f,\n 0.595699304f, 0.803207531f,\n 0.600616479f, 0.799537269f,\n 0.605511041f, 0.795836905f,\n 0.610382806f, 0.792106577f,\n 0.615231591f, 0.788346428f,\n 0.620057212f, 0.784556597f,\n 0.624859488f, 0.780737229f,\n 0.629638239f, 0.776888466f,\n 0.634393284f, 0.773010453f,\n 0.639124445f, 0.769103338f,\n 0.643831543f, 0.765167266f,\n 0.648514401f, 0.761202385f,\n 0.653172843f, 0.757208847f,\n 0.657806693f, 0.753186799f,\n 0.662415778f, 0.749136395f,\n 0.666999922f, 0.745057785f,\n 0.671558955f, 0.740951125f,\n 0.676092704f, 0.736816569f,\n 0.680600998f, 0.732654272f,\n 0.685083668f, 0.728464390f,\n 0.689540545f, 0.724247083f,\n 0.693971461f, 0.720002508f,\n 0.698376249f, 0.715730825f,\n 0.702754744f, 0.711432196f,\n 0.707106781f, 0.707106781f,\n 0.711432196f, 0.702754744f,\n 0.715730825f, 0.698376249f,\n 0.720002508f, 0.693971461f,\n 0.724247083f, 0.689540545f,\n 0.728464390f, 0.685083668f,\n 0.732654272f, 0.680600998f,\n 0.736816569f, 0.676092704f,\n 0.740951125f, 0.671558955f,\n 0.745057785f, 0.666999922f,\n 0.749136395f, 0.662415778f,\n 0.753186799f, 0.657806693f,\n 0.757208847f, 0.653172843f,\n 0.761202385f, 0.648514401f,\n 0.765167266f, 0.643831543f,\n 0.769103338f, 0.639124445f,\n 0.773010453f, 0.634393284f,\n 0.776888466f, 0.629638239f,\n 0.780737229f, 0.624859488f,\n 0.784556597f, 0.620057212f,\n 0.788346428f, 0.615231591f,\n 0.792106577f, 0.610382806f,\n 0.795836905f, 0.605511041f,\n 0.799537269f, 0.600616479f,\n 0.803207531f, 0.595699304f,\n 0.806847554f, 0.590759702f,\n 0.810457198f, 0.585797857f,\n 0.814036330f, 0.580813958f,\n 0.817584813f, 0.575808191f,\n 0.821102515f, 0.570780746f,\n 0.824589303f, 0.565731811f,\n 0.828045045f, 0.560661576f,\n 0.831469612f, 0.555570233f,\n 0.834862875f, 0.550457973f,\n 0.838224706f, 0.545324988f,\n 0.841554977f, 0.540171473f,\n 0.844853565f, 0.534997620f,\n 0.848120345f, 0.529803625f,\n 0.851355193f, 0.524589683f,\n 0.854557988f, 0.519355990f,\n 0.857728610f, 0.514102744f,\n 0.860866939f, 0.508830143f,\n 0.863972856f, 0.503538384f,\n 0.867046246f, 0.498227667f,\n 0.870086991f, 0.492898192f,\n 0.873094978f, 0.487550160f,\n 0.876070094f, 0.482183772f,\n 0.879012226f, 0.476799230f,\n 0.881921264f, 0.471396737f,\n 0.884797098f, 0.465976496f,\n 0.887639620f, 0.460538711f,\n 0.890448723f, 0.455083587f,\n 0.893224301f, 0.449611330f,\n 0.895966250f, 0.444122145f,\n 0.898674466f, 0.438616239f,\n 0.901348847f, 0.433093819f,\n 0.903989293f, 0.427555093f,\n 0.906595705f, 0.422000271f,\n 0.909167983f, 0.416429560f,\n 0.911706032f, 0.410843171f,\n 0.914209756f, 0.405241314f,\n 0.916679060f, 0.399624200f,\n 0.919113852f, 0.393992040f,\n 0.921514039f, 0.388345047f,\n 0.923879533f, 0.382683432f,\n 0.926210242f, 0.377007410f,\n 0.928506080f, 0.371317194f,\n 0.930766961f, 0.365612998f,\n 0.932992799f, 0.359895037f,\n 0.935183510f, 0.354163525f,\n 0.937339012f, 0.348418680f,\n 0.939459224f, 0.342660717f,\n 0.941544065f, 0.336889853f,\n 0.943593458f, 0.331106306f,\n 0.945607325f, 0.325310292f,\n 0.947585591f, 0.319502031f,\n 0.949528181f, 0.313681740f,\n 0.951435021f, 0.307849640f,\n 0.953306040f, 0.302005949f,\n 0.955141168f, 0.296150888f,\n 0.956940336f, 0.290284677f,\n 0.958703475f, 0.284407537f,\n 0.960430519f, 0.278519689f,\n 0.962121404f, 0.272621355f,\n 0.963776066f, 0.266712757f,\n 0.965394442f, 0.260794118f,\n 0.966976471f, 0.254865660f,\n 0.968522094f, 0.248927606f,\n 0.970031253f, 0.242980180f,\n 0.971503891f, 0.237023606f,\n 0.972939952f, 0.231058108f,\n 0.974339383f, 0.225083911f,\n 0.975702130f, 0.219101240f,\n 0.977028143f, 0.213110320f,\n 0.978317371f, 0.207111376f,\n 0.979569766f, 0.201104635f,\n 0.980785280f, 0.195090322f,\n 0.981963869f, 0.189068664f,\n 0.983105487f, 0.183039888f,\n 0.984210092f, 0.177004220f,\n 0.985277642f, 0.170961889f,\n 0.986308097f, 0.164913120f,\n 0.987301418f, 0.158858143f,\n 0.988257568f, 0.152797185f,\n 0.989176510f, 0.146730474f,\n 0.990058210f, 0.140658239f,\n 0.990902635f, 0.134580709f,\n 0.991709754f, 0.128498111f,\n 0.992479535f, 0.122410675f,\n 0.993211949f, 0.116318631f,\n 0.993906970f, 0.110222207f,\n 0.994564571f, 0.104121634f,\n 0.995184727f, 0.098017140f,\n 0.995767414f, 0.091908956f,\n 0.996312612f, 0.085797312f,\n 0.996820299f, 0.079682438f,\n 0.997290457f, 0.073564564f,\n 0.997723067f, 0.067443920f,\n 0.998118113f, 0.061320736f,\n 0.998475581f, 0.055195244f,\n 0.998795456f, 0.049067674f,\n 0.999077728f, 0.042938257f,\n 0.999322385f, 0.036807223f,\n 0.999529418f, 0.030674803f,\n 0.999698819f, 0.024541229f,\n 0.999830582f, 0.018406730f,\n 0.999924702f, 0.012271538f,\n 0.999981175f, 0.006135885f,\n 1.000000000f, 0.000000000f,\n 0.999981175f, -0.006135885f,\n 0.999924702f, -0.012271538f,\n 0.999830582f, -0.018406730f,\n 0.999698819f, -0.024541229f,\n 0.999529418f, -0.030674803f,\n 0.999322385f, -0.036807223f,\n 0.999077728f, -0.042938257f,\n 0.998795456f, -0.049067674f,\n 0.998475581f, -0.055195244f,\n 0.998118113f, -0.061320736f,\n 0.997723067f, -0.067443920f,\n 0.997290457f, -0.073564564f,\n 0.996820299f, -0.079682438f,\n 0.996312612f, -0.085797312f,\n 0.995767414f, -0.091908956f,\n 0.995184727f, -0.098017140f,\n 0.994564571f, -0.104121634f,\n 0.993906970f, -0.110222207f,\n 0.993211949f, -0.116318631f,\n 0.992479535f, -0.122410675f,\n 0.991709754f, -0.128498111f,\n 0.990902635f, -0.134580709f,\n 0.990058210f, -0.140658239f,\n 0.989176510f, -0.146730474f,\n 0.988257568f, -0.152797185f,\n 0.987301418f, -0.158858143f,\n 0.986308097f, -0.164913120f,\n 0.985277642f, -0.170961889f,\n 0.984210092f, -0.177004220f,\n 0.983105487f, -0.183039888f,\n 0.981963869f, -0.189068664f,\n 0.980785280f, -0.195090322f,\n 0.979569766f, -0.201104635f,\n 0.978317371f, -0.207111376f,\n 0.977028143f, -0.213110320f,\n 0.975702130f, -0.219101240f,\n 0.974339383f, -0.225083911f,\n 0.972939952f, -0.231058108f,\n 0.971503891f, -0.237023606f,\n 0.970031253f, -0.242980180f,\n 0.968522094f, -0.248927606f,\n 0.966976471f, -0.254865660f,\n 0.965394442f, -0.260794118f,\n 0.963776066f, -0.266712757f,\n 0.962121404f, -0.272621355f,\n 0.960430519f, -0.278519689f,\n 0.958703475f, -0.284407537f,\n 0.956940336f, -0.290284677f,\n 0.955141168f, -0.296150888f,\n 0.953306040f, -0.302005949f,\n 0.951435021f, -0.307849640f,\n 0.949528181f, -0.313681740f,\n 0.947585591f, -0.319502031f,\n 0.945607325f, -0.325310292f,\n 0.943593458f, -0.331106306f,\n 0.941544065f, -0.336889853f,\n 0.939459224f, -0.342660717f,\n 0.937339012f, -0.348418680f,\n 0.935183510f, -0.354163525f,\n 0.932992799f, -0.359895037f,\n 0.930766961f, -0.365612998f,\n 0.928506080f, -0.371317194f,\n 0.926210242f, -0.377007410f,\n 0.923879533f, -0.382683432f,\n 0.921514039f, -0.388345047f,\n 0.919113852f, -0.393992040f,\n 0.916679060f, -0.399624200f,\n 0.914209756f, -0.405241314f,\n 0.911706032f, -0.410843171f,\n 0.909167983f, -0.416429560f,\n 0.906595705f, -0.422000271f,\n 0.903989293f, -0.427555093f,\n 0.901348847f, -0.433093819f,\n 0.898674466f, -0.438616239f,\n 0.895966250f, -0.444122145f,\n 0.893224301f, -0.449611330f,\n 0.890448723f, -0.455083587f,\n 0.887639620f, -0.460538711f,\n 0.884797098f, -0.465976496f,\n 0.881921264f, -0.471396737f,\n 0.879012226f, -0.476799230f,\n 0.876070094f, -0.482183772f,\n 0.873094978f, -0.487550160f,\n 0.870086991f, -0.492898192f,\n 0.867046246f, -0.498227667f,\n 0.863972856f, -0.503538384f,\n 0.860866939f, -0.508830143f,\n 0.857728610f, -0.514102744f,\n 0.854557988f, -0.519355990f,\n 0.851355193f, -0.524589683f,\n 0.848120345f, -0.529803625f,\n 0.844853565f, -0.534997620f,\n 0.841554977f, -0.540171473f,\n 0.838224706f, -0.545324988f,\n 0.834862875f, -0.550457973f,\n 0.831469612f, -0.555570233f,\n 0.828045045f, -0.560661576f,\n 0.824589303f, -0.565731811f,\n 0.821102515f, -0.570780746f,\n 0.817584813f, -0.575808191f,\n 0.814036330f, -0.580813958f,\n 0.810457198f, -0.585797857f,\n 0.806847554f, -0.590759702f,\n 0.803207531f, -0.595699304f,\n 0.799537269f, -0.600616479f,\n 0.795836905f, -0.605511041f,\n 0.792106577f, -0.610382806f,\n 0.788346428f, -0.615231591f,\n 0.784556597f, -0.620057212f,\n 0.780737229f, -0.624859488f,\n 0.776888466f, -0.629638239f,\n 0.773010453f, -0.634393284f,\n 0.769103338f, -0.639124445f,\n 0.765167266f, -0.643831543f,\n 0.761202385f, -0.648514401f,\n 0.757208847f, -0.653172843f,\n 0.753186799f, -0.657806693f,\n 0.749136395f, -0.662415778f,\n 0.745057785f, -0.666999922f,\n 0.740951125f, -0.671558955f,\n 0.736816569f, -0.676092704f,\n 0.732654272f, -0.680600998f,\n 0.728464390f, -0.685083668f,\n 0.724247083f, -0.689540545f,\n 0.720002508f, -0.693971461f,\n 0.715730825f, -0.698376249f,\n 0.711432196f, -0.702754744f,\n 0.707106781f, -0.707106781f,\n 0.702754744f, -0.711432196f,\n 0.698376249f, -0.715730825f,\n 0.693971461f, -0.720002508f,\n 0.689540545f, -0.724247083f,\n 0.685083668f, -0.728464390f,\n 0.680600998f, -0.732654272f,\n 0.676092704f, -0.736816569f,\n 0.671558955f, -0.740951125f,\n 0.666999922f, -0.745057785f,\n 0.662415778f, -0.749136395f,\n 0.657806693f, -0.753186799f,\n 0.653172843f, -0.757208847f,\n 0.648514401f, -0.761202385f,\n 0.643831543f, -0.765167266f,\n 0.639124445f, -0.769103338f,\n 0.634393284f, -0.773010453f,\n 0.629638239f, -0.776888466f,\n 0.624859488f, -0.780737229f,\n 0.620057212f, -0.784556597f,\n 0.615231591f, -0.788346428f,\n 0.610382806f, -0.792106577f,\n 0.605511041f, -0.795836905f,\n 0.600616479f, -0.799537269f,\n 0.595699304f, -0.803207531f,\n 0.590759702f, -0.806847554f,\n 0.585797857f, -0.810457198f,\n 0.580813958f, -0.814036330f,\n 0.575808191f, -0.817584813f,\n 0.570780746f, -0.821102515f,\n 0.565731811f, -0.824589303f,\n 0.560661576f, -0.828045045f,\n 0.555570233f, -0.831469612f,\n 0.550457973f, -0.834862875f,\n 0.545324988f, -0.838224706f,\n 0.540171473f, -0.841554977f,\n 0.534997620f, -0.844853565f,\n 0.529803625f, -0.848120345f,\n 0.524589683f, -0.851355193f,\n 0.519355990f, -0.854557988f,\n 0.514102744f, -0.857728610f,\n 0.508830143f, -0.860866939f,\n 0.503538384f, -0.863972856f,\n 0.498227667f, -0.867046246f,\n 0.492898192f, -0.870086991f,\n 0.487550160f, -0.873094978f,\n 0.482183772f, -0.876070094f,\n 0.476799230f, -0.879012226f,\n 0.471396737f, -0.881921264f,\n 0.465976496f, -0.884797098f,\n 0.460538711f, -0.887639620f,\n 0.455083587f, -0.890448723f,\n 0.449611330f, -0.893224301f,\n 0.444122145f, -0.895966250f,\n 0.438616239f, -0.898674466f,\n 0.433093819f, -0.901348847f,\n 0.427555093f, -0.903989293f,\n 0.422000271f, -0.906595705f,\n 0.416429560f, -0.909167983f,\n 0.410843171f, -0.911706032f,\n 0.405241314f, -0.914209756f,\n 0.399624200f, -0.916679060f,\n 0.393992040f, -0.919113852f,\n 0.388345047f, -0.921514039f,\n 0.382683432f, -0.923879533f,\n 0.377007410f, -0.926210242f,\n 0.371317194f, -0.928506080f,\n 0.365612998f, -0.930766961f,\n 0.359895037f, -0.932992799f,\n 0.354163525f, -0.935183510f,\n 0.348418680f, -0.937339012f,\n 0.342660717f, -0.939459224f,\n 0.336889853f, -0.941544065f,\n 0.331106306f, -0.943593458f,\n 0.325310292f, -0.945607325f,\n 0.319502031f, -0.947585591f,\n 0.313681740f, -0.949528181f,\n 0.307849640f, -0.951435021f,\n 0.302005949f, -0.953306040f,\n 0.296150888f, -0.955141168f,\n 0.290284677f, -0.956940336f,\n 0.284407537f, -0.958703475f,\n 0.278519689f, -0.960430519f,\n 0.272621355f, -0.962121404f,\n 0.266712757f, -0.963776066f,\n 0.260794118f, -0.965394442f,\n 0.254865660f, -0.966976471f,\n 0.248927606f, -0.968522094f,\n 0.242980180f, -0.970031253f,\n 0.237023606f, -0.971503891f,\n 0.231058108f, -0.972939952f,\n 0.225083911f, -0.974339383f,\n 0.219101240f, -0.975702130f,\n 0.213110320f, -0.977028143f,\n 0.207111376f, -0.978317371f,\n 0.201104635f, -0.979569766f,\n 0.195090322f, -0.980785280f,\n 0.189068664f, -0.981963869f,\n 0.183039888f, -0.983105487f,\n 0.177004220f, -0.984210092f,\n 0.170961889f, -0.985277642f,\n 0.164913120f, -0.986308097f,\n 0.158858143f, -0.987301418f,\n 0.152797185f, -0.988257568f,\n 0.146730474f, -0.989176510f,\n 0.140658239f, -0.990058210f,\n 0.134580709f, -0.990902635f,\n 0.128498111f, -0.991709754f,\n 0.122410675f, -0.992479535f,\n 0.116318631f, -0.993211949f,\n 0.110222207f, -0.993906970f,\n 0.104121634f, -0.994564571f,\n 0.098017140f, -0.995184727f,\n 0.091908956f, -0.995767414f,\n 0.085797312f, -0.996312612f,\n 0.079682438f, -0.996820299f,\n 0.073564564f, -0.997290457f,\n 0.067443920f, -0.997723067f,\n 0.061320736f, -0.998118113f,\n 0.055195244f, -0.998475581f,\n 0.049067674f, -0.998795456f,\n 0.042938257f, -0.999077728f,\n 0.036807223f, -0.999322385f,\n 0.030674803f, -0.999529418f,\n 0.024541229f, -0.999698819f,\n 0.018406730f, -0.999830582f,\n 0.012271538f, -0.999924702f,\n 0.006135885f, -0.999981175f\n};\n\nconst float32_t twiddleCoef_rfft_2048[2048] = {\n 0.000000000f, 1.000000000f,\n 0.003067957f, 0.999995294f,\n 0.006135885f, 0.999981175f,\n 0.009203755f, 0.999957645f,\n 0.012271538f, 0.999924702f,\n 0.015339206f, 0.999882347f,\n 0.018406730f, 0.999830582f,\n 0.021474080f, 0.999769405f,\n 0.024541229f, 0.999698819f,\n 0.027608146f, 0.999618822f,\n 0.030674803f, 0.999529418f,\n 0.033741172f, 0.999430605f,\n 0.036807223f, 0.999322385f,\n 0.039872928f, 0.999204759f,\n 0.042938257f, 0.999077728f,\n 0.046003182f, 0.998941293f,\n 0.049067674f, 0.998795456f,\n 0.052131705f, 0.998640218f,\n 0.055195244f, 0.998475581f,\n 0.058258265f, 0.998301545f,\n 0.061320736f, 0.998118113f,\n 0.064382631f, 0.997925286f,\n 0.067443920f, 0.997723067f,\n 0.070504573f, 0.997511456f,\n 0.073564564f, 0.997290457f,\n 0.076623861f, 0.997060070f,\n 0.079682438f, 0.996820299f,\n 0.082740265f, 0.996571146f,\n 0.085797312f, 0.996312612f,\n 0.088853553f, 0.996044701f,\n 0.091908956f, 0.995767414f,\n 0.094963495f, 0.995480755f,\n 0.098017140f, 0.995184727f,\n 0.101069863f, 0.994879331f,\n 0.104121634f, 0.994564571f,\n 0.107172425f, 0.994240449f,\n 0.110222207f, 0.993906970f,\n 0.113270952f, 0.993564136f,\n 0.116318631f, 0.993211949f,\n 0.119365215f, 0.992850414f,\n 0.122410675f, 0.992479535f,\n 0.125454983f, 0.992099313f,\n 0.128498111f, 0.991709754f,\n 0.131540029f, 0.991310860f,\n 0.134580709f, 0.990902635f,\n 0.137620122f, 0.990485084f,\n 0.140658239f, 0.990058210f,\n 0.143695033f, 0.989622017f,\n 0.146730474f, 0.989176510f,\n 0.149764535f, 0.988721692f,\n 0.152797185f, 0.988257568f,\n 0.155828398f, 0.987784142f,\n 0.158858143f, 0.987301418f,\n 0.161886394f, 0.986809402f,\n 0.164913120f, 0.986308097f,\n 0.167938295f, 0.985797509f,\n 0.170961889f, 0.985277642f,\n 0.173983873f, 0.984748502f,\n 0.177004220f, 0.984210092f,\n 0.180022901f, 0.983662419f,\n 0.183039888f, 0.983105487f,\n 0.186055152f, 0.982539302f,\n 0.189068664f, 0.981963869f,\n 0.192080397f, 0.981379193f,\n 0.195090322f, 0.980785280f,\n 0.198098411f, 0.980182136f,\n 0.201104635f, 0.979569766f,\n 0.204108966f, 0.978948175f,\n 0.207111376f, 0.978317371f,\n 0.210111837f, 0.977677358f,\n 0.213110320f, 0.977028143f,\n 0.216106797f, 0.976369731f,\n 0.219101240f, 0.975702130f,\n 0.222093621f, 0.975025345f,\n 0.225083911f, 0.974339383f,\n 0.228072083f, 0.973644250f,\n 0.231058108f, 0.972939952f,\n 0.234041959f, 0.972226497f,\n 0.237023606f, 0.971503891f,\n 0.240003022f, 0.970772141f,\n 0.242980180f, 0.970031253f,\n 0.245955050f, 0.969281235f,\n 0.248927606f, 0.968522094f,\n 0.251897818f, 0.967753837f,\n 0.254865660f, 0.966976471f,\n 0.257831102f, 0.966190003f,\n 0.260794118f, 0.965394442f,\n 0.263754679f, 0.964589793f,\n 0.266712757f, 0.963776066f,\n 0.269668326f, 0.962953267f,\n 0.272621355f, 0.962121404f,\n 0.275571819f, 0.961280486f,\n 0.278519689f, 0.960430519f,\n 0.281464938f, 0.959571513f,\n 0.284407537f, 0.958703475f,\n 0.287347460f, 0.957826413f,\n 0.290284677f, 0.956940336f,\n 0.293219163f, 0.956045251f,\n 0.296150888f, 0.955141168f,\n 0.299079826f, 0.954228095f,\n 0.302005949f, 0.953306040f,\n 0.304929230f, 0.952375013f,\n 0.307849640f, 0.951435021f,\n 0.310767153f, 0.950486074f,\n 0.313681740f, 0.949528181f,\n 0.316593376f, 0.948561350f,\n 0.319502031f, 0.947585591f,\n 0.322407679f, 0.946600913f,\n 0.325310292f, 0.945607325f,\n 0.328209844f, 0.944604837f,\n 0.331106306f, 0.943593458f,\n 0.333999651f, 0.942573198f,\n 0.336889853f, 0.941544065f,\n 0.339776884f, 0.940506071f,\n 0.342660717f, 0.939459224f,\n 0.345541325f, 0.938403534f,\n 0.348418680f, 0.937339012f,\n 0.351292756f, 0.936265667f,\n 0.354163525f, 0.935183510f,\n 0.357030961f, 0.934092550f,\n 0.359895037f, 0.932992799f,\n 0.362755724f, 0.931884266f,\n 0.365612998f, 0.930766961f,\n 0.368466830f, 0.929640896f,\n 0.371317194f, 0.928506080f,\n 0.374164063f, 0.927362526f,\n 0.377007410f, 0.926210242f,\n 0.379847209f, 0.925049241f,\n 0.382683432f, 0.923879533f,\n 0.385516054f, 0.922701128f,\n 0.388345047f, 0.921514039f,\n 0.391170384f, 0.920318277f,\n 0.393992040f, 0.919113852f,\n 0.396809987f, 0.917900776f,\n 0.399624200f, 0.916679060f,\n 0.402434651f, 0.915448716f,\n 0.405241314f, 0.914209756f,\n 0.408044163f, 0.912962190f,\n 0.410843171f, 0.911706032f,\n 0.413638312f, 0.910441292f,\n 0.416429560f, 0.909167983f,\n 0.419216888f, 0.907886116f,\n 0.422000271f, 0.906595705f,\n 0.424779681f, 0.905296759f,\n 0.427555093f, 0.903989293f,\n 0.430326481f, 0.902673318f,\n 0.433093819f, 0.901348847f,\n 0.435857080f, 0.900015892f,\n 0.438616239f, 0.898674466f,\n 0.441371269f, 0.897324581f,\n 0.444122145f, 0.895966250f,\n 0.446868840f, 0.894599486f,\n 0.449611330f, 0.893224301f,\n 0.452349587f, 0.891840709f,\n 0.455083587f, 0.890448723f,\n 0.457813304f, 0.889048356f,\n 0.460538711f, 0.887639620f,\n 0.463259784f, 0.886222530f,\n 0.465976496f, 0.884797098f,\n 0.468688822f, 0.883363339f,\n 0.471396737f, 0.881921264f,\n 0.474100215f, 0.880470889f,\n 0.476799230f, 0.879012226f,\n 0.479493758f, 0.877545290f,\n 0.482183772f, 0.876070094f,\n 0.484869248f, 0.874586652f,\n 0.487550160f, 0.873094978f,\n 0.490226483f, 0.871595087f,\n 0.492898192f, 0.870086991f,\n 0.495565262f, 0.868570706f,\n 0.498227667f, 0.867046246f,\n 0.500885383f, 0.865513624f,\n 0.503538384f, 0.863972856f,\n 0.506186645f, 0.862423956f,\n 0.508830143f, 0.860866939f,\n 0.511468850f, 0.859301818f,\n 0.514102744f, 0.857728610f,\n 0.516731799f, 0.856147328f,\n 0.519355990f, 0.854557988f,\n 0.521975293f, 0.852960605f,\n 0.524589683f, 0.851355193f,\n 0.527199135f, 0.849741768f,\n 0.529803625f, 0.848120345f,\n 0.532403128f, 0.846490939f,\n 0.534997620f, 0.844853565f,\n 0.537587076f, 0.843208240f,\n 0.540171473f, 0.841554977f,\n 0.542750785f, 0.839893794f,\n 0.545324988f, 0.838224706f,\n 0.547894059f, 0.836547727f,\n 0.550457973f, 0.834862875f,\n 0.553016706f, 0.833170165f,\n 0.555570233f, 0.831469612f,\n 0.558118531f, 0.829761234f,\n 0.560661576f, 0.828045045f,\n 0.563199344f, 0.826321063f,\n 0.565731811f, 0.824589303f,\n 0.568258953f, 0.822849781f,\n 0.570780746f, 0.821102515f,\n 0.573297167f, 0.819347520f,\n 0.575808191f, 0.817584813f,\n 0.578313796f, 0.815814411f,\n 0.580813958f, 0.814036330f,\n 0.583308653f, 0.812250587f,\n 0.585797857f, 0.810457198f,\n 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-0.947585591f,\n 0.316593376f, -0.948561350f,\n 0.313681740f, -0.949528181f,\n 0.310767153f, -0.950486074f,\n 0.307849640f, -0.951435021f,\n 0.304929230f, -0.952375013f,\n 0.302005949f, -0.953306040f,\n 0.299079826f, -0.954228095f,\n 0.296150888f, -0.955141168f,\n 0.293219163f, -0.956045251f,\n 0.290284677f, -0.956940336f,\n 0.287347460f, -0.957826413f,\n 0.284407537f, -0.958703475f,\n 0.281464938f, -0.959571513f,\n 0.278519689f, -0.960430519f,\n 0.275571819f, -0.961280486f,\n 0.272621355f, -0.962121404f,\n 0.269668326f, -0.962953267f,\n 0.266712757f, -0.963776066f,\n 0.263754679f, -0.964589793f,\n 0.260794118f, -0.965394442f,\n 0.257831102f, -0.966190003f,\n 0.254865660f, -0.966976471f,\n 0.251897818f, -0.967753837f,\n 0.248927606f, -0.968522094f,\n 0.245955050f, -0.969281235f,\n 0.242980180f, -0.970031253f,\n 0.240003022f, -0.970772141f,\n 0.237023606f, -0.971503891f,\n 0.234041959f, -0.972226497f,\n 0.231058108f, -0.972939952f,\n 0.228072083f, -0.973644250f,\n 0.225083911f, -0.974339383f,\n 0.222093621f, -0.975025345f,\n 0.219101240f, -0.975702130f,\n 0.216106797f, -0.976369731f,\n 0.213110320f, -0.977028143f,\n 0.210111837f, -0.977677358f,\n 0.207111376f, -0.978317371f,\n 0.204108966f, -0.978948175f,\n 0.201104635f, -0.979569766f,\n 0.198098411f, -0.980182136f,\n 0.195090322f, -0.980785280f,\n 0.192080397f, -0.981379193f,\n 0.189068664f, -0.981963869f,\n 0.186055152f, -0.982539302f,\n 0.183039888f, -0.983105487f,\n 0.180022901f, -0.983662419f,\n 0.177004220f, -0.984210092f,\n 0.173983873f, -0.984748502f,\n 0.170961889f, -0.985277642f,\n 0.167938295f, -0.985797509f,\n 0.164913120f, -0.986308097f,\n 0.161886394f, -0.986809402f,\n 0.158858143f, -0.987301418f,\n 0.155828398f, -0.987784142f,\n 0.152797185f, -0.988257568f,\n 0.149764535f, -0.988721692f,\n 0.146730474f, -0.989176510f,\n 0.143695033f, -0.989622017f,\n 0.140658239f, -0.990058210f,\n 0.137620122f, -0.990485084f,\n 0.134580709f, -0.990902635f,\n 0.131540029f, -0.991310860f,\n 0.128498111f, -0.991709754f,\n 0.125454983f, -0.992099313f,\n 0.122410675f, -0.992479535f,\n 0.119365215f, -0.992850414f,\n 0.116318631f, -0.993211949f,\n 0.113270952f, -0.993564136f,\n 0.110222207f, -0.993906970f,\n 0.107172425f, -0.994240449f,\n 0.104121634f, -0.994564571f,\n 0.101069863f, -0.994879331f,\n 0.098017140f, -0.995184727f,\n 0.094963495f, -0.995480755f,\n 0.091908956f, -0.995767414f,\n 0.088853553f, -0.996044701f,\n 0.085797312f, -0.996312612f,\n 0.082740265f, -0.996571146f,\n 0.079682438f, -0.996820299f,\n 0.076623861f, -0.997060070f,\n 0.073564564f, -0.997290457f,\n 0.070504573f, -0.997511456f,\n 0.067443920f, -0.997723067f,\n 0.064382631f, -0.997925286f,\n 0.061320736f, -0.998118113f,\n 0.058258265f, -0.998301545f,\n 0.055195244f, -0.998475581f,\n 0.052131705f, -0.998640218f,\n 0.049067674f, -0.998795456f,\n 0.046003182f, -0.998941293f,\n 0.042938257f, -0.999077728f,\n 0.039872928f, -0.999204759f,\n 0.036807223f, -0.999322385f,\n 0.033741172f, -0.999430605f,\n 0.030674803f, -0.999529418f,\n 0.027608146f, -0.999618822f,\n 0.024541229f, -0.999698819f,\n 0.021474080f, -0.999769405f,\n 0.018406730f, -0.999830582f,\n 0.015339206f, -0.999882347f,\n 0.012271538f, -0.999924702f,\n 0.009203755f, -0.999957645f,\n 0.006135885f, -0.999981175f,\n 0.003067957f, -0.999995294f\n};\n\nconst float32_t twiddleCoef_rfft_4096[4096] = {\n 0.000000000f, 1.000000000f,\n 0.001533980f, 0.999998823f,\n 0.003067957f, 0.999995294f,\n 0.004601926f, 0.999989411f,\n 0.006135885f, 0.999981175f,\n 0.007669829f, 0.999970586f,\n 0.009203755f, 0.999957645f,\n 0.010737659f, 0.999942350f,\n 0.012271538f, 0.999924702f,\n 0.013805389f, 0.999904701f,\n 0.015339206f, 0.999882347f,\n 0.016872988f, 0.999857641f,\n 0.018406730f, 0.999830582f,\n 0.019940429f, 0.999801170f,\n 0.021474080f, 0.999769405f,\n 0.023007681f, 0.999735288f,\n 0.024541229f, 0.999698819f,\n 0.026074718f, 0.999659997f,\n 0.027608146f, 0.999618822f,\n 0.029141509f, 0.999575296f,\n 0.030674803f, 0.999529418f,\n 0.032208025f, 0.999481187f,\n 0.033741172f, 0.999430605f,\n 0.035274239f, 0.999377670f,\n 0.036807223f, 0.999322385f,\n 0.038340120f, 0.999264747f,\n 0.039872928f, 0.999204759f,\n 0.041405641f, 0.999142419f,\n 0.042938257f, 0.999077728f,\n 0.044470772f, 0.999010686f,\n 0.046003182f, 0.998941293f,\n 0.047535484f, 0.998869550f,\n 0.049067674f, 0.998795456f,\n 0.050599749f, 0.998719012f,\n 0.052131705f, 0.998640218f,\n 0.053663538f, 0.998559074f,\n 0.055195244f, 0.998475581f,\n 0.056726821f, 0.998389737f,\n 0.058258265f, 0.998301545f,\n 0.059789571f, 0.998211003f,\n 0.061320736f, 0.998118113f,\n 0.062851758f, 0.998022874f,\n 0.064382631f, 0.997925286f,\n 0.065913353f, 0.997825350f,\n 0.067443920f, 0.997723067f,\n 0.068974328f, 0.997618435f,\n 0.070504573f, 0.997511456f,\n 0.072034653f, 0.997402130f,\n 0.073564564f, 0.997290457f,\n 0.075094301f, 0.997176437f,\n 0.076623861f, 0.997060070f,\n 0.078153242f, 0.996941358f,\n 0.079682438f, 0.996820299f,\n 0.081211447f, 0.996696895f,\n 0.082740265f, 0.996571146f,\n 0.084268888f, 0.996443051f,\n 0.085797312f, 0.996312612f,\n 0.087325535f, 0.996179829f,\n 0.088853553f, 0.996044701f,\n 0.090381361f, 0.995907229f,\n 0.091908956f, 0.995767414f,\n 0.093436336f, 0.995625256f,\n 0.094963495f, 0.995480755f,\n 0.096490431f, 0.995333912f,\n 0.098017140f, 0.995184727f,\n 0.099543619f, 0.995033199f,\n 0.101069863f, 0.994879331f,\n 0.102595869f, 0.994723121f,\n 0.104121634f, 0.994564571f,\n 0.105647154f, 0.994403680f,\n 0.107172425f, 0.994240449f,\n 0.108697444f, 0.994074879f,\n 0.110222207f, 0.993906970f,\n 0.111746711f, 0.993736722f,\n 0.113270952f, 0.993564136f,\n 0.114794927f, 0.993389211f,\n 0.116318631f, 0.993211949f,\n 0.117842062f, 0.993032350f,\n 0.119365215f, 0.992850414f,\n 0.120888087f, 0.992666142f,\n 0.122410675f, 0.992479535f,\n 0.123932975f, 0.992290591f,\n 0.125454983f, 0.992099313f,\n 0.126976696f, 0.991905700f,\n 0.128498111f, 0.991709754f,\n 0.130019223f, 0.991511473f,\n 0.131540029f, 0.991310860f,\n 0.133060525f, 0.991107914f,\n 0.134580709f, 0.990902635f,\n 0.136100575f, 0.990695025f,\n 0.137620122f, 0.990485084f,\n 0.139139344f, 0.990272812f,\n 0.140658239f, 0.990058210f,\n 0.142176804f, 0.989841278f,\n 0.143695033f, 0.989622017f,\n 0.145212925f, 0.989400428f,\n 0.146730474f, 0.989176510f,\n 0.148247679f, 0.988950265f,\n 0.149764535f, 0.988721692f,\n 0.151281038f, 0.988490793f,\n 0.152797185f, 0.988257568f,\n 0.154312973f, 0.988022017f,\n 0.155828398f, 0.987784142f,\n 0.157343456f, 0.987543942f,\n 0.158858143f, 0.987301418f,\n 0.160372457f, 0.987056571f,\n 0.161886394f, 0.986809402f,\n 0.163399949f, 0.986559910f,\n 0.164913120f, 0.986308097f,\n 0.166425904f, 0.986053963f,\n 0.167938295f, 0.985797509f,\n 0.169450291f, 0.985538735f,\n 0.170961889f, 0.985277642f,\n 0.172473084f, 0.985014231f,\n 0.173983873f, 0.984748502f,\n 0.175494253f, 0.984480455f,\n 0.177004220f, 0.984210092f,\n 0.178513771f, 0.983937413f,\n 0.180022901f, 0.983662419f,\n 0.181531608f, 0.983385110f,\n 0.183039888f, 0.983105487f,\n 0.184547737f, 0.982823551f,\n 0.186055152f, 0.982539302f,\n 0.187562129f, 0.982252741f,\n 0.189068664f, 0.981963869f,\n 0.190574755f, 0.981672686f,\n 0.192080397f, 0.981379193f,\n 0.193585587f, 0.981083391f,\n 0.195090322f, 0.980785280f,\n 0.196594598f, 0.980484862f,\n 0.198098411f, 0.980182136f,\n 0.199601758f, 0.979877104f,\n 0.201104635f, 0.979569766f,\n 0.202607039f, 0.979260123f,\n 0.204108966f, 0.978948175f,\n 0.205610413f, 0.978633924f,\n 0.207111376f, 0.978317371f,\n 0.208611852f, 0.977998515f,\n 0.210111837f, 0.977677358f,\n 0.211611327f, 0.977353900f,\n 0.213110320f, 0.977028143f,\n 0.214608811f, 0.976700086f,\n 0.216106797f, 0.976369731f,\n 0.217604275f, 0.976037079f,\n 0.219101240f, 0.975702130f,\n 0.220597690f, 0.975364885f,\n 0.222093621f, 0.975025345f,\n 0.223589029f, 0.974683511f,\n 0.225083911f, 0.974339383f,\n 0.226578264f, 0.973992962f,\n 0.228072083f, 0.973644250f,\n 0.229565366f, 0.973293246f,\n 0.231058108f, 0.972939952f,\n 0.232550307f, 0.972584369f,\n 0.234041959f, 0.972226497f,\n 0.235533059f, 0.971866337f,\n 0.237023606f, 0.971503891f,\n 0.238513595f, 0.971139158f,\n 0.240003022f, 0.970772141f,\n 0.241491885f, 0.970402839f,\n 0.242980180f, 0.970031253f,\n 0.244467903f, 0.969657385f,\n 0.245955050f, 0.969281235f,\n 0.247441619f, 0.968902805f,\n 0.248927606f, 0.968522094f,\n 0.250413007f, 0.968139105f,\n 0.251897818f, 0.967753837f,\n 0.253382037f, 0.967366292f,\n 0.254865660f, 0.966976471f,\n 0.256348682f, 0.966584374f,\n 0.257831102f, 0.966190003f,\n 0.259312915f, 0.965793359f,\n 0.260794118f, 0.965394442f,\n 0.262274707f, 0.964993253f,\n 0.263754679f, 0.964589793f,\n 0.265234030f, 0.964184064f,\n 0.266712757f, 0.963776066f,\n 0.268190857f, 0.963365800f,\n 0.269668326f, 0.962953267f,\n 0.271145160f, 0.962538468f,\n 0.272621355f, 0.962121404f,\n 0.274096910f, 0.961702077f,\n 0.275571819f, 0.961280486f,\n 0.277046080f, 0.960856633f,\n 0.278519689f, 0.960430519f,\n 0.279992643f, 0.960002146f,\n 0.281464938f, 0.959571513f,\n 0.282936570f, 0.959138622f,\n 0.284407537f, 0.958703475f,\n 0.285877835f, 0.958266071f,\n 0.287347460f, 0.957826413f,\n 0.288816408f, 0.957384501f,\n 0.290284677f, 0.956940336f,\n 0.291752263f, 0.956493919f,\n 0.293219163f, 0.956045251f,\n 0.294685372f, 0.955594334f,\n 0.296150888f, 0.955141168f,\n 0.297615707f, 0.954685755f,\n 0.299079826f, 0.954228095f,\n 0.300543241f, 0.953768190f,\n 0.302005949f, 0.953306040f,\n 0.303467947f, 0.952841648f,\n 0.304929230f, 0.952375013f,\n 0.306389795f, 0.951906137f,\n 0.307849640f, 0.951435021f,\n 0.309308760f, 0.950961666f,\n 0.310767153f, 0.950486074f,\n 0.312224814f, 0.950008245f,\n 0.313681740f, 0.949528181f,\n 0.315137929f, 0.949045882f,\n 0.316593376f, 0.948561350f,\n 0.318048077f, 0.948074586f,\n 0.319502031f, 0.947585591f,\n 0.320955232f, 0.947094366f,\n 0.322407679f, 0.946600913f,\n 0.323859367f, 0.946105232f,\n 0.325310292f, 0.945607325f,\n 0.326760452f, 0.945107193f,\n 0.328209844f, 0.944604837f,\n 0.329658463f, 0.944100258f,\n 0.331106306f, 0.943593458f,\n 0.332553370f, 0.943084437f,\n 0.333999651f, 0.942573198f,\n 0.335445147f, 0.942059740f,\n 0.336889853f, 0.941544065f,\n 0.338333767f, 0.941026175f,\n 0.339776884f, 0.940506071f,\n 0.341219202f, 0.939983753f,\n 0.342660717f, 0.939459224f,\n 0.344101426f, 0.938932484f,\n 0.345541325f, 0.938403534f,\n 0.346980411f, 0.937872376f,\n 0.348418680f, 0.937339012f,\n 0.349856130f, 0.936803442f,\n 0.351292756f, 0.936265667f,\n 0.352728556f, 0.935725689f,\n 0.354163525f, 0.935183510f,\n 0.355597662f, 0.934639130f,\n 0.357030961f, 0.934092550f,\n 0.358463421f, 0.933543773f,\n 0.359895037f, 0.932992799f,\n 0.361325806f, 0.932439629f,\n 0.362755724f, 0.931884266f,\n 0.364184790f, 0.931326709f,\n 0.365612998f, 0.930766961f,\n 0.367040346f, 0.930205023f,\n 0.368466830f, 0.929640896f,\n 0.369892447f, 0.929074581f,\n 0.371317194f, 0.928506080f,\n 0.372741067f, 0.927935395f,\n 0.374164063f, 0.927362526f,\n 0.375586178f, 0.926787474f,\n 0.377007410f, 0.926210242f,\n 0.378427755f, 0.925630831f,\n 0.379847209f, 0.925049241f,\n 0.381265769f, 0.924465474f,\n 0.382683432f, 0.923879533f,\n 0.384100195f, 0.923291417f,\n 0.385516054f, 0.922701128f,\n 0.386931006f, 0.922108669f,\n 0.388345047f, 0.921514039f,\n 0.389758174f, 0.920917242f,\n 0.391170384f, 0.920318277f,\n 0.392581674f, 0.919717146f,\n 0.393992040f, 0.919113852f,\n 0.395401479f, 0.918508394f,\n 0.396809987f, 0.917900776f,\n 0.398217562f, 0.917290997f,\n 0.399624200f, 0.916679060f,\n 0.401029897f, 0.916064966f,\n 0.402434651f, 0.915448716f,\n 0.403838458f, 0.914830312f,\n 0.405241314f, 0.914209756f,\n 0.406643217f, 0.913587048f,\n 0.408044163f, 0.912962190f,\n 0.409444149f, 0.912335185f,\n 0.410843171f, 0.911706032f,\n 0.412241227f, 0.911074734f,\n 0.413638312f, 0.910441292f,\n 0.415034424f, 0.909805708f,\n 0.416429560f, 0.909167983f,\n 0.417823716f, 0.908528119f,\n 0.419216888f, 0.907886116f,\n 0.420609074f, 0.907241978f,\n 0.422000271f, 0.906595705f,\n 0.423390474f, 0.905947298f,\n 0.424779681f, 0.905296759f,\n 0.426167889f, 0.904644091f,\n 0.427555093f, 0.903989293f,\n 0.428941292f, 0.903332368f,\n 0.430326481f, 0.902673318f,\n 0.431710658f, 0.902012144f,\n 0.433093819f, 0.901348847f,\n 0.434475961f, 0.900683429f,\n 0.435857080f, 0.900015892f,\n 0.437237174f, 0.899346237f,\n 0.438616239f, 0.898674466f,\n 0.439994271f, 0.898000580f,\n 0.441371269f, 0.897324581f,\n 0.442747228f, 0.896646470f,\n 0.444122145f, 0.895966250f,\n 0.445496017f, 0.895283921f,\n 0.446868840f, 0.894599486f,\n 0.448240612f, 0.893912945f,\n 0.449611330f, 0.893224301f,\n 0.450980989f, 0.892533555f,\n 0.452349587f, 0.891840709f,\n 0.453717121f, 0.891145765f,\n 0.455083587f, 0.890448723f,\n 0.456448982f, 0.889749586f,\n 0.457813304f, 0.889048356f,\n 0.459176548f, 0.888345033f,\n 0.460538711f, 0.887639620f,\n 0.461899791f, 0.886932119f,\n 0.463259784f, 0.886222530f,\n 0.464618686f, 0.885510856f,\n 0.465976496f, 0.884797098f,\n 0.467333209f, 0.884081259f,\n 0.468688822f, 0.883363339f,\n 0.470043332f, 0.882643340f,\n 0.471396737f, 0.881921264f,\n 0.472749032f, 0.881197113f,\n 0.474100215f, 0.880470889f,\n 0.475450282f, 0.879742593f,\n 0.476799230f, 0.879012226f,\n 0.478147056f, 0.878279792f,\n 0.479493758f, 0.877545290f,\n 0.480839331f, 0.876808724f,\n 0.482183772f, 0.876070094f,\n 0.483527079f, 0.875329403f,\n 0.484869248f, 0.874586652f,\n 0.486210276f, 0.873841843f,\n 0.487550160f, 0.873094978f,\n 0.488888897f, 0.872346059f,\n 0.490226483f, 0.871595087f,\n 0.491562916f, 0.870842063f,\n 0.492898192f, 0.870086991f,\n 0.494232309f, 0.869329871f,\n 0.495565262f, 0.868570706f,\n 0.496897049f, 0.867809497f,\n 0.498227667f, 0.867046246f,\n 0.499557113f, 0.866280954f,\n 0.500885383f, 0.865513624f,\n 0.502212474f, 0.864744258f,\n 0.503538384f, 0.863972856f,\n 0.504863109f, 0.863199422f,\n 0.506186645f, 0.862423956f,\n 0.507508991f, 0.861646461f,\n 0.508830143f, 0.860866939f,\n 0.510150097f, 0.860085390f,\n 0.511468850f, 0.859301818f,\n 0.512786401f, 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0.307849640f, -0.951435021f,\n 0.306389795f, -0.951906137f,\n 0.304929230f, -0.952375013f,\n 0.303467947f, -0.952841648f,\n 0.302005949f, -0.953306040f,\n 0.300543241f, -0.953768190f,\n 0.299079826f, -0.954228095f,\n 0.297615707f, -0.954685755f,\n 0.296150888f, -0.955141168f,\n 0.294685372f, -0.955594334f,\n 0.293219163f, -0.956045251f,\n 0.291752263f, -0.956493919f,\n 0.290284677f, -0.956940336f,\n 0.288816408f, -0.957384501f,\n 0.287347460f, -0.957826413f,\n 0.285877835f, -0.958266071f,\n 0.284407537f, -0.958703475f,\n 0.282936570f, -0.959138622f,\n 0.281464938f, -0.959571513f,\n 0.279992643f, -0.960002146f,\n 0.278519689f, -0.960430519f,\n 0.277046080f, -0.960856633f,\n 0.275571819f, -0.961280486f,\n 0.274096910f, -0.961702077f,\n 0.272621355f, -0.962121404f,\n 0.271145160f, -0.962538468f,\n 0.269668326f, -0.962953267f,\n 0.268190857f, -0.963365800f,\n 0.266712757f, -0.963776066f,\n 0.265234030f, -0.964184064f,\n 0.263754679f, -0.964589793f,\n 0.262274707f, -0.964993253f,\n 0.260794118f, -0.965394442f,\n 0.259312915f, -0.965793359f,\n 0.257831102f, -0.966190003f,\n 0.256348682f, -0.966584374f,\n 0.254865660f, -0.966976471f,\n 0.253382037f, -0.967366292f,\n 0.251897818f, -0.967753837f,\n 0.250413007f, -0.968139105f,\n 0.248927606f, -0.968522094f,\n 0.247441619f, -0.968902805f,\n 0.245955050f, -0.969281235f,\n 0.244467903f, -0.969657385f,\n 0.242980180f, -0.970031253f,\n 0.241491885f, -0.970402839f,\n 0.240003022f, -0.970772141f,\n 0.238513595f, -0.971139158f,\n 0.237023606f, -0.971503891f,\n 0.235533059f, -0.971866337f,\n 0.234041959f, -0.972226497f,\n 0.232550307f, -0.972584369f,\n 0.231058108f, -0.972939952f,\n 0.229565366f, -0.973293246f,\n 0.228072083f, -0.973644250f,\n 0.226578264f, -0.973992962f,\n 0.225083911f, -0.974339383f,\n 0.223589029f, -0.974683511f,\n 0.222093621f, -0.975025345f,\n 0.220597690f, -0.975364885f,\n 0.219101240f, -0.975702130f,\n 0.217604275f, -0.976037079f,\n 0.216106797f, -0.976369731f,\n 0.214608811f, -0.976700086f,\n 0.213110320f, -0.977028143f,\n 0.211611327f, -0.977353900f,\n 0.210111837f, -0.977677358f,\n 0.208611852f, -0.977998515f,\n 0.207111376f, -0.978317371f,\n 0.205610413f, -0.978633924f,\n 0.204108966f, -0.978948175f,\n 0.202607039f, -0.979260123f,\n 0.201104635f, -0.979569766f,\n 0.199601758f, -0.979877104f,\n 0.198098411f, -0.980182136f,\n 0.196594598f, -0.980484862f,\n 0.195090322f, -0.980785280f,\n 0.193585587f, -0.981083391f,\n 0.192080397f, -0.981379193f,\n 0.190574755f, -0.981672686f,\n 0.189068664f, -0.981963869f,\n 0.187562129f, -0.982252741f,\n 0.186055152f, -0.982539302f,\n 0.184547737f, -0.982823551f,\n 0.183039888f, -0.983105487f,\n 0.181531608f, -0.983385110f,\n 0.180022901f, -0.983662419f,\n 0.178513771f, -0.983937413f,\n 0.177004220f, -0.984210092f,\n 0.175494253f, -0.984480455f,\n 0.173983873f, -0.984748502f,\n 0.172473084f, -0.985014231f,\n 0.170961889f, -0.985277642f,\n 0.169450291f, -0.985538735f,\n 0.167938295f, -0.985797509f,\n 0.166425904f, -0.986053963f,\n 0.164913120f, -0.986308097f,\n 0.163399949f, -0.986559910f,\n 0.161886394f, -0.986809402f,\n 0.160372457f, -0.987056571f,\n 0.158858143f, -0.987301418f,\n 0.157343456f, -0.987543942f,\n 0.155828398f, -0.987784142f,\n 0.154312973f, -0.988022017f,\n 0.152797185f, -0.988257568f,\n 0.151281038f, -0.988490793f,\n 0.149764535f, -0.988721692f,\n 0.148247679f, -0.988950265f,\n 0.146730474f, -0.989176510f,\n 0.145212925f, -0.989400428f,\n 0.143695033f, -0.989622017f,\n 0.142176804f, -0.989841278f,\n 0.140658239f, -0.990058210f,\n 0.139139344f, -0.990272812f,\n 0.137620122f, -0.990485084f,\n 0.136100575f, -0.990695025f,\n 0.134580709f, -0.990902635f,\n 0.133060525f, -0.991107914f,\n 0.131540029f, -0.991310860f,\n 0.130019223f, -0.991511473f,\n 0.128498111f, -0.991709754f,\n 0.126976696f, -0.991905700f,\n 0.125454983f, -0.992099313f,\n 0.123932975f, -0.992290591f,\n 0.122410675f, -0.992479535f,\n 0.120888087f, -0.992666142f,\n 0.119365215f, -0.992850414f,\n 0.117842062f, -0.993032350f,\n 0.116318631f, -0.993211949f,\n 0.114794927f, -0.993389211f,\n 0.113270952f, -0.993564136f,\n 0.111746711f, -0.993736722f,\n 0.110222207f, -0.993906970f,\n 0.108697444f, -0.994074879f,\n 0.107172425f, -0.994240449f,\n 0.105647154f, -0.994403680f,\n 0.104121634f, -0.994564571f,\n 0.102595869f, -0.994723121f,\n 0.101069863f, -0.994879331f,\n 0.099543619f, -0.995033199f,\n 0.098017140f, -0.995184727f,\n 0.096490431f, -0.995333912f,\n 0.094963495f, -0.995480755f,\n 0.093436336f, -0.995625256f,\n 0.091908956f, -0.995767414f,\n 0.090381361f, -0.995907229f,\n 0.088853553f, -0.996044701f,\n 0.087325535f, -0.996179829f,\n 0.085797312f, -0.996312612f,\n 0.084268888f, -0.996443051f,\n 0.082740265f, -0.996571146f,\n 0.081211447f, -0.996696895f,\n 0.079682438f, -0.996820299f,\n 0.078153242f, -0.996941358f,\n 0.076623861f, -0.997060070f,\n 0.075094301f, -0.997176437f,\n 0.073564564f, -0.997290457f,\n 0.072034653f, -0.997402130f,\n 0.070504573f, -0.997511456f,\n 0.068974328f, -0.997618435f,\n 0.067443920f, -0.997723067f,\n 0.065913353f, -0.997825350f,\n 0.064382631f, -0.997925286f,\n 0.062851758f, -0.998022874f,\n 0.061320736f, -0.998118113f,\n 0.059789571f, -0.998211003f,\n 0.058258265f, -0.998301545f,\n 0.056726821f, -0.998389737f,\n 0.055195244f, -0.998475581f,\n 0.053663538f, -0.998559074f,\n 0.052131705f, -0.998640218f,\n 0.050599749f, -0.998719012f,\n 0.049067674f, -0.998795456f,\n 0.047535484f, -0.998869550f,\n 0.046003182f, -0.998941293f,\n 0.044470772f, -0.999010686f,\n 0.042938257f, -0.999077728f,\n 0.041405641f, -0.999142419f,\n 0.039872928f, -0.999204759f,\n 0.038340120f, -0.999264747f,\n 0.036807223f, -0.999322385f,\n 0.035274239f, -0.999377670f,\n 0.033741172f, -0.999430605f,\n 0.032208025f, -0.999481187f,\n 0.030674803f, -0.999529418f,\n 0.029141509f, -0.999575296f,\n 0.027608146f, -0.999618822f,\n 0.026074718f, -0.999659997f,\n 0.024541229f, -0.999698819f,\n 0.023007681f, -0.999735288f,\n 0.021474080f, -0.999769405f,\n 0.019940429f, -0.999801170f,\n 0.018406730f, -0.999830582f,\n 0.016872988f, -0.999857641f,\n 0.015339206f, -0.999882347f,\n 0.013805389f, -0.999904701f,\n 0.012271538f, -0.999924702f,\n 0.010737659f, -0.999942350f,\n 0.009203755f, -0.999957645f,\n 0.007669829f, -0.999970586f,\n 0.006135885f, -0.999981175f,\n 0.004601926f, -0.999989411f,\n 0.003067957f, -0.999995294f,\n 0.001533980f, -0.999998823f\n};\n" }, { "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c", "content": "/* ---------------------------------------------------------------------- \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved. \n* \n* $Date: 17. January 2013\n* $Revision: \tV1.4.1\n* \n* Project: \t CMSIS DSP Library \n* Title:\t\tarm_cmplx_conj_f32.c \n* \n* Description:\tFloating-point complex conjugate. \n* \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n* - Redistributions of source code must retain the above copyright\n* notice, this list of conditions and the following disclaimer.\n* - Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in\n* the documentation and/or other materials provided with the \n* distribution.\n* - Neither the name of ARM LIMITED nor the names of its contributors\n* may be used to endorse or promote products derived from this\n* software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/** \n * @ingroup groupCmplxMath \n */\n\n/** \n * @defgroup cmplx_conj Complex Conjugate \n * \n * Conjugates the elements of a complex data vector. \n * \n * The pSrc points to the source data and \n * pDst points to the where the result should be written. \n * numSamples specifies the number of complex samples \n * and the data in each array is stored in an interleaved fashion \n * (real, imag, real, imag, ...). \n * Each array has a total of 2*numSamples values. \n * The underlying algorithm is used: \n * \n * 
        \n * for(n=0; n        \n *        \n * There are separate functions for floating-point, Q15, and Q31 data types.        \n */\n\n/**        \n * @addtogroup cmplx_conj        \n * @{        \n */\n\n/**        \n * @brief  Floating-point complex conjugate.        \n * @param  *pSrc points to the input vector        \n * @param  *pDst points to the output vector        \n * @param  numSamples number of complex samples in each vector        \n * @return none.        \n */\n\nvoid arm_cmplx_conj_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t inR1, inR2, inR3, inR4;\n  float32_t inI1, inI2, inI3, inI4;\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    /* read real input samples */\n    inR1 = pSrc[0];\n    /* store real samples to destination */\n    pDst[0] = inR1;\n    inR2 = pSrc[2];\n    pDst[2] = inR2;\n    inR3 = pSrc[4];\n    pDst[4] = inR3;\n    inR4 = pSrc[6];\n    pDst[6] = inR4;\n\n    /* read imaginary input samples */\n    inI1 = pSrc[1];\n    inI2 = pSrc[3];\n\n    /* conjugate input */\n    inI1 = -inI1;\n\n    /* read imaginary input samples */\n    inI3 = pSrc[5];\n\n    /* conjugate input */\n    inI2 = -inI2;\n\n    /* read imaginary input samples */\n    inI4 = pSrc[7];\n\n    /* conjugate input */\n    inI3 = -inI3;\n\n    /* store imaginary samples to destination */\n    pDst[1] = inI1;\n    pDst[3] = inI2;\n\n    /* conjugate input */\n    inI4 = -inI4;\n\n    /* store imaginary samples to destination */\n    pDst[5] = inI3;\n\n    /* increment source pointer by 8 to process next sampels */\n    pSrc += 8u;\n\n    /* store imaginary sample to destination */\n    pDst[7] = inI4;\n\n    /* increment destination pointer by 8 to store next samples */\n    pDst += 8u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* realOut + j (imagOut) = realIn + j (-1) imagIn */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    *pDst++ = *pSrc++;\n    *pDst++ = -*pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of cmplx_conj group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_conj_q15.c    \n*    \n* Description:\tQ15 complex conjugate.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_conj    \n * @{    \n */\n\n/**    \n * @brief  Q15 complex conjugate.    \n * @param  *pSrc points to the input vector    \n * @param  *pDst points to the output vector    \n * @param  numSamples number of complex samples in each vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    \n */\n\nvoid arm_cmplx_conj_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n  q31_t in1, in2, in3, in4;\n  q31_t zero = 0;\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    in1 = *__SIMD32(pSrc)++;\n    in2 = *__SIMD32(pSrc)++;\n    in3 = *__SIMD32(pSrc)++;\n    in4 = *__SIMD32(pSrc)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    in1 = __QASX(zero, in1);\n    in2 = __QASX(zero, in2);\n    in3 = __QASX(zero, in3);\n    in4 = __QASX(zero, in4);\n\n#else\n\n    in1 = __QSAX(zero, in1);\n    in2 = __QSAX(zero, in2);\n    in3 = __QSAX(zero, in3);\n    in4 = __QSAX(zero, in4);\n\n#endif //       #ifndef ARM_MATH_BIG_ENDIAN\n\n    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);\n    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);\n    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);\n    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);\n\n    *__SIMD32(pDst)++ = in1;\n    *__SIMD32(pDst)++ = in2;\n    *__SIMD32(pDst)++ = in3;\n    *__SIMD32(pDst)++ = in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    *pDst++ = *pSrc++;\n    *pDst++ = __SSAT(-*pSrc++, 16);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  q15_t in;\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    *pDst++ = *pSrc++;\n    in = *pSrc++;\n    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of cmplx_conj group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_conj_q31.c    \n*    \n* Description:\tQ31 complex conjugate.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupCmplxMath        \n */\n\n/**        \n * @addtogroup cmplx_conj        \n * @{        \n */\n\n/**        \n * @brief  Q31 complex conjugate.        \n * @param  *pSrc points to the input vector        \n * @param  *pDst points to the output vector        \n * @param  numSamples number of complex samples in each vector        \n * @return none.        \n *        \n * Scaling and Overflow Behavior:        \n * \\par        \n * The function uses saturating arithmetic.        \n * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.        \n */\n\nvoid arm_cmplx_conj_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples)\n{\n  uint32_t blkCnt;                               /* loop counter */\n  q31_t in;                                      /* Input value */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */\n  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */\n    /* read real input sample */\n    inR1 = pSrc[0];\n    /* store real input sample */\n    pDst[0] = inR1;\n\n    /* read imaginary input sample */\n    inI1 = pSrc[1];\n\n    /* read real input sample */\n    inR2 = pSrc[2];\n    /* store real input sample */\n    pDst[2] = inR2;\n\n    /* read imaginary input sample */\n    inI2 = pSrc[3];\n\n    /* negate imaginary input sample */\n    inI1 = __QSUB(0, inI1);\n\n    /* read real input sample */\n    inR3 = pSrc[4];\n    /* store real input sample */\n    pDst[4] = inR3;\n\n    /* read imaginary input sample */\n    inI3 = pSrc[5];\n\n    /* negate imaginary input sample */\n    inI2 = __QSUB(0, inI2);\n\n    /* read real input sample */\n    inR4 = pSrc[6];\n    /* store real input sample */\n    pDst[6] = inR4;\n\n    /* negate imaginary input sample */\n    inI3 = __QSUB(0, inI3);\n\n    /* store imaginary input sample */\n    inI4 = pSrc[7];\n\n    /* store imaginary input samples */\n    pDst[1] = inI1;\n\n    /* negate imaginary input sample */\n    inI4 = __QSUB(0, inI4);\n\n    /* store imaginary input samples */\n    pDst[3] = inI2;\n\n    /* increment source pointer by 8 to proecess next samples */\n    pSrc += 8u;\n\n    /* store imaginary input samples */\n    pDst[5] = inI3;\n    pDst[7] = inI4;\n\n    /* increment destination pointer by 8 to process next samples */\n    pDst += 8u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = numSamples;\n\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */\n    /* Calculate Complex Conjugate and then store the results in the destination buffer. */\n    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */\n    *pDst++ = *pSrc++;\n    in = *pSrc++;\n    *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of cmplx_conj group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_dot_prod_f32.c    \n*    \n* Description:\tFloating-point complex dot product    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @defgroup cmplx_dot_prod Complex Dot Product    \n *    \n * Computes the dot product of two complex vectors.    \n * The vectors are multiplied element-by-element and then summed.    \n *   \n * The pSrcA points to the first complex input vector and    \n * pSrcB points to the second complex input vector.    \n * numSamples specifies the number of complex samples    \n * and the data in each array is stored in an interleaved fashion    \n * (real, imag, real, imag, ...).    \n * Each array has a total of 2*numSamples values.    \n *    \n * The underlying algorithm is used:    \n * 
    \n * realResult=0;    \n * imagResult=0;    \n * for(n=0; n    \n *    \n * There are separate functions for floating-point, Q15, and Q31 data types.    \n */\n\n/**    \n * @addtogroup cmplx_dot_prod    \n * @{    \n */\n\n/**    \n * @brief  Floating-point complex dot product    \n * @param  *pSrcA points to the first input vector    \n * @param  *pSrcB points to the second input vector    \n * @param  numSamples number of complex samples in each vector    \n * @param  *realResult real part of the result returned here    \n * @param  *imagResult imaginary part of the result returned here    \n * @return none.    \n */\n\nvoid arm_cmplx_dot_prod_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  uint32_t numSamples,\n  float32_t * realResult,\n  float32_t * imagResult)\n{\n  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += (*pSrcA++) * (*pSrcB++);\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += (*pSrcA++) * (*pSrcB++);\n\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Store the real and imaginary results in the destination buffers */\n  *realResult = real_sum;\n  *imagResult = imag_sum;\n}\n\n/**    \n * @} end of cmplx_dot_prod group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_dot_prod_q15.c    \n*    \n* Description:\tProcessing function for the Q15 Complex Dot product    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_dot_prod    \n * @{    \n */\n\n/**    \n * @brief  Q15 complex dot product    \n * @param  *pSrcA points to the first input vector    \n * @param  *pSrcB points to the second input vector    \n * @param  numSamples number of complex samples in each vector    \n * @param  *realResult real part of the result returned here    \n * @param  *imagResult imaginary part of the result returned here    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    \n * These are accumulated in a 64-bit accumulator with 34.30 precision.    \n * As a final step, the accumulators are converted to 8.24 format.    \n * The return results realResult and imagResult are in 8.24 format.    \n */\n\nvoid arm_cmplx_dot_prod_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  uint32_t numSamples,\n  q31_t * realResult,\n  q31_t * imagResult)\n{\n  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Store the real and imaginary results in 8.24 format  */\n  /* Convert real data in 34.30 to 8.24 by 6 right shifts */\n  *realResult = (q31_t) (real_sum) >> 6;\n  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */\n  *imagResult = (q31_t) (imag_sum) >> 6;\n}\n\n/**    \n * @} end of cmplx_dot_prod group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_dot_prod_q31.c    \n*    \n* Description:\tQ31 complex dot product    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_dot_prod    \n * @{    \n */\n\n/**    \n * @brief  Q31 complex dot product    \n * @param  *pSrcA points to the first input vector    \n * @param  *pSrcB points to the second input vector    \n * @param  numSamples number of complex samples in each vector    \n * @param  *realResult real part of the result returned here    \n * @param  *imagResult imaginary part of the result returned here    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.    \n * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.    \n * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.    \n * The return results realResult and imagResult are in 16.48 format.    \n * Input down scaling is not required.    \n */\n\nvoid arm_cmplx_dot_prod_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  uint32_t numSamples,\n  q63_t * realResult,\n  q63_t * imagResult)\n{\n  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    /* Convert real data in 2.62 to 16.48 by 14 right shifts */\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */\n    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */\n    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Store the real and imaginary results in 16.48 format  */\n  *realResult = real_sum;\n  *imagResult = imag_sum;\n}\n\n/**    \n * @} end of cmplx_dot_prod group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_f32.c    \n*    \n* Description:\tFloating-point complex magnitude.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @defgroup cmplx_mag Complex Magnitude    \n *    \n * Computes the magnitude of the elements of a complex data vector.    \n *   \n * The pSrc points to the source data and    \n * pDst points to the where the result should be written.    \n * numSamples specifies the number of complex samples    \n * in the input array and the data is stored in an interleaved fashion    \n * (real, imag, real, imag, ...).    \n * The input array has a total of 2*numSamples values;    \n * the output array has a total of numSamples values.    \n * The underlying algorithm is used:    \n *    \n * 
    \n * for(n=0; n    \n *    \n * There are separate functions for floating-point, Q15, and Q31 data types.    \n */\n\n/**    \n * @addtogroup cmplx_mag    \n * @{    \n */\n/**    \n * @brief Floating-point complex magnitude.    \n * @param[in]       *pSrc points to complex input buffer    \n * @param[out]      *pDst points to real output buffer    \n * @param[in]       numSamples number of complex samples in the input vector    \n * @return none.    \n *    \n */\n\n\nvoid arm_cmplx_mag_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples)\n{\n  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    /* store the result in the destination buffer. */\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    /* store the result in the destination buffer. */\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* out = sqrt((real * real) + (imag * imag)) */\n    realIn = *pSrc++;\n    imagIn = *pSrc++;\n    /* store the result in the destination buffer. */\n    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of cmplx_mag group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_q15.c    \n*    \n* Description:\tQ15 complex magnitude.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_mag    \n * @{    \n */\n\n\n/**    \n * @brief  Q15 complex magnitude    \n * @param  *pSrc points to the complex input vector    \n * @param  *pDst points to the real output vector    \n * @param  numSamples number of complex samples in the input vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.    \n */\n\nvoid arm_cmplx_mag_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples)\n{\n  q31_t acc0, acc1;                              /* Accumulators */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n  q31_t in1, in2, in3, in4;\n  q31_t acc2, acc3;\n\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */\n    in1 = *__SIMD32(pSrc)++;\n    in2 = *__SIMD32(pSrc)++;\n    in3 = *__SIMD32(pSrc)++;\n    in4 = *__SIMD32(pSrc)++;\n\n    acc0 = __SMUAD(in1, in1);\n    acc1 = __SMUAD(in2, in2);\n    acc2 = __SMUAD(in3, in3);\n    acc3 = __SMUAD(in4, in4);\n\n    /* store the result in 2.14 format in the destination buffer. */\n    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);\n    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);\n    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);\n    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */\n    in1 = *__SIMD32(pSrc)++;\n    acc0 = __SMUAD(in1, in1);\n\n    /* store the result in 2.14 format in the destination buffer. */\n    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q15_t real, imag;                              /* Temporary variables to hold input values */\n\n  while(numSamples > 0u)\n  {\n    /* out = sqrt(real * real + imag * imag) */\n    real = *pSrc++;\n    imag = *pSrc++;\n\n    acc0 = (real * real);\n    acc1 = (imag * imag);\n\n    /* store the result in 2.14 format in the destination buffer. */\n    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of cmplx_mag group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_q31.c    \n*    \n* Description:\tQ31 complex magnitude    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupCmplxMath        \n */\n\n/**        \n * @addtogroup cmplx_mag        \n * @{        \n */\n\n/**        \n * @brief  Q31 complex magnitude        \n * @param  *pSrc points to the complex input vector        \n * @param  *pDst points to the real output vector        \n * @param  numSamples number of complex samples in the input vector        \n * @return none.        \n *        \n * Scaling and Overflow Behavior:        \n * \\par        \n * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.        \n * Input down scaling is not required.        \n */\n\nvoid arm_cmplx_mag_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples)\n{\n  q31_t real, imag;                              /* Temporary variables to hold input values */\n  q31_t acc0, acc1;                              /* Accumulators */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */\n  q31_t out1, out2, out3, out4;                  /* Accumulators */\n  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */\n\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* read complex input from source buffer */\n    real1 = pSrc[0];\n    imag1 = pSrc[1];\n    real2 = pSrc[2];\n    imag2 = pSrc[3];\n\n    /* calculate power of input values */\n    mul1 = (q63_t) real1 *real1;\n    mul2 = (q63_t) imag1 *imag1;\n    mul3 = (q63_t) real2 *real2;\n    mul4 = (q63_t) imag2 *imag2;\n\n    /* get the result to 3.29 format */\n    out1 = (q31_t) (mul1 >> 33);\n    out2 = (q31_t) (mul2 >> 33);\n    out3 = (q31_t) (mul3 >> 33);\n    out4 = (q31_t) (mul4 >> 33);\n\n    /* add real and imaginary accumulators */\n    out1 = out1 + out2;\n    out3 = out3 + out4;\n\n    /* read complex input from source buffer */\n    real1 = pSrc[4];\n    imag1 = pSrc[5];\n    real2 = pSrc[6];\n    imag2 = pSrc[7];\n\n    /* calculate square root */\n    arm_sqrt_q31(out1, &pDst[0]);\n\n    /* calculate power of input values */\n    mul1 = (q63_t) real1 *real1;\n\n    /* calculate square root */\n    arm_sqrt_q31(out3, &pDst[1]);\n\n    /* calculate power of input values */\n    mul2 = (q63_t) imag1 *imag1;\n    mul3 = (q63_t) real2 *real2;\n    mul4 = (q63_t) imag2 *imag2;\n\n    /* get the result to 3.29 format */\n    out1 = (q31_t) (mul1 >> 33);\n    out2 = (q31_t) (mul2 >> 33);\n    out3 = (q31_t) (mul3 >> 33);\n    out4 = (q31_t) (mul4 >> 33);\n\n    /* add real and imaginary accumulators */\n    out1 = out1 + out2;\n    out3 = out3 + out4;\n\n    /* calculate square root */\n    arm_sqrt_q31(out1, &pDst[2]);\n\n    /* increment destination by 8 to process next samples */\n    pSrc += 8u;\n\n    /* calculate square root */\n    arm_sqrt_q31(out3, &pDst[3]);\n\n    /* increment destination by 4 to process next samples */\n    pDst += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 2.30 format in the destination buffer. */\n    arm_sqrt_q31(acc0 + acc1, pDst++);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of cmplx_mag group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_squared_f32.c    \n*    \n* Description:\tFloating-point complex magnitude squared.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupCmplxMath        \n */\n\n/**        \n * @defgroup cmplx_mag_squared Complex Magnitude Squared        \n *        \n * Computes the magnitude squared of the elements of a complex data vector.        \n *       \n * The pSrc points to the source data and        \n * pDst points to the where the result should be written.        \n * numSamples specifies the number of complex samples        \n * in the input array and the data is stored in an interleaved fashion        \n * (real, imag, real, imag, ...).        \n * The input array has a total of 2*numSamples values;        \n * the output array has a total of numSamples values.        \n *        \n * The underlying algorithm is used:        \n *        \n * 
        \n * for(n=0; n        \n *        \n * There are separate functions for floating-point, Q15, and Q31 data types.        \n */\n\n/**        \n * @addtogroup cmplx_mag_squared        \n * @{        \n */\n\n\n/**        \n * @brief  Floating-point complex magnitude squared        \n * @param[in]  *pSrc points to the complex input vector        \n * @param[out]  *pDst points to the real output vector        \n * @param[in]  numSamples number of complex samples in the input vector        \n * @return none.        \n */\n\nvoid arm_cmplx_mag_squared_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples)\n{\n  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */\n  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */\n  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */\n  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */\n  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    /* read real input sample from source buffer */\n    real1 = pSrc[0];\n    /* read imaginary input sample from source buffer */\n    imag1 = pSrc[1];\n\n    /* calculate power of real value */\n    mul1 = real1 * real1;\n\n    /* read real input sample from source buffer */\n    real2 = pSrc[2];\n\n    /* calculate power of imaginary value */\n    mul2 = imag1 * imag1;\n\n    /* read imaginary input sample from source buffer */\n    imag2 = pSrc[3];\n\n    /* calculate power of real value */\n    mul3 = real2 * real2;\n\n    /* read real input sample from source buffer */\n    real3 = pSrc[4];\n\n    /* calculate power of imaginary value */\n    mul4 = imag2 * imag2;\n\n    /* read imaginary input sample from source buffer */\n    imag3 = pSrc[5];\n\n    /* calculate power of real value */\n    mul5 = real3 * real3;\n    /* calculate power of imaginary value */\n    mul6 = imag3 * imag3;\n\n    /* read real input sample from source buffer */\n    real4 = pSrc[6];\n\n    /* accumulate real and imaginary powers */\n    out1 = mul1 + mul2;\n\n    /* read imaginary input sample from source buffer */\n    imag4 = pSrc[7];\n\n    /* accumulate real and imaginary powers */\n    out2 = mul3 + mul4;\n\n    /* calculate power of real value */\n    mul7 = real4 * real4;\n    /* calculate power of imaginary value */\n    mul8 = imag4 * imag4;\n\n    /* store output to destination */\n    pDst[0] = out1;\n\n    /* accumulate real and imaginary powers */\n    out3 = mul5 + mul6;\n\n    /* store output to destination */\n    pDst[1] = out2;\n\n    /* accumulate real and imaginary powers */\n    out4 = mul7 + mul8;\n\n    /* store output to destination */\n    pDst[2] = out3;\n\n    /* increment destination pointer by 8 to process next samples */\n    pSrc += 8u;\n\n    /* store output to destination */\n    pDst[3] = out4;\n\n    /* increment destination pointer by 4 to process next samples */\n    pDst += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    real = *pSrc++;\n    imag = *pSrc++;\n\n    /* out = (real * real) + (imag * imag) */\n    /* store the result in the destination buffer. */\n    *pDst++ = (real * real) + (imag * imag);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of cmplx_mag_squared group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_squared_q15.c    \n*    \n* Description:\tQ15 complex magnitude squared.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_mag_squared    \n * @{    \n */\n\n/**    \n * @brief  Q15 complex magnitude squared    \n * @param  *pSrc points to the complex input vector    \n * @param  *pDst points to the real output vector    \n * @param  numSamples number of complex samples in the input vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    \n */\n\nvoid arm_cmplx_mag_squared_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples)\n{\n  q31_t acc0, acc1;                              /* Accumulators */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n  q31_t in1, in2, in3, in4;\n  q31_t acc2, acc3;\n\n  /*loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    in1 = *__SIMD32(pSrc)++;\n    in2 = *__SIMD32(pSrc)++;\n    in3 = *__SIMD32(pSrc)++;\n    in4 = *__SIMD32(pSrc)++;\n\n    acc0 = __SMUAD(in1, in1);\n    acc1 = __SMUAD(in2, in2);\n    acc2 = __SMUAD(in3, in3);\n    acc3 = __SMUAD(in4, in4);\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ = (q15_t) (acc0 >> 17);\n    *pDst++ = (q15_t) (acc1 >> 17);\n    *pDst++ = (q15_t) (acc2 >> 17);\n    *pDst++ = (q15_t) (acc3 >> 17);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    in1 = *__SIMD32(pSrc)++;\n    acc0 = __SMUAD(in1, in1);\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ = (q15_t) (acc0 >> 17);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */\n\n  while(numSamples > 0u)\n  {\n    /* out = ((real * real) + (imag * imag)) */\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (real * real);\n    acc1 = (imag * imag);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of cmplx_mag_squared group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cmplx_mag_squared_q31.c    \n*    \n* Description:\tQ31 complex magnitude squared.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup cmplx_mag_squared    \n * @{    \n */\n\n\n/**    \n * @brief  Q31 complex magnitude squared    \n * @param  *pSrc points to the complex input vector    \n * @param  *pDst points to the real output vector    \n * @param  numSamples number of complex samples in the input vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    \n * Input down scaling is not required.    \n */\n\nvoid arm_cmplx_mag_squared_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples)\n{\n  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */\n  q31_t acc0, acc1;                              /* Accumulators */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counter */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* out = ((real * real) + (imag * imag)) */\n    real = *pSrc++;\n    imag = *pSrc++;\n    acc0 = (q31_t) (((q63_t) real * real) >> 33);\n    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);\n    /* store the result in 3.29 format in the destination buffer. */\n    *pDst++ = acc0 + acc1;\n\n    /* Decrement the loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of cmplx_mag_squared group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_cmplx_f32.c    \n*    \n* Description:\tFloating-point complex-by-complex multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupCmplxMath        \n */\n\n/**        \n * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication        \n *        \n * Multiplies a complex vector by another complex vector and generates a complex result.        \n * The data in the complex arrays is stored in an interleaved fashion        \n * (real, imag, real, imag, ...).        \n * The parameter numSamples represents the number of complex        \n * samples processed.  The complex arrays have a total of 2*numSamples        \n * real values.        \n *        \n * The underlying algorithm is used:        \n *        \n * 
        \n * for(n=0; n        \n *        \n * There are separate functions for floating-point, Q15, and Q31 data types.        \n */\n\n/**        \n * @addtogroup CmplxByCmplxMult        \n * @{        \n */\n\n\n/**        \n * @brief  Floating-point complex-by-complex multiplication        \n * @param[in]  *pSrcA points to the first input vector        \n * @param[in]  *pSrcB points to the second input vector        \n * @param[out]  *pDst  points to the output vector        \n * @param[in]  numSamples number of complex samples in each vector        \n * @return none.        \n */\n\nvoid arm_cmplx_mult_cmplx_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t numSamples)\n{\n  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */\n  uint32_t blkCnt;                               /* loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */\n  float32_t acc1, acc2, acc3, acc4;\n\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a1 = *pSrcA;                /* A[2 * i] */\n    c1 = *pSrcB;                /* B[2 * i] */\n\n    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */\n    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */\n\n    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */\n    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */\n\n    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */\n    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */\n    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */\n\n    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */\n    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */\n\n    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */\n    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */\n\n    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */\n    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */\n\n    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */\n    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */\n    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */\n\n    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */\n    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */\n\n    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */\n    acc1 = (a1 * c1);\n\n    d1 = *(pSrcB + 5);\n    acc2 = (b1 * c1);\n\n    *(pDst + 2) = acc3;\n    *(pDst + 3) = acc4;\n\n    a2 = *(pSrcA + 6);\n    acc1 -= (b1 * d1);\n\n    c2 = *(pSrcB + 6);\n    acc2 += (a1 * d1);\n\n    b2 = *(pSrcA + 7);\n    acc3 = (a2 * c2);\n\n    d2 = *(pSrcB + 7);\n    acc4 = (b2 * c2);\n\n    *(pDst + 4) = acc1;\n    pSrcA += 8u;\n\n    acc3 -= (b2 * d2);\n    acc4 += (a2 * d2);\n\n    *(pDst + 5) = acc2;\n    pSrcB += 8u;\n\n    *(pDst + 6) = acc3;\n    *(pDst + 7) = acc4;\n\n    pDst += 8u;\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a1 = *pSrcA++;\n    b1 = *pSrcA++;\n    c1 = *pSrcB++;\n    d1 = *pSrcB++;\n\n    /* store the result in the destination buffer. */\n    *pDst++ = (a1 * c1) - (b1 * d1);\n    *pDst++ = (a1 * d1) + (b1 * c1);\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of CmplxByCmplxMult group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_cmplx_q15.c    \n*    \n* Description:\tQ15 complex-by-complex multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup CmplxByCmplxMult    \n * @{    \n */\n\n/**    \n * @brief  Q15 complex-by-complex multiplication    \n * @param[in]  *pSrcA points to the first input vector    \n * @param[in]  *pSrcB points to the second input vector    \n * @param[out]  *pDst  points to the output vector    \n * @param[in]  numSamples number of complex samples in each vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    \n */\n\nvoid arm_cmplx_mult_cmplx_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t numSamples)\n{\n  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counters */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);\n    /* store the result in 3.13 format in the destination buffer. */\n    *pDst++ =\n      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);\n\n    /* Decrement the blockSize loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of CmplxByCmplxMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_cmplx_q31.c    \n*    \n* Description:\tQ31 complex-by-complex multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup CmplxByCmplxMult    \n * @{    \n */\n\n\n/**    \n * @brief  Q31 complex-by-complex multiplication    \n * @param[in]  *pSrcA points to the first input vector    \n * @param[in]  *pSrcB points to the second input vector    \n * @param[out]  *pDst  points to the output vector    \n * @param[in]  numSamples number of complex samples in each vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    \n * Input down scaling is not required.    \n */\n\nvoid arm_cmplx_mult_cmplx_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t numSamples)\n{\n  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */\n  uint32_t blkCnt;                               /* loop counters */\n  q31_t mul1, mul2, mul3, mul4;\n  q31_t out1, out2;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 1u;\n\n  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.     \n   ** a second loop below computes the remaining 1 sample. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.     \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x2u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */\n    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */\n    a = *pSrcA++;\n    b = *pSrcA++;\n    c = *pSrcB++;\n    d = *pSrcB++;\n\n    mul1 = (q31_t) (((q63_t) a * c) >> 32);\n    mul2 = (q31_t) (((q63_t) b * d) >> 32);\n    mul3 = (q31_t) (((q63_t) a * d) >> 32);\n    mul4 = (q31_t) (((q63_t) b * c) >> 32);\n\n    mul1 = (mul1 >> 1);\n    mul2 = (mul2 >> 1);\n    mul3 = (mul3 >> 1);\n    mul4 = (mul4 >> 1);\n\n    out1 = mul1 - mul2;\n    out2 = mul3 + mul4;\n\n    /* store the real result in 3.29 format in the destination buffer. */\n    *pDst++ = out1;\n    /* store the imag result in 3.29 format in the destination buffer. */\n    *pDst++ = out2;\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of CmplxByCmplxMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_real_f32.c    \n*    \n* Description:\tFloating-point complex by real multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupCmplxMath        \n */\n\n/**        \n * @defgroup CmplxByRealMult Complex-by-Real Multiplication        \n *        \n * Multiplies a complex vector by a real vector and generates a complex result.        \n * The data in the complex arrays is stored in an interleaved fashion        \n * (real, imag, real, imag, ...).        \n * The parameter numSamples represents the number of complex        \n * samples processed.  The complex arrays have a total of 2*numSamples        \n * real values while the real array has a total of numSamples        \n * real values.        \n *        \n * The underlying algorithm is used:        \n *        \n * 
        \n * for(n=0; n        \n *        \n * There are separate functions for floating-point, Q15, and Q31 data types.        \n */\n\n/**        \n * @addtogroup CmplxByRealMult        \n * @{        \n */\n\n\n/**        \n * @brief  Floating-point complex-by-real multiplication        \n * @param[in]  *pSrcCmplx points to the complex input vector        \n * @param[in]  *pSrcReal points to the real input vector        \n * @param[out]  *pCmplxDst points to the complex output vector        \n * @param[in]  numSamples number of samples in each vector        \n * @return none.        \n */\n\nvoid arm_cmplx_mult_real_f32(\n  float32_t * pSrcCmplx,\n  float32_t * pSrcReal,\n  float32_t * pCmplxDst,\n  uint32_t numSamples)\n{\n  float32_t in;                                  /* Temporary variable to store input value */\n  uint32_t blkCnt;                               /* loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */\n  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */\n  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */\n  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */\n  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    /* read input from complex input buffer */\n    inA1 = pSrcCmplx[0];\n    inA2 = pSrcCmplx[1];\n    /* read input from real input buffer */\n    inB1 = pSrcReal[0];\n\n    /* read input from complex input buffer */\n    inA3 = pSrcCmplx[2];\n\n    /* multiply complex buffer real input with real buffer input */\n    out1 = inA1 * inB1;\n\n    /* read input from complex input buffer */\n    inA4 = pSrcCmplx[3];\n\n    /* multiply complex buffer imaginary input with real buffer input */\n    out2 = inA2 * inB1;\n\n    /* read input from real input buffer */\n    inB2 = pSrcReal[1];\n    /* read input from complex input buffer */\n    inA5 = pSrcCmplx[4];\n\n    /* multiply complex buffer real input with real buffer input */\n    out3 = inA3 * inB2;\n\n    /* read input from complex input buffer */\n    inA6 = pSrcCmplx[5];\n    /* read input from real input buffer */\n    inB3 = pSrcReal[2];\n\n    /* multiply complex buffer imaginary input with real buffer input */\n    out4 = inA4 * inB2;\n\n    /* read input from complex input buffer */\n    inA7 = pSrcCmplx[6];\n\n    /* multiply complex buffer real input with real buffer input */\n    out5 = inA5 * inB3;\n\n    /* read input from complex input buffer */\n    inA8 = pSrcCmplx[7];\n\n    /* multiply complex buffer imaginary input with real buffer input */\n    out6 = inA6 * inB3;\n\n    /* read input from real input buffer */\n    inB4 = pSrcReal[3];\n\n    /* store result to destination bufer */\n    pCmplxDst[0] = out1;\n\n    /* multiply complex buffer real input with real buffer input */\n    out7 = inA7 * inB4;\n\n    /* store result to destination bufer */\n    pCmplxDst[1] = out2;\n\n    /* multiply complex buffer imaginary input with real buffer input */\n    out8 = inA8 * inB4;\n\n    /* store result to destination bufer */\n    pCmplxDst[2] = out3;\n    pCmplxDst[3] = out4;\n    pCmplxDst[4] = out5;\n\n    /* incremnet complex input buffer by 8 to process next samples */\n    pSrcCmplx += 8u;\n\n    /* store result to destination bufer */\n    pCmplxDst[5] = out6;\n\n    /* increment real input buffer by 4 to process next samples */\n    pSrcReal += 4u;\n\n    /* store result to destination bufer */\n    pCmplxDst[6] = out7;\n    pCmplxDst[7] = out8;\n\n    /* increment destination buffer by 8 to process next sampels */\n    pCmplxDst += 8u;\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    in = *pSrcReal++;\n    /* store the result in the destination buffer. */\n    *pCmplxDst++ = (*pSrcCmplx++) * (in);\n    *pCmplxDst++ = (*pSrcCmplx++) * (in);\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n}\n\n/**        \n * @} end of CmplxByRealMult group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_real_q15.c    \n*    \n* Description:\tQ15 complex by real multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup CmplxByRealMult    \n * @{    \n */\n\n\n/**    \n * @brief  Q15 complex-by-real multiplication    \n * @param[in]  *pSrcCmplx points to the complex input vector    \n * @param[in]  *pSrcReal points to the real input vector    \n * @param[out]  *pCmplxDst points to the complex output vector    \n * @param[in]  numSamples number of samples in each vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    \n */\n\nvoid arm_cmplx_mult_real_q15(\n  q15_t * pSrcCmplx,\n  q15_t * pSrcReal,\n  q15_t * pCmplxDst,\n  uint32_t numSamples)\n{\n  q15_t in;                                      /* Temporary variable to store input value */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counters */\n  q31_t inA1, inA2;                              /* Temporary variables to hold input data */\n  q31_t inB1;                                    /* Temporary variables to hold input data */\n  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */\n  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    /* read complex number both real and imaginary from complex input buffer */\n    inA1 = *__SIMD32(pSrcCmplx)++;\n    /* read two real values at a time from real input buffer */\n    inB1 = *__SIMD32(pSrcReal)++;\n    /* read complex number both real and imaginary from complex input buffer */\n    inA2 = *__SIMD32(pSrcCmplx)++;\n\n    /* multiply complex number with real numbers */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));\n    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));\n    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));\n    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));\n\n#else\n\n    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));\n    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));\n    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);\n    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);\n\n#endif //      #ifndef ARM_MATH_BIG_ENDIAN\n\n    /* saturate the result */\n    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);\n    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);\n    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);\n    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);\n\n    /* pack real and imaginary outputs and store them to destination */\n    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);\n    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);\n\n    inA1 = *__SIMD32(pSrcCmplx)++;\n    inB1 = *__SIMD32(pSrcReal)++;\n    inA2 = *__SIMD32(pSrcCmplx)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));\n    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));\n    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));\n    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));\n\n#else\n\n    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));\n    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));\n    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);\n    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);\n\n#endif //      #ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);\n    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);\n    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);\n    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);\n\n    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);\n    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    in = *pSrcReal++;\n    /* store the result in the destination buffer. */\n    *pCmplxDst++ =\n      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);\n    *pCmplxDst++ =\n      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* realOut = realA * realB.            */\n    /* imagOut = imagA * realB.                */\n    in = *pSrcReal++;\n    /* store the result in the destination buffer. */\n    *pCmplxDst++ =\n      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);\n    *pCmplxDst++ =\n      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);\n\n    /* Decrement the numSamples loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of CmplxByRealMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cmplx_mult_real_q31.c    \n*    \n* Description:\tQ31 complex by real multiplication    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupCmplxMath    \n */\n\n/**    \n * @addtogroup CmplxByRealMult    \n * @{    \n */\n\n\n/**    \n * @brief  Q31 complex-by-real multiplication    \n * @param[in]  *pSrcCmplx points to the complex input vector    \n * @param[in]  *pSrcReal points to the real input vector    \n * @param[out]  *pCmplxDst points to the complex output vector    \n * @param[in]  numSamples number of samples in each vector    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    \n */\n\nvoid arm_cmplx_mult_real_q31(\n  q31_t * pSrcCmplx,\n  q31_t * pSrcReal,\n  q31_t * pCmplxDst,\n  uint32_t numSamples)\n{\n  q31_t inA1;                                    /* Temporary variable to store input value */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  uint32_t blkCnt;                               /* loop counters */\n  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */\n  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */\n  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */\n\n  /* loop Unrolling */\n  blkCnt = numSamples >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    /* read real input from complex input buffer */\n    inA1 = *pSrcCmplx++;\n    inA2 = *pSrcCmplx++;\n    /* read input from real input bufer */\n    inB1 = *pSrcReal++;\n    inB2 = *pSrcReal++;\n    /* read imaginary input from complex input buffer */\n    inA3 = *pSrcCmplx++;\n    inA4 = *pSrcCmplx++;\n\n    /* multiply complex input with real input */\n    out1 = ((q63_t) inA1 * inB1) >> 32;\n    out2 = ((q63_t) inA2 * inB1) >> 32;\n    out3 = ((q63_t) inA3 * inB2) >> 32;\n    out4 = ((q63_t) inA4 * inB2) >> 32;\n\n    /* sature the result */\n    out1 = __SSAT(out1, 31);\n    out2 = __SSAT(out2, 31);\n    out3 = __SSAT(out3, 31);\n    out4 = __SSAT(out4, 31);\n\n    /* get result in 1.31 format */\n    out1 = out1 << 1;\n    out2 = out2 << 1;\n    out3 = out3 << 1;\n    out4 = out4 << 1;\n\n    /* store the result to destination buffer */\n    *pCmplxDst++ = out1;\n    *pCmplxDst++ = out2;\n    *pCmplxDst++ = out3;\n    *pCmplxDst++ = out4;\n\n    /* read real input from complex input buffer */\n    inA1 = *pSrcCmplx++;\n    inA2 = *pSrcCmplx++;\n    /* read input from real input bufer */\n    inB1 = *pSrcReal++;\n    inB2 = *pSrcReal++;\n    /* read imaginary input from complex input buffer */\n    inA3 = *pSrcCmplx++;\n    inA4 = *pSrcCmplx++;\n\n    /* multiply complex input with real input */\n    out1 = ((q63_t) inA1 * inB1) >> 32;\n    out2 = ((q63_t) inA2 * inB1) >> 32;\n    out3 = ((q63_t) inA3 * inB2) >> 32;\n    out4 = ((q63_t) inA4 * inB2) >> 32;\n\n    /* sature the result */\n    out1 = __SSAT(out1, 31);\n    out2 = __SSAT(out2, 31);\n    out3 = __SSAT(out3, 31);\n    out4 = __SSAT(out4, 31);\n\n    /* get result in 1.31 format */\n    out1 = out1 << 1;\n    out2 = out2 << 1;\n    out3 = out3 << 1;\n    out4 = out4 << 1;\n\n    /* store the result to destination buffer */\n    *pCmplxDst++ = out1;\n    *pCmplxDst++ = out2;\n    *pCmplxDst++ = out3;\n    *pCmplxDst++ = out4;\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = numSamples % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C[2 * i] = A[2 * i] * B[i].            */\n    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */\n    /* read real input from complex input buffer */\n    inA1 = *pSrcCmplx++;\n    inA2 = *pSrcCmplx++;\n    /* read input from real input bufer */\n    inB1 = *pSrcReal++;\n\n    /* multiply complex input with real input */\n    out1 = ((q63_t) inA1 * inB1) >> 32;\n    out2 = ((q63_t) inA2 * inB1) >> 32;\n\n    /* sature the result */\n    out1 = __SSAT(out1, 31);\n    out2 = __SSAT(out2, 31);\n\n    /* get result in 1.31 format */\n    out1 = out1 << 1;\n    out2 = out2 << 1;\n\n    /* store the result to destination buffer */\n    *pCmplxDst++ = out1;\n    *pCmplxDst++ = out2;\n\n    /* Decrement the numSamples loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(numSamples > 0u)\n  {\n    /* realOut = realA * realB.            */\n    /* imagReal = imagA * realB.               */\n    inA1 = *pSrcReal++;\n    /* store the result in the destination buffer. */\n    *pCmplxDst++ =\n      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);\n    *pCmplxDst++ =\n      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);\n\n    /* Decrement the numSamples loop counter */\n    numSamples--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of CmplxByRealMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_init_f32.c    \n*    \n* Description:\tFloating-point PID Control initialization function    \n*\t\t\t\t   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the floating-point PID Control.   \n * @param[in,out] *S points to an instance of the PID structure.   \n * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.   \n * @return none.   \n * \\par Description:   \n * \\par    \n * The resetStateFlag specifies whether to set state to zero or not. \\n   \n * The function computes the structure fields: A0, A1 A2    \n * using the proportional gain( \\c Kp), integral gain( \\c Ki) and derivative gain( \\c Kd)    \n * also sets the state variables to all zeros.    \n */\n\nvoid arm_pid_init_f32(\n  arm_pid_instance_f32 * S,\n  int32_t resetStateFlag)\n{\n\n  /* Derived coefficient A0 */\n  S->A0 = S->Kp + S->Ki + S->Kd;\n\n  /* Derived coefficient A1 */\n  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);\n\n  /* Derived coefficient A2 */\n  S->A2 = S->Kd;\n\n  /* Check whether state needs reset or not */\n  if(resetStateFlag)\n  {\n    /* Clear the state buffer.  The size will be always 3 samples */\n    memset(S->state, 0, 3u * sizeof(float32_t));\n  }\n\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_init_q15.c    \n*    \n* Description:\tQ15 PID Control initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n * @details    \n * @param[in,out] *S points to an instance of the Q15 PID structure.    \n * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.    \n * @return none.    \n * \\par Description:   \n * \\par    \n * The resetStateFlag specifies whether to set state to zero or not. \\n   \n * The function computes the structure fields: A0, A1 A2    \n * using the proportional gain( \\c Kp), integral gain( \\c Ki) and derivative gain( \\c Kd)    \n * also sets the state variables to all zeros.    \n */\n\nvoid arm_pid_init_q15(\n  arm_pid_instance_q15 * S,\n  int32_t resetStateFlag)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Derived coefficient A0 */\n  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);\n\n  /* Derived coefficients and pack into A1 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);\n\n#else\n\n  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n  /* Check whether state needs reset or not */\n  if(resetStateFlag)\n  {\n    /* Clear the state buffer.  The size will be always 3 samples */\n    memset(S->state, 0, 3u * sizeof(q15_t));\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t temp;                                    /*to store the sum */\n\n  /* Derived coefficient A0 */\n  temp = S->Kp + S->Ki + S->Kd;\n  S->A0 = (q15_t) __SSAT(temp, 16);\n\n  /* Derived coefficients and pack into A1 */\n  temp = -(S->Kd + S->Kd + S->Kp);\n  S->A1 = (q15_t) __SSAT(temp, 16);\n  S->A2 = S->Kd;\n\n\n\n  /* Check whether state needs reset or not */\n  if(resetStateFlag)\n  {\n    /* Clear the state buffer.  The size will be always 3 samples */\n    memset(S->state, 0, 3u * sizeof(q15_t));\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_init_q31.c    \n*    \n* Description:\tQ31 PID Control initialization function     \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the Q31 PID Control.   \n * @param[in,out] *S points to an instance of the Q31 PID structure.   \n * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   \n * @return none.    \n * \\par Description:   \n * \\par    \n * The resetStateFlag specifies whether to set state to zero or not. \\n   \n * The function computes the structure fields: A0, A1 A2    \n * using the proportional gain( \\c Kp), integral gain( \\c Ki) and derivative gain( \\c Kd)    \n * also sets the state variables to all zeros.    \n */\n\nvoid arm_pid_init_q31(\n  arm_pid_instance_q31 * S,\n  int32_t resetStateFlag)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Derived coefficient A0 */\n  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);\n\n  /* Derived coefficient A1 */\n  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t temp;\n\n  /* Derived coefficient A0 */\n  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);\n  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);\n\n  /* Derived coefficient A1 */\n  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);\n  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Derived coefficient A2 */\n  S->A2 = S->Kd;\n\n  /* Check whether state needs reset or not */\n  if(resetStateFlag)\n  {\n    /* Clear the state buffer.  The size will be always 3 samples */\n    memset(S->state, 0, 3u * sizeof(q31_t));\n  }\n\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_reset_f32.c    \n*    \n* Description:\tFloating-point PID Control reset function   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n* @brief  Reset function for the floating-point PID Control.   \n* @param[in] *S\tInstance pointer of PID control data structure.   \n* @return none.    \n* \\par Description:   \n* The function resets the state buffer to zeros.    \n*/\nvoid arm_pid_reset_f32(\n  arm_pid_instance_f32 * S)\n{\n\n  /* Clear the state buffer.  The size will be always 3 samples */\n  memset(S->state, 0, 3u * sizeof(float32_t));\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_reset_q15.c    \n*    \n* Description:\tQ15 PID Control reset function   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n* @brief  Reset function for the Q15 PID Control.   \n* @param[in] *S\t\tInstance pointer of PID control data structure.   \n* @return none.    \n* \\par Description:   \n* The function resets the state buffer to zeros.    \n*/\nvoid arm_pid_reset_q15(\n  arm_pid_instance_q15 * S)\n{\n  /* Reset state to zero, The size will be always 3 samples */\n  memset(S->state, 0, 3u * sizeof(q15_t));\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_pid_reset_q31.c    \n*    \n* Description:\tQ31 PID Control reset function   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n /**    \n * @addtogroup PID    \n * @{    \n */\n\n/**    \n* @brief  Reset function for the Q31 PID Control.   \n* @param[in] *S\tInstance pointer of PID control data structure.   \n* @return none.    \n* \\par Description:   \n* The function resets the state buffer to zeros.    \n*/\nvoid arm_pid_reset_q31(\n  arm_pid_instance_q31 * S)\n{\n\n  /* Clear the state buffer.  The size will be always 3 samples */\n  memset(S->state, 0, 3u * sizeof(q31_t));\n}\n\n/**    \n * @} end of PID group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_sin_cos_f32.c    \n*    \n* Description:\tSine and Cosine calculation for floating-point values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupController    \n */\n\n/**    \n * @defgroup SinCos Sine Cosine   \n *    \n * Computes the trigonometric sine and cosine values using a combination of table lookup   \n * and linear interpolation.     \n * There are separate functions for Q31 and floating-point data types.   \n * The input to the floating-point version is in degrees while the   \n * fixed-point Q31 have a scaled input with the range   \n * [-1 0.9999] mapping to [-180 179] degrees.   \n *   \n * The implementation is based on table lookup using 360 values together with linear interpolation.   \n * The steps used are:   \n *  -# Calculation of the nearest integer table index.   \n *  -# Compute the fractional portion (fract) of the input.   \n *  -# Fetch the value corresponding to \\c index from sine table to \\c y0 and also value from \\c index+1 to \\c y1.      \n *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).    \n *  -# Fetch the value corresponding to \\c index from cosine table to \\c y0 and also value from \\c index+1 to \\c y1.      \n *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).    \n */\n\n /**    \n * @addtogroup SinCos    \n * @{    \n */\n\n\n/**    \n* \\par    \n* Cosine Table is generated from following loop    \n* 
for(i = 0; i < 360; i++)    \n* {    \n*    cosTable[i]= cos((i-180) * PI/180.0);    \n* } 
   \n*/\n\nstatic const float32_t cosTable[360] = {\n  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,\n  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,\n  -0.992546151641321980f, -0.990268068741570250f,\n  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,\n  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,\n  -0.965925826289068200f, -0.961261695938318670f,\n  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,\n  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,\n  -0.920504853452440150f, -0.913545457642600760f,\n  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,\n  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,\n  -0.857167300702112220f, -0.848048096156425960f,\n  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,\n  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,\n  -0.777145961456970680f, -0.766044443118977900f,\n  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,\n  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,\n  -0.681998360062498370f, -0.669130606358858240f,\n  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,\n  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,\n  -0.573576436351045830f, -0.559192903470746680f,\n  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,\n  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,\n  -0.453990499739546750f, -0.438371146789077510f,\n  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,\n  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,\n  -0.325568154457156420f, -0.309016994374947340f,\n  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,\n  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,\n  -0.190808995376544800f, -0.173648177666930300f,\n  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,\n  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,\n  -0.052335956242943620f, -0.034899496702500733f,\n  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,\n  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,\n  0.087155742747658138f, 0.104528463267653460f,\n  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,\n  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,\n  0.224951054343864920f, 0.241921895599667900f,\n  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,\n  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,\n  0.358367949545300380f, 0.374606593415911960f,\n  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,\n  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,\n  0.484809620246337110f, 0.500000000000000110f,\n  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,\n  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,\n  0.601815023152048270f, 0.615661475325658290f,\n  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,\n  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,\n  0.707106781186547570f, 0.719339800338651190f,\n  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,\n  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,\n  0.798635510047292830f, 0.809016994374947450f,\n  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,\n  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,\n  0.874619707139395740f, 0.882947592858926990f,\n  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,\n  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,\n  0.933580426497201740f, 0.939692620785908430f,\n  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,\n  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,\n  0.974370064785235250f, 0.978147600733805690f,\n  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,\n  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,\n  0.996194698091745550f, 0.997564050259824200f,\n  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,\n  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,\n  0.998629534754573830f, 0.997564050259824200f,\n  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,\n  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,\n  0.981627183447663980f, 0.978147600733805690f,\n  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,\n  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,\n  0.945518575599316850f, 0.939692620785908430f,\n  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,\n  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,\n  0.891006524188367900f, 0.882947592858926990f,\n  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,\n  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,\n  0.819152044288991800f, 0.809016994374947450f,\n  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,\n  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,\n  0.731353701619170570f, 0.719339800338651190f,\n  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,\n  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,\n  0.629320391049837500f, 0.615661475325658290f,\n  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,\n  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,\n  0.515038074910054380f, 0.500000000000000110f,\n  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,\n  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,\n  0.390731128489273940f, 0.374606593415911960f,\n  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,\n  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,\n  0.258819045102520740f, 0.241921895599667900f,\n  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,\n  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,\n  0.121869343405147490f, 0.104528463267653460f,\n  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,\n  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,\n  -0.017452406437283477f, -0.034899496702500733f,\n  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,\n  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,\n  -0.156434465040231040f, -0.173648177666930300f,\n  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,\n  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,\n  -0.292371704722736660f, -0.309016994374947340f,\n  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,\n  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,\n  -0.422618261740699330f, -0.438371146789077510f,\n  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,\n  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,\n  -0.544639035015027080f, -0.559192903470746680f,\n  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,\n  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,\n  -0.656059028990507500f, -0.669130606358858240f,\n  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,\n  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,\n  -0.754709580222772010f, -0.766044443118977900f,\n  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,\n  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,\n  -0.838670567945424160f, -0.848048096156425960f,\n  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,\n  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,\n  -0.906307787036649940f, -0.913545457642600760f,\n  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,\n  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,\n  -0.956304755963035440f, -0.961261695938318670f,\n  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,\n  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,\n  -0.987688340595137660f, -0.990268068741570250f,\n  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,\n  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,\n  -0.999847695156391270f, -1.000000000000000000f\n};\n\n/**    \n* \\par    \n* Sine Table is generated from following loop    \n* 
for(i = 0; i < 360; i++)    \n* {    \n*    sinTable[i]= sin((i-180) * PI/180.0);    \n* } 
    \n*/\n\n\nstatic const float32_t sinTable[360] = {\n  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,\n  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,\n  -0.121869343405147550f, -0.139173100960065740f,\n  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,\n  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,\n  -0.258819045102521020f, -0.275637355816999660f,\n  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,\n  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,\n  -0.390731128489274160f, -0.406736643075800430f,\n  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,\n  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,\n  -0.515038074910054380f, -0.529919264233204900f,\n  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,\n  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,\n  -0.629320391049837720f, -0.642787609686539470f,\n  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,\n  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,\n  -0.731353701619170570f, -0.743144825477394240f,\n  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,\n  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,\n  -0.819152044288992020f, -0.829037572555041740f,\n  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,\n  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,\n  -0.891006524188367900f, -0.898794046299166930f,\n  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,\n  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,\n  -0.945518575599316850f, -0.951056516295153640f,\n  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,\n  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,\n  -0.981627183447663980f, -0.984807753012208020f,\n  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,\n  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,\n  -0.998629534754573830f, -0.999390827019095760f,\n  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,\n  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,\n  -0.996194698091745550f, -0.994521895368273290f,\n  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,\n  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,\n  -0.974370064785235250f, -0.970295726275996470f,\n  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,\n  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,\n  -0.933580426497201740f, -0.927183854566787420f,\n  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,\n  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,\n  -0.874619707139395740f, -0.866025403784438600f,\n  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,\n  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,\n  -0.798635510047292830f, -0.788010753606722010f,\n  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,\n  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,\n  -0.707106781186547460f, -0.694658370458997250f,\n  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,\n  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,\n  -0.601815023152048270f, -0.587785252292473140f,\n  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,\n  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,\n  -0.484809620246337060f, -0.469471562785890810f,\n  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,\n  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,\n  -0.358367949545300270f, -0.342020143325668710f,\n  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,\n  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,\n  -0.224951054343865000f, -0.207911690817759310f,\n  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,\n  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,\n  -0.087155742747658166f, -0.069756473744125302f,\n  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,\n  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,\n  0.052335956242943828f, 0.069756473744125302f,\n  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,\n  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,\n  0.190808995376544800f, 0.207911690817759310f,\n  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,\n  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,\n  0.325568154457156640f, 0.342020143325668710f,\n  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,\n  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,\n  0.453990499739546750f, 0.469471562785890810f,\n  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,\n  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,\n  0.573576436351046050f, 0.587785252292473140f,\n  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,\n  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,\n  0.681998360062498480f, 0.694658370458997250f,\n  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,\n  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,\n  0.777145961456970790f, 0.788010753606722010f,\n  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,\n  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,\n  0.857167300702112220f, 0.866025403784438600f,\n  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,\n  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,\n  0.920504853452440260f, 0.927183854566787420f,\n  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,\n  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,\n  0.965925826289068310f, 0.970295726275996470f,\n  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,\n  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,\n  0.992546151641321980f, 0.994521895368273290f,\n  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,\n  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,\n  0.999847695156391270f, 0.999390827019095760f,\n  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,\n  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,\n  0.987688340595137660f, 0.984807753012208020f,\n  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,\n  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,\n  0.956304755963035550f, 0.951056516295153640f,\n  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,\n  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,\n  0.906307787036650050f, 0.898794046299166930f,\n  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,\n  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,\n  0.838670567945424050f, 0.829037572555041740f,\n  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,\n  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,\n  0.754709580222771790f, 0.743144825477394240f,\n  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,\n  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,\n  0.656059028990507280f, 0.642787609686539470f,\n  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,\n  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,\n  0.544639035015026860f, 0.529919264233204900f,\n  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,\n  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,\n  0.422618261740699500f, 0.406736643075800430f,\n  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,\n  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,\n  0.292371704722737050f, 0.275637355816999660f,\n  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,\n  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,\n  0.156434465040230980f, 0.139173100960065740f,\n  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,\n  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,\n  0.017452406437283439f, 0.000000000000000122f\n};\n\n\n/**    \n * @brief  Floating-point sin_cos function.   \n * @param[in]  theta    input value in degrees    \n * @param[out] *pSinVal points to the processed sine output.    \n * @param[out] *pCosVal points to the processed cos output.    \n * @return none.   \n */\n\n\nvoid arm_sin_cos_f32(\n  float32_t theta,\n  float32_t * pSinVal,\n  float32_t * pCosVal)\n{\n  int32_t i;                                     /* Index for reading nearwst output values */\n  float32_t x1 = -179.0f;                        /* Initial input value */\n  float32_t y0, y1;                              /* nearest output values */\n  float32_t y2, y3;\n  float32_t fract;                               /* fractional part of input */\n\n  /* Calculation of fractional part */\n  if(theta > 0.0f)\n  {\n    fract = theta - (float32_t) ((int32_t) theta);\n  }\n  else\n  {\n    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;\n  }\n\n  /* index calculation for reading nearest output values */\n  i = (uint32_t) (theta - x1);\n\n  /* Checking min and max index of table */\n  if(i < 0)\n  {\n    i = 0;\n  }\n  else if(i >= 359)\n  {\n    i = 358;\n  }\n\n  /* reading nearest sine output values */\n  y0 = sinTable[i];\n  y1 = sinTable[i + 1u];\n\n  /* reading nearest cosine output values */\n  y2 = cosTable[i];\n  y3 = cosTable[i + 1u];\n\n  y1 = y1 - y0;\n  y3 = y3 - y2;\n\n  y1 = fract * y1;\n  y3 = fract * y3;\n\n  /* Calculation of sine value */\n  *pSinVal = y0 + y1;\n\n  /* Calculation of cosine value */\n  *pCosVal = y2 + y3;\n\n}\n\n/**    \n * @} end of SinCos group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_sin_cos_q31.c    \n*    \n* Description:\tCosine & Sine calculation for Q31 values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupController    \n */\n\n /**    \n * @addtogroup SinCos    \n * @{    \n */\n\n/**    \n* \\par    \n* Sine Table is generated from following loop    \n* 
for(i = 0; i < 360; i++)    \n* {    \n*    sinTable[i]= sin((i-180) * PI/180.0);    \n* } 
   \n* Convert above coefficients to fixed point 1.31 format.    \n*/\n\nstatic const int32_t sinTableQ31[360] = {\n\n  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,\n  0xf06695da,\n  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,\n  0xe108b40d, 0xdedf047d,\n  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,\n  0xd00ce422, 0xcdfc85bb,\n  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,\n  0xc0000000, 0xbe133b7c,\n  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,\n  0xb1320139, 0xaf726def,\n  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,\n  0xa3ecac65, 0xa263007d,\n  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,\n  0x98722192, 0x9726069c,\n  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,\n  0x8efb92c2, 0x8df37f8b,\n  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,\n  0x87b826f7, 0x86f93f50,\n  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,\n  0x82cc0f36, 0x825a0a5b,\n  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,\n  0x804fd23a, 0x802ce84c,\n  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,\n  0x804fd23a, 0x807cb130,\n  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,\n  0x82cc0f36, 0x8347d77b,\n  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,\n  0x87b826f7, 0x88806fc4,\n  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,\n  0x8efb92c2, 0x900c7621,\n  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,\n  0x98722192, 0x99c64fc5,\n  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,\n  0xa3ecac65, 0xa57d8666,\n  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,\n  0xb1320139, 0xb2f7b9af,\n  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,\n  0xc0000000, 0xc1f1c224,\n  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,\n  0xd00ce422, 0xd220ffc0,\n  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,\n  0xe108b40d, 0xe334cdc9,\n  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,\n  0xf29ecfb2, 0xf4d814a4,\n  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,\n  0x6b2f1d2,\n  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,\n  0x163a1a7e, 0x186c6ddd,\n  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,\n  0x278dde6e, 0x29ac37a0,\n  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,\n  0x381c8bb5, 0x3a1c5c57,\n  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,\n  0x4793a210, 0x496af3e2,\n  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,\n  0x55a6125c, 0x574bb8e6,\n  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,\n  0x620dbe8b, 0x637984d4,\n  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,\n  0x6c8cd70b, 0x6db7a87a,\n  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,\n  0x74ef0ebc, 0x75d31a61,\n  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,\n  0x7b0a9f8d, 0x7ba3751d,\n  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,\n  0x7ec11aa5, 0x7f0bc097,\n  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,\n  0x7fffffff, 0x7ffb0260,\n  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,\n  0x7ec11aa5, 0x7e6c9251,\n  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,\n  0x7b0a9f8d, 0x7a6831ba,\n  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,\n  0x74ef0ebc, 0x7401e4c1,\n  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,\n  0x6c8cd70b, 0x6b598ea3,\n  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,\n  0x620dbe8b, 0x609a52d3,\n  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,\n  0x55a6125c, 0x53f9be05,\n  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,\n  0x4793a210, 0x45b6bb5e,\n  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,\n  0x381c8bb5, 0x36185aee,\n  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,\n  0x278dde6e, 0x256c6f9f,\n  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,\n  0x163a1a7e, 0x14060b68,\n  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,\n  0x4779632, 0x23be165,\n\n\n};\n\n/**    \n* \\par    \n* Cosine Table is generated from following loop    \n* 
for(i = 0; i < 360; i++)    \n* {    \n*    cosTable[i]= cos((i-180) * PI/180.0);    \n* } 
   \n* \\par    \n* Convert above coefficients to fixed point 1.31 format.    \n*/\nstatic const int32_t cosTableQ31[360] = {\n  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,\n  0x80b381ac, 0x80f43f69,\n  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,\n  0x83cd5982, 0x845c8ae3,\n  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,\n  0x89520a1a, 0x8a2ce59f,\n  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,\n  0x9126145f, 0x92485786,\n  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,\n  0x9b2276b0, 0x9c867b2c,\n  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,\n  0xa7156f3c, 0xa8b4471a,\n  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,\n  0xb4c373ee, 0xb6950c1e,\n  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,\n  0xc3e85b18, 0xc5e3a3a9,\n  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,\n  0xd438af17, 0xd653c860,\n  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,\n  0xe5632654, 0xe7939223,\n  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,\n  0xf7123849, 0xf94d0e2e,\n  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,\n  0xb27eb5c,\n  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,\n  0x1a9cd9ac, 0x1ccb3237,\n  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,\n  0x2bc750e9, 0x2ddf0040,\n  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,\n  0x3c17a4e8, 0x3e0e3ddc,\n  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,\n  0x4b3c8c12, 0x4d084651,\n  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,\n  0x58ea90c4, 0x5a82799a,\n  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,\n  0x64dd8950, 0x6639b03b,\n  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,\n  0x6ed9eba1, 0x6ff389df,\n  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,\n  0x76adf5e6, 0x777f903c,\n  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,\n  0x7c32a67e, 0x7cb82885,\n  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,\n  0x7f4c7e54, 0x7f834ed0,\n  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,\n  0x7fec09e3, 0x7fd317b4,\n  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,\n  0x7e0e2e32, 0x7da5f5a5,\n  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,\n  0x79bc384d, 0x7906c0b0,\n  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,\n  0x730baeed, 0x720c8075,\n  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,\n  0x6a1de737, 0x68d9f964,\n  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,\n  0x5f1f5ea1, 0x5d9cff83,\n  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,\n  0x5246dd49, 0x508d9211,\n  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,\n  0x43d464fb, 0x41ecc484,\n  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,\n  0x340ff242, 0x32037a45,\n  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,\n  0x234815ba, 0x2120fb83,\n  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,\n  0x11d06c97, 0xf996a26,\n  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,\n  0xfdc41e9b,\n  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,\n  0xee2f9369, 0xebf9f498,\n  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,\n  0xdcb7ea46, 0xda939061,\n  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,\n  0xcbf00dbe, 0xc9e7a512,\n  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,\n  0xbc2b9b05, 0xba4944a2,\n  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,\n  0xadb922b7, 0xac0641fb,\n  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,\n  0xa0e0a15f, 0x9f65ad2d,\n  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,\n  0x95e218c9, 0x94a6715d,\n  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,\n  0x8cf45113, 0x8bfe1b3f,\n  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,\n  0x8643c7b3, 0x8597ce46,\n  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,\n  0x81f1d1ce, 0x81936daf,\n  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,\n  0x8013f61d, 0x8004fda0,\n\n};\n\n\n/**    \n * @brief  Q31 sin_cos function.   \n * @param[in]  theta    scaled input value in degrees    \n * @param[out] *pSinVal points to the processed sine output.    \n * @param[out] *pCosVal points to the processed cosine output.    \n * @return none.   \n *    \n * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].   \n *    \n */\n\n\nvoid arm_sin_cos_q31(\n  q31_t theta,\n  q31_t * pSinVal,\n  q31_t * pCosVal)\n{\n  q31_t x0;                                      /* Nearest input value */\n  q31_t y0, y1;                                  /* Nearest output values */\n  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */\n  uint32_t i;                                    /* Index */\n  q31_t oneByXSpacing;                           /* 1/ xSpacing value */\n  q31_t out;                                     /* temporary variable */\n  uint32_t sign_bits;                            /* No.of sign bits */\n  uint32_t firstX = 0x80000000;                  /* First X value */\n\n  /* Calculation of index */\n  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;\n\n  /* Checking min and max index of table */\n  if(i >= 359)\n  {\n    i = 358;\n  }\n\n  /* Calculation of first nearest input value */\n  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);\n\n  /* Reading nearest sine output values from table */\n  y0 = sinTableQ31[i];\n  y1 = sinTableQ31[i + 1u];\n\n  /* Calculation of 1/(x1-x0) */\n  /* (x1-x0) is xSpacing which is fixed value */\n  sign_bits = 8u;\n  oneByXSpacing = 0x5A000000;\n\n  /* Calculation of (theta - x0)/(x1-x0) */\n  out =\n    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);\n\n  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */\n  *pSinVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));\n\n  /* Reading nearest cosine output values from table */\n  y0 = cosTableQ31[i];\n  y1 = cosTableQ31[i + 1u];\n\n  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */\n  *pCosVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));\n\n}\n\n/**    \n * @} end of SinCos group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cos_f32.c    \n*    \n* Description:\tFast cosine calculation for floating-point values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n/**    \n * @ingroup groupFastMath    \n */\n\n/**    \n * @defgroup cos Cosine    \n *    \n * Computes the trigonometric cosine function using a combination of table lookup   \n * and cubic interpolation.  There are separate functions for   \n * Q15, Q31, and floating-point data types.   \n * The input to the floating-point version is in radians while the   \n * fixed-point Q15 and Q31 have a scaled input with the range   \n * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a\n * value of 2*pi wraps around to 0.\n *   \n * The implementation is based on table lookup using 256 values together with cubic interpolation.   \n * The steps used are:   \n *  -# Calculation of the nearest integer table index   \n *  -# Fetch the four table values a, b, c, and d     \n *  -# Compute the fractional portion (fract) of the table index.   \n *  -# Calculation of wa, wb, wc, wd    \n *  -# The final result equals a*wa + b*wb + c*wc + d*wd   \n *   \n * where   \n * 
    \n *    a=Table[index-1];    \n *    b=Table[index+0];    \n *    c=Table[index+1];    \n *    d=Table[index+2];    \n * 
   \n * and   \n * 
    \n *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    \n *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    \n *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    \n *    wd=(1/6)*fract.^3 - (1/6)*fract;    \n * 
    \n */\n\n /**    \n * @addtogroup cos    \n * @{    \n */\n\n\n/**    \n* \\par    \n* Example code for Generation of Cos Table:\n* 
\n* tableSize = 256;    \n* for(n = -1; n < (tableSize + 2); n++)    \n* {    \n*\tcosTable[n+1]= cos(2*pi*n/tableSize);    \n* } 
    \n* where pi value is  3.14159265358979    \n*/\n\nstatic const float32_t cosTable[260] = {\n  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,\n  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,\n  0.992479562759399410f, 0.989176511764526370f,\n  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,\n  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,\n  0.949528157711029050f, 0.941544055938720700f,\n  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,\n  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,\n  0.870086967945098880f, 0.857728600502014160f,\n  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,\n  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,\n  0.757208824157714840f, 0.740951120853424070f,\n  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,\n  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,\n  0.615231573581695560f, 0.595699310302734380f,\n  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,\n  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,\n  0.449611335992813110f, 0.427555084228515630f,\n  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,\n  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,\n  0.266712754964828490f, 0.242980182170867920f,\n  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,\n  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,\n  0.073564566671848297f, 0.049067676067352295f,\n  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,\n  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,\n  -0.122410677373409270f, -0.146730467677116390f,\n  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,\n  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,\n  -0.313681751489639280f, -0.336889863014221190f,\n  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,\n  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,\n  -0.492898195981979370f, -0.514102756977081300f,\n  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,\n  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,\n  -0.653172850608825680f, -0.671558976173400880f,\n  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,\n  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,\n  -0.788346409797668460f, -0.803207516670227050f,\n  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,\n  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,\n  -0.893224298954010010f, -0.903989315032958980f,\n  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,\n  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,\n  -0.963776051998138430f, -0.970031261444091800f,\n  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,\n  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,\n  -0.997290432453155520f, -0.998795449733734130f,\n  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,\n  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,\n  -0.992479562759399410f, -0.989176511764526370f,\n  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,\n  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,\n  -0.949528157711029050f, -0.941544055938720700f,\n  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,\n  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,\n  -0.870086967945098880f, -0.857728600502014160f,\n  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,\n  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,\n  -0.757208824157714840f, -0.740951120853424070f,\n  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,\n  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,\n  -0.615231573581695560f, -0.595699310302734380f,\n  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,\n  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,\n  -0.449611335992813110f, -0.427555084228515630f,\n  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,\n  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,\n  -0.266712754964828490f, -0.242980182170867920f,\n  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,\n  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,\n  -0.073564566671848297f, -0.049067676067352295f,\n  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,\n  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,\n  0.122410677373409270f, 0.146730467677116390f,\n  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,\n  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,\n  0.313681751489639280f, 0.336889863014221190f,\n  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,\n  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,\n  0.492898195981979370f, 0.514102756977081300f,\n  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,\n  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,\n  0.653172850608825680f, 0.671558976173400880f,\n  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,\n  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,\n  0.788346409797668460f, 0.803207516670227050f,\n  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,\n  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,\n  0.893224298954010010f, 0.903989315032958980f,\n  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,\n  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,\n  0.963776051998138430f, 0.970031261444091800f,\n  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,\n  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,\n  0.997290432453155520f, 0.998795449733734130f,\n  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,\n  0.998795449733734130f\n};\n\n/**   \n * @brief  Fast approximation to the trigonometric cosine function for floating-point data.   \n * @param[in] x input value in radians.   \n * @return cos(x).   \n */\n\n\nfloat32_t arm_cos_f32(\n  float32_t x)\n{\n  float32_t cosVal, fract, in;\n  int32_t index;\n  uint32_t tableSize = (uint32_t) TABLE_SIZE;\n  float32_t wa, wb, wc, wd;\n  float32_t a, b, c, d;\n  float32_t *tablePtr;\n  int32_t n;\n  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;\n  float32_t oneminusfractby2;\n  float32_t frby2xfrsq, frby6xfrsq;\n\n  /* input x is in radians */\n  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */\n  in = x * 0.159154943092f;\n\n  /* Calculation of floor value of input */\n  n = (int32_t) in;\n\n  /* Make negative values towards -infinity */\n  if(x < 0.0f)\n  {\n    n = n - 1;\n  }\n\n  /* Map input value to [0 1] */\n  in = in - (float32_t) n;\n\n  /* Calculation of index of the table */\n  index = (uint32_t) (tableSize * in);\n\n  /* fractional value calculation */\n  fract = ((float32_t) tableSize * in) - (float32_t) index;\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (float32_t *) & cosTable[index];\n\n  /* Read four nearest values of input value from the cos table */\n  a = tablePtr[0];\n  b = tablePtr[1];\n  c = tablePtr[2];\n  d = tablePtr[3];\n\n  /* Cubic interpolation process */\n  fractsq = fract * fract;\n  fractby2 = fract * 0.5f;\n  fractby6 = fract * 0.166666667f;\n  fractby3 = fract * 0.3333333333333f;\n  fractsqby2 = fractsq * 0.5f;\n  frby2xfrsq = (fractby2) * fractsq;\n  frby6xfrsq = (fractby6) * fractsq;\n  oneminusfractby2 = 1.0f - fractby2;\n  wb = fractsqby2 - fractby3;\n  wc = (fractsqby2 + fract);\n  wa = wb - frby6xfrsq;\n  wb = frby2xfrsq - fractsq;\n  cosVal = wa * a;\n  wc = wc - frby2xfrsq;\n  wd = (frby6xfrsq) - fractby6;\n  wb = wb + oneminusfractby2;\n\n  /* Calculate cos value */\n  cosVal = (cosVal + (b * wb)) + ((c * wc) + (d * wd));\n\n  /* Return the output value */\n  return (cosVal);\n\n}\n\n/**    \n * @} end of cos group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cos_q15.c    \n*    \n* Description:\tFast cosine calculation for Q15 values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFastMath    \n */\n\n /**    \n * @addtogroup cos    \n * @{    \n */\n\n/**   \n* \\par    \n * Table values are in Q15 (1.15 fixed-point format) and generation is done in \n * three steps.  First,  generate cos values in floating point:    \n * 
\n * tableSize = 256;\n * for(n = -1; n < (tableSize + 1); n++)    \n * {    \n *\tcosTable[n+1]= cos(2*pi*n/tableSize);    \n * } 
     \n * where pi value is  3.14159265358979    \n * \\par    \n * Second, convert floating-point to Q15 (fixed-point):    \n *\t(cosTable[i] * pow(2, 15))    \n * \\par    \n * Finally, round to the nearest integer value:\n * \tcosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    \n*/\n\nstatic const q15_t cosTableQ15[259] = {\n  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,\n  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,\n  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,\n  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,\n  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,\n  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,\n  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,\n  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,\n  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,\n  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,\n  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,\n  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,\n  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,\n  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,\n  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,\n  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,\n  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,\n  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,\n  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,\n  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,\n  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,\n  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,\n  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,\n  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,\n  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,\n  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,\n  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,\n  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,\n  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,\n  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,\n  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,\n  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,\n  0x7ff6, 0x7fff, 0x7ff6\n};\n\n\n/**   \n * @brief Fast approximation to the trigonometric cosine function for Q15 data.   \n * @param[in] x Scaled input value in radians.   \n * @return  cos(x).   \n *   \n * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian\n * value in the range [0 2*pi).\n */\n\nq15_t arm_cos_q15(\n  q15_t x)\n{\n  q31_t cosVal;                                  /* Temporary variable for output */\n  q15_t *tablePtr;                               /* Pointer to table */\n  q15_t in, in2;                                 /* Temporary variables for input */\n  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */\n  q15_t a, b, c, d;                              /* Four nearest output values */\n  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */\n  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */\n  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */\n  int32_t index;                                 /* Index variable */\n\n  in = x;\n\n  /* Calculate the nearest index */\n  index = (int32_t) in / tableSpacing;\n\n  /* Calculate the nearest value of input */\n  in2 = (q15_t) index *tableSpacing;\n\n  /* Calculation of fractional value */\n  fract = (in - in2) << 8;\n\n  /* fractSquare = fract * fract */\n  fractSquare = (q15_t) ((fract * fract) >> 15);\n\n  /* fractCube = fract * fract * fract */\n  fractCube = (q15_t) ((fractSquare * fract) >> 15);\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (q15_t *) & cosTableQ15[index];\n\n  /* Cubic interpolation process */\n  /* Calculation of wa */\n  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */\n  wa = (q31_t) oneBy6 *fractCube;\n  wa += (q31_t) 0x2AAA *fract;\n  wa = -(wa >> 15);\n  wa += (fractSquare >> 1u);\n\n  /* Read first nearest value of output from the cos table */\n  a = *tablePtr++;\n\n  /* cosVal = a * wa */\n  cosVal = a * wa;\n\n  /* Calculation of wb */\n  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;\n\n  /* Read second nearest value of output from the cos table */\n  b = *tablePtr++;\n\n  /*      cosVal += b*wb */\n  cosVal += b * wb;\n\n  /* Calculation of wc */\n  wc = -(q31_t) fractCube + fractSquare;\n  wc = (wc >> 1u) + fract;\n\n  /* Read third nearest value of output from the cos table */\n  c = *tablePtr++;\n\n  /* cosVal += c*wc */\n  cosVal += c * wc;\n\n  /* Calculation of wd */\n  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */\n  fractCube = fractCube - fract;\n  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));\n\n  /* Read fourth nearest value of output from the cos table */\n  d = *tablePtr++;\n\n  /* cosVal += d*wd; */\n  cosVal += d * wd;\n\n  /* Convert output value in 1.15(q15) format and saturate */\n  cosVal = __SSAT((cosVal >> 15), 16);\n\n  /* Return the output value in 1.15(q15) format */\n  return ((q15_t) cosVal);\n\n}\n\n/**    \n * @} end of cos group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_cos_q31.c    \n*    \n* Description:\tFast cosine calculation for Q31 values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFastMath    \n */\n\n /**    \n * @addtogroup cos    \n * @{    \n */\n\n/**    \n * \\par    \n * Table values are in Q31 (1.31 fixed-point format) and generation is done in \n * three steps.  First,  generate cos values in floating point:    \n * 
\n * tableSize = 256;      \n * for(n = -1; n < (tableSize + 1); n++)    \n * {    \n *\tcosTable[n+1]= cos(2*pi*n/tableSize);    \n * } 
     \n * where pi value is  3.14159265358979    \n * \\par    \n * Second, convert floating-point to Q31 (Fixed point):\n *\t(cosTable[i] * pow(2, 31))    \n * \\par    \n * Finally, round to the nearest integer value:\n * \tcosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    \n */\n\n\nstatic const q31_t cosTableQ31[259] = {\n  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,\n  0x7f0991c4, 0x7e9d55fc,\n  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,\n  0x798a23b1, 0x78848414,\n  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,\n  0x6f5f02b2, 0x6dca0d14,\n  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,\n  0x60ec3830, 0x5ed77c8a,\n  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,\n  0x4ebfe8a5, 0x4c3fdff4,\n  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,\n  0x398cdd32, 0x36ba2014,\n  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,\n  0x2223a4c5, 0x1f19f97b,\n  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,\n  0x96a9049, 0x647d97c,\n  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,\n  0xed37ef91,\n  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,\n  0xd7d946d8, 0xd4e0cb15,\n  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,\n  0xc0e8b648, 0xbe31e19b,\n  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,\n  0xac64d510, 0xaa0a5b2e,\n  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,\n  0x9b1776da, 0x99307ee0,\n  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,\n  0x8daad37b, 0x8c4a142f,\n  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,\n  0x84a2fc62, 0x83d60412,\n  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,\n  0x8058c94c, 0x80277872,\n  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,\n  0x80f66e3c, 0x8162aa04,\n  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,\n  0x8675dc4f, 0x877b7bec,\n  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,\n  0x90a0fd4e, 0x9235f2ec,\n  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,\n  0x9f13c7d0, 0xa1288376,\n  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,\n  0xb140175b, 0xb3c0200c,\n  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,\n  0xc67322ce, 0xc945dfec,\n  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,\n  0xdddc5b3b, 0xe0e60685,\n  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,\n  0xf6956fb7, 0xf9b82684,\n  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,\n  0x12c8106f,\n  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,\n  0x2826b928, 0x2b1f34eb,\n  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,\n  0x3f1749b8, 0x41ce1e65,\n  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,\n  0x539b2af0, 0x55f5a4d2,\n  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,\n  0x64e88926, 0x66cf8120,\n  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,\n  0x72552c85, 0x73b5ebd1,\n  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,\n  0x7b5d039e, 0x7c29fbee,\n  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,\n  0x7fa736b4, 0x7fd8878e,\n  0x7ff62182, 0x7fffffff, 0x7ff62182\n};\n\n/**   \n * @brief Fast approximation to the trigonometric cosine function for Q31 data.   \n * @param[in] x Scaled input value in radians.   \n * @return  cos(x).   \n *   \n * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian\n * value in the range [0 2*pi).\n */\n\nq31_t arm_cos_q31(\n  q31_t x)\n{\n  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */\n  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */\n  q31_t a, b, c, d;                              /* Four nearest output values */\n  q31_t *tablePtr;                               /* Pointer to table */\n  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */\n  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */\n  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */\n  q31_t temp;                                    /* Temporary variable for intermediate process */\n  int32_t index;                                 /* Index variable */\n\n  in = x;\n\n  /* Calculate the nearest index */\n  index = in / tableSpacing;\n\n  /* Calculate the nearest value of input */\n  in2 = ((q31_t) index) * tableSpacing;\n\n  /* Calculation of fractional value */\n  fract = (in - in2) << 8;\n\n  /* fractSquare = fract * fract */\n  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));\n  fractSquare = fractSquare << 1;\n\n  /* fractCube = fract * fract * fract */\n  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));\n  fractCube = fractCube << 1;\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (q31_t *) & cosTableQ31[index];\n\n  /* Cubic interpolation process */\n  /* Calculation of wa */\n  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */\n  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));\n  temp = 0x2AAAAAAA;\n  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);\n  wa = -(wa << 1u);\n  wa += (fractSquare >> 1u);\n\n  /* Read first nearest value of output from the cos table */\n  a = *tablePtr++;\n\n  /* cosVal = a*wa */\n  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));\n\n  /* q31(1.31) Fixed point value of 1 */\n  temp = 0x7FFFFFFF;\n\n  /* Calculation of wb */\n  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;\n  /* Read second nearest value of output from the cos table */\n  b = *tablePtr++;\n\n  /*      cosVal += b*wb */\n  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);\n\n  /* Calculation of wc */\n  wc = -fractCube + fractSquare;\n  wc = (wc >> 1u) + fract;\n  /* Read third nearest values of output value from the cos table */\n  c = *tablePtr++;\n\n  /*      cosVal += c*wc */\n  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);\n\n  /* Calculation of wd */\n  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */\n  fractCube = fractCube - fract;\n  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));\n  wd = (wd << 1u);\n\n  /* Read fourth nearest value of output from the cos table */\n  d = *tablePtr++;\n\n  /* cosVal += d*wd; */\n  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);\n\n\n  /* convert cosVal in 2.30 format to 1.31 format */\n  return (__QADD(cosVal, cosVal));\n\n}\n\n/**    \n * @} end of cos group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_sin_f32.c    \n*    \n* Description:\tFast sine calculation for floating-point values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFastMath    \n */\n\n/**    \n * @defgroup sin Sine    \n *    \n * Computes the trigonometric sine function using a combination of table lookup   \n * and cubic interpolation.  There are separate functions for   \n * Q15, Q31, and floating-point data types.   \n * The input to the floating-point version is in radians while the   \n * fixed-point Q15 and Q31 have a scaled input with the range   \n * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a\n * value of 2*pi wraps around to 0.\n *   \n * The implementation is based on table lookup using 256 values together with cubic interpolation.   \n * The steps used are:   \n *  -# Calculation of the nearest integer table index   \n *  -# Fetch the four table values a, b, c, and d     \n *  -# Compute the fractional portion (fract) of the table index.   \n *  -# Calculation of wa, wb, wc, wd    \n *  -# The final result equals a*wa + b*wb + c*wc + d*wd   \n *   \n * where   \n * 
    \n *    a=Table[index-1];    \n *    b=Table[index+0];    \n *    c=Table[index+1];    \n *    d=Table[index+2];    \n * 
   \n * and   \n * 
    \n *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    \n *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    \n *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    \n *    wd=(1/6)*fract.^3 - (1/6)*fract;    \n * 
    \n */\n\n/**    \n * @addtogroup sin    \n * @{    \n */\n\n\n/**   \n * \\par    \n * Example code for the generation of the floating-point sine table:\n * 
\n * tableSize = 256;    \n * for(n = -1; n < (tableSize + 1); n++)    \n * {    \n *\tsinTable[n+1]=sin(2*pi*n/tableSize);    \n * }
    \n * \\par    \n * where pi value is  3.14159265358979    \n */\n\nstatic const float32_t sinTable[259] = {\n  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,\n  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,\n  0.122410677373409270f, 0.146730467677116390f,\n  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,\n  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,\n  0.313681751489639280f, 0.336889863014221190f,\n  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,\n  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,\n  0.492898195981979370f, 0.514102756977081300f,\n  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,\n  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,\n  0.653172850608825680f, 0.671558976173400880f,\n  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,\n  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,\n  0.788346409797668460f, 0.803207516670227050f,\n  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,\n  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,\n  0.893224298954010010f, 0.903989315032958980f,\n  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,\n  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,\n  0.963776051998138430f, 0.970031261444091800f,\n  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,\n  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,\n  0.997290432453155520f, 0.998795449733734130f,\n  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,\n  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,\n  0.992479562759399410f, 0.989176511764526370f,\n  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,\n  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,\n  0.949528157711029050f, 0.941544055938720700f,\n  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,\n  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,\n  0.870086967945098880f, 0.857728600502014160f,\n  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,\n  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,\n  0.757208824157714840f, 0.740951120853424070f,\n  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,\n  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,\n  0.615231573581695560f, 0.595699310302734380f,\n  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,\n  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,\n  0.449611335992813110f, 0.427555084228515630f,\n  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,\n  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,\n  0.266712754964828490f, 0.242980182170867920f,\n  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,\n  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,\n  0.073564566671848297f, 0.049067676067352295f,\n  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,\n  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,\n  -0.122410677373409270f, -0.146730467677116390f,\n  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,\n  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,\n  -0.313681751489639280f, -0.336889863014221190f,\n  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,\n  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,\n  -0.492898195981979370f, -0.514102756977081300f,\n  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,\n  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,\n  -0.653172850608825680f, -0.671558976173400880f,\n  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,\n  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,\n  -0.788346409797668460f, -0.803207516670227050f,\n  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,\n  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,\n  -0.893224298954010010f, -0.903989315032958980f,\n  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,\n  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,\n  -0.963776051998138430f, -0.970031261444091800f,\n  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,\n  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,\n  -0.997290432453155520f, -0.998795449733734130f,\n  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,\n  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,\n  -0.992479562759399410f, -0.989176511764526370f,\n  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,\n  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,\n  -0.949528157711029050f, -0.941544055938720700f,\n  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,\n  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,\n  -0.870086967945098880f, -0.857728600502014160f,\n  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,\n  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,\n  -0.757208824157714840f, -0.740951120853424070f,\n  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,\n  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,\n  -0.615231573581695560f, -0.595699310302734380f,\n  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,\n  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,\n  -0.449611335992813110f, -0.427555084228515630f,\n  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,\n  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,\n  -0.266712754964828490f, -0.242980182170867920f,\n  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,\n  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,\n  -0.073564566671848297f, -0.049067676067352295f,\n  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f\n};\n\n\n/**   \n * @brief  Fast approximation to the trigonometric sine function for floating-point data.   \n * @param[in] x input value in radians.   \n * @return  sin(x).   \n */\n\nfloat32_t arm_sin_f32(\n  float32_t x)\n{\n  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */\n  int32_t index;                                 /* Index variable */\n  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */\n  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */\n  float32_t a, b, c, d;                          /* Four nearest output values */\n  float32_t *tablePtr;                           /* Pointer to table */\n  int32_t n;\n  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;\n  float32_t oneminusfractby2;\n  float32_t frby2xfrsq, frby6xfrsq;\n\n  /* input x is in radians */\n  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */\n  in = x * 0.159154943092f;\n\n  /* Calculation of floor value of input */\n  n = (int32_t) in;\n\n  /* Make negative values towards -infinity */\n  if(x < 0.0f)\n  {\n    n = n - 1;\n  }\n\n  /* Map input value to [0 1] */\n  in = in - (float32_t) n;\n\n  /* Calculation of index of the table */\n  index = (uint32_t) (tableSize * in);\n\n  /* fractional value calculation */\n  fract = ((float32_t) tableSize * in) - (float32_t) index;\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (float32_t *) & sinTable[index];\n\n  /* Read four nearest values of input value from the sin table */\n  a = tablePtr[0];\n  b = tablePtr[1];\n  c = tablePtr[2];\n  d = tablePtr[3];\n\n  /* Cubic interpolation process */\n  fractsq = fract * fract;\n  fractby2 = fract * 0.5f;\n  fractby6 = fract * 0.166666667f;\n  fractby3 = fract * 0.3333333333333f;\n  fractsqby2 = fractsq * 0.5f;\n  frby2xfrsq = (fractby2) * fractsq;\n  frby6xfrsq = (fractby6) * fractsq;\n  oneminusfractby2 = 1.0f - fractby2;\n  wb = fractsqby2 - fractby3;\n  wc = (fractsqby2 + fract);\n  wa = wb - frby6xfrsq;\n  wb = frby2xfrsq - fractsq;\n  sinVal = wa * a;\n  wc = wc - frby2xfrsq;\n  wd = (frby6xfrsq) - fractby6;\n  wb = wb + oneminusfractby2;\n\n  /* Calculate sin value */\n  sinVal = (sinVal + (b * wb)) + ((c * wc) + (d * wd));\n\n  /* Return the output value */\n  return (sinVal);\n\n}\n\n/**    \n * @} end of sin group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_sin_q15.c    \n*    \n* Description:\tFast sine calculation for Q15 values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFastMath    \n */\n\n /**    \n * @addtogroup sin    \n * @{    \n */\n\n\n/**   \n* \\par    \n * Table values are in Q15 (1.15 fixed-point format) and generation is done in \n * three steps.  First,  generate sin values in floating point:    \n * 
\n * tableSize = 256;\n * for(n = -1; n < (tableSize + 1); n++)    \n * {    \n *\tsinTable[n+1]= sin(2*pi*n/tableSize);    \n * } 
     \n * where pi value is  3.14159265358979    \n * \\par    \n * Second, convert floating-point to Q15 (fixed-point):    \n *\t(sinTable[i] * pow(2, 15))    \n * \\par    \n * Finally, round to the nearest integer value:\n * \tsinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    \n*/\n\nstatic const q15_t sinTableQ15[259] = {\n  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,\n  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,\n  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,\n  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,\n  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,\n  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,\n  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,\n  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,\n  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,\n  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,\n  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,\n  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,\n  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,\n  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,\n  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,\n  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,\n  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,\n  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,\n  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,\n  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,\n  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,\n  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,\n  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,\n  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,\n  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,\n  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,\n  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,\n  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,\n  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,\n  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,\n  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,\n  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,\n  0xfcdc, 0x0, 0x324\n};\n\n\n/**   \n * @brief Fast approximation to the trigonometric sine function for Q15 data.   \n * @param[in] x Scaled input value in radians.   \n * @return  sin(x).   \n *   \n * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).\n */\n\nq15_t arm_sin_q15(\n  q15_t x)\n{\n  q31_t sinVal;                                  /* Temporary variables output */\n  q15_t *tablePtr;                               /* Pointer to table */\n  q15_t fract, in, in2;                          /* Temporary variables for input, output */\n  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */\n  q15_t a, b, c, d;                              /* Four nearest output values */\n  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */\n  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */\n  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */\n  int32_t index;                                 /* Index variable */\n\n  in = x;\n\n  /* Calculate the nearest index */\n  index = (int32_t) in / tableSpacing;\n\n  /* Calculate the nearest value of input */\n  in2 = (q15_t) ((index) * tableSpacing);\n\n  /* Calculation of fractional value */\n  fract = (in - in2) << 8;\n\n  /* fractSquare = fract * fract */\n  fractSquare = (q15_t) ((fract * fract) >> 15);\n\n  /* fractCube = fract * fract * fract */\n  fractCube = (q15_t) ((fractSquare * fract) >> 15);\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (q15_t *) & sinTableQ15[index];\n\n  /* Cubic interpolation process */\n  /* Calculation of wa */\n  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */\n  wa = (q31_t) oneBy6 *fractCube;\n  wa += (q31_t) 0x2AAA *fract;\n  wa = -(wa >> 15);\n  wa += ((q31_t) fractSquare >> 1u);\n\n  /* Read first nearest value of output from the sin table */\n  a = *tablePtr++;\n\n  /* sinVal = a * wa */\n  sinVal = a * wa;\n\n  /* Calculation of wb */\n  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -\n    (((q31_t) fract >> 1u) - 0x7FFF);\n\n  /* Read second nearest value of output from the sin table */\n  b = *tablePtr++;\n\n  /*      sinVal += b*wb */\n  sinVal += b * wb;\n\n\n  /* Calculation of wc */\n  wc = -(q31_t) fractCube + fractSquare;\n  wc = (wc >> 1u) + fract;\n\n  /* Read third nearest value of output from the sin table */\n  c = *tablePtr++;\n\n  /* sinVal += c*wc */\n  sinVal += c * wc;\n\n  /* Calculation of wd */\n  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */\n  fractCube = fractCube - fract;\n  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));\n\n  /* Read fourth nearest value of output from the sin table */\n  d = *tablePtr++;\n\n  /* sinVal += d*wd; */\n  sinVal += d * wd;\n\n  /* Convert output value in 1.15(q15) format and saturate */\n  sinVal = __SSAT((sinVal >> 15), 16);\n\n  /* Return the output value in 1.15(q15) format */\n  return ((q15_t) sinVal);\n\n}\n\n/**    \n * @} end of sin group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_sin_q31.c    \n*    \n* Description:\tFast sine calculation for Q31 values.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFastMath    \n */\n\n /**    \n * @addtogroup sin    \n * @{    \n */\n\n/**   \n * \\par    \n * Table values are in Q31 (1.31 fixed-point format) and generation is done in \n * three steps.  First,  generate sin values in floating point:    \n * 
\n * tableSize = 256;      \n * for(n = -1; n < (tableSize + 1); n++)    \n * {    \n *\tsinTable[n+1]= sin(2*pi*n/tableSize);    \n * } 
    \n * where pi value is  3.14159265358979    \n * \\par    \n * Second, convert floating-point to Q31 (Fixed point):\n *\t(sinTable[i] * pow(2, 31))    \n * \\par    \n * Finally, round to the nearest integer value:\n * \tsinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    \n */\n\nstatic const q31_t sinTableQ31[259] = {\n  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,\n  0x12c8106f,\n  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,\n  0x2826b928, 0x2b1f34eb,\n  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,\n  0x3f1749b8, 0x41ce1e65,\n  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,\n  0x539b2af0, 0x55f5a4d2,\n  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,\n  0x64e88926, 0x66cf8120,\n  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,\n  0x72552c85, 0x73b5ebd1,\n  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,\n  0x7b5d039e, 0x7c29fbee,\n  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,\n  0x7fa736b4, 0x7fd8878e,\n  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,\n  0x7f0991c4, 0x7e9d55fc,\n  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,\n  0x798a23b1, 0x78848414,\n  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,\n  0x6f5f02b2, 0x6dca0d14,\n  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,\n  0x60ec3830, 0x5ed77c8a,\n  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,\n  0x4ebfe8a5, 0x4c3fdff4,\n  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,\n  0x398cdd32, 0x36ba2014,\n  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,\n  0x2223a4c5, 0x1f19f97b,\n  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,\n  0x96a9049, 0x647d97c,\n  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,\n  0xed37ef91,\n  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,\n  0xd7d946d8, 0xd4e0cb15,\n  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,\n  0xc0e8b648, 0xbe31e19b,\n  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,\n  0xac64d510, 0xaa0a5b2e,\n  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,\n  0x9b1776da, 0x99307ee0,\n  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,\n  0x8daad37b, 0x8c4a142f,\n  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,\n  0x84a2fc62, 0x83d60412,\n  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,\n  0x8058c94c, 0x80277872,\n  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,\n  0x80f66e3c, 0x8162aa04,\n  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,\n  0x8675dc4f, 0x877b7bec,\n  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,\n  0x90a0fd4e, 0x9235f2ec,\n  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,\n  0x9f13c7d0, 0xa1288376,\n  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,\n  0xb140175b, 0xb3c0200c,\n  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,\n  0xc67322ce, 0xc945dfec,\n  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,\n  0xdddc5b3b, 0xe0e60685,\n  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,\n  0xf6956fb7, 0xf9b82684,\n  0xfcdbd541, 0x0, 0x3242abf\n};\n\n\n/**   \n * @brief Fast approximation to the trigonometric sine function for Q31 data.\n * @param[in] x Scaled input value in radians.\n * @return  sin(x).\n *\n * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */\n\nq31_t arm_sin_q31(\n  q31_t x)\n{\n  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */\n  int32_t index;                                 /* Index variables */\n  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */\n  q31_t a, b, c, d;                              /* Four nearest output values */\n  q31_t *tablePtr;                               /* Pointer to table */\n  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */\n  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */\n  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */\n  q31_t temp;                                    /* Temporary variable for intermediate process */\n\n  in = x;\n\n  /* Calculate the nearest index */\n  index = (uint32_t) in / (uint32_t) tableSpacing;\n\n  /* Calculate the nearest value of input */\n  in2 = (q31_t) index *tableSpacing;\n\n  /* Calculation of fractional value */\n  fract = (in - in2) << 8;\n\n  /* fractSquare = fract * fract */\n  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));\n  fractSquare = fractSquare << 1;\n\n  /* fractCube = fract * fract * fract */\n  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));\n  fractCube = fractCube << 1;\n\n  /* Checking min and max index of table */\n  if(index < 0)\n  {\n    index = 0;\n  }\n  else if(index > 256)\n  {\n    index = 256;\n  }\n\n  /* Initialise table pointer */\n  tablePtr = (q31_t *) & sinTableQ31[index];\n\n  /* Cubic interpolation process */\n  /* Calculation of wa */\n  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */\n  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));\n  temp = 0x2AAAAAAA;\n  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);\n  wa = -(wa << 1u);\n  wa += (fractSquare >> 1u);\n\n  /* Read first nearest value of output from the sin table */\n  a = *tablePtr++;\n\n  /* sinVal = a*wa */\n  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));\n\n  /* q31(1.31) Fixed point value of 1 */\n  temp = 0x7FFFFFFF;\n\n  /* Calculation of wb */\n  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;\n\n  /* Read second nearest value of output from the sin table */\n  b = *tablePtr++;\n\n  /*  sinVal += b*wb */\n  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);\n\n  /* Calculation of wc */\n  wc = -fractCube + fractSquare;\n  wc = (wc >> 1u) + fract;\n\n  /* Read third nearest value of output from the sin table */\n  c = *tablePtr++;\n\n  /*      sinVal += c*wc */\n  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);\n\n  /* Calculation of wd */\n  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */\n  fractCube = fractCube - fract;\n  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));\n  wd = (wd << 1u);\n\n  /* Read fourth nearest value of output from the sin table */\n  d = *tablePtr++;\n\n  /* sinVal += d*wd; */\n  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);\n\n  /* convert sinVal in 2.30 format to 1.31 format */\n  return (__QADD(sinVal, sinVal));\n\n}\n\n/**    \n * @} end of sin group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c",
    "content": "/* ----------------------------------------------------------------------     \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.  \n*     \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*     \n* Project:      CMSIS DSP Library  \n* Title:\t\tarm_sqrt_q15.c     \n*     \n* Description:\tQ15 square root function.    \n*     \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n\n/**     \n * @ingroup groupFastMath     \n */\n\n/**     \n * @addtogroup SQRT     \n * @{     \n */\n\n  /**    \n   * @brief  Q15 square root function.    \n   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.    \n   * @param[out]  *pOut  square root of input value.    \n   * @return The function returns ARM_MATH_SUCCESS if the input value is positive\n   * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For\n   * negative inputs, the function returns *pOut = 0.\n   */\n\narm_status arm_sqrt_q15(\n  q15_t in,\n  q15_t * pOut)\n{\n  q15_t number, temp1, var1, signBits1, half;\n  q31_t bits_val1;\n  float32_t temp_float1;\n  union\n  {\n    q31_t fracval;\n    float32_t floatval;\n  } tempconv;\n\n  number = in;\n\n  /* If the input is a positive number then compute the signBits. */\n  if(number > 0)\n  {\n    signBits1 = __CLZ(number) - 17;\n\n    /* Shift by the number of signBits1 */\n    if((signBits1 % 2) == 0)\n    {\n      number = number << signBits1;\n    }\n    else\n    {\n      number = number << (signBits1 - 1);\n    }\n\n    /* Calculate half value of the number */\n    half = number >> 1;\n    /* Store the number for later use */\n    temp1 = number;\n\n    /*Convert to float */\n    temp_float1 = number * 3.051757812500000e-005f;\n    /*Store as integer */\n    tempconv.floatval = temp_float1;\n    bits_val1 = tempconv.fracval;\n    /* Subtract the shifted value from the magic number to give intial guess */\n    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  \n    /* Store as float */\n    tempconv.fracval = bits_val1;\n    temp_float1 = tempconv.floatval;\n    /* Convert to integer format */\n    var1 = (q31_t) (temp_float1 * 16384);\n\n    /* 1st iteration */\n    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -\n                                     ((q15_t)\n                                      ((((q15_t)\n                                         (((q31_t) var1 * var1) >> 15)) *\n                                        (q31_t) half) >> 15))) >> 15)) << 2;\n    /* 2nd iteration */\n    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -\n                                     ((q15_t)\n                                      ((((q15_t)\n                                         (((q31_t) var1 * var1) >> 15)) *\n                                        (q31_t) half) >> 15))) >> 15)) << 2;\n    /* 3rd iteration */\n    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -\n                                     ((q15_t)\n                                      ((((q15_t)\n                                         (((q31_t) var1 * var1) >> 15)) *\n                                        (q31_t) half) >> 15))) >> 15)) << 2;\n\n    /* Multiply the inverse square root with the original value */\n    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;\n\n    /* Shift the output down accordingly */\n    if((signBits1 % 2) == 0)\n    {\n      var1 = var1 >> (signBits1 / 2);\n    }\n    else\n    {\n      var1 = var1 >> ((signBits1 - 1) / 2);\n    }\n    *pOut = var1;\n\n    return (ARM_MATH_SUCCESS);\n  }\n  /* If the number is a negative number then store zero as its square root value */\n  else\n  {\n    *pOut = 0;\n    return (ARM_MATH_ARGUMENT_ERROR);\n  }\n}\n\n/**     \n * @} end of SQRT group     \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c",
    "content": "/* ----------------------------------------------------------------------     \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.  \n*     \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*     \n* Project:      CMSIS DSP Library  \n* Title:\t\tarm_sqrt_q31.c     \n*     \n* Description:\tQ31 square root function.    \n*     \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**     \n * @ingroup groupFastMath     \n */\n\n/**     \n * @addtogroup SQRT     \n * @{     \n */\n\n/**    \n * @brief Q31 square root function.    \n * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.    \n * @param[out]  *pOut square root of input value.    \n * @return The function returns ARM_MATH_SUCCESS if the input value is positive\n * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For\n * negative inputs, the function returns *pOut = 0.\n */\n\narm_status arm_sqrt_q31(\n  q31_t in,\n  q31_t * pOut)\n{\n  q31_t number, temp1, bits_val1, var1, signBits1, half;\n  float32_t temp_float1;\n  union\n  {\n      q31_t fracval;\n      float32_t floatval;\n  } tempconv;\n\n  number = in;\n\n  /* If the input is a positive number then compute the signBits. */\n  if(number > 0)\n  {\n    signBits1 = __CLZ(number) - 1;\n\n    /* Shift by the number of signBits1 */\n    if((signBits1 % 2) == 0)\n    {\n      number = number << signBits1;\n    }\n    else\n    {\n      number = number << (signBits1 - 1);\n    }\n\n    /* Calculate half value of the number */\n    half = number >> 1;\n    /* Store the number for later use */\n    temp1 = number;\n\n    /*Convert to float */\n    temp_float1 = number * 4.6566128731e-010f;\n    /*Store as integer */\n    tempconv.floatval = temp_float1;\n    bits_val1 = tempconv.fracval;\n    /* Subtract the shifted value from the magic number to give intial guess */\n    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  \n    /* Store as float */\n    tempconv.fracval = bits_val1;\n    temp_float1 = tempconv.floatval;\n    /* Convert to integer format */\n    var1 = (q31_t) (temp_float1 * 1073741824);\n\n    /* 1st iteration */\n    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -\n                                     ((q31_t)\n                                      ((((q31_t)\n                                         (((q63_t) var1 * var1) >> 31)) *\n                                        (q63_t) half) >> 31))) >> 31)) << 2;\n    /* 2nd iteration */\n    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -\n                                     ((q31_t)\n                                      ((((q31_t)\n                                         (((q63_t) var1 * var1) >> 31)) *\n                                        (q63_t) half) >> 31))) >> 31)) << 2;\n    /* 3rd iteration */\n    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -\n                                     ((q31_t)\n                                      ((((q31_t)\n                                         (((q63_t) var1 * var1) >> 31)) *\n                                        (q63_t) half) >> 31))) >> 31)) << 2;\n\n    /* Multiply the inverse square root with the original value */\n    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;\n\n    /* Shift the output down accordingly */\n    if((signBits1 % 2) == 0)\n    {\n      var1 = var1 >> (signBits1 / 2);\n    }\n    else\n    {\n      var1 = var1 >> ((signBits1 - 1) / 2);\n    }\n    *pOut = var1;\n\n    return (ARM_MATH_SUCCESS);\n  }\n  /* If the number is a negative number then store zero as its square root value */\n  else\n  {\n    *pOut = 0;\n    return (ARM_MATH_ARGUMENT_ERROR);\n  }\n}\n\n/**     \n * @} end of SQRT group     \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_32x64_init_q31.c    \n*    \n* Description:\tHigh precision Q31 Biquad cascade filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1_32x64    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in,out] *S           \tpoints to an instance of the high precision Q31 Biquad cascade filter structure.    \n * @param[in]     numStages     number of 2nd order stages in the filter.    \n * @param[in]     *pCoeffs      points to the filter coefficients.    \n * @param[in]     *pState       points to the state buffer.    \n * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.    \n * @return        none    \n *    \n * Coefficient and State Ordering:    \n *    \n * \\par    \n * The coefficients are stored in the array pCoeffs in the following order:    \n * 
    \n *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n * 
    \n * where b1x and a1x are the coefficients for the first stage,    \n * b2x and a2x are the coefficients for the second stage,    \n * and so on.  The pCoeffs array contains a total of 5*numStages values.    \n *    \n * \\par    \n * The pState points to state variables array and size of each state variable is 1.63 format.    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    \n * The state variables are arranged in the state array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n */\n\nvoid arm_biquad_cas_df1_32x64_init_q31(\n  arm_biquad_cas_df1_32x64_ins_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q63_t * pState,\n  uint8_t postShift)\n{\n  /* Assign filter stages */\n  S->numStages = numStages;\n\n  /* Assign postShift to be applied to the output */\n  S->postShift = postShift;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always 4 * numStages */\n  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n}\n\n/**    \n * @} end of BiquadCascadeDF1_32x64 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_32x64_q31.c    \n*    \n* Description:\tHigh precision Q31 Biquad cascade filter processing function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter    \n *    \n * This function implements a high precision Biquad cascade filter which operates on    \n * Q31 data values.  The filter coefficients are in 1.31 format and the state variables    \n * are in 1.63 format.  The double precision state variables reduce quantization noise    \n * in the filter and provide a cleaner output.    \n * These filters are particularly useful when implementing filters in which the    \n * singularities are close to the unit circle.  This is common for low pass or high    \n * pass filters with very low cutoff frequencies.    \n *    \n * The function operates on blocks of input and output data    \n * and each call to the function processes blockSize samples through    \n * the filter. pSrc and pDst points to input and output arrays    \n * containing blockSize Q31 values.    \n *    \n * \\par Algorithm    \n * Each Biquad stage implements a second order filter using the difference equation:    \n * 
    \n *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n * 
    \n * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    \n * \\image html Biquad.gif \"Single Biquad filter stage\"    \n * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    \n * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    \n * Pay careful attention to the sign of the feedback coefficients.    \n * Some design tools use the difference equation    \n * 
    \n *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    \n * 
    \n * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    \n *    \n * \\par    \n * Higher order filters are realized as a cascade of second order sections.    \n * numStages refers to the number of second order stages used.    \n * For example, an 8th order filter would be realized with numStages=4 second order stages.    \n * \\image html BiquadCascade.gif \"8th order filter using a cascade of Biquad stages\"    \n * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    \n *    \n * \\par    \n * The pState points to state variables array .    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.    \n * The state variables are arranged in the array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n *    \n * \\par    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values of data in 1.63 format.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n *    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    \n *    \n * \\par Init Function    \n * There is also an associated initialization function which performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. \n *\n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros before static initialization.    \n * For example, to statically initialize the filter instance structure use    \n * 
    \n *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    \n * 
    \n * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    \n * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.    \n * \\par Fixed-Point Behavior    \n * Care must be taken while using Biquad Cascade 32x64 filter function.    \n * Following issues must be considered:    \n * - Scaling of coefficients    \n * - Filter gain    \n * - Overflow and saturation    \n *    \n * \\par    \n * Filter coefficients are represented as fractional values and    \n * restricted to lie in the range [-1 +1).    \n * The processing function has an additional scaling parameter postShift    \n * which allows the filter coefficients to exceed the range [+1 -1).    \n * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    \n * \\image html BiquadPostshift.gif \"Fixed-point Biquad with shift by postShift bits after accumulator\"    \n * This essentially scales the filter coefficients by 2^postShift.    \n * For example, to realize the coefficients    \n * 
    \n *    {1.5, -0.8, 1.2, 1.6, -0.9}    \n * 
    \n * set the Coefficient array to:    \n * 
    \n *    {0.75, -0.4, 0.6, 0.8, -0.45}    \n * 
    \n * and set postShift=1    \n *    \n * \\par    \n * The second thing to keep in mind is the gain through the filter.    \n * The frequency response of a Biquad filter is a function of its coefficients.    \n * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    \n * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    \n * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    \n *    \n * \\par    \n * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.    \n * This is described in the function specific documentation below.    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1_32x64    \n * @{    \n */\n\n/**    \n * @details    \n    \n * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.    \n * @param[in]  *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in]  blockSize number of samples to process.    \n * @return none.    \n *    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    \n * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    \n * 1.31 format by discarding the low 32 bits.    \n *    \n * \\par    \n * Two related functions are provided in the CMSIS DSP library.    \n * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.    \n * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.    \n */\n\nvoid arm_biquad_cas_df1_32x64_q31(\n  const arm_biquad_cas_df1_32x64_ins_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pIn = pSrc;                             /*  input pointer initialization  */\n  q31_t *pOut = pDst;                            /*  output pointer initialization */\n  q63_t *pState = S->pState;                     /*  state pointer initialization  */\n  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */\n  q63_t acc;                                     /*  accumulator                   */\n  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */\n  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */\n  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */\n  q31_t Xn;                                      /*  temporary input               */\n  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */\n  uint32_t sample, stage = S->numStages;         /*  loop counters                     */\n  q31_t acc_l, acc_h;                            /*  temporary output               */\n  uint32_t uShift = ((uint32_t) S->postShift + 1u);\n  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = (q31_t) (pState[0]);\n    Xn2 = (q31_t) (pState[1]);\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /* Apply loop unrolling and compute 4 output values simultaneously. */\n    /* The variable acc hold output value that is being computed and    \n     * stored in the destination buffer    \n     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n     */\n\n    sample = blockSize >> 2u;\n\n    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) Xn *b0;\n\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) Xn1 *b1;\n\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn2 *b2;\n\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn1, a1);\n\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn2, a2);\n\n      /* The result is converted to 1.63 , Yn2 variable is reused */\n      Yn2 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer in 1.31 format. */\n      *pOut = acc_h;\n\n      /* Read the second input into Xn2, to reuse the value */\n      Xn2 = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc +=  b1 * x[n-1] */\n      acc = (q63_t) Xn *b1;\n\n      /* acc =  b0 * x[n] */\n      acc += (q63_t) Xn2 *b0;\n\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn1 *b2;\n\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn2, a1);\n\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn1, a2);\n\n      /* The result is converted to 1.63, Yn1 variable is reused */\n      Yn1 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Read the third input into Xn1, to reuse the value */\n      Xn1 = *pIn++;\n\n      /* The result is converted to 1.31 */\n      /* Store the output in the destination buffer. */\n      *(pOut + 1u) = acc_h;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) Xn1 *b0;\n\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) Xn2 *b1;\n\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn *b2;\n\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn1, a1);\n\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn2, a2);\n\n      /* The result is converted to 1.63, Yn2 variable is reused  */\n      Yn2 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer in 1.31 format. */\n      *(pOut + 2u) = acc_h;\n\n      /* Read the fourth input into Xn, to reuse the value */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) Xn *b0;\n\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) Xn1 *b1;\n\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn2 *b2;\n\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn2, a1);\n\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn1, a2);\n\n      /* The result is converted to 1.63, Yn1 variable is reused  */\n      Yn1 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer in 1.31 format. */\n      *(pOut + 3u) = acc_h;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n\n      /* update output pointer */\n      pOut += 4u;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    sample = (blockSize & 0x3u);\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) Xn *b0;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) Xn1 *b1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn2 *b2;\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn1, a1);\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn2, a2);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      /* The result is converted to 1.63, Yn1 variable is reused  */\n      Yn1 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer in 1.31 format. */\n      *pOut++ = acc_h;\n      //Yn1 = acc << shift; \n\n      /* Store the output in the destination buffer in 1.31 format. */\n//      *pOut++ = (q31_t) (acc >> (32 - shift)); \n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  The first stage output is given as input to the second stage. */\n    pIn = pDst;\n\n    /* Reset to destination buffer working pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = (q63_t) Xn1;\n    *pState++ = (q63_t) Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /* The variable acc hold output value that is being computed and        \n     * stored in the destination buffer            \n     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]            \n     */\n\n    sample = blockSize;\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) Xn *b0;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) Xn1 *b1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) Xn2 *b2;\n      /* acc +=  a1 * y[n-1] */\n      acc += mult32x64(Yn1, a1);\n      /* acc +=  a2 * y[n-2] */\n      acc += mult32x64(Yn2, a2);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n\n      /* The result is converted to 1.63, Yn1 variable is reused  */\n      Yn1 = acc << shift;\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer in 1.31 format. */\n      *pOut++ = acc_h;\n\n      //Yn1 = acc << shift; \n\n      /* Store the output in the destination buffer in 1.31 format. */\n      //*pOut++ = (q31_t) (acc >> (32 - shift)); \n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  The first stage output is given as input to the second stage. */\n    pIn = pDst;\n\n    /* Reset to destination buffer working pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = (q63_t) Xn1;\n    *pState++ = (q63_t) Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n\n#endif /*    #ifndef ARM_MATH_CM0_FAMILY     */\n}\n\n  /**    \n   * @} end of BiquadCascadeDF1_32x64 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_f32.c    \n*    \n* Description:\tProcessing function for the    \n*               floating-point Biquad cascade DirectFormI(DF1) filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure    \n *    \n * This set of functions implements arbitrary order recursive (IIR) filters.    \n * The filters are implemented as a cascade of second order Biquad sections.    \n * The functions support Q15, Q31 and floating-point data types.  \n * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.    \n *    \n * The functions operate on blocks of input and output data and each call to the function    \n * processes blockSize samples through the filter.    \n * pSrc points to the array of input data and    \n * pDst points to the array of output data.    \n * Both arrays contain blockSize values.    \n *    \n * \\par Algorithm    \n * Each Biquad stage implements a second order filter using the difference equation:    \n * 
    \n *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n * 
    \n * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    \n * \\image html Biquad.gif \"Single Biquad filter stage\"    \n * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    \n * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    \n * Pay careful attention to the sign of the feedback coefficients.    \n * Some design tools use the difference equation    \n * 
    \n *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    \n * 
    \n * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    \n *    \n * \\par    \n * Higher order filters are realized as a cascade of second order sections.    \n * numStages refers to the number of second order stages used.    \n * For example, an 8th order filter would be realized with numStages=4 second order stages.    \n * \\image html BiquadCascade.gif \"8th order filter using a cascade of Biquad stages\"    \n * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    \n *    \n * \\par    \n * The pState points to state variables array.    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    \n * The state variables are arranged in the pState array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n *    \n * \\par    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values.    \n * The state variables are updated after each block of data is processed, the coefficients are untouched.    \n *    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Init Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numStages, pCoeffs, pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros before static initialization.    \n * The code below statically initializes each of the 3 different data type filter instance structures    \n * 
    \n *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    \n *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    \n *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    \n * 
    \n * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    \n * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.    \n *    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.    \n * Following issues must be considered:    \n * - Scaling of coefficients    \n * - Filter gain    \n * - Overflow and saturation    \n *    \n * \\par    \n * Scaling of coefficients:     \n * Filter coefficients are represented as fractional values and    \n * coefficients are restricted to lie in the range [-1 +1).    \n * The fixed-point functions have an additional scaling parameter postShift    \n * which allow the filter coefficients to exceed the range [+1 -1).    \n * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    \n * \\image html BiquadPostshift.gif \"Fixed-point Biquad with shift by postShift bits after accumulator\"    \n * This essentially scales the filter coefficients by 2^postShift.    \n * For example, to realize the coefficients    \n * 
    \n *    {1.5, -0.8, 1.2, 1.6, -0.9}    \n * 
    \n * set the pCoeffs array to:    \n * 
    \n *    {0.75, -0.4, 0.6, 0.8, -0.45}    \n * 
    \n * and set postShift=1    \n *    \n * \\par    \n * Filter gain:     \n * The frequency response of a Biquad filter is a function of its coefficients.    \n * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    \n * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    \n * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    \n *    \n * \\par    \n * Overflow and saturation:     \n * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.    \n * @param[in]  *pSrc      points to the block of input data.    \n * @param[out] *pDst      points to the block of output data.    \n * @param[in]  blockSize  number of samples to process per call.    \n * @return     none.    \n *    \n */\n\nvoid arm_biquad_cascade_df1_f32(\n  const arm_biquad_casd_df1_inst_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pIn = pSrc;                         /*  source pointer            */\n  float32_t *pOut = pDst;                        /*  destination pointer       */\n  float32_t *pState = S->pState;                 /*  pState pointer            */\n  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */\n  float32_t acc;                                 /*  Simulates the accumulator */\n  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */\n  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */\n  float32_t Xn;                                  /*  temporary input           */\n  uint32_t sample, stage = S->numStages;         /*  loop counters             */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the pState values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /* Apply loop unrolling and compute 4 output values simultaneously. */\n    /*      The variable acc hold output values that are being computed:    \n     *    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    \n     */\n\n    sample = blockSize >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(sample > 0u)\n    {\n      /* Read the first input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = Yn2;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n\n      /* Read the second input */\n      Xn2 = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = Yn1;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n\n      /* Read the third input */\n      Xn1 = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = Yn2;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as: */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n\n      /* Read the forth input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = Yn1;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n\n      /* decrement the loop counter */\n      sample--;\n\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    sample = blockSize & 0x3u;\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = acc;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:    */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = acc;\n\n      /* decrement the loop counter */\n      sample--;\n\n    }\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent numStages  occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset the output pointer */\n    pOut = pDst;\n\n    /* decrement the loop counter */\n    stage--;\n\n  } while(stage > 0u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the pState values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /*      The variables acc holds the output value that is computed:        \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]        \n     */\n\n    sample = blockSize;\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = acc;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:    */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = acc;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent numStages  occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset the output pointer */\n    pOut = pDst;\n\n    /* decrement the loop counter */\n    stage--;\n\n  } while(stage > 0u);\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY         */\n\n}\n\n\n  /**    \n   * @} end of BiquadCascadeDF1 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_fast_q15.c    \n*    \n* Description:\tFast processing function for the    \n*\t\t\t\tQ15 Biquad cascade filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @details    \n * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    \n * @param[in]  *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in]  blockSize number of samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * This fast version uses a 32-bit accumulator with 2.30 format.    \n * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around and distorts the result.    \n * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).    \n * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.    \n *    \n * \\par    \n * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.    \n *    \n */\n\nvoid arm_biquad_cascade_df1_fast_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pIn = pSrc;                             /*  Source pointer                               */\n  q15_t *pOut = pDst;                            /*  Destination pointer                          */\n  q31_t in;                                      /*  Temporary variable to hold input value       */\n  q31_t out;                                     /*  Temporary variable to hold output value      */\n  q31_t b0;                                      /*  Temporary variable to hold bo value          */\n  q31_t b1, a1;                                  /*  Filter coefficients                          */\n  q31_t state_in, state_out;                     /*  Filter state variables                       */\n  q31_t acc;                                     /*  Accumulator                                  */\n  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */\n  q15_t *pState = S->pState;                     /*  State pointer                                */\n  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */\n  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */\n\n\n\n  do\n  {\n\n    /* Read the b0 and 0 coefficients using SIMD  */\n    b0 = *__SIMD32(pCoeffs)++;\n\n    /* Read the b1 and b2 coefficients using SIMD */\n    b1 = *__SIMD32(pCoeffs)++;\n\n    /* Read the a1 and a2 coefficients using SIMD */\n    a1 = *__SIMD32(pCoeffs)++;\n\n    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */\n    state_in = *__SIMD32(pState)++;\n\n    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */\n    state_out = *__SIMD32(pState)--;\n\n    /* Apply loop unrolling and compute 2 output values simultaneously. */\n    /*      The variable acc hold output values that are being computed:       \n     *    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       \n     */\n    sample = blockSize >> 1u;\n\n    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    \n     ** a second loop below computes the remaining 1 sample. */\n    while(sample > 0u)\n    {\n\n      /* Read the input */\n      in = *__SIMD32(pIn)++;\n\n      /* out =  b0 * x[n] + 0 * 0 */\n      out = __SMUAD(b0, in);\n      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */\n      acc = __SMLAD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */\n      acc = __SMLAD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 and then saturation is applied */\n      out = __SSAT((acc >> shift), 16);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);\n      state_out = __PKHBT(state_out >> 16, (out), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* out =  b0 * x[n] + 0 * 0 */\n      out = __SMUADX(b0, in);\n      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */\n      acc = __SMLAD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */\n      acc = __SMLAD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 and then saturation is applied */\n      out = __SSAT((acc >> shift), 16);\n\n\n      /* Store the output in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);\n\n#else\n\n      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in >> 16, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, in, 16);\n      state_out = __PKHBT(state_out >> 16, out, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n\n      /* Decrement the loop counter */\n      sample--;\n\n    }\n\n    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n\n    if((blockSize & 0x1u) != 0u)\n    {\n      /* Read the input */\n      in = *pIn++;\n\n      /* out =  b0 * x[n] + 0 * 0 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      out = __SMUAD(b0, in);\n\n#else\n\n      out = __SMUADX(b0, in);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */\n      acc = __SMLAD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */\n      acc = __SMLAD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 and then saturation is applied */\n      out = __SSAT((acc >> shift), 16);\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = (q15_t) out;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, in, 16);\n      state_out = __PKHBT(state_out >> 16, out, 16);\n\n#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n    }\n\n    /*  The first stage goes from the input buffer to the output buffer.  */\n    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */\n    pIn = pDst;\n\n    /* Reset the output pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the state array */\n    *__SIMD32(pState)++ = state_in;\n    *__SIMD32(pState)++ = state_out;\n\n\n    /* Decrement the loop counter */\n    stage--;\n\n  } while(stage > 0u);\n}\n\n\n/**    \n * @} end of BiquadCascadeDF1 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_fast_q31.c    \n*    \n* Description:\tProcessing function for the    \n*\t\t\t\tQ31 Fast Biquad cascade DirectFormI(DF1) filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.    \n * @param[in]  *pSrc     points to the block of input data.    \n * @param[out] *pDst     points to the block of output data.    \n * @param[in]  blockSize number of samples to process per call.    \n * @return \t   none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    \n * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    \n * These intermediate results are added to a 2.30 accumulator.    \n * Finally, the accumulator is saturated and converted to a 1.31 result.    \n * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function    \n * arm_biquad_cascade_df1_init_q31() to initialize filter structure.    \n *    \n * \\par    \n * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.    \n */\n\nvoid arm_biquad_cascade_df1_fast_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t acc = 0;                                 /*  accumulator                   */\n  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */\n  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */\n  q31_t *pIn = pSrc;                             /*  input pointer initialization  */\n  q31_t *pOut = pDst;                            /*  output pointer initialization */\n  q31_t *pState = S->pState;                     /*  pState pointer initialization */\n  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */\n  q31_t Xn;                                      /*  temporary input               */\n  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */\n  uint32_t sample, stage = S->numStages;         /*  loop counters                     */\n\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /* Apply loop unrolling and compute 4 output values simultaneously. */\n    /*      The variables acc ... acc3 hold output values that are being computed:       \n     *       \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       \n     */\n\n    sample = blockSize >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);\n      mult_32x32_keep32_R(acc, b1, Xn1);\n      /* acc +=  b1 * x[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);   \n      multAcc_32x32_keep32_R(acc, b0, Xn);\n      /* acc +=  b[2] * x[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, b2, Xn2);\n      /* acc +=  a1 * y[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, a1, Yn1);\n      /* acc +=  a2 * y[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, a2, Yn2);\n\n      /* The result is converted to 1.31 , Yn2 variable is reused */\n      Yn2 = acc << shift;\n\n      /* Read the second input */\n      Xn2 = *(pIn + 1u);\n\n      /* Store the output in the destination buffer. */\n      *pOut = Yn2;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);\n      mult_32x32_keep32_R(acc, b0, Xn2);\n      /* acc +=  b1 * x[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);\n      multAcc_32x32_keep32_R(acc, b1, Xn);\n      /* acc +=  b[2] * x[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, b2, Xn1);\n      /* acc +=  a1 * y[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, a1, Yn2);\n      /* acc +=  a2 * y[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, a2, Yn1);\n\n      /* The result is converted to 1.31, Yn1 variable is reused  */\n      Yn1 = acc << shift;\n\n      /* Read the third input  */\n      Xn1 = *(pIn + 2u);\n\n      /* Store the output in the destination buffer. */\n      *(pOut + 1u) = Yn1;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);\n      mult_32x32_keep32_R(acc, b0, Xn1);\n      /* acc +=  b1 * x[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, b1, Xn2);\n      /* acc +=  b[2] * x[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);\n      multAcc_32x32_keep32_R(acc, b2, Xn);\n      /* acc +=  a1 * y[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, a1, Yn1);\n      /* acc +=  a2 * y[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, a2, Yn2);\n\n      /* The result is converted to 1.31, Yn2 variable is reused  */\n      Yn2 = acc << shift;\n\n      /* Read the forth input */\n      Xn = *(pIn + 3u);\n\n      /* Store the output in the destination buffer. */\n      *(pOut + 2u) = Yn2;\n      pIn += 4u;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);\n      mult_32x32_keep32_R(acc, b0, Xn);\n      /* acc +=  b1 * x[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, b1, Xn1);\n      /* acc +=  b[2] * x[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, b2, Xn2);\n      /* acc +=  a1 * y[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, a1, Yn2);\n      /* acc +=  a2 * y[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, a2, Yn1);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      Xn2 = Xn1;\n\n      /* The result is converted to 1.31, Yn1 variable is reused  */\n      Yn1 = acc << shift;\n\n      /* Xn1 = Xn     */\n      Xn1 = Xn;\n\n      /* Store the output in the destination buffer. */\n      *(pOut + 3u) = Yn1;\n      pOut += 4u;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       \n     ** No loop unrolling is used. */\n    sample = (blockSize & 0x3u);\n\n   while(sample > 0u)\n   {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);\n      mult_32x32_keep32_R(acc, b0, Xn);\n      /* acc +=  b1 * x[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, b1, Xn1);\n      /* acc +=  b[2] * x[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, b2, Xn2);\n      /* acc +=  a1 * y[n-1] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);\n      multAcc_32x32_keep32_R(acc, a1, Yn1);\n      /* acc +=  a2 * y[n-2] */\n      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);\n      multAcc_32x32_keep32_R(acc, a2, Yn2);\n\n      /* The result is converted to 1.31  */\n      acc = acc << shift;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = acc;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = acc;\n\n      /* decrement the loop counter */\n      sample--;\n   }\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent stages occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset to destination pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n}\n\n/**    \n  * @} end of BiquadCascadeDF1 group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_biquad_cascade_df1_init_f32.c    \n*    \n* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @details    \n * @brief  Initialization function for the floating-point Biquad cascade filter.    \n * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    \n * @param[in]     numStages    number of 2nd order stages in the filter.    \n * @param[in]     *pCoeffs     points to the filter coefficients array.    \n * @param[in]     *pState      points to the state array.    \n * @return        none    \n *    \n *    \n * Coefficient and State Ordering:    \n *    \n * \\par    \n * The coefficients are stored in the array pCoeffs in the following order:    \n * 
    \n *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n * 
    \n *    \n * \\par    \n * where b1x and a1x are the coefficients for the first stage,    \n * b2x and a2x are the coefficients for the second stage,    \n * and so on.  The pCoeffs array contains a total of 5*numStages values.    \n *    \n * \\par    \n * The pState is a pointer to state array.    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    \n * The state variables are arranged in the pState array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n *    \n */\n\nvoid arm_biquad_cascade_df1_init_f32(\n  arm_biquad_casd_df1_inst_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState)\n{\n  /* Assign filter stages */\n  S->numStages = numStages;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always 4 * numStages */\n  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n}\n\n/**    \n * @} end of BiquadCascadeDF1 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_biquad_cascade_df1_init_q15.c    \n*    \n* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.    \n * @param[in]     numStages    number of 2nd order stages in the filter.    \n * @param[in]     *pCoeffs     points to the filter coefficients.    \n * @param[in]     *pState      points to the state buffer.    \n * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format    \n * @return        none    \n *    \n * Coefficient and State Ordering:    \n *    \n * \\par    \n * The coefficients are stored in the array pCoeffs in the following order:    \n * 
    \n *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    \n * 
    \n * where b1x and a1x are the coefficients for the first stage,    \n * b2x and a2x are the coefficients for the second stage,    \n * and so on.  The pCoeffs array contains a total of 6*numStages values.    \n * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.    \n *    \n * \\par    \n * The state variables are stored in the array pState.    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    \n * The state variables are arranged in the pState array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n */\n\nvoid arm_biquad_cascade_df1_init_q15(\n  arm_biquad_casd_df1_inst_q15 * S,\n  uint8_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int8_t postShift)\n{\n  /* Assign filter stages */\n  S->numStages = numStages;\n\n  /* Assign postShift to be applied to the output */\n  S->postShift = postShift;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always 4 * numStages */\n  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n}\n\n/**    \n * @} end of BiquadCascadeDF1 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_init_q31.c    \n*    \n* Description:\tQ31 Biquad cascade DirectFormI(DF1) filter initialization function.    \n*    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    \n * @param[in]     numStages    number of 2nd order stages in the filter.    \n * @param[in]     *pCoeffs     points to the filter coefficients buffer.    \n * @param[in]     *pState      points to the state buffer.    \n * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    \n * @return        none    \n *    \n * Coefficient and State Ordering:    \n *    \n * \\par    \n * The coefficients are stored in the array pCoeffs in the following order:    \n * 
    \n *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n * 
    \n * where b1x and a1x are the coefficients for the first stage,    \n * b2x and a2x are the coefficients for the second stage,    \n * and so on.  The pCoeffs array contains a total of 5*numStages values.    \n *    \n * \\par    \n * The pState points to state variables array.    \n * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    \n * The state variables are arranged in the pState array as:    \n * 
    \n *     {x[n-1], x[n-2], y[n-1], y[n-2]}    \n * 
    \n * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    \n * The state array has a total length of 4*numStages values.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n */\n\nvoid arm_biquad_cascade_df1_init_q31(\n  arm_biquad_casd_df1_inst_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int8_t postShift)\n{\n  /* Assign filter stages */\n  S->numStages = numStages;\n\n  /* Assign postShift to be applied to the output */\n  S->postShift = postShift;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always 4 * numStages */\n  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n}\n\n/**    \n * @} end of BiquadCascadeDF1 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_q15.c    \n*    \n* Description:\tProcessing function for the    \n*\t\t\t\tQ15 Biquad cascade DirectFormI(DF1) filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 Biquad cascade filter.    \n * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    \n * @param[in]  *pSrc points to the block of input data.    \n * @param[out] *pDst points to the location where the output result is written.    \n * @param[in]  blockSize number of samples to process per call.    \n * @return none.    \n *    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.    \n * Finally, the result is saturated to 1.15 format.    \n *    \n * \\par    \n * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_biquad_cascade_df1_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q15_t *pIn = pSrc;                             /*  Source pointer                               */\n  q15_t *pOut = pDst;                            /*  Destination pointer                          */\n  q31_t in;                                      /*  Temporary variable to hold input value       */\n  q31_t out;                                     /*  Temporary variable to hold output value      */\n  q31_t b0;                                      /*  Temporary variable to hold bo value          */\n  q31_t b1, a1;                                  /*  Filter coefficients                          */\n  q31_t state_in, state_out;                     /*  Filter state variables                       */\n  q31_t acc_l, acc_h;\n  q63_t acc;                                     /*  Accumulator                                  */\n  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */\n  q15_t *pState = S->pState;                     /*  State pointer                                */\n  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */\n  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */\n  int32_t uShift = (32 - lShift);\n\n  do\n  {\n    /* Read the b0 and 0 coefficients using SIMD  */\n    b0 = *__SIMD32(pCoeffs)++;\n\n    /* Read the b1 and b2 coefficients using SIMD */\n    b1 = *__SIMD32(pCoeffs)++;\n\n    /* Read the a1 and a2 coefficients using SIMD */\n    a1 = *__SIMD32(pCoeffs)++;\n\n    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */\n    state_in = *__SIMD32(pState)++;\n\n    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */\n    state_out = *__SIMD32(pState)--;\n\n    /* Apply loop unrolling and compute 2 output values simultaneously. */\n    /*      The variable acc hold output values that are being computed:    \n     *    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n     */\n    sample = blockSize >> 1u;\n\n    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    \n     ** a second loop below computes the remaining 1 sample. */\n    while(sample > 0u)\n    {\n\n      /* Read the input */\n      in = *__SIMD32(pIn)++;\n\n      /* out =  b0 * x[n] + 0 * 0 */\n      out = __SMUAD(b0, in);\n\n      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */\n      acc = __SMLALD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */\n      acc = __SMLALD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      out = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      out = __SSAT(out, 16);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);\n      state_out = __PKHBT(state_out >> 16, (out), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* out =  b0 * x[n] + 0 * 0 */\n      out = __SMUADX(b0, in);\n      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */\n      acc = __SMLALD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */\n      acc = __SMLALD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      out = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      out = __SSAT(out, 16);\n\n      /* Store the output in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);\n\n#else\n\n      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in >> 16, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, in, 16);\n      state_out = __PKHBT(state_out >> 16, out, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n\n      /* Decrement the loop counter */\n      sample--;\n\n    }\n\n    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n\n    if((blockSize & 0x1u) != 0u)\n    {\n      /* Read the input */\n      in = *pIn++;\n\n      /* out =  b0 * x[n] + 0 * 0 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      out = __SMUAD(b0, in);\n\n#else\n\n      out = __SMUADX(b0, in);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */\n      acc = __SMLALD(b1, state_in, out);\n      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */\n      acc = __SMLALD(a1, state_out, acc);\n\n      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      out = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      out = __SSAT(out, 16);\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = (q15_t) out;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc   */\n      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */\n      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      state_in = __PKHBT(in, state_in, 16);\n      state_out = __PKHBT(out, state_out, 16);\n\n#else\n\n      state_in = __PKHBT(state_in >> 16, in, 16);\n      state_out = __PKHBT(state_out >> 16, out, 16);\n\n#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n    }\n\n    /*  The first stage goes from the input wire to the output wire.  */\n    /*  Subsequent numStages occur in-place in the output wire  */\n    pIn = pDst;\n\n    /* Reset the output pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the state array */\n    *__SIMD32(pState)++ = state_in;\n    *__SIMD32(pState)++ = state_out;\n\n\n    /* Decrement the loop counter */\n    stage--;\n\n  } while(stage > 0u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t *pIn = pSrc;                             /*  Source pointer                               */\n  q15_t *pOut = pDst;                            /*  Destination pointer                          */\n  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */\n  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */\n  q15_t Xn;                                      /*  temporary input               */\n  q63_t acc;                                     /*  Accumulator                                  */\n  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */\n  q15_t *pState = S->pState;                     /*  State pointer                                */\n  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */\n  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    pCoeffs++;  // skip the 0 coefficient\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /*      The variables acc holds the output value that is computed:         \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         \n     */\n\n    sample = blockSize;\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      acc = (q31_t) b0 *Xn;\n\n      /* acc +=  b1 * x[n-1] */\n      acc += (q31_t) b1 *Xn1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q31_t) b2 *Xn2;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q31_t) a1 *Yn1;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q31_t) a2 *Yn2;\n\n      /* The result is converted to 1.31  */\n      acc = __SSAT((acc >> shift), 16);\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = (q15_t) acc;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = (q15_t) acc;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent stages occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset to destination pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n\n#endif /*     #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n/**    \n * @} end of BiquadCascadeDF1 group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df1_q31.c    \n*    \n* Description:\tProcessing function for the    \n*\t\t\t\tQ31 Biquad cascade filter    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF1    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 Biquad cascade filter.    \n * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.    \n * @param[in]  *pSrc      points to the block of input data.    \n * @param[out] *pDst      points to the block of output data.    \n * @param[in]  blockSize  number of samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    \n * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    \n * 1.31 format by discarding the low 32 bits.    \n *    \n * \\par    \n * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_biquad_cascade_df1_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q63_t acc;                                     /*  accumulator                   */\n  uint32_t uShift = ((uint32_t) S->postShift + 1u);\n  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */\n  q31_t *pIn = pSrc;                             /*  input pointer initialization  */\n  q31_t *pOut = pDst;                            /*  output pointer initialization */\n  q31_t *pState = S->pState;                     /*  pState pointer initialization */\n  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */\n  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */\n  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */\n  q31_t Xn;                                      /*  temporary input               */\n  uint32_t sample, stage = S->numStages;         /*  loop counters                     */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q31_t acc_l, acc_h;                            /*  temporary output variables    */\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /* Apply loop unrolling and compute 4 output values simultaneously. */\n    /*      The variable acc hold output values that are being computed:    \n     *    \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n     */\n\n    sample = blockSize >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn2;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn1;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn2;\n\n      /* The result is converted to 1.31 , Yn2 variable is reused */\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = Yn2;\n\n      /* Read the second input */\n      Xn2 = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn2;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn1;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn2;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn1;\n\n\n      /* The result is converted to 1.31, Yn1 variable is reused  */\n\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = Yn1;\n\n      /* Read the third input  */\n      Xn1 = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn1;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn2;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn1;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn2;\n\n      /* The result is converted to 1.31, Yn2 variable is reused  */\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = Yn2;\n\n      /* Read the forth input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn2;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn2;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn1;\n\n      /* The result is converted to 1.31, Yn1 variable is reused  */\n      /* Calc lower part of acc */\n      acc_l = acc & 0xffffffff;\n\n      /* Calc upper part of acc */\n      acc_h = (acc >> 32) & 0xffffffff;\n\n      /* Apply shift for lower part of acc and upper part of acc */\n      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = Yn1;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    sample = (blockSize & 0x3u);\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn;\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn2;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn1;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn2;\n\n      /* The result is converted to 1.31  */\n      acc = acc >> lShift;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = (q31_t) acc;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = (q31_t) acc;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent stages occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset to destination pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  do\n  {\n    /* Reading the coefficients */\n    b0 = *pCoeffs++;\n    b1 = *pCoeffs++;\n    b2 = *pCoeffs++;\n    a1 = *pCoeffs++;\n    a2 = *pCoeffs++;\n\n    /* Reading the state values */\n    Xn1 = pState[0];\n    Xn2 = pState[1];\n    Yn1 = pState[2];\n    Yn2 = pState[3];\n\n    /*      The variables acc holds the output value that is computed:         \n     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         \n     */\n\n    sample = blockSize;\n\n    while(sample > 0u)\n    {\n      /* Read the input */\n      Xn = *pIn++;\n\n      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */\n      /* acc =  b0 * x[n] */\n      acc = (q63_t) b0 *Xn;\n\n      /* acc +=  b1 * x[n-1] */\n      acc += (q63_t) b1 *Xn1;\n      /* acc +=  b[2] * x[n-2] */\n      acc += (q63_t) b2 *Xn2;\n      /* acc +=  a1 * y[n-1] */\n      acc += (q63_t) a1 *Yn1;\n      /* acc +=  a2 * y[n-2] */\n      acc += (q63_t) a2 *Yn2;\n\n      /* The result is converted to 1.31  */\n      acc = acc >> lShift;\n\n      /* Every time after the output is computed state should be updated. */\n      /* The states should be updated as:  */\n      /* Xn2 = Xn1    */\n      /* Xn1 = Xn     */\n      /* Yn2 = Yn1    */\n      /* Yn1 = acc    */\n      Xn2 = Xn1;\n      Xn1 = Xn;\n      Yn2 = Yn1;\n      Yn1 = (q31_t) acc;\n\n      /* Store the output in the destination buffer. */\n      *pOut++ = (q31_t) acc;\n\n      /* decrement the loop counter */\n      sample--;\n    }\n\n    /*  The first stage goes from the input buffer to the output buffer. */\n    /*  Subsequent stages occur in-place in the output buffer */\n    pIn = pDst;\n\n    /* Reset to destination pointer */\n    pOut = pDst;\n\n    /*  Store the updated state variables back into the pState array */\n    *pState++ = Xn1;\n    *pState++ = Xn2;\n    *pState++ = Yn1;\n    *pState++ = Yn2;\n\n  } while(--stage);\n\n#endif /*  #ifndef ARM_MATH_CM0_FAMILY */\n}\n\n/**    \n  * @} end of BiquadCascadeDF1 group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_biquad_cascade_df2T_f32.c    \n*    \n* Description:  Processing function for the floating-point transposed    \n*               direct form II Biquad cascade filter.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**       \n* @ingroup groupFilters       \n*/\n\n/**       \n* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       \n*       \n* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       \n* The filters are implemented as a cascade of second order Biquad sections.       \n* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      \n* Only floating-point data is supported.       \n*       \n* This function operate on blocks of input and output data and each call to the function       \n* processes blockSize samples through the filter.       \n* pSrc points to the array of input data and       \n* pDst points to the array of output data.       \n* Both arrays contain blockSize values.       \n*       \n* \\par Algorithm       \n* Each Biquad stage implements a second order filter using the difference equation:       \n* 
       \n*    y[n] = b0 * x[n] + d1       \n*    d1 = b1 * x[n] + a1 * y[n] + d2       \n*    d2 = b2 * x[n] + a2 * y[n]       \n* 
       \n* where d1 and d2 represent the two state values.       \n*       \n* \\par       \n* A Biquad filter using a transposed Direct Form II structure is shown below.       \n* \\image html BiquadDF2Transposed.gif \"Single transposed Direct Form II Biquad\"       \n* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       \n* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       \n* Pay careful attention to the sign of the feedback coefficients.       \n* Some design tools flip the sign of the feedback coefficients:       \n* 
       \n*    y[n] = b0 * x[n] + d1;       \n*    d1 = b1 * x[n] - a1 * y[n] + d2;       \n*    d2 = b2 * x[n] - a2 * y[n];       \n* 
       \n* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       \n*       \n* \\par       \n* Higher order filters are realized as a cascade of second order sections.       \n* numStages refers to the number of second order stages used.       \n* For example, an 8th order filter would be realized with numStages=4 second order stages.       \n* A 9th order filter would be realized with numStages=5 second order stages with the       \n* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       \n*       \n* \\par       \n* pState points to the state variable array.       \n* Each Biquad stage has 2 state variables d1 and d2.       \n* The state variables are arranged in the pState array as:       \n* 
       \n*     {d11, d12, d21, d22, ...}       \n* 
       \n* where d1x refers to the state variables for the first Biquad and       \n* d2x refers to the state variables for the second Biquad.       \n* The state array has a total length of 2*numStages values.       \n* The state variables are updated after each block of data is processed; the coefficients are untouched.       \n*       \n* \\par       \n* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    \n* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    \n* That is why the Direct Form I structure supports Q15 and Q31 data types.    \n* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    \n* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    \n* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    \n*       \n* \\par Instance Structure       \n* The coefficients and state variables for a filter are stored together in an instance data structure.       \n* A separate instance structure must be defined for each filter.       \n* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       \n*       \n* \\par Init Functions       \n* There is also an associated initialization function.      \n* The initialization function performs following operations:       \n* - Sets the values of the internal structure fields.       \n* - Zeros out the values in the state buffer.       \n* To do this manually without calling the init function, assign the follow subfields of the instance structure:\n* numStages, pCoeffs, pState. Also set all of the values in pState to zero. \n*       \n* \\par       \n* Use of the initialization function is optional.       \n* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       \n* To place an instance structure into a const data section, the instance structure must be manually initialized.       \n* Set the values in the state buffer to zeros before static initialization.       \n* For example, to statically initialize the instance structure use       \n* 
       \n*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       \n* 
       \n* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       \n* pCoeffs is the address of the coefficient buffer;        \n*       \n*/\n\n/**       \n* @addtogroup BiquadCascadeDF2T       \n* @{       \n*/\n\n/**      \n* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      \n* @param[in]  *S        points to an instance of the filter data structure.      \n* @param[in]  *pSrc     points to the block of input data.      \n* @param[out] *pDst     points to the block of output data      \n* @param[in]  blockSize number of samples to process.      \n* @return none.      \n*/\n\n\nLOW_OPTIMIZATION_ENTER\nvoid arm_biquad_cascade_df2T_f32(\nconst arm_biquad_cascade_df2T_instance_f32 * S,\nfloat32_t * pSrc,\nfloat32_t * pDst,\nuint32_t blockSize)\n{\n\n   float32_t *pIn = pSrc;                         /*  source pointer            */\n   float32_t *pOut = pDst;                        /*  destination pointer       */\n   float32_t *pState = S->pState;                 /*  State pointer             */\n   float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */\n   float32_t acc1;                                /*  accumulator               */\n   float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */\n   float32_t Xn1;                                 /*  temporary input           */\n   float32_t d1, d2;                              /*  state variables           */\n   uint32_t sample, stage = S->numStages;         /*  loop counters             */\n\n#ifndef ARM_MATH_CM0_FAMILY_FAMILY\n\n   float32_t Xn2, Xn3, Xn4;                  \t  /*  Input State variables     */\n   float32_t acc2, acc3, acc4;              \t\t  /*  accumulator               */\n\n\n   float32_t p0, p1, p2, p3, p4, A1;\n\n   /* Run the below code for Cortex-M4 and Cortex-M3 */\n   do\n   {\n      /* Reading the coefficients */     \n      b0 = *pCoeffs++;\n      b1 = *pCoeffs++;\n      b2 = *pCoeffs++;\n      a1 = *pCoeffs++;\n      a2 = *pCoeffs++;\n      \n\n      /*Reading the state values */\n      d1 = pState[0];\n      d2 = pState[1];\n\n      /* Apply loop unrolling and compute 4 output values simultaneously. */\n      sample = blockSize >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       \n   ** a second loop below computes the remaining 1 to 3 samples. */\n      while(sample > 0u) {\n\n         /* y[n] = b0 * x[n] + d1 */\n         /* d1 = b1 * x[n] + a1 * y[n] + d2 */\n         /* d2 = b2 * x[n] + a2 * y[n] */\n\n         /* Read the four inputs */\n         Xn1 = pIn[0];\n         Xn2 = pIn[1];\n         Xn3 = pIn[2];\n         Xn4 = pIn[3];\n         pIn += 4;     \n\n         p0 = b0 * Xn1; \n         p1 = b1 * Xn1;\n         acc1 = p0 + d1;\n         p0 = b0 * Xn2; \n         p3 = a1 * acc1;\n         p2 = b2 * Xn1;\n         A1 = p1 + p3;\n         p4 = a2 * acc1;\n         d1 = A1 + d2;\n         d2 = p2 + p4;\n\n         p1 = b1 * Xn2;\n         acc2 = p0 + d1;\n         p0 = b0 * Xn3;\t \n         p3 = a1 * acc2; \n         p2 = b2 * Xn2;                                 \n         A1 = p1 + p3;\n         p4 = a2 * acc2;\n         d1 = A1 + d2;\n         d2 = p2 + p4;\n\n         p1 = b1 * Xn3;\n         acc3 = p0 + d1;\n         p0 = b0 * Xn4;\t\n         p3 = a1 * acc3;\n         p2 = b2 * Xn3;\n         A1 = p1 + p3;\n         p4 = a2 * acc3;\n         d1 = A1 + d2;\n         d2 = p2 + p4;\n\n         acc4 = p0 + d1;\n         p1 = b1 * Xn4;\n         p3 = a1 * acc4;\n         p2 = b2 * Xn4;\n         A1 = p1 + p3;\n         p4 = a2 * acc4;\n         d1 = A1 + d2;\n         d2 = p2 + p4;\n\n         pOut[0] = acc1;\t\n         pOut[1] = acc2;\t\n         pOut[2] = acc3;\t\n         pOut[3] = acc4;\n\t\t\t\t pOut += 4;\n\t\t\t\t \n         sample--;\t       \n      }\n\n      sample = blockSize & 0x3u;\n      while(sample > 0u) {\n         Xn1 = *pIn++;\n\n         p0 = b0 * Xn1; \n         p1 = b1 * Xn1;\n         acc1 = p0 + d1;\n         p3 = a1 * acc1;\n         p2 = b2 * Xn1;\n         A1 = p1 + p3;\n         p4 = a2 * acc1;\n         d1 = A1 + d2;\n         d2 = p2 + p4;\n\t\n         *pOut++ = acc1;\n         \n         sample--;\t       \n      }\n\n      /* Store the updated state variables back into the state array */\n      *pState++ = d1;\n      *pState++ = d2;\n\n      /* The current stage input is given as the output to the next stage */\n      pIn = pDst;\n\n      /*Reset the output working pointer */\n      pOut = pDst;\n\n      /* decrement the loop counter */\n      stage--;\n\n   } while(stage > 0u);\n\n#else\n\n   /* Run the below code for Cortex-M0 */\n\n   do\n   {\n      /* Reading the coefficients */\n      b0 = *pCoeffs++;\n      b1 = *pCoeffs++;\n      b2 = *pCoeffs++;\n      a1 = *pCoeffs++;\n      a2 = *pCoeffs++;\n\n      /*Reading the state values */\n      d1 = pState[0];\n      d2 = pState[1];\n\n\n      sample = blockSize;\n\n      while(sample > 0u)\n      {\n         /* Read the input */\n         Xn1 = *pIn++;\n\n         /* y[n] = b0 * x[n] + d1 */\n         acc1 = (b0 * Xn1) + d1;\n\n         /* Store the result in the accumulator in the destination buffer. */\n         *pOut++ = acc1;\n\n         /* Every time after the output is computed state should be updated. */\n         /* d1 = b1 * x[n] + a1 * y[n] + d2 */\n         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;\n\n         /* d2 = b2 * x[n] + a2 * y[n] */\n         d2 = (b2 * Xn1) + (a2 * acc1);\n\n         /* decrement the loop counter */\n         sample--;\n      }\n\n      /* Store the updated state variables back into the state array */\n      *pState++ = d1;\n      *pState++ = d2;\n\n      /* The current stage input is given as the output to the next stage */\n      pIn = pDst;\n\n      /*Reset the output working pointer */\n      pOut = pDst;\n\n      /* decrement the loop counter */\n      stage--;\n\n   } while(stage > 0u);\n\n#endif /*  #ifndef ARM_MATH_CM0_FAMILY         */\n\n}\nLOW_OPTIMIZATION_EXIT\n\n/**       \n   * @} end of BiquadCascadeDF2T group       \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_biquad_cascade_df2T_init_f32.c    \n*    \n* Description:  Initialization function for the floating-point transposed   \n*               direct form II Biquad cascade filter.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup BiquadCascadeDF2T    \n * @{    \n */\n\n/**   \n * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   \n * @param[in,out] *S           points to an instance of the filter data structure.   \n * @param[in]     numStages    number of 2nd order stages in the filter.   \n * @param[in]     *pCoeffs     points to the filter coefficients.   \n * @param[in]     *pState      points to the state buffer.   \n * @return        none   \n *    \n * Coefficient and State Ordering:    \n * \\par    \n * The coefficients are stored in the array pCoeffs in the following order:    \n * 
    \n *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n * 
    \n *    \n * \\par    \n * where b1x and a1x are the coefficients for the first stage,    \n * b2x and a2x are the coefficients for the second stage,    \n * and so on.  The pCoeffs array contains a total of 5*numStages values.    \n *    \n * \\par    \n * The pState is a pointer to state array.    \n * Each Biquad stage has 2 state variables d1, and d2.    \n * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    \n * The state array has a total length of 2*numStages values.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n */\n\nvoid arm_biquad_cascade_df2T_init_f32(\n  arm_biquad_cascade_df2T_instance_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState)\n{\n  /* Assign filter stages */\n  S->numStages = numStages;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always 2 * numStages */\n  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n}\n\n/**    \n * @} end of BiquadCascadeDF2T group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_f32.c    \n*    \n* Description:\tConvolution of floating-point sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup Conv Convolution    \n *    \n * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.    \n * Convolution is similar to correlation and is frequently used in filtering and data analysis.    \n * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.    \n * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.    \n *    \n * \\par Algorithm    \n * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    \n * Then the convolution    \n *    \n * 
    \n *                   c[n] = a[n] * b[n]    \n * 
    \n *    \n * \\par    \n * is defined as    \n * \\image html ConvolutionEquation.gif    \n * \\par    \n * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.    \n * pSrcA points to the first input vector of length srcALen and    \n * pSrcB points to the second input vector of length srcBLen.    \n * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.    \n *    \n * \\par    \n * Conceptually, when two signals a[n] and b[n] are convolved,    \n * the signal b[n] slides over a[n].    \n * For each offset \\c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.    \n *    \n * \\par    \n * Note that convolution is a commutative operation:    \n *    \n * 
    \n *                   a[n] * b[n] = b[n] * a[n].    \n * 
    \n *    \n * \\par    \n * This means that switching the A and B arguments to the convolution functions has no effect.    \n *    \n * Fixed-Point Behavior    \n *    \n * \\par    \n * Convolution requires summing up a large number of intermediate products.    \n * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    \n * Refer to the function specific documentation below for further details of the particular algorithm used.    \n *\n *\n * Fast Versions\n *\n * \\par \n * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires\n * the input signals should be scaled down to avoid intermediate overflows.   \n *\n *\n * Opt Versions\n *\n * \\par \n * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.\n * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @brief Convolution of floating-point sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @return none.    \n */\n\nvoid arm_conv_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t *pIn1;                               /* inputA pointer */\n  float32_t *pIn2;                               /* inputB pointer */\n  float32_t *pOut = pDst;                        /* output pointer */\n  float32_t *px;                                 /* Intermediate inputA pointer */\n  float32_t *py;                                 /* Intermediate inputB pointer */\n  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */\n  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */\n  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */\n  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally    \n   * divided into three stages according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first stage of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n   * In the third stage of the algorithm, the multiplications decrease by one    \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.    \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]    \n   * sum = x[0] * y[1] + x[1] * y[0]    \n   * ....    \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0.0f;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 1] */\n      sum += *px++ * *py--;\n\n      /* x[1] * y[srcBLen - 2] */\n      sum += *px++ * *py--;\n\n      /* x[2] * y[srcBLen - 3] */\n      sum += *px++ * *py--;\n\n      /* x[3] * y[srcBLen - 4] */\n      sum += *px++ * *py--;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += *px++ * *py--;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0.0f;\n      acc1 = 0.0f;\n      acc2 = 0.0f;\n      acc3 = 0.0f;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n      x2 = *(px++);\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[srcBLen - 1] sample */\n        c0 = *(py--);\n\n        /* Read x[3] sample */\n        x3 = *(px);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[0] * y[srcBLen - 1] */\n        acc0 += x0 * c0;\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] */\n        acc1 += x1 * c0;\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] */\n        acc2 += x2 * c0;\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] */\n        acc3 += x3 * c0;\n\n        /* Read y[srcBLen - 2] sample */\n        c0 = *(py--);\n\n        /* Read x[4] sample */\n        x0 = *(px + 1u);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[1] * y[srcBLen - 2] */\n        acc0 += x1 * c0;\n        /* acc1 +=  x[2] * y[srcBLen - 2] */\n        acc1 += x2 * c0;\n        /* acc2 +=  x[3] * y[srcBLen - 2] */\n        acc2 += x3 * c0;\n        /* acc3 +=  x[4] * y[srcBLen - 2] */\n        acc3 += x0 * c0;\n\n        /* Read y[srcBLen - 3] sample */\n        c0 = *(py--);\n\n        /* Read x[5] sample */\n        x1 = *(px + 2u);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[srcBLen - 3] */\n        acc0 += x2 * c0;\n        /* acc1 +=  x[3] * y[srcBLen - 2] */\n        acc1 += x3 * c0;\n        /* acc2 +=  x[4] * y[srcBLen - 2] */\n        acc2 += x0 * c0;\n        /* acc3 +=  x[5] * y[srcBLen - 2] */\n        acc3 += x1 * c0;\n\n        /* Read y[srcBLen - 4] sample */\n        c0 = *(py--);\n\n        /* Read x[6] sample */\n        x2 = *(px + 3u);\n        px += 4u;\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[3] * y[srcBLen - 4] */\n        acc0 += x3 * c0;\n        /* acc1 +=  x[4] * y[srcBLen - 4] */\n        acc1 += x0 * c0;\n        /* acc2 +=  x[5] * y[srcBLen - 4] */\n        acc2 += x1 * c0;\n        /* acc3 +=  x[6] * y[srcBLen - 4] */\n        acc3 += x2 * c0;\n\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[srcBLen - 5] sample */\n        c0 = *(py--);\n\n        /* Read x[7] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[srcBLen - 5] */\n        acc0 += x0 * c0;\n        /* acc1 +=  x[5] * y[srcBLen - 5] */\n        acc1 += x1 * c0;\n        /* acc2 +=  x[6] * y[srcBLen - 5] */\n        acc2 += x2 * c0;\n        /* acc3 +=  x[7] * y[srcBLen - 5] */\n        acc3 += x3 * c0;\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = acc0;\n      *pOut++ = acc1;\n      *pOut++ = acc2;\n      *pOut++ = acc3;\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += *px++ * *py--;\n        sum += *px++ * *py--;\n        sum += *px++ * *py--;\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n   * sum +=  x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0.0f;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n      sum += *px++ * *py--;\n\n      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n      sum += *px++ * *py--;\n\n      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n      sum += *px++ * *py--;\n\n      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n      sum += *px++ * *py--;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n      sum += *px++ * *py--;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t *pIn1 = pSrcA;                       /* inputA pointer */\n  float32_t *pIn2 = pSrcB;                       /* inputB pointer */\n  float32_t sum;                                 /* Accumulator */\n  uint32_t i, j;                                 /* loop counters */\n\n  /* Loop to calculate convolution for output length number of times */\n  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)\n  {\n    /* Initialize sum with zero to carry out MAC operations */\n    sum = 0.0f;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0u; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if((((i - j) < srcBLen) && (j < srcALen)))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += pIn1[j] * pIn2[i - j];\n      }\n    }\n    /* Store the output in the destination buffer */\n    pDst[i] = sum;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */\n\n}\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_fast_opt_q15.c    \n*    \n* Description:\tFast Q15 Convolution.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   \n * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   \n * @return none.    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    \n *     \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This fast version uses a 32-bit accumulator with 2.30 format.    \n * The accumulator maintains full precision of the intermediate multiplication results    \n * but provides only a single guard bit. There is no saturation on intermediate additions.    \n * Thus, if the accumulator overflows it wraps around and distorts the result.    \n * The input signals should be scaled down to avoid intermediate overflows.    \n * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    \n * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    \n * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    \n *    \n * \\par    \n * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    \n */\n\nvoid arm_conv_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */\n  q31_t y1, y2;                                  /* State variables */\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  uint32_t tapCnt;                               /* loop count */\n#ifdef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t a, b;\n\n#endif\t/*\t#ifdef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* Pointer to take end of scratch2 buffer */\n  pScr2 = pScratch2 + srcBLen - 1;\n\n  /* points to smaller length sequence */\n  px = pIn2;\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcBLen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n\n  /* Copy smaller length input sequence in reverse order into second scratch buffer */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcBLen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr2-- = *px++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* Initialze temporary scratch pointer */\n  pScr1 = pScratch1;\n\n  /* Assuming scratch1 buffer is aligned by 32-bit */\n  /* Fill (srcBLen - 1u) zeros in scratch1 buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr1 += (srcBLen - 1u);\n\n  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Copy (srcALen) samples in scratch buffer */\n  arm_copy_q15(pIn1, pScr1, srcALen);\n\n  /* Update pointers */\n  pScr1 += srcALen;\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcALen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr1 += (srcBLen - 1u);\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = (srcBLen - 1u) % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* Temporary pointer for scratch2 */\n  py = pScratch2;\n\n\n  /* Initialization of pIn2 pointer */\n  pIn2 = py;\n\n  /* First part of the processing with loop unrolling process 4 data points at a time.       \n   ** a second loop below process for the remaining 1 to 3 samples. */\n\n  /* Actual convolution process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read two samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr1)++;\n\n    /* Read next two samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr1)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pIn2);\n      y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n      /* multiply and accumlate */\n      acc0 = __SMLAD(x1, y1, acc0);\n      acc2 = __SMLAD(x2, y1, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      /* multiply and accumlate */\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      /* Read next two samples from scratch1 buffer */\n      x1 = _SIMD32_OFFSET(pScr1);\n\n      /* multiply and accumlate */\n      acc0 = __SMLAD(x2, y2, acc0);\n      acc2 = __SMLAD(x1, y2, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n      acc1 = __SMLADX(x3, y2, acc1);\n\n      x2 = _SIMD32_OFFSET(pScr1 + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y2, acc3);\n\n#else\t \n\n      /* Read four samples from smaller buffer */\n\t  a = *pIn2;\n\t  b = *(pIn2 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      y1 = __PKHBT(a, b, 16);\n#else\n      y1 = __PKHBT(b, a, 16);\n#endif\n\t  \n\t  a = *(pIn2 + 2);\n\t  b = *(pIn2 + 3);\n#ifndef ARM_MATH_BIG_ENDIAN\n      y2 = __PKHBT(a, b, 16);\n#else\n      y2 = __PKHBT(b, a, 16);\n#endif\t\t\t\t\n\n      acc0 = __SMLAD(x1, y1, acc0);\n\n      acc2 = __SMLAD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLADX(x3, y1, acc1);\n\n\t  a = *pScr1;\n\t  b = *(pScr1 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(a, b, 16);\n#else\n      x1 = __PKHBT(b, a, 16);\n#endif\n\n      acc0 = __SMLAD(x2, y2, acc0);\n\n      acc2 = __SMLAD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      acc1 = __SMLADX(x3, y2, acc1);\n\n\t  a = *(pScr1 + 2);\n\t  b = *(pScr1 + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x2 = __PKHBT(a, b, 16);\n#else\n      x2 = __PKHBT(b, a, 16);\n#endif\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y2, acc3);\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      /* update scratch pointers */\n      pIn2 += 4u;\n      pScr1 += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr1 -= 4u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pIn2);\n      acc1 += (*pScr1++ * *pIn2);\n      acc2 += (*pScr1++ * *pIn2);\n      acc3 += (*pScr1++ * *pIn2++);\n\n      pScr1 -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n\n    /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n\n#else\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch1 += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate convolution for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n\n      acc0 += (*pScr1++ * *pIn2++);\n      acc0 += (*pScr1++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the output in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch1 += 1u;\n\n  }\n\n}\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_fast_q15.c   \n*   \n* Description:\tFast Q15 Convolution.   \n*   \n* Target Processor: Cortex-M4/Cortex-M3\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Conv   \n * @{   \n */\n\n/**   \n * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   \n * @return none.   \n *   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * This fast version uses a 32-bit accumulator with 2.30 format.   \n * The accumulator maintains full precision of the intermediate multiplication results   \n * but provides only a single guard bit. There is no saturation on intermediate additions.   \n * Thus, if the accumulator overflows it wraps around and distorts the result.   \n * The input signals should be scaled down to avoid intermediate overflows.   \n * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   \n * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   \n * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   \n *   \n * \\par   \n * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   \n */\n\nvoid arm_conv_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst)\n{\n#ifndef UNALIGNED_SUPPORT_DISABLE\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *pOut = pDst;                            /* output pointer */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */\n  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally   \n   * divided into three stages according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first stage of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n   * In the third stage of the algorithm, the multiplications decrease by one   \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.   \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]   \n   * sum = x[0] * y[1] + x[1] * y[0]   \n   * ....   \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations less than 4 */\n  /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  while((count < 4u) && (blockSize1 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Loop over number of MAC operations between   \n     * inputA samples and inputB samples */\n    k = count;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLAD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* The second part of the stage starts here */\n  /* The internal loop, over count, is unrolled by 4 */\n  /* To, read the last two inputB samples using SIMD:   \n   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n  py = py - 1;\n\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */\n      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */\n      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* For the next MAC operations, the pointer py is used without SIMD   \n     * So, py is incremented by 1 */\n    py = py + 1u;\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLAD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + (count - 1u);\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is the index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n\n  /* --------------------   \n   * Stage2 process   \n   * -------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      py = py - 1u;\n\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n\n      /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n      /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px+1);\n\t  px+= 2u;\n\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the last two inputB samples using SIMD:   \n         * y[srcBLen - 1] and y[srcBLen - 2] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n        acc0 = __SMLADX(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n        acc1 = __SMLADX(x1, c0, acc1);\n\n        /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n        /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px+1);\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n        acc2 = __SMLADX(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n        acc3 = __SMLADX(x3, c0, acc3);\n\n        /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n        acc0 = __SMLADX(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n        acc1 = __SMLADX(x3, c0, acc1);\n\n        /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px+2);\n\n        /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px+3);\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n        acc2 = __SMLADX(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n        acc3 = __SMLADX(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLADX(x1, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n\n        /* Read y[srcBLen - 7] */\n\t\tc0 = *(py-1);\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n        x3 =  _SIMD32_OFFSET(px+2);\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x1, c0, acc0);\n        acc1 = __SMLAD(x2, c0, acc1);\n        acc2 = __SMLADX(x2, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      /* Store the results in the accumulators in the destination buffer. */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);\n      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);\n\n#else\n\n      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);\n      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n   * sum +=  x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  pIn2 = pSrc2 - 1u;\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations greater than 4 */\n  /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  j = blockSize3 >> 2u;\n\n  while((j > 0u) && (blockSize3 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   \n       * with y[srcBLen - 1], y[srcBLen - 2] respectively */\n      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   \n       * with y[srcBLen - 3], y[srcBLen - 4] respectively */\n      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* For the next MAC operations, the pointer py is used without SIMD   \n     * So, py is incremented by 1 */\n    py = py + 1u;\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */\n      sum = __SMLAD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n\n    j--;\n  }\n\n  /* The second part of the stage starts here */\n  /* SIMD is not used for the next MAC operations,   \n   * so pointer py is updated to read only one sample at a time */\n  py = py + 1u;\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n      sum = __SMLAD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *pOut = pDst;                            /* output pointer */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */\n  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */\n  q15_t a, b;\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally   \n   * divided into three stages according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first stage of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n   * In the third stage of the algorithm, the multiplications decrease by one   \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.   \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]   \n   * sum = x[0] * y[1] + x[1] * y[0]   \n   * ....   \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations less than 4 */\n  /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  while((count < 4u) && (blockSize1 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Loop over number of MAC operations between   \n     * inputA samples and inputB samples */\n    k = count;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* The second part of the stage starts here */\n  /* The internal loop, over count, is unrolled by 4 */\n  /* To, read the last two inputB samples using SIMD:   \n   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n  py = py - 1;\n\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n\tpy++;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + (count - 1u);\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is the index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n\n  /* --------------------   \n   * Stage2 process   \n   * -------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      py = py - 1u;\n\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\t  \n\n      /* read x[0], x[1] samples */\n\t  a = *px++;\n\t  b = *px++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x0 = __PKHBT(a, b, 16);\n\t  a = *px;\n\t  x1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x0 = __PKHBT(b, a, 16);\n\t  a = *px;\n\t  x1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the last two inputB samples using SIMD:   \n         * y[srcBLen - 1] and y[srcBLen - 2] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\t\tpy -= 2;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n        acc0 = __SMLADX(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n        acc1 = __SMLADX(x1, c0, acc1);\n\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x2 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x3 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x2 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x3 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n        acc2 = __SMLADX(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n        acc3 = __SMLADX(x3, c0, acc3);\n\n        /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\t\tpy -= 2;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n        acc0 = __SMLADX(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n        acc1 = __SMLADX(x3, c0, acc1);\n\n        /* Read x[4], x[5], x[6] */\n\t  a = *(px + 2);\n\t  b = *(px + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x0 = __PKHBT(a, b, 16);\n\t  a = *(px + 4);\n\t  x1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x0 = __PKHBT(b, a, 16);\n\t  a = *(px + 4);\n\t  x1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n        acc2 = __SMLADX(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n        acc3 = __SMLADX(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n\t\ta = *px;\n\t\tb = *(px+1);\n\t\tpx++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tx3 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tx3 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLADX(x1, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Read x[7], x[8], x[9] */\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x3 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x3 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Read x[7], x[8], x[9] */\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x3 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x3 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n\n        /* Read y[srcBLen - 7] */\n\t\tc0 = *(py-1);\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n\t\ta = *(px+2);\n\t\tb = *(px+3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tx3 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tx3 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x1, c0, acc0);\n        acc1 = __SMLAD(x2, c0, acc1);\n        acc2 = __SMLADX(x2, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      /* Store the results in the accumulators in the destination buffer. */\n\t  *pOut++ = (q15_t)(acc0 >> 15);\n\t  *pOut++ = (q15_t)(acc1 >> 15);\n\t  *pOut++ = (q15_t)(acc2 >> 15);\n\t  *pOut++ = (q15_t)(acc3 >> 15);\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n   * sum +=  x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  pIn2 = pSrc2 - 1u;\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations greater than 4 */\n  /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  j = blockSize3 >> 2u;\n\n  while((j > 0u) && (blockSize3 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n\tpy++;\n\n    while(k > 0u)\n    {\t\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */\n        sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n\n    j--;\n  }\n\n  /* The second part of the stage starts here */\n  /* SIMD is not used for the next MAC operations,   \n   * so pointer py is updated to read only one sample at a time */\n  py = py + 1u;\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (sum >> 15);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n}\n\n/**   \n * @} end of Conv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_fast_q31.c    \n*    \n* Description:\tQ31 Convolution (fast version).    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    \n * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    \n * These intermediate results are accumulated in a 32-bit register in 2.30 format.    \n * Finally, the accumulator is saturated and converted to a 1.31 result.    \n *    \n * \\par    \n * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signals must be scaled down.    \n * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    \n * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    \n *    \n * \\par    \n * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    \n */\n\nvoid arm_conv_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst)\n{\n  q31_t *pIn1;                                   /* inputA pointer */\n  q31_t *pIn2;                                   /* inputB pointer */\n  q31_t *pOut = pDst;                            /* output pointer */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */\n  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally    \n   * divided into three stages according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first stage of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n   * In the third stage of the algorithm, the multiplications decrease by one    \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.    \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * Initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]    \n   * sum = x[0] * y[1] + x[1] * y[0]    \n   * ....    \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 1] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* x[1] * y[srcBLen - 2] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* x[2] * y[srcBLen - 3] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* x[3] * y[srcBLen - 4] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = sum << 1;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n      x2 = *(px++);\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[srcBLen - 1] sample */\n        c0 = *(py--);\n\n        /* Read x[3] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[0] * y[srcBLen - 1] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n        /* Read y[srcBLen - 2] sample */\n        c0 = *(py--);\n\n        /* Read x[4] sample */\n        x0 = *(px++);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[1] * y[srcBLen - 2] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc1 +=  x[2] * y[srcBLen - 2] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc2 +=  x[3] * y[srcBLen - 2] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc3 +=  x[4] * y[srcBLen - 2] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n        /* Read y[srcBLen - 3] sample */\n        c0 = *(py--);\n\n        /* Read x[5] sample */\n        x1 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[srcBLen - 3] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc1 +=  x[3] * y[srcBLen - 3] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc2 +=  x[4] * y[srcBLen - 3] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc3 +=  x[5] * y[srcBLen - 3] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n        /* Read y[srcBLen - 4] sample */\n        c0 = *(py--);\n\n        /* Read x[6] sample */\n        x2 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[3] * y[srcBLen - 4] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc1 +=  x[4] * y[srcBLen - 4] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc2 +=  x[5] * y[srcBLen - 4] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc3 +=  x[6] * y[srcBLen - 4] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);\n\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[srcBLen - 5] sample */\n        c0 = *(py--);\n\n        /* Read x[7] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[srcBLen - 5] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc1 +=  x[5] * y[srcBLen - 5] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc2 +=  x[6] * y[srcBLen - 5] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc3 +=  x[7] * y[srcBLen - 5] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the results in the accumulators in the destination buffer. */\n      *pOut++ = (q31_t) (acc0 << 1);\n      *pOut++ = (q31_t) (acc1 << 1);\n      *pOut++ = (q31_t) (acc2 << 1);\n      *pOut++ = (q31_t) (acc3 << 1);\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum << 1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum << 1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n   * sum +=  x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py--))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = sum << 1;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n}\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_opt_q15.c    \n*    \n* Description:\tConvolution of Q15 sequences.      \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @brief Convolution of Q15 sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    \n * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).    \n * @return none.    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    \n *    \n *       \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * This approach provides 33 guard bits and there is no risk of overflow.    \n * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    \n *  \n *   \n * \\par    \n * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.     \n * \n *  \n */\n\nvoid arm_conv_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */\n  q31_t y1, y2;                                  /* State variables */\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  uint32_t tapCnt;                               /* loop count */\n#ifdef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t a, b;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* pointer to take end of scratch2 buffer */\n  pScr2 = pScratch2 + srcBLen - 1;\n\n  /* points to smaller length sequence */\n  px = pIn2;\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcBLen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  /* Copy smaller length input sequence in reverse order into second scratch buffer */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n    *pScr2-- = *px++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcBLen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr2-- = *px++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* Initialze temporary scratch pointer */\n  pScr1 = pScratch1;\n\n  /* Assuming scratch1 buffer is aligned by 32-bit */\n  /* Fill (srcBLen - 1u) zeros in scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr1 += (srcBLen - 1u);\n\n  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Copy (srcALen) samples in scratch buffer */\n  arm_copy_q15(pIn1, pScr1, srcALen);\n\n  /* Update pointers */\n  pScr1 += srcALen;\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n    *pScr1++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcALen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\n\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr1 += (srcBLen - 1u);\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = (srcBLen - 1u) % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\n\n  /* Temporary pointer for scratch2 */\n  py = pScratch2;\n\n\n  /* Initialization of pIn2 pointer */\n  pIn2 = py;\n\n  /* First part of the processing with loop unrolling process 4 data points at a time.       \n   ** a second loop below process for the remaining 1 to 3 samples. */\n\n  /* Actual convolution process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read two samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr1)++;\n\n    /* Read next two samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr1)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pIn2);\n      y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n      /* multiply and accumlate */\n      acc0 = __SMLALD(x1, y1, acc0);\n      acc2 = __SMLALD(x2, y1, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      /* multiply and accumlate */\n      acc1 = __SMLALDX(x3, y1, acc1);\n\n      /* Read next two samples from scratch1 buffer */\n      x1 = _SIMD32_OFFSET(pScr1);\n\n      /* multiply and accumlate */\n      acc0 = __SMLALD(x2, y2, acc0);\n      acc2 = __SMLALD(x1, y2, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y1, acc3);\n      acc1 = __SMLALDX(x3, y2, acc1);\n\n      x2 = _SIMD32_OFFSET(pScr1 + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y2, acc3);\n\n#else\t \n\n      /* Read four samples from smaller buffer */\n\t  a = *pIn2;\n\t  b = *(pIn2 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      y1 = __PKHBT(a, b, 16);\n#else\n      y1 = __PKHBT(b, a, 16);\n#endif\n\t  \n\t  a = *(pIn2 + 2);\n\t  b = *(pIn2 + 3);\n#ifndef ARM_MATH_BIG_ENDIAN\n      y2 = __PKHBT(a, b, 16);\n#else\n      y2 = __PKHBT(b, a, 16);\n#endif\t\t\t\t\n\n      acc0 = __SMLALD(x1, y1, acc0);\n\n      acc2 = __SMLALD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLALDX(x3, y1, acc1);\n\n\t  a = *pScr1;\n\t  b = *(pScr1 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(a, b, 16);\n#else\n      x1 = __PKHBT(b, a, 16);\n#endif\n\n      acc0 = __SMLALD(x2, y2, acc0);\n\n      acc2 = __SMLALD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y1, acc3);\n\n      acc1 = __SMLALDX(x3, y2, acc1);\n\n\t  a = *(pScr1 + 2);\n\t  b = *(pScr1 + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x2 = __PKHBT(a, b, 16);\n#else\n      x2 = __PKHBT(b, a, 16);\n#endif\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y2, acc3);\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      pIn2 += 4u;\n      pScr1 += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr1 -= 4u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pIn2);\n      acc1 += (*pScr1++ * *pIn2);\n      acc2 += (*pScr1++ * *pIn2);\n      acc3 += (*pScr1++ * *pIn2++);\n\n      pScr1 -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n\n    /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n\n    *__SIMD32(pOut)++ =\n      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch1 += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate convolution for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Read next two samples from scratch1 buffer */\n      acc0 += (*pScr1++ * *pIn2++);\n      acc0 += (*pScr1++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the output in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch1 += 1u;\n\n  }\n\n}\n\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_opt_q7.c    \n*    \n* Description:\tConvolution of Q7 sequences.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @brief Convolution of Q7 sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   \n * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   \n * @return none.    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     \n *       \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.    \n * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    \n * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    \n * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.    \n *\n */\n\nvoid arm_conv_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */\n  q15_t x4;                                      /* Temporary input variable */\n  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */\n  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */\n  q7_t *px;                                      /* Temporary input1 pointer */\n  q15_t *py;                                     /* Temporary input2 pointer */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q31_t x1, x2, x3, y1;                          /* Temporary input variables */\n  q7_t *pOut = pDst;                             /* output pointer */\n  q7_t out0, out1, out2, out3;                   /* temporary variables */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* pointer to take end of scratch2 buffer */\n  pScr2 = pScratch2;\n\n  /* points to smaller length sequence */\n  px = pIn2 + srcBLen - 1;\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcBLen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    x4 = (q15_t) * px--;\n    *pScr2++ = x4;\n    x4 = (q15_t) * px--;\n    *pScr2++ = x4;\n    x4 = (q15_t) * px--;\n    *pScr2++ = x4;\n    x4 = (q15_t) * px--;\n    *pScr2++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcBLen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    x4 = (q15_t) * px--;\n    *pScr2++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* Initialze temporary scratch pointer */\n  pScr1 = pScratch1;\n\n  /* Fill (srcBLen - 1u) zeros in scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr1 += (srcBLen - 1u);\n\n  /* Copy (srcALen) samples in scratch buffer */\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcALen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr1 += (srcBLen - 1u);\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = (srcBLen - 1u) % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\n\n  /* Temporary pointer for scratch2 */\n  py = pScratch2;\n\n  /* Initialization of pIn2 pointer */\n  pIn2 = (q7_t *) py;\n\n  pScr2 = py;\n\n  /* Actual convolution process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read two samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr1)++;\n\n    /* Read next two samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr1)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pScr2);\n\n      /* multiply and accumlate */\n      acc0 = __SMLAD(x1, y1, acc0);\n      acc2 = __SMLAD(x2, y1, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      /* multiply and accumlate */\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      /* Read next two samples from scratch1 buffer */\n      x1 = *__SIMD32(pScr1)++;\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pScr2 + 2u);\n\n      acc0 = __SMLAD(x2, y1, acc0);\n\n      acc2 = __SMLAD(x1, y1, acc2);\n\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      x2 = *__SIMD32(pScr1)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      pScr2 += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr1 -= 4u;\n\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pScr2);\n      acc1 += (*pScr1++ * *pScr2);\n      acc2 += (*pScr1++ * *pScr2);\n      acc3 += (*pScr1++ * *pScr2++);\n\n      pScr1 -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n    out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));\n    out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));\n    out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));\n    out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));\n\n    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);\n\n    /* Initialization of inputB pointer */\n    pScr2 = py;\n\n    pScratch1 += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate convolution for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n      acc0 += (*pScr1++ * *pScr2++);\n      acc0 += (*pScr1++ * *pScr2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pScr2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));\n\n    /* Initialization of inputB pointer */\n    pScr2 = py;\n\n    pScratch1 += 1u;\n\n  }\n\n}\n\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_f32.c    \n*    \n* Description:\tPartial convolution of floating-point sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup PartialConv Partial Convolution    \n *    \n * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.    \n * Each function has two additional arguments.    \n * firstIndex specifies the starting index of the subset of output samples.    \n * numPoints is the number of output samples to compute.    \n * The function computes the output in the range    \n * [firstIndex, ..., firstIndex+numPoints-1].    \n * The output array pDst contains numPoints values.    \n *    \n * The allowable range of output indices is [0 srcALen+srcBLen-2].    \n * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.    \n * Otherwise the functions return ARM_MATH_SUCCESS.    \n * \\note Refer arm_conv_f32() for details on fixed point behavior.   \n *\n * \n * Fast Versions\n *\n * \\par \n * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires\n * the input signals should be scaled down to avoid intermediate overflows.   \n *\n *\n * Opt Versions\n *\n * \\par \n * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.\n * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution\n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of floating-point sequences.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n */\n\narm_status arm_conv_partial_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t *pIn1 = pSrcA;                       /* inputA pointer */\n  float32_t *pIn2 = pSrcB;                       /* inputB pointer */\n  float32_t *pOut = pDst;                        /* output pointer */\n  float32_t *px;                                 /* Intermediate inputA pointer */\n  float32_t *py;                                 /* Intermediate inputB pointer */\n  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */\n  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */\n  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */\n  uint32_t j, k, count = 0u, blkCnt, check;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */\n  arm_status status;                             /* status of Partial convolution */\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds    \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = (int32_t) check - (int32_t) srcALen;\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = ((int32_t) check - blockSize3) -\n      (blockSize1 + (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally    \n     * divided into three stages according to the number of multiplications that has to be    \n     * taken place between inputA samples and inputB samples. In the first stage of the    \n     * algorithm, the multiplications increase by one for every iteration.    \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n     * In the third stage of the algorithm, the multiplications decrease by one    \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex    \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------    \n     * Initializations of stage1    \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]    \n     * sum = x[0] * y[1] + x[1] * y[0]    \n     * ....    \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.    \n       The count variable holds the number of MAC operations performed.    \n       Since the partial convolution starts from from firstIndex    \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc1 = pIn2 + firstIndex;\n    py = pSrc1;\n\n    /* ------------------------    \n     * Stage1 process    \n     * ----------------------*/\n\n    /* The first stage starts here */\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[0] * y[srcBLen - 1] */\n        sum += *px++ * *py--;\n\n        /* x[1] * y[srcBLen - 2] */\n        sum += *px++ * *py--;\n\n        /* x[2] * y[srcBLen - 3] */\n        sum += *px++ * *py--;\n\n        /* x[3] * y[srcBLen - 4] */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc1;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------    \n     * Initializations of stage2    \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n     * ....    \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n    /* -------------------    \n     * Stage2 process    \n     * ------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n     * So, to loop unroll over blockSize2,    \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blockSize2, by 4 */\n      blkCnt = ((uint32_t) blockSize2 >> 2u);\n\n      while(blkCnt > 0u)\n      {\n        /* Set all accumulators to zero */\n        acc0 = 0.0f;\n        acc1 = 0.0f;\n        acc2 = 0.0f;\n        acc3 = 0.0f;\n\n        /* read x[0], x[1], x[2] samples */\n        x0 = *(px++);\n        x1 = *(px++);\n        x2 = *(px++);\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        do\n        {\n          /* Read y[srcBLen - 1] sample */\n          c0 = *(py--);\n\n          /* Read x[3] sample */\n          x3 = *(px++);\n\n          /* Perform the multiply-accumulate */\n          /* acc0 +=  x[0] * y[srcBLen - 1] */\n          acc0 += x0 * c0;\n\n          /* acc1 +=  x[1] * y[srcBLen - 1] */\n          acc1 += x1 * c0;\n\n          /* acc2 +=  x[2] * y[srcBLen - 1] */\n          acc2 += x2 * c0;\n\n          /* acc3 +=  x[3] * y[srcBLen - 1] */\n          acc3 += x3 * c0;\n\n          /* Read y[srcBLen - 2] sample */\n          c0 = *(py--);\n\n          /* Read x[4] sample */\n          x0 = *(px++);\n\n          /* Perform the multiply-accumulate */\n          /* acc0 +=  x[1] * y[srcBLen - 2] */\n          acc0 += x1 * c0;\n          /* acc1 +=  x[2] * y[srcBLen - 2] */\n          acc1 += x2 * c0;\n          /* acc2 +=  x[3] * y[srcBLen - 2] */\n          acc2 += x3 * c0;\n          /* acc3 +=  x[4] * y[srcBLen - 2] */\n          acc3 += x0 * c0;\n\n          /* Read y[srcBLen - 3] sample */\n          c0 = *(py--);\n\n          /* Read x[5] sample */\n          x1 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[2] * y[srcBLen - 3] */\n          acc0 += x2 * c0;\n          /* acc1 +=  x[3] * y[srcBLen - 2] */\n          acc1 += x3 * c0;\n          /* acc2 +=  x[4] * y[srcBLen - 2] */\n          acc2 += x0 * c0;\n          /* acc3 +=  x[5] * y[srcBLen - 2] */\n          acc3 += x1 * c0;\n\n          /* Read y[srcBLen - 4] sample */\n          c0 = *(py--);\n\n          /* Read x[6] sample */\n          x2 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[3] * y[srcBLen - 4] */\n          acc0 += x3 * c0;\n          /* acc1 +=  x[4] * y[srcBLen - 4] */\n          acc1 += x0 * c0;\n          /* acc2 +=  x[5] * y[srcBLen - 4] */\n          acc2 += x1 * c0;\n          /* acc3 +=  x[6] * y[srcBLen - 4] */\n          acc3 += x2 * c0;\n\n\n        } while(--k);\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Read y[srcBLen - 5] sample */\n          c0 = *(py--);\n\n          /* Read x[7] sample */\n          x3 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[4] * y[srcBLen - 5] */\n          acc0 += x0 * c0;\n          /* acc1 +=  x[5] * y[srcBLen - 5] */\n          acc1 += x1 * c0;\n          /* acc2 +=  x[6] * y[srcBLen - 5] */\n          acc2 += x2 * c0;\n          /* acc3 +=  x[7] * y[srcBLen - 5] */\n          acc3 += x3 * c0;\n\n          /* Reuse the present samples for the next MAC */\n          x0 = x1;\n          x1 = x2;\n          x2 = x3;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = acc0;\n        *pOut++ = acc1;\n        *pOut++ = acc2;\n        *pOut++ = acc3;\n\n        /* Increment the pointer pIn1 index, count by 1 */\n        count += 4u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0.0f;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += *px++ * *py--;\n          sum += *px++ * *py--;\n          sum += *px++ * *py--;\n          sum += *px++ * *py--;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += *px++ * *py--;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = sum;\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,    \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0.0f;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += *px++ * *py--;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = sum;\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------    \n     * Initializations of stage3    \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n     * ....    \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n     * sum +=  x[srcALen-1] * y[srcBLen-1]    \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.    \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n        sum += *px++ * *py--;\n\n        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n        sum += *px++ * *py--;\n\n        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n        sum += *px++ * *py--;\n\n        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum += *px++ * *py--;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t *pIn1 = pSrcA;                       /* inputA pointer */\n  float32_t *pIn2 = pSrcB;                       /* inputB pointer */\n  float32_t sum;                                 /* Accumulator */\n  uint32_t i, j;                                 /* loop counters */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n    /* Loop to calculate convolution for output length number of values */\n    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)\n    {\n      /* Initialize sum with zero to carry on MAC operations */\n      sum = 0.0f;\n\n      /* Loop to perform MAC operations according to convolution equation */\n      for (j = 0u; j <= i; j++)\n      {\n        /* Check the array limitations for inputs */\n        if((((i - j) < srcBLen) && (j < srcALen)))\n        {\n          /* z[i] += x[i-j] * y[j] */\n          sum += pIn1[j] * pIn2[i - j];\n        }\n      }\n      /* Store the output in the destination buffer */\n      pDst[i] = sum;\n    }\n    /* set status as ARM_SUCCESS as there are no argument errors */\n    status = ARM_MATH_SUCCESS;\n  }\n  return (status);\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_fast_opt_q15.c    \n*    \n* Description:\tFast Q15 Partial convolution.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   \n * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   \n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n *    \n * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    \n *     \n */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\narm_status arm_conv_partial_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */\n  q31_t y1, y2;                                  /* State variables */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  arm_status status;\n\n  uint32_t tapCnt;                               /* loop count */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2 + srcBLen - 1;\n\n    /* points to smaller length sequence */\n    px = pIn2;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n\n    /* Copy smaller length input sequence in reverse order into second scratch buffer */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Assuming scratch1 buffer is aligned by 32-bit */\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n    /* Copy (srcALen) samples in scratch buffer */\n    arm_copy_q15(pIn1, pScr1, srcALen);\n\n    /* Update pointers */\n    pScr1 += srcALen;\n\n    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = py;\n\n    pScratch1 += firstIndex;\n\n    pOut = pDst + firstIndex;\n\n    /* First part of the processing with loop unrolling process 4 data points at a time.       \n     ** a second loop below process for the remaining 1 to 3 samples. */\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x1 = *__SIMD32(pScr1)++;\n\n      /* Read next two samples from scratch1 buffer */\n      x2 = *__SIMD32(pScr1)++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read four samples from smaller buffer */\n        y1 = _SIMD32_OFFSET(pIn2);\n        y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n        /* multiply and accumlate */\n        acc0 = __SMLAD(x1, y1, acc0);\n        acc2 = __SMLAD(x2, y1, acc2);\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        /* multiply and accumlate */\n        acc1 = __SMLADX(x3, y1, acc1);\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = _SIMD32_OFFSET(pScr1);\n\n        /* multiply and accumlate */\n        acc0 = __SMLAD(x2, y2, acc0);\n\n        acc2 = __SMLAD(x1, y2, acc2);\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x1, x2, 0);\n#else\n        x3 = __PKHBT(x2, x1, 0);\n#endif\n\n        acc3 = __SMLADX(x3, y1, acc3);\n        acc1 = __SMLADX(x3, y2, acc1);\n\n        x2 = _SIMD32_OFFSET(pScr1 + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        acc3 = __SMLADX(x3, y2, acc3);\n\n        /* update scratch pointers */\n        pIn2 += 4u;\n        pScr1 += 4u;\n\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2);\n        acc1 += (*pScr1++ * *pIn2);\n        acc2 += (*pScr1++ * *pIn2);\n        acc3 += (*pScr1++ * *pIn2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n\n    blkCnt = numPoints & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = *__SIMD32(pScr1)++;\n\n        /* Read two samples from smaller buffer */\n        y1 = *__SIMD32(pIn2)++;\n\n        acc0 = __SMLAD(x1, y1, acc0);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* The result is in 2.30 format.  Convert to 1.15 with saturation.       \n       ** Then store the output in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 1u;\n\n    }\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n  /* Return to application */\n  return (status);\n}\n\n#else\n\narm_status arm_conv_partial_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  arm_status status;                             /* Status variable */\n  uint32_t tapCnt;                               /* loop count */\n  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */\n  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2 + srcBLen - 1;\n\n    /* points to smaller length sequence */\n    px = pIn2;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcALen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcALen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr1++ = *pIn1++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = (srcBLen - 1u) >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = (srcBLen - 1u) % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = py;\n\n    pScratch1 += firstIndex;\n\n    pOut = pDst + firstIndex;\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x10 = *pScr1++;\n      x11 = *pScr1++;\n\n      /* Read next two samples from scratch1 buffer */\n      x20 = *pScr1++;\n      x21 = *pScr1++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read two samples from smaller buffer */\n        y10 = *pIn2;\n        y11 = *(pIn2 + 1u);\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x10 *y10;\n        acc0 += (q31_t) x11 *y11;\n        acc2 += (q31_t) x20 *y10;\n        acc2 += (q31_t) x21 *y11;\n\n        /* multiply and accumlate */\n        acc1 += (q31_t) x11 *y10;\n        acc1 += (q31_t) x20 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1;\n        x11 = *(pScr1 + 1u);\n\n        /* multiply and accumlate */\n        acc3 += (q31_t) x21 *y10;\n        acc3 += (q31_t) x10 *y11;\n\n        /* Read next two samples from scratch2 buffer */\n        y10 = *(pIn2 + 2u);\n        y11 = *(pIn2 + 3u);\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x20 *y10;\n        acc0 += (q31_t) x21 *y11;\n        acc2 += (q31_t) x10 *y10;\n        acc2 += (q31_t) x11 *y11;\n        acc1 += (q31_t) x21 *y10;\n        acc1 += (q31_t) x10 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x20 = *(pScr1 + 2);\n        x21 = *(pScr1 + 3);\n\n        /* multiply and accumlate */\n        acc3 += (q31_t) x11 *y10;\n        acc3 += (q31_t) x20 *y11;\n\n        /* update scratch pointers */\n        pIn2 += 4u;\n        pScr1 += 4u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2);\n        acc1 += (*pScr1++ * *pIn2);\n        acc2 += (*pScr1++ * *pIn2);\n        acc3 += (*pScr1++ * *pIn2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n      *pOut++ = __SSAT((acc0 >> 15), 16);\n      *pOut++ = __SSAT((acc1 >> 15), 16);\n      *pOut++ = __SSAT((acc2 >> 15), 16);\n      *pOut++ = __SSAT((acc3 >> 15), 16);\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n\n    blkCnt = numPoints & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1++;\n        x11 = *pScr1++;\n\n        /* Read two samples from smaller buffer */\n        y10 = *pIn2++;\n        y11 = *pIn2++;\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x10 *y10;\n        acc0 += (q31_t) x11 *y11;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 1u;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_partial_fast_q15.c   \n*   \n* Description:\tFast Q15 Partial convolution.   \n*   \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup PartialConv   \n * @{   \n */\n\n/**   \n * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   \n * @param[in]       *pSrcA points to the first input sequence.   \n * @param[in]       srcALen length of the first input sequence.   \n * @param[in]       *pSrcB points to the second input sequence.   \n * @param[in]       srcBLen length of the second input sequence.   \n * @param[out]      *pDst points to the location where the output result is written.   \n * @param[in]       firstIndex is the first output sample to start with.   \n * @param[in]       numPoints is the number of output points to be computed.   \n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   \n *   \n * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   \n */\n\n\narm_status arm_conv_partial_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >=srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds   \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally   \n     * divided into three stages according to the number of multiplications that has to be   \n     * taken place between inputA samples and inputB samples. In the first stage of the   \n     * algorithm, the multiplications increase by one for every iteration.   \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n     * In the third stage of the algorithm, the multiplications decrease by one   \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex   \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------   \n     * Initializations of stage1   \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]   \n     * sum = x[0] * y[1] + x[1] * y[0]   \n     * ....   \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed.   \n       Since the partial convolution starts from firstIndex   \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------   \n     * Stage1 process   \n     * ----------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations less than 4 */\n    /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n    /* The first part of the stage starts here */\n    while((count < 4u) && (blockSize1 > 0))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over number of MAC operations between   \n       * inputA samples and inputB samples */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* The second part of the stage starts here */\n    /* The internal loop, over count, is unrolled by 4 */\n    /* To, read the last two inputB samples using SIMD:   \n     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n    py = py - 1;\n\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */\n        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */\n        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* For the next MAC operations, the pointer py is used without SIMD   \n       * So, py is incremented by 1 */\n      py = py + 1u;\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2 - 1u;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------   \n     * Initializations of stage2   \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n     * ....   \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is the index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n\n    /* --------------------   \n     * Stage2 process   \n     * -------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n     * So, to loop unroll over blockSize2,   \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blockSize2, by 4 */\n      blkCnt = ((uint32_t) blockSize2 >> 2u);\n\n      while(blkCnt > 0u)\n      {\n      py = py - 1u;\n\n        /* Set all accumulators to zero */\n        acc0 = 0;\n        acc1 = 0;\n        acc2 = 0;\n        acc3 = 0;\n\n\n        /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n        /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px+1);\n\t  px+= 2u;\n\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        do\n        {\n          /* Read the last two inputB samples using SIMD:   \n           * y[srcBLen - 1] and y[srcBLen - 2] */\n        c0 = *__SIMD32(py)--;\n\n          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n          acc0 = __SMLADX(x0, c0, acc0);\n\n          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n          acc1 = __SMLADX(x1, c0, acc1);\n\n          /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n          /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px+1);\n\n          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n          acc2 = __SMLADX(x2, c0, acc2);\n\n          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n          acc3 = __SMLADX(x3, c0, acc3);\n\n          /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n        c0 = *__SIMD32(py)--;\n\n          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n          acc0 = __SMLADX(x2, c0, acc0);\n\n          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n          acc1 = __SMLADX(x3, c0, acc1);\n\n          /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px+2);\n\n          /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px+3);\n\t\tpx += 4u;\n\n          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n          acc2 = __SMLADX(x0, c0, acc2);\n\n          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n          acc3 = __SMLADX(x1, c0, acc3);\n\n        } while(--k);\n\n        /* For the next MAC operations, SIMD is not used   \n         * So, the 16 bit pointer if inputB, py is updated */\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        if(k == 1u)\n        {\n          /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n          /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n          /* Perform the multiply-accumulates */\n          acc0 = __SMLAD(x0, c0, acc0);\n          acc1 = __SMLAD(x1, c0, acc1);\n          acc2 = __SMLADX(x1, c0, acc2);\n          acc3 = __SMLADX(x3, c0, acc3);\n        }\n\n        if(k == 2u)\n        {\n          /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n          /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\t\tpx += 2u;\n\n          /* Perform the multiply-accumulates */\n          acc0 = __SMLADX(x0, c0, acc0);\n          acc1 = __SMLADX(x1, c0, acc1);\n          acc2 = __SMLADX(x3, c0, acc2);\n          acc3 = __SMLADX(x2, c0, acc3);\n        }\n\n        if(k == 3u)\n        {\n          /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n          /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n          /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\n          /* Perform the multiply-accumulates */\n          acc0 = __SMLADX(x0, c0, acc0);\n          acc1 = __SMLADX(x1, c0, acc1);\n          acc2 = __SMLADX(x3, c0, acc2);\n          acc3 = __SMLADX(x2, c0, acc3);\n\n\t\tc0 = *(py-1);\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n          /* Read x[10] */\n        x3 =  _SIMD32_OFFSET(px+2);\n\t\tpx += 3u;\n\n          /* Perform the multiply-accumulates */\n          acc0 = __SMLADX(x1, c0, acc0);\n          acc1 = __SMLAD(x2, c0, acc1);\n          acc2 = __SMLADX(x2, c0, acc2);\n          acc3 = __SMLADX(x3, c0, acc3);\n        }\n\n        /* Store the results in the accumulators in the destination buffer. */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);\n        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);\n\n#else\n\n        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);\n        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n        /* Increment the pointer pIn1 index, count by 4 */\n        count += 4u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (sum >> 15);\n\n        /* Increment the pointer pIn1 index, count by 1 */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,   \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (sum >> 15);\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------   \n     * Initializations of stage3   \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n     * ....   \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n     * sum +=  x[srcALen-1] * y[srcBLen-1]   \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    pIn2 = pSrc2 - 1u;\n    py = pIn2;\n\n    /* -------------------   \n     * Stage3 process   \n     * ------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations greater than 4 */\n    /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n    /* The first part of the stage starts here */\n    j = count >> 2u;\n\n    while((j > 0u) && (blockSize3 > 0))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   \n         * with y[srcBLen - 1], y[srcBLen - 2] respectively */\n        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   \n         * with y[srcBLen - 3], y[srcBLen - 4] respectively */\n        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* For the next MAC operations, the pointer py is used without SIMD   \n       * So, py is incremented by 1 */\n      py = py + 1u;\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */\n        sum = __SMLAD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pIn2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n      j--;\n    }\n\n    /* The second part of the stage starts here */\n    /* SIMD is not used for the next MAC operations,   \n     * so pointer py is updated to read only one sample at a time */\n    py = py + 1u;\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum = __SMLAD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#else\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */\n  arm_status status;                             /* status of Partial convolution */\n  q15_t a, b;\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >=srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds   \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally   \n     * divided into three stages according to the number of multiplications that has to be   \n     * taken place between inputA samples and inputB samples. In the first stage of the   \n     * algorithm, the multiplications increase by one for every iteration.   \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n     * In the third stage of the algorithm, the multiplications decrease by one   \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex   \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------   \n     * Initializations of stage1   \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]   \n     * sum = x[0] * y[1] + x[1] * y[0]   \n     * ....   \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed.   \n       Since the partial convolution starts from firstIndex   \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------   \n     * Stage1 process   \n     * ----------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations less than 4 */\n    /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n    /* The first part of the stage starts here */\n  while((count < 4u) && (blockSize1 > 0u))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over number of MAC operations between   \n       * inputA samples and inputB samples */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n      sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* The second part of the stage starts here */\n    /* The internal loop, over count, is unrolled by 4 */\n    /* To, read the last two inputB samples using SIMD:   \n     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n    py = py - 1;\n\n  while(blockSize1 > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n\tpy++;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n      sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2 - 1u;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------   \n     * Initializations of stage2   \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n     * ....   \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is the index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n\n    /* --------------------   \n     * Stage2 process   \n     * -------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n     * So, to loop unroll over blockSize2,   \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blockSize2, by 4 */\n      blkCnt = ((uint32_t) blockSize2 >> 2u);\n\n      while(blkCnt > 0u)\n      {\n      py = py - 1u;\n\n        /* Set all accumulators to zero */\n        acc0 = 0;\n        acc1 = 0;\n        acc2 = 0;\n        acc3 = 0;\n\n      /* read x[0], x[1] samples */\n\t  a = *px++;\n\t  b = *px++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x0 = __PKHBT(a, b, 16);\n\t  a = *px;\n\t  x1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x0 = __PKHBT(b, a, 16);\n\t  a = *px;\n\t  x1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the last two inputB samples using SIMD:   \n         * y[srcBLen - 1] and y[srcBLen - 2] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\t\tpy -= 2;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n        acc0 = __SMLADX(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n        acc1 = __SMLADX(x1, c0, acc1);\n\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x2 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x3 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x2 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x3 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n        acc2 = __SMLADX(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n        acc3 = __SMLADX(x3, c0, acc3);\n\n        /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\t\tpy -= 2;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n        acc0 = __SMLADX(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n        acc1 = __SMLADX(x3, c0, acc1);\n\n        /* Read x[4], x[5], x[6] */\n\t  a = *(px + 2);\n\t  b = *(px + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x0 = __PKHBT(a, b, 16);\n\t  a = *(px + 4);\n\t  x1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x0 = __PKHBT(b, a, 16);\n\t  a = *(px + 4);\n\t  x1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n        acc2 = __SMLADX(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n        acc3 = __SMLADX(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n\t\ta = *px;\n\t\tb = *(px+1);\n\t\tpx++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tx3 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tx3 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLADX(x1, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Read x[7], x[8], x[9] */\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x3 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x3 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n\t\ta = *py;\n\t\tb = *(py+1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tc0 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tc0 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Read x[7], x[8], x[9] */\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t  x3 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x3 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t   */\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x0, c0, acc0);\n        acc1 = __SMLADX(x1, c0, acc1);\n        acc2 = __SMLADX(x3, c0, acc2);\n        acc3 = __SMLADX(x2, c0, acc3);\n\n        /* Read y[srcBLen - 7] */\n\t\tc0 = *(py-1);\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n\t\ta = *(px+2);\n\t\tb = *(px+3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t\tx3 = __PKHBT(a, b, 16);\n\n#else\n\n \t\tx3 = __PKHBT(b, a, 16);;\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x1, c0, acc0);\n        acc1 = __SMLAD(x2, c0, acc1);\n        acc2 = __SMLADX(x2, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      /* Store the results in the accumulators in the destination buffer. */\n\t  *pOut++ = (q15_t)(acc0 >> 15);\n\t  *pOut++ = (q15_t)(acc1 >> 15);\n\t  *pOut++ = (q15_t)(acc2 >> 15);\n\t  *pOut++ = (q15_t)(acc3 >> 15);\n\n        /* Increment the pointer pIn1 index, count by 4 */\n        count += 4u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (sum >> 15);\n\n        /* Increment the pointer pIn1 index, count by 1 */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,   \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (sum >> 15);\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------   \n     * Initializations of stage3   \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n     * ....   \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n     * sum +=  x[srcALen-1] * y[srcBLen-1]   \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    pIn2 = pSrc2 - 1u;\n    py = pIn2;\n\n    /* -------------------   \n     * Stage3 process   \n     * ------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations greater than 4 */\n    /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n    /* The first part of the stage starts here */\n    j = count >> 2u;\n\n    while((j > 0u) && (blockSize3 > 0))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n\tpy++;\n\n    while(k > 0u)\n    {\t\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n        sum += ((q31_t) * px++ * *py--);\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pIn2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n      j--;\n    }\n\n    /* The second part of the stage starts here */\n    /* SIMD is not used for the next MAC operations,   \n     * so pointer py is updated to read only one sample at a time */\n    py = py + 1u;\n\n  while(blockSize3 > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (sum >> 15);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */\n}\n\n/**   \n * @} end of PartialConv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_fast_q31.c    \n*    \n* Description:\tFast Q31 Partial convolution.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n *    \n * \\par    \n * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    \n */\n\narm_status arm_conv_partial_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n  q31_t *pIn1;                                   /* inputA pointer               */\n  q31_t *pIn2;                                   /* inputB pointer               */\n  q31_t *pOut = pDst;                            /* output pointer               */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q31_t x0, x1, x2, x3, c0;\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */\n  arm_status status;                             /* status of Partial convolution */\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds    \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally    \n     * divided into three stages according to the number of multiplications that has to be    \n     * taken place between inputA samples and inputB samples. In the first stage of the    \n     * algorithm, the multiplications increase by one for every iteration.    \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n     * In the third stage of the algorithm, the multiplications decrease by one    \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex    \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------    \n     * Initializations of stage1    \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]    \n     * sum = x[0] * y[1] + x[1] * y[0]    \n     * ....    \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.    \n       The count variable holds the number of MAC operations performed.    \n       Since the partial convolution starts from firstIndex    \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------    \n     * Stage1 process    \n     * ----------------------*/\n\n    /* The first loop starts here */\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[0] * y[srcBLen - 1] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* x[1] * y[srcBLen - 2] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* x[2] * y[srcBLen - 3] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* x[3] * y[srcBLen - 4] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum << 1;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------    \n     * Initializations of stage2    \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n     * ....    \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n    /* -------------------    \n     * Stage2 process    \n     * ------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n     * So, to loop unroll over blockSize2,    \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blockSize2 */\n      blkCnt = ((uint32_t) blockSize2 >> 2u);\n\n      while(blkCnt > 0u)\n      {\n        /* Set all accumulators to zero */\n        acc0 = 0;\n        acc1 = 0;\n        acc2 = 0;\n        acc3 = 0;\n\n        /* read x[0], x[1], x[2] samples */\n        x0 = *(px++);\n        x1 = *(px++);\n        x2 = *(px++);\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        do\n        {\n          /* Read y[srcBLen - 1] sample */\n          c0 = *(py--);\n\n          /* Read x[3] sample */\n          x3 = *(px++);\n\n          /* Perform the multiply-accumulate */\n          /* acc0 +=  x[0] * y[srcBLen - 1] */\n          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n          /* acc1 +=  x[1] * y[srcBLen - 1] */\n          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n          /* acc2 +=  x[2] * y[srcBLen - 1] */\n          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n\n          /* acc3 +=  x[3] * y[srcBLen - 1] */\n          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n          /* Read y[srcBLen - 2] sample */\n          c0 = *(py--);\n\n          /* Read x[4] sample */\n          x0 = *(px++);\n\n          /* Perform the multiply-accumulate */\n          /* acc0 +=  x[1] * y[srcBLen - 2] */\n          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);\n          /* acc1 +=  x[2] * y[srcBLen - 2] */\n          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);\n          /* acc2 +=  x[3] * y[srcBLen - 2] */\n          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);\n          /* acc3 +=  x[4] * y[srcBLen - 2] */\n          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n          /* Read y[srcBLen - 3] sample */\n          c0 = *(py--);\n\n          /* Read x[5] sample */\n          x1 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[2] * y[srcBLen - 3] */\n          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);\n          /* acc1 +=  x[3] * y[srcBLen - 2] */\n          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);\n          /* acc2 +=  x[4] * y[srcBLen - 2] */\n          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);\n          /* acc3 +=  x[5] * y[srcBLen - 2] */\n          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n          /* Read y[srcBLen - 4] sample */\n          c0 = *(py--);\n\n          /* Read x[6] sample */\n          x2 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[3] * y[srcBLen - 4] */\n          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);\n          /* acc1 +=  x[4] * y[srcBLen - 4] */\n          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);\n          /* acc2 +=  x[5] * y[srcBLen - 4] */\n          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);\n          /* acc3 +=  x[6] * y[srcBLen - 4] */\n          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);\n\n\n        } while(--k);\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Read y[srcBLen - 5] sample */\n          c0 = *(py--);\n\n          /* Read x[7] sample */\n          x3 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[4] * y[srcBLen - 5] */\n          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n          /* acc1 +=  x[5] * y[srcBLen - 5] */\n          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n          /* acc2 +=  x[6] * y[srcBLen - 5] */\n          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n          /* acc3 +=  x[7] * y[srcBLen - 5] */\n          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n          /* Reuse the present samples for the next MAC */\n          x0 = x1;\n          x1 = x2;\n          x2 = x3;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q31_t) (acc0 << 1);\n        *pOut++ = (q31_t) (acc1 << 1);\n        *pOut++ = (q31_t) (acc2 << 1);\n        *pOut++ = (q31_t) (acc3 << 1);\n\n        /* Increment the pointer pIn1 index, count by 4 */\n        count += 4u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = sum << 1;\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,    \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * px++ * (*py--))) >> 32);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = sum << 1;\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------    \n     * Initializations of stage3    \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n     * ....    \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n     * sum +=  x[srcALen-1] * y[srcBLen-1]    \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.    \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* -------------------    \n     * Stage3 process    \n     * ------------------*/\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py--))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = sum << 1;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n}\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_opt_q15.c    \n*    \n* Description:\tPartial convolution of Q15 sequences.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of Q15 sequences.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   \n * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   \n * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, state buffers should be aligned by 32-bit    \n *    \n * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   \n *  \n * \n */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\narm_status arm_conv_partial_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */\n  q31_t y1, y2;                                  /* State variables */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  arm_status status;                             /* Status variable */\n  uint32_t tapCnt;                               /* loop count */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2 + srcBLen - 1;\n\n    /* points to smaller length sequence */\n    px = pIn2;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n    /* Copy (srcALen) samples in scratch buffer */\n    arm_copy_q15(pIn1, pScr1, srcALen);\n\n    /* Update pointers */\n    pScr1 += srcALen;\n\n    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = py;\n\n    pScratch1 += firstIndex;\n\n    pOut = pDst + firstIndex;\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x1 = *__SIMD32(pScr1)++;\n\n      /* Read next two samples from scratch1 buffer */\n      x2 = *__SIMD32(pScr1)++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read four samples from smaller buffer */\n        y1 = _SIMD32_OFFSET(pIn2);\n        y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n        /* multiply and accumlate */\n        acc0 = __SMLALD(x1, y1, acc0);\n        acc2 = __SMLALD(x2, y1, acc2);\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        /* multiply and accumlate */\n        acc1 = __SMLALDX(x3, y1, acc1);\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = _SIMD32_OFFSET(pScr1);\n\n        /* multiply and accumlate */\n        acc0 = __SMLALD(x2, y2, acc0);\n        acc2 = __SMLALD(x1, y2, acc2);\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x1, x2, 0);\n#else\n        x3 = __PKHBT(x2, x1, 0);\n#endif\n\n        acc3 = __SMLALDX(x3, y1, acc3);\n        acc1 = __SMLALDX(x3, y2, acc1);\n\n        x2 = _SIMD32_OFFSET(pScr1 + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        acc3 = __SMLALDX(x3, y2, acc3);\n\n        /* update scratch pointers */\n        pIn2 += 4u;\n        pScr1 += 4u;\n\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2);\n        acc1 += (*pScr1++ * *pIn2);\n        acc2 += (*pScr1++ * *pIn2);\n        acc3 += (*pScr1++ * *pIn2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n\n    blkCnt = numPoints & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = *__SIMD32(pScr1)++;\n\n        /* Read two samples from smaller buffer */\n        y1 = *__SIMD32(pIn2)++;\n\n        acc0 = __SMLALD(x1, y1, acc0);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 1u;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n#else\n\narm_status arm_conv_partial_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pOut = pDst;                            /* output pointer */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  uint32_t j, k, blkCnt;                         /* loop counter */\n  arm_status status;                             /* Status variable */\n  uint32_t tapCnt;                               /* loop count */\n  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */\n  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2 + srcBLen - 1;\n\n    /* points to smaller length sequence */\n    px = pIn2;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr2-- = *px++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */\n\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcALen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n      *pScr1++ = *pIn1++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcALen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr1++ = *pIn1++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = (srcBLen - 1u) >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = (srcBLen - 1u) % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = py;\n\n    pScratch1 += firstIndex;\n\n    pOut = pDst + firstIndex;\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x10 = *pScr1++;\n      x11 = *pScr1++;\n\n      /* Read next two samples from scratch1 buffer */\n      x20 = *pScr1++;\n      x21 = *pScr1++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read two samples from smaller buffer */\n        y10 = *pIn2;\n        y11 = *(pIn2 + 1u);\n\n        /* multiply and accumlate */\n        acc0 += (q63_t) x10 *y10;\n        acc0 += (q63_t) x11 *y11;\n        acc2 += (q63_t) x20 *y10;\n        acc2 += (q63_t) x21 *y11;\n\n        /* multiply and accumlate */\n        acc1 += (q63_t) x11 *y10;\n        acc1 += (q63_t) x20 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1;\n        x11 = *(pScr1 + 1u);\n\n        /* multiply and accumlate */\n        acc3 += (q63_t) x21 *y10;\n        acc3 += (q63_t) x10 *y11;\n\n        /* Read next two samples from scratch2 buffer */\n        y10 = *(pIn2 + 2u);\n        y11 = *(pIn2 + 3u);\n\n        /* multiply and accumlate */\n        acc0 += (q63_t) x20 *y10;\n        acc0 += (q63_t) x21 *y11;\n        acc2 += (q63_t) x10 *y10;\n        acc2 += (q63_t) x11 *y11;\n        acc1 += (q63_t) x21 *y10;\n        acc1 += (q63_t) x10 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x20 = *(pScr1 + 2);\n        x21 = *(pScr1 + 3);\n\n        /* multiply and accumlate */\n        acc3 += (q63_t) x11 *y10;\n        acc3 += (q63_t) x20 *y11;\n\n        /* update scratch pointers */\n        pIn2 += 4u;\n        pScr1 += 4u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2);\n        acc1 += (*pScr1++ * *pIn2);\n        acc2 += (*pScr1++ * *pIn2);\n        acc3 += (*pScr1++ * *pIn2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n      *pOut++ = __SSAT((acc0 >> 15), 16);\n      *pOut++ = __SSAT((acc1 >> 15), 16);\n      *pOut++ = __SSAT((acc2 >> 15), 16);\n      *pOut++ = __SSAT((acc3 >> 15), 16);\n\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n\n    blkCnt = numPoints & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1++;\n        x11 = *pScr1++;\n\n        /* Read two samples from smaller buffer */\n        y10 = *pIn2++;\n        y11 = *pIn2++;\n\n        /* multiply and accumlate */\n        acc0 += (q63_t) x10 *y10;\n        acc0 += (q63_t) x11 *y11;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pIn2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n\n      /* Initialization of inputB pointer */\n      pIn2 = py;\n\n      pScratch1 += 1u;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_opt_q7.c    \n*    \n* Description:\tPartial convolution of Q7 sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of Q7 sequences.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    \n * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    \n * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit   \n * \n *\n * \n */\n\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\narm_status arm_conv_partial_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */\n  q15_t x4;                                      /* Temporary input variable */\n  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */\n  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */\n  q7_t *px;                                      /* Temporary input1 pointer */\n  q15_t *py;                                     /* Temporary input2 pointer */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  q31_t x1, x2, x3, y1;                          /* Temporary input variables */\n  arm_status status;\n  q7_t *pOut = pDst;                             /* output pointer */\n  q7_t out0, out1, out2, out3;                   /* temporary variables */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2;\n\n    /* points to smaller length sequence */\n    px = pIn2 + srcBLen - 1;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy (srcALen) samples in scratch buffer */\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcALen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcALen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update pointer */\n    pScr1 += (srcBLen - 1u);\n\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = (q7_t *) py;\n\n    pScr2 = py;\n\n    pOut = pDst + firstIndex;\n\n    pScratch1 += firstIndex;\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x1 = *__SIMD32(pScr1)++;\n\n      /* Read next two samples from scratch1 buffer */\n      x2 = *__SIMD32(pScr1)++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read four samples from smaller buffer */\n        y1 = _SIMD32_OFFSET(pScr2);\n\n        /* multiply and accumlate */\n        acc0 = __SMLAD(x1, y1, acc0);\n        acc2 = __SMLAD(x2, y1, acc2);\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        /* multiply and accumlate */\n        acc1 = __SMLADX(x3, y1, acc1);\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = *__SIMD32(pScr1)++;\n\n        /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x1, x2, 0);\n#else\n        x3 = __PKHBT(x2, x1, 0);\n#endif\n\n        acc3 = __SMLADX(x3, y1, acc3);\n\n        /* Read four samples from smaller buffer */\n        y1 = _SIMD32_OFFSET(pScr2 + 2u);\n\n        acc0 = __SMLAD(x2, y1, acc0);\n\n        acc2 = __SMLAD(x1, y1, acc2);\n\n        acc1 = __SMLADX(x3, y1, acc1);\n\n        x2 = *__SIMD32(pScr1)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n        x3 = __PKHBT(x2, x1, 0);\n#else\n        x3 = __PKHBT(x1, x2, 0);\n#endif\n\n        acc3 = __SMLADX(x3, y1, acc3);\n\n        pScr2 += 4u;\n\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pScr2);\n        acc1 += (*pScr1++ * *pScr2);\n        acc2 += (*pScr1++ * *pScr2);\n        acc3 += (*pScr1++ * *pScr2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));\n      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));\n      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));\n      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));\n\n      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);\n\n      /* Initialization of inputB pointer */\n      pScr2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n    blkCnt = (numPoints) & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x1 = *__SIMD32(pScr1)++;\n\n        /* Read two samples from smaller buffer */\n        y1 = *__SIMD32(pScr2)++;\n\n        acc0 = __SMLAD(x1, y1, acc0);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pScr2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));\n\n      /* Initialization of inputB pointer */\n      pScr2 = py;\n\n      pScratch1 += 1u;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n\n  }\n\n  return (status);\n\n}\n\n#else\n\narm_status arm_conv_partial_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n\n  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */\n  q15_t x4;                                      /* Temporary input variable */\n  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */\n  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */\n  q7_t *px;                                      /* Temporary input1 pointer */\n  q15_t *py;                                     /* Temporary input2 pointer */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */\n  arm_status status;\n  q7_t *pOut = pDst;                             /* output pointer */\n  q15_t x10, x11, x20, x21;                      /* Temporary input variables */\n  q15_t y10, y11;                                /* Temporary input variables */\n  q7_t out0, out1, out2, out3;                   /* temporary variables */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* pointer to take end of scratch2 buffer */\n    pScr2 = pScratch2;\n\n    /* points to smaller length sequence */\n    px = pIn2 + srcBLen - 1;\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcBLen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcBLen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      x4 = (q15_t) * px--;\n      *pScr2++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Initialze temporary scratch pointer */\n    pScr1 = pScratch1;\n\n    /* Fill (srcBLen - 1u) zeros in scratch buffer */\n    arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n    /* Update temporary scratch pointer */\n    pScr1 += (srcBLen - 1u);\n\n    /* Copy (srcALen) samples in scratch buffer */\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = srcALen >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = srcALen % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      x4 = (q15_t) * pIn1++;\n      *pScr1++ = x4;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Apply loop unrolling and do 4 Copies simultaneously. */\n    k = (srcBLen - 1u) >> 2u;\n\n    /* First part of the processing with loop unrolling copies 4 data points at a time.       \n     ** a second loop below copies for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner */\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, copy remaining samples here.       \n     ** No loop unrolling is used. */\n    k = (srcBLen - 1u) % 0x4u;\n\n    while(k > 0u)\n    {\n      /* copy second buffer in reversal manner for remaining samples */\n      *pScr1++ = 0;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n\n    /* Temporary pointer for scratch2 */\n    py = pScratch2;\n\n    /* Initialization of pIn2 pointer */\n    pIn2 = (q7_t *) py;\n\n    pScr2 = py;\n\n    pOut = pDst + firstIndex;\n\n    pScratch1 += firstIndex;\n\n    /* Actual convolution process starts here */\n    blkCnt = (numPoints) >> 2;\n\n\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* Read two samples from scratch1 buffer */\n      x10 = *pScr1++;\n      x11 = *pScr1++;\n\n      /* Read next two samples from scratch1 buffer */\n      x20 = *pScr1++;\n      x21 = *pScr1++;\n\n      tapCnt = (srcBLen) >> 2u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read four samples from smaller buffer */\n        y10 = *pScr2;\n        y11 = *(pScr2 + 1u);\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x10 *y10;\n        acc0 += (q31_t) x11 *y11;\n        acc2 += (q31_t) x20 *y10;\n        acc2 += (q31_t) x21 *y11;\n\n\n        acc1 += (q31_t) x11 *y10;\n        acc1 += (q31_t) x20 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1;\n        x11 = *(pScr1 + 1u);\n\n        /* multiply and accumlate */\n        acc3 += (q31_t) x21 *y10;\n        acc3 += (q31_t) x10 *y11;\n\n        /* Read next two samples from scratch2 buffer */\n        y10 = *(pScr2 + 2u);\n        y11 = *(pScr2 + 3u);\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x20 *y10;\n        acc0 += (q31_t) x21 *y11;\n        acc2 += (q31_t) x10 *y10;\n        acc2 += (q31_t) x11 *y11;\n        acc1 += (q31_t) x21 *y10;\n        acc1 += (q31_t) x10 *y11;\n\n        /* Read next two samples from scratch1 buffer */\n        x20 = *(pScr1 + 2);\n        x21 = *(pScr1 + 3);\n\n        /* multiply and accumlate */\n        acc3 += (q31_t) x11 *y10;\n        acc3 += (q31_t) x20 *y11;\n\n        /* update scratch pointers */\n\n        pScr1 += 4u;\n        pScr2 += 4u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n\n\n      /* Update scratch pointer for remaining samples of smaller length sequence */\n      pScr1 -= 4u;\n\n\n      /* apply same above for remaining samples of smaller length sequence */\n      tapCnt = (srcBLen) & 3u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pScr2);\n        acc1 += (*pScr1++ * *pScr2);\n        acc2 += (*pScr1++ * *pScr2);\n        acc3 += (*pScr1++ * *pScr2++);\n\n        pScr1 -= 3u;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));\n      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));\n      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));\n      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));\n\n\n      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);\n\n      /* Initialization of inputB pointer */\n      pScr2 = py;\n\n      pScratch1 += 4u;\n\n    }\n\n    blkCnt = (numPoints) & 0x3;\n\n    /* Calculate convolution for remaining samples of Bigger length sequence */\n    while(blkCnt > 0)\n    {\n      /* Initialze temporary scratch pointer as scratch1 */\n      pScr1 = pScratch1;\n\n      /* Clear Accumlators */\n      acc0 = 0;\n\n      tapCnt = (srcBLen) >> 1u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read next two samples from scratch1 buffer */\n        x10 = *pScr1++;\n        x11 = *pScr1++;\n\n        /* Read two samples from smaller buffer */\n        y10 = *pScr2++;\n        y11 = *pScr2++;\n\n        /* multiply and accumlate */\n        acc0 += (q31_t) x10 *y10;\n        acc0 += (q31_t) x11 *y11;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      tapCnt = (srcBLen) & 1u;\n\n      /* apply same above for remaining samples of smaller length sequence */\n      while(tapCnt > 0u)\n      {\n\n        /* accumlate the results */\n        acc0 += (*pScr1++ * *pScr2++);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      blkCnt--;\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));\n\n      /* Initialization of inputB pointer */\n      pScr2 = py;\n\n      pScratch1 += 1u;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n  }\n\n  return (status);\n\n}\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_partial_q15.c   \n*   \n* Description:\tPartial convolution of Q15 sequences.  \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n* \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup PartialConv   \n * @{   \n */\n\n/**   \n * @brief Partial convolution of Q15 sequences.   \n * @param[in]       *pSrcA points to the first input sequence.   \n * @param[in]       srcALen length of the first input sequence.   \n * @param[in]       *pSrcB points to the second input sequence.   \n * @param[in]       srcBLen length of the second input sequence.   \n * @param[out]      *pDst points to the location where the output result is written.   \n * @param[in]       firstIndex is the first output sample to start with.   \n * @param[in]       numPoints is the number of output points to be computed.   \n * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   \n *   \n * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.  \n * \n * \\par    \n * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.\n * \n */\n\n\narm_status arm_conv_partial_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n\n#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds   \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally   \n     * divided into three stages according to the number of multiplications that has to be   \n     * taken place between inputA samples and inputB samples. In the first stage of the   \n     * algorithm, the multiplications increase by one for every iteration.   \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n     * In the third stage of the algorithm, the multiplications decrease by one   \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex   \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------   \n     * Initializations of stage1   \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]   \n     * sum = x[0] * y[1] + x[1] * y[0]   \n     * ....   \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed.   \n       Since the partial convolution starts from firstIndex   \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------   \n     * Stage1 process   \n     * ----------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations less than 4 */\n    /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n    /* The first part of the stage starts here */\n    while((count < 4u) && (blockSize1 > 0))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over number of MAC operations between   \n       * inputA samples and inputB samples */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = __SMLALD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* The second part of the stage starts here */\n    /* The internal loop, over count, is unrolled by 4 */\n    /* To, read the last two inputB samples using SIMD:   \n     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n    py = py - 1;\n\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */\n        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */\n        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* For the next MAC operations, the pointer py is used without SIMD   \n       * So, py is incremented by 1 */\n      py = py + 1u;\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = __SMLALD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2 - 1u;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------   \n     * Initializations of stage2   \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n     * ....   \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n  /* count is the index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n\n  /* --------------------   \n   * Stage2 process   \n   * -------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      py = py - 1u;\n\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n\n      /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n      /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px+1);\n\t  px+= 2u;\n\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the last two inputB samples using SIMD:   \n         * y[srcBLen - 1] and y[srcBLen - 2] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n        acc0 = __SMLALDX(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n        acc1 = __SMLALDX(x1, c0, acc1);\n\n        /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n        /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px+1);\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n        acc2 = __SMLALDX(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n        acc3 = __SMLALDX(x3, c0, acc3);\n\n        /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n        acc0 = __SMLALDX(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n        acc1 = __SMLALDX(x3, c0, acc1);\n\n        /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px+2);\n\n        /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px+3);\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n        acc2 = __SMLALDX(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n        acc3 = __SMLALDX(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALD(x0, c0, acc0);\n        acc1 = __SMLALD(x1, c0, acc1);\n        acc2 = __SMLALDX(x1, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x0, c0, acc0);\n        acc1 = __SMLALDX(x1, c0, acc1);\n        acc2 = __SMLALDX(x3, c0, acc2);\n        acc3 = __SMLALDX(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x0, c0, acc0);\n        acc1 = __SMLALDX(x1, c0, acc1);\n        acc2 = __SMLALDX(x3, c0, acc2);\n        acc3 = __SMLALDX(x2, c0, acc3);\n\n\t\tc0 = *(py-1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n        x3 =  _SIMD32_OFFSET(px+2);\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x1, c0, acc0);\n        acc1 = __SMLALD(x2, c0, acc1);\n        acc2 = __SMLALDX(x2, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n  \t  \n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));\n\n        /* Increment the pointer pIn1 index, count by 1 */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,   \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += (q63_t) ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n  \n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------   \n     * Initializations of stage3   \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n     * ....   \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n     * sum +=  x[srcALen-1] * y[srcBLen-1]   \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    pIn2 = pSrc2 - 1u;\n    py = pIn2;\n\n    /* -------------------   \n     * Stage3 process   \n     * ------------------*/\n\n    /* For loop unrolling by 4, this stage is divided into two. */\n    /* First part of this stage computes the MAC operations greater than 4 */\n    /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n    /* The first part of the stage starts here */\n    j = count >> 2u;\n\n    while((j > 0u) && (blockSize3 > 0))\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   \n         * with y[srcBLen - 1], y[srcBLen - 2] respectively */\n        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   \n         * with y[srcBLen - 3], y[srcBLen - 4] respectively */\n        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* For the next MAC operations, the pointer py is used without SIMD   \n       * So, py is incremented by 1 */\n      py = py + 1u;\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */\n        sum = __SMLALD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pIn2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n      j--;\n    }\n\n    /* The second part of the stage starts here */\n    /* SIMD is not used for the next MAC operations,   \n     * so pointer py is updated to read only one sample at a time */\n    py = py + 1u;\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum = __SMLALD(*px++, *py--, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t *pIn1 = pSrcA;                           /* inputA pointer */\n  q15_t *pIn2 = pSrcB;                           /* inputB pointer */\n  q63_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counters */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n    /* Loop to calculate convolution for output length number of values */\n    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)\n    {\n      /* Initialize sum with zero to carry on MAC operations */\n      sum = 0;\n\n      /* Loop to perform MAC operations according to convolution equation */\n      for (j = 0; j <= i; j++)\n      {\n        /* Check the array limitations */\n        if(((i - j) < srcBLen) && (j < srcALen))\n        {\n          /* z[i] += x[i-j] * y[j] */\n          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));\n        }\n      }\n\n      /* Store the output in the destination buffer */\n      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);\n    }\n    /* set status as ARM_SUCCESS as there are no argument errors */\n    status = ARM_MATH_SUCCESS;\n  }\n  return (status);\n\n#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)  */\n\n}\n\n/**   \n * @} end of PartialConv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_partial_q31.c    \n*    \n* Description:\tPartial convolution of Q31 sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup PartialConv    \n * @{    \n */\n\n/**    \n * @brief Partial convolution of Q31 sequences.    \n * @param[in]       *pSrcA points to the first input sequence.    \n * @param[in]       srcALen length of the first input sequence.    \n * @param[in]       *pSrcB points to the second input sequence.    \n * @param[in]       srcBLen length of the second input sequence.    \n * @param[out]      *pDst points to the location where the output result is written.    \n * @param[in]       firstIndex is the first output sample to start with.    \n * @param[in]       numPoints is the number of output points to be computed.    \n * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    \n *    \n * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n */\n\narm_status arm_conv_partial_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t *pIn1;                                   /* inputA pointer               */\n  q31_t *pIn2;                                   /* inputB pointer               */\n  q31_t *pOut = pDst;                            /* output pointer               */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */\n  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */\n  q31_t x0, x1, x2, c0;\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */\n  arm_status status;                             /* status of Partial convolution */\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds    \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally    \n     * divided into three stages according to the number of multiplications that has to be    \n     * taken place between inputA samples and inputB samples. In the first stage of the    \n     * algorithm, the multiplications increase by one for every iteration.    \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n     * In the third stage of the algorithm, the multiplications decrease by one    \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex    \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------    \n     * Initializations of stage1    \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]    \n     * sum = x[0] * y[1] + x[1] * y[0]    \n     * ....    \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.    \n       The count variable holds the number of MAC operations performed.    \n       Since the partial convolution starts from firstIndex    \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------    \n     * Stage1 process    \n     * ----------------------*/\n\n    /* The first loop starts here */\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[0] * y[srcBLen - 1] */\n        sum += (q63_t) * px++ * (*py--);\n        /* x[1] * y[srcBLen - 2] */\n        sum += (q63_t) * px++ * (*py--);\n        /* x[2] * y[srcBLen - 3] */\n        sum += (q63_t) * px++ * (*py--);\n        /* x[3] * y[srcBLen - 4] */\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q31_t) (sum >> 31);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------    \n     * Initializations of stage2    \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n     * ....    \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n    /* -------------------    \n     * Stage2 process    \n     * ------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n     * So, to loop unroll over blockSize2,    \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blkCnt */\n\n      blkCnt = blockSize2 / 3;\n      while(blkCnt > 0u)\n      {\n        /* Set all accumulators to zero */\n        acc0 = 0;\n        acc1 = 0;\n        acc2 = 0;\n\n        /* read x[0], x[1] samples */\n        x0 = *(px++);\n        x1 = *(px++);\n\n        /* Apply loop unrolling and compute 3 MACs simultaneously. */\n        k = srcBLen / 3;\n\n        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        \n         ** a second loop below computes MACs for the remaining 1 to 2 samples. */\n        do\n        {\n          /* Read y[srcBLen - 1] sample */\n          c0 = *(py);\n\n          /* Read x[2] sample */\n          x2 = *(px);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[0] * y[srcBLen - 1] */\n          acc0 += (q63_t) x0 *c0;\n          /* acc1 +=  x[1] * y[srcBLen - 1] */\n          acc1 += (q63_t) x1 *c0;\n          /* acc2 +=  x[2] * y[srcBLen - 1] */\n          acc2 += (q63_t) x2 *c0;\n\n          /* Read y[srcBLen - 2] sample */\n          c0 = *(py - 1u);\n\n          /* Read x[3] sample */\n          x0 = *(px + 1u);\n\n          /* Perform the multiply-accumulate */\n          /* acc0 +=  x[1] * y[srcBLen - 2] */\n          acc0 += (q63_t) x1 *c0;\n          /* acc1 +=  x[2] * y[srcBLen - 2] */\n          acc1 += (q63_t) x2 *c0;\n          /* acc2 +=  x[3] * y[srcBLen - 2] */\n          acc2 += (q63_t) x0 *c0;\n\n          /* Read y[srcBLen - 3] sample */\n          c0 = *(py - 2u);\n\n          /* Read x[4] sample */\n          x1 = *(px + 2u);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[2] * y[srcBLen - 3] */\n          acc0 += (q63_t) x2 *c0;\n          /* acc1 +=  x[3] * y[srcBLen - 2] */\n          acc1 += (q63_t) x0 *c0;\n          /* acc2 +=  x[4] * y[srcBLen - 2] */\n          acc2 += (q63_t) x1 *c0;\n\n\n          px += 3u;\n\n          py -= 3u;\n\n        } while(--k);\n\n        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        \n         ** No loop unrolling is used. */\n        k = srcBLen - (3 * (srcBLen / 3));\n\n        while(k > 0u)\n        {\n          /* Read y[srcBLen - 5] sample */\n          c0 = *(py--);\n\n          /* Read x[7] sample */\n          x2 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[4] * y[srcBLen - 5] */\n          acc0 += (q63_t) x0 *c0;\n          /* acc1 +=  x[5] * y[srcBLen - 5] */\n          acc1 += (q63_t) x1 *c0;\n          /* acc2 +=  x[6] * y[srcBLen - 5] */\n          acc2 += (q63_t) x2 *c0;\n\n          /* Reuse the present samples for the next MAC */\n          x0 = x1;\n          x1 = x2;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q31_t) (acc0 >> 31);\n        *pOut++ = (q31_t) (acc1 >> 31);\n        *pOut++ = (q31_t) (acc2 >> 31);\n\n        /* Increment the pointer pIn1 index, count by 3 */\n        count += 3u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        \n       ** No loop unrolling is used. */\n      blkCnt = blockSize2 - 3 * (blockSize2 / 3);\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += (q63_t) * px++ * (*py--);\n          sum += (q63_t) * px++ * (*py--);\n          sum += (q63_t) * px++ * (*py--);\n          sum += (q63_t) * px++ * (*py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += (q63_t) * px++ * (*py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q31_t) (sum >> 31);\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,    \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += (q63_t) * px++ * (*py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q31_t) (sum >> 31);\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------    \n     * Initializations of stage3    \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n     * ....    \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n     * sum +=  x[srcALen-1] * y[srcBLen-1]    \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.    \n       The blockSize3 variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* -------------------    \n     * Stage3 process    \n     * ------------------*/\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q31_t) (sum >> 31);\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t *pIn1 = pSrcA;                           /* inputA pointer */\n  q31_t *pIn2 = pSrcB;                           /* inputB pointer */\n  q63_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counters */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n    /* Loop to calculate convolution for output length number of values */\n    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)\n    {\n      /* Initialize sum with zero to carry on MAC operations */\n      sum = 0;\n\n      /* Loop to perform MAC operations according to convolution equation */\n      for (j = 0; j <= i; j++)\n      {\n        /* Check the array limitations */\n        if(((i - j) < srcBLen) && (j < srcALen))\n        {\n          /* z[i] += x[i-j] * y[j] */\n          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));\n        }\n      }\n\n      /* Store the output in the destination buffer */\n      pDst[i] = (q31_t) (sum >> 31u);\n    }\n    /* set status as ARM_SUCCESS as there are no argument errors */\n    status = ARM_MATH_SUCCESS;\n  }\n  return (status);\n\n#endif /*    #ifndef ARM_MATH_CM0_FAMILY      */\n\n}\n\n/**    \n * @} end of PartialConv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_partial_q7.c   \n*   \n* Description:\tPartial convolution of Q7 sequences.   \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup PartialConv   \n * @{   \n */\n\n/**   \n * @brief Partial convolution of Q7 sequences.   \n * @param[in]       *pSrcA points to the first input sequence.   \n * @param[in]       srcALen length of the first input sequence.   \n * @param[in]       *pSrcB points to the second input sequence.   \n * @param[in]       srcBLen length of the second input sequence.   \n * @param[out]      *pDst points to the location where the output result is written.   \n * @param[in]       firstIndex is the first output sample to start with.   \n * @param[in]       numPoints is the number of output points to be computed.   \n * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   \n *  \n * \\par    \n * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.\n *  \n */\n\narm_status arm_conv_partial_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t *pIn1;                                    /* inputA pointer */\n  q7_t *pIn2;                                    /* inputB pointer */\n  q7_t *pOut = pDst;                             /* output pointer */\n  q7_t *px;                                      /* Intermediate inputA pointer */\n  q7_t *py;                                      /* Intermediate inputB pointer */\n  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q31_t input1, input2;\n  q15_t in1, in2;\n  q7_t x0, x1, x2, x3, c0, c1;\n  uint32_t j, k, count, check, blkCnt;\n  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */\n  arm_status status;\n\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_MATH_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n\n    /* The algorithm implementation is based on the lengths of the inputs. */\n    /* srcB is always made to slide across srcA. */\n    /* So srcBLen is always considered as shorter or equal to srcALen */\n    if(srcALen >= srcBLen)\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcA;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcB;\n    }\n    else\n    {\n      /* Initialization of inputA pointer */\n      pIn1 = pSrcB;\n\n      /* Initialization of inputB pointer */\n      pIn2 = pSrcA;\n\n      /* srcBLen is always considered as shorter or equal to srcALen */\n      j = srcBLen;\n      srcBLen = srcALen;\n      srcALen = j;\n    }\n\n    /* Conditions to check which loopCounter holds   \n     * the first and last indices of the output samples to be calculated. */\n    check = firstIndex + numPoints;\n    blockSize3 = ((int32_t) check - (int32_t) srcALen);\n    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;\n    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);\n    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :\n                                     (int32_t) numPoints) : 0;\n    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +\n                                    (int32_t) firstIndex);\n    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;\n\n    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n    /* The function is internally   \n     * divided into three stages according to the number of multiplications that has to be   \n     * taken place between inputA samples and inputB samples. In the first stage of the   \n     * algorithm, the multiplications increase by one for every iteration.   \n     * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n     * In the third stage of the algorithm, the multiplications decrease by one   \n     * for every iteration. */\n\n    /* Set the output pointer to point to the firstIndex   \n     * of the output sample to be calculated. */\n    pOut = pDst + firstIndex;\n\n    /* --------------------------   \n     * Initializations of stage1   \n     * -------------------------*/\n\n    /* sum = x[0] * y[0]   \n     * sum = x[0] * y[1] + x[1] * y[0]   \n     * ....   \n     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n     */\n\n    /* In this stage the MAC operations are increased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed.   \n       Since the partial convolution starts from from firstIndex   \n       Number of Macs to be performed is firstIndex + 1 */\n    count = 1u + firstIndex;\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + firstIndex;\n    py = pSrc2;\n\n    /* ------------------------   \n     * Stage1 process   \n     * ----------------------*/\n\n    /* The first stage starts here */\n    while(blockSize1 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* x[0] , x[1] */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* y[srcBLen - 1] , y[srcBLen - 2] */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* x[0] * y[srcBLen - 1] */\n        /* x[1] * y[srcBLen - 2] */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* x[2] , x[3] */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* y[srcBLen - 3] , y[srcBLen - 4] */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* x[2] * y[srcBLen - 3] */\n        /* x[3] * y[srcBLen - 4] */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      py = ++pSrc2;\n      px = pIn1;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Decrement the loop counter */\n      blockSize1--;\n    }\n\n    /* --------------------------   \n     * Initializations of stage2   \n     * ------------------------*/\n\n    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n     * ....   \n     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n     */\n\n    /* Working pointer of inputA */\n    px = pIn1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* count is index by which the pointer pIn1 to be incremented */\n    count = 0u;\n\n    /* -------------------   \n     * Stage2 process   \n     * ------------------*/\n\n    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n     * So, to loop unroll over blockSize2,   \n     * srcBLen should be greater than or equal to 4 */\n    if(srcBLen >= 4u)\n    {\n      /* Loop unroll over blockSize2, by 4 */\n      blkCnt = ((uint32_t) blockSize2 >> 2u);\n\n      while(blkCnt > 0u)\n      {\n        /* Set all accumulators to zero */\n        acc0 = 0;\n        acc1 = 0;\n        acc2 = 0;\n        acc3 = 0;\n\n        /* read x[0], x[1], x[2] samples */\n        x0 = *(px++);\n        x1 = *(px++);\n        x2 = *(px++);\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        do\n        {\n          /* Read y[srcBLen - 1] sample */\n          c0 = *(py--);\n          /* Read y[srcBLen - 2] sample */\n          c1 = *(py--);\n\n          /* Read x[3] sample */\n          x3 = *(px++);\n\n          /* x[0] and x[1] are packed */\n          in1 = (q15_t) x0;\n          in2 = (q15_t) x1;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */\n          in1 = (q15_t) c0;\n          in2 = (q15_t) c1;\n\n          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */\n          acc0 = __SMLAD(input1, input2, acc0);\n\n          /* x[1] and x[2] are packed */\n          in1 = (q15_t) x1;\n          in2 = (q15_t) x2;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */\n          acc1 = __SMLAD(input1, input2, acc1);\n\n          /* x[2] and x[3] are packed */\n          in1 = (q15_t) x2;\n          in2 = (q15_t) x3;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */\n          acc2 = __SMLAD(input1, input2, acc2);\n\n          /* Read x[4] sample */\n          x0 = *(px++);\n\n          /* x[3] and x[4] are packed */\n          in1 = (q15_t) x3;\n          in2 = (q15_t) x0;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */\n          acc3 = __SMLAD(input1, input2, acc3);\n\n          /* Read y[srcBLen - 3] sample */\n          c0 = *(py--);\n          /* Read y[srcBLen - 4] sample */\n          c1 = *(py--);\n\n          /* Read x[5] sample */\n          x1 = *(px++);\n\n          /* x[2] and x[3] are packed */\n          in1 = (q15_t) x2;\n          in2 = (q15_t) x3;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */\n          in1 = (q15_t) c0;\n          in2 = (q15_t) c1;\n\n          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */\n          acc0 = __SMLAD(input1, input2, acc0);\n\n          /* x[3] and x[4] are packed */\n          in1 = (q15_t) x3;\n          in2 = (q15_t) x0;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */\n          acc1 = __SMLAD(input1, input2, acc1);\n\n          /* x[4] and x[5] are packed */\n          in1 = (q15_t) x0;\n          in2 = (q15_t) x1;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */\n          acc2 = __SMLAD(input1, input2, acc2);\n\n          /* Read x[6] sample */\n          x2 = *(px++);\n\n          /* x[5] and x[6] are packed */\n          in1 = (q15_t) x1;\n          in2 = (q15_t) x2;\n\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */\n          acc3 = __SMLAD(input1, input2, acc3);\n\n        } while(--k);\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Read y[srcBLen - 5] sample */\n          c0 = *(py--);\n\n          /* Read x[7] sample */\n          x3 = *(px++);\n\n          /* Perform the multiply-accumulates */\n          /* acc0 +=  x[4] * y[srcBLen - 5] */\n          acc0 += ((q31_t) x0 * c0);\n          /* acc1 +=  x[5] * y[srcBLen - 5] */\n          acc1 += ((q31_t) x1 * c0);\n          /* acc2 +=  x[6] * y[srcBLen - 5] */\n          acc2 += ((q31_t) x2 * c0);\n          /* acc3 +=  x[7] * y[srcBLen - 5] */\n          acc3 += ((q31_t) x3 * c0);\n\n          /* Reuse the present samples for the next MAC */\n          x0 = x1;\n          x1 = x2;\n          x2 = x3;\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));\n        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));\n        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));\n        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));\n\n        /* Increment the pointer pIn1 index, count by 4 */\n        count += 4u;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n\n      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n       ** No loop unrolling is used. */\n      blkCnt = (uint32_t) blockSize2 % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        k = srcBLen >> 2u;\n\n        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n         ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n        while(k > 0u)\n        {\n\n          /* Reading two inputs of SrcA buffer and packing */\n          in1 = (q15_t) * px++;\n          in2 = (q15_t) * px++;\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* Reading two inputs of SrcB buffer and packing */\n          in1 = (q15_t) * py--;\n          in2 = (q15_t) * py--;\n          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* Perform the multiply-accumulates */\n          sum = __SMLAD(input1, input2, sum);\n\n          /* Reading two inputs of SrcA buffer and packing */\n          in1 = (q15_t) * px++;\n          in2 = (q15_t) * px++;\n          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* Reading two inputs of SrcB buffer and packing */\n          in1 = (q15_t) * py--;\n          in2 = (q15_t) * py--;\n          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n          /* Perform the multiply-accumulates */\n          sum = __SMLAD(input1, input2, sum);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n         ** No loop unrolling is used. */\n        k = srcBLen % 0x4u;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulates */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));\n\n        /* Increment the pointer pIn1 index, count by 1 */\n \t    count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n      \tpx = pIn1 + count;\n        py = pSrc2;\t\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n    else\n    {\n      /* If the srcBLen is not a multiple of 4,   \n       * the blockSize2 loop cannot be unrolled by 4 */\n      blkCnt = (uint32_t) blockSize2;\n\n      while(blkCnt > 0u)\n      {\n        /* Accumulator is made zero for every iteration */\n        sum = 0;\n\n        /* srcBLen number of MACS should be performed */\n        k = srcBLen;\n\n        while(k > 0u)\n        {\n          /* Perform the multiply-accumulate */\n          sum += ((q31_t) * px++ * *py--);\n\n          /* Decrement the loop counter */\n          k--;\n        }\n\n        /* Store the result in the accumulator in the destination buffer. */\n        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));\n\n        /* Increment the MAC count */\n        count++;\n\n        /* Update the inputA and inputB pointers for next MAC calculation */\n        px = pIn1 + count;\n        py = pSrc2;\n\n        /* Decrement the loop counter */\n        blkCnt--;\n      }\n    }\n\n\n    /* --------------------------   \n     * Initializations of stage3   \n     * -------------------------*/\n\n    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n     * ....   \n     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n     * sum +=  x[srcALen-1] * y[srcBLen-1]   \n     */\n\n    /* In this stage the MAC operations are decreased by 1 for every iteration.   \n       The count variable holds the number of MAC operations performed */\n    count = srcBLen - 1u;\n\n    /* Working pointer of inputA */\n    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n    px = pSrc1;\n\n    /* Working pointer of inputB */\n    pSrc2 = pIn2 + (srcBLen - 1u);\n    py = pSrc2;\n\n    /* -------------------   \n     * Stage3 process   \n     * ------------------*/\n\n    while(blockSize3 > 0)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = count >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the count is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = count % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n        sum += ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = ++pSrc1;\n      py = pSrc2;\n\n      /* Decrement the MAC count */\n      count--;\n\n      /* Decrement the loop counter */\n      blockSize3--;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q7_t *pIn1 = pSrcA;                            /* inputA pointer */\n  q7_t *pIn2 = pSrcB;                            /* inputB pointer */\n  q31_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counters */\n  arm_status status;                             /* status of Partial convolution */\n\n  /* Check for range of output samples to be calculated */\n  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))\n  {\n    /* Set status as ARM_ARGUMENT_ERROR */\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n    /* Loop to calculate convolution for output length number of values */\n    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)\n    {\n      /* Initialize sum with zero to carry on MAC operations */\n      sum = 0;\n\n      /* Loop to perform MAC operations according to convolution equation */\n      for (j = 0; j <= i; j++)\n      {\n        /* Check the array limitations */\n        if(((i - j) < srcBLen) && (j < srcALen))\n        {\n          /* z[i] += x[i-j] * y[j] */\n          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));\n        }\n      }\n\n      /* Store the output in the destination buffer */\n      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);\n    }\n    /* set status as ARM_SUCCESS as there are no argument errors */\n    status = ARM_MATH_SUCCESS;\n  }\n  return (status);\n\n#endif /*  #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**   \n * @} end of PartialConv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_q15.c   \n*   \n* Description:\tConvolution of Q15 sequences.     \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Conv   \n * @{   \n */\n\n/**   \n * @brief Convolution of Q15 sequences.   \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   \n * @return none.   \n *   \n * @details   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * The function is implemented using a 64-bit internal accumulator.   \n * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   \n * This approach provides 33 guard bits and there is no risk of overflow.   \n * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   \n *   \n * \\par   \n * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. \n *\n * \\par    \n * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.\n *  \n */\n\nvoid arm_conv_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst)\n{\n\n#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q15_t *pIn1;                                   /* inputA pointer */\n  q15_t *pIn2;                                   /* inputB pointer */\n  q15_t *pOut = pDst;                            /* output pointer */\n  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */\n  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally   \n   * divided into three stages according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first stage of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n   * In the third stage of the algorithm, the multiplications decrease by one   \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.   \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]   \n   * sum = x[0] * y[1] + x[1] * y[0]   \n   * ....   \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations less than 4 */\n  /* Second part of this stage computes the MAC operations greater than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  while((count < 4u) && (blockSize1 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Loop over number of MAC operations between   \n     * inputA samples and inputB samples */\n    k = count;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLALD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* The second part of the stage starts here */\n  /* The internal loop, over count, is unrolled by 4 */\n  /* To, read the last two inputB samples using SIMD:   \n   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */\n  py = py - 1;\n\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */\n      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */\n      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* For the next MAC operations, the pointer py is used without SIMD   \n     * So, py is incremented by 1 */\n    py = py + 1u;\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLALD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + (count - 1u);\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is the index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n\n  /* --------------------   \n   * Stage2 process   \n   * -------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      py = py - 1u;\n\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n\n      /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n      /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px+1);\n\t  px+= 2u;\n\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the last two inputB samples using SIMD:   \n         * y[srcBLen - 1] and y[srcBLen - 2] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */\n        acc0 = __SMLALDX(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */\n        acc1 = __SMLALDX(x1, c0, acc1);\n\n        /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n        /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px+1);\n\n        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */\n        acc2 = __SMLALDX(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */\n        acc3 = __SMLALDX(x3, c0, acc3);\n\n        /* Read y[srcBLen - 3] and y[srcBLen - 4] */\n        c0 = *__SIMD32(py)--;\n\n        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */\n        acc0 = __SMLALDX(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */\n        acc1 = __SMLALDX(x3, c0, acc1);\n\n        /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px+2);\n\n        /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px+3);\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */\n        acc2 = __SMLALDX(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */\n        acc3 = __SMLALDX(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[srcBLen - 5] */\n        c0 = *(py+1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n        /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALD(x0, c0, acc0);\n        acc1 = __SMLALD(x1, c0, acc1);\n        acc2 = __SMLALDX(x1, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x0, c0, acc0);\n        acc1 = __SMLALDX(x1, c0, acc1);\n        acc2 = __SMLALDX(x3, c0, acc2);\n        acc3 = __SMLALDX(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[srcBLen - 5], y[srcBLen - 6] */\n        c0 = _SIMD32_OFFSET(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px+1);\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x0, c0, acc0);\n        acc1 = __SMLALDX(x1, c0, acc1);\n        acc2 = __SMLALDX(x3, c0, acc2);\n        acc3 = __SMLALDX(x2, c0, acc3);\n\n\t\tc0 = *(py-1);\n\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n        /* Read x[10] */\n        x3 =  _SIMD32_OFFSET(px+2);\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x1, c0, acc0);\n        acc1 = __SMLALD(x2, c0, acc1);\n        acc2 = __SMLALDX(x2, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n\n      /* Store the results in the accumulators in the destination buffer. */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n      *__SIMD32(pOut)++ =\n        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n       /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) ((q31_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n   * sum +=  x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  blockSize3 = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  pIn2 = pSrc2 - 1u;\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  /* For loop unrolling by 4, this stage is divided into two. */\n  /* First part of this stage computes the MAC operations greater than 4 */\n  /* Second part of this stage computes the MAC operations less than or equal to 4 */\n\n  /* The first part of the stage starts here */\n  j = blockSize3 >> 2u;\n\n  while((j > 0u) && (blockSize3 > 0u))\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   \n       * with y[srcBLen - 1], y[srcBLen - 2] respectively */\n      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   \n       * with y[srcBLen - 3], y[srcBLen - 4] respectively */\n      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* For the next MAC operations, the pointer py is used without SIMD   \n     * So, py is incremented by 1 */\n    py = py + 1u;\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */\n      sum = __SMLALD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n\n    j--;\n  }\n\n  /* The second part of the stage starts here */\n  /* SIMD is not used for the next MAC operations,   \n   * so pointer py is updated to read only one sample at a time */\n  py = py + 1u;\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum +=  x[srcALen-1] * y[srcBLen-1] */\n      sum = __SMLALD(*px++, *py--, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  q15_t *pIn1 = pSrcA;                           /* input pointer */\n  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */\n  q63_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counter */\n\n  /* Loop to calculate output of convolution for output length number of times */\n  for (i = 0; i < (srcALen + srcBLen - 1); i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if(((i - j) < srcBLen) && (j < srcALen))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += (q31_t) pIn1[j] * (pIn2[i - j]);\n      }\n    }\n\n    /* Store the output in the destination buffer */\n    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);\n  }\n\n#endif /*  #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/\n\n}\n\n/**   \n * @} end of Conv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_conv_q31.c    \n*    \n* Description:\tConvolution of Q31 sequences.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Conv    \n * @{    \n */\n\n/**    \n * @brief Convolution of Q31 sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * There is no saturation on intermediate additions.    \n * Thus, if the accumulator overflows it wraps around and distorts the result.    \n * The input signals should be scaled down to avoid intermediate overflows.    \n * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    \n * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    \n * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    \n *    \n * \\par    \n * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_conv_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t *pIn1;                                   /* inputA pointer */\n  q31_t *pIn2;                                   /* inputB pointer */\n  q31_t *pOut = pDst;                            /* output pointer */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */\n  q63_t sum;                                     /* Accumulator */\n  q63_t acc0, acc1, acc2;                        /* Accumulator */\n  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */\n  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (q31_t *) pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = (q31_t *) pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally    \n   * divided into three stages according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first stage of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.    \n   * In the third stage of the algorithm, the multiplications decrease by one    \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.    \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * Initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]    \n   * sum = x[0] * y[1] + x[1] * y[0]    \n   * ....    \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 1] */\n      sum += (q63_t) * px++ * (*py--);\n      /* x[1] * y[srcBLen - 2] */\n      sum += (q63_t) * px++ * (*py--);\n      /* x[2] * y[srcBLen - 3] */\n      sum += (q63_t) * px++ * (*py--);\n      /* x[3] * y[srcBLen - 4] */\n      sum += (q63_t) * px++ * (*py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (q63_t) * px++ * (*py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q31_t) (sum >> 31);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll by 3 */\n    blkCnt = blockSize2 / 3;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n\n      /* Apply loop unrolling and compute 3 MACs simultaneously. */\n      k = srcBLen / 3;\n\n      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        \n       ** a second loop below computes MACs for the remaining 1 to 2 samples. */\n      do\n      {\n        /* Read y[srcBLen - 1] sample */\n        c0 = *(py);\n\n        /* Read x[3] sample */\n        x2 = *(px);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[0] * y[srcBLen - 1] */\n        acc0 += ((q63_t) x0 * c0);\n        /* acc1 +=  x[1] * y[srcBLen - 1] */\n        acc1 += ((q63_t) x1 * c0);\n        /* acc2 +=  x[2] * y[srcBLen - 1] */\n        acc2 += ((q63_t) x2 * c0);\n\n        /* Read y[srcBLen - 2] sample */\n        c0 = *(py - 1u);\n\n        /* Read x[4] sample */\n        x0 = *(px + 1u);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[1] * y[srcBLen - 2] */\n        acc0 += ((q63_t) x1 * c0);\n        /* acc1 +=  x[2] * y[srcBLen - 2] */\n        acc1 += ((q63_t) x2 * c0);\n        /* acc2 +=  x[3] * y[srcBLen - 2] */\n        acc2 += ((q63_t) x0 * c0);\n\n        /* Read y[srcBLen - 3] sample */\n        c0 = *(py - 2u);\n\n        /* Read x[5] sample */\n        x1 = *(px + 2u);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[srcBLen - 3] */\n        acc0 += ((q63_t) x2 * c0);\n        /* acc1 +=  x[3] * y[srcBLen - 2] */\n        acc1 += ((q63_t) x0 * c0);\n        /* acc2 +=  x[4] * y[srcBLen - 2] */\n        acc2 += ((q63_t) x1 * c0);\n\n        /* update scratch pointers */\n        px += 3u;\n        py -= 3u;\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        \n       ** No loop unrolling is used. */\n      k = srcBLen - (3 * (srcBLen / 3));\n\n      while(k > 0u)\n      {\n        /* Read y[srcBLen - 5] sample */\n        c0 = *(py--);\n\n        /* Read x[7] sample */\n        x2 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[srcBLen - 5] */\n        acc0 += ((q63_t) x0 * c0);\n        /* acc1 +=  x[5] * y[srcBLen - 5] */\n        acc1 += ((q63_t) x1 * c0);\n        /* acc2 +=  x[6] * y[srcBLen - 5] */\n        acc2 += ((q63_t) x2 * c0);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the results in the accumulators in the destination buffer. */\n      *pOut++ = (q31_t) (acc0 >> 31);\n      *pOut++ = (q31_t) (acc1 >> 31);\n      *pOut++ = (q31_t) (acc2 >> 31);\n\n      /* Increment the pointer pIn1 index, count by 3 */\n      count += 3u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 - 3 * (blockSize2 / 3);\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q31_t) (sum >> 31);\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q31_t) (sum >> 31);\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    \n   * sum +=  x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n      sum += (q63_t) * px++ * (*py--);\n      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n      sum += (q63_t) * px++ * (*py--);\n      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n      sum += (q63_t) * px++ * (*py--);\n      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n      sum += (q63_t) * px++ * (*py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (q63_t) * px++ * (*py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q31_t) (sum >> 31);\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t *pIn1 = pSrcA;                           /* input pointer */\n  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */\n  q63_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counter */\n\n  /* Loop to calculate output of convolution for output length number of times */\n  for (i = 0; i < (srcALen + srcBLen - 1); i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if(((i - j) < srcBLen) && (j < srcALen))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));\n      }\n    }\n\n    /* Store the output in the destination buffer */\n    pDst[i] = (q31_t) (sum >> 31u);\n  }\n\n#endif /*     #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of Conv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_conv_q7.c   \n*   \n* Description:\tConvolution of Q7 sequences. \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Conv   \n * @{   \n */\n\n/**   \n * @brief Convolution of Q7 sequences.   \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   \n * @return none.   \n *   \n * @details   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * The function is implemented using a 32-bit internal accumulator.   \n * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   \n * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   \n * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   \n *\n * \\par    \n * Refer the function arm_conv_opt_q7() for a faster implementation of this function.\n * \n */\n\nvoid arm_conv_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t *pIn1;                                    /* inputA pointer */\n  q7_t *pIn2;                                    /* inputB pointer */\n  q7_t *pOut = pDst;                             /* output pointer */\n  q7_t *px;                                      /* Intermediate inputA pointer */\n  q7_t *py;                                      /* Intermediate inputB pointer */\n  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */\n  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */\n  q31_t input1, input2;                          /* Temporary input variables */\n  q15_t in1, in2;                                /* Temporary input variables */\n  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n  }\n\n  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */\n  /* The function is internally   \n   * divided into three stages according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first stage of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second stage of the algorithm, srcBLen number of multiplications are done.   \n   * In the third stage of the algorithm, the multiplications decrease by one   \n   * for every iteration. */\n\n  /* The algorithm is implemented in three stages.   \n     The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = (srcALen - srcBLen) + 1u;\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[0]   \n   * sum = x[0] * y[1] + x[1] * y[0]   \n   * ....   \n   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] , x[1] */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* y[srcBLen - 1] , y[srcBLen - 2] */\n      in1 = (q15_t) * py--;\n      in2 = (q15_t) * py--;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* x[0] * y[srcBLen - 1] */\n      /* x[1] * y[srcBLen - 2] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* x[2] , x[3] */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* y[srcBLen - 3] , y[srcBLen - 4] */\n      in1 = (q15_t) * py--;\n      in2 = (q15_t) * py--;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* x[2] * y[srcBLen - 3] */\n      /* x[3] * y[srcBLen - 4] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += ((q15_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pIn2 + count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   \n   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------   \n   * Stage2 process   \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n      x2 = *(px++);\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[srcBLen - 1] sample */\n        c0 = *(py--);\n        /* Read y[srcBLen - 2] sample */\n        c1 = *(py--);\n\n        /* Read x[3] sample */\n        x3 = *(px++);\n\n        /* x[0] and x[1] are packed */\n        in1 = (q15_t) x0;\n        in2 = (q15_t) x1;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */\n        in1 = (q15_t) c0;\n        in2 = (q15_t) c1;\n\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */\n        acc0 = __SMLAD(input1, input2, acc0);\n\n        /* x[1] and x[2] are packed */\n        in1 = (q15_t) x1;\n        in2 = (q15_t) x2;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */\n        acc1 = __SMLAD(input1, input2, acc1);\n\n        /* x[2] and x[3] are packed */\n        in1 = (q15_t) x2;\n        in2 = (q15_t) x3;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */\n        acc2 = __SMLAD(input1, input2, acc2);\n\n        /* Read x[4] sample */\n        x0 = *(px++);\n\n        /* x[3] and x[4] are packed */\n        in1 = (q15_t) x3;\n        in2 = (q15_t) x0;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */\n        acc3 = __SMLAD(input1, input2, acc3);\n\n        /* Read y[srcBLen - 3] sample */\n        c0 = *(py--);\n        /* Read y[srcBLen - 4] sample */\n        c1 = *(py--);\n\n        /* Read x[5] sample */\n        x1 = *(px++);\n\n        /* x[2] and x[3] are packed */\n        in1 = (q15_t) x2;\n        in2 = (q15_t) x3;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */\n        in1 = (q15_t) c0;\n        in2 = (q15_t) c1;\n\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */\n        acc0 = __SMLAD(input1, input2, acc0);\n\n        /* x[3] and x[4] are packed */\n        in1 = (q15_t) x3;\n        in2 = (q15_t) x0;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */\n        acc1 = __SMLAD(input1, input2, acc1);\n\n        /* x[4] and x[5] are packed */\n        in1 = (q15_t) x0;\n        in2 = (q15_t) x1;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */\n        acc2 = __SMLAD(input1, input2, acc2);\n\n        /* Read x[6] sample */\n        x2 = *(px++);\n\n        /* x[5] and x[6] are packed */\n        in1 = (q15_t) x1;\n        in2 = (q15_t) x2;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */\n        acc3 = __SMLAD(input1, input2, acc3);\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[srcBLen - 5] sample */\n        c0 = *(py--);\n\n        /* Read x[7] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[srcBLen - 5] */\n        acc0 += ((q15_t) x0 * c0);\n        /* acc1 +=  x[5] * y[srcBLen - 5] */\n        acc1 += ((q15_t) x1 * c0);\n        /* acc2 +=  x[6] * y[srcBLen - 5] */\n        acc2 += ((q15_t) x2 * c0);\n        /* acc3 +=  x[7] * y[srcBLen - 5] */\n        acc3 += ((q15_t) x3 * c0);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));\n      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));\n      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));\n      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n\n        /* Reading two inputs of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* Reading two inputs of SrcB buffer and packing */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Reading two inputs of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* Reading two inputs of SrcB buffer and packing */\n        in1 = (q15_t) * py--;\n        in2 = (q15_t) * py--;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q15_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* srcBLen number of MACS should be performed */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q15_t) * px++ * *py--);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pSrc2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   \n   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   \n   * sum +=  x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The blockSize3 variable holds the number of MAC operations performed */\n\n  /* Working pointer of inputA */\n  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  pSrc2 = pIn2 + (srcBLen - 1u);\n  py = pSrc2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = blockSize3 >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */\n      in1 = (q15_t) * py--;\n      in2 = (q15_t) * py--;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */\n      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */\n      in1 = (q15_t) * py--;\n      in2 = (q15_t) * py--;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);\n\n      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */\n      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = blockSize3 % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += ((q15_t) * px++ * *py--);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pSrc2;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q7_t *pIn1 = pSrcA;                            /* input pointer */\n  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */\n  q31_t sum;                                     /* Accumulator */\n  uint32_t i, j;                                 /* loop counter */\n\n  /* Loop to calculate output of convolution for output length number of times */\n  for (i = 0; i < (srcALen + srcBLen - 1); i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if(((i - j) < srcBLen) && (j < srcALen))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += (q15_t) pIn1[j] * (pIn2[i - j]);\n      }\n    }\n\n    /* Store the output in the destination buffer */\n    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */\n\n}\n\n/**   \n * @} end of Conv group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_f32.c    \n*    \n* Description:\t Correlation of floating-point sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup Corr Correlation    \n *    \n * Correlation is a mathematical operation that is similar to convolution.    \n * As with convolution, correlation uses two signals to produce a third signal.    \n * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.    \n * Correlation is commonly used to measure the similarity between two signals.    \n * It has applications in pattern recognition, cryptanalysis, and searching.    \n * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.    \n * Fast versions of the Q15 and Q31 functions are also provided.    \n *    \n * \\par Algorithm    \n * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    \n * The convolution of the two signals is denoted by    \n * 
    \n *                   c[n] = a[n] * b[n]    \n * 
    \n * In correlation, one of the signals is flipped in time    \n * 
    \n *                   c[n] = a[n] * b[-n]    \n * 
    \n *    \n * \\par    \n * and this is mathematically defined as    \n * \\image html CorrelateEquation.gif    \n * \\par    \n * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.    \n * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).    \n * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.    \n *    \n * Note   \n * \\par  \n * The pDst should be initialized to all zeros before being used.  \n *  \n * Fixed-Point Behavior    \n * \\par    \n * Correlation requires summing up a large number of intermediate products.    \n * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    \n * Refer to the function specific documentation below for further details of the particular algorithm used.    \n *\n *\n * Fast Versions\n *\n * \\par \n * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires\n * the input signals should be scaled down to avoid intermediate overflows.   \n *\n *\n * Opt Versions\n *\n * \\par \n * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.\n * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n/**    \n * @brief Correlation of floating-point sequences.    \n * @param[in]  *pSrcA points to the first input sequence.    \n * @param[in]  srcALen length of the first input sequence.    \n * @param[in]  *pSrcB points to the second input sequence.    \n * @param[in]  srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @return none.    \n */\n\nvoid arm_correlate_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t *pIn1;                               /* inputA pointer */\n  float32_t *pIn2;                               /* inputB pointer */\n  float32_t *pOut = pDst;                        /* output pointer */\n  float32_t *px;                                 /* Intermediate inputA pointer */\n  float32_t *py;                                 /* Intermediate inputB pointer */\n  float32_t *pSrc1;                              /* Intermediate pointers */\n  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */\n  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */\n  int32_t inc = 1;                               /* Destination address modifier */\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,    \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,    \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,    \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcA;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcB;\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding has to be done to srcB    \n     * to make their lengths equal.    \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n    //while(j > 0u)   \n    //{   \n    //  /* Zero is stored in the destination buffer */   \n    //  *pOut++ = 0.0f;   \n\n    //  /* Decrement the loop counter */   \n    //  j--;   \n    //}   \n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization of inputB pointer */\n    pIn2 = pSrcA;\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally    \n   * divided into three parts according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first part of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second part of the algorithm, srcBLen number of multiplications are done.    \n   * In the third part of the algorithm, the multiplications decrease by one    \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.    \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * Initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]    \n   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]    \n   * ....    \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0.0f;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] */\n      sum += *px++ * *py++;\n      /* x[1] * y[srcBLen - 3] */\n      sum += *px++ * *py++;\n      /* x[2] * y[srcBLen - 2] */\n      sum += *px++ * *py++;\n      /* x[3] * y[srcBLen - 1] */\n      sum += *px++ * *py++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      /* x[0] * y[srcBLen - 1] */\n      sum += *px++ * *py++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = sum;\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0.0f;\n      acc1 = 0.0f;\n      acc2 = 0.0f;\n      acc3 = 0.0f;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n      x2 = *(px++);\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[0] sample */\n        c0 = *(py++);\n\n        /* Read x[3] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[0] * y[0] */\n        acc0 += x0 * c0;\n        /* acc1 +=  x[1] * y[0] */\n        acc1 += x1 * c0;\n        /* acc2 +=  x[2] * y[0] */\n        acc2 += x2 * c0;\n        /* acc3 +=  x[3] * y[0] */\n        acc3 += x3 * c0;\n\n        /* Read y[1] sample */\n        c0 = *(py++);\n\n        /* Read x[4] sample */\n        x0 = *(px++);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[1] * y[1] */\n        acc0 += x1 * c0;\n        /* acc1 +=  x[2] * y[1] */\n        acc1 += x2 * c0;\n        /* acc2 +=  x[3] * y[1] */\n        acc2 += x3 * c0;\n        /* acc3 +=  x[4] * y[1] */\n        acc3 += x0 * c0;\n\n        /* Read y[2] sample */\n        c0 = *(py++);\n\n        /* Read x[5] sample */\n        x1 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[2] */\n        acc0 += x2 * c0;\n        /* acc1 +=  x[3] * y[2] */\n        acc1 += x3 * c0;\n        /* acc2 +=  x[4] * y[2] */\n        acc2 += x0 * c0;\n        /* acc3 +=  x[5] * y[2] */\n        acc3 += x1 * c0;\n\n        /* Read y[3] sample */\n        c0 = *(py++);\n\n        /* Read x[6] sample */\n        x2 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[3] * y[3] */\n        acc0 += x3 * c0;\n        /* acc1 +=  x[4] * y[3] */\n        acc1 += x0 * c0;\n        /* acc2 +=  x[5] * y[3] */\n        acc2 += x1 * c0;\n        /* acc3 +=  x[6] * y[3] */\n        acc3 += x2 * c0;\n\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[4] sample */\n        c0 = *(py++);\n\n        /* Read x[7] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[4] */\n        acc0 += x0 * c0;\n        /* acc1 +=  x[5] * y[4] */\n        acc1 += x1 * c0;\n        /* acc2 +=  x[6] * y[4] */\n        acc2 += x2 * c0;\n        /* acc3 +=  x[7] * y[4] */\n        acc3 += x3 * c0;\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = acc0;\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = acc1;\n      pOut += inc;\n\n      *pOut = acc2;\n      pOut += inc;\n\n      *pOut = acc3;\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += *px++ * *py++;\n        sum += *px++ * *py++;\n        sum += *px++ * *py++;\n        sum += *px++ * *py++;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += *px++ * *py++;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = sum;\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0.0f;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += *px++ * *py++;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = sum;\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    \n   * sum +=  x[srcALen-1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0.0f;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] */\n      sum += *px++ * *py++;\n      /* sum += x[srcALen - srcBLen + 3] * y[2] */\n      sum += *px++ * *py++;\n      /* sum += x[srcALen - srcBLen + 2] * y[1] */\n      sum += *px++ * *py++;\n      /* sum += x[srcALen - srcBLen + 1] * y[0] */\n      sum += *px++ * *py++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += *px++ * *py++;\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = sum;\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t *pIn1 = pSrcA;                       /* inputA pointer */\n  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */\n  float32_t sum;                                 /* Accumulator */\n  uint32_t i = 0u, j;                            /* loop counters */\n  uint32_t inv = 0u;                             /* Reverse order flag */\n  uint32_t tot = 0u;                             /* Length */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and a varaible, inv is set to 1 */\n  /* If lengths are not equal then zero pad has to be done to  make the two    \n   * inputs of same length. But to improve the performance, we include zeroes    \n   * in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    \n   * starting of the output buffer */\n  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   \n   * ending of the output buffer */\n  /* Once the zero padding is done the remaining of the output is calcualted   \n   * using convolution but with the shorter signal time shifted. */\n\n  /* Calculate the length of the remaining sequence */\n  tot = ((srcALen + srcBLen) - 2u);\n\n  if(srcALen > srcBLen)\n  {\n    /* Calculating the number of zeros to be padded to the output */\n    j = srcALen - srcBLen;\n\n    /* Initialise the pointer after zero padding */\n    pDst += j;\n  }\n\n  else if(srcALen < srcBLen)\n  {\n    /* Initialization to inputB pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization to the end of inputA pointer */\n    pIn2 = pSrcA + (srcALen - 1u);\n\n    /* Initialisation of the pointer after zero padding */\n    pDst = pDst + tot;\n\n    /* Swapping the lengths */\n    j = srcALen;\n    srcALen = srcBLen;\n    srcBLen = j;\n\n    /* Setting the reverse flag */\n    inv = 1;\n\n  }\n\n  /* Loop to calculate convolution for output length number of times */\n  for (i = 0u; i <= tot; i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0.0f;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0u; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if((((i - j) < srcBLen) && (j < srcALen)))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += pIn1[j] * pIn2[-((int32_t) i - j)];\n      }\n    }\n    /* Store the output in the destination buffer */\n    if(inv == 1)\n      *pDst-- = sum;\n    else\n      *pDst++ = sum;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_fast_opt_q15.c    \n*    \n* Description:\tFast Q15 Correlation.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n\n/**    \n * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   \n * @return none.    \n *    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch buffers should be aligned by 32-bit    \n *    \n *     \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This fast version uses a 32-bit accumulator with 2.30 format.    \n * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * There is no saturation on intermediate additions.    \n * Thus, if the accumulator overflows it wraps around and distorts the result.    \n * The input signals should be scaled down to avoid intermediate overflows.    \n * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a    \n * maximum of min(srcALen, srcBLen) number of additions is carried internally.    \n * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    \n *    \n * \\par    \n * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    \n */\n\nvoid arm_correlate_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch)\n{\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */\n  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n  uint32_t tapCnt;\n  q31_t y1, y2;\n  q15_t *pScr;                                   /* Intermediate pointers        */\n  q15_t *pOut = pDst;                            /* output pointer               */\n#ifdef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t a, b;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,        \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB        \n     * to make their lengths equal.        \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  pScr = pScratch;\n\n  /* Fill (srcBLen - 1u) zeros in scratch buffer */\n  arm_fill_q15(0, pScr, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr += (srcBLen - 1u);\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Copy (srcALen) samples in scratch buffer */\n  arm_copy_q15(pIn1, pScr, srcALen);\n\n  /* Update pointers */\n  pScr += srcALen;\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  j = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  j = srcALen % 0x4u;\n\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr += (srcBLen - 1u);\n\n#else\n\n/* Apply loop unrolling and do 4 Copies simultaneously. */\n  j = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr++ = 0;\n    *pScr++ = 0;\n    *pScr++ = 0;\n    *pScr++ = 0;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  j = (srcBLen - 1u) % 0x4u;\n\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr++ = 0;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* Temporary pointer for scratch2 */\n  py = pIn2;\n\n\n  /* Actual correlation process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr = pScratch;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read four samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr)++;\n\n    /* Read next four samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pIn2);\n      y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n      acc0 = __SMLAD(x1, y1, acc0);\n\n      acc2 = __SMLAD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      x1 = _SIMD32_OFFSET(pScr);\n\n      acc0 = __SMLAD(x2, y2, acc0);\n\n      acc2 = __SMLAD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      acc1 = __SMLADX(x3, y2, acc1);\n\n      x2 = _SIMD32_OFFSET(pScr + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y2, acc3);\n#else\t \n\n      /* Read four samples from smaller buffer */\n\t  a = *pIn2;\n\t  b = *(pIn2 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      y1 = __PKHBT(a, b, 16);\n#else\n      y1 = __PKHBT(b, a, 16);\n#endif\n\t  \n\t  a = *(pIn2 + 2);\n\t  b = *(pIn2 + 3);\n#ifndef ARM_MATH_BIG_ENDIAN\n      y2 = __PKHBT(a, b, 16);\n#else\n      y2 = __PKHBT(b, a, 16);\n#endif\t\t\t\t\n\n      acc0 = __SMLAD(x1, y1, acc0);\n\n      acc2 = __SMLAD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLADX(x3, y1, acc1);\n\n\t  a = *pScr;\n\t  b = *(pScr + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(a, b, 16);\n#else\n      x1 = __PKHBT(b, a, 16);\n#endif\n\n      acc0 = __SMLAD(x2, y2, acc0);\n\n      acc2 = __SMLAD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      acc1 = __SMLADX(x3, y2, acc1);\n\n\t  a = *(pScr + 2);\n\t  b = *(pScr + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x2 = __PKHBT(a, b, 16);\n#else\n      x2 = __PKHBT(b, a, 16);\n#endif\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y2, acc3);\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      pIn2 += 4u;\n\n      pScr += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr -= 4u;\n\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr++ * *pIn2);\n      acc1 += (*pScr++ * *pIn2);\n      acc2 += (*pScr++ * *pIn2);\n      acc3 += (*pScr++ * *pIn2++);\n\n      pScr -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n\n    /* Store the results in the accumulators in the destination buffer. */\n    *pOut = (__SSAT(acc0 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc1 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc2 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc3 >> 15u, 16));\n    pOut += inc;\n\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate correlation for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr = pScratch;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n\n      acc0 += (*pScr++ * *pIn2++);\n      acc0 += (*pScr++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n\n    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    pOut += inc;\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch += 1u;\n\n  }\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_correlate_fast_q15.c   \n*   \n* Description:\tFast Q15 Correlation.   \n*   \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Corr   \n * @{   \n */\n\n/**   \n * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   \n * @return none.   \n *   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * This fast version uses a 32-bit accumulator with 2.30 format.   \n * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   \n * There is no saturation on intermediate additions.   \n * Thus, if the accumulator overflows it wraps around and distorts the result.   \n * The input signals should be scaled down to avoid intermediate overflows.   \n * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   \n * maximum of min(srcALen, srcBLen) number of additions is carried internally.   \n * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   \n *   \n * \\par   \n * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   \n */\n\nvoid arm_correlate_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst)\n{\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1;                                  /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,   \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB   \n     * to make their lengths equal.   \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally   \n   * divided into three parts according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first part of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second part of the algorithm, srcBLen number of multiplications are done.   \n   * In the third part of the algorithm, the multiplications decrease by one   \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.   \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]   \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   \n   * ....   \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* The first loop starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */\n      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */\n      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n      sum = __SMLAD(*px++, *py++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (sum >> 15);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------   \n   * Stage2 process   \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n      /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px + 1);\n\t  px += 2u;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the first two inputB samples using SIMD:   \n         * y[0] and y[1] */\n        c0 = *__SIMD32(py)++;\n\n        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */\n        acc0 = __SMLAD(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */\n        acc1 = __SMLAD(x1, c0, acc1);\n\n        /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n        /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px + 1);\n\n        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */\n        acc2 = __SMLAD(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */\n        acc3 = __SMLAD(x3, c0, acc3);\n\n        /* Read y[2] and y[3] */\n        c0 = *__SIMD32(py)++;\n\n        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */\n        acc0 = __SMLAD(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */\n        acc1 = __SMLAD(x3, c0, acc1);\n\n        /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px + 2);\n\n        /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px + 3);\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */\n        acc2 = __SMLAD(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */\n        acc3 = __SMLAD(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[4] */\n        c0 = *py;\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLADX(x1, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[4], y[5] */\n        c0 = *__SIMD32(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px + 1);\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLAD(x3, c0, acc2);\n        acc3 = __SMLAD(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[4], y[5] */\n        c0 = *__SIMD32(py)++;\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px + 1);\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLAD(x3, c0, acc2);\n        acc3 = __SMLAD(x2, c0, acc3);\n\n        c0 = (*py);\n        /* Read y[6] */\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n        x3 = _SIMD32_OFFSET(px + 2);\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x1, c0, acc0);\n        acc1 = __SMLAD(x2, c0, acc1);\n        acc2 = __SMLADX(x2, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (acc0 >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q15_t) (acc1 >> 15);\n      pOut += inc;\n\n      *pOut = (q15_t) (acc2 >> 15);\n      pOut += inc;\n\n      *pOut = (q15_t) (acc3 >> 15);\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (sum >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (sum >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   \n   * sum +=  x[srcALen-1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */\n      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */\n      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLAD(*px++, *py++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (sum >> 15);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1;                                  /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n  q15_t a, b;\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,   \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB   \n     * to make their lengths equal.   \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally   \n   * divided into three parts according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first part of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second part of the algorithm, srcBLen number of multiplications are done.   \n   * In the third part of the algorithm, the multiplications decrease by one   \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.   \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]   \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   \n   * ....   \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* The first loop starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n        sum += ((q31_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (sum >> 15);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------   \n   * Stage2 process   \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n\t  a = *px;\n\t  b = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  x0 = __PKHBT(a, b, 16);\n\t  a = *(px + 2);\n\t  x1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  x0 = __PKHBT(b, a, 16);\n\t  a = *(px + 2);\n\t  x1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t  px += 2u;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the first two inputB samples using SIMD:   \n         * y[0] and y[1] */\n\t\t  a = *py;\n\t\t  b = *(py + 1);\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\t  c0 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\t  c0 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */\n        acc0 = __SMLAD(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */\n        acc1 = __SMLAD(x1, c0, acc1);\n\n        /* Read x[2], x[3], x[4] */\n\t  \ta = *px;\n\t  \tb = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  \tx2 = __PKHBT(a, b, 16);\n\t  \ta = *(px + 2);\n\t  \tx3 = __PKHBT(b, a, 16);\n\n#else\n\n\t  \tx2 = __PKHBT(b, a, 16);\n\t  \ta = *(px + 2);\n\t  \tx3 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */\n        acc2 = __SMLAD(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */\n        acc3 = __SMLAD(x3, c0, acc3);\n\n        /* Read y[2] and y[3] */\n\t\t  a = *(py + 2);\n\t\t  b = *(py + 3);\n\n\t\t  py += 4u;\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\t  c0 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\t  c0 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */\n        acc0 = __SMLAD(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */\n        acc1 = __SMLAD(x3, c0, acc1);\n\n        /* Read x[4], x[5], x[6] */\n\t  \ta = *(px + 2);\n\t  \tb = *(px + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  \tx0 = __PKHBT(a, b, 16);\n\t  \ta = *(px + 4);\n\t  \tx1 = __PKHBT(b, a, 16);\n\n#else\n\n\t  \tx0 = __PKHBT(b, a, 16);\n\t  \ta = *(px + 4);\n\t  \tx1 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */\n        acc2 = __SMLAD(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */\n        acc3 = __SMLAD(x1, c0, acc3);\n\n      } while(--k);\n\n      /* For the next MAC operations, SIMD is not used   \n       * So, the 16 bit pointer if inputB, py is updated */\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[4] */\n        c0 = *py;\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[7] */\n\t\ta = *px;\n\t\tb = *(px + 1);\n\n\t\tpx++;;\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\tx3 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\tx3 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLADX(x1, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[4], y[5] */\n\t\t  a = *py;\n\t\t  b = *(py + 1);\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\t  c0 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\t  c0 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Read x[7], x[8], x[9] */\n\t  \ta = *px;\n\t  \tb = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  \tx3 = __PKHBT(a, b, 16);\n\t  \ta = *(px + 2);\n\t  \tx2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  \tx3 = __PKHBT(b, a, 16);\n\t  \ta = *(px + 2);\n\t  \tx2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLAD(x3, c0, acc2);\n        acc3 = __SMLAD(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[4], y[5] */\n\t\t  a = *py;\n\t\t  b = *(py + 1);\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\t  c0 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\t  c0 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpy += 2u;\n\n        /* Read x[7], x[8], x[9] */\n\t  \ta = *px;\n\t  \tb = *(px + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  \tx3 = __PKHBT(a, b, 16);\n\t  \ta = *(px + 2);\n\t  \tx2 = __PKHBT(b, a, 16);\n\n#else\n\n\t  \tx3 = __PKHBT(b, a, 16);\n\t  \ta = *(px + 2);\n\t  \tx2 = __PKHBT(a, b, 16);\n\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLAD(x0, c0, acc0);\n        acc1 = __SMLAD(x1, c0, acc1);\n        acc2 = __SMLAD(x3, c0, acc2);\n        acc3 = __SMLAD(x2, c0, acc3);\n\n        c0 = (*py);\n        /* Read y[6] */\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n\n        /* Read x[10] */\n\t\tb = *(px + 3);\n\t\n#ifndef ARM_MATH_BIG_ENDIAN\n\t\n\t\tx3 = __PKHBT(a, b, 16);\n\t\n#else\n\t\n\t\tx3 = __PKHBT(b, a, 16);\n\t\n#endif\t/*\t#ifndef ARM_MATH_BIG_ENDIAN\t*/\n\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLADX(x1, c0, acc0);\n        acc1 = __SMLAD(x2, c0, acc1);\n        acc2 = __SMLADX(x2, c0, acc2);\n        acc3 = __SMLADX(x3, c0, acc3);\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (acc0 >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q15_t) (acc1 >> 15);\n      pOut += inc;\n\n      *pOut = (q15_t) (acc2 >> 15);\n      pOut += inc;\n\n      *pOut = (q15_t) (acc3 >> 15);\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (sum >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q31_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (sum >> 15);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   \n   * sum +=  x[srcALen-1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n        sum += ((q31_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n        sum += ((q31_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (sum >> 15);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */\n\n}\n\n/**   \n * @} end of Corr group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_fast_q31.c    \n*    \n* Description:\tFast Q31 Correlation.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n\n/**    \n * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    \n * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    \n * These intermediate results are accumulated in a 32-bit register in 2.30 format.    \n * Finally, the accumulator is saturated and converted to a 1.31 result.    \n *    \n * \\par    \n * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signals must be scaled down.    \n * The input signals should be scaled down to avoid intermediate overflows.    \n * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    \n * maximum of min(srcALen, srcBLen) number of additions is carried internally.    \n *    \n * \\par    \n * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    \n */\n\nvoid arm_correlate_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst)\n{\n  q31_t *pIn1;                                   /* inputA pointer               */\n  q31_t *pIn2;                                   /* inputB pointer               */\n  q31_t *pOut = pDst;                            /* output pointer               */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1;                                  /* Intermediate pointers        */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB    \n     * to make their lengths equal.    \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally    \n   * divided into three parts according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first part of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second part of the algorithm, srcBLen number of multiplications are done.    \n   * In the third part of the algorithm, the multiplications decrease by one    \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.    \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * Initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]    \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    \n   * ....    \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* x[1] * y[srcBLen - 3] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* x[2] * y[srcBLen - 2] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* x[3] * y[srcBLen - 1] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = sum << 1;\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n      x2 = *(px++);\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[0] sample */\n        c0 = *(py++);\n\n        /* Read x[3] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[0] * y[0] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc1 +=  x[1] * y[0] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc2 +=  x[2] * y[0] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc3 +=  x[3] * y[0] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n        /* Read y[1] sample */\n        c0 = *(py++);\n\n        /* Read x[4] sample */\n        x0 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[1] * y[1] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc1 +=  x[2] * y[1] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc2 +=  x[3] * y[1] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc3 +=  x[4] * y[1] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n        /* Read y[2] sample */\n        c0 = *(py++);\n\n        /* Read x[5] sample */\n        x1 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[2] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc1 +=  x[3] * y[2] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc2 +=  x[4] * y[2] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc3 +=  x[5] * y[2] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n        /* Read y[3] sample */\n        c0 = *(py++);\n\n        /* Read x[6] sample */\n        x2 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[3] * y[3] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);\n        /* acc1 +=  x[4] * y[3] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc2 +=  x[5] * y[3] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc3 +=  x[6] * y[3] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);\n\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[4] sample */\n        c0 = *(py++);\n\n        /* Read x[7] sample */\n        x3 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[4] */\n        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n        /* acc1 +=  x[5] * y[4] */\n        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n        /* acc2 +=  x[6] * y[4] */\n        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);\n        /* acc3 +=  x[7] * y[4] */\n        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q31_t) (acc0 << 1);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q31_t) (acc1 << 1);\n      pOut += inc;\n\n      *pOut = (q31_t) (acc2 << 1);\n      pOut += inc;\n\n      *pOut = (q31_t) (acc3 << 1);\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 4 */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = sum << 1;\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum = (q31_t) ((((q63_t) sum << 32) +\n                        ((q63_t) * px++ * (*py++))) >> 32);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = sum << 1;\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    \n   * sum +=  x[srcALen-1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* sum += x[srcALen - srcBLen + 3] * y[2] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* sum += x[srcALen - srcBLen + 2] * y[1] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n      /* sum += x[srcALen - srcBLen + 1] * y[0] */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = (q31_t) ((((q63_t) sum << 32) +\n                      ((q63_t) * px++ * (*py++))) >> 32);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = sum << 1;\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_opt_q15.c    \n*    \n* Description:\tCorrelation of Q15 sequences.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n\n/**    \n * @brief Correlation of Q15 sequences.  \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    \n * @return none.    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch buffers should be aligned by 32-bit    \n *     \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * This approach provides 33 guard bits and there is no risk of overflow.    \n * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    \n *    \n * \\par    \n * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   \n *  \n * \n */\n\n\nvoid arm_correlate_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch)\n{\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */\n  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */\n  int32_t inc = 1;                               /* output pointer increment     */\n  uint32_t tapCnt;\n  q31_t y1, y2;\n  q15_t *pScr;                                   /* Intermediate pointers        */\n  q15_t *pOut = pDst;                            /* output pointer               */\n#ifdef UNALIGNED_SUPPORT_DISABLE\n\n  q15_t a, b;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,        \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB        \n     * to make their lengths equal.        \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  pScr = pScratch;\n\n  /* Fill (srcBLen - 1u) zeros in scratch buffer */\n  arm_fill_q15(0, pScr, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr += (srcBLen - 1u);\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Copy (srcALen) samples in scratch buffer */\n  arm_copy_q15(pIn1, pScr, srcALen);\n\n  /* Update pointers */\n  //pIn1 += srcALen;    \n  pScr += srcALen;\n\n#else\n\n  /* Apply loop unrolling and do 4 Copies simultaneously. */\n  j = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n    *pScr++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  j = srcALen % 0x4u;\n\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr++ = *pIn1++;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr += (srcBLen - 1u);\n\n#else\n\n/* Apply loop unrolling and do 4 Copies simultaneously. */\n  j = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr++ = 0;\n    *pScr++ = 0;\n    *pScr++ = 0;\n    *pScr++ = 0;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  j = (srcBLen - 1u) % 0x4u;\n\n  while(j > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr++ = 0;\n\n    /* Decrement the loop counter */\n    j--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* Temporary pointer for scratch2 */\n  py = pIn2;\n\n\n  /* Actual correlation process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr = pScratch;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read four samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr)++;\n\n    /* Read next four samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pIn2);\n      y2 = _SIMD32_OFFSET(pIn2 + 2u);\n\n      acc0 = __SMLALD(x1, y1, acc0);\n\n      acc2 = __SMLALD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLALDX(x3, y1, acc1);\n\n      x1 = _SIMD32_OFFSET(pScr);\n\n      acc0 = __SMLALD(x2, y2, acc0);\n\n      acc2 = __SMLALD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y1, acc3);\n\n      acc1 = __SMLALDX(x3, y2, acc1);\n\n      x2 = _SIMD32_OFFSET(pScr + 2u);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y2, acc3);\n\n#else\t \n\n      /* Read four samples from smaller buffer */\n\t  a = *pIn2;\n\t  b = *(pIn2 + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      y1 = __PKHBT(a, b, 16);\n#else\n      y1 = __PKHBT(b, a, 16);\n#endif\n\t  \n\t  a = *(pIn2 + 2);\n\t  b = *(pIn2 + 3);\n#ifndef ARM_MATH_BIG_ENDIAN\n      y2 = __PKHBT(a, b, 16);\n#else\n      y2 = __PKHBT(b, a, 16);\n#endif\t\t\t\t\n\n      acc0 = __SMLALD(x1, y1, acc0);\n\n      acc2 = __SMLALD(x2, y1, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc1 = __SMLALDX(x3, y1, acc1);\n\n\t  a = *pScr;\n\t  b = *(pScr + 1);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(a, b, 16);\n#else\n      x1 = __PKHBT(b, a, 16);\n#endif\n\n      acc0 = __SMLALD(x2, y2, acc0);\n\n      acc2 = __SMLALD(x1, y2, acc2);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y1, acc3);\n\n      acc1 = __SMLALDX(x3, y2, acc1);\n\n\t  a = *(pScr + 2);\n\t  b = *(pScr + 3);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x2 = __PKHBT(a, b, 16);\n#else\n      x2 = __PKHBT(b, a, 16);\n#endif\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLALDX(x3, y2, acc3);\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      pIn2 += 4u;\n\n      pScr += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr -= 4u;\n\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr++ * *pIn2);\n      acc1 += (*pScr++ * *pIn2);\n      acc2 += (*pScr++ * *pIn2);\n      acc3 += (*pScr++ * *pIn2++);\n\n      pScr -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n\n    /* Store the results in the accumulators in the destination buffer. */\n    *pOut = (__SSAT(acc0 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc1 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc2 >> 15u, 16));\n    pOut += inc;\n    *pOut = (__SSAT(acc3 >> 15u, 16));\n    pOut += inc;\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate correlation for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr = pScratch;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n\n      acc0 += (*pScr++ * *pIn2++);\n      acc0 += (*pScr++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr++ * *pIn2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    pOut += inc;\n\n    /* Initialization of inputB pointer */\n    pIn2 = py;\n\n    pScratch += 1u;\n\n  }\n\n\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_opt_q7.c    \n*    \n* Description:\tCorrelation of Q7 sequences.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n\n/**    \n * @brief Correlation of Q7 sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    \n * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    \n * @return none.    \n *    \n *    \n * \\par Restrictions    \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    \n *\tIn this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     \n *        \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.    \n * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    \n * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    \n * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.  \n *  \n * \n */\n\n\n\nvoid arm_correlate_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2)\n{\n  q7_t *pOut = pDst;                             /* output pointer                */\n  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */\n  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */\n  q7_t *pIn1;                                    /* inputA pointer                */\n  q7_t *pIn2;                                    /* inputB pointer                */\n  q15_t *py;                                     /* Intermediate inputB pointer   */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */\n  uint32_t j, k = 0u, blkCnt;                    /* loop counter                  */\n  int32_t inc = 1;                               /* output pointer increment          */\n  uint32_t outBlockSize;                         /* loop counter                  */\n  q15_t x4;                                      /* Temporary input variable      */\n  uint32_t tapCnt;                               /* loop counter                  */\n  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,        \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,        \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB        \n     * to make their lengths equal.        \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n\n  /* Copy (srcBLen) samples in scratch buffer */\n  k = srcBLen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    x4 = (q15_t) * pIn2++;\n    *pScr2++ = x4;\n    x4 = (q15_t) * pIn2++;\n    *pScr2++ = x4;\n    x4 = (q15_t) * pIn2++;\n    *pScr2++ = x4;\n    x4 = (q15_t) * pIn2++;\n    *pScr2++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcBLen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    x4 = (q15_t) * pIn2++;\n    *pScr2++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* Fill (srcBLen - 1u) zeros in scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update temporary scratch pointer */\n  pScr1 += (srcBLen - 1u);\n\n  /* Copy (srcALen) samples in scratch buffer */\n  k = srcALen >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = srcALen % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    x4 = (q15_t) * pIn1++;\n    *pScr1++ = x4;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */\n  arm_fill_q15(0, pScr1, (srcBLen - 1u));\n\n  /* Update pointer */\n  pScr1 += (srcBLen - 1u);\n\n#else\n\n/* Apply loop unrolling and do 4 Copies simultaneously. */\n  k = (srcBLen - 1u) >> 2u;\n\n  /* First part of the processing with loop unrolling copies 4 data points at a time.       \n   ** a second loop below copies for the remaining 1 to 3 samples. */\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner */\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n  /* If the count is not a multiple of 4, copy remaining samples here.       \n   ** No loop unrolling is used. */\n  k = (srcBLen - 1u) % 0x4u;\n\n  while(k > 0u)\n  {\n    /* copy second buffer in reversal manner for remaining samples */\n    *pScr1++ = 0;\n\n    /* Decrement the loop counter */\n    k--;\n  }\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n  /* Temporary pointer for second sequence */\n  py = pScratch2;\n\n  /* Initialization of pScr2 pointer */\n  pScr2 = pScratch2;\n\n  /* Actual correlation process starts here */\n  blkCnt = (srcALen + srcBLen - 1u) >> 2;\n\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Read two samples from scratch1 buffer */\n    x1 = *__SIMD32(pScr1)++;\n\n    /* Read next two samples from scratch1 buffer */\n    x2 = *__SIMD32(pScr1)++;\n\n    tapCnt = (srcBLen) >> 2u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pScr2);\n\n      /* multiply and accumlate */\n      acc0 = __SMLAD(x1, y1, acc0);\n      acc2 = __SMLAD(x2, y1, acc2);\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      /* multiply and accumlate */\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      /* Read next two samples from scratch1 buffer */\n      x1 = *__SIMD32(pScr1)++;\n\n      /* pack input data */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x1, x2, 0);\n#else\n      x3 = __PKHBT(x2, x1, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      /* Read four samples from smaller buffer */\n      y1 = _SIMD32_OFFSET(pScr2 + 2u);\n\n      acc0 = __SMLAD(x2, y1, acc0);\n\n      acc2 = __SMLAD(x1, y1, acc2);\n\n      acc1 = __SMLADX(x3, y1, acc1);\n\n      x2 = *__SIMD32(pScr1)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n      x3 = __PKHBT(x2, x1, 0);\n#else\n      x3 = __PKHBT(x1, x2, 0);\n#endif\n\n      acc3 = __SMLADX(x3, y1, acc3);\n\n      pScr2 += 4u;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n\n\n    /* Update scratch pointer for remaining samples of smaller length sequence */\n    pScr1 -= 4u;\n\n\n    /* apply same above for remaining samples of smaller length sequence */\n    tapCnt = (srcBLen) & 3u;\n\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pScr2);\n      acc1 += (*pScr1++ * *pScr2);\n      acc2 += (*pScr1++ * *pScr2);\n      acc3 += (*pScr1++ * *pScr2++);\n\n      pScr1 -= 3u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));\n    pOut += inc;\n    *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));\n    pOut += inc;\n    *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));\n    pOut += inc;\n    *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));\n    pOut += inc;\n\n    /* Initialization of inputB pointer */\n    pScr2 = py;\n\n    pScratch1 += 4u;\n\n  }\n\n\n  blkCnt = (srcALen + srcBLen - 1u) & 0x3;\n\n  /* Calculate correlation for remaining samples of Bigger length sequence */\n  while(blkCnt > 0)\n  {\n    /* Initialze temporary scratch pointer as scratch1 */\n    pScr1 = pScratch1;\n\n    /* Clear Accumlators */\n    acc0 = 0;\n\n    tapCnt = (srcBLen) >> 1u;\n\n    while(tapCnt > 0u)\n    {\n      acc0 += (*pScr1++ * *pScr2++);\n      acc0 += (*pScr1++ * *pScr2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    tapCnt = (srcBLen) & 1u;\n\n    /* apply same above for remaining samples of smaller length sequence */\n    while(tapCnt > 0u)\n    {\n\n      /* accumlate the results */\n      acc0 += (*pScr1++ * *pScr2++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    blkCnt--;\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));\n\n    pOut += inc;\n\n    /* Initialization of inputB pointer */\n    pScr2 = py;\n\n    pScratch1 += 1u;\n\n  }\n\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_correlate_q15.c   \n*   \n* Description:\tCorrelation of Q15 sequences. \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Corr   \n * @{   \n */\n\n/**   \n * @brief Correlation of Q15 sequences. \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   \n * @return none.   \n *   \n * @details   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * The function is implemented using a 64-bit internal accumulator.   \n * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   \n * This approach provides 33 guard bits and there is no risk of overflow.   \n * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   \n *   \n * \\par   \n * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. \n *\n * \\par    \n * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.\n * \n */\n\nvoid arm_correlate_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst)\n{\n\n#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q15_t *pIn1;                                   /* inputA pointer               */\n  q15_t *pIn2;                                   /* inputB pointer               */\n  q15_t *pOut = pDst;                            /* output pointer               */\n  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q15_t *px;                                     /* Intermediate inputA pointer  */\n  q15_t *py;                                     /* Intermediate inputB pointer  */\n  q15_t *pSrc1;                                  /* Intermediate pointers        */\n  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,   \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB   \n     * to make their lengths equal.   \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally   \n   * divided into three parts according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first part of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second part of the algorithm, srcBLen number of multiplications are done.   \n   * In the third part of the algorithm, the multiplications decrease by one   \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.   \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]   \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   \n   * ....   \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* The first loop starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */\n      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */\n      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n      sum = __SMLALD(*px++, *py++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (__SSAT((sum >> 15), 16));\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------   \n   * Stage2 process   \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1] samples */\n      x0 = *__SIMD32(px);\n      /* read x[1], x[2] samples */\n      x1 = _SIMD32_OFFSET(px + 1);\n\t  px += 2u;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read the first two inputB samples using SIMD:   \n         * y[0] and y[1] */\n        c0 = *__SIMD32(py)++;\n\n        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */\n        acc0 = __SMLALD(x0, c0, acc0);\n\n        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */\n        acc1 = __SMLALD(x1, c0, acc1);\n\n        /* Read x[2], x[3] */\n        x2 = *__SIMD32(px);\n\n        /* Read x[3], x[4] */\n        x3 = _SIMD32_OFFSET(px + 1);\n\n        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */\n        acc2 = __SMLALD(x2, c0, acc2);\n\n        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */\n        acc3 = __SMLALD(x3, c0, acc3);\n\n        /* Read y[2] and y[3] */\n        c0 = *__SIMD32(py)++;\n\n        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */\n        acc0 = __SMLALD(x2, c0, acc0);\n\n        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */\n        acc1 = __SMLALD(x3, c0, acc1);\n\n        /* Read x[4], x[5] */\n        x0 = _SIMD32_OFFSET(px + 2);\n\n        /* Read x[5], x[6] */\n        x1 = _SIMD32_OFFSET(px + 3);\n\n\t\tpx += 4u;\n\n        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */\n        acc2 = __SMLALD(x0, c0, acc2);\n\n        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */\n        acc3 = __SMLALD(x1, c0, acc3);\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      if(k == 1u)\n      {\n        /* Read y[4] */\n        c0 = *py;\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n\n#else\n\n        c0 = c0 & 0x0000FFFF;\n\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n        /* Read x[7] */\n        x3 = *__SIMD32(px);\n\t\tpx++;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALD(x0, c0, acc0);\n        acc1 = __SMLALD(x1, c0, acc1);\n        acc2 = __SMLALDX(x1, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n      if(k == 2u)\n      {\n        /* Read y[4], y[5] */\n        c0 = *__SIMD32(py);\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px + 1);\n\t\tpx += 2u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALD(x0, c0, acc0);\n        acc1 = __SMLALD(x1, c0, acc1);\n        acc2 = __SMLALD(x3, c0, acc2);\n        acc3 = __SMLALD(x2, c0, acc3);\n      }\n\n      if(k == 3u)\n      {\n        /* Read y[4], y[5] */\n        c0 = *__SIMD32(py)++;\n\n        /* Read x[7], x[8] */\n        x3 = *__SIMD32(px);\n\n        /* Read x[9] */\n        x2 = _SIMD32_OFFSET(px + 1);\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALD(x0, c0, acc0);\n        acc1 = __SMLALD(x1, c0, acc1);\n        acc2 = __SMLALD(x3, c0, acc2);\n        acc3 = __SMLALD(x2, c0, acc3);\n\n        c0 = (*py);\n\n        /* Read y[6] */\n#ifdef  ARM_MATH_BIG_ENDIAN\n\n        c0 = c0 << 16u;\n#else\n\n        c0 = c0 & 0x0000FFFF;\n#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */\n        /* Read x[10] */\n        x3 = _SIMD32_OFFSET(px + 2);\n\t\tpx += 3u;\n\n        /* Perform the multiply-accumulates */\n        acc0 = __SMLALDX(x1, c0, acc0);\n        acc1 = __SMLALD(x2, c0, acc1);\n        acc2 = __SMLALDX(x2, c0, acc2);\n        acc3 = __SMLALDX(x3, c0, acc3);\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));\n      pOut += inc;\n\n      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));\n      pOut += inc;\n\n      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));\n      pOut += inc;\n\n      /* Increment the count by 4 as 4 output values are computed */\n      count += 4u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q63_t) * px++ * *py++);\n        sum += ((q63_t) * px++ * *py++);\n        sum += ((q63_t) * px++ * *py++);\n        sum += ((q63_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q63_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (__SSAT(sum >> 15, 16));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment count by 1, as one output value is computed */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q63_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q15_t) (__SSAT(sum >> 15, 16));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   \n   * sum +=  x[srcALen-1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */\n      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */\n      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum = __SMLALD(*px++, *py++, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q15_t) (__SSAT((sum >> 15), 16));\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */\n  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */\n  q63_t sum;                                     /* Accumulators                  */\n  uint32_t i = 0u, j;                            /* loop counters */\n  uint32_t inv = 0u;                             /* Reverse order flag */\n  uint32_t tot = 0u;                             /* Length */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and a varaible, inv is set to 1 */\n  /* If lengths are not equal then zero pad has to be done to  make the two   \n   * inputs of same length. But to improve the performance, we include zeroes   \n   * in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   \n   * starting of the output buffer */\n  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  \n   * ending of the output buffer */\n  /* Once the zero padding is done the remaining of the output is calcualted  \n   * using convolution but with the shorter signal time shifted. */\n\n  /* Calculate the length of the remaining sequence */\n  tot = ((srcALen + srcBLen) - 2u);\n\n  if(srcALen > srcBLen)\n  {\n    /* Calculating the number of zeros to be padded to the output */\n    j = srcALen - srcBLen;\n\n    /* Initialise the pointer after zero padding */\n    pDst += j;\n  }\n\n  else if(srcALen < srcBLen)\n  {\n    /* Initialization to inputB pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization to the end of inputA pointer */\n    pIn2 = pSrcA + (srcALen - 1u);\n\n    /* Initialisation of the pointer after zero padding */\n    pDst = pDst + tot;\n\n    /* Swapping the lengths */\n    j = srcALen;\n    srcALen = srcBLen;\n    srcBLen = j;\n\n    /* Setting the reverse flag */\n    inv = 1;\n\n  }\n\n  /* Loop to calculate convolution for output length number of times */\n  for (i = 0u; i <= tot; i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0u; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if((((i - j) < srcBLen) && (j < srcALen)))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);\n      }\n    }\n    /* Store the output in the destination buffer */\n    if(inv == 1)\n      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);\n    else\n      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);\n  }\n\n#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */\n\n}\n\n/**   \n * @} end of Corr group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_correlate_q31.c    \n*    \n* Description:\tCorrelation of Q31 sequences.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup Corr    \n * @{    \n */\n\n/**    \n * @brief Correlation of Q31 sequences.    \n * @param[in] *pSrcA points to the first input sequence.    \n * @param[in] srcALen length of the first input sequence.    \n * @param[in] *pSrcB points to the second input sequence.    \n * @param[in] srcBLen length of the second input sequence.    \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * There is no saturation on intermediate additions.    \n * Thus, if the accumulator overflows it wraps around and distorts the result.    \n * The input signals should be scaled down to avoid intermediate overflows.    \n * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    \n * maximum of min(srcALen, srcBLen) number of additions is carried internally.    \n * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    \n *    \n * \\par    \n * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_correlate_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t *pIn1;                                   /* inputA pointer               */\n  q31_t *pIn2;                                   /* inputB pointer               */\n  q31_t *pOut = pDst;                            /* output pointer               */\n  q31_t *px;                                     /* Intermediate inputA pointer  */\n  q31_t *py;                                     /* Intermediate inputB pointer  */\n  q31_t *pSrc1;                                  /* Intermediate pointers        */\n  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */\n  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;                               /* Destination address modifier */\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,    \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,    \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,    \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB    \n     * to make their lengths equal.    \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally    \n   * divided into three parts according to the number of multiplications that has to be    \n   * taken place between inputA samples and inputB samples. In the first part of the    \n   * algorithm, the multiplications increase by one for every iteration.    \n   * In the second part of the algorithm, srcBLen number of multiplications are done.    \n   * In the third part of the algorithm, the multiplications decrease by one    \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.    \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------    \n   * Initializations of stage1    \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]    \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    \n   * ....    \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------    \n   * Stage1 process    \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] * y[srcBLen - 4] */\n      sum += (q63_t) * px++ * (*py++);\n      /* x[1] * y[srcBLen - 3] */\n      sum += (q63_t) * px++ * (*py++);\n      /* x[2] * y[srcBLen - 2] */\n      sum += (q63_t) * px++ * (*py++);\n      /* x[3] * y[srcBLen - 1] */\n      sum += (q63_t) * px++ * (*py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n      sum += (q63_t) * px++ * (*py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q31_t) (sum >> 31);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------    \n   * Initializations of stage2    \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    \n   * ....    \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------    \n   * Stage2 process    \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    \n   * So, to loop unroll over blockSize2,    \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll by 3 */\n    blkCnt = blockSize2 / 3;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n\n      /* read x[0], x[1] samples */\n      x0 = *(px++);\n      x1 = *(px++);\n\n      /* Apply loop unrolling and compute 3 MACs simultaneously. */\n      k = srcBLen / 3;\n\n      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        \n       ** a second loop below computes MACs for the remaining 1 to 2 samples. */\n      do\n      {\n        /* Read y[0] sample */\n        c0 = *(py);\n\n        /* Read x[2] sample */\n        x2 = *(px);\n\n        /* Perform the multiply-accumulate */\n        /* acc0 +=  x[0] * y[0] */\n        acc0 += ((q63_t) x0 * c0);\n        /* acc1 +=  x[1] * y[0] */\n        acc1 += ((q63_t) x1 * c0);\n        /* acc2 +=  x[2] * y[0] */\n        acc2 += ((q63_t) x2 * c0);\n\n        /* Read y[1] sample */\n        c0 = *(py + 1u);\n\n        /* Read x[3] sample */\n        x0 = *(px + 1u);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[1] * y[1] */\n        acc0 += ((q63_t) x1 * c0);\n        /* acc1 +=  x[2] * y[1] */\n        acc1 += ((q63_t) x2 * c0);\n        /* acc2 +=  x[3] * y[1] */\n        acc2 += ((q63_t) x0 * c0);\n\n        /* Read y[2] sample */\n        c0 = *(py + 2u);\n\n        /* Read x[4] sample */\n        x1 = *(px + 2u);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[2] * y[2] */\n        acc0 += ((q63_t) x2 * c0);\n        /* acc1 +=  x[3] * y[2] */\n        acc1 += ((q63_t) x0 * c0);\n        /* acc2 +=  x[4] * y[2] */\n        acc2 += ((q63_t) x1 * c0);\n\n        /* update scratch pointers */\n        px += 3u;\n        py += 3u;\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        \n       ** No loop unrolling is used. */\n      k = srcBLen - (3 * (srcBLen / 3));\n\n      while(k > 0u)\n      {\n        /* Read y[4] sample */\n        c0 = *(py++);\n\n        /* Read x[7] sample */\n        x2 = *(px++);\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[4] */\n        acc0 += ((q63_t) x0 * c0);\n        /* acc1 +=  x[5] * y[4] */\n        acc1 += ((q63_t) x1 * c0);\n        /* acc2 +=  x[6] * y[4] */\n        acc2 += ((q63_t) x2 * c0);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q31_t) (acc0 >> 31);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q31_t) (acc1 >> 31);\n      pOut += inc;\n\n      *pOut = (q31_t) (acc2 >> 31);\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 3 */\n      count += 3u;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 - 3 * (blockSize2 / 3);\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += (q63_t) * px++ * (*py++);\n        sum += (q63_t) * px++ * (*py++);\n        sum += (q63_t) * px++ * (*py++);\n        sum += (q63_t) * px++ * (*py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q31_t) (sum >> 31);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,    \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) * px++ * (*py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q31_t) (sum >> 31);\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------    \n   * Initializations of stage3    \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    \n   * ....    \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    \n   * sum +=  x[srcALen-1] * y[0]    \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.    \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------    \n   * Stage3 process    \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] */\n      sum += (q63_t) * px++ * (*py++);\n      /* sum += x[srcALen - srcBLen + 3] * y[2] */\n      sum += (q63_t) * px++ * (*py++);\n      /* sum += x[srcALen - srcBLen + 2] * y[1] */\n      sum += (q63_t) * px++ * (*py++);\n      /* sum += x[srcALen - srcBLen + 1] * y[0] */\n      sum += (q63_t) * px++ * (*py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.    \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += (q63_t) * px++ * (*py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q31_t) (sum >> 31);\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */\n  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */\n  q63_t sum;                                     /* Accumulators                  */\n  uint32_t i = 0u, j;                            /* loop counters */\n  uint32_t inv = 0u;                             /* Reverse order flag */\n  uint32_t tot = 0u;                             /* Length */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and a varaible, inv is set to 1 */\n  /* If lengths are not equal then zero pad has to be done to  make the two    \n   * inputs of same length. But to improve the performance, we include zeroes    \n   * in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    \n   * starting of the output buffer */\n  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   \n   * ending of the output buffer */\n  /* Once the zero padding is done the remaining of the output is calcualted   \n   * using correlation but with the shorter signal time shifted. */\n\n  /* Calculate the length of the remaining sequence */\n  tot = ((srcALen + srcBLen) - 2u);\n\n  if(srcALen > srcBLen)\n  {\n    /* Calculating the number of zeros to be padded to the output */\n    j = srcALen - srcBLen;\n\n    /* Initialise the pointer after zero padding */\n    pDst += j;\n  }\n\n  else if(srcALen < srcBLen)\n  {\n    /* Initialization to inputB pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization to the end of inputA pointer */\n    pIn2 = pSrcA + (srcALen - 1u);\n\n    /* Initialisation of the pointer after zero padding */\n    pDst = pDst + tot;\n\n    /* Swapping the lengths */\n    j = srcALen;\n    srcALen = srcBLen;\n    srcBLen = j;\n\n    /* Setting the reverse flag */\n    inv = 1;\n\n  }\n\n  /* Loop to calculate correlation for output length number of times */\n  for (i = 0u; i <= tot; i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to correlation equation */\n    for (j = 0u; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if((((i - j) < srcBLen) && (j < srcALen)))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);\n      }\n    }\n    /* Store the output in the destination buffer */\n    if(inv == 1)\n      *pDst-- = (q31_t) (sum >> 31u);\n    else\n      *pDst++ = (q31_t) (sum >> 31u);\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of Corr group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t\tarm_correlate_q7.c   \n*   \n* Description:\tCorrelation of Q7 sequences. \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**   \n * @ingroup groupFilters   \n */\n\n/**   \n * @addtogroup Corr   \n * @{   \n */\n\n/**   \n * @brief Correlation of Q7 sequences.   \n * @param[in] *pSrcA points to the first input sequence.   \n * @param[in] srcALen length of the first input sequence.   \n * @param[in] *pSrcB points to the second input sequence.   \n * @param[in] srcBLen length of the second input sequence.   \n * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   \n * @return none.   \n *   \n * @details   \n * Scaling and Overflow Behavior:   \n *   \n * \\par   \n * The function is implemented using a 32-bit internal accumulator.   \n * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   \n * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   \n * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   \n *\n * \\par    \n * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.\n * \n */\n\nvoid arm_correlate_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t *pIn1;                                    /* inputA pointer               */\n  q7_t *pIn2;                                    /* inputB pointer               */\n  q7_t *pOut = pDst;                             /* output pointer               */\n  q7_t *px;                                      /* Intermediate inputA pointer  */\n  q7_t *py;                                      /* Intermediate inputB pointer  */\n  q7_t *pSrc1;                                   /* Intermediate pointers        */\n  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */\n  q31_t input1, input2;                          /* temporary variables */\n  q15_t in1, in2;                                /* temporary variables */\n  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */\n  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */\n  int32_t inc = 1;\n\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and the destination pointer modifier, inc is set to -1 */\n  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */\n  /* But to improve the performance,   \n   * we include zeroes in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */\n  /* If srcALen < srcBLen,   \n   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */\n  if(srcALen >= srcBLen)\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcA);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcB);\n\n    /* Number of output samples is calculated */\n    outBlockSize = (2u * srcALen) - 1u;\n\n    /* When srcALen > srcBLen, zero padding is done to srcB   \n     * to make their lengths equal.   \n     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   \n     * number of output samples are made zero */\n    j = outBlockSize - (srcALen + (srcBLen - 1u));\n\n    /* Updating the pointer position to non zero value */\n    pOut += j;\n\n  }\n  else\n  {\n    /* Initialization of inputA pointer */\n    pIn1 = (pSrcB);\n\n    /* Initialization of inputB pointer */\n    pIn2 = (pSrcA);\n\n    /* srcBLen is always considered as shorter or equal to srcALen */\n    j = srcBLen;\n    srcBLen = srcALen;\n    srcALen = j;\n\n    /* CORR(x, y) = Reverse order(CORR(y, x)) */\n    /* Hence set the destination pointer to point to the last output sample */\n    pOut = pDst + ((srcALen + srcBLen) - 2u);\n\n    /* Destination address modifier is set to -1 */\n    inc = -1;\n\n  }\n\n  /* The function is internally   \n   * divided into three parts according to the number of multiplications that has to be   \n   * taken place between inputA samples and inputB samples. In the first part of the   \n   * algorithm, the multiplications increase by one for every iteration.   \n   * In the second part of the algorithm, srcBLen number of multiplications are done.   \n   * In the third part of the algorithm, the multiplications decrease by one   \n   * for every iteration.*/\n  /* The algorithm is implemented in three stages.   \n   * The loop counters of each stage is initiated here. */\n  blockSize1 = srcBLen - 1u;\n  blockSize2 = srcALen - (srcBLen - 1u);\n  blockSize3 = blockSize1;\n\n  /* --------------------------   \n   * Initializations of stage1   \n   * -------------------------*/\n\n  /* sum = x[0] * y[srcBlen - 1]   \n   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   \n   * ....   \n   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   \n   */\n\n  /* In this stage the MAC operations are increased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = 1u;\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  pSrc1 = pIn2 + (srcBLen - 1u);\n  py = pSrc1;\n\n  /* ------------------------   \n   * Stage1 process   \n   * ----------------------*/\n\n  /* The first stage starts here */\n  while(blockSize1 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[0] , x[1] */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* y[srcBLen - 4] , y[srcBLen - 3] */\n      in1 = (q15_t) * py++;\n      in2 = (q15_t) * py++;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* x[0] * y[srcBLen - 4] */\n      /* x[1] * y[srcBLen - 3] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* x[2] , x[3] */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* y[srcBLen - 2] , y[srcBLen - 1] */\n      in1 = (q15_t) * py++;\n      in2 = (q15_t) * py++;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* x[2] * y[srcBLen - 2] */\n      /* x[3] * y[srcBLen - 1] */\n      sum = __SMLAD(input1, input2, sum);\n\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      /* x[0] * y[srcBLen - 1] */\n      sum += (q31_t) ((q15_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q7_t) (__SSAT(sum >> 7, 8));\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    py = pSrc1 - count;\n    px = pIn1;\n\n    /* Increment the MAC count */\n    count++;\n\n    /* Decrement the loop counter */\n    blockSize1--;\n  }\n\n  /* --------------------------   \n   * Initializations of stage2   \n   * ------------------------*/\n\n  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   \n   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   \n   * ....   \n   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   */\n\n  /* Working pointer of inputA */\n  px = pIn1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* count is index by which the pointer pIn1 to be incremented */\n  count = 0u;\n\n  /* -------------------   \n   * Stage2 process   \n   * ------------------*/\n\n  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   \n   * So, to loop unroll over blockSize2,   \n   * srcBLen should be greater than or equal to 4 */\n  if(srcBLen >= 4u)\n  {\n    /* Loop unroll over blockSize2, by 4 */\n    blkCnt = blockSize2 >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Set all accumulators to zero */\n      acc0 = 0;\n      acc1 = 0;\n      acc2 = 0;\n      acc3 = 0;\n\n      /* read x[0], x[1], x[2] samples */\n      x0 = *px++;\n      x1 = *px++;\n      x2 = *px++;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      do\n      {\n        /* Read y[0] sample */\n        c0 = *py++;\n        /* Read y[1] sample */\n        c1 = *py++;\n\n        /* Read x[3] sample */\n        x3 = *px++;\n\n        /* x[0] and x[1] are packed */\n        in1 = (q15_t) x0;\n        in2 = (q15_t) x1;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* y[0] and y[1] are packed */\n        in1 = (q15_t) c0;\n        in2 = (q15_t) c1;\n\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc0 += x[0] * y[0] + x[1] * y[1]  */\n        acc0 = __SMLAD(input1, input2, acc0);\n\n        /* x[1] and x[2] are packed */\n        in1 = (q15_t) x1;\n        in2 = (q15_t) x2;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc1 += x[1] * y[0] + x[2] * y[1] */\n        acc1 = __SMLAD(input1, input2, acc1);\n\n        /* x[2] and x[3] are packed */\n        in1 = (q15_t) x2;\n        in2 = (q15_t) x3;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc2 += x[2] * y[0] + x[3] * y[1]  */\n        acc2 = __SMLAD(input1, input2, acc2);\n\n        /* Read x[4] sample */\n        x0 = *(px++);\n\n        /* x[3] and x[4] are packed */\n        in1 = (q15_t) x3;\n        in2 = (q15_t) x0;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc3 += x[3] * y[0] + x[4] * y[1]  */\n        acc3 = __SMLAD(input1, input2, acc3);\n\n        /* Read y[2] sample */\n        c0 = *py++;\n        /* Read y[3] sample */\n        c1 = *py++;\n\n        /* Read x[5] sample */\n        x1 = *px++;\n\n        /* x[2] and x[3] are packed */\n        in1 = (q15_t) x2;\n        in2 = (q15_t) x3;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* y[2] and y[3] are packed */\n        in1 = (q15_t) c0;\n        in2 = (q15_t) c1;\n\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc0 += x[2] * y[2] + x[3] * y[3]  */\n        acc0 = __SMLAD(input1, input2, acc0);\n\n        /* x[3] and x[4] are packed */\n        in1 = (q15_t) x3;\n        in2 = (q15_t) x0;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc1 += x[3] * y[2] + x[4] * y[3]  */\n        acc1 = __SMLAD(input1, input2, acc1);\n\n        /* x[4] and x[5] are packed */\n        in1 = (q15_t) x0;\n        in2 = (q15_t) x1;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc2 += x[4] * y[2] + x[5] * y[3]  */\n        acc2 = __SMLAD(input1, input2, acc2);\n\n        /* Read x[6] sample */\n        x2 = *px++;\n\n        /* x[5] and x[6] are packed */\n        in1 = (q15_t) x1;\n        in2 = (q15_t) x2;\n\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* acc3 += x[5] * y[2] + x[6] * y[3]  */\n        acc3 = __SMLAD(input1, input2, acc3);\n\n      } while(--k);\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Read y[4] sample */\n        c0 = *py++;\n\n        /* Read x[7] sample */\n        x3 = *px++;\n\n        /* Perform the multiply-accumulates */\n        /* acc0 +=  x[4] * y[4] */\n        acc0 += ((q15_t) x0 * c0);\n        /* acc1 +=  x[5] * y[4] */\n        acc1 += ((q15_t) x1 * c0);\n        /* acc2 +=  x[6] * y[4] */\n        acc2 += ((q15_t) x2 * c0);\n        /* acc3 +=  x[7] * y[4] */\n        acc3 += ((q15_t) x3 * c0);\n\n        /* Reuse the present samples for the next MAC */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));\n      pOut += inc;\n\n      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));\n      pOut += inc;\n\n      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));\n      pOut += inc;\n\n\t  count += 4u;\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   \n     ** No loop unrolling is used. */\n    blkCnt = blockSize2 % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Apply loop unrolling and compute 4 MACs simultaneously. */\n      k = srcBLen >> 2u;\n\n      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n       ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n      while(k > 0u)\n      {\n        /* Reading two inputs of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Reading two inputs of SrcB buffer and packing */\n        in1 = (q15_t) * py++;\n        in2 = (q15_t) * py++;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Reading two inputs of SrcA buffer and packing */\n        in1 = (q15_t) * px++;\n        in2 = (q15_t) * px++;\n        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Reading two inputs of SrcB buffer and packing */\n        in1 = (q15_t) * py++;\n        in2 = (q15_t) * py++;\n        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n        /* Perform the multiply-accumulates */\n        sum = __SMLAD(input1, input2, sum);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   \n       ** No loop unrolling is used. */\n      k = srcBLen % 0x4u;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulates */\n        sum += ((q15_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q7_t) (__SSAT(sum >> 7, 8));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the pointer pIn1 index, count by 1 */\n\t  count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n  else\n  {\n    /* If the srcBLen is not a multiple of 4,   \n     * the blockSize2 loop cannot be unrolled by 4 */\n    blkCnt = blockSize2;\n\n    while(blkCnt > 0u)\n    {\n      /* Accumulator is made zero for every iteration */\n      sum = 0;\n\n      /* Loop over srcBLen */\n      k = srcBLen;\n\n      while(k > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += ((q15_t) * px++ * *py++);\n\n        /* Decrement the loop counter */\n        k--;\n      }\n\n      /* Store the result in the accumulator in the destination buffer. */\n      *pOut = (q7_t) (__SSAT(sum >> 7, 8));\n      /* Destination pointer is updated according to the address modifier, inc */\n      pOut += inc;\n\n      /* Increment the MAC count */\n      count++;\n\n      /* Update the inputA and inputB pointers for next MAC calculation */\n      px = pIn1 + count;\n      py = pIn2;\n\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n  }\n\n  /* --------------------------   \n   * Initializations of stage3   \n   * -------------------------*/\n\n  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   \n   * ....   \n   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   \n   * sum +=  x[srcALen-1] * y[0]   \n   */\n\n  /* In this stage the MAC operations are decreased by 1 for every iteration.   \n     The count variable holds the number of MAC operations performed */\n  count = srcBLen - 1u;\n\n  /* Working pointer of inputA */\n  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));\n  px = pSrc1;\n\n  /* Working pointer of inputB */\n  py = pIn2;\n\n  /* -------------------   \n   * Stage3 process   \n   * ------------------*/\n\n  while(blockSize3 > 0u)\n  {\n    /* Accumulator is made zero for every iteration */\n    sum = 0;\n\n    /* Apply loop unrolling and compute 4 MACs simultaneously. */\n    k = count >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   \n     ** a second loop below computes MACs for the remaining 1 to 3 samples. */\n    while(k > 0u)\n    {\n      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* y[0] , y[1] */\n      in1 = (q15_t) * py++;\n      in2 = (q15_t) * py++;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* sum += x[srcALen - srcBLen + 1] * y[0] */\n      /* sum += x[srcALen - srcBLen + 2] * y[1] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */\n      in1 = (q15_t) * px++;\n      in2 = (q15_t) * px++;\n      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* y[2] , y[3] */\n      in1 = (q15_t) * py++;\n      in2 = (q15_t) * py++;\n      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);\n\n      /* sum += x[srcALen - srcBLen + 3] * y[2] */\n      /* sum += x[srcALen - srcBLen + 4] * y[3] */\n      sum = __SMLAD(input1, input2, sum);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* If the count is not a multiple of 4, compute any remaining MACs here.   \n     ** No loop unrolling is used. */\n    k = count % 0x4u;\n\n    while(k > 0u)\n    {\n      /* Perform the multiply-accumulates */\n      sum += ((q15_t) * px++ * *py++);\n\n      /* Decrement the loop counter */\n      k--;\n    }\n\n    /* Store the result in the accumulator in the destination buffer. */\n    *pOut = (q7_t) (__SSAT(sum >> 7, 8));\n    /* Destination pointer is updated according to the address modifier, inc */\n    pOut += inc;\n\n    /* Update the inputA and inputB pointers for next MAC calculation */\n    px = ++pSrc1;\n    py = pIn2;\n\n    /* Decrement the MAC count */\n    count--;\n\n    /* Decrement the loop counter */\n    blockSize3--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  q7_t *pIn1 = pSrcA;                            /* inputA pointer */\n  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */\n  q31_t sum;                                     /* Accumulator */\n  uint32_t i = 0u, j;                            /* loop counters */\n  uint32_t inv = 0u;                             /* Reverse order flag */\n  uint32_t tot = 0u;                             /* Length */\n\n  /* The algorithm implementation is based on the lengths of the inputs. */\n  /* srcB is always made to slide across srcA. */\n  /* So srcBLen is always considered as shorter or equal to srcALen */\n  /* But CORR(x, y) is reverse of CORR(y, x) */\n  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */\n  /* and a varaible, inv is set to 1 */\n  /* If lengths are not equal then zero pad has to be done to  make the two   \n   * inputs of same length. But to improve the performance, we include zeroes   \n   * in the output instead of zero padding either of the the inputs*/\n  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   \n   * starting of the output buffer */\n  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  \n   * ending of the output buffer */\n  /* Once the zero padding is done the remaining of the output is calcualted  \n   * using convolution but with the shorter signal time shifted. */\n\n  /* Calculate the length of the remaining sequence */\n  tot = ((srcALen + srcBLen) - 2u);\n\n  if(srcALen > srcBLen)\n  {\n    /* Calculating the number of zeros to be padded to the output */\n    j = srcALen - srcBLen;\n\n    /* Initialise the pointer after zero padding */\n    pDst += j;\n  }\n\n  else if(srcALen < srcBLen)\n  {\n    /* Initialization to inputB pointer */\n    pIn1 = pSrcB;\n\n    /* Initialization to the end of inputA pointer */\n    pIn2 = pSrcA + (srcALen - 1u);\n\n    /* Initialisation of the pointer after zero padding */\n    pDst = pDst + tot;\n\n    /* Swapping the lengths */\n    j = srcALen;\n    srcALen = srcBLen;\n    srcBLen = j;\n\n    /* Setting the reverse flag */\n    inv = 1;\n\n  }\n\n  /* Loop to calculate convolution for output length number of times */\n  for (i = 0u; i <= tot; i++)\n  {\n    /* Initialize sum with zero to carry on MAC operations */\n    sum = 0;\n\n    /* Loop to perform MAC operations according to convolution equation */\n    for (j = 0u; j <= i; j++)\n    {\n      /* Check the array limitations */\n      if((((i - j) < srcBLen) && (j < srcALen)))\n      {\n        /* z[i] += x[i-j] * y[j] */\n        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);\n      }\n    }\n    /* Store the output in the destination buffer */\n    if(inv == 1)\n      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);\n    else\n      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**   \n * @} end of Corr group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_decimate_f32.c    \n*    \n* Description:\tFIR decimation for floating-point sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator    \n *    \n * These functions combine an FIR filter together with a decimator.    \n * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.    \n * Conceptually, the functions are equivalent to the block diagram below:    \n * \\image html FIRDecimator.gif \"Components included in the FIR Decimator functions\"    \n * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized    \n * cutoff frequency of 1/M in order to prevent aliasing distortion.    \n * The user of the function is responsible for providing the filter coefficients.    \n *    \n * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.    \n * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the    \n * samples output by the decimator are computed.    \n * The functions operate on blocks of input and output data.    \n * pSrc points to an array of blockSize input values and    \n * pDst points to an array of blockSize/M output values.    \n * In order to have an integer number of output samples blockSize    \n * must always be a multiple of the decimation factor M.    \n *    \n * The library provides separate functions for Q15, Q31 and floating-point data types.    \n *    \n * \\par Algorithm:    \n * The FIR portion of the algorithm uses the standard form filter:    \n * 
    \n *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n * 
    \n * where, b[n] are the filter coefficients.    \n * \\par   \n * The pCoeffs points to a coefficient array of size numTaps.    \n * Coefficients are stored in time reversed order.    \n * \\par    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to a state array of size numTaps + blockSize - 1.    \n * Samples in the state buffer are stored in the order:    \n * \\par    \n * 
    \n *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n * 
    \n * The state variables are updated after each block of data is processed, the coefficients are untouched.    \n *    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * - Checks to make sure that the size of the input is a multiple of the decimation factor.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * The code below statically initializes each of the 3 different data type filter instance structures    \n * 
    \n *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    \n *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    \n *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    \n * 
    \n * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;    \n * pCoeffs is the address of the coefficient buffer;    \n * pState is the address of the state buffer.    \n * Be sure to set the values in the state buffer to zeros when doing static initialization.    \n *    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n  /**    \n   * @brief Processing function for the floating-point FIR decimator.    \n   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.    \n   * @param[in] *pSrc     points to the block of input data.    \n   * @param[out] *pDst    points to the block of output data.    \n   * @param[in] blockSize number of input samples to process per call.    \n   * @return none.    \n   */\n\nvoid arm_fir_decimate_f32(\n  const arm_fir_decimate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */\n  float32_t sum0;                                /* Accumulator */\n  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  uint32_t blkCntN4;\n  float32_t *px0, *px1, *px2, *px3;\n  float32_t acc0, acc1, acc2, acc3;\n  float32_t x1, x2, x3;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize / 4;\n  blkCntN4 = outBlockSize - (4 * blkCnt);\n\n  while(blkCnt > 0u)\n  {\n    /* Copy 4 * decimation factor number of new input samples into the state buffer */\n    i = 4 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulators to zero */\n    acc0 = 0.0f;\n    acc1 = 0.0f;\n    acc2 = 0.0f;\n    acc3 = 0.0f;\n\n    /* Initialize state pointer for all the samples */\n    px0 = pState;\n    px1 = pState + S->M;\n    px2 = pState + 2 * S->M;\n    px3 = pState + 3 * S->M;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n\n    while(tapCnt > 0u)\n    {\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-1] sample for acc0 */\n      x0 = *(px0++);\n      /* Read x[n-numTaps-1] sample for acc1 */\n      x1 = *(px1++);\n      /* Read x[n-numTaps-1] sample for acc2 */\n      x2 = *(px2++);\n      /* Read x[n-numTaps-1] sample for acc3 */\n      x3 = *(px3++);\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n      acc2 += x2 * c0;\n      acc3 += x3 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */\n      x0 = *(px0++);\n      x1 = *(px1++);\n      x2 = *(px2++);\n      x3 = *(px3++);\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n      acc2 += x2 * c0;\n      acc3 += x3 * c0;\n\n      /* Read the b[numTaps-3] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */\n      x0 = *(px0++);\n      x1 = *(px1++);\n      x2 = *(px2++);\n      x3 = *(px3++);\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n      acc2 += x2 * c0;\n      acc3 += x3 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */\n      x0 = *(px0++);\n      x1 = *(px1++);\n      x2 = *(px2++);\n      x3 = *(px3++);\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n      acc2 += x2 * c0;\n      acc3 += x3 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch  state variables for acc0, acc1, acc2, acc3 */\n      x0 = *(px0++);\n      x1 = *(px1++);\n      x2 = *(px2++);\n      x3 = *(px3++);\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n      acc2 += x2 * c0;\n      acc3 += x3 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + 4 * S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = acc0;\n    *pDst++ = acc1;\n    *pDst++ = acc2;\n    *pDst++ = acc3;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  while(blkCntN4 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    sum0 = 0.0f;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-1] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-2] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-3] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = sum0;\n\n    /* Decrement the loop counter */\n    blkCntN4--;\n  }\n\n  /* Processing is complete.    \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    sum0 = 0.0f;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor           \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = sum0;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Copy numTaps number of values */\n  i = (numTaps - 1u);\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */\n\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_decimate_fast_q15.c    \n*    \n* Description:\tFast Q15 FIR Decimator.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    \n * @param[in] *S points to an instance of the Q15 FIR decimator structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none    \n *    \n * \\par Restrictions   \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   \n *\tIn this case input, output, state buffers should be aligned by 32-bit   \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * This fast version uses a 32-bit accumulator with 2.30 format.    \n * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around and distorts the result.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).    \n * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    \n *    \n * \\par    \n * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    \n * Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.    \n */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\nvoid arm_fir_decimate_fast_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer coefficient buffer */\n  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */\n  q31_t sum0;                                    /* Accumulators */\n  q31_t acc0, acc1;\n  q15_t *px0, *px1;\n  uint32_t blkCntN3;\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize / 2;\n  blkCntN3 = outBlockSize - (2 * blkCnt);\n\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = 2 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    acc0 = 0;\n    acc1 = 0;\n\n    /* Initialize state pointer */\n    px0 = pState;\n\n    px1 = pState + S->M;\n\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */\n      x0 = *__SIMD32(px0)++;\n\n      x1 = *__SIMD32(px1)++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLAD(x0, c0, acc0);\n\n      acc1 = __SMLAD(x1, c0, acc1);\n\n      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */\n      x0 = *__SIMD32(px0)++;\n\n      x1 = *__SIMD32(px1)++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLAD(x0, c0, acc0);\n\n      acc1 = __SMLAD(x1, c0, acc1);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px0++;\n\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLAD(x0, c0, acc0);\n      acc1 = __SMLAD(x1, c0, acc1);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M * 2;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n\n  while(blkCntN3 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /*Set sum to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */\n      x0 = *__SIMD32(px)++;\n\n      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */\n      c1 = *__SIMD32(pb)++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLAD(x0, c0, sum0);\n\n      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */\n      x0 = *__SIMD32(px)++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLAD(x0, c1, sum0);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLAD(x0, c0, sum0);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCntN3--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n#else\n\n\nvoid arm_fir_decimate_fast_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer coefficient buffer */\n  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */\n  q31_t sum0;                                    /* Accumulators */\n  q31_t acc0, acc1;\n  q15_t *px0, *px1;\n  uint32_t blkCntN3;\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize / 2;\n  blkCntN3 = outBlockSize - (2 * blkCnt);\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = 2 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    acc0 = 0;\n    acc1 = 0;\n\n    /* Initialize state pointer */\n    px0 = pState;\n\n    px1 = pState + S->M;\n\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-2] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-3]  coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-3] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-4] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M * 2;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));\n\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  while(blkCntN3 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /*Set sum to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-1] and sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-2] and  sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-3]  coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-3] sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCntN3--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_decimate_fast_q31.c    \n*    \n* Description:\tFast Q31 FIR Decimator.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    \n * @param[in] *S points to an instance of the Q31 FIR decimator structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none    \n *    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    \n * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    \n * These intermediate results are added to a 2.30 accumulator.    \n * Finally, the accumulator is saturated and converted to a 1.31 result.    \n * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    \n *    \n * \\par    \n * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    \n * Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.    \n */\n\nvoid arm_fir_decimate_fast_q31(\n  arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  q31_t *px;                                     /* Temporary pointers for state buffer */\n  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */\n  q31_t sum0;                                    /* Accumulator */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n  uint32_t blkCntN2;\n  q31_t x1;\n  q31_t acc0, acc1;\n  q31_t *px0, *px1;\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n\n  blkCnt = outBlockSize / 2;\n  blkCntN2 = outBlockSize - (2 * blkCnt);\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = 2 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    acc0 = 0;\n    acc1 = 0;\n\n    /* Initialize state pointer */\n    px0 = pState;\n    px1 = pState + S->M;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb);\n\n      /* Read x[n-numTaps-1] for sample 0 sample 1 */\n      x0 = *(px0);\n      x1 = *(px1);\n\n      /* Perform the multiply-accumulate */\n      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb + 1u);\n\n      /* Read x[n-numTaps-2]  for sample 0 sample 1  */\n      x0 = *(px0 + 1u);\n      x1 = *(px1 + 1u);\n\n      /* Perform the multiply-accumulate */\n      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n      /* Read the b[numTaps-3] coefficient */\n      c0 = *(pb + 2u);\n\n      /* Read x[n-numTaps-3]  for sample 0 sample 1 */\n      x0 = *(px0 + 2u);\n      x1 = *(px1 + 2u);\n      pb += 4u;\n\n      /* Perform the multiply-accumulate */\n      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *(pb - 1u);\n\n      /* Read x[n-numTaps-4] for sample 0 sample 1 */\n      x0 = *(px0 + 3u);\n      x1 = *(px1 + 3u);\n\n\n      /* Perform the multiply-accumulate */\n      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n      /* update state pointers */\n      px0 += 4u;\n      px1 += 4u;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x0 = *(px0++);\n      x1 = *(px1++);\n\n      /* Perform the multiply-accumulate */\n      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);\n      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M * 2;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = (q31_t) (acc0 << 1);\n    *pDst++ = (q31_t) (acc1 << 1);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  while(blkCntN2 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-1] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-2] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n      /* Read the b[numTaps-3] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = (q31_t) (sum0 << 1);\n\n    /* Decrement the loop counter */\n    blkCntN2--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_decimate_init_f32.c    \n*    \n* Description:  Floating-point FIR Decimator initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the floating-point FIR decimator.    \n * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.    \n * @param[in] numTaps  number of coefficients in the filter.    \n * @param[in] M  decimation factor.    \n * @param[in] *pCoeffs points to the filter coefficients.    \n * @param[in] *pState points to the state buffer.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * blockSize is not a multiple of M.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().    \n * M is the decimation factor.    \n */\n\narm_status arm_fir_decimate_init_f32(\n  arm_fir_decimate_instance_f32 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n  /* The size of the input block must be a multiple of the decimation factor */\n  if((blockSize % M) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n    /* Assign filter taps */\n    S->numTaps = numTaps;\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Clear state buffer and size is always (blockSize + numTaps - 1) */\n    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    /* Assign Decimation Factor */\n    S->M = M;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_decimate_init_q15.c    \n*    \n* Description:  Initialization function for the Q15 FIR Decimator.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the Q15 FIR decimator.    \n * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.    \n * @param[in] numTaps  number of coefficients in the filter.    \n * @param[in] M  decimation factor.    \n * @param[in] *pCoeffs points to the filter coefficients.    \n * @param[in] *pState points to the state buffer.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * blockSize is not a multiple of M.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples    \n * to the call arm_fir_decimate_q15().    \n * M is the decimation factor.    \n */\n\narm_status arm_fir_decimate_init_q15(\n  arm_fir_decimate_instance_q15 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize)\n{\n\n  arm_status status;\n\n  /* The size of the input block must be a multiple of the decimation factor */\n  if((blockSize % M) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n    /* Assign filter taps */\n    S->numTaps = numTaps;\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */\n    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    /* Assign Decimation factor */\n    S->M = M;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_decimate_init_q31.c    \n*    \n* Description:  Initialization function for Q31 FIR Decimation filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the Q31 FIR decimator.    \n * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.    \n * @param[in] numTaps  number of coefficients in the filter.    \n * @param[in] M  decimation factor.    \n * @param[in] *pCoeffs points to the filter coefficients.    \n * @param[in] *pState points to the state buffer.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * blockSize is not a multiple of M.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().    \n * M is the decimation factor.    \n */\n\narm_status arm_fir_decimate_init_q31(\n  arm_fir_decimate_instance_q31 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n  /* The size of the input block must be a multiple of the decimation factor */\n  if((blockSize % M) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n    /* Assign filter taps */\n    S->numTaps = numTaps;\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */\n    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    /* Assign Decimation factor */\n    S->M = M;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_decimate_q15.c    \n*    \n* Description:\tQ15 FIR Decimator.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 FIR decimator.    \n * @param[in] *S points to an instance of the Q15 FIR decimator structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the location where the output result is written.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    \n * Lastly, the accumulator is saturated to yield a result in 1.15 format.    \n *    \n * \\par    \n * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\nvoid arm_fir_decimate_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer coefficient buffer */\n  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */\n  q63_t sum0;                                    /* Accumulators */\n  q63_t acc0, acc1;\n  q15_t *px0, *px1;\n  uint32_t blkCntN3;\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize / 2;\n  blkCntN3 = outBlockSize - (2 * blkCnt);\n\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = 2 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    acc0 = 0;\n    acc1 = 0;\n\n    /* Initialize state pointer */\n    px0 = pState;\n\n    px1 = pState + S->M;\n\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */\n      x0 = *__SIMD32(px0)++;\n\n      x1 = *__SIMD32(px1)++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLALD(x0, c0, acc0);\n\n      acc1 = __SMLALD(x1, c0, acc1);\n\n      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */\n      x0 = *__SIMD32(px0)++;\n\n      x1 = *__SIMD32(px1)++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLALD(x0, c0, acc0);\n\n      acc1 = __SMLALD(x1, c0, acc1);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px0++;\n\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 = __SMLALD(x0, c0, acc0);\n      acc1 = __SMLALD(x1, c0, acc1);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M * 2;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n\n  while(blkCntN3 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /*Set sum to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */\n      x0 = *__SIMD32(px)++;\n\n      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */\n      c1 = *__SIMD32(pb)++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLALD(x0, c0, sum0);\n\n      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */\n      x0 = *__SIMD32(px)++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLALD(x0, c1, sum0);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 = __SMLALD(x0, c0, sum0);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCntN3--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n#else\n\n\nvoid arm_fir_decimate_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer coefficient buffer */\n  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */\n  q63_t sum0;                                    /* Accumulators */\n  q63_t acc0, acc1;\n  q15_t *px0, *px1;\n  uint32_t blkCntN3;\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize / 2;\n  blkCntN3 = outBlockSize - (2 * blkCnt);\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = 2 * S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    acc0 = 0;\n    acc1 = 0;\n\n    /* Initialize state pointer */\n    px0 = pState;\n\n    px1 = pState + S->M;\n\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-2] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-3] coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-3] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-4] for sample 0 and sample 1 */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px0++;\n      x1 = *px1++;\n\n      /* Perform the multiply-accumulate */\n      acc0 += x0 * c0;\n      acc1 += x1 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M * 2;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  while(blkCntN3 > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /*Set sum to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the Read b[numTaps-1] coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-1] and sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-2] and  sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-3]  coefficients */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-3] sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *pb++;\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += x0 * c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor       \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* Store filter output, smlad returns the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCntN3--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#else\n\n\nvoid arm_fir_decimate_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer coefficient buffer */\n  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  q63_t sum0;                                    /* Accumulators */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n\n/* Run the below code for Cortex-M0 */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /*Set sum to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q31_t) x0 *c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor           \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /*Store filter output , smlad will return the values in 2.14 format */\n    /* so downsacle by 15 to get output in 1.15 */\n    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = numTaps - 1u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n\n}\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_decimate_q31.c    \n*    \n* Description:\tQ31 FIR Decimator.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_decimate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 FIR decimator.    \n * @param[in] *S points to an instance of the Q31 FIR decimator structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    \n * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    \n *    \n * \\par    \n * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_fir_decimate_q31(\n  const arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  q31_t *px;                                     /* Temporary pointers for state buffer */\n  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */\n  q63_t sum0;                                    /* Accumulator */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps */\n  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.    \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    while(tapCnt > 0u)\n    {\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-1] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-2] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Read the b[numTaps-3] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Read the b[numTaps-4] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor    \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = (q31_t) (sum0 >> 31);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.    \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n  i = (numTaps - 1u) % 0x04u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Total number of output samples to be computed */\n  blkCnt = outBlockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy decimation factor number of new input samples into the state buffer */\n    i = S->M;\n\n    do\n    {\n      *pStateCurnt++ = *pSrc++;\n\n    } while(--i);\n\n    /* Set accumulator to zero */\n    sum0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = pCoeffs;\n\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Read coefficients */\n      c0 = *pb++;\n\n      /* Fetch 1 state variable */\n      x0 = *px++;\n\n      /* Perform the multiply-accumulate */\n      sum0 += (q63_t) x0 *c0;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance the state pointer by the decimation factor           \n     * to process the next group of decimation factor number samples */\n    pState = pState + S->M;\n\n    /* The result is in the accumulator, store in the destination buffer. */\n    *pDst++ = (q31_t) (sum0 >> 31);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = numTaps - 1u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_decimate group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c",
    "content": "/* ----------------------------------------------------------------------  \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.  \n*  \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*  \n* Project: \t    CMSIS DSP Library  \n* Title:\t    arm_fir_f32.c  \n*  \n* Description:\tFloating-point FIR filter processing function.  \n*  \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**  \n* @ingroup groupFilters  \n*/\n\n/**  \n* @defgroup FIR Finite Impulse Response (FIR) Filters  \n*  \n* This set of functions implements Finite Impulse Response (FIR) filters  \n* for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.  \n* The functions operate on blocks of input and output data and each call to the function processes  \n* blockSize samples through the filter.  pSrc and  \n* pDst points to input and output arrays containing blockSize values.  \n*  \n* \\par Algorithm:  \n* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.  \n* Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].  \n* 
  \n*    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  \n* 
  \n* \\par  \n* \\image html FIR.gif \"Finite Impulse Response filter\"  \n* \\par  \n* pCoeffs points to a coefficient array of size numTaps.  \n* Coefficients are stored in time reversed order.  \n* \\par  \n* 
  \n*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  \n* 
  \n* \\par  \n* pState points to a state array of size numTaps + blockSize - 1.  \n* Samples in the state buffer are stored in the following order.  \n* \\par  \n* 
  \n*    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  \n* 
  \n* \\par  \n* Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.  \n* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,  \n* to be avoided and yields a significant speed improvement.  \n* The state variables are updated after each block of data is processed; the coefficients are untouched.  \n* \\par Instance Structure  \n* The coefficients and state variables for a filter are stored together in an instance data structure.  \n* A separate instance structure must be defined for each filter.  \n* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.  \n* There are separate instance structure declarations for each of the 4 supported data types.  \n*  \n* \\par Initialization Functions  \n* There is also an associated initialization function for each data type.  \n* The initialization function performs the following operations:  \n* - Sets the values of the internal structure fields.  \n* - Zeros out the values in the state buffer.  \n* To do this manually without calling the init function, assign the follow subfields of the instance structure:\n* numTaps, pCoeffs, pState. Also set all of the values in pState to zero. \n*  \n* \\par  \n* Use of the initialization function is optional.  \n* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.  \n* To place an instance structure into a const data section, the instance structure must be manually initialized.  \n* Set the values in the state buffer to zeros before static initialization.  \n* The code below statically initializes each of the 4 different data type filter instance structures  \n* 
  \n*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  \n* 
  \n*  \n* where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;  \n* pCoeffs is the address of the coefficient buffer.  \n*  \n* \\par Fixed-Point Behavior  \n* Care must be taken when using the fixed-point versions of the FIR filter functions.  \n* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.  \n* Refer to the function specific documentation below for usage guidelines.  \n*/\n\n/**  \n* @addtogroup FIR  \n* @{  \n*/\n\n/**  \n*  \n* @param[in]  *S points to an instance of the floating-point FIR filter structure.  \n* @param[in]  *pSrc points to the block of input data.  \n* @param[out] *pDst points to the block of output data.  \n* @param[in]  blockSize number of samples to process per call.  \n* @return     none.  \n*  \n*/\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_fir_f32(\nconst arm_fir_instance_f32 * S,\nfloat32_t * pSrc,\nfloat32_t * pDst,\nuint32_t blockSize)\n{\n   float32_t *pState = S->pState;                 /* State pointer */\n   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n   float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */\n   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */\n   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */\n   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */\n   float32_t p0,p1,p2,p3,p4,p5,p6,p7;             /* Temporary product values */\n\n   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n   /* pStateCurnt points to the location where the new input data should be written */\n   pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n   /* Apply loop unrolling and compute 8 output values simultaneously.  \n    * The variables acc0 ... acc7 hold output values that are being computed:  \n    *  \n    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  \n    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  \n    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  \n    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  \n    */\n   blkCnt = blockSize >> 3;\n\n   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.  \n   ** a second loop below computes the remaining 1 to 7 samples. */\n   while(blkCnt > 0u)\n   {\n      /* Copy four new input samples into the state buffer */\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n\n      /* Set all accumulators to zero */\n      acc0 = 0.0f;\n      acc1 = 0.0f;\n      acc2 = 0.0f;\n      acc3 = 0.0f;\n      acc4 = 0.0f;\n      acc5 = 0.0f;\n      acc6 = 0.0f;\n      acc7 = 0.0f;\t\t\n\n      /* Initialize state pointer */\n      px = pState;\n\n      /* Initialize coeff pointer */\n      pb = (pCoeffs);\t\t\n   \n      /* This is separated from the others to avoid \n       * a call to __aeabi_memmove which would be slower\n       */\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n      *pStateCurnt++ = *pSrc++;\n\n      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */\n      x0 = *px++;\n      x1 = *px++;\n      x2 = *px++;\n      x3 = *px++;\n      x4 = *px++;\n      x5 = *px++;\n      x6 = *px++;\n\n      /* Loop unrolling.  Process 8 taps at a time. */\n      tapCnt = numTaps >> 3u;\n      \n      /* Loop over the number of taps.  Unroll by a factor of 8.  \n       ** Repeat until we've computed numTaps-8 coefficients. */\n      while(tapCnt > 0u)\n      {\n         /* Read the b[numTaps-1] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-3] sample */\n         x7 = *(px++);\n\n         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */\n         p0 = x0 * c0;\n\n         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */\n         p1 = x1 * c0;\n\n         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */\n         p2 = x2 * c0;\n\n         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */\n         p3 = x3 * c0;\n\n         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */\n         p4 = x4 * c0;\n\n         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */\n         p5 = x5 * c0;\n\n         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */\n         p6 = x6 * c0;\n\n         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */\n         p7 = x7 * c0;\n         \n         /* Read the b[numTaps-2] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-4] sample */\n         x0 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n\n         /* Perform the multiply-accumulate */\n         p0 = x1 * c0;\n         p1 = x2 * c0;   \n         p2 = x3 * c0;   \n         p3 = x4 * c0;   \n         p4 = x5 * c0;   \n         p5 = x6 * c0;   \n         p6 = x7 * c0;   \n         p7 = x0 * c0;   \n         \n         /* Read the b[numTaps-3] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-5] sample */\n         x1 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x2 * c0;\n         p1 = x3 * c0;   \n         p2 = x4 * c0;   \n         p3 = x5 * c0;   \n         p4 = x6 * c0;   \n         p5 = x7 * c0;   \n         p6 = x0 * c0;   \n         p7 = x1 * c0;   \n\n         /* Read the b[numTaps-4] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-6] sample */\n         x2 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x3 * c0;\n         p1 = x4 * c0;   \n         p2 = x5 * c0;   \n         p3 = x6 * c0;   \n         p4 = x7 * c0;   \n         p5 = x0 * c0;   \n         p6 = x1 * c0;   \n         p7 = x2 * c0;   \n\n         /* Read the b[numTaps-4] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-6] sample */\n         x3 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x4 * c0;\n         p1 = x5 * c0;   \n         p2 = x6 * c0;   \n         p3 = x7 * c0;   \n         p4 = x0 * c0;   \n         p5 = x1 * c0;   \n         p6 = x2 * c0;   \n         p7 = x3 * c0;   \n\n         /* Read the b[numTaps-4] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-6] sample */\n         x4 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x5 * c0;\n         p1 = x6 * c0;   \n         p2 = x7 * c0;   \n         p3 = x0 * c0;   \n         p4 = x1 * c0;   \n         p5 = x2 * c0;   \n         p6 = x3 * c0;   \n         p7 = x4 * c0;   \n\n         /* Read the b[numTaps-4] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-6] sample */\n         x5 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x6 * c0;\n         p1 = x7 * c0;   \n         p2 = x0 * c0;   \n         p3 = x1 * c0;   \n         p4 = x2 * c0;   \n         p5 = x3 * c0;   \n         p6 = x4 * c0;   \n         p7 = x5 * c0;   \n\n         /* Read the b[numTaps-4] coefficient */\n         c0 = *(pb++);\n\n         /* Read x[n-numTaps-6] sample */\n         x6 = *(px++);\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Perform the multiply-accumulates */      \n         p0 = x7 * c0;\n         p1 = x0 * c0;   \n         p2 = x1 * c0;   \n         p3 = x2 * c0;   \n         p4 = x3 * c0;   \n         p5 = x4 * c0;   \n         p6 = x5 * c0;   \n         p7 = x6 * c0;   \n\n         tapCnt--;\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n      }\n\n      /* If the filter length is not a multiple of 8, compute the remaining filter taps */\n      tapCnt = numTaps % 0x8u;\n\n      while(tapCnt > 0u)\n      {\n         /* Read coefficients */\n         c0 = *(pb++);\n\n         /* Fetch 1 state variable */\n         x7 = *(px++);\n\n         /* Perform the multiply-accumulates */      \n         p0 = x0 * c0;\n         p1 = x1 * c0;   \n         p2 = x2 * c0;   \n         p3 = x3 * c0;   \n         p4 = x4 * c0;   \n         p5 = x5 * c0;   \n         p6 = x6 * c0;   \n         p7 = x7 * c0;   \n\n         /* Reuse the present sample states for next sample */\n         x0 = x1;\n         x1 = x2;\n         x2 = x3;\n         x3 = x4;\n         x4 = x5;\n         x5 = x6;\n         x6 = x7;\n         \n         acc0 += p0;\n         acc1 += p1;\n         acc2 += p2;\n         acc3 += p3;\n         acc4 += p4;\n         acc5 += p5;\n         acc6 += p6;\n         acc7 += p7;\n\n         /* Decrement the loop counter */\n         tapCnt--;\n      }\n\n      /* Advance the state pointer by 8 to process the next group of 8 samples */\n      pState = pState + 8;\n\n      /* The results in the 8 accumulators, store in the destination buffer. */\n      *pDst++ = acc0;\n      *pDst++ = acc1;\n      *pDst++ = acc2;\n      *pDst++ = acc3;\n      *pDst++ = acc4;\n      *pDst++ = acc5;\n      *pDst++ = acc6;\n      *pDst++ = acc7;\n\n      blkCnt--;\n   }\n\n   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.  \n   ** No loop unrolling is used. */\n   blkCnt = blockSize % 0x8u;\n\n   while(blkCnt > 0u)\n   {\n      /* Copy one sample at a time into state buffer */\n      *pStateCurnt++ = *pSrc++;\n\n      /* Set the accumulator to zero */\n      acc0 = 0.0f;\n\n      /* Initialize state pointer */\n      px = pState;\n\n      /* Initialize Coefficient pointer */\n      pb = (pCoeffs);\n\n      i = numTaps;\n\n      /* Perform the multiply-accumulates */\n      do\n      {\n         acc0 += *px++ * *pb++;\n         i--;\n\n      } while(i > 0u);\n\n      /* The result is store in the destination buffer. */\n      *pDst++ = acc0;\n\n      /* Advance state pointer by 1 for the next sample */\n      pState = pState + 1;\n\n      blkCnt--;\n   }\n\n   /* Processing is complete.  \n   ** Now copy the last numTaps - 1 samples to the start of the state buffer.  \n   ** This prepares the state buffer for the next function call. */\n\n   /* Points to the start of the state buffer */\n   pStateCurnt = S->pState;\n\n   tapCnt = (numTaps - 1u) >> 2u;\n\n   /* copy data */\n   while(tapCnt > 0u)\n   {\n      *pStateCurnt++ = *pState++;\n      *pStateCurnt++ = *pState++;\n      *pStateCurnt++ = *pState++;\n      *pStateCurnt++ = *pState++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n   }\n\n   /* Calculate remaining number of copies */\n   tapCnt = (numTaps - 1u) % 0x4u;\n\n   /* Copy the remaining q31_t data */\n   while(tapCnt > 0u)\n   {\n      *pStateCurnt++ = *pState++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n   }\n}\n\n#else\n\nvoid arm_fir_f32(\nconst arm_fir_instance_f32 * S,\nfloat32_t * pSrc,\nfloat32_t * pDst,\nuint32_t blockSize)\n{\n   float32_t *pState = S->pState;                 /* State pointer */\n   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n   float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */\n   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */\n\n   /* Run the below code for Cortex-M0 */\n\n   float32_t acc;\n\n   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n   /* pStateCurnt points to the location where the new input data should be written */\n   pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n   /* Initialize blkCnt with blockSize */\n   blkCnt = blockSize;\n\n   while(blkCnt > 0u)\n   {\n      /* Copy one sample at a time into state buffer */\n      *pStateCurnt++ = *pSrc++;\n\n      /* Set the accumulator to zero */\n      acc = 0.0f;\n\n      /* Initialize state pointer */\n      px = pState;\n\n      /* Initialize Coefficient pointer */\n      pb = pCoeffs;\n\n      i = numTaps;\n\n      /* Perform the multiply-accumulates */\n      do\n      {\n         /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */\n         acc += *px++ * *pb++;\n         i--;\n\n      } while(i > 0u);\n\n      /* The result is store in the destination buffer. */\n      *pDst++ = acc;\n\n      /* Advance state pointer by 1 for the next sample */\n      pState = pState + 1;\n\n      blkCnt--;\n   }\n\n   /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n   /* Points to the start of the state buffer */\n   pStateCurnt = S->pState;\n\n   /* Copy numTaps number of values */\n   tapCnt = numTaps - 1u;\n\n   /* Copy data */\n   while(tapCnt > 0u)\n   {\n      *pStateCurnt++ = *pState++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n   }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n/**  \n* @} end of FIR group  \n*/\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_fast_q15.c    \n*    \n* Description:  Q15 Fast FIR filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @param[in] *S points to an instance of the Q15 FIR filter structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in] blockSize number of samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * This fast version uses a 32-bit accumulator with 2.30 format.    \n * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around and distorts the result.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    \n * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    \n *    \n * \\par    \n * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_fir_init_q15() to initialize the filter structure.    \n */\n\nvoid arm_fir_fast_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */\n  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.      \n   * The variables acc0 ... acc3 hold output values that are being computed:      \n   *      \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      \n   */\n\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy four new input samples into the state buffer.      \n     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */\n    px = pState;\n\n    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */\n    pb = pCoeffs;\n\n    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */\n    x0 = *__SIMD32(px)++;\n\n    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */\n    x2 = *__SIMD32(px)++;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.      \n     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0)\n    {\n      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */\n      acc0 = __SMLAD(x0, c0, acc0);\n\n      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */\n      acc2 = __SMLAD(x2, c0, acc2);\n\n      /* pack  x[n-N-1] and x[n-N-2] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* Read state x[n-N-4], x[n-N-5] */\n      x0 = _SIMD32_OFFSET(px);\n\n      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */\n      acc1 = __SMLADX(x1, c0, acc1);\n\n      /* pack  x[n-N-3] and x[n-N-4] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x0, x2, 0);\n#else\n      x1 = __PKHBT(x2, x0, 0);\n#endif\n\n      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */\n      acc3 = __SMLADX(x1, c0, acc3);\n\n      /* Read coefficients b[N-2], b[N-3] */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */\n      acc0 = __SMLAD(x2, c0, acc0);\n\n      /* Read state x[n-N-6], x[n-N-7] with offset */\n      x2 = _SIMD32_OFFSET(px + 2u);\n\n      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */\n      acc2 = __SMLAD(x0, c0, acc2);\n\n      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */\n      acc1 = __SMLADX(x1, c0, acc1);\n\n      /* pack  x[n-N-5] and x[n-N-6] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */\n      acc3 = __SMLADX(x1, c0, acc3);\n\n      /* Update state pointer for next state reading */\n      px += 4u;\n\n      /* Decrement tap count */\n      tapCnt--;\n\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       \n     ** This is always be 2 taps since the filter length is even. */\n    if((numTaps & 0x3u) != 0u)\n    {\n\n      /* Read last two coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Perform the multiply-accumulates */\n      acc0 = __SMLAD(x0, c0, acc0);\n      acc2 = __SMLAD(x2, c0, acc2);\n\n      /* pack state variables */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* Read last state variables */\n      x0 = *__SIMD32(px);\n\n      /* Perform the multiply-accumulates */\n      acc1 = __SMLADX(x1, c0, acc1);\n\n      /* pack state variables */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x0, x2, 0);\n#else\n      x1 = __PKHBT(x2, x0, 0);\n#endif\n\n      /* Perform the multiply-accumulates */\n      acc3 = __SMLADX(x1, c0, acc3);\n    }\n\n    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the 4 outputs in the destination buffer. */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n  while(blkCnt > 0u)\n  {\n    /* Copy two samples into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Use SIMD to hold states and coefficients */\n    px = pState;\n    pb = pCoeffs;\n\n    tapCnt = numTaps >> 1u;\n\n    do\n    {\n\n      acc0 += (q31_t) * px++ * *pb++;\n\t  acc0 += (q31_t) * px++ * *pb++;\n\n      tapCnt--;\n    }\n    while(tapCnt > 0u);\n\n    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.      \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculation of count for copying integer writes */\n  tapCnt = (numTaps - 1u) >> 2;\n\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    tapCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* copy remaining data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_fast_q31.c    \n*    \n* Description:\tProcessing function for the Q31 Fast FIR filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @param[in] *S points to an instance of the Q31 structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block output data.    \n * @param[in] blockSize number of samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    \n * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    \n * These intermediate results are added to a 2.30 accumulator.    \n * Finally, the accumulator is saturated and converted to a 1.31 result.    \n * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    \n *    \n * \\par    \n * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.    \n * Use the function arm_fir_init_q31() to initialize the filter structure.    \n */\n\nIAR_ONLY_LOW_OPTIMIZATION_ENTER\nvoid arm_fir_fast_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */\n  q31_t c0;                                      /* Temporary variable to hold coefficient value */\n  q31_t *px;                                     /* Temporary pointer for state */\n  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.    \n   * The variables acc0 ... acc3 hold output values that are being computed:    \n   *    \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    \n   */\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy four new input samples into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Read the first three samples from the state buffer:    \n     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */\n    x0 = *(px++);\n    x1 = *(px++);\n    x2 = *(px++);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n    i = tapCnt;\n\n    while(i > 0u)\n    {\n      /* Read the b[numTaps] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample */\n      x3 = *(px++);\n\n      /* acc0 +=  b[numTaps] * x[n-numTaps] */\n      multAcc_32x32_keep32_R(acc0, x0, c0);\n\n      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */\n      multAcc_32x32_keep32_R(acc1, x1, c0);\n\n      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */\n      multAcc_32x32_keep32_R(acc2, x2, c0);\n\n      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */\n      multAcc_32x32_keep32_R(acc3, x3, c0);\n\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulates */      \n      multAcc_32x32_keep32_R(acc0, x1, c0);\n      multAcc_32x32_keep32_R(acc1, x2, c0);\n      multAcc_32x32_keep32_R(acc2, x3, c0);\n      multAcc_32x32_keep32_R(acc3, x0, c0);\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-5] sample */\n      x1 = *(px++);\n\n      /* Perform the multiply-accumulates */      \n      multAcc_32x32_keep32_R(acc0, x2, c0);\n      multAcc_32x32_keep32_R(acc1, x3, c0);\n      multAcc_32x32_keep32_R(acc2, x0, c0);\n      multAcc_32x32_keep32_R(acc3, x1, c0);\n\n      /* Read the b[numTaps-3] coefficients */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-6] sample */\n      x2 = *(px++);\n\n      /* Perform the multiply-accumulates */      \n      multAcc_32x32_keep32_R(acc0, x3, c0);\n      multAcc_32x32_keep32_R(acc1, x0, c0);\n      multAcc_32x32_keep32_R(acc2, x1, c0);\n      multAcc_32x32_keep32_R(acc3, x2, c0);\n      i--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n\n    i = numTaps - (tapCnt * 4u);\n    while(i > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x3 = *(px++);\n\n      /* Perform the multiply-accumulates */      \n      multAcc_32x32_keep32_R(acc0, x0, c0);\n      multAcc_32x32_keep32_R(acc1, x1, c0);\n      multAcc_32x32_keep32_R(acc2, x2, c0);\n      multAcc_32x32_keep32_R(acc3, x3, c0);\n\n      /* Reuse the present sample states for next sample */\n      x0 = x1;\n      x1 = x2;\n      x2 = x3;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 4;\n\n    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31    \n     ** Then store the 4 outputs in the destination buffer. */\n    *pDst++ = (q31_t) (acc0 << 1);\n    *pDst++ = (q31_t) (acc1 << 1);\n    *pDst++ = (q31_t) (acc2 << 1);\n    *pDst++ = (q31_t) (acc3 << 1);\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize Coefficient pointer */\n    pb = (pCoeffs);\n\n    i = numTaps;\n\n    /* Perform the multiply-accumulates */\n    do\n    {\n      multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));\n      i--;\n    } while(i > 0u);\n\n    /* The result is in 2.30 format.  Convert to 1.31    \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q31_t) (acc0 << 1);\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.    \n   ** Now copy the last numTaps - 1 samples to the start of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n\n}\nIAR_ONLY_LOW_OPTIMIZATION_EXIT\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_init_f32.c    \n*    \n* Description:  Floating-point FIR filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in,out] *S points to an instance of the floating-point FIR filter structure.    \n * @param[in] \t  numTaps  Number of filter coefficients in the filter.    \n * @param[in]     *pCoeffs points to the filter coefficients buffer.    \n * @param[in]     *pState points to the state buffer.    \n * @param[in] \t  blockSize number of samples that are processed per call.    \n * @return \t\t  none.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().    \n */\n\nvoid arm_fir_init_f32(\n  arm_fir_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_init_q15.c    \n*    \n* Description:  Q15 FIR filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.    \n * @param[in] \t   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.    \n * @param[in]      *pCoeffs points to the filter coefficients buffer.    \n * @param[in]      *pState points to the state buffer.    \n * @param[in]      blockSize is number of samples processed per call.    \n * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if    \n * numTaps is not greater than or equal to 4 and even.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * Note that numTaps must be even and greater than or equal to 4.    \n * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.    \n * For example, to implement a filter with numTaps=3 and coefficients    \n * 
    \n *     {0.3, -0.8, 0.3}    \n * 
    \n * set numTaps=4 and use the coefficients:    \n * 
    \n *     {0.3, -0.8, 0.3, 0}.    \n * 
    \n * Similarly, to implement a two point filter    \n * 
    \n *     {0.3, -0.3}    \n * 
    \n * set numTaps=4 and use the coefficients:    \n * 
    \n *     {0.3, -0.3, 0, 0}.    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3  and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().    \n */\n\narm_status arm_fir_init_q15(\n  arm_fir_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* The Number of filter coefficients in the filter must be even and at least 4 */\n  if(numTaps & 0x1u)\n  {\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n  else\n  {\n    /* Assign filter taps */\n    S->numTaps = numTaps;\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */\n    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  status = ARM_MATH_SUCCESS;\n\n  return (status);\n\n#endif /*  #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_init_q31.c    \n*    \n* Description:\tQ31 FIR filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @details    \n *    \n * @param[in,out] *S points to an instance of the Q31 FIR filter structure.    \n * @param[in] \t  numTaps  Number of filter coefficients in the filter.    \n * @param[in] \t  *pCoeffs points to the filter coefficients buffer.    \n * @param[in] \t  *pState points to the state buffer.    \n * @param[in] \t  blockSize number of samples that are processed per call.    \n * @return        none.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().    \n */\n\nvoid arm_fir_init_q31(\n  arm_fir_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */\n  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_init_q7.c    \n*    \n* Description:  Q7 FIR filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n/**    \n * @param[in,out] *S points to an instance of the Q7 FIR filter structure.    \n * @param[in] \t  numTaps  Number of filter coefficients in the filter.    \n * @param[in] \t  *pCoeffs points to the filter coefficients buffer.    \n * @param[in]     *pState points to the state buffer.    \n * @param[in]     blockSize number of samples that are processed per call.    \n * @return     \t  none    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().    \n */\n\nvoid arm_fir_init_q7(\n  arm_fir_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  uint32_t blockSize)\n{\n\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_interpolate_f32.c    \n*    \n* Description:\tFIR interpolation for floating-point sequences.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator    \n *    \n * These functions combine an upsampler (zero stuffer) and an FIR filter.    \n * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.    \n * Conceptually, the functions are equivalent to the block diagram below:    \n * \\image html FIRInterpolator.gif \"Components included in the FIR Interpolator functions\"    \n * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized    \n * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.    \n * The user of the function is responsible for providing the filter coefficients.    \n *    \n * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.    \n * The upsampler inserts L-1 zeros between each sample.    \n * Instead of multiplying by these zero values, the FIR filter is designed to skip them.    \n * This leads to an efficient implementation without any wasted effort.    \n * The functions operate on blocks of input and output data.    \n * pSrc points to an array of blockSize input values and    \n * pDst points to an array of blockSize*L output values.    \n *    \n * The library provides separate functions for Q15, Q31, and floating-point data types.    \n *    \n * \\par Algorithm:    \n * The functions use a polyphase filter structure:    \n * 
    \n *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    \n *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    \n *    ...    \n *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    \n * 
    \n * This approach is more efficient than straightforward upsample-then-filter algorithms.    \n * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.    \n * \\par    \n * pCoeffs points to a coefficient array of size numTaps.    \n * numTaps must be a multiple of the interpolation factor L and this is checked by the    \n * initialization functions.    \n * Internally, the function divides the FIR filter's impulse response into shorter filters of length    \n * phaseLength=numTaps/L.    \n * Coefficients are stored in time reversed order.    \n * \\par    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to a state array of size blockSize + phaseLength - 1.    \n * Samples in the state buffer are stored in the order:    \n * \\par    \n * 
    \n *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    \n * 
    \n * The state variables are updated after each block of data is processed, the coefficients are untouched.    \n *    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * The code below statically initializes each of the 3 different data type filter instance structures    \n * 
    \n * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    \n * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    \n * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    \n * 
    \n * where L is the interpolation factor; phaseLength=numTaps/L is the    \n * length of each of the shorter FIR filters used internally,    \n * pCoeffs is the address of the coefficient buffer;    \n * pState is the address of the state buffer.    \n * Be sure to set the values in the state buffer to zeros when doing static initialization.    \n *    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the floating-point FIR interpolator.    \n * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.    \n * @param[in] *pSrc     points to the block of input data.    \n * @param[out] *pDst    points to the block of output data.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none.    \n */\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_fir_interpolate_f32(\n  const arm_fir_interpolate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */\n  float32_t sum0;                                /* Accumulators */\n  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */\n  uint32_t i, blkCnt, j;                         /* Loop counters */\n  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */\n  float32_t acc0, acc1, acc2, acc3;\n  float32_t x1, x2, x3;\n  uint32_t blkCntN4;\n  float32_t c1, c2, c3;\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (phaseLen - 1u);\n\n  /* Initialise  blkCnt */\n  blkCnt = blockSize / 4;\n  blkCntN4 = blockSize - (4 * blkCnt);\n\n  /* Samples loop unrolled by 4 */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = (S->L);\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      acc0 = 0.0f;\n      acc1 = 0.0f;\n      acc2 = 0.0f;\n      acc3 = 0.0f;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2u;\n\n      x0 = *(ptr1++);\n      x1 = *(ptr1++);\n      x2 = *(ptr1++);\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x3 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += x0 * c0;\n        acc1 += x1 * c0;\n        acc2 += x2 * c0;\n        acc3 += x3 * c0;\n\n        /* Read the coefficient */\n        c1 = *(ptr2 + S->L);\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += x1 * c1;\n        acc1 += x2 * c1;\n        acc2 += x3 * c1;\n        acc3 += x0 * c1;\n\n        /* Read the coefficient */\n        c2 = *(ptr2 + S->L * 2);\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += x2 * c2;\n        acc1 += x3 * c2;\n        acc2 += x0 * c2;\n        acc3 += x1 * c2;\n\n        /* Read the coefficient */\n        c3 = *(ptr2 + S->L * 3);\n\n        /* Read the input sample */\n        x2 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += x3 * c3;\n        acc1 += x0 * c3;\n        acc2 += x1 * c3;\n        acc3 += x2 * c3;\n\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += 4 * S->L;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen % 0x4u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x3 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += x0 * c0;\n        acc1 += x1 * c0;\n        acc2 += x2 * c0;\n        acc3 += x3 * c0;\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* update states for next sample processing */\n        x0 = x1;\n        x1 = x2;\n        x2 = x3;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst = acc0;\n      *(pDst + S->L) = acc1;\n      *(pDst + 2 * S->L) = acc2;\n      *(pDst + 3 * S->L) = acc3;\n\n      pDst++;\n\n      /* Increment the address modifier index of coefficient buffer */\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 4;\n\n    pDst += S->L * 3;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n\n  while(blkCntN4 > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum0 = 0.0f;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2u;\n      while(tapCnt > 0u)\n      {\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += x0 * c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += x0 * c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += x0 * c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += x0 * c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen % 0x4u;\n\n      while(tapCnt > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum0 += *(ptr1++) * (*ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst++ = sum0;\n\n      /* Increment the address modifier index of coefficient buffer */\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCntN4--;\n  }\n\n  /* Processing is complete.        \n   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = (phaseLen - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  tapCnt = (phaseLen - 1u) % 0x04u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n}\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\nvoid arm_fir_interpolate_f32(\n  const arm_fir_interpolate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */\n\n\n  float32_t sum;                                 /* Accumulator */\n  uint32_t i, blkCnt;                            /* Loop counters */\n  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */\n\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (phaseLen - 1u);\n\n  /* Total number of intput samples */\n  blkCnt = blockSize;\n\n  /* Loop over the blockSize. */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum = 0.0f;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (i - 1u);\n\n      /* Loop over the polyPhase length */\n      tapCnt = phaseLen;\n\n      while(tapCnt > 0u)\n      {\n        /* Perform the multiply-accumulate */\n        sum += *ptr1++ * *ptr2;\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst++ = sum;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1           \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = phaseLen - 1u;\n\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_interpolate_init_f32.c    \n*    \n* Description:  Floating-point FIR interpolator initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the floating-point FIR interpolator.    \n * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.    \n * @param[in]     L         upsample factor.    \n * @param[in]     numTaps   number of filter coefficients in the filter.    \n * @param[in]     *pCoeffs  points to the filter coefficient buffer.    \n * @param[in]     *pState   points to the state buffer.    \n * @param[in]     blockSize number of input samples to process per call.    \n * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * the filter length numTaps is not a multiple of the interpolation factor L.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n * 
    \n * The length of the filter numTaps must be a multiple of the interpolation factor L.    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length (numTaps/L)+blockSize-1 words    \n * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().    \n */\n\narm_status arm_fir_interpolate_init_f32(\n  arm_fir_interpolate_instance_f32 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n  /* The filter length must be a multiple of the interpolation factor */\n  if((numTaps % L) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Assign Interpolation factor */\n    S->L = L;\n\n    /* Assign polyPhaseLength */\n    S->phaseLength = numTaps / L;\n\n    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */\n    memset(pState, 0,\n           (blockSize +\n            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_interpolate_init_q15.c    \n*    \n* Description:  Q15 FIR interpolator initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n/**    \n * @brief  Initialization function for the Q15 FIR interpolator.    \n * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.    \n * @param[in]     L         upsample factor.    \n * @param[in]     numTaps   number of filter coefficients in the filter.    \n * @param[in]     *pCoeffs  points to the filter coefficient buffer.    \n * @param[in]     *pState   points to the state buffer.    \n * @param[in]     blockSize number of input samples to process per call.    \n * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * the filter length numTaps is not a multiple of the interpolation factor L.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n * 
    \n * The length of the filter numTaps must be a multiple of the interpolation factor L.    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length (numTaps/L)+blockSize-1 words    \n * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().    \n */\n\narm_status arm_fir_interpolate_init_q15(\n  arm_fir_interpolate_instance_q15 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n  /* The filter length must be a multiple of the interpolation factor */\n  if((numTaps % L) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Assign Interpolation factor */\n    S->L = L;\n\n    /* Assign polyPhaseLength */\n    S->phaseLength = numTaps / L;\n\n    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */\n    memset(pState, 0,\n           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_interpolate_init_q31.c    \n*    \n* Description:  Q31 FIR interpolator initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n\n/**    \n * @brief  Initialization function for the Q31 FIR interpolator.    \n * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.    \n * @param[in]     L         upsample factor.    \n * @param[in]     numTaps   number of filter coefficients in the filter.    \n * @param[in]     *pCoeffs  points to the filter coefficient buffer.    \n * @param[in]     *pState   points to the state buffer.    \n * @param[in]     blockSize number of input samples to process per call.    \n * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    \n * the filter length numTaps is not a multiple of the interpolation factor L.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n * 
    \n * The length of the filter numTaps must be a multiple of the interpolation factor L.    \n * \\par    \n * pState points to the array of state variables.    \n * pState is of length (numTaps/L)+blockSize-1 words    \n * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().    \n */\n\narm_status arm_fir_interpolate_init_q31(\n  arm_fir_interpolate_instance_q31 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize)\n{\n  arm_status status;\n\n  /* The filter length must be a multiple of the interpolation factor */\n  if((numTaps % L) != 0u)\n  {\n    /* Set status as ARM_MATH_LENGTH_ERROR */\n    status = ARM_MATH_LENGTH_ERROR;\n  }\n  else\n  {\n\n    /* Assign coefficient pointer */\n    S->pCoeffs = pCoeffs;\n\n    /* Assign Interpolation factor */\n    S->L = L;\n\n    /* Assign polyPhaseLength */\n    S->phaseLength = numTaps / L;\n\n    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */\n    memset(pState, 0,\n           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));\n\n    /* Assign state pointer */\n    S->pState = pState;\n\n    status = ARM_MATH_SUCCESS;\n  }\n\n  return (status);\n\n}\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fir_interpolate_q15.c    \n*    \n* Description:\tQ15 FIR interpolation.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 FIR interpolator.    \n * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.    \n * @param[in] *pSrc     points to the block of input data.    \n * @param[out] *pDst    points to the block of output data.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    \n * Lastly, the accumulator is saturated to yield a result in 1.15 format.    \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_fir_interpolate_q15(\n  const arm_fir_interpolate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer                                            */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */\n  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */\n  q63_t sum0;                                    /* Accumulators                                             */\n  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */\n  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */\n  uint32_t blkCntN2;\n  q63_t acc0, acc1;\n  q15_t x1;\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);\n\n  /* Initialise  blkCnt */\n  blkCnt = blockSize / 2;\n  blkCntN2 = blockSize - (2 * blkCnt);\n\n  /* Samples loop unrolled by 2 */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = (S->L);\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      acc0 = 0;\n      acc1 = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2u;\n\n      x0 = *(ptr1++);\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L);\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x1 *c0;\n        acc1 += (q63_t) x0 *c0;\n\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L * 2);\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L * 3);\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x1 *c0;\n        acc1 += (q63_t) x0 *c0;\n\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += 4 * S->L;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen % 0x4u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* update states for next sample processing */\n        x0 = x1;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));\n      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));\n\n      pDst++;\n\n      /* Increment the address modifier index of coefficient buffer */\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 2;\n\n    pDst += S->L;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = blkCntN2;\n\n  /* Loop over the blockSize. */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum0 = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2;\n      while(tapCnt > 0u)\n      {\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen & 0x3u;\n\n      while(tapCnt > 0u)\n      {\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));\n\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n  /* Processing is complete.    \n   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = ((uint32_t) phaseLen - 1u) >> 2u;\n\n  /* copy data */\n  while(i > 0u)\n  {\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n#else\n\n    *pStateCurnt++ = *pState++;\n\t*pStateCurnt++ = *pState++;\n\t*pStateCurnt++ = *pState++;\n\t*pStateCurnt++ = *pState++;\n\t\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\t\n\t/* Decrement the loop counter */\n    i--;\n  }\n\n  i = ((uint32_t) phaseLen - 1u) % 0x04u;\n\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n}\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\nvoid arm_fir_interpolate_q15(\n  const arm_fir_interpolate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer                                            */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */\n  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */\n  q63_t sum;                                     /* Accumulator */\n  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */\n  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */\n\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (phaseLen - 1u);\n\n  /* Total number of intput samples */\n  blkCnt = blockSize;\n\n  /* Loop over the blockSize. */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (i - 1u);\n\n      /* Loop over the polyPhase length */\n      tapCnt = (uint32_t) phaseLen;\n\n      while(tapCnt > 0u)\n      {\n        /* Read the coefficient */\n        c0 = *ptr2;\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *ptr1++;\n\n        /* Perform the multiply-accumulate */\n        sum += ((q31_t) x0 * c0);\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* Store the result after converting to 1.15 format in the destination buffer */\n      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1           \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  i = (uint32_t) phaseLen - 1u;\n\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fir_interpolate_q31.c    \n*    \n* Description:\tQ31 FIR interpolation.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Interpolate    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 FIR interpolator.    \n * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.    \n * @param[in] *pSrc     points to the block of input data.    \n * @param[out] *pDst    points to the block of output data.    \n * @param[in] blockSize number of input samples to process per call.    \n * @return none.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).    \n * since numTaps/L additions occur per output sample.    \n * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_fir_interpolate_q31(\n  const arm_fir_interpolate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */\n  q63_t sum0;                                    /* Accumulators */\n  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  uint32_t i, blkCnt, j;                         /* Loop counters */\n  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */\n\n  uint32_t blkCntN2;\n  q63_t acc0, acc1;\n  q31_t x1;\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);\n\n  /* Initialise  blkCnt */\n  blkCnt = blockSize / 2;\n  blkCntN2 = blockSize - (2 * blkCnt);\n\n  /* Samples loop unrolled by 2 */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = (S->L);\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      acc0 = 0;\n      acc1 = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2u;\n\n      x0 = *(ptr1++);\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L);\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x1 *c0;\n        acc1 += (q63_t) x0 *c0;\n\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L * 2);\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2 + S->L * 3);\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x1 *c0;\n        acc1 += (q63_t) x0 *c0;\n\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += 4 * S->L;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen % 0x4u;\n\n      while(tapCnt > 0u)\n      {\n\n        /* Read the input sample */\n        x1 = *(ptr1++);\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Perform the multiply-accumulate */\n        acc0 += (q63_t) x0 *c0;\n        acc1 += (q63_t) x1 *c0;\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* update states for next sample processing */\n        x0 = x1;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst = (q31_t) (acc0 >> 31);\n      *(pDst + S->L) = (q31_t) (acc1 >> 31);\n\n\n      pDst++;\n\n      /* Increment the address modifier index of coefficient buffer */\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 2;\n\n    pDst += S->L;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = blkCntN2;\n\n  /* Loop over the blockSize. */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Address modifier index of coefficient buffer */\n    j = 1u;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum0 = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (S->L - j);\n\n      /* Loop over the polyPhase length. Unroll by a factor of 4.        \n       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */\n      tapCnt = phaseLen >> 2;\n      while(tapCnt > 0u)\n      {\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Upsampling is done by stuffing L-1 zeros between each sample.        \n         * So instead of multiplying zeros with coefficients,        \n         * Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */\n      tapCnt = phaseLen & 0x3u;\n\n      while(tapCnt > 0u)\n      {\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *(ptr1++);\n\n        /* Perform the multiply-accumulate */\n        sum0 += (q63_t) x0 *c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst++ = (q31_t) (sum0 >> 31);\n\n      /* Increment the address modifier index of coefficient buffer */\n      j++;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1        \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.        \n   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = (phaseLen - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  tapCnt = (phaseLen - 1u) % 0x04u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n\n#else\n\nvoid arm_fir_interpolate_q31(\n  const arm_fir_interpolate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */\n\n  /* Run the below code for Cortex-M0 */\n\n  q63_t sum;                                     /* Accumulator */\n  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */\n  uint32_t i, blkCnt;                            /* Loop counters */\n  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */\n\n\n  /* S->pState buffer contains previous frame (phaseLen - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);\n\n  /* Total number of intput samples */\n  blkCnt = blockSize;\n\n  /* Loop over the blockSize. */\n  while(blkCnt > 0u)\n  {\n    /* Copy new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Loop over the Interpolation factor. */\n    i = S->L;\n\n    while(i > 0u)\n    {\n      /* Set accumulator to zero */\n      sum = 0;\n\n      /* Initialize state pointer */\n      ptr1 = pState;\n\n      /* Initialize coefficient pointer */\n      ptr2 = pCoeffs + (i - 1u);\n\n      tapCnt = phaseLen;\n\n      while(tapCnt > 0u)\n      {\n        /* Read the coefficient */\n        c0 = *(ptr2);\n\n        /* Increment the coefficient pointer by interpolation factor times. */\n        ptr2 += S->L;\n\n        /* Read the input sample */\n        x0 = *ptr1++;\n\n        /* Perform the multiply-accumulate */\n        sum += (q63_t) x0 *c0;\n\n        /* Decrement the loop counter */\n        tapCnt--;\n      }\n\n      /* The result is in the accumulator, store in the destination buffer. */\n      *pDst++ = (q31_t) (sum >> 31);\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 1           \n     * to process the next group of interpolation factor number samples */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = phaseLen - 1u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n /**    \n  * @} end of FIR_Interpolate group    \n  */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_lattice_f32.c    \n*    \n* Description:\tProcessing function for the floating-point FIR Lattice filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters    \n *    \n * This set of functions implements Finite Impulse Response (FIR) lattice filters    \n * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     \n * variety of adaptive filter applications.  The filter structure is feedforward and    \n * the net impulse response is finite length.    \n * The functions operate on blocks    \n * of input and output data and each call to the function processes    \n * blockSize samples through the filter.  pSrc and    \n * pDst point to input and output arrays containing blockSize values.    \n *    \n * \\par Algorithm:    \n * \\image html FIRLattice.gif \"Finite Impulse Response Lattice filter\"    \n * The following difference equation is implemented:    \n * 
    \n *    f0[n] = g0[n] = x[n]    \n *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    \n *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    \n *    y[n] = fM[n]    \n * 
    \n * \\par    \n * pCoeffs points to tha array of reflection coefficients of size numStages.    \n * Reflection Coefficients are stored in the following order.    \n * \\par    \n * 
    \n *    {k1, k2, ..., kM}    \n * 
    \n * where M is number of stages    \n * \\par    \n * pState points to a state array of size numStages.    \n * The state variables (g values) hold previous inputs and are stored in the following order.    \n * 
    \n *    {g0[n], g1[n], g2[n] ...gM-1[n]}    \n * 
    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numStages, pCoeffs, pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    \n * 
    \n *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    \n *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    \n *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    \n * 
    \n * \\par    \n * where numStages is the number of stages in the filter; pState is the address of the state buffer;    \n * pCoeffs is the address of the coefficient buffer.    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n\n  /**    \n   * @brief Processing function for the floating-point FIR lattice filter.    \n   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.    \n   * @param[in]  *pSrc     points to the block of input data.    \n   * @param[out] *pDst     points to the block of output data    \n   * @param[in]  blockSize number of samples to process.    \n   * @return none.    \n   */\n\nvoid arm_fir_lattice_f32(\n  const arm_fir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pState;                             /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *px;                                 /* temporary state pointer */\n  float32_t *pk;                                 /* temporary coefficient pointer */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */\n  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */\n  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */\n  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */\n  uint32_t numStages = S->numStages;             /* Number of stages in the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n\n  gcurr1 = 0.0f;\n  pState = &S->pState[0];\n\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n    /* Read two samples from input buffer */\n    /* f0(n) = x(n) */\n    fcurr1 = *pSrc++;\n    fcurr2 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Read g0(n-1) from state */\n    gcurr1 = *px;\n\n    /* Process first sample for first tap */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = fcurr1 + ((*pk) * gcurr1);\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (fcurr1 * (*pk)) + gcurr1;\n\n    /* Process second sample for first tap */\n    /* for sample 2 processing */\n    fnext2 = fcurr2 + ((*pk) * fcurr1);\n    gnext2 = (fcurr2 * (*pk)) + fcurr1;\n\n    /* Read next two samples from input buffer */\n    /* f0(n+2) = x(n+2) */\n    fcurr3 = *pSrc++;\n    fcurr4 = *pSrc++;\n\n    /* Copy only last input samples into the state buffer    \n       which will be used for next four samples processing */\n    *px++ = fcurr4;\n\n    /* Process third sample for first tap */\n    fnext3 = fcurr3 + ((*pk) * fcurr2);\n    gnext3 = (fcurr3 * (*pk)) + fcurr2;\n\n    /* Process fourth sample for first tap */\n    fnext4 = fcurr4 + ((*pk) * fcurr3);\n    gnext4 = (fcurr4 * (*pk++)) + fcurr3;\n\n    /* Update of f values for next coefficient set processing */\n    fcurr1 = fnext1;\n    fcurr2 = fnext2;\n    fcurr3 = fnext3;\n    fcurr4 = fnext4;\n\n    /* Loop unrolling.  Process 4 taps at a time . */\n    stageCnt = (numStages - 1u) >> 2u;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.    \n     ** Repeat until we've computed numStages-3 coefficients. */\n\n    /* Process 2nd, 3rd, 4th and 5th taps ... here */\n    while(stageCnt > 0u)\n    {\n      /* Read g1(n-1), g3(n-1) .... from state */\n      gcurr1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext4;\n\n      /* Process first sample for 2nd, 6th .. tap */\n      /* Sample processing for K2, K6.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext1 = fcurr1 + ((*pk) * gcurr1);\n      /* Process second sample for 2nd, 6th .. tap */\n      /* for sample 2 processing */\n      fnext2 = fcurr2 + ((*pk) * gnext1);\n      /* Process third sample for 2nd, 6th .. tap */\n      fnext3 = fcurr3 + ((*pk) * gnext2);\n      /* Process fourth sample for 2nd, 6th .. tap */\n      fnext4 = fcurr4 + ((*pk) * gnext3);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      /* Calculation of state values for next stage */\n      gnext4 = (fcurr4 * (*pk)) + gnext3;\n      gnext3 = (fcurr3 * (*pk)) + gnext2;\n      gnext2 = (fcurr2 * (*pk)) + gnext1;\n      gnext1 = (fcurr1 * (*pk++)) + gcurr1;\n\n\n      /* Read g2(n-1), g4(n-1) .... from state */\n      gcurr1 = *px;\n\n      /* save g2(n) in state buffer */\n      *px++ = gnext4;\n\n      /* Sample processing for K3, K7.... */\n      /* Process first sample for 3rd, 7th .. tap */\n      /* f3(n) = f2(n) +  K3 * g2(n-1) */\n      fcurr1 = fnext1 + ((*pk) * gcurr1);\n      /* Process second sample for 3rd, 7th .. tap */\n      fcurr2 = fnext2 + ((*pk) * gnext1);\n      /* Process third sample for 3rd, 7th .. tap */\n      fcurr3 = fnext3 + ((*pk) * gnext2);\n      /* Process fourth sample for 3rd, 7th .. tap */\n      fcurr4 = fnext4 + ((*pk) * gnext3);\n\n      /* Calculation of state values for next stage */\n      /* g3(n) = f2(n) * K3  +  g2(n-1) */\n      gnext4 = (fnext4 * (*pk)) + gnext3;\n      gnext3 = (fnext3 * (*pk)) + gnext2;\n      gnext2 = (fnext2 * (*pk)) + gnext1;\n      gnext1 = (fnext1 * (*pk++)) + gcurr1;\n\n\n      /* Read g1(n-1), g3(n-1) .... from state */\n      gcurr1 = *px;\n\n      /* save g3(n) in state buffer */\n      *px++ = gnext4;\n\n      /* Sample processing for K4, K8.... */\n      /* Process first sample for 4th, 8th .. tap */\n      /* f4(n) = f3(n) +  K4 * g3(n-1) */\n      fnext1 = fcurr1 + ((*pk) * gcurr1);\n      /* Process second sample for 4th, 8th .. tap */\n      /* for sample 2 processing */\n      fnext2 = fcurr2 + ((*pk) * gnext1);\n      /* Process third sample for 4th, 8th .. tap */\n      fnext3 = fcurr3 + ((*pk) * gnext2);\n      /* Process fourth sample for 4th, 8th .. tap */\n      fnext4 = fcurr4 + ((*pk) * gnext3);\n\n      /* g4(n) = f3(n) * K4  +  g3(n-1) */\n      /* Calculation of state values for next stage */\n      gnext4 = (fcurr4 * (*pk)) + gnext3;\n      gnext3 = (fcurr3 * (*pk)) + gnext2;\n      gnext2 = (fcurr2 * (*pk)) + gnext1;\n      gnext1 = (fcurr1 * (*pk++)) + gcurr1;\n\n      /* Read g2(n-1), g4(n-1) .... from state */\n      gcurr1 = *px;\n\n      /* save g4(n) in state buffer */\n      *px++ = gnext4;\n\n      /* Sample processing for K5, K9.... */\n      /* Process first sample for 5th, 9th .. tap */\n      /* f5(n) = f4(n) +  K5 * g4(n-1) */\n      fcurr1 = fnext1 + ((*pk) * gcurr1);\n      /* Process second sample for 5th, 9th .. tap */\n      fcurr2 = fnext2 + ((*pk) * gnext1);\n      /* Process third sample for 5th, 9th .. tap */\n      fcurr3 = fnext3 + ((*pk) * gnext2);\n      /* Process fourth sample for 5th, 9th .. tap */\n      fcurr4 = fnext4 + ((*pk) * gnext3);\n\n      /* Calculation of state values for next stage */\n      /* g5(n) = f4(n) * K5  +  g4(n-1) */\n      gnext4 = (fnext4 * (*pk)) + gnext3;\n      gnext3 = (fnext3 * (*pk)) + gnext2;\n      gnext2 = (fnext2 * (*pk)) + gnext1;\n      gnext1 = (fnext1 * (*pk++)) + gcurr1;\n\n      stageCnt--;\n    }\n\n    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */\n    stageCnt = (numStages - 1u) % 0x4u;\n\n    while(stageCnt > 0u)\n    {\n      gcurr1 = *px;\n\n      /* save g value in state buffer */\n      *px++ = gnext4;\n\n      /* Process four samples for last three taps here */\n      fnext1 = fcurr1 + ((*pk) * gcurr1);\n      fnext2 = fcurr2 + ((*pk) * gnext1);\n      fnext3 = fcurr3 + ((*pk) * gnext2);\n      fnext4 = fcurr4 + ((*pk) * gnext3);\n\n      /* g1(n) = f0(n) * K1  +  g0(n-1) */\n      gnext4 = (fcurr4 * (*pk)) + gnext3;\n      gnext3 = (fcurr3 * (*pk)) + gnext2;\n      gnext2 = (fcurr2 * (*pk)) + gnext1;\n      gnext1 = (fcurr1 * (*pk++)) + gcurr1;\n\n      /* Update of f values for next coefficient set processing */\n      fcurr1 = fnext1;\n      fcurr2 = fnext2;\n      fcurr3 = fnext3;\n      fcurr4 = fnext4;\n\n      stageCnt--;\n\n    }\n\n    /* The results in the 4 accumulators, store in the destination buffer. */\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr1;\n    *pDst++ = fcurr2;\n    *pDst++ = fcurr3;\n    *pDst++ = fcurr4;\n\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurr1 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g2(n) from state buffer */\n    gcurr1 = *px;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = fcurr1 + ((*pk) * gcurr1);\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (fcurr1 * (*pk++)) + gcurr1;\n\n    /* save g1(n) in state buffer */\n    *px++ = fcurr1;\n\n    /* f1(n) is saved in fcurr1    \n       for next stage processing */\n    fcurr1 = fnext1;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* read g2(n) from state buffer */\n      gcurr1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext1;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext1 = fcurr1 + ((*pk) * gcurr1);\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext1 = (fcurr1 * (*pk++)) + gcurr1;\n\n      /* f1(n) is saved in fcurr1    \n         for next stage processing */\n      fcurr1 = fnext1;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr1;\n\n    blkCnt--;\n\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */\n  uint32_t numStages = S->numStages;             /* Length of the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n\n  pState = &S->pState[0];\n\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = pCoeffs;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g0(n-1) from state buffer */\n    gcurr = *px;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext = fcurr + ((*pk) * gcurr);\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext = (fcurr * (*pk++)) + gcurr;\n\n    /* save f0(n) in state buffer */\n    *px++ = fcurr;\n\n    /* f1(n) is saved in fcurr            \n       for next stage processing */\n    fcurr = fnext;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* read g2(n) from state buffer */\n      gcurr = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext = fcurr + ((*pk) * gcurr);\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext = (fcurr * (*pk++)) + gcurr;\n\n      /* f1(n) is saved in fcurr1            \n         for next stage processing */\n      fcurr = fnext;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr;\n\n    blkCnt--;\n\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_lattice_init_f32.c    \n*    \n* Description:  Floating-point FIR Lattice filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n/**    \n * @brief Initialization function for the floating-point FIR lattice filter.    \n * @param[in] *S points to an instance of the floating-point FIR lattice structure.    \n * @param[in] numStages  number of filter stages.    \n * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    \n * @param[in] *pState points to the state buffer.  The array is of length numStages.    \n * @return none.    \n */\n\nvoid arm_fir_lattice_init_f32(\n  arm_fir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always numStages */\n  memset(pState, 0, (numStages) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_lattice_init_q15.c    \n*    \n* Description:  Q15 FIR Lattice filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for the Q15 FIR lattice filter.    \n   * @param[in] *S points to an instance of the Q15 FIR lattice structure.    \n   * @param[in] numStages  number of filter stages.    \n   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.     \n   * @param[in] *pState points to the state buffer.  The array is of length numStages.     \n   * @return none.    \n   */\n\nvoid arm_fir_lattice_init_q15(\n  arm_fir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always numStages */\n  memset(pState, 0, (numStages) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_lattice_init_q31.c    \n*    \n* Description:  Q31 FIR lattice filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for the Q31 FIR lattice filter.    \n   * @param[in] *S points to an instance of the Q31 FIR lattice structure.    \n   * @param[in] numStages  number of filter stages.    \n   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    \n   * @param[in] *pState points to the state buffer.   The array is of length numStages.    \n   * @return none.    \n   */\n\nvoid arm_fir_lattice_init_q31(\n  arm_fir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always numStages */\n  memset(pState, 0, (numStages) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_lattice_q15.c    \n*    \n* Description:\tQ15 FIR lattice filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n\n/**    \n * @brief Processing function for the Q15 FIR lattice filter.    \n * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.    \n * @param[in]  *pSrc     points to the block of input data.    \n * @param[out] *pDst     points to the block of output data    \n * @param[in]  blockSize number of samples to process.    \n * @return none.    \n */\n\nvoid arm_fir_lattice_q15(\n  const arm_fir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState;                                 /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *px;                                     /* temporary state pointer */\n  q15_t *pk;                                     /* temporary coefficient pointer */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */\n  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */\n  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */\n  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */\n  uint32_t numStages = S->numStages;             /* Number of stages in the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n\n  pState = &S->pState[0];\n\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n    /* Read two samples from input buffer */\n    /* f0(n) = x(n) */\n    fcurnt1 = *pSrc++;\n    fcurnt2 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Read g0(n-1) from state */\n    gcurnt1 = *px;\n\n    /* Process first sample for first tap */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n    fnext1 = __SSAT(fnext1, 16);\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;\n    gnext1 = __SSAT(gnext1, 16);\n\n    /* Process second sample for first tap */\n    /* for sample 2 processing */\n    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;\n    fnext2 = __SSAT(fnext2, 16);\n\n    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;\n    gnext2 = __SSAT(gnext2, 16);\n\n\n    /* Read next two samples from input buffer */\n    /* f0(n+2) = x(n+2) */\n    fcurnt3 = *pSrc++;\n    fcurnt4 = *pSrc++;\n\n    /* Copy only last input samples into the state buffer    \n       which is used for next four samples processing */\n    *px++ = (q15_t) fcurnt4;\n\n    /* Process third sample for first tap */\n    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;\n    fnext3 = __SSAT(fnext3, 16);\n    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;\n    gnext3 = __SSAT(gnext3, 16);\n\n    /* Process fourth sample for first tap */\n    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;\n    fnext4 = __SSAT(fnext4, 16);\n    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;\n    gnext4 = __SSAT(gnext4, 16);\n\n    /* Update of f values for next coefficient set processing */\n    fcurnt1 = fnext1;\n    fcurnt2 = fnext2;\n    fcurnt3 = fnext3;\n    fcurnt4 = fnext4;\n\n\n    /* Loop unrolling.  Process 4 taps at a time . */\n    stageCnt = (numStages - 1u) >> 2;\n\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.    \n     ** Repeat until we've computed numStages-3 coefficients. */\n\n    /* Process 2nd, 3rd, 4th and 5th taps ... here */\n    while(stageCnt > 0u)\n    {\n      /* Read g1(n-1), g3(n-1) .... from state */\n      gcurnt1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = (q15_t) gnext4;\n\n      /* Process first sample for 2nd, 6th .. tap */\n      /* Sample processing for K2, K6.... */\n      /* f1(n) = f0(n) +  K1 * g0(n-1) */\n      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n      fnext1 = __SSAT(fnext1, 16);\n\n\n      /* Process second sample for 2nd, 6th .. tap */\n      /* for sample 2 processing */\n      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;\n      fnext2 = __SSAT(fnext2, 16);\n      /* Process third sample for 2nd, 6th .. tap */\n      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;\n      fnext3 = __SSAT(fnext3, 16);\n      /* Process fourth sample for 2nd, 6th .. tap */\n      /* fnext4 = fcurnt4 + (*pk) * gnext3; */\n      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;\n      fnext4 = __SSAT(fnext4, 16);\n\n      /* g1(n) = f0(n) * K1  +  g0(n-1) */\n      /* Calculation of state values for next stage */\n      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;\n      gnext4 = __SSAT(gnext4, 16);\n      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;\n      gnext3 = __SSAT(gnext3, 16);\n\n      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;\n      gnext2 = __SSAT(gnext2, 16);\n\n      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n\n      /* Read g2(n-1), g4(n-1) .... from state */\n      gcurnt1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = (q15_t) gnext4;\n\n      /* Sample processing for K3, K7.... */\n      /* Process first sample for 3rd, 7th .. tap */\n      /* f3(n) = f2(n) +  K3 * g2(n-1) */\n      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;\n      fcurnt1 = __SSAT(fcurnt1, 16);\n\n      /* Process second sample for 3rd, 7th .. tap */\n      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;\n      fcurnt2 = __SSAT(fcurnt2, 16);\n\n      /* Process third sample for 3rd, 7th .. tap */\n      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;\n      fcurnt3 = __SSAT(fcurnt3, 16);\n\n      /* Process fourth sample for 3rd, 7th .. tap */\n      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;\n      fcurnt4 = __SSAT(fcurnt4, 16);\n\n      /* Calculation of state values for next stage */\n      /* g3(n) = f2(n) * K3  +  g2(n-1) */\n      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;\n      gnext4 = __SSAT(gnext4, 16);\n\n      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;\n      gnext3 = __SSAT(gnext3, 16);\n\n      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;\n      gnext2 = __SSAT(gnext2, 16);\n\n      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n      /* Read g1(n-1), g3(n-1) .... from state */\n      gcurnt1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = (q15_t) gnext4;\n\n      /* Sample processing for K4, K8.... */\n      /* Process first sample for 4th, 8th .. tap */\n      /* f4(n) = f3(n) +  K4 * g3(n-1) */\n      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n      fnext1 = __SSAT(fnext1, 16);\n\n      /* Process second sample for 4th, 8th .. tap */\n      /* for sample 2 processing */\n      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;\n      fnext2 = __SSAT(fnext2, 16);\n\n      /* Process third sample for 4th, 8th .. tap */\n      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;\n      fnext3 = __SSAT(fnext3, 16);\n\n      /* Process fourth sample for 4th, 8th .. tap */\n      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;\n      fnext4 = __SSAT(fnext4, 16);\n\n      /* g4(n) = f3(n) * K4  +  g3(n-1) */\n      /* Calculation of state values for next stage */\n      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;\n      gnext4 = __SSAT(gnext4, 16);\n\n      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;\n      gnext3 = __SSAT(gnext3, 16);\n\n      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;\n      gnext2 = __SSAT(gnext2, 16);\n      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n\n      /* Read g2(n-1), g4(n-1) .... from state */\n      gcurnt1 = *px;\n\n      /* save g4(n) in state buffer */\n      *px++ = (q15_t) gnext4;\n\n      /* Sample processing for K5, K9.... */\n      /* Process first sample for 5th, 9th .. tap */\n      /* f5(n) = f4(n) +  K5 * g4(n-1) */\n      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;\n      fcurnt1 = __SSAT(fcurnt1, 16);\n\n      /* Process second sample for 5th, 9th .. tap */\n      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;\n      fcurnt2 = __SSAT(fcurnt2, 16);\n\n      /* Process third sample for 5th, 9th .. tap */\n      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;\n      fcurnt3 = __SSAT(fcurnt3, 16);\n\n      /* Process fourth sample for 5th, 9th .. tap */\n      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;\n      fcurnt4 = __SSAT(fcurnt4, 16);\n\n      /* Calculation of state values for next stage */\n      /* g5(n) = f4(n) * K5  +  g4(n-1) */\n      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;\n      gnext4 = __SSAT(gnext4, 16);\n      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;\n      gnext3 = __SSAT(gnext3, 16);\n      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;\n      gnext2 = __SSAT(gnext2, 16);\n      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n      stageCnt--;\n    }\n\n    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */\n    stageCnt = (numStages - 1u) % 0x4u;\n\n    while(stageCnt > 0u)\n    {\n      gcurnt1 = *px;\n\n      /* save g value in state buffer */\n      *px++ = (q15_t) gnext4;\n\n      /* Process four samples for last three taps here */\n      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n      fnext1 = __SSAT(fnext1, 16);\n      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;\n      fnext2 = __SSAT(fnext2, 16);\n\n      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;\n      fnext3 = __SSAT(fnext3, 16);\n\n      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;\n      fnext4 = __SSAT(fnext4, 16);\n\n      /* g1(n) = f0(n) * K1  +  g0(n-1) */\n      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;\n      gnext4 = __SSAT(gnext4, 16);\n      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;\n      gnext3 = __SSAT(gnext3, 16);\n      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;\n      gnext2 = __SSAT(gnext2, 16);\n      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n      /* Update of f values for next coefficient set processing */\n      fcurnt1 = fnext1;\n      fcurnt2 = fnext2;\n      fcurnt3 = fnext3;\n      fcurnt4 = fnext4;\n\n      stageCnt--;\n\n    }\n\n    /* The results in the 4 accumulators, store in the destination buffer. */\n    /* y(n) = fN(n) */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);\n    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);\n\n#else\n\n    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);\n    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurnt1 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g2(n) from state buffer */\n    gcurnt1 = *px;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n    fnext1 = __SSAT(fnext1, 16);\n\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;\n    gnext1 = __SSAT(gnext1, 16);\n\n    /* save g1(n) in state buffer */\n    *px++ = (q15_t) fcurnt1;\n\n    /* f1(n) is saved in fcurnt1    \n       for next stage processing */\n    fcurnt1 = fnext1;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* read g2(n) from state buffer */\n      gcurnt1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = (q15_t) gnext1;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;\n      fnext1 = __SSAT(fnext1, 16);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;\n      gnext1 = __SSAT(gnext1, 16);\n\n\n      /* f1(n) is saved in fcurnt1    \n         for next stage processing */\n      fcurnt1 = fnext1;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = __SSAT(fcurnt1, 16);\n\n\n    blkCnt--;\n\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */\n  uint32_t numStages = S->numStages;             /* Length of the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n\n  pState = &S->pState[0];\n\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurnt = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g0(n-1) from state buffer */\n    gcurnt = *px;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;\n    fnext = __SSAT(fnext, 16);\n\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;\n    gnext = __SSAT(gnext, 16);\n\n    /* save f0(n) in state buffer */\n    *px++ = (q15_t) fcurnt;\n\n    /* f1(n) is saved in fcurnt            \n       for next stage processing */\n    fcurnt = fnext;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* read g1(n-1) from state buffer */\n      gcurnt = *px;\n\n      /* save g0(n-1) in state buffer */\n      *px++ = (q15_t) gnext;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;\n      fnext = __SSAT(fnext, 16);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;\n      gnext = __SSAT(gnext, 16);\n\n\n      /* f1(n) is saved in fcurnt            \n         for next stage processing */\n      fcurnt = fnext;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = __SSAT(fcurnt, 16);\n\n\n    blkCnt--;\n\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_lattice_q31.c    \n*    \n* Description:\tQ31 FIR lattice filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Lattice    \n * @{    \n */\n\n\n/**    \n * @brief Processing function for the Q31 FIR lattice filter.    \n * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.    \n * @param[in]  *pSrc     points to the block of input data.    \n * @param[out] *pDst     points to the block of output data    \n * @param[in]  blockSize number of samples to process.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.    \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_fir_lattice_q31(\n  const arm_fir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState;                                 /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *px;                                     /* temporary state pointer */\n  q31_t *pk;                                     /* temporary coefficient pointer */\n  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */\n  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */\n  uint32_t numStages = S->numStages;             /* Length of the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n  q31_t k;\n\n  pState = &S->pState[0];\n\n  blkCnt = blockSize >> 1u;\n\n  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.        \n     a second loop below computes the remaining 1 sample. */\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurr1 = *pSrc++;\n\n    /* f0(n) = x(n) */\n    fcurr2 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g0(n - 1) from state buffer */\n    gcurr1 = *px;\n\n    /* Read the reflection coefficient */\n    k = *pk++;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);\n    fnext1 = fcurr1 + (fnext1 << 1u);\n    gnext1 = gcurr1 + (gnext1 << 1u);\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);\n    fnext2 = fcurr2 + (fnext2 << 1u);\n    gnext2 = fcurr1 + (gnext2 << 1u);\n\n    /* save g1(n) in state buffer */\n    *px++ = fcurr2;\n\n    /* f1(n) is saved in fcurr1        \n       for next stage processing */\n    fcurr1 = fnext1;\n    fcurr2 = fnext2;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n\n      /* Read the reflection coefficient */\n      k = *pk++;\n\n      /* read g2(n) from state buffer */\n      gcurr1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext2;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);\n      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);\n\n      fnext1 = fcurr1 + (fnext1 << 1u);\n      fnext2 = fcurr2 + (fnext2 << 1u);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);\n      gnext2 = gnext1 + (gnext2 << 1u);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);\n      gnext1 = gcurr1 + (gnext1 << 1u);\n\n      /* f1(n) is saved in fcurr1        \n         for next stage processing */\n      fcurr1 = fnext1;\n      fcurr2 = fnext2;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr1;\n    *pDst++ = fcurr2;\n\n    blkCnt--;\n\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x2u;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurr1 = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g0(n - 1) from state buffer */\n    gcurr1 = *px;\n\n    /* Read the reflection coefficient */\n    k = *pk++;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);\n    fnext1 = fcurr1 + (fnext1 << 1u);\n\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);\n    gnext1 = gcurr1 + (gnext1 << 1u);\n\n    /* save g1(n) in state buffer */\n    *px++ = fcurr1;\n\n    /* f1(n) is saved in fcurr1        \n       for next stage processing */\n    fcurr1 = fnext1;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* Read the reflection coefficient */\n      k = *pk++;\n\n      /* read g2(n) from state buffer */\n      gcurr1 = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext1;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);\n      fnext1 = fcurr1 + (fnext1 << 1u);\n\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);\n      gnext1 = gcurr1 + (gnext1 << 1u);\n\n      /* f1(n) is saved in fcurr1        \n         for next stage processing */\n      fcurr1 = fnext1;\n\n      stageCnt--;\n\n    }\n\n\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr1;\n\n    blkCnt--;\n\n  }\n\n\n}\n\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\nvoid arm_fir_lattice_q31(\n  const arm_fir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState;                                 /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *px;                                     /* temporary state pointer */\n  q31_t *pk;                                     /* temporary coefficient pointer */\n  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */\n  uint32_t numStages = S->numStages;             /* Length of the filter */\n  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */\n\n  pState = &S->pState[0];\n\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* f0(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize coeff pointer */\n    pk = (pCoeffs);\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* read g0(n-1) from state buffer */\n    gcurr = *px;\n\n    /* for sample 1 processing */\n    /* f1(n) = f0(n) +  K1 * g0(n-1) */\n    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;\n    /* g1(n) = f0(n) * K1  +  g0(n-1) */\n    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;\n    /* save g1(n) in state buffer */\n    *px++ = fcurr;\n\n    /* f1(n) is saved in fcurr1            \n       for next stage processing */\n    fcurr = fnext;\n\n    stageCnt = (numStages - 1u);\n\n    /* stage loop */\n    while(stageCnt > 0u)\n    {\n      /* read g2(n) from state buffer */\n      gcurr = *px;\n\n      /* save g1(n) in state buffer */\n      *px++ = gnext;\n\n      /* Sample processing for K2, K3.... */\n      /* f2(n) = f1(n) +  K2 * g1(n-1) */\n      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;\n      /* g2(n) = f1(n) * K2  +  g1(n-1) */\n      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;\n\n      /* f1(n) is saved in fcurr1            \n         for next stage processing */\n      fcurr = fnext;\n\n      stageCnt--;\n\n    }\n\n    /* y(n) = fN(n) */\n    *pDst++ = fcurr;\n\n    blkCnt--;\n\n  }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n\n/**    \n * @} end of FIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_q15.c    \n*    \n* Description:  Q15 FIR filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**       \n * @ingroup groupFilters       \n */\n\n/**       \n * @addtogroup FIR       \n * @{       \n */\n\n/**       \n * @brief Processing function for the Q15 FIR filter.       \n * @param[in] *S points to an instance of the Q15 FIR structure.       \n * @param[in] *pSrc points to the block of input data.       \n * @param[out] *pDst points to the block of output data.       \n * @param[in]  blockSize number of samples to process per call.       \n * @return none.       \n *   \n *   \n * \\par Restrictions   \n *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   \n *\tIn this case input, output, state buffers should be aligned by 32-bit   \n *   \n * Scaling and Overflow Behavior:       \n * \\par       \n * The function is implemented using a 64-bit internal accumulator.       \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.       \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.       \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.       \n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.       \n * Lastly, the accumulator is saturated to yield a result in 1.15 format.       \n *       \n * \\par       \n * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.       \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n/* Run the below code for Cortex-M4 and Cortex-M3 */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n\nvoid arm_fir_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.       \n   * The variables acc0 ... acc3 hold output values that are being computed:       \n   *       \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]       \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]       \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]       \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]       \n   */\n\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy four new input samples into the state buffer.       \n     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Initialize state pointer of type q15 */\n    px1 = pState;\n\n    /* Initialize coeff pointer of type q31 */\n    pb = pCoeffs;\n\n    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */\n    x0 = _SIMD32_OFFSET(px1);\n\n    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */\n    x1 = _SIMD32_OFFSET(px1 + 1u);\n\n    px1 += 2u;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.       \n     ** Repeat until we've computed numTaps-4 coefficients. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */\n      acc0 = __SMLALD(x0, c0, acc0);\n\n      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */\n      acc1 = __SMLALD(x1, c0, acc1);\n\n      /* Read state x[n-N-2], x[n-N-3] */\n      x2 = _SIMD32_OFFSET(px1);\n\n      /* Read state x[n-N-3], x[n-N-4] */\n      x3 = _SIMD32_OFFSET(px1 + 1u);\n\n      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */\n      acc2 = __SMLALD(x2, c0, acc2);\n\n      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */\n      acc3 = __SMLALD(x3, c0, acc3);\n\n      /* Read coefficients b[N-2], b[N-3] */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */\n      acc0 = __SMLALD(x2, c0, acc0);\n\n      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */\n      acc1 = __SMLALD(x3, c0, acc1);\n\n      /* Read state x[n-N-4], x[n-N-5] */\n      x0 = _SIMD32_OFFSET(px1 + 2u);\n\n      /* Read state x[n-N-5], x[n-N-6] */\n      x1 = _SIMD32_OFFSET(px1 + 3u);\n\n      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */\n      acc2 = __SMLALD(x0, c0, acc2);\n\n      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */\n      acc3 = __SMLALD(x1, c0, acc3);\n\n      px1 += 4u;\n\n      tapCnt--;\n\n    }\n\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       \n     ** This is always be 2 taps since the filter length is even. */\n    if((numTaps & 0x3u) != 0u)\n    {\n      /* Read 2 coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Fetch 4 state variables */\n      x2 = _SIMD32_OFFSET(px1);\n\n      x3 = _SIMD32_OFFSET(px1 + 1u);\n\n      /* Perform the multiply-accumulates */\n      acc0 = __SMLALD(x0, c0, acc0);\n\n      px1 += 2u;\n\n      acc1 = __SMLALD(x1, c0, acc1);\n      acc2 = __SMLALD(x2, c0, acc2);\n      acc3 = __SMLALD(x3, c0, acc3);\n    }\n\n    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the 4 outputs in the destination buffer. */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */\n\n\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n  while(blkCnt > 0u)\n  {\n    /* Copy two samples into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Initialize state pointer of type q15 */\n    px1 = pState;\n\n    /* Initialize coeff pointer of type q31 */\n    pb = pCoeffs;\n\n    tapCnt = numTaps >> 1;\n\n    do\n    {\n\n      c0 = *__SIMD32(pb)++;\n      x0 = *__SIMD32(px1)++;\n\n      acc0 = __SMLALD(x0, c0, acc0);\n      tapCnt--;\n    }\n    while(tapCnt > 0u);\n\n    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.       \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculation of count for copying integer writes */\n  tapCnt = (numTaps - 1u) >> 2;\n\n  while(tapCnt > 0u)\n  {\n\n    /* Copy state values to start of state buffer */\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n    tapCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* copy remaining data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n}\n\n#else /* UNALIGNED_SUPPORT_DISABLE */\n\nvoid arm_fir_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */\n  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */\n  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.      \n   * The variables acc0 ... acc3 hold output values that are being computed:      \n   *      \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      \n   */\n\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy four new input samples into the state buffer.      \n     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */\n    px = pState;\n\n    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */\n    pb = pCoeffs;\n\n    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */\n    x0 = *__SIMD32(px)++;\n\n    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */\n    x2 = *__SIMD32(px)++;\n\n    /* Loop over the number of taps.  Unroll by a factor of 4.      \n     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0)\n    {\n      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */\n      acc0 = __SMLALD(x0, c0, acc0);\n\n      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */\n      acc2 = __SMLALD(x2, c0, acc2);\n\n      /* pack  x[n-N-1] and x[n-N-2] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* Read state x[n-N-4], x[n-N-5] */\n      x0 = _SIMD32_OFFSET(px);\n\n      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */\n      acc1 = __SMLALDX(x1, c0, acc1);\n\n      /* pack  x[n-N-3] and x[n-N-4] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x0, x2, 0);\n#else\n      x1 = __PKHBT(x2, x0, 0);\n#endif\n\n      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */\n      acc3 = __SMLALDX(x1, c0, acc3);\n\n      /* Read coefficients b[N-2], b[N-3] */\n      c0 = *__SIMD32(pb)++;\n\n      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */\n      acc0 = __SMLALD(x2, c0, acc0);\n\n      /* Read state x[n-N-6], x[n-N-7] with offset */\n      x2 = _SIMD32_OFFSET(px + 2u);\n\n      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */\n      acc2 = __SMLALD(x0, c0, acc2);\n\n      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */\n      acc1 = __SMLALDX(x1, c0, acc1);\n\n      /* pack  x[n-N-5] and x[n-N-6] */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */\n      acc3 = __SMLALDX(x1, c0, acc3);\n\n      /* Update state pointer for next state reading */\n      px += 4u;\n\n      /* Decrement tap count */\n      tapCnt--;\n\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       \n     ** This is always be 2 taps since the filter length is even. */\n    if((numTaps & 0x3u) != 0u)\n    {\n\n      /* Read last two coefficients */\n      c0 = *__SIMD32(pb)++;\n\n      /* Perform the multiply-accumulates */\n      acc0 = __SMLALD(x0, c0, acc0);\n      acc2 = __SMLALD(x2, c0, acc2);\n\n      /* pack state variables */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x2, x0, 0);\n#else\n      x1 = __PKHBT(x0, x2, 0);\n#endif\n\n      /* Read last state variables */\n      x0 = *__SIMD32(px);\n\n      /* Perform the multiply-accumulates */\n      acc1 = __SMLALDX(x1, c0, acc1);\n\n      /* pack state variables */\n#ifndef ARM_MATH_BIG_ENDIAN\n      x1 = __PKHBT(x0, x2, 0);\n#else\n      x1 = __PKHBT(x2, x0, 0);\n#endif\n\n      /* Perform the multiply-accumulates */\n      acc3 = __SMLALDX(x1, c0, acc3);\n    }\n\n    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       \n     ** Then store the 4 outputs in the destination buffer. */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);\n\n#else\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);\n\n    *__SIMD32(pDst)++ =\n      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n  while(blkCnt > 0u)\n  {\n    /* Copy two samples into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Use SIMD to hold states and coefficients */\n    px = pState;\n    pb = pCoeffs;\n\n    tapCnt = numTaps >> 1u;\n\n    do\n    {\n      acc0 += (q31_t) * px++ * *pb++;\n\t  acc0 += (q31_t) * px++ * *pb++;\n      tapCnt--;\n    }\n    while(tapCnt > 0u);\n\n    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.      \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculation of count for copying integer writes */\n  tapCnt = (numTaps - 1u) >> 2;\n\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    tapCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* copy remaining data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n}\n\n\n#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\n\n#else /* ARM_MATH_CM0_FAMILY */\n\n\n/* Run the below code for Cortex-M0 */\n\nvoid arm_fir_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n\n\n\n  q15_t *px;                                     /* Temporary pointer for state buffer */\n  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q63_t acc;                                     /* Accumulator */\n  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Initialize blkCnt with blockSize */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize Coefficient pointer */\n    pb = pCoeffs;\n\n    tapCnt = numTaps;\n\n    /* Perform the multiply-accumulates */\n    do\n    {\n      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */\n      acc += (q31_t) * px++ * *pb++;\n      tapCnt--;\n    } while(tapCnt > 0u);\n\n    /* The result is in 2.30 format.  Convert to 1.15         \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Copy numTaps number of values */\n  tapCnt = (numTaps - 1u);\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n\n\n/**       \n * @} end of FIR group       \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_q31.c    \n*    \n* Description:\tQ31 FIR filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @param[in] *S points to an instance of the Q31 FIR filter structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in] blockSize number of samples to process per call.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    \n * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.  \n *    \n * \\par    \n * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    \n */\n\nvoid arm_fir_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t x0, x1, x2;                              /* Temporary variables to hold state */\n  q31_t c0;                                      /* Temporary variable to hold coefficient value */\n  q31_t *px;                                     /* Temporary pointer for state */\n  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q63_t acc0, acc1, acc2;                        /* Accumulators */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.    \n   * The variables acc0 ... acc3 hold output values that are being computed:    \n   *    \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    \n   */\n  blkCnt = blockSize / 3;\n  blockSize = blockSize - (3 * blkCnt);\n\n  tapCnt = numTaps / 3;\n  tapCntN3 = numTaps - (3 * tapCnt);\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy three new input samples into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Read the first two samples from the state buffer:    \n     *  x[n-numTaps], x[n-numTaps-1] */\n    x0 = *(px++);\n    x1 = *(px++);\n\n    /* Loop unrolling.  Process 3 taps at a time. */\n    i = tapCnt;\n\n    while(i > 0u)\n    {\n      /* Read the b[numTaps] coefficient */\n      c0 = *pb;\n\n      /* Read x[n-numTaps-2] sample */\n      x2 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q63_t) x0 * c0);\n      acc1 += ((q63_t) x1 * c0);\n      acc2 += ((q63_t) x2 * c0);\n\n      /* Read the coefficient and state */\n      c0 = *(pb + 1u);\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q63_t) x1 * c0);\n      acc1 += ((q63_t) x2 * c0);\n      acc2 += ((q63_t) x0 * c0);\n\n      /* Read the coefficient and state */\n      c0 = *(pb + 2u);\n      x1 = *(px++);\n\n      /* update coefficient pointer */\n      pb += 3u;\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q63_t) x2 * c0);\n      acc1 += ((q63_t) x0 * c0);\n      acc2 += ((q63_t) x1 * c0);\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* If the filter length is not a multiple of 3, compute the remaining filter taps */\n\n    i = tapCntN3;\n\n    while(i > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x2 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q63_t) x0 * c0);\n      acc1 += ((q63_t) x1 * c0);\n      acc2 += ((q63_t) x2 * c0);\n\n      /* Reuse the present sample states for next sample */\n      x0 = x1;\n      x1 = x2;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 3 to process the next group of 3 samples */\n    pState = pState + 3;\n\n    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31    \n     ** Then store the 3 outputs in the destination buffer. */\n    *pDst++ = (q31_t) (acc0 >> 31u);\n    *pDst++ = (q31_t) (acc1 >> 31u);\n    *pDst++ = (q31_t) (acc2 >> 31u);\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n\n  while(blockSize > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize Coefficient pointer */\n    pb = (pCoeffs);\n\n    i = numTaps;\n\n    /* Perform the multiply-accumulates */\n    do\n    {\n      acc0 += (q63_t) * (px++) * (*(pb++));\n      i--;\n    } while(i > 0u);\n\n    /* The result is in 2.62 format.  Convert to 1.31    \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q31_t) (acc0 >> 31u);\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the samples loop counter */\n    blockSize--;\n  }\n\n  /* Processing is complete.    \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  q31_t *px;                                     /* Temporary pointer for state */\n  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  q63_t acc;                                     /* Accumulator */\n  uint32_t numTaps = S->numTaps;                 /* Length of the filter */\n  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */\n\n  /* S->pState buffer contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Initialize blkCnt with blockSize */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize Coefficient pointer */\n    pb = pCoeffs;\n\n    i = numTaps;\n\n    /* Perform the multiply-accumulates */\n    do\n    {\n      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */\n      acc += (q63_t) * px++ * *pb++;\n      i--;\n    } while(i > 0u);\n\n    /* The result is in 2.62 format.  Convert to 1.31         \n     ** Then store the output in the destination buffer. */\n    *pDst++ = (q31_t) (acc >> 31u);\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  /* Copy numTaps number of values */\n  tapCnt = numTaps - 1u;\n\n  /* Copy the data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n\n#endif /*  #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_q7.c    \n*    \n* Description:  Q7 FIR filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR    \n * @{    \n */\n\n/**    \n * @param[in]   *S points to an instance of the Q7 FIR filter structure.    \n * @param[in]   *pSrc points to the block of input data.    \n * @param[out]  *pDst points to the block of output data.    \n * @param[in]   blockSize number of samples to process per call.    \n * @return \tnone.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * The accumulator is converted to 18.7 format by discarding the low 7 bits.    \n * Finally, the result is truncated to 1.7 format.    \n */\n\nvoid arm_fir_q7(\n  const arm_fir_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t *pState = S->pState;                      /* State pointer */\n  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */\n  q7_t *pStateCurnt;                             /* Points to the current sample of the state */\n  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */\n  q7_t c0;                                       /* Temporary variable to hold coefficient value */\n  q7_t *px;                                      /* Temporary pointer for state */\n  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */\n  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Apply loop unrolling and compute 4 output values simultaneously.    \n   * The variables acc0 ... acc3 hold output values that are being computed:    \n   *    \n   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    \n   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    \n   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    \n   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    \n   */\n  blkCnt = blockSize >> 2;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Copy four new input samples into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set all accumulators to zero */\n    acc0 = 0;\n    acc1 = 0;\n    acc2 = 0;\n    acc3 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Read the first three samples from the state buffer:    \n     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */\n    x0 = *(px++);\n    x1 = *(px++);\n    x2 = *(px++);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n    i = tapCnt;\n\n    while(i > 0u)\n    {\n      /* Read the b[numTaps] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-3] sample */\n      x3 = *(px++);\n\n      /* acc0 +=  b[numTaps] * x[n-numTaps] */\n      acc0 += ((q15_t) x0 * c0);\n\n      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */\n      acc1 += ((q15_t) x1 * c0);\n\n      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */\n      acc2 += ((q15_t) x2 * c0);\n\n      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */\n      acc3 += ((q15_t) x3 * c0);\n\n      /* Read the b[numTaps-1] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-4] sample */\n      x0 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q15_t) x1 * c0);\n      acc1 += ((q15_t) x2 * c0);\n      acc2 += ((q15_t) x3 * c0);\n      acc3 += ((q15_t) x0 * c0);\n\n      /* Read the b[numTaps-2] coefficient */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-5] sample */\n      x1 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q15_t) x2 * c0);\n      acc1 += ((q15_t) x3 * c0);\n      acc2 += ((q15_t) x0 * c0);\n      acc3 += ((q15_t) x1 * c0);\n      /* Read the b[numTaps-3] coefficients */\n      c0 = *(pb++);\n\n      /* Read x[n-numTaps-6] sample */\n      x2 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q15_t) x3 * c0);\n      acc1 += ((q15_t) x0 * c0);\n      acc2 += ((q15_t) x1 * c0);\n      acc3 += ((q15_t) x2 * c0);\n      i--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n\n    i = numTaps - (tapCnt * 4u);\n    while(i > 0u)\n    {\n      /* Read coefficients */\n      c0 = *(pb++);\n\n      /* Fetch 1 state variable */\n      x3 = *(px++);\n\n      /* Perform the multiply-accumulates */\n      acc0 += ((q15_t) x0 * c0);\n      acc1 += ((q15_t) x1 * c0);\n      acc2 += ((q15_t) x2 * c0);\n      acc3 += ((q15_t) x3 * c0);\n\n      /* Reuse the present sample states for next sample */\n      x0 = x1;\n      x1 = x2;\n      x2 = x3;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 4;\n\n    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31    \n     ** Then store the 4 outputs in the destination buffer. */\n    acc0 = __SSAT((acc0 >> 7u), 8);\n    *pDst++ = acc0;\n    acc1 = __SSAT((acc1 >> 7u), 8);\n    *pDst++ = acc1;\n    acc2 = __SSAT((acc2 >> 7u), 8);\n    *pDst++ = acc2;\n    acc3 = __SSAT((acc3 >> 7u), 8);\n    *pDst++ = acc3;\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set the accumulator to zero */\n    acc0 = 0;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize Coefficient pointer */\n    pb = (pCoeffs);\n\n    i = numTaps;\n\n    /* Perform the multiply-accumulates */\n    do\n    {\n      acc0 += (q15_t) * (px++) * (*(pb++));\n      i--;\n    } while(i > 0u);\n\n    /* The result is in 2.14 format.  Convert to 1.7    \n     ** Then store the output in the destination buffer. */\n    *pDst++ = __SSAT((acc0 >> 7u), 8);\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the samples loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.    \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    \n   ** This prepares the state buffer for the next function call. */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */\n  uint32_t i, blkCnt;                            /* Loop counters */\n  q7_t *pState = S->pState;                      /* State pointer */\n  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */\n  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */\n  q31_t acc = 0;                                 /* Accumlator */\n  q7_t *pStateCurnt;                             /* Points to the current sample of the state */\n\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = S->pState + (numTaps - 1u);\n\n  /* Initialize blkCnt with blockSize */\n  blkCnt = blockSize;\n\n  /* Perform filtering upto BlockSize - BlockSize%4  */\n  while(blkCnt > 0u)\n  {\n    /* Copy one sample at a time into state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Set accumulator to zero */\n    acc = 0;\n\n    /* Initialize state pointer of type q7 */\n    px = pState;\n\n    /* Initialize coeff pointer of type q7 */\n    pb = pCoeffs;\n\n\n    i = numTaps;\n\n    while(i > 0u)\n    {\n      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */\n      acc += (q15_t) * px++ * *pb++;\n      i--;\n    }\n\n    /* Store the 1.7 format filter output in destination buffer */\n    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);\n\n    /* Advance the state pointer by 1 to process the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete.         \n   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       \n   ** This prepares the state buffer for the next function call. */\n\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = S->pState;\n\n\n  /* Copy numTaps number of values */\n  i = (numTaps - 1u);\n\n  /* Copy q7_t data */\n  while(i > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    i--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_sparse_f32.c    \n*    \n* Description:\tFloating-point sparse FIR filter processing function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters    \n *    \n * This group of functions implements sparse FIR filters.     \n * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.   \n * Sparse filters are used for simulating reflections in communications and audio applications.   \n *   \n * There are separate functions for Q7, Q15, Q31, and floating-point data types.    \n * The functions operate on blocks  of input and output data and each call to the function processes    \n * blockSize samples through the filter.  pSrc and    \n * pDst points to input and output arrays respectively containing blockSize values.    \n *    \n * \\par Algorithm:    \n * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.   \n * This is in addition to the coefficient array b.   \n * The implementation essentially skips the multiplications by zero and leads to an efficient realization.   \n * 
   \n *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    \n * 
    \n * \\par    \n * \\image html FIRSparse.gif \"Sparse FIR filter.  b[n] represents the filter coefficients\"   \n * \\par    \n * pCoeffs points to a coefficient array of size numTaps;    \n * pTapDelay points to an array of nonzero indices and is also of size numTaps;   \n * pState points to a state array of size maxDelay + blockSize, where   \n * maxDelay is the largest offset value that is ever used in the pTapDelay array.   \n * Some of the processing functions also require temporary working buffers.   \n *   \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.    \n * There are separate instance structure declarations for each of the 4 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros before static initialization.    \n * The code below statically initializes each of the 4 different data type filter instance structures    \n * 
    \n *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n * 
    \n * \\par    \n *    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief Processing function for the floating-point sparse FIR filter.   \n * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.   \n * @param[in]  *pSrc       points to the block of input data.   \n * @param[out] *pDst       points to the block of output data   \n * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   \n * @param[in]  blockSize   number of input samples to process per call.   \n * @return none.   \n */\n\nvoid arm_fir_sparse_f32(\n  arm_fir_sparse_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  float32_t * pScratchIn,\n  uint32_t blockSize)\n{\n\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *px;                                 /* Scratch buffer pointer */\n  float32_t *py = pState;                        /* Temporary pointers for state buffer */\n  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */\n  float32_t *pOut;                               /* Destination pointer */\n  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */\n  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */\n  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */\n  int32_t readIndex;                             /* Read index of the state buffer */\n  uint32_t tapCnt, blkCnt;                       /* loop counters */\n  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */\n\n\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,\n                        (int32_t *) pSrc, 1, blockSize);\n\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                       blockSize);\n\n  /* Working pointer for the scratch buffer */\n  px = pb;\n\n  /* Working pointer for destination buffer */\n  pOut = pDst;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Loop over the blockSize. Unroll by a factor of 4.    \n   * Compute 4 Multiplications at a time. */\n  blkCnt = blockSize >> 2u;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in destination buffer */\n    *pOut++ = *px++ * coeff;\n    *pOut++ = *px++ * coeff;\n    *pOut++ = *px++ * coeff;\n    *pOut++ = *px++ * coeff;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n   * compute the remaining samples */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in destination buffer */\n    *pOut++ = *px++ * coeff;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and    \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                         blockSize);\n\n    /* Working pointer for the scratch buffer */\n    px = pb;\n\n    /* Working pointer for destination buffer */\n    pOut = pDst;\n\n    /* Loop over the blockSize. Unroll by a factor of 4.    \n     * Compute 4 MACS at a time. */\n    blkCnt = blockSize >> 2u;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pOut++ += *px++ * coeff;\n      *pOut++ += *px++ * coeff;\n      *pOut++ += *px++ * coeff;\n      *pOut++ += *px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4,    \n     * compute the remaining samples */\n    blkCnt = blockSize % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pOut++ += *px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and    \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = ((int32_t) S->stateIndex -\n                 (int32_t) blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n#else\n\n/* Run the below code for Cortex-M0 */\n\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in destination buffer */\n    *pOut++ = *px++ * coeff;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and           \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                         blockSize);\n\n    /* Working pointer for the scratch buffer */\n    px = pb;\n\n    /* Working pointer for destination buffer */\n    pOut = pDst;\n\n    blkCnt = blockSize;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pOut++ += *px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and           \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex =\n      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_sparse_init_f32.c    \n*    \n* Description:\tFloating-point sparse FIR filter initialization function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief  Initialization function for the floating-point sparse FIR filter.   \n * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.   \n * @param[in]     numTaps    number of nonzero coefficients in the filter.   \n * @param[in]     *pCoeffs   points to the array of filter coefficients.   \n * @param[in]     *pState    points to the state buffer.   \n * @param[in]     *pTapDelay points to the array of offset times.   \n * @param[in]     maxDelay   maximum offset time supported.   \n * @param[in]     blockSize  number of samples that will be processed per block.   \n * @return none   \n *    \n * Description:    \n * \\par    \n * pCoeffs holds the filter coefficients and has length numTaps.    \n * pState holds the filter's state variables and must be of length    \n * maxDelay + blockSize, where maxDelay    \n * is the maximum number of delay line values.    \n * blockSize is the    \n * number of samples processed by the arm_fir_sparse_f32() function.    \n */\n\nvoid arm_fir_sparse_init_f32(\n  arm_fir_sparse_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Assign TapDelay pointer */\n  S->pTapDelay = pTapDelay;\n\n  /* Assign MaxDelay */\n  S->maxDelay = maxDelay;\n\n  /* reset the stateIndex to 0 */\n  S->stateIndex = 0u;\n\n  /* Clear state buffer and size is always maxDelay + blockSize */\n  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_sparse_init_q15.c    \n*    \n* Description:\tQ15 sparse FIR filter initialization function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief  Initialization function for the Q15 sparse FIR filter.   \n * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.   \n * @param[in]     numTaps    number of nonzero coefficients in the filter.   \n * @param[in]     *pCoeffs   points to the array of filter coefficients.   \n * @param[in]     *pState    points to the state buffer.   \n * @param[in]     *pTapDelay points to the array of offset times.   \n * @param[in]     maxDelay   maximum offset time supported.   \n * @param[in]     blockSize  number of samples that will be processed per block.   \n * @return none   \n *    \n * Description:    \n * \\par    \n * pCoeffs holds the filter coefficients and has length numTaps.    \n * pState holds the filter's state variables and must be of length    \n * maxDelay + blockSize, where maxDelay    \n * is the maximum number of delay line values.    \n * blockSize is the    \n * number of words processed by arm_fir_sparse_q15() function.    \n */\n\nvoid arm_fir_sparse_init_q15(\n  arm_fir_sparse_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Assign TapDelay pointer */\n  S->pTapDelay = pTapDelay;\n\n  /* Assign MaxDelay */\n  S->maxDelay = maxDelay;\n\n  /* reset the stateIndex to 0 */\n  S->stateIndex = 0u;\n\n  /* Clear state buffer and size is always maxDelay + blockSize */\n  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_sparse_init_q31.c    \n*    \n* Description:\tQ31 sparse FIR filter initialization function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief  Initialization function for the Q31 sparse FIR filter.   \n * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.   \n * @param[in]     numTaps    number of nonzero coefficients in the filter.   \n * @param[in]     *pCoeffs   points to the array of filter coefficients.   \n * @param[in]     *pState    points to the state buffer.   \n * @param[in]     *pTapDelay points to the array of offset times.   \n * @param[in]     maxDelay   maximum offset time supported.   \n * @param[in]     blockSize  number of samples that will be processed per block.   \n * @return none   \n *    \n * Description:    \n * \\par    \n * pCoeffs holds the filter coefficients and has length numTaps.    \n * pState holds the filter's state variables and must be of length    \n * maxDelay + blockSize, where maxDelay    \n * is the maximum number of delay line values.    \n * blockSize is the number of words processed by arm_fir_sparse_q31() function.    \n */\n\nvoid arm_fir_sparse_init_q31(\n  arm_fir_sparse_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Assign TapDelay pointer */\n  S->pTapDelay = pTapDelay;\n\n  /* Assign MaxDelay */\n  S->maxDelay = maxDelay;\n\n  /* reset the stateIndex to 0 */\n  S->stateIndex = 0u;\n\n  /* Clear state buffer and size is always maxDelay + blockSize */\n  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_fir_sparse_init_q7.c    \n*    \n* Description:\tQ7 sparse FIR filter initialization function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE. \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief  Initialization function for the Q7 sparse FIR filter.   \n * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.   \n * @param[in]     numTaps    number of nonzero coefficients in the filter.   \n * @param[in]     *pCoeffs   points to the array of filter coefficients.   \n * @param[in]     *pState    points to the state buffer.   \n * @param[in]     *pTapDelay points to the array of offset times.   \n * @param[in]     maxDelay   maximum offset time supported.   \n * @param[in]     blockSize  number of samples that will be processed per block.   \n * @return none   \n *    \n * Description:    \n * \\par    \n * pCoeffs holds the filter coefficients and has length numTaps.    \n * pState holds the filter's state variables and must be of length    \n * maxDelay + blockSize, where maxDelay    \n * is the maximum number of delay line values.    \n * blockSize is the    \n * number of samples processed by the arm_fir_sparse_q7() function.    \n */\n\nvoid arm_fir_sparse_init_q7(\n  arm_fir_sparse_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Assign TapDelay pointer */\n  S->pTapDelay = pTapDelay;\n\n  /* Assign MaxDelay */\n  S->maxDelay = maxDelay;\n\n  /* reset the stateIndex to 0 */\n  S->stateIndex = 0u;\n\n  /* Clear state buffer and size is always maxDelay + blockSize */\n  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_sparse_q15.c    \n*    \n* Description:\tQ15 sparse FIR filter processing function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief Processing function for the Q15 sparse FIR filter.   \n * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.   \n * @param[in]  *pSrc        points to the block of input data.   \n * @param[out] *pDst        points to the block of output data   \n * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   \n * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   \n * @param[in]  blockSize    number of input samples to process per call.   \n * @return none.   \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 32-bit accumulator.   \n * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.   \n * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.   \n * If the accumulator result overflows it will wrap around rather than saturate.   \n * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.    \n * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   \n */\n\n\nvoid arm_fir_sparse_q15(\n  arm_fir_sparse_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  q15_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize)\n{\n\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pIn = pSrc;                             /* Working pointer for input */\n  q15_t *pOut = pDst;                            /* Working pointer for output */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *px;                                     /* Temporary pointers for scratch buffer */\n  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */\n  q15_t *py = pState;                            /* Temporary pointers for state buffer */\n  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */\n  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */\n  uint16_t numTaps = S->numTaps;                 /* Filter order */\n  int32_t readIndex;                             /* Read index of the state buffer */\n  uint32_t tapCnt, blkCnt;                       /* loop counters */\n  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */\n  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in1, in2;                                /* Temporary variables */\n\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);\n\n  /* Loop over the number of taps. */\n  tapCnt = numTaps;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_q15(py, delaySize, &readIndex, 1,\n                       pb, pb, blockSize, 1, blockSize);\n\n  /* Working pointer for the scratch buffer of state values */\n  px = pb;\n\n  /* Working pointer for scratch buffer of output values */\n  pScratchOut = pScr2;\n\n  /* Loop over the blockSize. Unroll by a factor of 4.    \n   * Compute 4 multiplications at a time. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n   * compute the remaining samples */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and    \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_q15(py, delaySize, &readIndex, 1,\n                         pb, pb, blockSize, 1, blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pScratchOut = pScr2;\n\n    /* Loop over the blockSize. Unroll by a factor of 4.    \n     * Compute 4 MACS at a time. */\n    blkCnt = blockSize >> 2;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4,    \n     * compute the remaining samples */\n    blkCnt = blockSize % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and    \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* All the output values are in pScratchOut buffer.    \n     Convert them into 1.15 format, saturate and store in the destination buffer. */\n  /* Loop over the blockSize. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    in1 = *pScr2++;\n    in2 = *pScr2++;\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pOut)++ =\n      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),\n              16);\n\n#else\n    *__SIMD32(pOut)++ =\n      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),\n              16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n    in1 = *pScr2++;\n\n    in2 = *pScr2++;\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pOut)++ =\n      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),\n              16);\n\n#else\n\n    *__SIMD32(pOut)++ =\n      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),\n              16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n\n    blkCnt--;\n\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n     remaining samples are processed in the below loop */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);\n\n  /* Loop over the number of taps. */\n  tapCnt = numTaps;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_q15(py, delaySize, &readIndex, 1,\n                       pb, pb, blockSize, 1, blockSize);\n\n  /* Working pointer for the scratch buffer of state values */\n  px = pb;\n\n  /* Working pointer for scratch buffer of output values */\n  pScratchOut = pScr2;\n\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and           \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_q15(py, delaySize, &readIndex, 1,\n                         pb, pb, blockSize, 1, blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pScratchOut = pScr2;\n\n    blkCnt = blockSize;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      *pScratchOut++ += (q31_t) * px++ * coeff;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and           \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* All the output values are in pScratchOut buffer.       \n     Convert them into 1.15 format, saturate and store in the destination buffer. */\n  /* Loop over the blockSize. */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);\n    blkCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_sparse_q31.c    \n*    \n* Description:\tQ31 sparse FIR filter processing function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n/**   \n * @brief Processing function for the Q31 sparse FIR filter.   \n * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.   \n * @param[in]  *pSrc       points to the block of input data.   \n * @param[out] *pDst       points to the block of output data   \n * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   \n * @param[in]  blockSize   number of input samples to process per call.   \n * @return none.   \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 32-bit accumulator.   \n * The 1.31 x 1.31 multiplications are truncated to 2.30 format.   \n * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.    \n * If the accumulator result overflows, it wraps around rather than saturate.   \n * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   \n */\n\nvoid arm_fir_sparse_q31(\n  arm_fir_sparse_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  q31_t * pScratchIn,\n  uint32_t blockSize)\n{\n\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *px;                                     /* Scratch buffer pointer */\n  q31_t *py = pState;                            /* Temporary pointers for state buffer */\n  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */\n  q31_t *pOut;                                   /* Destination pointer */\n  q63_t out;                                     /* Temporary output variable */\n  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */\n  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */\n  uint16_t numTaps = S->numTaps;                 /* Filter order */\n  int32_t readIndex;                             /* Read index of the state buffer */\n  uint32_t tapCnt, blkCnt;                       /* loop counters */\n  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */\n  q31_t in;\n\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,\n                        (int32_t *) pSrc, 1, blockSize);\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                       blockSize);\n\n  /* Working pointer for the scratch buffer of state values */\n  px = pb;\n\n  /* Working pointer for scratch buffer of output values */\n  pOut = pDst;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Loop over the blockSize. Unroll by a factor of 4.    \n   * Compute 4 Multiplications at a time. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in the destination buffer */\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n   * compute the remaining samples */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in the destination buffer */\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and    \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                         blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pOut = pDst;\n\n    /* Loop over the blockSize. Unroll by a factor of 4.    \n     * Compute 4 MACS at a time. */\n    blkCnt = blockSize >> 2;\n\n    while(blkCnt > 0u)\n    {\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4,    \n     * compute the remaining samples */\n    blkCnt = blockSize % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and    \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* Working output pointer is updated */\n  pOut = pDst;\n\n  /* Output is converted into 1.31 format. */\n  /* Loop over the blockSize. Unroll by a factor of 4.    \n   * process 4 output samples at a time. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    in = *pOut << 1;\n    *pOut++ = in;\n    in = *pOut << 1;\n    *pOut++ = in;\n    in = *pOut << 1;\n    *pOut++ = in;\n    in = *pOut << 1;\n    *pOut++ = in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n   * process the remaining output samples */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    in = *pOut << 1;\n    *pOut++ = in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform Multiplications and store in the destination buffer */\n    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and           \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,\n                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,\n                         blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pOut = pDst;\n\n    blkCnt = blockSize;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      out = *pOut;\n      out += ((q63_t) * px++ * coeff) >> 32;\n      *pOut++ = (q31_t) (out);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and           \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* Working output pointer is updated */\n  pOut = pDst;\n\n  /* Output is converted into 1.31 format. */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    in = *pOut << 1;\n    *pOut++ = in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_fir_sparse_q7.c    \n*    \n* Description:\tQ7 sparse FIR filter processing function.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ------------------------------------------------------------------- */\n#include \"arm_math.h\"\n\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup FIR_Sparse    \n * @{    \n */\n\n\n/**   \n * @brief Processing function for the Q7 sparse FIR filter.   \n * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.   \n * @param[in]  *pSrc        points to the block of input data.   \n * @param[out] *pDst        points to the block of output data   \n * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   \n * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   \n * @param[in]  blockSize    number of input samples to process per call.   \n * @return none.   \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    \n * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * The accumulator is then converted to 18.7 format by discarding the low 7 bits.   \n * Finally, the result is truncated to 1.7 format.   \n */\n\nvoid arm_fir_sparse_q7(\n  arm_fir_sparse_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  q7_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize)\n{\n\n  q7_t *pState = S->pState;                      /* State pointer */\n  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */\n  q7_t *px;                                      /* Scratch buffer pointer */\n  q7_t *py = pState;                             /* Temporary pointers for state buffer */\n  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */\n  q7_t *pOut = pDst;                             /* Destination pointer */\n  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */\n  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */\n  uint16_t numTaps = S->numTaps;                 /* Filter order */\n  int32_t readIndex;                             /* Read index of the state buffer */\n  uint32_t tapCnt, blkCnt;                       /* loop counters */\n  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */\n  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */\n  q31_t in;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t in1, in2, in3, in4;\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,\n                       blockSize);\n\n  /* Loop over the number of taps. */\n  tapCnt = numTaps;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,\n                      (int32_t) blockSize, 1, blockSize);\n\n  /* Working pointer for the scratch buffer of state values */\n  px = pb;\n\n  /* Working pointer for scratch buffer of output values */\n  pScratchOut = pScr2;\n\n  /* Loop over the blockSize. Unroll by a factor of 4.    \n   * Compute 4 multiplications at a time. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n   * compute the remaining samples */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and    \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,\n                        (int32_t) blockSize, 1, blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pScratchOut = pScr2;\n\n    /* Loop over the blockSize. Unroll by a factor of 4.    \n     * Compute 4 MACS at a time. */\n    blkCnt = blockSize >> 2;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4,    \n     * compute the remaining samples */\n    blkCnt = blockSize % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and    \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex = ((int32_t) S->stateIndex -\n                 (int32_t) blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* All the output values are in pScratchOut buffer.    \n     Convert them into 1.15 format, saturate and store in the destination buffer. */\n  /* Loop over the blockSize. */\n  blkCnt = blockSize >> 2;\n\n  while(blkCnt > 0u)\n  {\n    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n\n    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4,    \n     remaining samples are processed in the below loop */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* BlockSize of Input samples are copied into the state buffer */\n  /* StateIndex points to the starting position to write in the state buffer */\n  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,\n                       blockSize);\n\n  /* Loop over the number of taps. */\n  tapCnt = numTaps;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Working pointer for state buffer is updated */\n  py = pState;\n\n  /* blockSize samples are read from the state buffer */\n  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,\n                      (int32_t) blockSize, 1, blockSize);\n\n  /* Working pointer for the scratch buffer of state values */\n  px = pb;\n\n  /* Working pointer for scratch buffer of output values */\n  pScratchOut = pScr2;\n\n  /* Loop over the blockSize */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Perform multiplication and store in the scratch buffer */\n    *pScratchOut++ = ((q31_t) * px++ * coeff);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Load the coefficient value and           \n   * increment the coefficient buffer for the next set of state values */\n  coeff = *pCoeffs++;\n\n  /* Read Index, from where the state buffer should be read, is calculated. */\n  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n  /* Wraparound of readIndex */\n  if(readIndex < 0)\n  {\n    readIndex += (int32_t) delaySize;\n  }\n\n  /* Loop over the number of taps. */\n  tapCnt = (uint32_t) numTaps - 1u;\n\n  while(tapCnt > 0u)\n  {\n    /* Working pointer for state buffer is updated */\n    py = pState;\n\n    /* blockSize samples are read from the state buffer */\n    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,\n                        (int32_t) blockSize, 1, blockSize);\n\n    /* Working pointer for the scratch buffer of state values */\n    px = pb;\n\n    /* Working pointer for scratch buffer of output values */\n    pScratchOut = pScr2;\n\n    /* Loop over the blockSize */\n    blkCnt = blockSize;\n\n    while(blkCnt > 0u)\n    {\n      /* Perform Multiply-Accumulate */\n      in = *pScratchOut + ((q31_t) * px++ * coeff);\n      *pScratchOut++ = in;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Load the coefficient value and           \n     * increment the coefficient buffer for the next set of state values */\n    coeff = *pCoeffs++;\n\n    /* Read Index, from where the state buffer should be read, is calculated. */\n    readIndex =\n      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;\n\n    /* Wraparound of readIndex */\n    if(readIndex < 0)\n    {\n      readIndex += (int32_t) delaySize;\n    }\n\n    /* Decrement the tap loop counter */\n    tapCnt--;\n  }\n\n  /* All the output values are in pScratchOut buffer.       \n     Convert them into 1.15 format, saturate and store in the destination buffer. */\n  /* Loop over the blockSize. */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);\n\n    /* Decrement the blockSize loop counter */\n    blkCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of FIR_Sparse group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_iir_lattice_f32.c    \n*    \n* Description:\tFloating-point IIR Lattice filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters    \n *    \n * This set of functions implements lattice filters    \n * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     \n * variety of adaptive filter applications.  The filter structure has feedforward and    \n * feedback components and the net impulse response is infinite length.    \n * The functions operate on blocks    \n * of input and output data and each call to the function processes    \n * blockSize samples through the filter.  pSrc and    \n * pDst point to input and output arrays containing blockSize values.    \n    \n * \\par Algorithm:    \n * \\image html IIRLattice.gif \"Infinite Impulse Response Lattice filter\"    \n * 
    \n *    fN(n)   =  x(n)    \n *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    \n *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    \n *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    \n * 
    \n * \\par    \n * pkCoeffs points to array of reflection coefficients of size numStages.     \n * Reflection coefficients are stored in time-reversed order.    \n * \\par    \n * 
    \n *    {kN, kN-1, ....k1}    \n * 
    \n * pvCoeffs points to the array of ladder coefficients of size (numStages+1).     \n * Ladder coefficients are stored in time-reversed order.    \n * \\par    \n * 
    \n *    {vN, vN-1, ...v0}    \n * 
    \n * pState points to a state array of size numStages + blockSize.    \n * The state variables shown in the figure above (the g values) are stored in the pState array.    \n * The state variables are updated after each block of data is processed; the coefficients are untouched.    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter.    \n * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n  *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.   \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. \n *    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    \n * 
    \n *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n * 
    \n * \\par    \n * where numStages is the number of stages in the filter; pState points to the state buffer array;    \n * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.    \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n/**    \n * @brief Processing function for the floating-point IIR lattice filter.    \n * @param[in] *S points to an instance of the floating-point IIR lattice structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in] blockSize number of samples to process.    \n * @return none.    \n */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\nvoid arm_iir_lattice_f32(\n  const arm_iir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */\n  float32_t acc;                                 /* Accumlator */\n  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */\n  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */\n  uint32_t numStages = S->numStages;             /* number of stages */\n  float32_t *pState;                             /* State pointer */\n  float32_t *pStateCurnt;                        /* State current pointer */\n  float32_t k1, k2;\n  float32_t v1, v2, v3, v4;\n  float32_t gcurr2;\n  float32_t fnext2;\n\n  /* initialise loop count */\n  blkCnt = blockSize;\n\n  /* initialise state pointer */\n  pState = &S->pState[0];\n\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fnext2 = *pSrc++;\n\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n\n    /* Set accumulator to zero */\n    acc = 0.0;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = (numStages) >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Read gN-1(n-1) from state buffer */\n      gcurr1 = *px1;\n\n      /* read reflection coefficient kN */\n      k1 = *pk;\n\n      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */\n      fnext1 = fnext2 - (k1 * gcurr1);\n\n      /* read ladder coefficient vN */\n      v1 = *pv;\n\n      /* read next reflection coefficient kN-1 */\n      k2 = *(pk + 1u);\n\n      /* Read gN-2(n-1) from state buffer */\n      gcurr2 = *(px1 + 1u);\n\n      /* read next ladder coefficient vN-1 */\n      v2 = *(pv + 1u);\n\n      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */\n      fnext2 = fnext1 - (k2 * gcurr2);\n\n      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */\n      gnext = gcurr1 + (k1 * fnext1);\n\n      /* read reflection coefficient kN-2 */\n      k1 = *(pk + 2u);\n\n      /* write gN(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      /* Read gN-3(n-1) from state buffer */\n      gcurr1 = *(px1 + 2u);\n\n      /* y(n) += gN(n) * vN  */\n      acc += (gnext * v1);\n\n      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */\n      fnext1 = fnext2 - (k1 * gcurr1);\n\n      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */\n      gnext = gcurr2 + (k2 * fnext2);\n\n      /* Read gN-4(n-1) from state buffer */\n      gcurr2 = *(px1 + 3u);\n\n      /* y(n) += gN-1(n) * vN-1  */\n      acc += (gnext * v2);\n\n      /* read reflection coefficient kN-3 */\n      k2 = *(pk + 3u);\n\n      /* write gN-1(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */\n      fnext2 = fnext1 - (k2 * gcurr2);\n\n      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */\n      gnext = gcurr1 + (k1 * fnext1);\n\n      /* read ladder coefficient vN-2 */\n      v3 = *(pv + 2u);\n\n      /* y(n) += gN-2(n) * vN-2  */\n      acc += (gnext * v3);\n\n      /* write gN-2(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      /* update pointer */\n      pk += 4u;\n\n      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */\n      gnext = (fnext2 * k2) + gcurr2;\n\n      /* read next ladder coefficient vN-3 */\n      v4 = *(pv + 3u);\n\n      /* y(n) += gN-4(n) * vN-4  */\n      acc += (gnext * v4);\n\n      /* write gN-3(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      /* update pointers */\n      px1 += 4u;\n      pv += 4u;\n\n      tapCnt--;\n\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = (numStages) % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      gcurr1 = *px1++;\n      /* Process sample for last taps */\n      fnext1 = fnext2 - ((*pk) * gcurr1);\n      gnext = (fnext1 * (*pk++)) + gcurr1;\n      /* Output samples for last taps */\n      acc += (gnext * (*pv++));\n      *px2++ = gnext;\n      fnext2 = fnext1;\n\n      tapCnt--;\n\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (fnext2 * (*pv));\n\n    *px2++ = fnext2;\n\n    /* write out into pDst */\n    *pDst++ = acc;\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 1u;\n\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer        \n     for the preperation of next frame process */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  tapCnt = numStages >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numStages) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n}\n\n#else\n\nvoid arm_iir_lattice_f32(\n  const arm_iir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */\n  float32_t acc;                                 /* Accumlator */\n  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */\n  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */\n  uint32_t numStages = S->numStages;             /* number of stages */\n  float32_t *pState;                             /* State pointer */\n  float32_t *pStateCurnt;                        /* State current pointer */\n\n\n  /* Run the below code for Cortex-M0 */\n\n  blkCnt = blockSize;\n\n  pState = &S->pState[0];\n\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n    /* Set accumulator to zero */\n    acc = 0.0f;\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n\n    /* Process sample for numStages */\n    tapCnt = numStages;\n\n    while(tapCnt > 0u)\n    {\n      gcurr = *px1++;\n      /* Process sample for last taps */\n      fnext = fcurr - ((*pk) * gcurr);\n      gnext = (fnext * (*pk++)) + gcurr;\n\n      /* Output samples for last taps */\n      acc += (gnext * (*pv++));\n      *px2++ = gnext;\n      fcurr = fnext;\n\n      /* Decrementing loop counter */\n      tapCnt--;\n\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (fnext * (*pv));\n\n    *px2++ = fnext;\n\n    /* write out into pDst */\n    *pDst++ = acc;\n\n    /* Advance the state pointer by 1 to process the next group of samples */\n    pState = pState + 1u;\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           \n     for the preperation of next frame process */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  tapCnt = numStages;\n\n  /* Copy the data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n}\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n\n/**    \n * @} end of IIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_iir_lattice_init_f32.c    \n*    \n* Description:  Floating-point IIR lattice filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n/**    \n * @brief Initialization function for the floating-point IIR lattice filter.    \n * @param[in] *S points to an instance of the floating-point IIR lattice structure.    \n * @param[in] numStages number of stages in the filter.    \n * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    \n * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    \n * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    \n * @param[in] blockSize number of samples to process.    \n * @return none.    \n */\n\nvoid arm_iir_lattice_init_f32(\n  arm_iir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pkCoeffs,\n  float32_t * pvCoeffs,\n  float32_t * pState,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign reflection coefficient pointer */\n  S->pkCoeffs = pkCoeffs;\n\n  /* Assign ladder coefficient pointer */\n  S->pvCoeffs = pvCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numStages */\n  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n\n}\n\n  /**    \n   * @} end of IIR_Lattice group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_iir_lattice_init_q15.c    \n*    \n* Description:  Q15 IIR lattice filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for the Q15 IIR lattice filter.    \n   * @param[in] *S points to an instance of the Q15 IIR lattice structure.    \n   * @param[in] numStages  number of stages in the filter.    \n   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.    \n   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.    \n   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.    \n   * @param[in] blockSize number of samples to process per call.    \n   * @return none.    \n   */\n\nvoid arm_iir_lattice_init_q15(\n  arm_iir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pkCoeffs,\n  q15_t * pvCoeffs,\n  q15_t * pState,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign reflection coefficient pointer */\n  S->pkCoeffs = pkCoeffs;\n\n  /* Assign ladder coefficient pointer */\n  S->pvCoeffs = pvCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numStages */\n  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n\n}\n\n/**    \n * @} end of IIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_iir_lattice_init_q31.c    \n*    \n* Description:  Initialization function for the Q31 IIR lattice filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for the Q31 IIR lattice filter.    \n   * @param[in] *S points to an instance of the Q31 IIR lattice structure.    \n   * @param[in] numStages number of stages in the filter.    \n   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    \n   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    \n   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    \n   * @param[in] blockSize number of samples to process.    \n   * @return none.    \n   */\n\nvoid arm_iir_lattice_init_q31(\n  arm_iir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pkCoeffs,\n  q31_t * pvCoeffs,\n  q31_t * pState,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numStages = numStages;\n\n  /* Assign reflection coefficient pointer */\n  S->pkCoeffs = pkCoeffs;\n\n  /* Assign ladder coefficient pointer */\n  S->pvCoeffs = pvCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numStages */\n  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n\n}\n\n/**    \n * @} end of IIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_iir_lattice_q15.c    \n*    \n* Description:\tQ15 IIR lattice filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 IIR lattice filter.    \n * @param[in] *S points to an instance of the Q15 IIR lattice structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in] blockSize number of samples to process.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    \n * Lastly, the accumulator is saturated to yield a result in 1.15 format.    \n */\n\nvoid arm_iir_lattice_q15(\n  const arm_iir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */\n  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */\n  uint32_t stgCnt;                               /* Temporary variables for counts */\n  q63_t acc;                                     /* Accumlator */\n  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */\n  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */\n  uint32_t numStages = S->numStages;             /* number of stages */\n  q15_t *pState;                                 /* State pointer */\n  q15_t *pStateCurnt;                            /* State current pointer */\n  q15_t out;                                     /* Temporary variable for output */\n  q31_t v;                                       /* Temporary variable for ladder coefficient */\n#ifdef UNALIGNED_SUPPORT_DISABLE\n\tq15_t v1, v2;\n#endif\n\n\n  blkCnt = blockSize;\n\n  pState = &S->pState[0];\n\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n    /* Set accumulator to zero */\n    acc = 0;\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n\n    /* Process sample for first tap */\n    gcurr = *px1++;\n    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */\n    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);\n    fnext = __SSAT(fnext, 16);\n    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */\n    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;\n    gnext = __SSAT(gnext, 16);\n    /* write gN(n) into state for next sample processing */\n    *px2++ = (q15_t) gnext;\n    /* y(n) += gN(n) * vN  */\n    acc += (q31_t) ((gnext * (*pv++)));\n\n\n    /* Update f values for next coefficient processing */\n    fcurr = fnext;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = (numStages - 1u) >> 2;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Process sample for 2nd, 6th ...taps */\n      /* Read gN-2(n-1) from state buffer */\n      gcurr = *px1++;\n      /* Process sample for 2nd, 6th .. taps */\n      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */\n      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);\n      fnext = __SSAT(fnext, 16);\n      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */\n      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;\n      gnext1 = (q15_t) __SSAT(gnext, 16);\n      /* write gN-1(n) into state */\n      *px2++ = (q15_t) gnext1;\n\n\n      /* Process sample for 3nd, 7th ...taps */\n      /* Read gN-3(n-1) from state */\n      gcurr = *px1++;\n      /* Process sample for 3rd, 7th .. taps */\n      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */\n      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);\n      fcurr = __SSAT(fcurr, 16);\n      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */\n      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;\n      gnext2 = (q15_t) __SSAT(gnext, 16);\n      /* write gN-2(n) into state */\n      *px2++ = (q15_t) gnext2;\n\n      /* Read vN-1 and vN-2 at a time */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      v = *__SIMD32(pv)++;\n\n#else\n\n\t  v1 = *pv++;\n\t  v2 = *pv++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  v = __PKHBT(v1, v2, 16);\n\n#else\n\n\t  v = __PKHBT(v2, v1, 16);\n\n#endif\t/* \t#ifndef ARM_MATH_BIG_ENDIAN\t\t*/\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE */\n\n\n      /* Pack gN-1(n) and gN-2(n) */\n\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      gnext = __PKHBT(gnext1, gnext2, 16);\n\n#else\n\n      gnext = __PKHBT(gnext2, gnext1, 16);\n\n#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* y(n) += gN-1(n) * vN-1  */\n      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */\n      /* y(n) += gN-2(n) * vN-2  */\n      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */\n      acc = __SMLALD(gnext, v, acc);\n\n\n      /* Process sample for 4th, 8th ...taps */\n      /* Read gN-4(n-1) from state */\n      gcurr = *px1++;\n      /* Process sample for 4th, 8th .. taps */\n      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */\n      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);\n      fnext = __SSAT(fnext, 16);\n      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */\n      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;\n      gnext1 = (q15_t) __SSAT(gnext, 16);\n      /* write  gN-3(n) for the next sample process */\n      *px2++ = (q15_t) gnext1;\n\n\n      /* Process sample for 5th, 9th ...taps */\n      /* Read gN-5(n-1) from state */\n      gcurr = *px1++;\n      /* Process sample for 5th, 9th .. taps */\n      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */\n      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);\n      fcurr = __SSAT(fcurr, 16);\n      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */\n      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;\n      gnext2 = (q15_t) __SSAT(gnext, 16);\n      /* write      gN-4(n) for the next sample process */\n      *px2++ = (q15_t) gnext2;\n\n      /* Read vN-3 and vN-4 at a time */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      v = *__SIMD32(pv)++;\n\n#else\n\n\t  v1 = *pv++;\n\t  v2 = *pv++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n\t  v = __PKHBT(v1, v2, 16);\n\n#else\n\n\t  v = __PKHBT(v2, v1, 16);\n\n#endif\t/* #ifndef ARM_MATH_BIG_ENDIAN\t */\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE */\n\n\n      /* Pack gN-3(n) and gN-4(n) */\n#ifndef  ARM_MATH_BIG_ENDIAN\n\n      gnext = __PKHBT(gnext1, gnext2, 16);\n\n#else\n\n      gnext = __PKHBT(gnext2, gnext1, 16);\n\n#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */\n\n      /* y(n) += gN-4(n) * vN-4  */\n      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */\n      /* y(n) += gN-3(n) * vN-3  */\n      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */\n      acc = __SMLALD(gnext, v, acc);\n\n      tapCnt--;\n\n    }\n\n    fnext = fcurr;\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = (numStages - 1u) % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      gcurr = *px1++;\n      /* Process sample for last taps */\n      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);\n      fnext = __SSAT(fnext, 16);\n      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;\n      gnext = __SSAT(gnext, 16);\n      /* Output samples for last taps */\n      acc += (q31_t) (((q31_t) gnext * (*pv++)));\n      *px2++ = (q15_t) gnext;\n      fcurr = fnext;\n\n      tapCnt--;\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (q31_t) (((q31_t) fnext * (*pv++)));\n\n    out = (q15_t) __SSAT(acc >> 15, 16);\n    *px2++ = (q15_t) fnext;\n\n    /* write out into pDst */\n    *pDst++ = out;\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 1u;\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    \n     for the preperation of next frame process */\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  stgCnt = (numStages >> 2u);\n\n  /* copy data */\n  while(stgCnt > 0u)\n  {\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n#else\n\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n#endif /*\t#ifndef UNALIGNED_SUPPORT_DISABLE */\n\n    /* Decrement the loop counter */\n    stgCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  stgCnt = (numStages) % 0x4u;\n\n  /* copy data */\n  while(stgCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    stgCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */\n  uint32_t stgCnt;                               /* Temporary variables for counts */\n  q63_t acc;                                     /* Accumlator */\n  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */\n  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */\n  uint32_t numStages = S->numStages;             /* number of stages */\n  q15_t *pState;                                 /* State pointer */\n  q15_t *pStateCurnt;                            /* State current pointer */\n  q15_t out;                                     /* Temporary variable for output */\n\n\n  blkCnt = blockSize;\n\n  pState = &S->pState[0];\n\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n    /* Set accumulator to zero */\n    acc = 0;\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n    tapCnt = numStages;\n\n    while(tapCnt > 0u)\n    {\n      gcurr = *px1++;\n      /* Process sample */\n      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */\n      fnext = fcurr - ((gcurr * (*pk)) >> 15);\n      fnext = __SSAT(fnext, 16);\n      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */\n      gnext = ((fnext * (*pk++)) >> 15) + gcurr;\n      gnext = __SSAT(gnext, 16);\n      /* Output samples */\n      /* y(n) += gN(n) * vN */\n      acc += (q31_t) ((gnext * (*pv++)));\n      /* write gN(n) into state for next sample processing */\n      *px2++ = (q15_t) gnext;\n      /* Update f values for next coefficient processing */\n      fcurr = fnext;\n\n      tapCnt--;\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (q31_t) ((fnext * (*pv++)));\n\n    out = (q15_t) __SSAT(acc >> 15, 16);\n    *px2++ = (q15_t) fnext;\n\n    /* write out into pDst */\n    *pDst++ = out;\n\n    /* Advance the state pointer by 1 to process the next group of samples */\n    pState = pState + 1u;\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           \n     for the preperation of next frame process */\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  stgCnt = numStages;\n\n  /* copy data */\n  while(stgCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    stgCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n\n\n/**    \n * @} end of IIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_iir_lattice_q31.c    \n*    \n* Description:\tQ31 IIR lattice filter processing function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup IIR_Lattice    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 IIR lattice filter.    \n * @param[in] *S points to an instance of the Q31 IIR lattice structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[out] *pDst points to the block of output data.    \n * @param[in] blockSize number of samples to process.    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    \n * Thus, if the accumulator result overflows it wraps around rather than clip.    \n * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.    \n * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.    \n */\n\nvoid arm_iir_lattice_q31(\n  const arm_iir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */\n  q63_t acc;                                     /* Accumlator */\n  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */\n  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */\n  uint32_t numStages = S->numStages;             /* number of stages */\n  q31_t *pState;                                 /* State pointer */\n  q31_t *pStateCurnt;                            /* State current pointer */\n\n  blkCnt = blockSize;\n\n  pState = &S->pState[0];\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n    /* Set accumulator to zero */\n    acc = 0;\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n\n    /* Process sample for first tap */\n    gcurr = *px1++;\n    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */\n    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */\n    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));\n    /* write gN-1(n-1) into state for next sample processing */\n    *px2++ = gnext;\n    /* y(n) += gN(n) * vN  */\n    acc += ((q63_t) gnext * *pv++);\n\n    /* Update f values for next coefficient processing */\n    fcurr = fnext;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = (numStages - 1u) >> 2;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Process sample for 2nd, 6th .. taps */\n      /* Read gN-2(n-1) from state buffer */\n      gcurr = *px1++;\n      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */\n      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */\n      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));\n      /* y(n) += gN-1(n) * vN-1  */\n      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */\n      acc += ((q63_t) gnext * *pv++);\n      /* write gN-1(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      /* Process sample for 3nd, 7th ...taps */\n      /* Read gN-3(n-1) from state buffer */\n      gcurr = *px1++;\n      /* Process sample for 3rd, 7th .. taps */\n      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */\n      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */\n      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));\n      /* y(n) += gN-2(n) * vN-2  */\n      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */\n      acc += ((q63_t) gnext * *pv++);\n      /* write gN-2(n) into state for next sample processing */\n      *px2++ = gnext;\n\n\n      /* Process sample for 4th, 8th ...taps */\n      /* Read gN-4(n-1) from state buffer */\n      gcurr = *px1++;\n      /* Process sample for 4th, 8th .. taps */\n      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */\n      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */\n      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));\n      /* y(n) += gN-3(n) * vN-3  */\n      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */\n      acc += ((q63_t) gnext * *pv++);\n      /* write gN-3(n) into state for next sample processing */\n      *px2++ = gnext;\n\n\n      /* Process sample for 5th, 9th ...taps */\n      /* Read gN-5(n-1) from state buffer */\n      gcurr = *px1++;\n      /* Process sample for 5th, 9th .. taps */\n      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */\n      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */\n      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));\n      /* y(n) += gN-4(n) * vN-4  */\n      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */\n      acc += ((q63_t) gnext * *pv++);\n      /* write gN-4(n) into state for next sample processing */\n      *px2++ = gnext;\n\n      tapCnt--;\n\n    }\n\n    fnext = fcurr;\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = (numStages - 1u) % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      gcurr = *px1++;\n      /* Process sample for last taps */\n      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));\n      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));\n      /* Output samples for last taps */\n      acc += ((q63_t) gnext * *pv++);\n      *px2++ = gnext;\n      fcurr = fnext;\n\n      tapCnt--;\n\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (q63_t) fnext *(\n  *pv++);\n\n    *px2++ = fnext;\n\n    /* write out into pDst */\n    *pDst++ = (q31_t) (acc >> 31u);\n\n    /* Advance the state pointer by 4 to process the next group of 4 samples */\n    pState = pState + 1u;\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    \n     for the preperation of next frame process */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  tapCnt = numStages >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numStages) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  };\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  /* Sample processing */\n  while(blkCnt > 0u)\n  {\n    /* Read Sample from input buffer */\n    /* fN(n) = x(n) */\n    fcurr = *pSrc++;\n\n    /* Initialize state read pointer */\n    px1 = pState;\n    /* Initialize state write pointer */\n    px2 = pState;\n    /* Set accumulator to zero */\n    acc = 0;\n    /* Initialize Ladder coeff pointer */\n    pv = &S->pvCoeffs[0];\n    /* Initialize Reflection coeff pointer */\n    pk = &S->pkCoeffs[0];\n\n    tapCnt = numStages;\n\n    while(tapCnt > 0u)\n    {\n      gcurr = *px1++;\n      /* Process sample */\n      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */\n      fnext =\n        clip_q63_to_q31(((q63_t) fcurr -\n                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));\n      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */\n      gnext =\n        clip_q63_to_q31(((q63_t) gcurr +\n                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));\n      /* Output samples */\n      /* y(n) += gN(n) * vN  */\n      acc += ((q63_t) gnext * *pv++);\n      /* write gN-1(n-1) into state for next sample processing */\n      *px2++ = gnext;\n      /* Update f values for next coefficient processing */\n      fcurr = fnext;\n\n      tapCnt--;\n    }\n\n    /* y(n) += g0(n) * v0 */\n    acc += (q63_t) fnext *(\n  *pv++);\n\n    *px2++ = fnext;\n\n    /* write out into pDst */\n    *pDst++ = (q31_t) (acc >> 31u);\n\n    /* Advance the state pointer by 1 to process the next group of samples */\n    pState = pState + 1u;\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           \n     for the preperation of next frame process */\n\n  /* Points to the start of the state buffer */\n  pStateCurnt = &S->pState[0];\n  pState = &S->pState[blockSize];\n\n  tapCnt = numStages;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n\n\n/**    \n * @} end of IIR_Lattice group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_f32.c    \n*    \n* Description:\tProcessing function for the floating-point LMS filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup LMS Least Mean Square (LMS) Filters    \n *    \n * LMS filters are a class of adaptive filters that are able to \"learn\" an unknown transfer functions.    \n * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.    \n * Adaptive filters are often used in communication systems, equalizers, and noise removal.    \n * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.    \n * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.    \n *    \n * An LMS filter consists of two components as shown below.    \n * The first component is a standard transversal or FIR filter.    \n * The second component is a coefficient update mechanism.    \n * The LMS filter has two input signals.    \n * The \"input\" feeds the FIR filter while the \"reference input\" corresponds to the desired output of the FIR filter.    \n * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    \n * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    \n * This \"error signal\" tends towards zero as the filter adapts.    \n * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.    \n * \\image html LMS.gif \"Internal structure of the Least Mean Square filter\"    \n *    \n * The functions operate on blocks of data and each call to the function processes    \n * blockSize samples through the filter.    \n * pSrc points to input signal, pRef points to reference signal,    \n * pOut points to output signal and pErr points to error signal.    \n * All arrays contain blockSize values.    \n *    \n * The functions operate on a block-by-block basis.    \n * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    \n * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    \n *    \n * \\par Algorithm:    \n * The output signal y[n] is computed by a standard FIR filter:    \n * 
    \n *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n * 
    \n *    \n * \\par    \n * The error signal equals the difference between the reference signal d[n] and the filter output:    \n * 
    \n *     e[n] = d[n] - y[n].    \n * 
    \n *    \n * \\par    \n * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:    \n * 
    \n *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    \n * 
    \n * where mu is the step size and controls the rate of coefficient convergence.    \n *\\par    \n * In the APIs, pCoeffs points to a coefficient array of size numTaps.    \n * Coefficients are stored in time reversed order.    \n * \\par    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to a state array of size numTaps + blockSize - 1.    \n * Samples in the state buffer are stored in the order:    \n * \\par    \n * 
    \n *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n * 
    \n * \\par    \n * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    \n * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    \n * to be avoided and yields a significant speed improvement.    \n * The state variables are updated after each block of data is processed.    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter and    \n * coefficient and state arrays cannot be shared among instances.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. \n *\n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Set the values in the state buffer to zeros before static initialization.    \n * The code below statically initializes each of the 3 different data type filter instance structures    \n * 
    \n *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    \n *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    \n *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    \n * 
    \n * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;    \n * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.    \n *    \n * \\par Fixed-Point Behavior:    \n * Care must be taken when using the Q15 and Q31 versions of the LMS filter.    \n * The following issues must be considered:    \n * - Scaling of coefficients    \n * - Overflow and saturation    \n *    \n * \\par Scaling of Coefficients:    \n * Filter coefficients are represented as fractional values and    \n * coefficients are restricted to lie in the range [-1 +1).    \n * The fixed-point functions have an additional scaling parameter postShift.    \n * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    \n * This essentially scales the filter coefficients by 2^postShift and    \n * allows the filter coefficients to exceed the range [+1 -1).    \n * The value of postShift is set by the user based on the expected gain through the system being modeled.    \n *    \n * \\par Overflow and Saturation:    \n * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    \n * described separately as part of the function specific documentation below.    \n */\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n/**           \n * @details           \n * This function operates on floating-point data types.       \n *    \n * @brief Processing function for floating-point LMS filter.    \n * @param[in]  *S points to an instance of the floating-point LMS filter structure.    \n * @param[in]  *pSrc points to the block of input data.    \n * @param[in]  *pRef points to the block of reference data.    \n * @param[out] *pOut points to the block of output data.    \n * @param[out] *pErr points to the block of error data.    \n * @param[in]  blockSize number of samples to process.    \n * @return     none.    \n */\n\nvoid arm_lms_f32(\n  const arm_lms_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize)\n{\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */\n  float32_t mu = S->mu;                          /* Adaptive factor */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  float32_t sum, e, d;                           /* accumulator, error, reference data sample */\n  float32_t w = 0.0f;                            /* weight factor */\n\n  e = 0.0f;\n  d = 0.0f;\n\n  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  blkCnt = blockSize;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Set the accumulator to zero */\n    sum = 0.0f;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* The result in the accumulator, store in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Compute and store error */\n    d = (float32_t) (*pRef++);\n    e = d - sum;\n    *pErr++ = e;\n\n    /* Calculation of Weighting factor for the updating filter coefficients */\n    w = e * mu;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Loop unrolling for (numTaps - 1u) samples copy */\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Set the accumulator to zero */\n    sum = 0.0f;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* The result is stored in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Compute and store error */\n    d = (float32_t) (*pRef++);\n    e = d - sum;\n    *pErr++ = e;\n\n    /* Weighting factor for the LMS version */\n    w = e * mu;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb = *pb + (w * (*px++));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the        \n   * start of the state buffer. This prepares the state buffer for the        \n   * next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /*  Copy (numTaps - 1u) samples  */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of LMS group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_init_f32.c    \n*    \n* Description:  Floating-point LMS filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for floating-point LMS filter.    \n   * @param[in] *S points to an instance of the floating-point LMS filter structure.    \n   * @param[in] numTaps  number of filter coefficients.    \n   * @param[in] *pCoeffs points to the coefficient buffer.    \n   * @param[in] *pState points to state buffer.    \n   * @param[in] mu step size that controls filter coefficient updates.    \n   * @param[in] blockSize number of samples to process.    \n   * @return none.    \n   */\n\n/**    \n * \\par Description:    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * The initial filter coefficients serve as a starting point for the adaptive filter.    \n * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().    \n */\n\nvoid arm_lms_init_f32(\n  arm_lms_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps */\n  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n}\n\n/**    \n * @} end of LMS group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_init_q15.c    \n*    \n* Description:  Q15 LMS filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n/**    \n* @brief Initialization function for the Q15 LMS filter.    \n* @param[in] *S points to an instance of the Q15 LMS filter structure.    \n* @param[in] numTaps  number of filter coefficients.    \n* @param[in] *pCoeffs points to the coefficient buffer.    \n* @param[in] *pState points to the state buffer.    \n* @param[in] mu step size that controls filter coefficient updates.    \n* @param[in] blockSize number of samples to process.    \n* @param[in] postShift bit shift applied to coefficients.    \n* @return    none.    \n*    \n* \\par Description:    \n* pCoeffs points to the array of filter coefficients stored in time reversed order:    \n* 
    \n*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n* 
    \n* The initial filter coefficients serve as a starting point for the adaptive filter.    \n* pState points to the array of state variables and size of array is    \n* numTaps+blockSize-1 samples, where blockSize is the number of    \n* input samples processed by each call to arm_lms_q15().    \n*/\n\nvoid arm_lms_init_q15(\n  arm_lms_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint32_t postShift)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps - 1 */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n\n  /* Assign postShift value to be applied */\n  S->postShift = postShift;\n\n}\n\n/**    \n * @} end of LMS group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_init_q31.c    \n*    \n* Description:  Q31 LMS filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for Q31 LMS filter.    \n   * @param[in] *S points to an instance of the Q31 LMS filter structure.    \n   * @param[in] numTaps  number of filter coefficients.    \n   * @param[in] *pCoeffs points to coefficient buffer.    \n   * @param[in] *pState points to state buffer.    \n   * @param[in] mu step size that controls filter coefficient updates.    \n   * @param[in] blockSize number of samples to process.    \n   * @param[in] postShift bit shift applied to coefficients.    \n   * @return none.    \n *    \n * \\par Description:    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * The initial filter coefficients serve as a starting point for the adaptive filter.    \n * pState points to an array of length numTaps+blockSize-1 samples,    \n * where blockSize is the number of input samples processed by each call to    \n * arm_lms_q31().    \n */\n\nvoid arm_lms_init_q31(\n  arm_lms_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint32_t postShift)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps - 1 */\n  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n\n  /* Assign postShift value to be applied */\n  S->postShift = postShift;\n\n}\n\n/**    \n * @} end of LMS group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_norm_f32.c    \n*    \n* Description:\tProcessing function for the floating-point Normalised LMS.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @defgroup LMS_NORM Normalized LMS Filters    \n *    \n * This set of functions implements a commonly used adaptive filter.    \n * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization    \n * factor which increases the adaptation rate of the filter.    \n * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.    \n *    \n * A normalized least mean square (NLMS) filter consists of two components as shown below.    \n * The first component is a standard transversal or FIR filter.    \n * The second component is a coefficient update mechanism.    \n * The NLMS filter has two input signals.    \n * The \"input\" feeds the FIR filter while the \"reference input\" corresponds to the desired output of the FIR filter.    \n * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    \n * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    \n * This \"error signal\" tends towards zero as the filter adapts.    \n * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.    \n * \\image html LMS.gif \"Internal structure of the NLMS adaptive filter\"    \n *    \n * The functions operate on blocks of data and each call to the function processes    \n * blockSize samples through the filter.    \n * pSrc points to input signal, pRef points to reference signal,    \n * pOut points to output signal and pErr points to error signal.    \n * All arrays contain blockSize values.    \n *    \n * The functions operate on a block-by-block basis.    \n * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    \n * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    \n *    \n * \\par Algorithm:    \n * The output signal y[n] is computed by a standard FIR filter:    \n * 
    \n *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n * 
    \n *    \n * \\par    \n * The error signal equals the difference between the reference signal d[n] and the filter output:    \n * 
    \n *     e[n] = d[n] - y[n].    \n * 
    \n *    \n * \\par    \n * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:    \n * 
    \n *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    \n * 
    \n * The filter coefficients b[k] are then updated on a sample-by-sample basis:    \n * 
    \n *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    \n * 
    \n * where mu is the step size and controls the rate of coefficient convergence.    \n *\\par    \n * In the APIs, pCoeffs points to a coefficient array of size numTaps.    \n * Coefficients are stored in time reversed order.    \n * \\par    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * \\par    \n * pState points to a state array of size numTaps + blockSize - 1.    \n * Samples in the state buffer are stored in the order:    \n * \\par    \n * 
    \n *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n * 
    \n * \\par    \n * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    \n * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    \n * to be avoided and yields a significant speed improvement.    \n * The state variables are updated after each block of data is processed.    \n * \\par Instance Structure    \n * The coefficients and state variables for a filter are stored together in an instance data structure.    \n * A separate instance structure must be defined for each filter and    \n * coefficient and state arrays cannot be shared among instances.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Zeros out the values in the state buffer.    \n * To do this manually without calling the init function, assign the follow subfields of the instance structure:\n * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. \n * For Q7, Q15, and Q31 the following fields must also be initialized;\n * recipTable, postShift\n *\n * \\par    \n * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.    \n * \\par Fixed-Point Behavior:    \n * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.    \n * The following issues must be considered:    \n * - Scaling of coefficients    \n * - Overflow and saturation    \n *    \n * \\par Scaling of Coefficients:    \n * Filter coefficients are represented as fractional values and    \n * coefficients are restricted to lie in the range [-1 +1).    \n * The fixed-point functions have an additional scaling parameter postShift.    \n * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    \n * This essentially scales the filter coefficients by 2^postShift and    \n * allows the filter coefficients to exceed the range [+1 -1).    \n * The value of postShift is set by the user based on the expected gain through the system being modeled.    \n *    \n * \\par Overflow and Saturation:    \n * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    \n * described separately as part of the function specific documentation below.    \n */\n\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n\n  /**    \n   * @brief Processing function for floating-point normalized LMS filter.    \n   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.    \n   * @param[in] *pSrc points to the block of input data.    \n   * @param[in] *pRef points to the block of reference data.    \n   * @param[out] *pOut points to the block of output data.    \n   * @param[out] *pErr points to the block of error data.    \n   * @param[in] blockSize number of samples to process.    \n   * @return none.    \n   */\n\nvoid arm_lms_norm_f32(\n  arm_lms_norm_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize)\n{\n  float32_t *pState = S->pState;                 /* State pointer */\n  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */\n  float32_t *pStateCurnt;                        /* Points to the current sample of the state */\n  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */\n  float32_t mu = S->mu;                          /* Adaptive factor */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  float32_t energy;                              /* Energy of the input */\n  float32_t sum, e, d;                           /* accumulator, error, reference data sample */\n  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */\n\n  /* Initializations of error,  difference, Coefficient update */\n  e = 0.0f;\n  d = 0.0f;\n  w = 0.0f;\n\n  energy = S->energy;\n  x0 = S->x0;\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy -= x0 * x0;\n    energy += in * in;\n\n    /* Set the accumulator to zero */\n    sum = 0.0f;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* The result in the accumulator, store in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Compute and store error */\n    d = (float32_t) (*pRef++);\n    e = d - sum;\n    *pErr++ = e;\n\n    /* Calculation of Weighting factor for updating filter coefficients */\n    /* epsilon value 0.000000119209289f */\n    w = (e * mu) / (energy + 0.000000119209289f);\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb += w * (*px++);\n      pb++;\n\n      *pb += w * (*px++);\n      pb++;\n\n      *pb += w * (*px++);\n      pb++;\n\n      *pb += w * (*px++);\n      pb++;\n\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb += w * (*px++);\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  S->energy = energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Loop unrolling for (numTaps - 1u)/4 samples copy */\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy -= x0 * x0;\n    energy += in * in;\n\n    /* Set the accumulator to zero */\n    sum = 0.0f;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      sum += (*px++) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* The result in the accumulator is stored in the destination buffer. */\n    *pOut++ = sum;\n\n    /* Compute and store error */\n    d = (float32_t) (*pRef++);\n    e = d - sum;\n    *pErr++ = e;\n\n    /* Calculation of Weighting factor for updating filter coefficients */\n    /* epsilon value 0.000000119209289f */\n    w = (e * mu) / (energy + 0.000000119209289f);\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCcoeffs pointer */\n    pb = pCoeffs;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb += w * (*px++);\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  S->energy = energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the        \n     satrt of the state buffer. This prepares the state buffer for the        \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Copy (numTaps - 1u) samples  */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of LMS_NORM group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_norm_init_f32.c    \n*    \n* Description:  Floating-point NLMS filter initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for floating-point normalized LMS filter.    \n   * @param[in] *S points to an instance of the floating-point LMS filter structure.    \n   * @param[in] numTaps  number of filter coefficients.    \n   * @param[in] *pCoeffs points to coefficient buffer.    \n   * @param[in] *pState points to state buffer.    \n   * @param[in] mu step size that controls filter coefficient updates.    \n   * @param[in] blockSize number of samples to process.    \n   * @return none.    \n   *    \n * \\par Description:    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * The initial filter coefficients serve as a starting point for the adaptive filter.    \n * pState points to an array of length numTaps+blockSize-1 samples,    \n * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().    \n */\n\nvoid arm_lms_norm_init_f32(\n  arm_lms_norm_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps - 1 */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n\n  /* Initialise Energy to zero */\n  S->energy = 0.0f;\n\n  /* Initialise x0 to zero */\n  S->x0 = 0.0f;\n\n}\n\n/**    \n * @} end of LMS_NORM group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_norm_init_q15.c    \n*    \n* Description:  Q15 NLMS initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for Q15 normalized LMS filter.    \n   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    \n   * @param[in] numTaps  number of filter coefficients.    \n   * @param[in] *pCoeffs points to coefficient buffer.    \n   * @param[in] *pState points to state buffer.    \n   * @param[in] mu step size that controls filter coefficient updates.    \n   * @param[in] blockSize number of samples to process.    \n   * @param[in] postShift bit shift applied to coefficients.    \n   * @return none.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * The initial filter coefficients serve as a starting point for the adaptive filter.    \n * pState points to the array of state variables and size of array is    \n * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed    \n * by each call to arm_lms_norm_q15().    \n */\n\nvoid arm_lms_norm_init_q15(\n  arm_lms_norm_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint8_t postShift)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps - 1 */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));\n\n  /* Assign post Shift value applied to coefficients */\n  S->postShift = postShift;\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n\n  /* Initialize reciprocal pointer table */\n  S->recipTable = (q15_t *) armRecipTableQ15;\n\n  /* Initialise Energy to zero */\n  S->energy = 0;\n\n  /* Initialise x0 to zero */\n  S->x0 = 0;\n\n}\n\n/**    \n * @} end of LMS_NORM group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c",
    "content": "/*-----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_lms_norm_init_q31.c    \n*    \n* Description:  Q31 NLMS initialization function.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------*/\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n  /**    \n   * @brief Initialization function for Q31 normalized LMS filter.    \n   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    \n   * @param[in] numTaps  number of filter coefficients.    \n   * @param[in] *pCoeffs points to coefficient buffer.    \n   * @param[in] *pState points to state buffer.    \n   * @param[in] mu step size that controls filter coefficient updates.    \n   * @param[in] blockSize number of samples to process.    \n   * @param[in] postShift bit shift applied to coefficients.    \n   * @return none.    \n *    \n * Description:    \n * \\par    \n * pCoeffs points to the array of filter coefficients stored in time reversed order:    \n * 
    \n *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n * 
    \n * The initial filter coefficients serve as a starting point for the adaptive filter.    \n * pState points to an array of length numTaps+blockSize-1 samples,    \n * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().    \n */\n\nvoid arm_lms_norm_init_q31(\n  arm_lms_norm_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint8_t postShift)\n{\n  /* Assign filter taps */\n  S->numTaps = numTaps;\n\n  /* Assign coefficient pointer */\n  S->pCoeffs = pCoeffs;\n\n  /* Clear state buffer and size is always blockSize + numTaps - 1  */\n  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));\n\n  /* Assign post Shift value applied to coefficients */\n  S->postShift = postShift;\n\n  /* Assign state pointer */\n  S->pState = pState;\n\n  /* Assign Step size value */\n  S->mu = mu;\n\n  /* Initialize reciprocal pointer table */\n  S->recipTable = (q31_t *) armRecipTableQ31;\n\n  /* Initialise Energy to zero */\n  S->energy = 0;\n\n  /* Initialise x0 to zero */\n  S->x0 = 0;\n\n}\n\n/**    \n * @} end of LMS_NORM group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_norm_q15.c    \n*    \n* Description:\tQ15 NLMS filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n/**    \n* @brief Processing function for Q15 normalized LMS filter.    \n* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    \n* @param[in] *pSrc points to the block of input data.    \n* @param[in] *pRef points to the block of reference data.    \n* @param[out] *pOut points to the block of output data.    \n* @param[out] *pErr points to the block of error data.    \n* @param[in] blockSize number of samples to process.    \n* @return none.    \n*    \n* Scaling and Overflow Behavior:     \n* \\par     \n* The function is implemented using a 64-bit internal accumulator.     \n* Both coefficients and state variables are represented in 1.15 format and    \n* multiplications yield a 2.30 result. The 2.30 intermediate results are    \n* accumulated in a 64-bit accumulator in 34.30 format.     \n* There is no risk of internal overflow with this approach and the full    \n* precision of intermediate multiplications is preserved. After all additions    \n* have been performed, the accumulator is truncated to 34.15 format by    \n* discarding low 15 bits. Lastly, the accumulator is saturated to yield a    \n* result in 1.15 format.    \n*    \n* \\par   \n* \tIn this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    \n*    \n */\n\nvoid arm_lms_norm_q15(\n  arm_lms_norm_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */\n  q15_t mu = S->mu;                              /* Adaptive factor */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  q31_t energy;                                  /* Energy of the input */\n  q63_t acc;                                     /* Accumulator */\n  q15_t e = 0, d = 0;                            /* error, reference data sample */\n  q15_t w = 0, in;                               /* weight factor and state */\n  q15_t x0;                                      /* temporary variable to hold input sample */\n  //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */ \n  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */\n  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */\n  q31_t coef;                                    /* Teporary variable for coefficient */\n  q31_t acc_l, acc_h;\n  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */\n  int32_t uShift = (32 - lShift);\n\n  energy = S->energy;\n  x0 = S->x0;\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy -= (((q31_t) x0 * (x0)) >> 15);\n    energy += (((q31_t) in * (in)) >> 15);\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n\n      /* Perform the multiply-accumulate */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);\n      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);\n\n#else\n\n      acc += (((q31_t) * px++ * (*pb++)));\n      acc += (((q31_t) * px++ * (*pb++)));\n      acc += (((q31_t) * px++ * (*pb++)));\n      acc += (((q31_t) * px++ * (*pb++)));\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += (((q31_t) * px++ * (*pb++)));\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    /* Apply shift for lower part of acc and upper part of acc */\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Converting the result to 1.15 format and saturate the output */\n    acc = __SSAT(acc, 16u);\n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q15_t) acc;\n\n    /* Compute and store error */\n    d = *pRef++;\n    e = d - (q15_t) acc;\n    *pErr++ = e;\n\n    /* Calculation of 1/energy */\n    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,\n                              &oneByEnergy, S->recipTable);\n\n    /* Calculation of e * mu value */\n    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);\n\n    /* Calculation of (e * mu) * (1/energy) value */\n    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));\n\n    /* Weighting factor for the normalized version */\n    w = (q15_t) __SSAT((q31_t) acc, 16);\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Read the sample from state buffer */\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Save energy and x0 values for the next frame */\n  S->energy = (q15_t) energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculation of count for copying integer writes */\n  tapCnt = (numTaps - 1u) >> 2;\n\n  while(tapCnt > 0u)\n  {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n\n#else\n\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n#endif\n\n    tapCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy -= (((q31_t) x0 * (x0)) >> 15);\n    energy += (((q31_t) in * (in)) >> 15);\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += (((q31_t) * px++ * (*pb++)));\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    /* Apply shift for lower part of acc and upper part of acc */\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Converting the result to 1.15 format and saturate the output */\n    acc = __SSAT(acc, 16u);\n\n    /* Converting the result to 1.15 format */\n    //acc = __SSAT((acc >> (16u - shift)), 16u); \n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q15_t) acc;\n\n    /* Compute and store error */\n    d = *pRef++;\n    e = d - (q15_t) acc;\n    *pErr++ = e;\n\n    /* Calculation of 1/energy */\n    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,\n                              &oneByEnergy, S->recipTable);\n\n    /* Calculation of e * mu value */\n    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);\n\n    /* Calculation of (e * mu) * (1/energy) value */\n    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));\n\n    /* Weighting factor for the normalized version */\n    w = (q15_t) __SSAT((q31_t) acc, 16);\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = *pb + (((q31_t) w * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Read the sample from state buffer */\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Save energy and x0 values for the next frame */\n  S->energy = (q15_t) energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the        \n     satrt of the state buffer. This prepares the state buffer for the        \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* copy (numTaps - 1u) data */\n  tapCnt = (numTaps - 1u);\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n/**    \n   * @} end of LMS_NORM group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_norm_q31.c    \n*    \n* Description:\tProcessing function for the Q31 NLMS filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS_NORM    \n * @{    \n */\n\n/**    \n* @brief Processing function for Q31 normalized LMS filter.    \n* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    \n* @param[in] *pSrc points to the block of input data.    \n* @param[in] *pRef points to the block of reference data.    \n* @param[out] *pOut points to the block of output data.    \n* @param[out] *pErr points to the block of error data.    \n* @param[in] blockSize number of samples to process.    \n* @return none.    \n*    \n* Scaling and Overflow Behavior:     \n* \\par     \n* The function is implemented using an internal 64-bit accumulator.     \n* The accumulator has a 2.62 format and maintains full precision of the intermediate   \n* multiplication results but provides only a single guard bit.     \n* Thus, if the accumulator result overflows it wraps around rather than clip.     \n* In order to avoid overflows completely the input signal must be scaled down by    \n* log2(numTaps) bits. The reference signal should not be scaled down.     \n* After all multiply-accumulates are performed, the 2.62 accumulator is shifted    \n* and saturated to 1.31 format to yield the final result.     \n* The output signal and error signal are in 1.31 format.     \n*    \n* \\par    \n* \tIn this filter, filter coefficients are updated for each sample and the    \n* updation of filter cofficients are saturted.    \n*     \n*/\n\nvoid arm_lms_norm_q31(\n  arm_lms_norm_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */\n  q31_t mu = S->mu;                              /* Adaptive factor */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  q63_t energy;                                  /* Energy of the input */\n  q63_t acc;                                     /* Accumulator */\n  q31_t e = 0, d = 0;                            /* error, reference data sample */\n  q31_t w = 0, in;                               /* weight factor and state */\n  q31_t x0;                                      /* temporary variable to hold input sample */\n//  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */      \n  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */\n  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */\n  q31_t coef;                                    /* Temporary variable for coef */\n  q31_t acc_l, acc_h;                            /*  temporary input */\n  uint32_t uShift = ((uint32_t) S->postShift + 1u);\n  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */\n\n  energy = S->energy;\n  x0 = S->x0;\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  while(blkCnt > 0u)\n  {\n\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy = (q31_t) ((((q63_t) energy << 32) -\n                       (((q63_t) x0 * x0) << 1)) >> 32);\n    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += ((q63_t) (*px++)) * (*pb++);\n      acc += ((q63_t) (*px++)) * (*pb++);\n      acc += ((q63_t) (*px++)) * (*pb++);\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Converting the result to 1.31 format */\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q31_t) acc;\n\n    /* Compute and store error */\n    d = *pRef++;\n    e = d - (q31_t) acc;\n    *pErr++ = e;\n\n    /* Calculates the reciprocal of energy */\n    postShift = arm_recip_q31(energy + DELTA_Q31,\n                              &oneByEnergy, &S->recipTable[0]);\n\n    /* Calculation of product of (e * mu) */\n    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);\n\n    /* Weighting factor for the normalized version */\n    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n\n      /* coef is in 2.30 format */\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      /* get coef in 1.31 format by left shifting */\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      /* update coefficient buffer to next coefficient */\n      pb++;\n\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Read the sample from state buffer */\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Save energy and x0 values for the next frame */\n  S->energy = (q31_t) energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Loop unrolling for (numTaps - 1u) samples copy */\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(blkCnt > 0u)\n  {\n\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Read the sample from input buffer */\n    in = *pSrc++;\n\n    /* Update the energy calculation */\n    energy =\n      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);\n    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Converting the result to 1.31 format */\n    /* Converting the result to 1.31 format */\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n\n    //acc = (q31_t) (acc >> shift); \n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q31_t) acc;\n\n    /* Compute and store error */\n    d = *pRef++;\n    e = d - (q31_t) acc;\n    *pErr++ = e;\n\n    /* Calculates the reciprocal of energy */\n    postShift =\n      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);\n\n    /* Calculation of product of (e * mu) */\n    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);\n\n    /* Weighting factor for the normalized version */\n    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize coeff pointer */\n    pb = (pCoeffs);\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      /* coef is in 2.30 format */\n      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));\n      /* get coef in 1.31 format by left shifting */\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      /* update coefficient buffer to next coefficient */\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Read the sample from state buffer */\n    x0 = *pState;\n\n    /* Advance state pointer by 1 for the next sample */\n    pState = pState + 1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Save energy and x0 values for the next frame */\n  S->energy = (q31_t) energy;\n  S->x0 = x0;\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the     \n     start of the state buffer. This prepares the state buffer for the        \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Loop for (numTaps - 1u) samples copy */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of LMS_NORM group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_q15.c    \n*    \n* Description:\tProcessing function for the Q15 LMS filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n /**    \n * @brief Processing function for Q15 LMS filter.    \n * @param[in] *S points to an instance of the Q15 LMS filter structure.    \n * @param[in] *pSrc points to the block of input data.    \n * @param[in] *pRef points to the block of reference data.    \n * @param[out] *pOut points to the block of output data.    \n * @param[out] *pErr points to the block of error data.    \n * @param[in] blockSize number of samples to process.    \n * @return none.    \n *    \n * \\par Scaling and Overflow Behavior:    \n * The function is implemented using a 64-bit internal accumulator.    \n * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    \n * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    \n * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    \n * Lastly, the accumulator is saturated to yield a result in 1.15 format.    \n *   \n * \\par   \n * \tIn this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   \n *    \n */\n\nvoid arm_lms_q15(\n  const arm_lms_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize)\n{\n  q15_t *pState = S->pState;                     /* State pointer */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q15_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q15_t mu = S->mu;                              /* Adaptive factor */\n  q15_t *px;                                     /* Temporary pointer for state */\n  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  q63_t acc;                                     /* Accumulator */\n  q15_t e = 0;                                   /* error of data sample */\n  q15_t alpha;                                   /* Intermediate constant for taps update */\n  q31_t acc_l, acc_h;\n  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */\n  int32_t uShift = (32 - lShift);\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t coef;                                    /* Teporary variable for coefficient */\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Initializing blkCnt with blockSize */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2u;\n\n    while(tapCnt > 0u)\n    {\n      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */\n      /* Perform the multiply-accumulate */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);\n      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);\n\n#else\n\n      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));\n      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));\n      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));\n      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));\n\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    /* Apply shift for lower part of acc and upper part of acc */\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Converting the result to 1.15 format and saturate the output */\n    acc = __SSAT(acc, 16);\n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q15_t) acc;\n\n    /* Compute and store error */\n    e = *pRef++ - (q15_t) acc;\n\n    *pErr++ = (q15_t) e;\n\n    /* Compute alpha i.e. intermediate constant for taps update */\n    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);\n\n    /* Initialize state pointer */\n    /* Advance state pointer by 1 for the next sample */\n    px = pState++;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2u;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);\n      *pb++ = (q15_t) __SSAT((coef), 16);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Calculation of count for copying integer writes */\n  tapCnt = (numTaps - 1u) >> 2;\n\n  while(tapCnt > 0u)\n  {\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;\n#else\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n#endif\n\n    tapCnt--;\n\n  }\n\n  /* Calculation of count for remaining q15_t data */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += (q63_t) ((q31_t) (*px++) * (*pb++));\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    /* Apply shift for lower part of acc and upper part of acc */\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Converting the result to 1.15 format and saturate the output */\n    acc = __SSAT(acc, 16);\n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q15_t) acc;\n\n    /* Compute and store error */\n    e = *pRef++ - (q15_t) acc;\n\n    *pErr++ = (q15_t) e;\n\n    /* Compute alpha i.e. intermediate constant for taps update */\n    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);\n\n    /* Initialize pState pointer */\n    /* Advance state pointer by 1 for the next sample */\n    px = pState++;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the        \n     start of the state buffer. This prepares the state buffer for the   \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /*  Copy (numTaps - 1u) samples  */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of LMS group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_lms_q31.c    \n*    \n* Description:\tProcessing function for the Q31 LMS filter.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n/**    \n * @ingroup groupFilters    \n */\n\n/**    \n * @addtogroup LMS    \n * @{    \n */\n\n /**    \n * @brief Processing function for Q31 LMS filter.    \n * @param[in]  *S points to an instance of the Q15 LMS filter structure.    \n * @param[in]  *pSrc points to the block of input data.    \n * @param[in]  *pRef points to the block of reference data.    \n * @param[out] *pOut points to the block of output data.    \n * @param[out] *pErr points to the block of error data.    \n * @param[in]  blockSize number of samples to process.    \n * @return     none.    \n *    \n * \\par Scaling and Overflow Behavior:     \n * The function is implemented using an internal 64-bit accumulator.     \n * The accumulator has a 2.62 format and maintains full precision of the intermediate    \n * multiplication results but provides only a single guard bit.     \n * Thus, if the accumulator result overflows it wraps around rather than clips.     \n * In order to avoid overflows completely the input signal must be scaled down by    \n * log2(numTaps) bits.     \n * The reference signal should not be scaled down.     \n * After all multiply-accumulates are performed, the 2.62 accumulator is shifted    \n * and saturated to 1.31 format to yield the final result.     \n * The output signal and error signal are in 1.31 format.     \n *    \n * \\par    \n * \tIn this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    \n */\n\nvoid arm_lms_q31(\n  const arm_lms_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize)\n{\n  q31_t *pState = S->pState;                     /* State pointer */\n  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */\n  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */\n  q31_t *pStateCurnt;                            /* Points to the current sample of the state */\n  q31_t mu = S->mu;                              /* Adaptive factor */\n  q31_t *px;                                     /* Temporary pointer for state */\n  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */\n  uint32_t tapCnt, blkCnt;                       /* Loop counters */\n  q63_t acc;                                     /* Accumulator */\n  q31_t e = 0;                                   /* error of data sample */\n  q31_t alpha;                                   /* Intermediate constant for taps update */\n  q31_t coef;                                    /* Temporary variable for coef */\n  q31_t acc_l, acc_h;                            /*  temporary input */\n  uint32_t uShift = ((uint32_t) S->postShift + 1u);\n  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */\n\n  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */\n  /* pStateCurnt points to the location where the new input data should be written */\n  pStateCurnt = &(S->pState[(numTaps - 1u)]);\n\n  /* Initializing blkCnt with blockSize */\n  blkCnt = blockSize;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize state pointer */\n    px = pState;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      /* acc +=  b[N] * x[n-N] */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* acc +=  b[N-1] * x[n-N-1] */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* acc +=  b[N-2] * x[n-N-2] */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* acc +=  b[N-3] * x[n-N-3] */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Converting the result to 1.31 format */\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    /* Store the result from accumulator into the destination buffer. */\n    *pOut++ = (q31_t) acc;\n\n    /* Compute and store error */\n    e = *pRef++ - (q31_t) acc;\n\n    *pErr++ = (q31_t) e;\n\n    /* Compute alpha i.e. intermediate constant for taps update */\n    alpha = (q31_t) (((q63_t) e * mu) >> 31);\n\n    /* Initialize state pointer */\n    /* Advance state pointer by 1 for the next sample */\n    px = pState++;\n\n    /* Initialize coefficient pointer */\n    pb = pCoeffs;\n\n    /* Loop unrolling.  Process 4 taps at a time. */\n    tapCnt = numTaps >> 2;\n\n    /* Update filter coefficients */\n    while(tapCnt > 0u)\n    {\n      /* coef is in 2.30 format */\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      /* get coef in 1.31 format by left shifting */\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      /* update coefficient buffer to next coefficient */\n      pb++;\n\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* If the filter length is not a multiple of 4, compute the remaining filter taps */\n    tapCnt = numTaps % 0x4u;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the    \n     satrt of the state buffer. This prepares the state buffer for the    \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /* Loop unrolling for (numTaps - 1u) samples copy */\n  tapCnt = (numTaps - 1u) >> 2u;\n\n  /* copy data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n  /* Calculate remaining number of copies */\n  tapCnt = (numTaps - 1u) % 0x4u;\n\n  /* Copy the remaining q31_t data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  while(blkCnt > 0u)\n  {\n    /* Copy the new input sample into the state buffer */\n    *pStateCurnt++ = *pSrc++;\n\n    /* Initialize pState pointer */\n    px = pState;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Set the accumulator to zero */\n    acc = 0;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      acc += ((q63_t) (*px++)) * (*pb++);\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Converting the result to 1.31 format */\n    /* Store the result from accumulator into the destination buffer. */\n    /* Calc lower part of acc */\n    acc_l = acc & 0xffffffff;\n\n    /* Calc upper part of acc */\n    acc_h = (acc >> 32) & 0xffffffff;\n\n    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;\n\n    *pOut++ = (q31_t) acc;\n\n    /* Compute and store error */\n    e = *pRef++ - (q31_t) acc;\n\n    *pErr++ = (q31_t) e;\n\n    /* Weighting factor for the LMS version */\n    alpha = (q31_t) (((q63_t) e * mu) >> 31);\n\n    /* Initialize pState pointer */\n    /* Advance state pointer by 1 for the next sample */\n    px = pState++;\n\n    /* Initialize pCoeffs pointer */\n    pb = pCoeffs;\n\n    /* Loop over numTaps number of values */\n    tapCnt = numTaps;\n\n    while(tapCnt > 0u)\n    {\n      /* Perform the multiply-accumulate */\n      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));\n      *pb += (coef << 1u);\n      pb++;\n\n      /* Decrement the loop counter */\n      tapCnt--;\n    }\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Processing is complete. Now copy the last numTaps - 1 samples to the     \n     start of the state buffer. This prepares the state buffer for the   \n     next function call. */\n\n  /* Points to the start of the pState buffer */\n  pStateCurnt = S->pState;\n\n  /*  Copy (numTaps - 1u) samples  */\n  tapCnt = (numTaps - 1u);\n\n  /* Copy the data */\n  while(tapCnt > 0u)\n  {\n    *pStateCurnt++ = *pState++;\n\n    /* Decrement the loop counter */\n    tapCnt--;\n  }\n\n#endif /*   #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of LMS group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt",
    "content": "\n\n\n  1.0\n\n  
### uVision Project, (C) Keil Software
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  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj",
    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM0 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M0\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n          \n          \n          \n          4803\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM0l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          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       \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n            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arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              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      \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM0 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M0\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n          \n          \n          \n          4803\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM0l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DARMCM1.DLL\n          -pCM0\n          SARMCM3.DLL\n          \n          TARMCM1.DLL\n          -pCM0\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M0\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            3\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n  \n\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt",
    "content": "\n\n\n  1.0\n\n  
### uVision Project, (C) Keil Software
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  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj",
    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM3 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M3\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n          \n          \n          \n          4349\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM3l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM3\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM3\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M3\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            5\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM3 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M3\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n          \n          \n          \n          4349\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM3l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM3\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM3\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M3\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            3\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n            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    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM4 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n          \n          \n          \n          5125\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            5\n            2\n            1\n            \n              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mcpu=cortex-m4 -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n          \n          \n          \n          5125\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            3\n            2\n            1\n            \n              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mcpu=cortex-m4 -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE FPU\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4 FPU\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n          \n          \n          \n          5237\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4lf_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \"\" ()\n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            5\n            2\n            1\n            \n              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE FPU O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4 FPU\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n          \n          \n          \n          5237\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4lf_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\G++\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \"\" ()\n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n         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1\n            \n              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n  \n\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat",
    "content": "@echo off\n\nSET TMP=C:\\Temp\nSET TEMP=C:\\Temp\n\nSET UVEXE=C:\\Keil\\UV4\\UV4.EXE\n\necho.\necho   Building DSP Library for Cortex-M0 Little Endian\n%UVEXE% -rb arm_cortexM0x_math.uvproj -t\"DSP_Lib CM0 LE\" -o\"DSP_Lib CM0 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M3 Little Endian\n%UVEXE% -rb arm_cortexM3x_math.uvproj -t\"DSP_Lib CM3 LE\" -o\"DSP_Lib CM3 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M4 Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE\" -o\"DSP_Lib CM4 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M4 with FPU Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE FPU\" -o\"DSP_Lib CM4 LE FPU.txt\" -j0\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt",
    "content": "\n\n\n  1.0\n\n  
### uVision Project, (C) Keil Software
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  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj",
    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM0 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M0\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n          \n          \n          \n          4803\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM0l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            1\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            cmd.exe /C getSizeInfo \".\\intermediateFiles\\lib@L.a\" \"@L_SizeInfo.txt\"\n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DARMCM1.DLL\n          -pCM0\n          SARMCM3.DLL\n          \n          TARMCM1.DLL\n          -pCM0\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            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         0\n            0\n            5\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ../BasicMathFunctions/arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ../BasicMathFunctions/arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ../BasicMathFunctions/arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ../BasicMathFunctions/arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ../BasicMathFunctions/arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ../BasicMathFunctions/arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ../BasicMathFunctions/arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ../BasicMathFunctions/arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ../BasicMathFunctions/arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              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arm_negate_q7.c\n              1\n              ../BasicMathFunctions/arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ../BasicMathFunctions/arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ../BasicMathFunctions/arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ../BasicMathFunctions/arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ../BasicMathFunctions/arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ../BasicMathFunctions/arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ../BasicMathFunctions/arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ../BasicMathFunctions/arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ../BasicMathFunctions/arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ../BasicMathFunctions/arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ../BasicMathFunctions/arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ../BasicMathFunctions/arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ../BasicMathFunctions/arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ../BasicMathFunctions/arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ../BasicMathFunctions/arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              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    \n              arm_sin_q31.c\n              1\n              ../FastMathFunctions/arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ../FastMathFunctions/arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ../FastMathFunctions/arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              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    1\n              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c\n           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../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ../FilteringFunctions/arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ../FilteringFunctions/arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ../FilteringFunctions/arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ../FilteringFunctions/arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ../FilteringFunctions/arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ../FilteringFunctions/arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ../FilteringFunctions/arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ../FilteringFunctions/arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ../FilteringFunctions/arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ../FilteringFunctions/arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ../FilteringFunctions/arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ../FilteringFunctions/arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ../FilteringFunctions/arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ../FilteringFunctions/arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ../FilteringFunctions/arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ../FilteringFunctions/arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ../FilteringFunctions/arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ../FilteringFunctions/arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ../FilteringFunctions/arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ../FilteringFunctions/arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ../FilteringFunctions/arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ../FilteringFunctions/arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ../FilteringFunctions/arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ../FilteringFunctions/arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ../FilteringFunctions/arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ../FilteringFunctions/arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ../FilteringFunctions/arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ../FilteringFunctions/arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ../FilteringFunctions/arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ../MatrixFunctions/arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ../MatrixFunctions/arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ../MatrixFunctions/arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ../MatrixFunctions/arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ../MatrixFunctions/arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ../MatrixFunctions/arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ../MatrixFunctions/arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ../MatrixFunctions/arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ../MatrixFunctions/arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ../MatrixFunctions/arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ../MatrixFunctions/arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ../MatrixFunctions/arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ../MatrixFunctions/arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ../MatrixFunctions/arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ../MatrixFunctions/arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ../MatrixFunctions/arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ../MatrixFunctions/arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ../MatrixFunctions/arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ../MatrixFunctions/arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ../MatrixFunctions/arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ../MatrixFunctions/arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ../TransformFunctions/arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ../TransformFunctions/arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ../TransformFunctions/arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ../TransformFunctions/arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ../TransformFunctions/arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ../TransformFunctions/arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ../TransformFunctions/arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ../TransformFunctions/arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ../TransformFunctions/arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ../TransformFunctions/arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ../TransformFunctions/arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ../TransformFunctions/arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ../TransformFunctions/arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ../TransformFunctions/arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ../TransformFunctions/arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ../TransformFunctions/arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ../TransformFunctions/arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ../ControllerFunctions/arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ../ControllerFunctions/arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ../ControllerFunctions/arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ../ControllerFunctions/arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ../ControllerFunctions/arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ../ControllerFunctions/arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ../ControllerFunctions/arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ../ControllerFunctions/arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ../StatisticsFunctions/arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ../StatisticsFunctions/arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ../StatisticsFunctions/arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ../StatisticsFunctions/arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ../StatisticsFunctions/arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ../StatisticsFunctions/arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ../StatisticsFunctions/arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ../StatisticsFunctions/arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ../StatisticsFunctions/arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ../StatisticsFunctions/arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ../StatisticsFunctions/arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ../StatisticsFunctions/arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ../StatisticsFunctions/arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ../StatisticsFunctions/arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ../StatisticsFunctions/arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ../StatisticsFunctions/arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ../StatisticsFunctions/arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ../StatisticsFunctions/arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ../StatisticsFunctions/arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ../StatisticsFunctions/arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ../StatisticsFunctions/arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ../StatisticsFunctions/arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ../StatisticsFunctions/arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ../StatisticsFunctions/arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ../StatisticsFunctions/arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ../SupportFunctions/arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ../SupportFunctions/arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ../SupportFunctions/arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ../SupportFunctions/arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ../SupportFunctions/arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ../SupportFunctions/arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ../SupportFunctions/arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ../SupportFunctions/arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ../SupportFunctions/arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ../SupportFunctions/arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ../SupportFunctions/arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ../SupportFunctions/arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ../SupportFunctions/arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ../SupportFunctions/arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ../SupportFunctions/arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ../SupportFunctions/arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ../SupportFunctions/arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ../SupportFunctions/arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ../SupportFunctions/arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ../SupportFunctions/arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ../CommonTables/arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM0 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M0\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M0\") ESEL ELITTLE\n          \n          \n          \n          4803\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM0l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DARMCM1.DLL\n          -pCM0\n          SARMCM3.DLL\n          \n          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 1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M0\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            3\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM0, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ../BasicMathFunctions/arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ../BasicMathFunctions/arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ../BasicMathFunctions/arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ../BasicMathFunctions/arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ../BasicMathFunctions/arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ../BasicMathFunctions/arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ../BasicMathFunctions/arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ../BasicMathFunctions/arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ../BasicMathFunctions/arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ../BasicMathFunctions/arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ../BasicMathFunctions/arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ../BasicMathFunctions/arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ../BasicMathFunctions/arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ../BasicMathFunctions/arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ../BasicMathFunctions/arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ../BasicMathFunctions/arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ../BasicMathFunctions/arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ../BasicMathFunctions/arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ../BasicMathFunctions/arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ../BasicMathFunctions/arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ../BasicMathFunctions/arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ../BasicMathFunctions/arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ../BasicMathFunctions/arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ../BasicMathFunctions/arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ../BasicMathFunctions/arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ../BasicMathFunctions/arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ../BasicMathFunctions/arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ../BasicMathFunctions/arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ../BasicMathFunctions/arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ../BasicMathFunctions/arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ../BasicMathFunctions/arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ../BasicMathFunctions/arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ../BasicMathFunctions/arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ../BasicMathFunctions/arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ../BasicMathFunctions/arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ../FastMathFunctions/arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ../FastMathFunctions/arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ../FastMathFunctions/arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ../FastMathFunctions/arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ../FastMathFunctions/arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ../FastMathFunctions/arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ../FastMathFunctions/arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ../FastMathFunctions/arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ../FilteringFunctions/arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ../FilteringFunctions/arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ../FilteringFunctions/arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ../FilteringFunctions/arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ../FilteringFunctions/arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ../FilteringFunctions/arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ../FilteringFunctions/arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ../FilteringFunctions/arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ../FilteringFunctions/arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ../FilteringFunctions/arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ../FilteringFunctions/arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ../FilteringFunctions/arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ../FilteringFunctions/arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ../FilteringFunctions/arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ../FilteringFunctions/arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ../FilteringFunctions/arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ../FilteringFunctions/arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_decimate_init_f32.c\n            \n            \n    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arm_fir_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ../FilteringFunctions/arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ../FilteringFunctions/arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ../FilteringFunctions/arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ../FilteringFunctions/arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ../FilteringFunctions/arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ../FilteringFunctions/arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ../FilteringFunctions/arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ../FilteringFunctions/arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ../FilteringFunctions/arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ../FilteringFunctions/arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ../FilteringFunctions/arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ../FilteringFunctions/arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ../FilteringFunctions/arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ../FilteringFunctions/arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ../FilteringFunctions/arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ../FilteringFunctions/arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ../FilteringFunctions/arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ../FilteringFunctions/arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ../MatrixFunctions/arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ../MatrixFunctions/arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ../MatrixFunctions/arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ../MatrixFunctions/arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ../MatrixFunctions/arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ../MatrixFunctions/arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ../MatrixFunctions/arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ../MatrixFunctions/arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ../MatrixFunctions/arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ../MatrixFunctions/arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ../MatrixFunctions/arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ../MatrixFunctions/arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ../MatrixFunctions/arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ../MatrixFunctions/arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ../MatrixFunctions/arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ../MatrixFunctions/arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ../MatrixFunctions/arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ../MatrixFunctions/arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ../MatrixFunctions/arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ../MatrixFunctions/arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ../MatrixFunctions/arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ../TransformFunctions/arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ../TransformFunctions/arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ../TransformFunctions/arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ../TransformFunctions/arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ../TransformFunctions/arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ../TransformFunctions/arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ../TransformFunctions/arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ../TransformFunctions/arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ../TransformFunctions/arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ../TransformFunctions/arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ../TransformFunctions/arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ../TransformFunctions/arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ../TransformFunctions/arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ../TransformFunctions/arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ../TransformFunctions/arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ../TransformFunctions/arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ../TransformFunctions/arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ../TransformFunctions/arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ../TransformFunctions/arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ../ControllerFunctions/arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ../ControllerFunctions/arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ../ControllerFunctions/arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ../ControllerFunctions/arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ../ControllerFunctions/arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ../ControllerFunctions/arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ../ControllerFunctions/arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ../ControllerFunctions/arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ../StatisticsFunctions/arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ../StatisticsFunctions/arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ../StatisticsFunctions/arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ../StatisticsFunctions/arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ../StatisticsFunctions/arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ../StatisticsFunctions/arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ../StatisticsFunctions/arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ../StatisticsFunctions/arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ../StatisticsFunctions/arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ../StatisticsFunctions/arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ../StatisticsFunctions/arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ../StatisticsFunctions/arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ../StatisticsFunctions/arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ../StatisticsFunctions/arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ../StatisticsFunctions/arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ../StatisticsFunctions/arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ../StatisticsFunctions/arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ../StatisticsFunctions/arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ../StatisticsFunctions/arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ../StatisticsFunctions/arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ../StatisticsFunctions/arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ../StatisticsFunctions/arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ../StatisticsFunctions/arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ../StatisticsFunctions/arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ../StatisticsFunctions/arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ../SupportFunctions/arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ../SupportFunctions/arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ../SupportFunctions/arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ../SupportFunctions/arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ../SupportFunctions/arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ../SupportFunctions/arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ../SupportFunctions/arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ../SupportFunctions/arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ../SupportFunctions/arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ../SupportFunctions/arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ../SupportFunctions/arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ../SupportFunctions/arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ../SupportFunctions/arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ../SupportFunctions/arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ../SupportFunctions/arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ../SupportFunctions/arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ../SupportFunctions/arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ../SupportFunctions/arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ../SupportFunctions/arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ../SupportFunctions/arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ../CommonTables/arm_common_tables.c\n            \n          \n        \n      \n    \n  \n\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt",
    "content": "\n\n\n  1.0\n\n  
### uVision Project, (C) Keil Software
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  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj",
    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM3 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M3\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n          \n          \n          \n          4349\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM3l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            1\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            cmd.exe /C getSizeInfo \".\\intermediateFiles\\lib@L.a\" \"@L_SizeInfo.txt\"\n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM3\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM3\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M3\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n     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0\n            0\n            5\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              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arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM3 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M3\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M3\") ESEL ELITTLE\n          \n          \n          \n          4349\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM3l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM3\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM3\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M3\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n              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       -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM3, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              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     1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n  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  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt",
    "content": "\n\n\n  1.0\n\n  
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    ..\\SupportFunctions\\arm_q15_to_q31.c\n      arm_q15_to_q31.c\n      0\n      0\n    \n    \n      9\n      258\n      1\n      0\n      0\n      0\n      0\n      0\n      0\n      0\n      ..\\SupportFunctions\\arm_q31_to_float.c\n      arm_q31_to_float.c\n      0\n      0\n    \n    \n      9\n      259\n      1\n      0\n      0\n      0\n      0\n      0\n      0\n      0\n      ..\\SupportFunctions\\arm_q31_to_q7.c\n      arm_q31_to_q7.c\n      0\n      0\n    \n    \n      9\n      260\n      1\n      0\n      0\n      0\n      0\n      0\n      0\n      0\n      ..\\SupportFunctions\\arm_q31_to_q15.c\n      arm_q31_to_q15.c\n      0\n      0\n    \n  \n\n  \n    CommonTables\n    0\n    0\n    0\n    0\n    \n      10\n      261\n      1\n      0\n      0\n      0\n      0\n      0\n      0\n      0\n      ..\\CommonTables\\arm_common_tables.c\n      arm_common_tables.c\n      0\n      0\n    \n  \n\n\n"
  },
  {
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    "content": "\n\n\n  1.1\n\n  
### uVision Project, (C) Keil Software
\n\n  \n    \n      DSP_Lib CM4 LE\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n          \n          \n          \n          5125\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            1\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            cmd.exe /C getSizeInfo \".\\intermediateFiles\\lib@L.a\" \"@L_SizeInfo.txt\"\n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n       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0\n            0\n            5\n            2\n            1\n            \n              -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              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     arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              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arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE\n          \n          \n          \n          5125\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4l_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n              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       -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              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     1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE FPU\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4 FPU\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n          \n          \n          \n          5237\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4lf_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            1\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            cmd.exe /C getSizeInfo \".\\intermediateFiles\\lib@L.a\" \"@L_SizeInfo.txt\"\n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \"\" ()\n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            5\n            2\n            1\n            \n              -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n    \n      DSP_Lib CM4 LE FPU O2\n      0x3\n      ARM-GNU\n      \n        \n          Cortex-M4 FPU\n          ARM\n          CLOCK(12000000) CPUTYPE(\"Cortex-M4\") ESEL ELITTLE FPU2\n          \n          \n          \n          5237\n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          \n          0\n          \n          \n          \n          \n          \n          \n            0\n            0\n            0\n            0\n            1\n          \n          .\\intermediateFiles\\\n          arm_cortexM4lf_math\n          0\n          1\n          0\n          1\n          0\n          .\\intermediateFiles\\\n          1\n          0\n          0\n          \n            0\n            0\n            \n            \n            0\n            0\n            0\n            0\n          \n          \n            0\n            0\n            \n            \n            0\n            0\n          \n          \n            1\n            0\n            cmd.exe /C copy \".\\intermediateFiles\\lib@L.a\" \"..\\..\\..\\Lib\\GCC\\\"\n            \n            0\n            0\n          \n          0\n          \n        \n        \n          0\n          0\n          0\n          0\n          0\n          1\n          0\n          0\n          0\n          0\n          3\n          \n          \n        \n        \n          SARMCM3.DLL\n          \n          DCM.DLL\n          -pCM4\n          SARMCM3.DLL\n          \n          TCM.DLL\n          -pCM4\n        \n        \n          \n            1\n            0\n            0\n            0\n            16\n          \n          \n            1\n            0\n            0\n            1\n            1\n            1\n            1\n            1\n            0\n          \n          \n            0\n            0\n            0\n            1\n            1\n            1\n            0\n            1\n            0\n          \n          0\n          -1\n          \n            \n            \n            \n            \n            \n          \n          \n            \n            \n            \n            \n            \n            \n          \n        \n        \n          \n            1\n            0\n            0\n            0\n            0\n            -1\n          \n          \n          \"\" ()\n          \n        \n        \n          \n            0\n            1\n            1\n            1\n            1\n            1\n            1\n            1\n            0\n            1\n            1\n            0\n            \"Cortex-M4\"\n            0\n            0\n            0\n            0\n            0\n            0\n            0\n            2\n            0\n            0\n            \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n              \n                0\n                0x0\n                0x0\n              \n            \n          \n          \n            0\n            0\n            0\n            0\n            0\n            0\n            3\n            2\n            1\n            \n              -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fno-strict-aliasing -ffunction-sections\n              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, __FPU_PRESENT = 1, UNALIGNED_SUPPORT_DISABLE\n              \n              ..\\..\\..\\Include\n            \n          \n          \n            0\n            0\n            \n              \n              \n              \n              \n            \n          \n          \n            1\n            0\n            1\n            0\n            1\n            \n            \n            \n            \n            \n            -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections\n            \n          \n        \n      \n      \n        \n          BasicMathFunctions\n          \n            \n              arm_abs_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_f32.c\n            \n            \n              arm_abs_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q7.c\n            \n            \n              arm_abs_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q15.c\n            \n            \n              arm_abs_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_abs_q31.c\n            \n            \n              arm_add_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_add_f32.c\n            \n            \n              arm_add_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q7.c\n            \n            \n              arm_add_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q15.c\n            \n            \n              arm_add_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_add_q31.c\n            \n            \n              arm_dot_prod_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_f32.c\n            \n            \n              arm_dot_prod_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q7.c\n            \n            \n              arm_dot_prod_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q15.c\n            \n            \n              arm_dot_prod_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_dot_prod_q31.c\n            \n            \n              arm_mult_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_f32.c\n            \n            \n              arm_mult_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q7.c\n            \n            \n              arm_mult_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q15.c\n            \n            \n              arm_mult_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_mult_q31.c\n            \n            \n              arm_negate_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_f32.c\n            \n            \n              arm_negate_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q7.c\n            \n            \n              arm_negate_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q15.c\n            \n            \n              arm_negate_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_negate_q31.c\n            \n            \n              arm_offset_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_f32.c\n            \n            \n              arm_offset_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q7.c\n            \n            \n              arm_offset_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q15.c\n            \n            \n              arm_offset_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_offset_q31.c\n            \n            \n              arm_scale_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_f32.c\n            \n            \n              arm_scale_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q7.c\n            \n            \n              arm_scale_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q15.c\n            \n            \n              arm_scale_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_scale_q31.c\n            \n            \n              arm_shift_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q7.c\n            \n            \n              arm_shift_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q15.c\n            \n            \n              arm_shift_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_shift_q31.c\n            \n            \n              arm_sub_f32.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_f32.c\n            \n            \n              arm_sub_q7.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q7.c\n            \n            \n              arm_sub_q15.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q15.c\n            \n            \n              arm_sub_q31.c\n              1\n              ..\\BasicMathFunctions\\arm_sub_q31.c\n            \n          \n        \n        \n          FastMathFunctions\n          \n            \n              arm_cos_f32.c\n              1\n              ..\\FastMathFunctions\\arm_cos_f32.c\n            \n            \n              arm_cos_q15.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q15.c\n            \n            \n              arm_cos_q31.c\n              1\n              ..\\FastMathFunctions\\arm_cos_q31.c\n            \n            \n              arm_sin_f32.c\n              1\n              ..\\FastMathFunctions\\arm_sin_f32.c\n            \n            \n              arm_sin_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q15.c\n            \n            \n              arm_sin_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sin_q31.c\n            \n            \n              arm_sqrt_q15.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q15.c\n            \n            \n              arm_sqrt_q31.c\n              1\n              ..\\FastMathFunctions\\arm_sqrt_q31.c\n            \n          \n        \n        \n          ComplexMathFunctions\n          \n            \n              arm_cmplx_conj_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_f32.c\n            \n            \n              arm_cmplx_conj_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q15.c\n            \n            \n              arm_cmplx_conj_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_conj_q31.c\n            \n            \n              arm_cmplx_dot_prod_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_f32.c\n            \n            \n              arm_cmplx_dot_prod_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q15.c\n            \n            \n              arm_cmplx_dot_prod_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_dot_prod_q31.c\n            \n            \n              arm_cmplx_mag_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_f32.c\n            \n            \n              arm_cmplx_mag_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q15.c\n            \n            \n              arm_cmplx_mag_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_q31.c\n            \n            \n              arm_cmplx_mag_squared_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_f32.c\n            \n            \n              arm_cmplx_mag_squared_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q15.c\n            \n            \n              arm_cmplx_mag_squared_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mag_squared_q31.c\n            \n            \n              arm_cmplx_mult_cmplx_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_f32.c\n            \n            \n              arm_cmplx_mult_cmplx_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q15.c\n            \n            \n              arm_cmplx_mult_cmplx_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_cmplx_q31.c\n            \n            \n              arm_cmplx_mult_real_f32.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_f32.c\n            \n            \n              arm_cmplx_mult_real_q15.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q15.c\n            \n            \n              arm_cmplx_mult_real_q31.c\n              1\n              ..\\ComplexMathFunctions\\arm_cmplx_mult_real_q31.c\n            \n          \n        \n        \n          FilteringFunctions\n          \n            \n              arm_biquad_cascade_df1_32x64_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_32x64_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_32x64_q31.c\n            \n            \n              arm_biquad_cascade_df1_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_f32.c\n            \n            \n              arm_biquad_cascade_df1_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q15.c\n            \n            \n              arm_biquad_cascade_df1_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_fast_q31.c\n            \n            \n              arm_biquad_cascade_df1_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_f32.c\n            \n            \n              arm_biquad_cascade_df1_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q15.c\n            \n            \n              arm_biquad_cascade_df1_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_init_q31.c\n            \n            \n              arm_biquad_cascade_df1_q15.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q15.c\n            \n            \n              arm_biquad_cascade_df1_q31.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df1_q31.c\n            \n            \n              arm_biquad_cascade_df2T_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_f32.c\n            \n            \n              arm_biquad_cascade_df2T_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_biquad_cascade_df2T_init_f32.c\n            \n            \n              arm_conv_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_f32.c\n            \n            \n              arm_conv_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_opt_q15.c\n            \n            \n              arm_conv_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q15.c\n            \n            \n              arm_conv_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_fast_q31.c\n            \n            \n              arm_conv_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q7.c\n            \n            \n              arm_conv_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_opt_q15.c\n            \n            \n              arm_conv_partial_f32.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_f32.c\n            \n            \n              arm_conv_partial_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_opt_q15.c\n            \n            \n              arm_conv_partial_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q15.c\n            \n            \n              arm_conv_partial_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_fast_q31.c\n            \n            \n              arm_conv_partial_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q7.c\n            \n            \n              arm_conv_partial_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_opt_q15.c\n            \n            \n              arm_conv_partial_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q7.c\n            \n            \n              arm_conv_partial_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q15.c\n            \n            \n              arm_conv_partial_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_partial_q31.c\n            \n            \n              arm_conv_q7.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q7.c\n            \n            \n              arm_conv_q15.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q15.c\n            \n            \n              arm_conv_q31.c\n              1\n              ..\\FilteringFunctions\\arm_conv_q31.c\n            \n            \n              arm_correlate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_f32.c\n            \n            \n              arm_correlate_fast_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_opt_q15.c\n            \n            \n              arm_correlate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q15.c\n            \n            \n              arm_correlate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_fast_q31.c\n            \n            \n              arm_correlate_opt_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q7.c\n            \n            \n              arm_correlate_opt_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_opt_q15.c\n            \n            \n              arm_correlate_q7.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q7.c\n            \n            \n              arm_correlate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q15.c\n            \n            \n              arm_correlate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_correlate_q31.c\n            \n            \n              arm_fir_decimate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_f32.c\n            \n            \n              arm_fir_decimate_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q15.c\n            \n            \n              arm_fir_decimate_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_fast_q31.c\n            \n            \n              arm_fir_decimate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_f32.c\n            \n            \n              arm_fir_decimate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q15.c\n            \n            \n              arm_fir_decimate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_init_q31.c\n            \n            \n              arm_fir_decimate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q15.c\n            \n            \n              arm_fir_decimate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_decimate_q31.c\n            \n            \n              arm_fir_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_f32.c\n            \n            \n              arm_fir_fast_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q15.c\n            \n            \n              arm_fir_fast_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_fast_q31.c\n            \n            \n              arm_fir_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_f32.c\n            \n            \n              arm_fir_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q7.c\n            \n            \n              arm_fir_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q15.c\n            \n            \n              arm_fir_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_init_q31.c\n            \n            \n              arm_fir_interpolate_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_f32.c\n            \n            \n              arm_fir_interpolate_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_f32.c\n            \n            \n              arm_fir_interpolate_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q15.c\n            \n            \n              arm_fir_interpolate_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_init_q31.c\n            \n            \n              arm_fir_interpolate_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q15.c\n            \n            \n              arm_fir_interpolate_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_interpolate_q31.c\n            \n            \n              arm_fir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_f32.c\n            \n            \n              arm_fir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_f32.c\n            \n            \n              arm_fir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q15.c\n            \n            \n              arm_fir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_init_q31.c\n            \n            \n              arm_fir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q15.c\n            \n            \n              arm_fir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_lattice_q31.c\n            \n            \n              arm_fir_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q7.c\n            \n            \n              arm_fir_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q15.c\n            \n            \n              arm_fir_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_q31.c\n            \n            \n              arm_fir_sparse_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_f32.c\n            \n            \n              arm_fir_sparse_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_f32.c\n            \n            \n              arm_fir_sparse_init_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q7.c\n            \n            \n              arm_fir_sparse_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q15.c\n            \n            \n              arm_fir_sparse_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_init_q31.c\n            \n            \n              arm_fir_sparse_q7.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q7.c\n            \n            \n              arm_fir_sparse_q15.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q15.c\n            \n            \n              arm_fir_sparse_q31.c\n              1\n              ..\\FilteringFunctions\\arm_fir_sparse_q31.c\n            \n            \n              arm_iir_lattice_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_f32.c\n            \n            \n              arm_iir_lattice_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_f32.c\n            \n            \n              arm_iir_lattice_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q15.c\n            \n            \n              arm_iir_lattice_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_init_q31.c\n            \n            \n              arm_iir_lattice_q15.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q15.c\n            \n            \n              arm_iir_lattice_q31.c\n              1\n              ..\\FilteringFunctions\\arm_iir_lattice_q31.c\n            \n            \n              arm_lms_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_f32.c\n            \n            \n              arm_lms_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_f32.c\n            \n            \n              arm_lms_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q15.c\n            \n            \n              arm_lms_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_init_q31.c\n            \n            \n              arm_lms_norm_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_f32.c\n            \n            \n              arm_lms_norm_init_f32.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_f32.c\n            \n            \n              arm_lms_norm_init_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q15.c\n            \n            \n              arm_lms_norm_init_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_init_q31.c\n            \n            \n              arm_lms_norm_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q15.c\n            \n            \n              arm_lms_norm_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_norm_q31.c\n            \n            \n              arm_lms_q15.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q15.c\n            \n            \n              arm_lms_q31.c\n              1\n              ..\\FilteringFunctions\\arm_lms_q31.c\n            \n          \n        \n        \n          MatrixFunctions\n          \n            \n              arm_mat_add_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_f32.c\n            \n            \n              arm_mat_add_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q15.c\n            \n            \n              arm_mat_add_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_add_q31.c\n            \n            \n              arm_mat_init_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_f32.c\n            \n            \n              arm_mat_init_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q15.c\n            \n            \n              arm_mat_init_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_init_q31.c\n            \n            \n              arm_mat_inverse_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_inverse_f32.c\n            \n            \n              arm_mat_mult_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_f32.c\n            \n            \n              arm_mat_mult_fast_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q15.c\n            \n            \n              arm_mat_mult_fast_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_fast_q31.c\n            \n            \n              arm_mat_mult_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q15.c\n            \n            \n              arm_mat_mult_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_mult_q31.c\n            \n            \n              arm_mat_scale_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_f32.c\n            \n            \n              arm_mat_scale_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q15.c\n            \n            \n              arm_mat_scale_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_scale_q31.c\n            \n            \n              arm_mat_sub_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_f32.c\n            \n            \n              arm_mat_sub_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q15.c\n            \n            \n              arm_mat_sub_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_sub_q31.c\n            \n            \n              arm_mat_trans_f32.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_f32.c\n            \n            \n              arm_mat_trans_q15.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q15.c\n            \n            \n              arm_mat_trans_q31.c\n              1\n              ..\\MatrixFunctions\\arm_mat_trans_q31.c\n            \n          \n        \n        \n          TransformFunctions\n          \n            \n              arm_bitreversal.c\n              1\n              ..\\TransformFunctions\\arm_bitreversal.c\n            \n            \n              arm_bitreversal2.S\n              1\n              ..\\TransformFunctions\\arm_bitreversal2.S\n            \n            \n              arm_cfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_f32.c\n            \n            \n              arm_cfft_radix2_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_f32.c\n            \n            \n              arm_cfft_radix2_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_f32.c\n            \n            \n              arm_cfft_radix2_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q15.c\n            \n            \n              arm_cfft_radix2_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_init_q31.c\n            \n            \n              arm_cfft_radix2_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q15.c\n            \n            \n              arm_cfft_radix2_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix2_q31.c\n            \n            \n              arm_cfft_radix4_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_f32.c\n            \n            \n              arm_cfft_radix4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_f32.c\n            \n            \n              arm_cfft_radix4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q15.c\n            \n            \n              arm_cfft_radix4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_init_q31.c\n            \n            \n              arm_cfft_radix4_q15.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q15.c\n            \n            \n              arm_cfft_radix4_q31.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix4_q31.c\n            \n            \n              arm_cfft_radix8_f32.c\n              1\n              ..\\TransformFunctions\\arm_cfft_radix8_f32.c\n            \n            \n              arm_dct4_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_f32.c\n            \n            \n              arm_dct4_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_f32.c\n            \n            \n              arm_dct4_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q15.c\n            \n            \n              arm_dct4_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_init_q31.c\n            \n            \n              arm_dct4_q15.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q15.c\n            \n            \n              arm_dct4_q31.c\n              1\n              ..\\TransformFunctions\\arm_dct4_q31.c\n            \n            \n              arm_rfft_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_f32.c\n            \n            \n              arm_rfft_fast_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_f32.c\n            \n            \n              arm_rfft_fast_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_fast_init_f32.c\n            \n            \n              arm_rfft_init_f32.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_f32.c\n            \n            \n              arm_rfft_init_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q15.c\n            \n            \n              arm_rfft_init_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_init_q31.c\n            \n            \n              arm_rfft_q15.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q15.c\n            \n            \n              arm_rfft_q31.c\n              1\n              ..\\TransformFunctions\\arm_rfft_q31.c\n            \n          \n        \n        \n          ControllerFunctions\n          \n            \n              arm_pid_init_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_f32.c\n            \n            \n              arm_pid_init_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q15.c\n            \n            \n              arm_pid_init_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_init_q31.c\n            \n            \n              arm_pid_reset_f32.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_f32.c\n            \n            \n              arm_pid_reset_q15.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q15.c\n            \n            \n              arm_pid_reset_q31.c\n              1\n              ..\\ControllerFunctions\\arm_pid_reset_q31.c\n            \n            \n              arm_sin_cos_f32.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_f32.c\n            \n            \n              arm_sin_cos_q31.c\n              1\n              ..\\ControllerFunctions\\arm_sin_cos_q31.c\n            \n          \n        \n        \n          StatisticsFunctions\n          \n            \n              arm_max_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_max_f32.c\n            \n            \n              arm_max_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q7.c\n            \n            \n              arm_max_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q15.c\n            \n            \n              arm_max_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_max_q31.c\n            \n            \n              arm_mean_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_f32.c\n            \n            \n              arm_mean_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q7.c\n            \n            \n              arm_mean_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q15.c\n            \n            \n              arm_mean_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_mean_q31.c\n            \n            \n              arm_min_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_min_f32.c\n            \n            \n              arm_min_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q7.c\n            \n            \n              arm_min_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q15.c\n            \n            \n              arm_min_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_min_q31.c\n            \n            \n              arm_power_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_power_f32.c\n            \n            \n              arm_power_q7.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q7.c\n            \n            \n              arm_power_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q15.c\n            \n            \n              arm_power_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_power_q31.c\n            \n            \n              arm_rms_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_f32.c\n            \n            \n              arm_rms_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q15.c\n            \n            \n              arm_rms_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_rms_q31.c\n            \n            \n              arm_std_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_std_f32.c\n            \n            \n              arm_std_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q15.c\n            \n            \n              arm_std_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_std_q31.c\n            \n            \n              arm_var_f32.c\n              1\n              ..\\StatisticsFunctions\\arm_var_f32.c\n            \n            \n              arm_var_q15.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q15.c\n            \n            \n              arm_var_q31.c\n              1\n              ..\\StatisticsFunctions\\arm_var_q31.c\n            \n          \n        \n        \n          SupportFunctions\n          \n            \n              arm_copy_f32.c\n              1\n              ..\\SupportFunctions\\arm_copy_f32.c\n            \n            \n              arm_copy_q7.c\n              1\n              ..\\SupportFunctions\\arm_copy_q7.c\n            \n            \n              arm_copy_q15.c\n              1\n              ..\\SupportFunctions\\arm_copy_q15.c\n            \n            \n              arm_copy_q31.c\n              1\n              ..\\SupportFunctions\\arm_copy_q31.c\n            \n            \n              arm_fill_f32.c\n              1\n              ..\\SupportFunctions\\arm_fill_f32.c\n            \n            \n              arm_fill_q7.c\n              1\n              ..\\SupportFunctions\\arm_fill_q7.c\n            \n            \n              arm_fill_q15.c\n              1\n              ..\\SupportFunctions\\arm_fill_q15.c\n            \n            \n              arm_fill_q31.c\n              1\n              ..\\SupportFunctions\\arm_fill_q31.c\n            \n            \n              arm_float_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q7.c\n            \n            \n              arm_float_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q15.c\n            \n            \n              arm_float_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_float_to_q31.c\n            \n            \n              arm_q7_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_float.c\n            \n            \n              arm_q7_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q15.c\n            \n            \n              arm_q7_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q7_to_q31.c\n            \n            \n              arm_q15_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_float.c\n            \n            \n              arm_q15_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q7.c\n            \n            \n              arm_q15_to_q31.c\n              1\n              ..\\SupportFunctions\\arm_q15_to_q31.c\n            \n            \n              arm_q31_to_float.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_float.c\n            \n            \n              arm_q31_to_q7.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q7.c\n            \n            \n              arm_q31_to_q15.c\n              1\n              ..\\SupportFunctions\\arm_q31_to_q15.c\n            \n          \n        \n        \n          CommonTables\n          \n            \n              arm_common_tables.c\n              1\n              ..\\CommonTables\\arm_common_tables.c\n            \n          \n        \n      \n    \n  \n\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat",
    "content": "@echo off\n\nSET TMP=C:\\Temp\nSET TEMP=C:\\Temp\n\nSET UVEXE=C:\\Keil\\UV4\\UV4.EXE\n\necho.\necho   Building DSP Library for Cortex-M0 Little Endian\n%UVEXE% -rb arm_cortexM0x_math.uvproj -t\"DSP_Lib CM0 LE\" -o\"DSP_Lib CM0 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M3 Little Endian\n%UVEXE% -rb arm_cortexM3x_math.uvproj -t\"DSP_Lib CM3 LE\" -o\"DSP_Lib CM3 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M4 Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE\" -o\"DSP_Lib CM4 LE.txt\" -j0\n\necho.\necho   Building DSP Library for Cortex-M4 with FPU Little Endian\n%UVEXE% -rb arm_cortexM4x_math.uvproj -t\"DSP_Lib CM4 LE FPU\" -o\"DSP_Lib CM4 LE FPU.txt\" -j0\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/GCC/getSizeInfo.bat",
    "content": "@echo off\n\nif .%1==. goto help\nif exist %1 goto getSizeInfo\ngoto help\n\n:getSizeInfo\narm-none-eabi-size -t %1 > %2\ngoto end\n\n:help\necho   Syntax: getSizeInfo inFile outFile\necho.\necho   e.g.: getSizeInfo .\\intermediateFiles\\libarm_cortexM0l_math.a  arm_cortexM0l_math.txt\n\n:end\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_mat_add_f32.c    \n*    \n* Description:\tFloating-point matrix addition    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupMatrix        \n */\n\n/**        \n * @defgroup MatrixAdd Matrix Addition        \n *        \n * Adds two matrices.        \n * \\image html MatrixAddition.gif \"Addition of two 3 x 3 matrices\"        \n *        \n * The functions check to make sure that        \n * pSrcA, pSrcB, and pDst have the same        \n * number of rows and columns.        \n */\n\n/**        \n * @addtogroup MatrixAdd        \n * @{        \n */\n\n\n/**        \n * @brief Floating-point matrix addition.        \n * @param[in]       *pSrcA points to the first input matrix structure        \n * @param[in]       *pSrcB points to the second input matrix structure        \n * @param[out]      *pDst points to output matrix structure        \n * @return     \t\tThe function returns either        \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        \n */\n\narm_status arm_mat_add_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */\n  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  uint32_t numSamples;                           /* total number of elements in the matrix  */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix addition */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif\n  {\n\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Loop unrolling */\n    blkCnt = numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add and then store the results in the destination buffer. */\n      /* Read values from source A */\n      inA1 = pIn1[0];\n\n      /* Read values from source B */\n      inB1 = pIn2[0];\n\n      /* Read values from source A */\n      inA2 = pIn1[1];\n\n      /* out = sourceA + sourceB */\n      out1 = inA1 + inB1;\n\n      /* Read values from source B */\n      inB2 = pIn2[1];\n\n      /* Read values from source A */\n      inA1 = pIn1[2];\n\n      /* out = sourceA + sourceB */\n      out2 = inA2 + inB2;\n\n      /* Read values from source B */\n      inB1 = pIn2[2];\n\n      /* Store result in destination */\n      pOut[0] = out1;\n      pOut[1] = out2;\n\n      /* Read values from source A */\n      inA2 = pIn1[3];\n\n      /* Read values from source B */\n      inB2 = pIn2[3];\n\n      /* out = sourceA + sourceB */\n      out1 = inA1 + inB1;\n\n      /* out = sourceA + sourceB */\n      out2 = inA2 + inB2;\n\n      /* Store result in destination */\n      pOut[2] = out1;\n\n      /* Store result in destination */\n      pOut[3] = out2;\n\n\n      /* update pointers to process next sampels */\n      pIn1 += 4u;\n      pIn2 += 4u;\n      pOut += 4u;\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add and then store the results in the destination buffer. */\n      *pOut++ = (*pIn1++) + (*pIn2++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixAdd group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_add_q15.c    \n*    \n* Description:\tQ15 matrix addition    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixAdd    \n * @{    \n */\n\n/**    \n * @brief Q15 matrix addition.    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    \n */\n\narm_status arm_mat_add_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst)\n{\n  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */\n  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */\n  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  uint16_t numSamples;                           /* total number of elements in the matrix  */\n  uint32_t blkCnt;                               /* loop counters  */\n  arm_status status;                             /* status of matrix addition  */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop unrolling */\n    blkCnt = (uint32_t) numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add, Saturate and then store the results in the destination buffer. */\n      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);\n      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = (uint32_t) numSamples % 0x4u;\n\n    /* q15 pointers of input and output are initialized */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add, Saturate and then store the results in the destination buffer. */\n      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = (uint32_t) numSamples;\n\n\n    /* q15 pointers of input and output are initialized */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add, Saturate and then store the results in the destination buffer. */\n      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixAdd group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_add_q31.c    \n*    \n* Description:\tQ31 matrix addition    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**      \n * @ingroup groupMatrix      \n */\n\n/**      \n * @addtogroup MatrixAdd      \n * @{      \n */\n\n/**      \n * @brief Q31 matrix addition.      \n * @param[in]       *pSrcA points to the first input matrix structure      \n * @param[in]       *pSrcB points to the second input matrix structure      \n * @param[out]      *pDst points to output matrix structure      \n * @return     \t\tThe function returns either      \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      \n *      \n * Scaling and Overflow Behavior:      \n * \\par      \n * The function uses saturating arithmetic.      \n * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.      \n */\n\narm_status arm_mat_add_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */\n  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */\n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  q31_t inA1, inB1;                              /* temporary variables */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q31_t inA2, inB2;                              /* temporary variables */\n  q31_t out1, out2;                              /* temporary variables */\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  uint32_t numSamples;                           /* total number of elements in the matrix  */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix addition */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2u;\n\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add, saturate and then store the results in the destination buffer. */\n      /* Read values from source A */\n      inA1 = pIn1[0];\n\n      /* Read values from source B */\n      inB1 = pIn2[0];\n\n      /* Read values from source A */\n      inA2 = pIn1[1];\n\n      /* Add and saturate */\n      out1 = __QADD(inA1, inB1);\n\n      /* Read values from source B */\n      inB2 = pIn2[1];\n\n      /* Read values from source A */\n      inA1 = pIn1[2];\n\n      /* Add and saturate */\n      out2 = __QADD(inA2, inB2);\n\n      /* Read values from source B */\n      inB1 = pIn2[2];\n\n      /* Store result in destination */\n      pOut[0] = out1;\n      pOut[1] = out2;\n\n      /* Read values from source A */\n      inA2 = pIn1[3];\n\n      /* Read values from source B */\n      inB2 = pIn2[3];\n\n      /* Add and saturate */\n      out1 = __QADD(inA1, inB1);\n      out2 = __QADD(inA2, inB2);\n\n      /* Store result in destination */\n      pOut[2] = out1;\n      pOut[3] = out2;\n\n      /* update pointers to process next sampels */\n      pIn1 += 4u;\n      pIn2 += 4u;\n      pOut += 4u;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.      \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) + B(m,n) */\n      /* Add, saturate and then store the results in the destination buffer. */\n      inA1 = *pIn1++;\n      inB1 = *pIn2++;\n\n      inA1 = __QADD(inA1, inB1);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n\n      *pOut++ = inA1;\n\n    }\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**      \n * @} end of MatrixAdd group      \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_mat_init_f32.c    \n*    \n* Description:\tFloating-point matrix initialization.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @defgroup MatrixInit Matrix Initialization    \n *    \n * Initializes the underlying matrix data structure.    \n * The functions set the numRows,    \n * numCols, and pData fields    \n * of the matrix data structure.    \n */\n\n/**    \n * @addtogroup MatrixInit    \n * @{    \n */\n\n/**    \n   * @brief  Floating-point matrix initialization.    \n   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    \n   * @param[in]     nRows          number of rows in the matrix.    \n   * @param[in]     nColumns       number of columns in the matrix.    \n   * @param[in]     *pData\t   points to the matrix data array.    \n   * @return        none    \n   */\n\nvoid arm_mat_init_f32(\n  arm_matrix_instance_f32 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  float32_t * pData)\n{\n  /* Assign Number of Rows */\n  S->numRows = nRows;\n\n  /* Assign Number of Columns */\n  S->numCols = nColumns;\n\n  /* Assign Data pointer */\n  S->pData = pData;\n}\n\n/**    \n * @} end of MatrixInit group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_mat_init_q15.c    \n*    \n* Description:\tQ15 matrix initialization.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixInit    \n * @{    \n */\n\n  /**    \n   * @brief  Q15 matrix initialization.    \n   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    \n   * @param[in]     nRows          number of rows in the matrix.    \n   * @param[in]     nColumns       number of columns in the matrix.    \n   * @param[in]     *pData\t   points to the matrix data array.    \n   * @return        none    \n   */\n\nvoid arm_mat_init_q15(\n  arm_matrix_instance_q15 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q15_t * pData)\n{\n  /* Assign Number of Rows */\n  S->numRows = nRows;\n\n  /* Assign Number of Columns */\n  S->numCols = nColumns;\n\n  /* Assign Data pointer */\n  S->pData = pData;\n}\n\n/**    \n * @} end of MatrixInit group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_mat_init_q31.c    \n*    \n* Description:\tQ31 matrix initialization.    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @defgroup MatrixInit Matrix Initialization    \n *    \n */\n\n/**    \n * @addtogroup MatrixInit    \n * @{    \n */\n\n  /**    \n   * @brief  Q31 matrix initialization.    \n   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    \n   * @param[in]     nRows          number of rows in the matrix.    \n   * @param[in]     nColumns       number of columns in the matrix.    \n   * @param[in]     *pData\t   points to the matrix data array.    \n   * @return        none    \n   */\n\nvoid arm_mat_init_q31(\n  arm_matrix_instance_q31 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q31_t * pData)\n{\n  /* Assign Number of Rows */\n  S->numRows = nRows;\n\n  /* Assign Number of Columns */\n  S->numCols = nColumns;\n\n  /* Assign Data pointer */\n  S->pData = pData;\n}\n\n/**    \n * @} end of MatrixInit group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        1. March 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_inverse_f32.c    \n*    \n* Description:\tFloating-point matrix inverse.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @defgroup MatrixInv Matrix Inverse    \n *    \n * Computes the inverse of a matrix.    \n *    \n * The inverse is defined only if the input matrix is square and non-singular (the determinant    \n * is non-zero). The function checks that the input and output matrices are square and of the    \n * same size.    \n *    \n * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    \n * inversion of floating-point matrices.    \n *    \n * \\par Algorithm    \n * The Gauss-Jordan method is used to find the inverse.    \n * The algorithm performs a sequence of elementary row-operations till it    \n * reduces the input matrix to an identity matrix. Applying the same sequence    \n * of elementary row-operations to an identity matrix yields the inverse matrix.    \n * If the input matrix is singular, then the algorithm terminates and returns error status    \n * ARM_MATH_SINGULAR.    \n * \\image html MatrixInverse.gif \"Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method\"    \n */\n\n/**    \n * @addtogroup MatrixInv    \n * @{    \n */\n\n/**    \n * @brief Floating-point matrix inverse.    \n * @param[in]       *pSrc points to input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns    \n * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size    \n * of the output matrix does not match the size of the input matrix.    \n * If the input matrix is found to be singular (non-invertible), then the function returns    \n * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.    \n */\n\narm_status arm_mat_inverse_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */\n  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */\n  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */\n  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */\n  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */\n  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */\n\n#ifndef ARM_MATH_CM0_FAMILY\n  float32_t maxC;                                /* maximum value in the column */\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */\n  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */\n  arm_status status;                             /* status of matrix inverse */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)\n     || (pSrc->numRows != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n\n    /*--------------------------------------------------------------------------------------------------------------    \n\t * Matrix Inverse can be solved using elementary row operations.    \n\t *    \n\t *\tGauss-Jordan Method:    \n\t *    \n\t *\t   1. First combine the identity matrix and the input matrix separated by a bar to form an    \n\t *        augmented matrix as follows:    \n\t *\t\t\t\t        _ \t      \t       _         _\t       _    \n\t *\t\t\t\t\t   |  a11  a12 | 1   0  |       |  X11 X12  |    \n\t *\t\t\t\t\t   |           |        |   =   |           |    \n\t *\t\t\t\t\t   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    \n\t *    \n\t *\t\t2. In our implementation, pDst Matrix is used as identity matrix.    \n\t *    \n\t *\t\t3. Begin with the first row. Let i = 1.    \n\t *    \n\t *\t    4. Check to see if the pivot for column i is the greatest of the column.    \n\t *\t\t   The pivot is the element of the main diagonal that is on the current row.    \n\t *\t\t   For instance, if working with row i, then the pivot element is aii.    \n\t *\t\t   If the pivot is not the most significant of the coluimns, exchange that row with a row\n\t *\t\t   below it that does contain the most significant value in column i. If the most\n\t *         significant value of the column is zero, then an inverse to that matrix does not exist.\n\t *\t\t   The most significant value of the column is the absolut maximum.\n\t *    \n\t *\t    5. Divide every element of row i by the pivot.    \n\t *    \n\t *\t    6. For every row below and  row i, replace that row with the sum of that row and    \n\t *\t\t   a multiple of row i so that each new element in column i below row i is zero.    \n\t *    \n\t *\t    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    \n\t *\t\t   for every element below and above the main diagonal.    \n\t *    \n\t *\t\t8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    \n\t *\t\t   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    \n\t *----------------------------------------------------------------------------------------------------------------*/\n\n    /* Working pointer for destination matrix */\n    pInT2 = pOut;\n\n    /* Loop over the number of rows */\n    rowCnt = numRows;\n\n    /* Making the destination matrix as identity matrix */\n    while(rowCnt > 0u)\n    {\n      /* Writing all zeroes in lower triangle of the destination matrix */\n      j = numRows - rowCnt;\n      while(j > 0u)\n      {\n        *pInT2++ = 0.0f;\n        j--;\n      }\n\n      /* Writing all ones in the diagonal of the destination matrix */\n      *pInT2++ = 1.0f;\n\n      /* Writing all zeroes in upper triangle of the destination matrix */\n      j = rowCnt - 1u;\n      while(j > 0u)\n      {\n        *pInT2++ = 0.0f;\n        j--;\n      }\n\n      /* Decrement the loop counter */\n      rowCnt--;\n    }\n\n    /* Loop over the number of columns of the input matrix.    \n       All the elements in each column are processed by the row operations */\n    loopCnt = numCols;\n\n    /* Index modifier to navigate through the columns */\n    l = 0u;\n\n    while(loopCnt > 0u)\n    {\n      /* Check if the pivot element is zero..    \n       * If it is zero then interchange the row with non zero row below.    \n       * If there is no non zero element to replace in the rows below,    \n       * then the matrix is Singular. */\n\n      /* Working pointer for the input matrix that points    \n       * to the pivot element of the particular row  */\n      pInT1 = pIn + (l * numCols);\n\n      /* Working pointer for the destination matrix that points    \n       * to the pivot element of the particular row  */\n      pInT3 = pOut + (l * numCols);\n\n      /* Temporary variable to hold the pivot value */\n      in = *pInT1;\n\n      /* Destination pointer modifier */\n      k = 1u;\n\n     /* Grab the most significant value from column l */\n      maxC = 0;\n      for (i = 0; i < numRows; i++)\n      {\n        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);\n        pInT1 += numCols;\n      }\n\n      /* Update the status if the matrix is singular */\n      if(maxC == 0.0f)\n      {\n        status = ARM_MATH_SINGULAR;\n        break;\n      }\n\n      /* Restore pInT1  */\n      pInT1 -= numRows * numCols;\n      \n      /* Check if the pivot element is the most significant of the column */\n      if( (in > 0.0f ? in : -in) != maxC)\n      {\n        /* Loop over the number rows present below */\n        i = numRows - (l + 1u);\n\n        while(i > 0u)\n        {\n          /* Update the input and destination pointers */\n          pInT2 = pInT1 + (numCols * l);\n          pInT4 = pInT3 + (numCols * k);\n\n          /* Look for the most significant element to    \n           * replace in the rows below */\n          if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)\n          {\n            /* Loop over number of columns    \n             * to the right of the pilot element */\n            j = numCols - l;\n\n            while(j > 0u)\n            {\n              /* Exchange the row elements of the input matrix */\n              Xchg = *pInT2;\n              *pInT2++ = *pInT1;\n              *pInT1++ = Xchg;\n\n              /* Decrement the loop counter */\n              j--;\n            }\n\n            /* Loop over number of columns of the destination matrix */\n            j = numCols;\n\n            while(j > 0u)\n            {\n              /* Exchange the row elements of the destination matrix */\n              Xchg = *pInT4;\n              *pInT4++ = *pInT3;\n              *pInT3++ = Xchg;\n\n              /* Decrement the loop counter */\n              j--;\n            }\n\n            /* Flag to indicate whether exchange is done or not */\n            flag = 1u;\n\n            /* Break after exchange is done */\n            break;\n          }\n\n          /* Update the destination pointer modifier */\n          k++;\n\n          /* Decrement the loop counter */\n          i--;\n        }\n      }\n\n      /* Update the status if the matrix is singular */\n      if((flag != 1u) && (in == 0.0f))\n      {\n        status = ARM_MATH_SINGULAR;\n\n        break;\n      }\n\n      /* Points to the pivot row of input and destination matrices */\n      pPivotRowIn = pIn + (l * numCols);\n      pPivotRowDst = pOut + (l * numCols);\n\n      /* Temporary pointers to the pivot row pointers */\n      pInT1 = pPivotRowIn;\n      pInT2 = pPivotRowDst;\n\n      /* Pivot element of the row */\n      in = *pPivotRowIn;\n\n      /* Loop over number of columns    \n       * to the right of the pilot element */\n      j = (numCols - l);\n\n      while(j > 0u)\n      {\n        /* Divide each element of the row of the input matrix    \n         * by the pivot element */\n        in1 = *pInT1;\n        *pInT1++ = in1 / in;\n\n        /* Decrement the loop counter */\n        j--;\n      }\n\n      /* Loop over number of columns of the destination matrix */\n      j = numCols;\n\n      while(j > 0u)\n      {\n        /* Divide each element of the row of the destination matrix    \n         * by the pivot element */\n        in1 = *pInT2;\n        *pInT2++ = in1 / in;\n\n        /* Decrement the loop counter */\n        j--;\n      }\n\n      /* Replace the rows with the sum of that row and a multiple of row i    \n       * so that each new element in column i above row i is zero.*/\n\n      /* Temporary pointers for input and destination matrices */\n      pInT1 = pIn;\n      pInT2 = pOut;\n\n      /* index used to check for pivot element */\n      i = 0u;\n\n      /* Loop over number of rows */\n      /*  to be replaced by the sum of that row and a multiple of row i */\n      k = numRows;\n\n      while(k > 0u)\n      {\n        /* Check for the pivot element */\n        if(i == l)\n        {\n          /* If the processing element is the pivot element,    \n             only the columns to the right are to be processed */\n          pInT1 += numCols - l;\n\n          pInT2 += numCols;\n        }\n        else\n        {\n          /* Element of the reference row */\n          in = *pInT1;\n\n          /* Working pointers for input and destination pivot rows */\n          pPRT_in = pPivotRowIn;\n          pPRT_pDst = pPivotRowDst;\n\n          /* Loop over the number of columns to the right of the pivot element,    \n             to replace the elements in the input matrix */\n          j = (numCols - l);\n\n          while(j > 0u)\n          {\n            /* Replace the element by the sum of that row    \n               and a multiple of the reference row  */\n            in1 = *pInT1;\n            *pInT1++ = in1 - (in * *pPRT_in++);\n\n            /* Decrement the loop counter */\n            j--;\n          }\n\n          /* Loop over the number of columns to    \n             replace the elements in the destination matrix */\n          j = numCols;\n\n          while(j > 0u)\n          {\n            /* Replace the element by the sum of that row    \n               and a multiple of the reference row  */\n            in1 = *pInT2;\n            *pInT2++ = in1 - (in * *pPRT_pDst++);\n\n            /* Decrement the loop counter */\n            j--;\n          }\n\n        }\n\n        /* Increment the temporary input pointer */\n        pInT1 = pInT1 + l;\n\n        /* Decrement the loop counter */\n        k--;\n\n        /* Increment the pivot index */\n        i++;\n      }\n\n      /* Increment the input pointer */\n      pIn++;\n\n      /* Decrement the loop counter */\n      loopCnt--;\n\n      /* Increment the index modifier */\n      l++;\n    }\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */\n  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */\n  arm_status status;                             /* status of matrix inverse */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)\n     || (pSrc->numRows != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n  {\n\n    /*--------------------------------------------------------------------------------------------------------------       \n\t * Matrix Inverse can be solved using elementary row operations.        \n\t *        \n\t *\tGauss-Jordan Method:       \n\t *\t \t       \n\t *\t   1. First combine the identity matrix and the input matrix separated by a bar to form an        \n\t *        augmented matrix as follows:        \n\t *\t\t\t\t        _  _\t      _\t    _\t   _   _         _\t       _       \n\t *\t\t\t\t\t   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         \n\t *\t\t\t\t\t   |  |            | | |        |   |   =   |           |        \n\t *\t\t\t\t\t   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       \n\t *\t\t\t\t\t          \n\t *\t\t2. In our implementation, pDst Matrix is used as identity matrix.    \n\t *       \n\t *\t\t3. Begin with the first row. Let i = 1.       \n\t *       \n\t *\t    4. Check to see if the pivot for row i is zero.       \n\t *\t\t   The pivot is the element of the main diagonal that is on the current row.       \n\t *\t\t   For instance, if working with row i, then the pivot element is aii.       \n\t *\t\t   If the pivot is zero, exchange that row with a row below it that does not        \n\t *\t\t   contain a zero in column i. If this is not possible, then an inverse        \n\t *\t\t   to that matrix does not exist.       \n\t *\t       \n\t *\t    5. Divide every element of row i by the pivot.       \n\t *\t       \n\t *\t    6. For every row below and  row i, replace that row with the sum of that row and        \n\t *\t\t   a multiple of row i so that each new element in column i below row i is zero.       \n\t *\t       \n\t *\t    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       \n\t *\t\t   for every element below and above the main diagonal.        \n\t *\t\t   \t\t          \n\t *\t\t8. Now an identical matrix is formed to the left of the bar(input matrix, src).       \n\t *\t\t   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         \n\t *----------------------------------------------------------------------------------------------------------------*/\n\n    /* Working pointer for destination matrix */\n    pInT2 = pOut;\n\n    /* Loop over the number of rows */\n    rowCnt = numRows;\n\n    /* Making the destination matrix as identity matrix */\n    while(rowCnt > 0u)\n    {\n      /* Writing all zeroes in lower triangle of the destination matrix */\n      j = numRows - rowCnt;\n      while(j > 0u)\n      {\n        *pInT2++ = 0.0f;\n        j--;\n      }\n\n      /* Writing all ones in the diagonal of the destination matrix */\n      *pInT2++ = 1.0f;\n\n      /* Writing all zeroes in upper triangle of the destination matrix */\n      j = rowCnt - 1u;\n      while(j > 0u)\n      {\n        *pInT2++ = 0.0f;\n        j--;\n      }\n\n      /* Decrement the loop counter */\n      rowCnt--;\n    }\n\n    /* Loop over the number of columns of the input matrix.     \n       All the elements in each column are processed by the row operations */\n    loopCnt = numCols;\n\n    /* Index modifier to navigate through the columns */\n    l = 0u;\n    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   \n    while(loopCnt > 0u)\n    {\n      /* Check if the pivot element is zero..    \n       * If it is zero then interchange the row with non zero row below.   \n       * If there is no non zero element to replace in the rows below,   \n       * then the matrix is Singular. */\n\n      /* Working pointer for the input matrix that points     \n       * to the pivot element of the particular row  */\n      pInT1 = pIn + (l * numCols);\n\n      /* Working pointer for the destination matrix that points     \n       * to the pivot element of the particular row  */\n      pInT3 = pOut + (l * numCols);\n\n      /* Temporary variable to hold the pivot value */\n      in = *pInT1;\n\n      /* Destination pointer modifier */\n      k = 1u;\n\n      /* Check if the pivot element is zero */\n      if(*pInT1 == 0.0f)\n      {\n        /* Loop over the number rows present below */\n        for (i = (l + 1u); i < numRows; i++)\n        {\n          /* Update the input and destination pointers */\n          pInT2 = pInT1 + (numCols * l);\n          pInT4 = pInT3 + (numCols * k);\n\n          /* Check if there is a non zero pivot element to     \n           * replace in the rows below */\n          if(*pInT2 != 0.0f)\n          {\n            /* Loop over number of columns     \n             * to the right of the pilot element */\n            for (j = 0u; j < (numCols - l); j++)\n            {\n              /* Exchange the row elements of the input matrix */\n              Xchg = *pInT2;\n              *pInT2++ = *pInT1;\n              *pInT1++ = Xchg;\n            }\n\n            for (j = 0u; j < numCols; j++)\n            {\n              Xchg = *pInT4;\n              *pInT4++ = *pInT3;\n              *pInT3++ = Xchg;\n            }\n\n            /* Flag to indicate whether exchange is done or not */\n            flag = 1u;\n\n            /* Break after exchange is done */\n            break;\n          }\n\n          /* Update the destination pointer modifier */\n          k++;\n        }\n      }\n\n      /* Update the status if the matrix is singular */\n      if((flag != 1u) && (in == 0.0f))\n      {\n        status = ARM_MATH_SINGULAR;\n\n        break;\n      }\n\n      /* Points to the pivot row of input and destination matrices */\n      pPivotRowIn = pIn + (l * numCols);\n      pPivotRowDst = pOut + (l * numCols);\n\n      /* Temporary pointers to the pivot row pointers */\n      pInT1 = pPivotRowIn;\n      pInT2 = pPivotRowDst;\n\n      /* Pivot element of the row */\n      in = *(pIn + (l * numCols));\n\n      /* Loop over number of columns     \n       * to the right of the pilot element */\n      for (j = 0u; j < (numCols - l); j++)\n      {\n        /* Divide each element of the row of the input matrix     \n         * by the pivot element */\n        *pInT1 = *pInT1 / in;\n        pInT1++;\n      }\n      for (j = 0u; j < numCols; j++)\n      {\n        /* Divide each element of the row of the destination matrix     \n         * by the pivot element */\n        *pInT2 = *pInT2 / in;\n        pInT2++;\n      }\n\n      /* Replace the rows with the sum of that row and a multiple of row i     \n       * so that each new element in column i above row i is zero.*/\n\n      /* Temporary pointers for input and destination matrices */\n      pInT1 = pIn;\n      pInT2 = pOut;\n\n      for (i = 0u; i < numRows; i++)\n      {\n        /* Check for the pivot element */\n        if(i == l)\n        {\n          /* If the processing element is the pivot element,     \n             only the columns to the right are to be processed */\n          pInT1 += numCols - l;\n          pInT2 += numCols;\n        }\n        else\n        {\n          /* Element of the reference row */\n          in = *pInT1;\n\n          /* Working pointers for input and destination pivot rows */\n          pPRT_in = pPivotRowIn;\n          pPRT_pDst = pPivotRowDst;\n\n          /* Loop over the number of columns to the right of the pivot element,     \n             to replace the elements in the input matrix */\n          for (j = 0u; j < (numCols - l); j++)\n          {\n            /* Replace the element by the sum of that row     \n               and a multiple of the reference row  */\n            *pInT1 = *pInT1 - (in * *pPRT_in++);\n            pInT1++;\n          }\n          /* Loop over the number of columns to     \n             replace the elements in the destination matrix */\n          for (j = 0u; j < numCols; j++)\n          {\n            /* Replace the element by the sum of that row     \n               and a multiple of the reference row  */\n            *pInT2 = *pInT2 - (in * *pPRT_pDst++);\n            pInT2++;\n          }\n\n        }\n        /* Increment the temporary input pointer */\n        pInT1 = pInT1 + l;\n      }\n      /* Increment the input pointer */\n      pIn++;\n\n      /* Decrement the loop counter */\n      loopCnt--;\n      /* Increment the index modifier */\n      l++;\n    }\n\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n\n    if((flag != 1u) && (in == 0.0f))\n    {\n      status = ARM_MATH_SINGULAR;\n    }\n  }\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixInv group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_mult_f32.c    \n*    \n* Description:  Floating-point matrix multiplication.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @defgroup MatrixMult Matrix Multiplication    \n *    \n * Multiplies two matrices.    \n *    \n * \\image html MatrixMultiplication.gif \"Multiplication of two 3 x 3 matrices\"    \n    \n * Matrix multiplication is only defined if the number of columns of the    \n * first matrix equals the number of rows of the second matrix.    \n * Multiplying an M x N matrix with an N x P matrix results    \n * in an M x P matrix.    \n * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of    \n * pSrcA and pSrcB are equal; and (2) that the size of the output    \n * matrix equals the outer dimensions of pSrcA and pSrcB.    \n */\n\n\n/**    \n * @addtogroup MatrixMult    \n * @{    \n */\n\n/**    \n * @brief Floating-point matrix multiplication.    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n */\n\narm_status arm_mat_mult_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */\n  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */\n  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */\n  float32_t *px;                                 /* Temporary output data matrix pointer */\n  float32_t sum;                                 /* Accumulator */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t in1, in2, in3, in4;\n  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set    \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      j = 0u;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0.0f;\n\n        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */\n        pIn1 = pInA;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        colCnt = numColsA >> 2u;\n\n        /* matrix multiplication        */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          in3 = *pIn2;\n          pIn2 += numColsB;\n          in1 = pIn1[0];\n          in2 = pIn1[1];\n          sum += in1 * in3;\n          in4 = *pIn2;\n          pIn2 += numColsB;\n          sum += in2 * in4;\n\n          in3 = *pIn2;\n          pIn2 += numColsB;\n          in1 = pIn1[2];\n          in2 = pIn1[3];\n          sum += in1 * in3;\n          in4 = *pIn2;\n          pIn2 += numColsB;\n          sum += in2 * in4;\n          pIn1 += 4u;\n\n          /* Decrement the loop count */\n          colCnt--;\n        }\n\n        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.    \n         ** No loop unrolling is used. */\n        colCnt = numColsA % 0x4u;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          sum += *pIn1++ * (*pIn2);\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Store the result in the destination buffer */\n        *px++ = sum;\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        j++;\n        pIn2 = pSrcB->pData + j;\n\n        /* Decrement the column loop counter */\n        col--;\n\n      } while(col > 0u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */\n  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pInA with each column in pInB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set     \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0.0f;\n\n        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */\n        pIn1 = pInA;\n\n        /* Matrix A columns number of MAC operations are to be performed */\n        colCnt = numColsA;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          sum += *pIn1++ * (*pIn2);\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Store the result in the destination buffer */\n        *px++ = sum;\n\n        /* Decrement the column loop counter */\n        col--;\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        pIn2 = pInB + (numColsB - col);\n\n      } while(col > 0u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n      /* Update the pointer pInA to point to the  starting address of the next row */\n      i = i + numColsB;\n      pInA = pInA + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_mult_fast_q15.c    \n*    \n* Description:\t Q15 matrix multiplication (fast variant)    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixMult    \n * @{    \n */\n\n\n/**    \n * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @param[in]\t\t*pState points to the array for storing intermediate results    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The difference between the function arm_mat_mult_q15() and this fast variant is that    \n * the fast variant use a 32-bit rather than a 64-bit accumulator.    \n * The result of each 1.15 x 1.15 multiplication is truncated to        \n * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30        \n * format. Finally, the accumulator is saturated and converted to a 1.15 result.        \n *        \n * \\par        \n * The fast version has the same overflow behavior as the standard version but provides        \n * less precision since it discards the low 16 bits of each multiplication result.        \n * In order to avoid overflows completely the input signals must be scaled down.        \n * Scale down one of the input matrices by log2(numColsA) bits to        \n * avoid overflows, as a total of numColsA additions are computed internally for each        \n * output element.        \n *        \n * \\par    \n * See arm_mat_mult_q15() for a slower implementation of this function    \n * which uses 64-bit accumulation to provide higher precision.    \n */\n\narm_status arm_mat_mult_fast_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState)\n{\n  q31_t sum;                                     /* accumulator */\n  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */\n  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */\n  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */\n  q15_t *px;                                     /* Temporary output data matrix pointer */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */\n  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  q31_t in;                                      /* Temporary variable to hold the input value */\n  q31_t inA1, inA2, inB1, inB2;\n\n#else\n\n  q15_t in;                                      /* Temporary variable to hold the input value */\n  q15_t inA1, inA2, inB1, inB2;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif\n  {\n    /* Matrix transpose */\n    do\n    {\n      /* Apply loop unrolling and exchange the columns with row elements */\n      col = numColsB >> 2;\n\n      /* The pointer px is set to starting address of the column being processed */\n      px = pSrcBT + i;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n       ** a second loop below computes the remaining 1 to 3 samples. */\n      while(col > 0u)\n      {\n#ifndef UNALIGNED_SUPPORT_DISABLE\n        /* Read two elements from the row */\n        in = *__SIMD32(pInB)++;\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) in;\n\n#else\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Unpack and store the second element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *px = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read two elements from the row */\n        in = *__SIMD32(pInB)++;\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) in;\n\n#else\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Unpack and store the second element in the destination */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *px = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n#else\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n        \n\t\t/* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        \n       ** No loop unrolling is used. */\n      col = numColsB % 0x4u;\n\n      while(col > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pInB++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n      i++;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* Reset the variables for the usage in the following multiplication process */\n    row = numRowsA;\n    i = 0u;\n    px = pDst->pData;\n\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set        \n       ** to the starting address of the transposed pSrcB data */\n      pInB = pSrcBT;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 2 MACs simultaneously. */\n        colCnt = numColsA >> 2;\n\n        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */\n        pInA = pSrcA->pData + i;\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n          inA1 = *__SIMD32(pInA)++;\n          inB1 = *__SIMD32(pInB)++;\n          inA2 = *__SIMD32(pInA)++;\n          inB2 = *__SIMD32(pInB)++;\n\n          sum = __SMLAD(inA1, inB1, sum);\n          sum = __SMLAD(inA2, inB2, sum);\n\n#else\n\n          inA1 = *pInA++;\n          inB1 = *pInB++;\n          inA2 = *pInA++;\n          sum += inA1 * inB1;\n          inB2 = *pInB++;\n\n          inA1 = *pInA++;\n          inB1 = *pInB++;\n          sum += inA2 * inB2;\n          inA2 = *pInA++;\n          inB2 = *pInB++;\n\n          sum += inA1 * inB1;\n          sum += inA2 * inB2;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* process odd column samples */\n        colCnt = numColsA % 0x4u;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          sum += (q31_t) (*pInA++) * (*pInB++);\n\n          colCnt--;\n        }\n\n        /* Saturate and store the result in the destination buffer */\n        *px = (q15_t) (sum >> 15);\n        px++;\n\n        /* Decrement the column loop counter */\n        col--;\n\n      } while(col > 0u);\n\n      i = i + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixMult group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_mult_fast_q31.c    \n*    \n* Description:\t Q31 matrix multiplication (fast variant).    \n*    \n* Target Processor: Cortex-M4/Cortex-M3\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixMult    \n * @{    \n */\n\n/**    \n * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The difference between the function arm_mat_mult_q31() and this fast variant is that    \n * the fast variant use a 32-bit rather than a 64-bit accumulator.    \n * The result of each 1.31 x 1.31 multiplication is truncated to    \n * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30    \n * format. Finally, the accumulator is saturated and converted to a 1.31 result.    \n *    \n * \\par    \n * The fast version has the same overflow behavior as the standard version but provides    \n * less precision since it discards the low 32 bits of each multiplication result.    \n * In order to avoid overflows completely the input signals must be scaled down.    \n * Scale down one of the input matrices by log2(numColsA) bits to    \n * avoid overflows, as a total of numColsA additions are computed internally for each    \n * output element.    \n *    \n * \\par    \n * See arm_mat_mult_q31() for a slower implementation of this function    \n * which uses 64-bit accumulation to provide higher precision.    \n */\n\narm_status arm_mat_mult_fast_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */\n  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */\n  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */\n//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */    \n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  q31_t *px;                                     /* Temporary output data matrix pointer */\n  q31_t sum;                                     /* Accumulator */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n  q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set    \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      j = 0u;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Initiate the pointer pIn1 to point to the starting address of pInA */\n        pIn1 = pInA;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        colCnt = numColsA >> 2;\n\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          inB1 = *pIn2;\n          pIn2 += numColsB;\n\n          inA1 = pIn1[0];\n          inA2 = pIn1[1];\n\n          inB2 = *pIn2;\n          pIn2 += numColsB;\n\n          inB3 = *pIn2;\n          pIn2 += numColsB;\n\n          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);\n          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);\n\n          inA3 = pIn1[2];\n          inA4 = pIn1[3];\n\n          inB4 = *pIn2;\n          pIn2 += numColsB;\n\n          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);\n          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);\n\n          pIn1 += 4u;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    \n         ** No loop unrolling is used. */\n        colCnt = numColsA % 0x4u;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          sum = (q31_t) ((((q63_t) sum << 32) +\n                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */\n        *px++ = sum << 1;\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        j++;\n        pIn2 = pSrcB->pData + j;\n\n        /* Decrement the column loop counter */\n        col--;\n\n      } while(col > 0u);\n\n      /* Update the pointer pInA to point to the  starting address of the next row */\n      i = i + numColsB;\n      pInA = pInA + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_mult_q15.c    \n*    \n* Description:\t Q15 matrix multiplication.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixMult    \n * @{    \n */\n\n\n/**    \n * @brief Q15 matrix multiplication    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @param[in]\t\t*pState points to the array for storing intermediate results   \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator. The inputs to the    \n * multiplications are in 1.15 format and multiplications yield a 2.30 result.    \n * The 2.30 intermediate    \n * results are accumulated in a 64-bit accumulator in 34.30 format. This approach    \n * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then    \n * truncated to 34.15 format by discarding the low 15 bits and then saturated to    \n * 1.15 format.    \n *    \n * \\par    \n * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.    \n *    \n */\n\narm_status arm_mat_mult_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState CMSIS_UNUSED)\n{\n  q63_t sum;                                     /* accumulator */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */\n  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */\n  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */\n  q15_t *px;                                     /* Temporary output data matrix pointer */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */\n  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  q31_t in;                                      /* Temporary variable to hold the input value */\n  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;\n\n#else\n\n  q15_t in;                                      /* Temporary variable to hold the input value */\n  q15_t inA1, inB1, inA2, inB2;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n  {\n    /* Matrix transpose */\n    do\n    {\n      /* Apply loop unrolling and exchange the columns with row elements */\n      col = numColsB >> 2;\n\n      /* The pointer px is set to starting address of the column being processed */\n      px = pSrcBT + i;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        \n       ** a second loop below computes the remaining 1 to 3 samples. */\n      while(col > 0u)\n      {\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n        /* Read two elements from the row */\n        in = *__SIMD32(pInB)++;\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) in;\n\n#else\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Unpack and store the second element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *px = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read two elements from the row */\n        in = *__SIMD32(pInB)++;\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) in;\n\n#else\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Unpack and store the second element in the destination */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *px = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n#else\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Read one element from the row */\n        in = *pInB++;\n\n        /* Store one element in the destination */\n        *px = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n       /* Decrement the column loop counter */\n        col--;\n      }\n\n      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        \n       ** No loop unrolling is used. */\n      col = numColsB % 0x4u;\n\n      while(col > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pInB++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += numRowsB;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n      i++;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* Reset the variables for the usage in the following multiplication process */\n    row = numRowsA;\n    i = 0u;\n    px = pDst->pData;\n\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set        \n       ** to the starting address of the transposed pSrcB data */\n      pInB = pSrcBT;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Apply loop unrolling and compute 2 MACs simultaneously. */\n        colCnt = numColsA >> 2;\n\n        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */\n        pInA = pSrcA->pData + i;\n\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n          /* read real and imag values from pSrcA and pSrcB buffer */\n          pSourceA1 = *__SIMD32(pInA)++;\n          pSourceB1 = *__SIMD32(pInB)++;\n\n          pSourceA2 = *__SIMD32(pInA)++;\n          pSourceB2 = *__SIMD32(pInB)++;\n\n          /* Multiply and Accumlates */\n          sum = __SMLALD(pSourceA1, pSourceB1, sum);\n          sum = __SMLALD(pSourceA2, pSourceB2, sum);\n\n#else\n          /* read real and imag values from pSrcA and pSrcB buffer */\n          inA1 = *pInA++;\n          inB1 = *pInB++;\n          inA2 = *pInA++;\n          /* Multiply and Accumlates */\n          sum += inA1 * inB1;\n          inB2 = *pInB++;\n\n          inA1 = *pInA++;\n          inB1 = *pInB++;\n          /* Multiply and Accumlates */\n          sum += inA2 * inB2;\n          inA2 = *pInA++;\n          inB2 = *pInB++;\n\n          /* Multiply and Accumlates */\n          sum += inA1 * inB1;\n          sum += inA2 * inB2;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* process remaining column samples */\n        colCnt = numColsA & 3u;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          sum += *pInA++ * *pInB++;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Saturate and store the result in the destination buffer */\n        *px = (q15_t) (__SSAT((sum >> 15), 16));\n        px++;\n\n        /* Decrement the column loop counter */\n        col--;\n\n      } while(col > 0u);\n\n      i = i + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */\n  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */\n  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */\n  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */\n  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  q15_t *px;                                     /* Temporary output data matrix pointer */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */\n  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set          \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */\n        pIn1 = pInA;\n\n        /* Matrix A columns number of MAC operations are to be performed */\n        colCnt = numColsA;\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          sum += (q31_t) * pIn1++ * *pIn2;\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */\n        /* Saturate and store the result in the destination buffer */\n        *px++ = (q15_t) __SSAT((sum >> 15), 16);\n\n        /* Decrement the column loop counter */\n        col--;\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        pIn2 = pInB + (numColsB - col);\n\n      } while(col > 0u);\n\n      /* Update the pointer pSrcA to point to the  starting address of the next row */\n      i = i + numColsB;\n      pInA = pInA + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixMult group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_mult_q31.c    \n*    \n* Description:\t Q31 matrix multiplication.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixMult    \n * @{    \n */\n\n/**    \n * @brief Q31 matrix multiplication    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The accumulator has a 2.62 format and maintains full precision of the intermediate    \n * multiplication results but provides only a single guard bit. There is no saturation    \n * on intermediate additions. Thus, if the accumulator overflows it wraps around and    \n * distorts the result. The input signals should be scaled down to avoid intermediate    \n * overflows. The input is thus scaled down by log2(numColsA) bits    \n * to avoid overflows, as a total of numColsA additions are performed internally.    \n * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    \n *    \n * \\par    \n * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    \n *    \n */\n\narm_status arm_mat_mult_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */\n  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */\n  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */\n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  q31_t *px;                                     /* Temporary output data matrix pointer */\n  q63_t sum;                                     /* Accumulator */\n  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */\n  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */\n  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n  q31_t a0, a1, a2, a3, b0, b1, b2, b3;\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set    \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      j = 0u;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Initiate the pointer pIn1 to point to the starting address of pInA */\n        pIn1 = pInA;\n\n        /* Apply loop unrolling and compute 4 MACs simultaneously. */\n        colCnt = numColsA >> 2;\n\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          b0 = *pIn2;\n          pIn2 += numColsB;\n\n          a0 = *pIn1++;\n          a1 = *pIn1++;\n\n          b1 = *pIn2;\n          pIn2 += numColsB;\n          b2 = *pIn2;\n          pIn2 += numColsB;\n\n          sum += (q63_t) a0 *b0;\n          sum += (q63_t) a1 *b1;\n\n          a2 = *pIn1++;\n          a3 = *pIn1++;\n\n          b3 = *pIn2;\n          pIn2 += numColsB;\n\n          sum += (q63_t) a2 *b2;\n          sum += (q63_t) a3 *b3;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    \n         ** No loop unrolling is used. */\n        colCnt = numColsA % 0x4u;\n\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          sum += (q63_t) * pIn1++ * *pIn2;\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */\n        *px++ = (q31_t) (sum >> 31);\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        j++;\n        pIn2 = (pSrcB->pData) + j;\n\n        /* Decrement the column loop counter */\n        col--;\n\n      } while(col > 0u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */\n  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */\n  arm_status status;                             /* status of matrix multiplication */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numCols != pSrcB->numRows) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */\n    /* row loop */\n    do\n    {\n      /* Output pointer is set to starting address of the row being processed */\n      px = pOut + i;\n\n      /* For every row wise process, the column loop counter is to be initiated */\n      col = numColsB;\n\n      /* For every row wise process, the pIn2 pointer is set          \n       ** to the starting address of the pSrcB data */\n      pIn2 = pSrcB->pData;\n\n      /* column loop */\n      do\n      {\n        /* Set the variable sum, that acts as accumulator, to zero */\n        sum = 0;\n\n        /* Initiate the pointer pIn1 to point to the starting address of pInA */\n        pIn1 = pInA;\n\n        /* Matrix A columns number of MAC operations are to be performed */\n        colCnt = numColsA;\n\n        /* matrix multiplication */\n        while(colCnt > 0u)\n        {\n          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */\n          /* Perform the multiply-accumulates */\n          sum += (q63_t) * pIn1++ * *pIn2;\n          pIn2 += numColsB;\n\n          /* Decrement the loop counter */\n          colCnt--;\n        }\n\n        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */\n        *px++ = (q31_t) (sum >> 31);\n\n        /* Decrement the column loop counter */\n        col--;\n\n        /* Update the pointer pIn2 to point to the  starting address of the next column */\n        pIn2 = pInB + (numColsB - col);\n\n      } while(col > 0u);\n\n#endif\n\n      /* Update the pointer pInA to point to the  starting address of the next row */\n      i = i + numColsB;\n      pInA = pInA + numColsA;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixMult group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:        arm_mat_scale_f32.c    \n*    \n* Description:\tMultiplies a floating-point matrix by a scalar.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupMatrix        \n */\n\n/**        \n * @defgroup MatrixScale Matrix Scale        \n *        \n * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the        \n * matrix by the scalar.  For example:        \n * \\image html MatrixScale.gif \"Matrix Scaling of a 3 x 3 matrix\"        \n *        \n * The function checks to make sure that the input and output matrices are of the same size.        \n *        \n * In the fixed-point Q15 and Q31 functions, scale is represented by        \n * a fractional multiplication scaleFract and an arithmetic shift shift.        \n * The shift allows the gain of the scaling operation to exceed 1.0.        \n * The overall scale factor applied to the fixed-point data is        \n * 
        \n *     scale = scaleFract * 2^shift.        \n * 
        \n */\n\n/**        \n * @addtogroup MatrixScale        \n * @{        \n */\n\n/**        \n * @brief Floating-point matrix scaling.        \n * @param[in]       *pSrc points to input matrix structure        \n * @param[in]       scale scale factor to be applied         \n * @param[out]      *pDst points to output matrix structure        \n * @return     \t\tThe function returns either ARM_MATH_SIZE_MISMATCH         \n * or ARM_MATH_SUCCESS based on the outcome of size checking.        \n *        \n */\n\narm_status arm_mat_scale_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  float32_t scale,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */\n  uint32_t numSamples;                           /* total number of elements in the matrix */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix scaling     */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  float32_t in1, in2, in3, in4;                  /* temporary variables */\n  float32_t out1, out2, out3, out4;              /* temporary variables */\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * scale */\n      /* Scaling and results are stored in the destination buffer. */\n      in1 = pIn[0];\n      in2 = pIn[1];\n      in3 = pIn[2];\n      in4 = pIn[3];\n\n      out1 = in1 * scale;\n      out2 = in2 * scale;\n      out3 = in3 * scale;\n      out4 = in4 * scale;\n\n\n      pOut[0] = out1;\n      pOut[1] = out2;\n      pOut[2] = out3;\n      pOut[3] = out4;\n\n      /* update pointers to process next sampels */\n      pIn += 4u;\n      pOut += 4u;\n\n      /* Decrement the numSamples loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * scale */\n      /* The results are stored in the destination buffer. */\n      *pOut++ = (*pIn++) * scale;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixScale group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_scale_q15.c    \n*    \n* Description:\tMultiplies a Q15 matrix by a scalar.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixScale    \n * @{    \n */\n\n/**    \n * @brief Q15 matrix scaling.    \n * @param[in]       *pSrc points to input matrix    \n * @param[in]       scaleFract fractional portion of the scale factor    \n * @param[in]       shift number of bits to shift the result by    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The input data *pSrc and scaleFract are in 1.15 format.    \n * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    \n */\n\narm_status arm_mat_scale_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  q15_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q15 * pDst)\n{\n  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */\n  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  uint32_t numSamples;                           /* total number of elements in the matrix */\n  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix scaling     */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q15_t in1, in2, in3, in4;\n  q31_t out1, out2, out3, out4;\n  q31_t inA1, inA2;\n\n#endif //     #ifndef ARM_MATH_CM0_FAMILY\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch */\n  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif //    #ifdef ARM_MATH_MATRIX_CHECK\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * k */\n      /* Scale, saturate and then store the results in the destination buffer. */\n      /* Reading 2 inputs from memory */\n      inA1 = _SIMD32_OFFSET(pIn);\n      inA2 = _SIMD32_OFFSET(pIn + 2);\n\n      /* C = A * scale */\n      /* Scale the inputs and then store the 2 results in the destination buffer        \n       * in single cycle by packing the outputs */\n      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);\n      out2 = (q31_t) ((q15_t) inA1 * scaleFract);\n      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);\n      out4 = (q31_t) ((q15_t) inA2 * scaleFract);\n\n      out1 = out1 >> totShift;\n      inA1 = _SIMD32_OFFSET(pIn + 4);\n      out2 = out2 >> totShift;\n      inA2 = _SIMD32_OFFSET(pIn + 6);\n      out3 = out3 >> totShift;\n      out4 = out4 >> totShift;\n\n      in1 = (q15_t) (__SSAT(out1, 16));\n      in2 = (q15_t) (__SSAT(out2, 16));\n      in3 = (q15_t) (__SSAT(out3, 16));\n      in4 = (q15_t) (__SSAT(out4, 16));\n\n      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);\n      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);\n\n      /* update pointers to process next sampels */\n      pIn += 4u;\n      pOut += 4u;\n\n\n      /* Decrement the numSamples loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * k */\n      /* Scale, saturate and then store the results in the destination buffer. */\n      *pOut++ =\n        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));\n\n      /* Decrement the numSamples loop counter */\n      blkCnt--;\n    }\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixScale group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_scale_q31.c    \n*    \n* Description:\tMultiplies a Q31 matrix by a scalar.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  ------------------------------------------------ */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupMatrix        \n */\n\n/**        \n * @addtogroup MatrixScale        \n * @{        \n */\n\n/**        \n * @brief Q31 matrix scaling.        \n * @param[in]       *pSrc points to input matrix        \n * @param[in]       scaleFract fractional portion of the scale factor        \n * @param[in]       shift number of bits to shift the result by        \n * @param[out]      *pDst points to output matrix structure        \n * @return     \t\tThe function returns either        \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        \n *        \n * @details        \n * Scaling and Overflow Behavior:        \n * \\par        \n * The input data *pSrc and scaleFract are in 1.31 format.        \n * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.        \n */\n\narm_status arm_mat_scale_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  q31_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */\n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  uint32_t numSamples;                           /* total number of elements in the matrix */\n  int32_t totShift = shift + 1;                  /* shift to apply after scaling */\n  uint32_t blkCnt;                               /* loop counters  */\n  arm_status status;                             /* status of matrix scaling      */\n  q31_t in1, in2, out1;                          /* temporary variabels */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q31_t in3, in4, out2, out3, out4;              /* temporary variables */\n\n#endif //      #ifndef ARM_MAT_CM0\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch  */\n  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif //    #ifdef ARM_MATH_MATRIX_CHECK\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * k */\n      /* Read values from input */\n      in1 = *pIn;\n      in2 = *(pIn + 1);\n      in3 = *(pIn + 2);\n      in4 = *(pIn + 3);\n\n      /* multiply input with scaler value */\n      in1 = ((q63_t) in1 * scaleFract) >> 32;\n      in2 = ((q63_t) in2 * scaleFract) >> 32;\n      in3 = ((q63_t) in3 * scaleFract) >> 32;\n      in4 = ((q63_t) in4 * scaleFract) >> 32;\n\n      /* apply shifting */\n      out1 = in1 << totShift;\n      out2 = in2 << totShift;\n\n      /* saturate the results. */\n      if(in1 != (out1 >> totShift))\n        out1 = 0x7FFFFFFF ^ (in1 >> 31);\n\n      if(in2 != (out2 >> totShift))\n        out2 = 0x7FFFFFFF ^ (in2 >> 31);\n\n      out3 = in3 << totShift;\n      out4 = in4 << totShift;\n\n      *pOut = out1;\n      *(pOut + 1) = out2;\n\n      if(in3 != (out3 >> totShift))\n        out3 = 0x7FFFFFFF ^ (in3 >> 31);\n\n      if(in4 != (out4 >> totShift))\n        out4 = 0x7FFFFFFF ^ (in4 >> 31);\n\n\n      *(pOut + 2) = out3;\n      *(pOut + 3) = out4;\n\n      /* update pointers to process next sampels */\n      pIn += 4u;\n      pOut += 4u;\n\n\n      /* Decrement the numSamples loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) * k */\n      /* Scale, saturate and then store the results in the destination buffer. */\n      in1 = *pIn++;\n\n      in2 = ((q63_t) in1 * scaleFract) >> 32;\n\n      out1 = in2 << totShift;\n\n      if(in2 != (out1 >> totShift))\n        out1 = 0x7FFFFFFF ^ (in2 >> 31);\n\n      *pOut++ = out1;\n\n      /* Decrement the numSamples loop counter */\n      blkCnt--;\n    }\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixScale group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_sub_f32.c    \n*    \n* Description:\tFloating-point matrix subtraction.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupMatrix        \n */\n\n/**        \n * @defgroup MatrixSub Matrix Subtraction        \n *        \n * Subtract two matrices.        \n * \\image html MatrixSubtraction.gif \"Subraction of two 3 x 3 matrices\"        \n *        \n * The functions check to make sure that        \n * pSrcA, pSrcB, and pDst have the same        \n * number of rows and columns.        \n */\n\n/**        \n * @addtogroup MatrixSub        \n * @{        \n */\n\n/**        \n * @brief Floating-point matrix subtraction        \n * @param[in]       *pSrcA points to the first input matrix structure        \n * @param[in]       *pSrcB points to the second input matrix structure        \n * @param[out]      *pDst points to output matrix structure        \n * @return     \t\tThe function returns either        \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        \n */\n\narm_status arm_mat_sub_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */\n  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  uint32_t numSamples;                           /* total number of elements in the matrix  */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix subtraction */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract and then store the results in the destination buffer. */\n      /* Read values from source A */\n      inA1 = pIn1[0];\n\n      /* Read values from source B */\n      inB1 = pIn2[0];\n\n      /* Read values from source A */\n      inA2 = pIn1[1];\n\n      /* out = sourceA - sourceB */\n      out1 = inA1 - inB1;\n\n      /* Read values from source B */\n      inB2 = pIn2[1];\n\n      /* Read values from source A */\n      inA1 = pIn1[2];\n\n      /* out = sourceA - sourceB */\n      out2 = inA2 - inB2;\n\n      /* Read values from source B */\n      inB1 = pIn2[2];\n\n      /* Store result in destination */\n      pOut[0] = out1;\n      pOut[1] = out2;\n\n      /* Read values from source A */\n      inA2 = pIn1[3];\n\n      /* Read values from source B */\n      inB2 = pIn2[3];\n\n      /* out = sourceA - sourceB */\n      out1 = inA1 - inB1;\n\n\n      /* out = sourceA - sourceB */\n      out2 = inA2 - inB2;\n\n      /* Store result in destination */\n      pOut[2] = out1;\n\n      /* Store result in destination */\n      pOut[3] = out2;\n\n\n      /* update pointers to process next sampels */\n      pIn1 += 4u;\n      pIn2 += 4u;\n      pOut += 4u;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract and then store the results in the destination buffer. */\n      *pOut++ = (*pIn1++) - (*pIn2++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixSub group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_sub_q15.c    \n*    \n* Description:\tQ15 Matrix subtraction    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixSub    \n * @{    \n */\n\n/**    \n * @brief Q15 matrix subtraction.    \n * @param[in]       *pSrcA points to the first input matrix structure    \n * @param[in]       *pSrcB points to the second input matrix structure    \n * @param[out]      *pDst points to output matrix structure    \n * @return     \t\tThe function returns either    \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    \n *    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    \n */\n\narm_status arm_mat_sub_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst)\n{\n  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */\n  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */\n  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  uint32_t numSamples;                           /* total number of elements in the matrix */\n  uint32_t blkCnt;                               /* loop counters  */\n  arm_status status;                             /* status of matrix subtraction  */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Apply loop unrolling */\n    blkCnt = numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract, Saturate and then store the results in the destination buffer. */\n      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);\n      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract and then store the results in the destination buffer. */\n      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract and then store the results in the destination buffer. */\n      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixSub group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_sub_q31.c    \n*    \n* Description:\tQ31 matrix subtraction    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupMatrix        \n */\n\n/**        \n * @addtogroup MatrixSub        \n * @{        \n */\n\n/**        \n * @brief Q31 matrix subtraction.        \n * @param[in]       *pSrcA points to the first input matrix structure        \n * @param[in]       *pSrcB points to the second input matrix structure        \n * @param[out]      *pDst points to output matrix structure        \n * @return     \t\tThe function returns either        \n * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        \n *        \n * Scaling and Overflow Behavior:        \n * \\par        \n * The function uses saturating arithmetic.        \n * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        \n */\n\n\narm_status arm_mat_sub_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */\n  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */\n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  q31_t inA1, inB1;                              /* temporary variables */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q31_t inA2, inB2;                              /* temporary variables */\n  q31_t out1, out2;                              /* temporary variables */\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  uint32_t numSamples;                           /* total number of elements in the matrix  */\n  uint32_t blkCnt;                               /* loop counters */\n  arm_status status;                             /* status of matrix subtraction */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n  /* Check for matrix mismatch condition  */\n  if((pSrcA->numRows != pSrcB->numRows) ||\n     (pSrcA->numCols != pSrcB->numCols) ||\n     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif\n  {\n    /* Total number of samples in the input matrix */\n    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n    /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n    /* Loop Unrolling */\n    blkCnt = numSamples >> 2u;\n\n    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n     ** a second loop below computes the remaining 1 to 3 samples. */\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract, saturate and then store the results in the destination buffer. */\n      /* Read values from source A */\n      inA1 = pIn1[0];\n\n      /* Read values from source B */\n      inB1 = pIn2[0];\n\n      /* Read values from source A */\n      inA2 = pIn1[1];\n\n      /* Subtract and saturate */\n      out1 = __QSUB(inA1, inB1);\n\n      /* Read values from source B */\n      inB2 = pIn2[1];\n\n      /* Read values from source A */\n      inA1 = pIn1[2];\n\n      /* Subtract and saturate */\n      out2 = __QSUB(inA2, inB2);\n\n      /* Read values from source B */\n      inB1 = pIn2[2];\n\n      /* Store result in destination */\n      pOut[0] = out1;\n      pOut[1] = out2;\n\n      /* Read values from source A */\n      inA2 = pIn1[3];\n\n      /* Read values from source B */\n      inB2 = pIn2[3];\n\n      /* Subtract and saturate */\n      out1 = __QSUB(inA1, inB1);\n\n      /* Subtract and saturate */\n      out2 = __QSUB(inA2, inB2);\n\n      /* Store result in destination */\n      pOut[2] = out1;\n      pOut[3] = out2;\n\n      /* update pointers to process next samples */\n      pIn1 += 4u;\n      pIn2 += 4u;\n      pOut += 4u;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        \n     ** No loop unrolling is used. */\n    blkCnt = numSamples % 0x4u;\n\n#else\n\n    /* Run the below code for Cortex-M0 */\n\n    /* Initialize blkCnt with number of samples */\n    blkCnt = numSamples;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n    while(blkCnt > 0u)\n    {\n      /* C(m,n) = A(m,n) - B(m,n) */\n      /* Subtract, saturate and then store the results in the destination buffer. */\n      inA1 = *pIn1++;\n      inB1 = *pIn2++;\n\n      inA1 = __QSUB(inA1, inB1);\n\n      *pOut++ = inA1;\n\n      /* Decrement the loop counter */\n      blkCnt--;\n    }\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**        \n * @} end of MatrixSub group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_trans_f32.c    \n*    \n* Description:\tFloating-point matrix transpose.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n/**    \n * @defgroup MatrixTrans Matrix Transpose    \n *    \n * Tranposes a matrix.    \n * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.    \n * \\image html MatrixTranspose.gif \"Transpose of a 3 x 3 matrix\"    \n */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixTrans    \n * @{    \n */\n\n/**    \n  * @brief Floating-point matrix transpose.    \n  * @param[in]  *pSrc points to the input matrix    \n  * @param[out] *pDst points to the output matrix    \n  * @return \tThe function returns either  ARM_MATH_SIZE_MISMATCH    \n  * or ARM_MATH_SUCCESS based on the outcome of size checking.    \n  */\n\n\narm_status arm_mat_trans_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  arm_matrix_instance_f32 * pDst)\n{\n  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */\n  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */\n  float32_t *px;                                 /* Temporary output data matrix pointer */\n  uint16_t nRows = pSrc->numRows;                /* number of rows */\n  uint16_t nColumns = pSrc->numCols;             /* number of columns */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */\n  arm_status status;                             /* status of matrix transpose  */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n      /* Loop Unrolling */\n      blkCnt = nColumns >> 2;\n\n      /* The pointer px is set to starting address of the column being processed */\n      px = pOut + i;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n       ** a second loop below computes the remaining 1 to 3 samples. */\n      while(blkCnt > 0u)        /* column loop */\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        blkCnt--;\n      }\n\n      /* Perform matrix transpose for last 3 samples here. */\n      blkCnt = nColumns % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        blkCnt--;\n      }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  uint16_t col, i = 0u, row = nRows;             /* loop counters */\n  arm_status status;                             /* status of matrix transpose  */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n      /* The pointer px is set to starting address of the column being processed */\n      px = pOut + i;\n\n      /* Initialize column loop counter */\n      col = nColumns;\n\n      while(col > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n      i++;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);          /* row loop end  */\n\n    /* Set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixTrans group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_trans_q15.c    \n*    \n* Description:\tQ15 matrix transpose.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixTrans    \n * @{    \n */\n\n/*    \n * @brief Q15 matrix transpose.    \n * @param[in]  *pSrc points to the input matrix    \n * @param[out] *pDst points to the output matrix    \n * @return \tThe function returns either  ARM_MATH_SIZE_MISMATCH    \n * or ARM_MATH_SUCCESS based on the outcome of size checking.    \n */\n\narm_status arm_mat_trans_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  arm_matrix_instance_q15 * pDst)\n{\n  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */\n  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */\n  uint16_t nRows = pSrc->numRows;                /* number of nRows */\n  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */\n  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */\n  arm_status status;                             /* status of matrix transpose */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n  q31_t in;                                      /* variable to hold temporary output  */\n\n#else\n\n  q15_t in;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n\n      /* Apply loop unrolling and exchange the columns with row elements */\n      col = nColumns >> 2u;\n\n      /* The pointer pOut is set to starting address of the column being processed */\n      pOut = pDst->pData + i;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n       ** a second loop below computes the remaining 1 to 3 samples. */\n      while(col > 0u)\n      {\n#ifndef UNALIGNED_SUPPORT_DISABLE\n\n        /* Read two elements from the row */\n        in = *__SIMD32(pSrcA)++;\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *pOut = (q15_t) in;\n\n#else\n\n        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer pOut to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Unpack and store the second element in the destination */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *pOut = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer pOut to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Read two elements from the row */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        in = *__SIMD32(pSrcA)++;\n\n#else\n\n        in = *__SIMD32(pSrcA)++;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Unpack and store one element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *pOut = (q15_t) in;\n\n#else\n\n        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n        /* Update the pointer pOut to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Unpack and store the second element in the destination */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);\n\n#else\n\n        *pOut = (q15_t) in;\n\n#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */\n\n#else\t \n        /* Read one element from the row */\n        in = *pSrcA++;\n\n        /* Store one element in the destination */\n        *pOut = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Read one element from the row */\n        in = *pSrcA++;\n\n        /* Store one element in the destination */\n        *pOut = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Read one element from the row */\n        in = *pSrcA++;\n\n        /* Store one element in the destination */\n        *pOut = in;\n \n        /* Update the pointer px to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Read one element from the row */\n        in = *pSrcA++;\n\n        /* Store one element in the destination */\n        *pOut = in;\n\n#endif\t/*\t#ifndef UNALIGNED_SUPPORT_DISABLE\t*/\n\n        /* Update the pointer pOut to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n      /* Perform matrix transpose for last 3 samples here. */\n      col = nColumns % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n      /* The pointer pOut is set to starting address of the column being processed */\n      pOut = pDst->pData + i;\n\n      /* Initialize column loop counter */\n      col = nColumns;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n      while(col > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *pOut = *pSrcA++;\n\n        /* Update the pointer pOut to point to the next row of the transposed matrix */\n        pOut += nRows;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n      i++;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    } while(row > 0u);\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixTrans group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1\n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_mat_trans_q31.c    \n*    \n* Description:\tQ31 matrix transpose.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupMatrix    \n */\n\n/**    \n * @addtogroup MatrixTrans    \n * @{    \n */\n\n/*    \n  * @brief Q31 matrix transpose.    \n  * @param[in]  *pSrc points to the input matrix    \n  * @param[out] *pDst points to the output matrix    \n  * @return \tThe function returns either  ARM_MATH_SIZE_MISMATCH    \n  * or ARM_MATH_SUCCESS based on the outcome of size checking.    \n */\n\narm_status arm_mat_trans_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  arm_matrix_instance_q31 * pDst)\n{\n  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */\n  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */\n  q31_t *px;                                     /* Temporary output data matrix pointer */\n  uint16_t nRows = pSrc->numRows;                /* number of nRows */\n  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */\n  arm_status status;                             /* status of matrix transpose */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n      /* Apply loop unrolling and exchange the columns with row elements */\n      blkCnt = nColumns >> 2u;\n\n      /* The pointer px is set to starting address of the column being processed */\n      px = pOut + i;\n\n      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n       ** a second loop below computes the remaining 1 to 3 samples. */\n      while(blkCnt > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        blkCnt--;\n      }\n\n      /* Perform matrix transpose for last 3 samples here. */\n      blkCnt = nColumns % 0x4u;\n\n      while(blkCnt > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        blkCnt--;\n      }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  uint16_t col, i = 0u, row = nRows;             /* loop counters */\n  arm_status status;                             /* status of matrix transpose */\n\n\n#ifdef ARM_MATH_MATRIX_CHECK\n\n  /* Check for matrix mismatch condition */\n  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))\n  {\n    /* Set status as ARM_MATH_SIZE_MISMATCH */\n    status = ARM_MATH_SIZE_MISMATCH;\n  }\n  else\n#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */\n\n  {\n    /* Matrix transpose by exchanging the rows with columns */\n    /* row loop     */\n    do\n    {\n      /* The pointer px is set to starting address of the column being processed */\n      px = pOut + i;\n\n      /* Initialize column loop counter */\n      col = nColumns;\n\n      while(col > 0u)\n      {\n        /* Read and store the input element in the destination */\n        *px = *pIn++;\n\n        /* Update the pointer px to point to the next row of the transposed matrix */\n        px += nRows;\n\n        /* Decrement the column loop counter */\n        col--;\n      }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n      i++;\n\n      /* Decrement the row loop counter */\n      row--;\n\n    }\n    while(row > 0u);            /* row loop end */\n\n    /* set status as ARM_MATH_SUCCESS */\n    status = ARM_MATH_SUCCESS;\n  }\n\n  /* Return to application */\n  return (status);\n}\n\n/**    \n * @} end of MatrixTrans group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_max_f32.c    \n*    \n* Description:\tMaximum value of a floating-point vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup Max Maximum    \n *    \n * Computes the maximum value of an array of data.     \n * The function returns both the maximum value and its position within the array.     \n * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    \n */\n\n/**    \n * @addtogroup Max    \n * @{    \n */\n\n\n/**    \n * @brief Maximum value of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult maximum value returned here    \n * @param[out]      *pIndex index of maximum value returned here    \n * @return none.    \n */\n\nvoid arm_max_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 1u;\n    }\n\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 2u;\n    }\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  blkCnt = (blockSize - 1u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and it's index */\n      out = maxVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Store the maximum value and it's index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Max group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_max_q15.c    \n*    \n* Description:\tMaximum value of a Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup Max    \n * @{    \n */\n\n\n/**    \n * @brief Maximum value of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult maximum value returned here    \n * @param[out]      *pIndex index of maximum value returned here    \n * @return none.    \n */\n\nvoid arm_max_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 1u;\n    }\n\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 2u;\n    }\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  blkCnt = (blockSize - 1u);\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and it's index */\n      out = maxVal1;\n      outIndex = blockSize - blkCnt;\n    }\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Store the maximum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Max group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_max_q31.c    \n*    \n* Description:\tMaximum value of a Q31 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup Max    \n * @{    \n */\n\n\n/**    \n * @brief Maximum value of a Q31 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult maximum value returned here    \n * @param[out]      *pIndex index of maximum value returned here    \n * @return none.    \n */\n\nvoid arm_max_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 1u;\n    }\n\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 2u;\n    }\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  blkCnt = (blockSize - 1u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and it's index */\n      out = maxVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Store the maximum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Max group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_max_q7.c    \n*    \n* Description:\tMaximum value of a Q7 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup Max    \n * @{    \n */\n\n\n/**    \n * @brief Maximum value of a Q7 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult maximum value returned here    \n * @param[out]      *pIndex index of maximum value returned here    \n  * @return none.    \n */\n\nvoid arm_max_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 1u;\n    }\n\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 2u;\n    }\n\n    maxVal2 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the maximum value */\n    if(out < maxVal2)\n    {\n      /* Update the maximum value and its index */\n      out = maxVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  blkCnt = (blockSize - 1u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* Initialize maxVal to the next consecutive values one by one */\n    maxVal1 = *pSrc++;\n\n    /* compare for the maximum value */\n    if(out < maxVal1)\n    {\n      /* Update the maximum value and it's index */\n      out = maxVal1;\n      outIndex = blockSize - blkCnt;\n    }\n    /* Decrement the loop counter */\n    blkCnt--;\n\n  }\n\n  /* Store the maximum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n\n}\n\n/**    \n * @} end of Max group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_mean_f32.c    \n*    \n* Description:\tMean value of a floating-point vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup mean Mean    \n *    \n * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.    \n * The underlying algorithm is used:    \n *    \n * 
    \n * \tResult = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    \n * 
    \n *    \n * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    \n */\n\n/**    \n * @addtogroup mean    \n * @{    \n */\n\n\n/**    \n * @brief Mean value of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult mean value returned here    \n * @return none.    \n */\n\n\nvoid arm_mean_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult)\n{\n  float32_t sum = 0.0f;                          /* Temporary result storage */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t in1, in2, in3, in4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    in1 = *pSrc++;\n    in2 = *pSrc++;\n    in3 = *pSrc++;\n    in4 = *pSrc++;\n\n    sum += in1;\n    sum += in2;\n    sum += in3;\n    sum += in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    sum += *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */\n  /* Store the result to the destination */\n  *pResult = sum / (float32_t) blockSize;\n}\n\n/**    \n * @} end of mean group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_mean_q15.c    \n*    \n* Description:\tMean value of a Q15 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup mean    \n * @{    \n */\n\n/**    \n * @brief Mean value of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult mean value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.    \n * The input is represented in 1.15 format and is accumulated in a 32-bit     \n * accumulator in 17.15 format.     \n * There is no risk of internal overflow with this approach, and the     \n * full precision of intermediate result is preserved.     \n * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.    \n *    \n */\n\n\nvoid arm_mean_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult)\n{\n  q31_t sum = 0;                                 /* Temporary result storage */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    sum += *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */\n  /* Store the result to the destination */\n  *pResult = (q15_t) (sum / blockSize);\n}\n\n/**    \n * @} end of mean group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_mean_q31.c    \n*    \n* Description:\tMean value of a Q31 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup mean    \n * @{    \n */\n\n/**    \n * @brief Mean value of a Q31 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult mean value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *\\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * The input is represented in 1.31 format and is accumulated in a 64-bit    \n * accumulator in 33.31 format.    \n * There is no risk of internal overflow with this approach, and the     \n * full precision of intermediate result is preserved.     \n * Finally, the accumulator is truncated to yield a result of 1.31 format.    \n *    \n */\n\n\nvoid arm_mean_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult)\n{\n  q63_t sum = 0;                                 /* Temporary result storage */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2, in3, in4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    in1 = *pSrc++;\n    in2 = *pSrc++;\n    in3 = *pSrc++;\n    in4 = *pSrc++;\n\n    sum += in1;\n    sum += in2;\n    sum += in3;\n    sum += in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    sum += *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */\n  /* Store the result to the destination */\n  *pResult = (q31_t) (sum / (int32_t) blockSize);\n}\n\n/**    \n * @} end of mean group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_mean_q7.c    \n*    \n* Description:\tMean value of a Q7 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup mean    \n * @{    \n */\n\n/**    \n * @brief Mean value of a Q7 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult mean value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.     \n * The input is represented in 1.7 format and is accumulated in a 32-bit    \n * accumulator in 25.7 format.    \n * There is no risk of internal overflow with this approach, and the     \n * full precision of intermediate result is preserved.     \n * Finally, the accumulator is truncated to yield a result of 1.7 format.    \n *    \n */\n\n\nvoid arm_mean_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult)\n{\n  q31_t sum = 0;                                 /* Temporary result storage */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    in = *__SIMD32(pSrc)++;\n\n    sum += ((in << 24) >> 24);\n    sum += ((in << 16) >> 24);\n    sum += ((in << 8) >> 24);\n    sum += (in >> 24);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    sum += *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */\n  /* Store the result to the destination */\n  *pResult = (q7_t) (sum / (int32_t) blockSize);\n}\n\n/**    \n * @} end of mean group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_min_f32.c    \n*    \n* Description:\tMinimum value of a floating-point vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup Min Minimum    \n *    \n * Computes the minimum value of an array of data.     \n * The function returns both the minimum value and its position within the array.     \n * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    \n */\n\n/**    \n * @addtogroup Min    \n * @{    \n */\n\n\n/**    \n * @brief Minimum value of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult minimum value returned here    \n * @param[out]      *pIndex index of minimum value returned here    \n  * @return none.    \n *    \n */\n\nvoid arm_min_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 1u;\n    }\n\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 2u;\n    }\n\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u ) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  float32_t minVal1, out;                        /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  blkCnt = (blockSize - 1u);\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and it's index */\n      out = minVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n    blkCnt--;\n\n  }\n\n  /* Store the minimum value and it's index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Min group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_min_q15.c    \n*    \n* Description:\tMinimum value of a Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n\n/**    \n * @addtogroup Min    \n * @{    \n */\n\n\n/**    \n * @brief Minimum value of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult minimum value returned here    \n * @param[out]      *pIndex index of minimum value returned here    \n * @return none.    \n *    \n */\n\nvoid arm_min_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 1u;\n    }\n\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 2u;\n    }\n\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u ) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q15_t minVal1, out;                            /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  blkCnt = (blockSize - 1u);\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and it's index */\n      out = minVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n    blkCnt--;\n\n  }\n\n\n\n  /* Store the minimum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Min group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_min_q31.c    \n*    \n* Description:\tMinimum value of a Q31 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n\n/**    \n * @addtogroup Min    \n * @{    \n */\n\n\n/**    \n * @brief Minimum value of a Q31 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult minimum value returned here    \n * @param[out]      *pIndex index of minimum value returned here    \n * @return none.    \n *    \n */\n\nvoid arm_min_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 1u;\n    }\n\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 2u;\n    }\n\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u ) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q31_t minVal1, out;                            /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  blkCnt = (blockSize - 1u);\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and it's index */\n      out = minVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n    blkCnt--;\n\n  }\n\n  /* Store the minimum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n}\n\n/**    \n * @} end of Min group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_min_q7.c    \n*    \n* Description:\tMinimum value of a Q7 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup Min    \n * @{    \n */\n\n\n/**    \n * @brief Minimum value of a Q7 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult minimum value returned here    \n * @param[out]      *pIndex index of minimum value returned here    \n * @return none.    \n *    \n */\n\nvoid arm_min_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult,\n  uint32_t * pIndex)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex, count;              /* loop counter */\n\n  /* Initialise the count value. */\n  count = 0u;\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  /* Loop unrolling */\n  blkCnt = (blockSize - 1u) >> 2u;\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 1u;\n    }\n\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 2u;\n    }\n\n    minVal2 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and its index */\n      out = minVal1;\n      outIndex = count + 3u;\n    }\n\n    /* compare for the minimum value */\n    if(out > minVal2)\n    {\n      /* Update the minimum value and its index */\n      out = minVal2;\n      outIndex = count + 4u;\n    }\n\n    count += 4u;\n\n    blkCnt--;\n  }\n\n  /* if (blockSize - 1u ) is not multiple of 4 */\n  blkCnt = (blockSize - 1u) % 4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q7_t minVal1, out;                             /* Temporary variables to store the output value. */\n  uint32_t blkCnt, outIndex;                     /* loop counter */\n\n  /* Initialise the index value to zero. */\n  outIndex = 0u;\n  /* Load first input value that act as reference value for comparision */\n  out = *pSrc++;\n\n  blkCnt = (blockSize - 1u);\n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n  while(blkCnt > 0)\n  {\n    /* Initialize minVal to the next consecutive values one by one */\n    minVal1 = *pSrc++;\n\n    /* compare for the minimum value */\n    if(out > minVal1)\n    {\n      /* Update the minimum value and it's index */\n      out = minVal1;\n      outIndex = blockSize - blkCnt;\n    }\n\n    blkCnt--;\n\n  }\n\n  /* Store the minimum value and its index into destination pointers */\n  *pResult = out;\n  *pIndex = outIndex;\n\n\n}\n\n/**    \n * @} end of Min group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_power_f32.c    \n*    \n* Description:\tSum of the squares of the elements of a floating-point vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup power Power    \n *    \n * Calculates the sum of the squares of the elements in the input vector.    \n * The underlying algorithm is used:    \n *    \n * 
    \n * \tResult = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    \n * 
    \n *   \n * There are separate functions for floating point, Q31, Q15, and Q7 data types.     \n */\n\n/**    \n * @addtogroup power    \n * @{    \n */\n\n\n/**    \n * @brief Sum of the squares of the elements of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult sum of the squares value returned here    \n * @return none.    \n *    \n */\n\n\nvoid arm_power_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult)\n{\n  float32_t sum = 0.0f;                          /* accumulator */\n  float32_t in;                                  /* Temporary variable to store input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* compute power and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Store the result to the destination */\n  *pResult = sum;\n}\n\n/**    \n * @} end of power group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_power_q15.c    \n*    \n* Description:\tSum of the squares of the elements of a Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup power    \n * @{    \n */\n\n/**    \n * @brief Sum of the squares of the elements of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult sum of the squares value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.     \n * The input is represented in 1.15 format.   \n * Intermediate multiplication yields a 2.30 format, and this    \n * result is added without saturation to a 64-bit accumulator in 34.30 format.    \n * With 33 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the return result is in 34.30 format.     \n *    \n */\n\nvoid arm_power_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult)\n{\n  q63_t sum = 0;                                 /* Temporary result storage */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in32;                                    /* Temporary variable to store input value */\n  q15_t in16;                                    /* Temporary variable to store input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n  /* loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in32 = *__SIMD32(pSrc)++;\n    sum = __SMLALD(in32, in32, sum);\n    in32 = *__SIMD32(pSrc)++;\n    sum = __SMLALD(in32, in32, sum);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in16 = *pSrc++;\n    sum = __SMLALD(in16, in16, sum);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t in;                                      /* Temporary variable to store input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += ((q31_t) in * in);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Store the results in 34.30 format  */\n  *pResult = sum;\n}\n\n/**    \n * @} end of power group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_power_q31.c    \n*    \n* Description:\tSum of the squares of the elements of a Q31 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup power    \n * @{    \n */\n\n/**    \n * @brief Sum of the squares of the elements of a Q31 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult sum of the squares value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * The input is represented in 1.31 format.    \n * Intermediate multiplication yields a 2.62 format, and this    \n * result is truncated to 2.48 format by discarding the lower 14 bits.    \n * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    \n * With 15 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the return result is in 16.48 format.     \n *    \n */\n\nvoid arm_power_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult)\n{\n  q63_t sum = 0;                                 /* Temporary result storage */\n  q31_t in;\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */\n    in = *pSrc++;\n    sum += ((q63_t) in * in) >> 14u;\n\n    in = *pSrc++;\n    sum += ((q63_t) in * in) >> 14u;\n\n    in = *pSrc++;\n    sum += ((q63_t) in * in) >> 14u;\n\n    in = *pSrc++;\n    sum += ((q63_t) in * in) >> 14u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += ((q63_t) in * in) >> 14u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Store the results in 16.48 format  */\n  *pResult = sum;\n}\n\n/**    \n * @} end of power group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_power_q7.c    \n*    \n* Description:\tSum of the squares of the elements of a Q7 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup power    \n * @{    \n */\n\n/**    \n * @brief Sum of the squares of the elements of a Q7 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult sum of the squares value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 32-bit internal accumulator.     \n * The input is represented in 1.7 format.   \n * Intermediate multiplication yields a 2.14 format, and this    \n * result is added without saturation to an accumulator in 18.14 format.    \n * With 17 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the return result is in 18.14 format.     \n *    \n */\n\nvoid arm_power_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult)\n{\n  q31_t sum = 0;                                 /* Temporary result storage */\n  q7_t in;                                       /* Temporary variable to store input */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t input1;                                  /* Temporary variable to store packed input */\n  q31_t in1, in2;                                /* Temporary variables to store input */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* Reading two inputs of pSrc vector and packing */\n    input1 = *__SIMD32(pSrc)++;\n\n    in1 = __SXTB16(__ROR(input1, 8));\n    in2 = __SXTB16(input1);\n\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* calculate power and accumulate to accumulator */\n    sum = __SMLAD(in1, in1, sum);\n    sum = __SMLAD(in2, in2, sum);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute Power and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += ((q15_t) in * in);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Store the result in 18.14 format  */\n  *pResult = sum;\n}\n\n/**    \n * @} end of power group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_rms_f32.c    \n*    \n* Description:\tRoot mean square value of an array of F32 type    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup RMS Root mean square (RMS)    \n *    \n *     \n * Calculates the Root Mean Sqaure of the elements in the input vector.    \n * The underlying algorithm is used:    \n *    \n * 
    \n * \tResult = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    \n * 
    \n *   \n * There are separate functions for floating point, Q31, and Q15 data types.     \n */\n\n/**    \n * @addtogroup RMS    \n * @{    \n */\n\n\n/**    \n * @brief Root Mean Square of the elements of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult rms value returned here    \n * @return none.    \n *    \n */\n\nvoid arm_rms_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult)\n{\n  float32_t sum = 0.0f;                          /* Accumulator */\n  float32_t in;                                  /* Tempoprary variable to store input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute sum of the squares and then store the result in a temporary variable, sum  */\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n    in = *pSrc++;\n    sum += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute sum of the squares and then store the results in a temporary variable, sum  */\n    in = *pSrc++;\n    sum += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Rms and store the result in the destination */\n  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);\n}\n\n/**    \n * @} end of RMS group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_rms_q15.c    \n*    \n* Description:\tRoot Mean Square of the elements of a Q15 vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @addtogroup RMS    \n * @{    \n */\n\n/**    \n * @brief Root Mean Square of the elements of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult rms value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * The input is represented in 1.15 format.    \n * Intermediate multiplication yields a 2.30 format, and this    \n * result is added without saturation to a 64-bit accumulator in 34.30 format.    \n * With 33 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     \n * 15 bits, and then saturated to yield a result in 1.15 format.    \n *    \n */\n\nvoid arm_rms_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult)\n{\n  q63_t sum = 0;                                 /* accumulator */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in;                                      /* temporary variable to store the input value */\n  q15_t in1;                                     /* temporary variable to store the input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n  /* loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute sum of the squares and then store the results in a temporary variable, sum */\n    in = *__SIMD32(pSrc)++;\n    sum = __SMLALD(in, in, sum);\n    in = *__SIMD32(pSrc)++;\n    sum = __SMLALD(in, in, sum);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute sum of the squares and then store the results in a temporary variable, sum */\n    in1 = *pSrc++;\n    sum = __SMLALD(in1, in1, sum);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Truncating and saturating the accumulator to 1.15 format */\n  in = (q31_t)(sum >> 15);\n\n  in1 = __SSAT(in / blockSize, 16);\n\n  /* Store the result in the destination */\n  arm_sqrt_q15(in1, pResult);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t in;                                      /* temporary variable to store the input value */\n  q31_t tmp;                                     /* temporary variable to store the input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute sum of the squares and then store the results in a temporary variable, sum */\n    in = *pSrc++;\n    sum += ((q31_t) in * in);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Truncating and saturating the accumulator to 1.15 format */\n  tmp = (q31_t)(sum >> 15);\n\n  in = __SSAT(tmp / blockSize, 16);\n\n  /* Store the result in the destination */\n  arm_sqrt_q15(in, pResult);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of RMS group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_rms_q31.c    \n*    \n* Description:\tRoot Mean Square of the elements of a Q31 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @addtogroup RMS        \n * @{        \n */\n\n\n/**        \n * @brief Root Mean Square of the elements of a Q31 vector.        \n * @param[in]       *pSrc points to the input vector        \n * @param[in]       blockSize length of the input vector        \n * @param[out]      *pResult rms value returned here        \n * @return none.        \n *        \n * @details        \n * Scaling and Overflow Behavior:        \n *        \n *\\par        \n * The function is implemented using an internal 64-bit accumulator.        \n * The input is represented in 1.31 format, and intermediate multiplication        \n * yields a 2.62 format.        \n * The accumulator maintains full precision of the intermediate multiplication results,         \n * but provides only a single guard bit.        \n * There is no saturation on intermediate additions.        \n * If the accumulator overflows, it wraps around and distorts the result.         \n * In order to avoid overflows completely, the input signal must be scaled down by         \n * log2(blockSize) bits, as a total of blockSize additions are performed internally.         \n * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        \n *        \n */\n\nvoid arm_rms_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult)\n{\n  q63_t sum = 0;                                 /* accumulator */\n  q31_t in;                                      /* Temporary variable to store the input */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in1, in2, in3, in4;                      /* Temporary input variables */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.        \n   ** a second loop below computes the remaining 1 to 7 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute sum of the squares and then store the result in a temporary variable, sum */\n    /* read two samples from source buffer */\n    in1 = pSrc[0];\n    in2 = pSrc[1];\n\n    /* calculate power and accumulate to accumulator */\n    sum += (q63_t) in1 *in1;\n    sum += (q63_t) in2 *in2;\n\n    /* read two samples from source buffer */\n    in3 = pSrc[2];\n    in4 = pSrc[3];\n\n    /* calculate power and accumulate to accumulator */\n    sum += (q63_t) in3 *in3;\n    sum += (q63_t) in4 *in4;\n\n\n    /* update source buffer to process next samples */\n    pSrc += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.        \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */\n    /* Compute sum of the squares and then store the results in a temporary variable, sum */\n    in = *pSrc++;\n    sum += (q63_t) in *in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */\n\n  sum = __SSAT(sum >> 31, 31);\n\n\n  /* Compute Rms and store the result in the destination vector */\n  arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);\n}\n\n/**        \n * @} end of RMS group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_std_f32.c    \n*    \n* Description:\tStandard deviation of the elements of a floating-point vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup STD Standard deviation    \n *    \n * Calculates the standard deviation of the elements in the input vector.     \n * The underlying algorithm is used:    \n *   \n * 
    \n * \tResult = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))   \n *   \n *\t   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   \n *   \n *\t                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   \n * 
   \n *    \n * There are separate functions for floating point, Q31, and Q15 data types.    \n */\n\n/**    \n * @addtogroup STD    \n * @{    \n */\n\n\n/**    \n * @brief Standard deviation of the elements of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult standard deviation value returned here    \n * @return none.    \n *    \n */\n\n\nvoid arm_std_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult)\n{\n  float32_t sum = 0.0f;                          /* Temporary result storage */\n  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */\n  float32_t in;                                  /* input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t meanOfSquares, mean, squareOfMean;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples    \n   * and then store the result in a temporary variable, meanOfSquares. */\n  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);\n\n  /* Compute mean of all input values */\n  mean = sum / (float32_t) blockSize;\n\n  /* Compute square of mean */\n  squareOfMean = (mean * mean) * (((float32_t) blockSize) /\n                                  ((float32_t) blockSize - 1.0f));\n\n  /* Compute standard deviation and then store the result to the destination */\n  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  float32_t squareOfSum;                         /* Square of Sum */\n  float32_t var;                                 /* Temporary varaince storage */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples     \n     * and then store the result in a temporary variable, sumOfSquares. */\n    in = *pSrc++;\n    sumOfSquares += in * in;\n\n    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */\n    /* Compute Sum of the input samples     \n     * and then store the result in a temporary variable, sum. */\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute the square of sum */\n  squareOfSum = ((sum * sum) / (float32_t) blockSize);\n\n  /* Compute the variance */\n  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));\n\n  /* Compute standard deviation and then store the result to the destination */\n  arm_sqrt_f32(var, pResult);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of STD group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_std_q15.c    \n*    \n* Description:\tStandard deviation of an array of Q15 type.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup STD    \n * @{    \n */\n\n/**    \n * @brief Standard deviation of the elements of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult standard deviation value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * The input is represented in 1.15 format.   \n * Intermediate multiplication yields a 2.30 format, and this    \n * result is added without saturation to a 64-bit accumulator in 34.30 format.    \n * With 33 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     \n * 15 bits, and then saturated to yield a result in 1.15 format.    \n */\n\nvoid arm_std_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult)\n{\n  q31_t sum = 0;                                 /* Accumulator */\n  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */\n  q15_t mean;                                    /* mean */\n  uint32_t blkCnt;                               /* loop counter */\n  q15_t t;                                       /* Temporary variable */\n  q63_t sumOfSquares = 0;                        /* Accumulator */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in;                                      /* input value */\n  q15_t in1;                                     /* input value */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n    sumOfSquares = __SMLALD(in, in, sumOfSquares);\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n    sumOfSquares = __SMLALD(in, in, sumOfSquares);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in1 = *pSrc++;\n    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);\n    sum += in1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples    \n   * and then store the result in a temporary variable, meanOfSquares. */\n  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);\n  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);\n\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);\n\n  /* Compute mean of all input values */\n  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);\n  mean = (q15_t) __SSAT(sum, 16u);\n\n  /* Compute square of mean */\n  squareOfMean = ((q31_t) mean * mean) >> 15;\n  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);\n\n  /* mean of the squares minus the square of the mean. */\n  in1 = (q15_t) (meanOfSquares - squareOfMean);\n\n  /* Compute standard deviation and store the result to the destination */\n  arm_sqrt_q15(in1, pResult);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  q15_t in;                                      /* input value */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples     \n     * and then store the result in a temporary variable, sumOfSquares. */\n    in = *pSrc++;\n    sumOfSquares += (in * in);\n\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    /* Compute sum of all input values and then store the result in a temporary variable, sum. */\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples     \n   * and then store the result in a temporary variable, meanOfSquares. */\n  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);\n  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);\n\n  /* Compute mean of all input values */\n  mean = (q15_t) __SSAT(sum, 16u);\n\n  /* Compute square of mean of the input samples   \n   * and then store the result in a temporary variable, squareOfMean.*/\n  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);\n  squareOfMean = ((q31_t) mean * mean) >> 15;\n  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);\n\n  /* mean of the squares minus the square of the mean. */\n  in = (q15_t) (meanOfSquares - squareOfMean);\n\n  /* Compute standard deviation and store the result to the destination */\n  arm_sqrt_q15(in, pResult);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n}\n\n/**    \n * @} end of STD group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_std_q31.c    \n*    \n* Description:\tStandard deviation of an array of Q31 type.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup STD    \n * @{    \n */\n\n\n/**    \n * @brief Standard deviation of the elements of a Q31 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult standard deviation value returned here    \n * @return none.    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n *\\par    \n * The function is implemented using an internal 64-bit accumulator.    \n * The input is represented in 1.31 format, and intermediate multiplication    \n * yields a 2.62 format.    \n * The accumulator maintains full precision of the intermediate multiplication results,     \n * but provides only a single guard bit.    \n * There is no saturation on intermediate additions.    \n * If the accumulator overflows it wraps around and distorts the result.    \n * In order to avoid overflows completely the input signal must be scaled down by     \n * log2(blockSize) bits, as a total of blockSize additions are performed internally.     \n * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.    \n *    \n */\n\n\nvoid arm_std_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult)\n{\n  q63_t sum = 0;                                 /* Accumulator */\n  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */\n  q31_t mean;                                    /* mean */\n  q31_t in;                                      /* input value */\n  q31_t t;                                       /* Temporary variable */\n  uint32_t blkCnt;                               /* loop counter */\n  q63_t sumOfSquares = 0;                        /* Accumulator */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += ((q63_t) (in) * (in));\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += ((q63_t) (in) * (in));\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += ((q63_t) (in) * (in));\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += ((q63_t) (in) * (in));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += ((q63_t) (in) * (in));\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);\n\n  /* Compute Mean of squares of the input samples    \n   * and then store the result in a temporary variable, meanOfSquares. */\n  sumOfSquares = (sumOfSquares >> 31);\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples     \n     * and then store the result in a temporary variable, sumOfSquares. */\n    in = *pSrc++;\n    sumOfSquares += ((q63_t) (in) * (in));\n\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    /* Compute sum of all input values and then store the result in a temporary variable, sum. */\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples     \n   * and then store the result in a temporary variable, meanOfSquares. */\n  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);\n  sumOfSquares = (sumOfSquares >> 31);\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Compute mean of all input values */\n  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);\n  mean = (q31_t) (sum);\n\n  /* Compute square of mean */\n  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);\n  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);\n\n\n  /* Compute standard deviation and then store the result to the destination */\n  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);\n\n}\n\n/**    \n * @} end of STD group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_var_f32.c    \n*    \n* Description:\tVariance of the elements of a floating-point vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @defgroup variance  Variance    \n *    \n * Calculates the variance of the elements in the input vector.    \n * The underlying algorithm is used:    \n *    \n * 
    \n * \tResult = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)   \n *   \n *\t   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   \n *   \n *\t                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   \n * 
   \n *    \n * There are separate functions for floating point, Q31, and Q15 data types.    \n */\n\n/**    \n * @addtogroup variance    \n * @{    \n */\n\n\n/**    \n * @brief Variance of the elements of a floating-point vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult variance value returned here    \n * @return none.    \n *    \n */\n\n\nvoid arm_var_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult)\n{\n\n  float32_t sum = 0.0f;                          /* Temporary result storage */\n  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */\n  float32_t in;                                  /* input value */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sum += in;\n    sumOfSquares += in * in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples    \n   * and then store the result in a temporary variable, meanOfSquares. */\n  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);\n\n  /* Compute mean of all input values */\n  mean = sum / (float32_t) blockSize;\n\n  /* Compute square of mean */\n  squareOfMean = (mean * mean) * (((float32_t) blockSize) /\n                                  ((float32_t) blockSize - 1.0f));\n\n  /* Compute variance and then store the result to the destination */\n  *pResult = meanOfSquares - squareOfMean;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  float32_t squareOfSum;                         /* Square of Sum */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples     \n     * and then store the result in a temporary variable, sumOfSquares. */\n    in = *pSrc++;\n    sumOfSquares += in * in;\n\n    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */\n    /* Compute Sum of the input samples     \n     * and then store the result in a temporary variable, sum. */\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute the square of sum */\n  squareOfSum = ((sum * sum) / (float32_t) blockSize);\n\n  /* Compute the variance */\n  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of variance group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_var_q15.c    \n*    \n* Description:\tVariance of an array of Q15 type.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupStats    \n */\n\n/**    \n * @addtogroup variance    \n * @{    \n */\n\n/**    \n * @brief Variance of the elements of a Q15 vector.    \n * @param[in]       *pSrc points to the input vector    \n * @param[in]       blockSize length of the input vector    \n * @param[out]      *pResult variance value returned here    \n * @return none.    \n *    \n * @details    \n * Scaling and Overflow Behavior:    \n *    \n * \\par    \n * The function is implemented using a 64-bit internal accumulator.    \n * The input is represented in 1.15 format.   \n * Intermediate multiplication yields a 2.30 format, and this    \n * result is added without saturation to a 64-bit accumulator in 34.30 format.    \n * With 33 guard bits in the accumulator, there is no risk of overflow, and the    \n * full precision of the intermediate multiplication is preserved.    \n * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     \n * 15 bits, and then saturated to yield a result in 1.15 format.    \n *    \n */\n\n\nvoid arm_var_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult)\n{\n  q31_t sum = 0;                                 /* Accumulator */\n  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */\n  q15_t mean;                                    /* mean */\n  uint32_t blkCnt;                               /* loop counter */\n  q15_t t;                                       /* Temporary variable */\n  q63_t sumOfSquares = 0;                        /* Accumulator */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t in;                                      /* Input variable */\n  q15_t in1;                                     /* Temporary variable */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n    sumOfSquares = __SMLALD(in, in, sumOfSquares);\n    in = *__SIMD32(pSrc)++;\n    sum += ((in << 16) >> 16);\n    sum += (in >> 16);\n    sumOfSquares = __SMLALD(in, in, sumOfSquares);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples    \n     * and then store the result in a temporary variable, sum. */\n    in1 = *pSrc++;\n    sum += in1;\n    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples    \n   * and then store the result in a temporary variable, meanOfSquares. */\n  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);\n  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);\n\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t in;                                      /* Temporary variable */\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples     \n     * and then store the result in a temporary variable, sumOfSquares. */\n    in = *pSrc++;\n    sumOfSquares += (in * in);\n\n    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */\n    /* Compute sum of all input values and then store the result in a temporary variable, sum. */\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* Compute Mean of squares of the input samples     \n   * and then store the result in a temporary variable, meanOfSquares. */\n  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);\n  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);\n  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  /* Compute mean of all input values */\n  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);\n  mean = __SSAT(sum, 16u);\n\n  /* Compute square of mean */\n  squareOfMean = ((q31_t) mean * mean) >> 15;\n  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);\n\n  /* Compute variance and then store the result to the destination */\n  *pResult = (meanOfSquares - squareOfMean);\n\n}\n\n/**    \n * @} end of variance group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_var_q31.c    \n*    \n* Description:\tVariance of an array of Q31 type.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**        \n * @ingroup groupStats        \n */\n\n/**        \n * @addtogroup variance        \n * @{        \n */\n\n/**        \n * @brief Variance of the elements of a Q31 vector.        \n * @param[in]       *pSrc points to the input vector        \n * @param[in]       blockSize length of the input vector        \n * @param[out]      *pResult variance value returned here        \n * @return none.        \n *        \n * @details        \n * Scaling and Overflow Behavior:        \n *        \n *\\par        \n * The function is implemented using an internal 64-bit accumulator.        \n * The input is represented in 1.31 format, and intermediate multiplication        \n * yields a 2.62 format.        \n * The accumulator maintains full precision of the intermediate multiplication results,         \n * but provides only a single guard bit.        \n * There is no saturation on intermediate additions.        \n * If the accumulator overflows it wraps around and distorts the result.        \n * In order to avoid overflows completely the input signal must be scaled down by         \n * log2(blockSize) bits, as a total of blockSize additions are performed internally.         \n * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        \n *        \n */\n\n\nvoid arm_var_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult)\n{\n  q63_t sum = 0, sumSquare = 0;                  /* Accumulator */\n  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */\n  q31_t mean;                                    /* mean */\n  q31_t in;                                      /* input value */\n  q31_t t;                                       /* Temporary variable */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q63_t sumSquare1 = 0;                          /* Accumulator */\n  q31_t in1, in2, in3, in4;                      /* Temporary input variables */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */\n    /* Compute Sum of squares of the input samples        \n     * and then store the result in a temporary variable, sum. */\n    /* read input samples from source buffer */\n    in1 = pSrc[0];\n    in2 = pSrc[1];\n\n    /* calculate sum of inputs */\n    sum += in1;\n    /* calculate sum of squares */\n    sumSquare += ((q63_t) (in1) * (in1));\n    in3 = pSrc[2];\n    sum += in2;\n    sumSquare1 += ((q63_t) (in2) * (in2));\n    in4 = pSrc[3];\n    sum += in3;\n    sumSquare += ((q63_t) (in3) * (in3));\n    sum += in4;\n    sumSquare1 += ((q63_t) (in4) * (in4));\n\n    /* update input pointer to process next samples */\n    pSrc += 4u;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* add two accumulators */\n  sumSquare = sumSquare + sumSquare1;\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */\n    /* Compute Sum of squares of the input samples        \n     * and then store the result in a temporary variable, sum. */\n    in = *pSrc++;\n    sumSquare += ((q63_t) (in) * (in));\n    sum += in;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);\n\n  /* Compute Mean of squares of the input samples        \n   * and then store the result in a temporary variable, meanOfSquares. */\n  sumSquare = (sumSquare >> 31);\n  meanOfSquares = (q31_t) ((sumSquare * t) >> 30);\n\n  /* Compute mean of all input values */\n  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);\n  mean = (q31_t) (sum);\n\n  /* Compute square of mean */\n  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);\n  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);\n\n  /* Compute variance and then store the result to the destination */\n  *pResult = (q63_t) meanOfSquares - squareOfMean;\n\n}\n\n/**        \n * @} end of variance group        \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_copy_f32.c    \n*    \n* Description:\tCopies the elements of a floating-point vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup copy Vector Copy    \n *    \n * Copies sample by sample from source vector to destination vector.    \n *    \n * 
    \n * \tpDst[n] = pSrc[n];   0 <= n < blockSize.    \n * 
    \n *   \n * There are separate functions for floating point, Q31, Q15, and Q7 data types.     \n */\n\n/**    \n * @addtogroup copy    \n * @{    \n */\n\n/**    \n * @brief Copies the elements of a floating-point vector.     \n * @param[in]       *pSrc points to input vector    \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the input vector   \n * @return none.    \n *    \n */\n\n\nvoid arm_copy_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t in1, in2, in3, in4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the results in the destination buffer */\n    in1 = *pSrc++;\n    in2 = *pSrc++;\n    in3 = *pSrc++;\n    in4 = *pSrc++;\n\n    *pDst++ = in1;\n    *pDst++ = in2;\n    *pDst++ = in3;\n    *pDst++ = in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the results in the destination buffer */\n    *pDst++ = *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of BasicCopy group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_copy_q15.c    \n*    \n* Description:\tCopies the elements of a Q15 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup copy    \n * @{    \n */\n/**    \n * @brief Copies the elements of a Q15 vector.     \n * @param[in]       *pSrc points to input vector    \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the input vector   \n * @return none.    \n *    \n */\n\nvoid arm_copy_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Read two inputs */\n    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;\n    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the value in the destination buffer */\n    *pDst++ = *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of BasicCopy group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_copy_q31.c    \n*    \n* Description:\tCopies the elements of a Q31 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup copy    \n * @{    \n */\n\n/**    \n * @brief Copies the elements of a Q31 vector.     \n * @param[in]       *pSrc points to input vector    \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the input vector   \n * @return none.    \n *    \n */\n\nvoid arm_copy_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2, in3, in4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the values in the destination buffer */\n    in1 = *pSrc++;\n    in2 = *pSrc++;\n    in3 = *pSrc++;\n    in4 = *pSrc++;\n\n    *pDst++ = in1;\n    *pDst++ = in2;\n    *pDst++ = in3;\n    *pDst++ = in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the value in the destination buffer */\n    *pDst++ = *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of BasicCopy group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_copy_q7.c    \n*    \n* Description:\tCopies the elements of a Q7 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup copy    \n * @{    \n */\n\n/**    \n * @brief Copies the elements of a Q7 vector.    \n * @param[in]       *pSrc points to input vector    \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the input vector   \n * @return none.    \n *    \n */\n\nvoid arm_copy_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the results in the destination buffer */\n    /* 4 samples are copied and stored at a time using SIMD */\n    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n  while(blkCnt > 0u)\n  {\n    /* C = A */\n    /* Copy and then store the results in the destination buffer */\n    *pDst++ = *pSrc++;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of BasicCopy group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fill_f32.c    \n*    \n* Description:\tFills a constant value into a floating-point vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup Fill Vector Fill    \n *    \n * Fills the destination vector with a constant value.    \n *    \n * 
    \n * \tpDst[n] = value;   0 <= n < blockSize.    \n * 
    \n *   \n * There are separate functions for floating point, Q31, Q15, and Q7 data types.     \n */\n\n/**    \n * @addtogroup Fill    \n * @{    \n */\n\n/**    \n * @brief Fills a constant value into a floating-point vector.     \n * @param[in]       value input value to be filled   \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the output vector   \n * @return none.    \n *    \n */\n\n\nvoid arm_fill_f32(\n  float32_t value,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  float32_t in1 = value;\n  float32_t in2 = value;\n  float32_t in3 = value;\n  float32_t in4 = value;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = in1;\n    *pDst++ = in2;\n    *pDst++ = in3;\n    *pDst++ = in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = value;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of Fill group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fill_q15.c    \n*    \n* Description:\tFills a constant value into a Q15 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup Fill    \n * @{    \n */\n\n/**    \n * @brief Fills a constant value into a Q15 vector.    \n * @param[in]       value input value to be filled   \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the output vector   \n * @return none.    \n *    \n */\n\nvoid arm_fill_q15(\n  q15_t value,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t packedValue;                             /* value packed to 32 bits */\n\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* Packing two 16 bit values to 32 bit value in order to use SIMD */\n  packedValue = __PKHBT(value, value, 16u);\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *__SIMD32(pDst)++ = packedValue;\n    *__SIMD32(pDst)++ = packedValue;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = value;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of Fill group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fill_q31.c    \n*    \n* Description:\tFills a constant value into a Q31 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup Fill    \n * @{    \n */\n\n/**    \n * @brief Fills a constant value into a Q31 vector.    \n * @param[in]       value input value to be filled   \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the output vector   \n * @return none.    \n *    \n */\n\nvoid arm_fill_q31(\n  q31_t value,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1 = value;\n  q31_t in2 = value;\n  q31_t in3 = value;\n  q31_t in4 = value;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = in1;\n    *pDst++ = in2;\n    *pDst++ = in3;\n    *pDst++ = in4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = value;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of Fill group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_fill_q7.c    \n*    \n* Description:\tFills a constant value into a Q7 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup Fill    \n * @{    \n */\n\n/**    \n * @brief Fills a constant value into a Q7 vector.    \n * @param[in]       value input value to be filled   \n * @param[out]      *pDst points to output vector    \n * @param[in]       blockSize length of the output vector   \n * @return none.    \n *    \n */\n\nvoid arm_fill_q7(\n  q7_t value,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t packedValue;                             /* value packed to 32 bits */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* Packing four 8 bit values to 32 bit value in order to use SIMD */\n  packedValue = __PACKq7(value, value, value, value);\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *__SIMD32(pDst)++ = packedValue;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = value */\n    /* Fill the value in the destination buffer */\n    *pDst++ = value;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of Fill group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_float_to_q15.c    \n*    \n* Description:\tConverts the elements of the floating-point vector to Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup float_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the floating-point vector to Q15 vector.    \n * @param[in]       *pSrc points to the floating-point input vector    \n * @param[out]      *pDst points to the Q15 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n * \\par   \n * The equation used for the conversion process is:    \n * 
    \n * \tpDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    \n * 
    \n * \\par Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    \n * \\note   \n * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     \n * defined in the preprocessor section of project options.     \n *    \n */\n\n\nvoid arm_float_to_q15(\n  float32_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pIn = pSrc;                         /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifdef ARM_MATH_ROUNDING\n\n  float32_t in;\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n#else\n\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n#else\n\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 32768.0f);\n    in += in > 0 ? 0.5f : -0.5f;\n    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));\n\n#else\n\n    /* C = A * 32768 */\n    /* convert from float to q15 and then store the results in the destination buffer */\n    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of float_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_float_to_q31.c    \n*    \n* Description:\tConverts the elements of the floating-point vector to Q31 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup float_to_x  Convert 32-bit floating point value    \n */\n\n/**    \n * @addtogroup float_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the floating-point vector to Q31 vector.    \n * @param[in]       *pSrc points to the floating-point input vector    \n * @param[out]      *pDst points to the Q31 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n *\\par Description:    \n * \\par   \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    \n * 
    \n * Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    \n *   \n * \\note In order to apply rounding, the library should be rebuilt with the ROUNDING macro     \n * defined in the preprocessor section of project options.     \n */\n\n\nvoid arm_float_to_q31(\n  float32_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pIn = pSrc;                         /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifdef ARM_MATH_ROUNDING\n\n  float32_t in;\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n\n    /* C = A * 32768 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n#else\n\n    /* C = A * 2147483648 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n\n    /* C = A * 2147483648 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n#else\n\n    /* C = A * 2147483648 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n\n    /* C = A * 2147483648 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 2147483648.0f);\n    in += in > 0 ? 0.5f : -0.5f;\n    *pDst++ = clip_q63_to_q31((q63_t) (in));\n\n#else\n\n    /* C = A * 2147483648 */\n    /* convert from float to Q31 and then store the results in the destination buffer */\n    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of float_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_float_to_q7.c    \n*    \n* Description:\tConverts the elements of the floating-point vector to Q7 vector.   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup float_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the floating-point vector to Q7 vector.    \n * @param[in]       *pSrc points to the floating-point input vector    \n * @param[out]      *pDst points to the Q7 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n *\\par Description:    \n * \\par   \n * The equation used for the conversion process is:    \n * 
    \n * \tpDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    \n * 
    \n * \\par Scaling and Overflow Behavior:    \n * \\par    \n * The function uses saturating arithmetic.    \n * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    \n * \\note   \n * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     \n * defined in the preprocessor section of project options.     \n */\n\n\nvoid arm_float_to_q7(\n  float32_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n  float32_t *pIn = pSrc;                         /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifdef ARM_MATH_ROUNDING\n\n  float32_t in;\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 128);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));\n\n    in = *pIn++;\n    in = (in * 128);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));\n\n    in = *pIn++;\n    in = (in * 128);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));\n\n    in = *pIn++;\n    in = (in * 128);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));\n\n#else\n\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n  while(blkCnt > 0u)\n  {\n\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 128);\n    in += in > 0 ? 0.5 : -0.5;\n    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));\n\n#else\n\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n  while(blkCnt > 0u)\n  {\n#ifdef ARM_MATH_ROUNDING\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    in = *pIn++;\n    in = (in * 128.0f);\n    in += in > 0 ? 0.5f : -0.5f;\n    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));\n\n#else\n\n    /* C = A * 128 */\n    /* convert from float to q7 and then store the results in the destination buffer */\n    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);\n\n#endif /*      #ifdef ARM_MATH_ROUNDING        */\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n * @} end of float_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q15_to_float.c    \n*    \n* Description:\tConverts the elements of the Q15 vector to floating-point vector.     \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup q15_to_x  Convert 16-bit Integer value    \n */\n\n/**    \n * @addtogroup q15_to_x    \n * @{    \n */\n\n\n\n\n/**    \n * @brief  Converts the elements of the Q15 vector to floating-point vector.     \n * @param[in]       *pSrc points to the Q15 input vector    \n * @param[out]      *pDst points to the floating-point output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q15_to_float(\n  q15_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 32768 */\n    /* convert from q15 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 32768.0f);\n    *pDst++ = ((float32_t) * pIn++ / 32768.0f);\n    *pDst++ = ((float32_t) * pIn++ / 32768.0f);\n    *pDst++ = ((float32_t) * pIn++ / 32768.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 32768 */\n    /* convert from q15 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 32768.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of q15_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q15_to_q31.c    \n*    \n* Description:\tConverts the elements of the Q15 vector to Q31 vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q15_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q15 vector to Q31 vector.     \n * @param[in]       *pSrc points to the Q15 input vector    \n * @param[out]      *pDst points to the Q31 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:   \n *   \n * 
    \n * \tpDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q15_to_q31(\n  q15_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2;\n  q31_t out1, out2, out3, out4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q31_t)A << 16 */\n    /* convert from q15 to q31 and then store the results in the destination buffer */\n    in1 = *__SIMD32(pIn)++;\n    in2 = *__SIMD32(pIn)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* extract lower 16 bits to 32 bit result */\n    out1 = in1 << 16u;\n    /* extract upper 16 bits to 32 bit result */\n    out2 = in1 & 0xFFFF0000;\n    /* extract lower 16 bits to 32 bit result */\n    out3 = in2 << 16u;\n    /* extract upper 16 bits to 32 bit result */\n    out4 = in2 & 0xFFFF0000;\n\n#else\n\n    /* extract upper 16 bits to 32 bit result */\n    out1 = in1 & 0xFFFF0000;\n    /* extract lower 16 bits to 32 bit result */\n    out2 = in1 << 16u;\n    /* extract upper 16 bits to 32 bit result */\n    out3 = in2 & 0xFFFF0000;\n    /* extract lower 16 bits to 32 bit result */\n    out4 = in2 << 16u;\n\n#endif //      #ifndef ARM_MATH_BIG_ENDIAN\n\n    *pDst++ = out1;\n    *pDst++ = out2;\n    *pDst++ = out3;\n    *pDst++ = out4;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q31_t)A << 16 */\n    /* convert from q15 to q31 and then store the results in the destination buffer */\n    *pDst++ = (q31_t) * pIn++ << 16;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q15_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q15_to_q7.c    \n*    \n* Description:\tConverts the elements of the Q15 vector to Q7 vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q15_to_x    \n * @{    \n */\n\n\n/**    \n * @brief Converts the elements of the Q15 vector to Q7 vector.     \n * @param[in]       *pSrc points to the Q15 input vector    \n * @param[out]      *pDst points to the Q7 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    \n * 
   \n *   \n */\n\n\nvoid arm_q15_to_q7(\n  q15_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n  q15_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2;\n  q31_t out1, out2;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q7_t) A >> 8 */\n    /* convert from q15 to q7 and then store the results in the destination buffer */\n    in1 = *__SIMD32(pIn)++;\n    in2 = *__SIMD32(pIn)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __PKHTB(in2, in1, 16);\n    out2 = __PKHBT(in2, in1, 16);\n\n#else\n\n    out1 = __PKHTB(in1, in2, 16);\n    out2 = __PKHBT(in1, in2, 16);\n\n#endif //      #ifndef ARM_MATH_BIG_ENDIAN\n\n    /* rotate packed value by 24 */\n    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);\n\n    /* anding with 0xff00ff00 to get two 8 bit values */\n    out1 = out1 & 0xFF00FF00;\n    /* anding with 0x00ff00ff to get two 8 bit values */\n    out2 = out2 & 0x00FF00FF;\n\n    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */\n    out1 = out1 | out2;\n\n    /* store 4 samples at a time to destiantion buffer */\n    *__SIMD32(pDst)++ = out1;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q7_t) A >> 8 */\n    /* convert from q15 to q7 and then store the results in the destination buffer */\n    *pDst++ = (q7_t) (*pIn++ >> 8);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q15_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q31_to_float.c    \n*    \n* Description:\tConverts the elements of the Q31 vector to floating-point vector.      \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup q31_to_x  Convert 32-bit Integer value    \n */\n\n/**    \n * @addtogroup q31_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q31 vector to floating-point vector.    \n * @param[in]       *pSrc points to the Q31 input vector    \n * @param[out]      *pDst points to the floating-point output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q31_to_float(\n  q31_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 2147483648 */\n    /* convert from q31 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);\n    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);\n    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);\n    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 2147483648 */\n    /* convert from q31 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of q31_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q31_to_q15.c    \n*    \n* Description:\tConverts the elements of the Q31 vector to Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q31_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q31 vector to Q15 vector.    \n * @param[in]       *pSrc points to the Q31 input vector    \n * @param[out]      *pDst points to the Q15 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *     \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q31_to_q15(\n  q31_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2, in3, in4;\n  q31_t out1, out2;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q15_t) A >> 16 */\n    /* convert from q31 to q15 and then store the results in the destination buffer */\n    in1 = *pIn++;\n    in2 = *pIn++;\n    in3 = *pIn++;\n    in4 = *pIn++;\n\n    /* pack two higher 16-bit values from two 32-bit values */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __PKHTB(in2, in1, 16);\n    out2 = __PKHTB(in4, in3, 16);\n\n#else\n\n    out1 = __PKHTB(in1, in2, 16);\n    out2 = __PKHTB(in3, in4, 16);\n\n#endif //      #ifdef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst)++ = out1;\n    *__SIMD32(pDst)++ = out2;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q15_t) A >> 16 */\n    /* convert from q31 to q15 and then store the results in the destination buffer */\n    *pDst++ = (q15_t) (*pIn++ >> 16);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q31_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q31_to_q7.c    \n*    \n* Description:\tConverts the elements of the Q31 vector to Q7 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q31_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q31 vector to Q7 vector.    \n * @param[in]       *pSrc points to the Q31 input vector    \n * @param[out]      *pDst points to the Q7 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     \n * 
    \n *   \n */\n\n\nvoid arm_q31_to_q7(\n  q31_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize)\n{\n  q31_t *pIn = pSrc;                             /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n  q31_t in1, in2, in3, in4;\n  q7_t out1, out2, out3, out4;\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q7_t) A >> 24 */\n    /* convert from q31 to q7 and then store the results in the destination buffer */\n    in1 = *pIn++;\n    in2 = *pIn++;\n    in3 = *pIn++;\n    in4 = *pIn++;\n\n    out1 = (q7_t) (in1 >> 24);\n    out2 = (q7_t) (in2 >> 24);\n    out3 = (q7_t) (in3 >> 24);\n    out4 = (q7_t) (in4 >> 24);\n\n    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q7_t) A >> 24 */\n    /* convert from q31 to q7 and then store the results in the destination buffer */\n    *pDst++ = (q7_t) (*pIn++ >> 24);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q31_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q7_to_float.c    \n*    \n* Description:\tConverts the elements of the Q7 vector to floating-point vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @defgroup q7_to_x  Convert 8-bit Integer value    \n */\n\n/**    \n * @addtogroup q7_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q7 vector to floating-point vector.    \n * @param[in]       *pSrc points to the Q7 input vector    \n * @param[out]      *pDst points to the floating-point output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *\t\t     \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q7_to_float(\n  q7_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize)\n{\n  q7_t *pIn = pSrc;                              /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 128 */\n    /* convert from q7 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 128.0f);\n    *pDst++ = ((float32_t) * pIn++ / 128.0f);\n    *pDst++ = ((float32_t) * pIn++ / 128.0f);\n    *pDst++ = ((float32_t) * pIn++ / 128.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (float32_t) A / 128 */\n    /* convert from q7 to float and then store the results in the destination buffer */\n    *pDst++ = ((float32_t) * pIn++ / 128.0f);\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n}\n\n/**    \n * @} end of q7_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q7_to_q15.c    \n*    \n* Description:\tConverts the elements of the Q7 vector to Q15 vector.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q7_to_x    \n * @{    \n */\n\n\n\n\n/**    \n * @brief Converts the elements of the Q7 vector to Q15 vector.    \n * @param[in]       *pSrc points to the Q7 input vector    \n * @param[out]      *pDst points to the Q15 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    \n * 
    \n *   \n */\n\n\nvoid arm_q7_to_q15(\n  q7_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize)\n{\n  q7_t *pIn = pSrc;                              /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n  q31_t in;\n  q31_t in1, in2;\n  q31_t out1, out2;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q15_t) A << 8 */\n    /* convert from q7 to q15 and then store the results in the destination buffer */\n    in = *__SIMD32(pIn)++;\n\n    /* rotatate in by 8 and extend two q7_t values to q15_t values */\n    in1 = __SXTB16(__ROR(in, 8));\n\n    /* extend remainig two q7_t values to q15_t values */\n    in2 = __SXTB16(in);\n\n    in1 = in1 << 8u;\n    in2 = in2 << 8u;\n\n    in1 = in1 & 0xFF00FF00;\n    in2 = in2 & 0xFF00FF00;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out2 = __PKHTB(in1, in2, 16);\n    out1 = __PKHBT(in2, in1, 16);\n\n#else\n\n    out1 = __PKHTB(in1, in2, 16);\n    out2 = __PKHBT(in2, in1, 16);\n\n#endif\n\n    *__SIMD32(pDst)++ = out1;\n    *__SIMD32(pDst)++ = out2;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q15_t) A << 8 */\n    /* convert from q7 to q15 and then store the results in the destination buffer */\n    *pDst++ = (q15_t) * pIn++ << 8;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q7_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c",
    "content": "/* ----------------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t\tarm_q7_to_q31.c    \n*    \n* Description:\tConverts the elements of the Q7 vector to Q31 vector.  \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* ---------------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupSupport    \n */\n\n/**    \n * @addtogroup q7_to_x    \n * @{    \n */\n\n/**    \n * @brief Converts the elements of the Q7 vector to Q31 vector.    \n * @param[in]       *pSrc points to the Q7 input vector    \n * @param[out]      *pDst points to the Q31 output vector   \n * @param[in]       blockSize length of the input vector    \n * @return none.    \n *    \n * \\par Description:    \n *    \n * The equation used for the conversion process is:    \n *   \n * 
    \n * \tpDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   \n * 
     \n *   \n */\n\n\nvoid arm_q7_to_q31(\n  q7_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize)\n{\n  q7_t *pIn = pSrc;                              /* Src pointer */\n  uint32_t blkCnt;                               /* loop counter */\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  q31_t in;\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /*loop Unrolling */\n  blkCnt = blockSize >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  while(blkCnt > 0u)\n  {\n    /* C = (q31_t) A << 24 */\n    /* convert from q7 to q31 and then store the results in the destination buffer */\n    in = *__SIMD32(pIn)++;\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *pDst++ = (__ROR(in, 8)) & 0xFF000000;\n    *pDst++ = (__ROR(in, 16)) & 0xFF000000;\n    *pDst++ = (__ROR(in, 24)) & 0xFF000000;\n    *pDst++ = (in & 0xFF000000);\n\n#else\n\n    *pDst++ = (in & 0xFF000000);\n    *pDst++ = (__ROR(in, 24)) & 0xFF000000;\n    *pDst++ = (__ROR(in, 16)) & 0xFF000000;\n    *pDst++ = (__ROR(in, 8)) & 0xFF000000;\n\n#endif //              #ifndef ARM_MATH_BIG_ENDIAN\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  blkCnt = blockSize % 0x4u;\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Loop over blockSize number of values */\n  blkCnt = blockSize;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n  while(blkCnt > 0u)\n  {\n    /* C = (q31_t) A << 24 */\n    /* convert from q7 to q31 and then store the results in the destination buffer */\n    *pDst++ = (q31_t) * pIn++ << 24;\n\n    /* Decrement the loop counter */\n    blkCnt--;\n  }\n\n}\n\n/**    \n * @} end of q7_to_x group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_bitreversal.c    \n*    \n* Description:\tThis file has common tables like Bitreverse, reciprocal etc which are used across different functions    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/*    \n* @brief  In-place bit reversal function.   \n* @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.   \n* @param[in]      fftSize      length of the FFT.   \n* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.   \n* @param[in]      *pBitRevTab  points to the bit reversal table.   \n* @return none.   \n*/\n\nvoid arm_bitreversal_f32(\nfloat32_t * pSrc,\nuint16_t fftSize,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTab)\n{\n   uint16_t fftLenBy2, fftLenBy2p1;\n   uint16_t i, j;\n   float32_t in;\n\n   /*  Initializations */\n   j = 0u;\n   fftLenBy2 = fftSize >> 1u;\n   fftLenBy2p1 = (fftSize >> 1u) + 1u;\n\n   /* Bit Reversal Implementation */\n   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)\n   {\n      if(i < j)\n      {\n         /*  pSrc[i] <-> pSrc[j]; */\n         in = pSrc[2u * i];\n         pSrc[2u * i] = pSrc[2u * j];\n         pSrc[2u * j] = in;\n\n         /*  pSrc[i+1u] <-> pSrc[j+1u] */\n         in = pSrc[(2u * i) + 1u];\n         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];\n         pSrc[(2u * j) + 1u] = in;\n\n         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */\n         in = pSrc[2u * (i + fftLenBy2p1)];\n         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];\n         pSrc[2u * (j + fftLenBy2p1)] = in;\n\n         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */\n         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];\n         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =\n         pSrc[(2u * (j + fftLenBy2p1)) + 1u];\n         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;\n\n      }\n\n      /*  pSrc[i+1u] <-> pSrc[j+1u] */\n      in = pSrc[2u * (i + 1u)];\n      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];\n      pSrc[2u * (j + fftLenBy2)] = in;\n\n      /*  pSrc[i+2u] <-> pSrc[j+2u] */\n      in = pSrc[(2u * (i + 1u)) + 1u];\n      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];\n      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;\n\n      /*  Reading the index for the bit reversal */\n      j = *pBitRevTab;\n\n      /*  Updating the bit reversal index depending on the fft length  */\n      pBitRevTab += bitRevFactor;\n   }\n}\n\n\n\n/*    \n* @brief  In-place bit reversal function.   \n* @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.   \n* @param[in]      fftLen       length of the FFT.   \n* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   \n* @param[in]      *pBitRevTab  points to bit reversal table.   \n* @return none.   \n*/\n\nvoid arm_bitreversal_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTable)\n{\n   uint32_t fftLenBy2, fftLenBy2p1, i, j;\n   q31_t in;\n\n   /*  Initializations      */\n   j = 0u;\n   fftLenBy2 = fftLen / 2u;\n   fftLenBy2p1 = (fftLen / 2u) + 1u;\n\n   /* Bit Reversal Implementation */\n   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)\n   {\n      if(i < j)\n      {\n         /*  pSrc[i] <-> pSrc[j]; */\n         in = pSrc[2u * i];\n         pSrc[2u * i] = pSrc[2u * j];\n         pSrc[2u * j] = in;\n\n         /*  pSrc[i+1u] <-> pSrc[j+1u] */\n         in = pSrc[(2u * i) + 1u];\n         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];\n         pSrc[(2u * j) + 1u] = in;\n\n         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */\n         in = pSrc[2u * (i + fftLenBy2p1)];\n         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];\n         pSrc[2u * (j + fftLenBy2p1)] = in;\n\n         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */\n         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];\n         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =\n         pSrc[(2u * (j + fftLenBy2p1)) + 1u];\n         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;\n\n      }\n\n      /*  pSrc[i+1u] <-> pSrc[j+1u] */\n      in = pSrc[2u * (i + 1u)];\n      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];\n      pSrc[2u * (j + fftLenBy2)] = in;\n\n      /*  pSrc[i+2u] <-> pSrc[j+2u] */\n      in = pSrc[(2u * (i + 1u)) + 1u];\n      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];\n      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;\n\n      /*  Reading the index for the bit reversal */\n      j = *pBitRevTable;\n\n      /*  Updating the bit reversal index depending on the fft length */\n      pBitRevTable += bitRevFactor;\n   }\n}\n\n\n\n/*    \n   * @brief  In-place bit reversal function.   \n   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.   \n   * @param[in]      fftLen       length of the FFT.   \n   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   \n   * @param[in]      *pBitRevTab  points to bit reversal table.   \n   * @return none.   \n*/\n\nvoid arm_bitreversal_q15(\nq15_t * pSrc16,\nuint32_t fftLen,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTab)\n{\n   q31_t *pSrc = (q31_t *) pSrc16;\n   q31_t in;\n   uint32_t fftLenBy2, fftLenBy2p1;\n   uint32_t i, j;\n\n   /*  Initializations */\n   j = 0u;\n   fftLenBy2 = fftLen / 2u;\n   fftLenBy2p1 = (fftLen / 2u) + 1u;\n\n   /* Bit Reversal Implementation */\n   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)\n   {\n      if(i < j)\n      {\n         /*  pSrc[i] <-> pSrc[j]; */\n         /*  pSrc[i+1u] <-> pSrc[j+1u] */\n         in = pSrc[i];\n         pSrc[i] = pSrc[j];\n         pSrc[j] = in;\n\n         /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */\n         /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */\n         in = pSrc[i + fftLenBy2p1];\n         pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];\n         pSrc[j + fftLenBy2p1] = in;\n      }\n\n      /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */\n      /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */\n      in = pSrc[i + 1u];\n      pSrc[i + 1u] = pSrc[j + fftLenBy2];\n      pSrc[j + fftLenBy2] = in;\n\n      /*  Reading the index for the bit reversal */\n      j = *pBitRevTab;\n\n      /*  Updating the bit reversal index depending on the fft length  */\n      pBitRevTab += bitRevFactor;\n   }\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S",
    "content": ";/* ----------------------------------------------------------------------    \n;* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n;*    \n;* $Date:        17. January 2013  \n;* $Revision: \tV1.4.1  \n;*    \n;* Project: \t    CMSIS DSP Library    \n;* Title:\t    arm_bitreversal2.S   \n;*    \n;* Description:\tThis is the arm_bitreversal_32 function done in\n;*                assembly for maximum speed.  This function is called\n;*                after doing an fft to reorder the output.  The function\n;*                is loop unrolled by 2.\n;*    \n;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n;*  \n;* Redistribution and use in source and binary forms, with or without \n;* modification, are permitted provided that the following conditions\n;* are met:\n;*   - Redistributions of source code must retain the above copyright\n;*     notice, this list of conditions and the following disclaimer.\n;*   - Redistributions in binary form must reproduce the above copyright\n;*     notice, this list of conditions and the following disclaimer in\n;*     the documentation and/or other materials provided with the \n;*     distribution.\n;*   - Neither the name of ARM LIMITED nor the names of its contributors\n;*     may be used to endorse or promote products derived from this\n;*     software without specific prior written permission.\n;*\n;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n;* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n;* POSSIBILITY OF SUCH DAMAGE.   \n;* -------------------------------------------------------------------- */\n#if defined(__CC_ARM) //Keil\n\t#define CODESECT AREA     ||.text||, CODE, READONLY, ALIGN=2\n\t#define LABEL\n#elif defined(__IASMARM__) //IAR\n\t#define CODESECT SECTION `.text`:CODE\n\t#define PROC \n\t#define LABEL \n\t#define ENDP\n\t#define EXPORT PUBLIC\n#elif defined (__GNUC__) //GCC\n\t.syntax unified\n\t.cpu cortex-m4\n\t.fpu softvfp\n\t#define THUMB .thumb\n\t#define CODESECT .section text\n\t#define EXPORT .global\n\t#define PROC :\n\t#define LABEL :\n\t#define ENDP\n\t#define END\n#endif\n\n\tCODESECT\n\tTHUMB\n\n;/*    \n;* @brief  In-place bit reversal function.   \n;* @param[in, out] *pSrc        points to the in-place buffer of unknown 32-bit data type. \n;* @param[in]      bitRevLen    bit reversal table length\n;* @param[in]      *pBitRevTab  points to bit reversal table.   \n;* @return none.   \n;*/\n\tEXPORT arm_bitreversal_32\n   \n#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)\n\narm_bitreversal_32 PROC\n\tADDS     r3,r1,#1\n\tPUSH     {r4-r6}           \n\tADDS     r1,r2,#0          \n\tLSRS     r3,r3,#1          \narm_bitreversal_32_0 LABEL\n\tLDRH     r2,[r1,#2]        \n\tLDRH     r6,[r1,#0]    \n\tADD      r2,r0,r2   \n\tADD      r6,r0,r6   \n\tLDR      r5,[r2,#0] \n\tLDR      r4,[r6,#0]\n\tSTR      r5,[r6,#0]\n\tSTR      r4,[r2,#0]    \n\tLDR      r5,[r2,#4]        \n\tLDR      r4,[r6,#4]       \n\tSTR      r5,[r6,#4]       \n\tSTR      r4,[r2,#4]        \n\tADDS     r1,r1,#4          \n\tSUBS     r3,r3,#1          \n\tBNE      arm_bitreversal_32_0\n\tPOP      {r4-r6}\n\tBX       lr\n\tENDP\n\n#else\n\narm_bitreversal_32 PROC\n\tADDS     r3,r1,#1\n\tCMP      r3,#1\n\tIT       LS\n\tBXLS     lr\n\tPUSH     {r4-r9}           \n\tADDS     r1,r2,#2          \n\tLSRS     r3,r3,#2          \narm_bitreversal_32_0 LABEL       ;/* loop unrolled by 2 */\n\tLDRH     r8,[r1,#4]        \n\tLDRH     r9,[r1,#2]  \n\tLDRH     r2,[r1,#0]        \n\tLDRH     r12,[r1,#-2]    \n\tADD      r8,r0,r8   \n\tADD      r9,r0,r9    \n\tADD      r2,r0,r2   \n\tADD      r12,r0,r12   \n\tLDR      r7,[r9,#0] \n\tLDR      r6,[r8,#0]\n\tLDR      r5,[r2,#0] \n\tLDR      r4,[r12,#0]\n\tSTR      r6,[r9,#0]\n\tSTR      r7,[r8,#0] \n\tSTR      r5,[r12,#0]\n\tSTR      r4,[r2,#0]      \n\tLDR      r7,[r9,#4]        \n\tLDR      r6,[r8,#4] \n\tLDR      r5,[r2,#4]        \n\tLDR      r4,[r12,#4]           \n\tSTR      r6,[r9,#4]       \n\tSTR      r7,[r8,#4]   \n\tSTR      r5,[r12,#4]       \n\tSTR      r4,[r2,#4]        \n\tADDS     r1,r1,#8          \n\tSUBS     r3,r3,#1          \n\tBNE      arm_bitreversal_32_0\n\tPOP      {r4-r9}\n\tBX       lr\n\tENDP\n   \n#endif\n   \n\tEND\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_f32.c   \n*    \n* Description:\tCombined Radix Decimation in Frequency CFFT Floating point processing function\n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\nextern void arm_radix8_butterfly_f32(\n  float32_t * pSrc,\n  uint16_t fftLen,\n  const float32_t * pCoef,\n  uint16_t twidCoefModifier);\n\nextern void arm_bitreversal_32(\n\t\tuint32_t * pSrc,\n\t\tconst uint16_t bitRevLen,\n\t\tconst uint16_t * pBitRevTable);\n\n/**   \n* @ingroup groupTransforms   \n*/\n\n/**   \n* @defgroup ComplexFFT Complex FFT Functions   \n*   \n* \\par\n* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the\n* Discrete Fourier Transform (DFT).  The FFT can be orders of magnitude faster\n* than the DFT, especially for long lengths.\n* The algorithms described in this section\n* operate on complex data.  A separate set of functions is devoted to handling\n* of real sequences.\n* \\par\n* There are separate algorithms for handling floating-point, Q15, and Q31 data\n* types.  The algorithms available for each data type are described next.\n* \\par\n* The FFT functions operate in-place.  That is, the array holding the input data\n* will also be used to hold the corresponding result.  The input data is complex\n* and contains 2*fftLen interleaved values as shown below.\n* 
 {real[0], imag[0], real[1], imag[1],..} 
\n* The FFT result will be contained in the same array and the frequency domain\n* values will have the same interleaving.\n*\n* \\par Floating-point\n* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-8\n* stages are performed along with a single radix-2 or radix-4 stage, as needed.\n* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses\n* a different twiddle factor table.  \n* \\par\n* The function uses the standard FFT definition and output values may grow by a\n* factor of fftLen when computing the forward transform.  The\n* inverse transform includes a scale of 1/fftLen as part of the\n* calculation and this matches the textbook definition of the inverse FFT.\n* \\par\n* Preinitialized data structures containing twiddle factors and bit reversal\n* tables are provided and defined in arm_const_structs.h.  Include \n* this header in your function and then pass one of the constant structures as \n* an argument to arm_cfft_f32.  For example:\n* \\par\n* arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)\n* \\par\n* computes a 64-point inverse complex FFT including bit reversal.\n* The data structures are treated as constant data and not modified during the\n* calculation.  The same data structure can be reused for multiple transforms\n* including mixing forward and inverse transforms.\n* \\par\n* Earlier releases of the library provided separate radix-2 and radix-4\n* algorithms that operated on floating-point data.  These functions are still\n* provided but are deprecated.  The older functions are slower and less general\n* than the new functions.\n* \\par\n* An example of initialization of the constants for the arm_cfft_f32 function follows:\n* \\par\n* const static arm_cfft_instance_f32 *S;\n* ...\n*\t\tswitch (length) {\n*    \t\tcase 16:\n*    \t\t\tS = & arm_cfft_sR_f32_len16;\n*    \t\tbreak;\n*    \t\tcase 32:\n*    \t\t\tS = & arm_cfft_sR_f32_len32;\n*    \t\tbreak;\n*\t\t\tcase 64:\n*    \t\t\tS = & arm_cfft_sR_f32_len64;\n*    \t\tbreak;\n*    \t\tcase 128:\n*    \t\t\tS = & arm_cfft_sR_f32_len128;\n*    \t\tbreak;\n*    \t\tcase 256:\n*    \t\t\tS = & arm_cfft_sR_f32_len256;\n*    \t\tbreak;\n*    \t\tcase 512:\n*    \t\t\tS = & arm_cfft_sR_f32_len512;\n*    \t\tbreak;\n*    \t\tcase 1024:\n*    \t\t\tS = & arm_cfft_sR_f32_len1024;\n*    \t\tbreak;\n*    \t\tcase 2048:\n*    \t\t\tS = & arm_cfft_sR_f32_len2048;\n*    \t\tbreak;\n*    \t\tcase 4096:\n*    \t\t\tS = & arm_cfft_sR_f32_len4096;\n*    \t\tbreak;\n*\t\t\t}\n* \\par Q15 and Q31\n* The library provides radix-2 and radix-4 FFT algorithms for fixed-point data.  The\n* radix-2 algorithm supports lengths of [16, 32, 64, ..., 4096].  The radix-4\n* algorithm supports lengths of [16, 64, 256, ..., 4096].  When possible, you\n* should use the radix-4 algorithm since it is faster than the radix-2 of the\n* same length.\n* \\par\n* The forward FFTs include scaling in order to prevent results from overflowing.\n* Intermediate results are scaled down during each butterfly stage.  In the\n* radix-2 algorithm, a scale of 0.5 is applied during each butterfly.  In the\n* radix-4 algorithm, a scale of 0.25 is applied.  The scaling applies to both\n* the forward and the inverse FFTs.  Thus the forward FFT contains an additional\n* scale factor of 1/fftLen as compared to the standard textbook\n* definition of the FFT.  The inverse FFT also scales down during each butterfly\n* stage and this corresponds to the standard textbook definition.\n* \\par\n* A separate instance structure must be defined for each transform used but\n* twiddle factor and bit reversal tables can be reused.\n* \\par \n* There is also an associated initialization function for each data type.   \n* The initialization function performs the following operations:   \n* - Sets the values of the internal structure fields.   \n* - Initializes twiddle factor table and bit reversal table pointers.\n* \\par   \n* Use of the initialization function is optional.   \n* However, if the initialization function is used, then the instance structure \n* cannot be placed into a const data section. To place an instance structure \n* into a const data section, the instance structure should be manually \n* initialized as follows:\n* 
   \n*arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   \n*arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   \n*arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    \n*arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    \n*arm_cfft_instance_f32 S = {fftLen, pTwiddle, pBitRevTable, bitRevLength};\n* 
   \n* \\par   \n* where fftLen length of CFFT/CIFFT; ifftFlag Flag for\n* selection of forward or inverse transform.  When ifftFlag is set the inverse\n* transform is calculated.\n* bitReverseFlag Flag for selection of output order (Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    \n* pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the bit reversal table.   \n* twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    \n* pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   \n* onebyfftLen value of 1/fftLen to calculate CIFFT;\n* \\par\n* The Q15 and Q31 FFT functions use a large bit reversal and twiddle factor\n* table.  The tables are defined for the maximum length transform and a subset\n* of the coefficients are used in shorter transforms.\n* \n*/\n\nvoid arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1) \n{\n   uint32_t    L  = S->fftLen;\n   float32_t * pCol1, * pCol2, * pMid1, * pMid2;\n   float32_t * p2 = p1 + L;\n   const float32_t * tw = (float32_t *) S->pTwiddle;\n   float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;\n   float32_t m0, m1, m2, m3;\n   uint32_t l;\n\n   pCol1 = p1;\n   pCol2 = p2;\n\n   //    Define new length\n   L >>= 1;\n   //    Initialize mid pointers\n   pMid1 = p1 + L;\n   pMid2 = p2 + L;\n\n   // do two dot Fourier transform\n   for ( l = L >> 2; l > 0; l-- ) \n   {\n      t1[0] = p1[0];\n      t1[1] = p1[1];\n      t1[2] = p1[2];\n      t1[3] = p1[3];\n\n      t2[0] = p2[0];\n      t2[1] = p2[1];\n      t2[2] = p2[2];\n      t2[3] = p2[3];\n\n      t3[0] = pMid1[0];\n      t3[1] = pMid1[1];\n      t3[2] = pMid1[2];\n      t3[3] = pMid1[3];\n\n      t4[0] = pMid2[0];\n      t4[1] = pMid2[1];\n      t4[2] = pMid2[2];\n      t4[3] = pMid2[3];\n\n      *p1++ = t1[0] + t2[0];\n      *p1++ = t1[1] + t2[1];\n      *p1++ = t1[2] + t2[2];\n      *p1++ = t1[3] + t2[3];    // col 1\n\n      t2[0] = t1[0] - t2[0];\n      t2[1] = t1[1] - t2[1];\n      t2[2] = t1[2] - t2[2];\n      t2[3] = t1[3] - t2[3];    // for col 2\n\n      *pMid1++ = t3[0] + t4[0];\n      *pMid1++ = t3[1] + t4[1];\n      *pMid1++ = t3[2] + t4[2];\n      *pMid1++ = t3[3] + t4[3]; // col 1\n\n      t4[0] = t4[0] - t3[0];\n      t4[1] = t4[1] - t3[1];\n      t4[2] = t4[2] - t3[2];\n      t4[3] = t4[3] - t3[3];    // for col 2\n\n      twR = *tw++;\n      twI = *tw++;\n\n      // multiply by twiddle factors\n      m0 = t2[0] * twR;\n      m1 = t2[1] * twI;\n      m2 = t2[1] * twR;\n      m3 = t2[0] * twI;\n      \n      // R  =  R  *  Tr - I * Ti\n      *p2++ = m0 + m1;\n      // I  =  I  *  Tr + R * Ti\n      *p2++ = m2 - m3;\n      \n      // use vertical symmetry\n\t  //  0.9988 - 0.0491i <==> -0.0491 - 0.9988i\n      m0 = t4[0] * twI;\n      m1 = t4[1] * twR;\n      m2 = t4[1] * twI;\n      m3 = t4[0] * twR;\n      \n      *pMid2++ = m0 - m1;\n      *pMid2++ = m2 + m3;\n\n      twR = *tw++;\n      twI = *tw++;\n      \n      m0 = t2[2] * twR;\n      m1 = t2[3] * twI;\n      m2 = t2[3] * twR;\n      m3 = t2[2] * twI;\n      \n      *p2++ = m0 + m1;\n      *p2++ = m2 - m3;\n         \n      m0 = t4[2] * twI;\n      m1 = t4[3] * twR;\n      m2 = t4[3] * twI;\n      m3 = t4[2] * twR;\n      \n      *pMid2++ = m0 - m1;\n      *pMid2++ = m2 + m3;\n   }\n\n   // first col\n   arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);\n   // second col\n   arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);\n   \n}\n\nvoid arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1) \n{\n   uint32_t    L  = S->fftLen >> 1;\n   float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;\n\tconst float32_t *tw2, *tw3, *tw4;\n   float32_t * p2 = p1 + L;\n   float32_t * p3 = p2 + L;\n   float32_t * p4 = p3 + L;\n   float32_t t2[4], t3[4], t4[4], twR, twI;\n   float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;\n   float32_t m0, m1, m2, m3;\n   uint32_t l, twMod2, twMod3, twMod4;\n\n   pCol1 = p1;         // points to real values by default\n   pCol2 = p2;\n   pCol3 = p3;\n   pCol4 = p4;\n   pEnd1 = p2 - 1;     // points to imaginary values by default\n   pEnd2 = p3 - 1;\n   pEnd3 = p4 - 1;\n   pEnd4 = pEnd3 + L;\n   \n   tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;\n   \n   L >>= 1;\n\n   // do four dot Fourier transform\n\n   twMod2 = 2;\n   twMod3 = 4;\n   twMod4 = 6;\n\n   // TOP\n   p1ap3_0 = p1[0] + p3[0];\n   p1sp3_0 = p1[0] - p3[0];\n   p1ap3_1 = p1[1] + p3[1];\n   p1sp3_1 = p1[1] - p3[1];\n\n   // col 2\n   t2[0] = p1sp3_0 + p2[1] - p4[1];\n   t2[1] = p1sp3_1 - p2[0] + p4[0];\n   // col 3\n   t3[0] = p1ap3_0 - p2[0] - p4[0];\n   t3[1] = p1ap3_1 - p2[1] - p4[1];\n   // col 4\n   t4[0] = p1sp3_0 - p2[1] + p4[1];\n   t4[1] = p1sp3_1 + p2[0] - p4[0];\n   // col 1\n   *p1++ = p1ap3_0 + p2[0] + p4[0];\n   *p1++ = p1ap3_1 + p2[1] + p4[1];\n\n   // Twiddle factors are ones\n   *p2++ = t2[0];\n   *p2++ = t2[1];\n   *p3++ = t3[0];\n   *p3++ = t3[1];\n   *p4++ = t4[0];\n   *p4++ = t4[1];\n   \n   tw2 += twMod2;\n   tw3 += twMod3;\n   tw4 += twMod4;\n   \n   for (l = (L - 2) >> 1; l > 0; l-- ) \n   {\n\n      // TOP\n      p1ap3_0 = p1[0] + p3[0];\n      p1sp3_0 = p1[0] - p3[0];\n      p1ap3_1 = p1[1] + p3[1];\n      p1sp3_1 = p1[1] - p3[1];\n      // col 2\n      t2[0] = p1sp3_0 + p2[1] - p4[1];\n      t2[1] = p1sp3_1 - p2[0] + p4[0];\n      // col 3\n      t3[0] = p1ap3_0 - p2[0] - p4[0];\n      t3[1] = p1ap3_1 - p2[1] - p4[1];\n      // col 4\n      t4[0] = p1sp3_0 - p2[1] + p4[1];\n      t4[1] = p1sp3_1 + p2[0] - p4[0];\n      // col 1 - top\n      *p1++ = p1ap3_0 + p2[0] + p4[0];\n      *p1++ = p1ap3_1 + p2[1] + p4[1];\n\n      // BOTTOM\n      p1ap3_1 = pEnd1[-1] + pEnd3[-1];\n      p1sp3_1 = pEnd1[-1] - pEnd3[-1];\n      p1ap3_0 = pEnd1[0] + pEnd3[0];\n      p1sp3_0 = pEnd1[0] - pEnd3[0];\n      // col 2\n      t2[2] = pEnd2[0]  - pEnd4[0] + p1sp3_1;\n      t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];\n      // col 3\n      t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];\n      t3[3] = p1ap3_0 - pEnd2[0]  - pEnd4[0];\n      // col 4\n      t4[2] = pEnd2[0]  - pEnd4[0]  - p1sp3_1;\n      t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;\n      // col 1 - Bottom\n      *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];\n      *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];\n\n      // COL 2\n      // read twiddle factors\n      twR = *tw2++;\n      twI = *tw2++;\n      // multiply by twiddle factors\n      //  let    Z1 = a + i(b),   Z2 = c + i(d)\n      //   =>  Z1 * Z2  =  (a*c - b*d) + i(b*c + a*d)\n      // Top\n      m0 = t2[0] * twR;\n      m1 = t2[1] * twI;\n      m2 = t2[1] * twR;\n      m3 = t2[0] * twI;\n      \n      *p2++ = m0 + m1;\n      *p2++ = m2 - m3;\n      // use vertical symmetry col 2\n      // 0.9997 - 0.0245i  <==>  0.0245 - 0.9997i\n      // Bottom\n      m0 = t2[3] * twI;\n      m1 = t2[2] * twR;\n      m2 = t2[2] * twI;\n      m3 = t2[3] * twR;\n      \n      *pEnd2-- = m0 - m1;\n      *pEnd2-- = m2 + m3;\n\n      // COL 3\n      twR = tw3[0];\n      twI = tw3[1];\n      tw3 += twMod3;\n      // Top\n      m0 = t3[0] * twR;\n      m1 = t3[1] * twI;\n      m2 = t3[1] * twR;\n      m3 = t3[0] * twI;\n      \n      *p3++ = m0 + m1;\n      *p3++ = m2 - m3;\n      // use vertical symmetry col 3\n      // 0.9988 - 0.0491i  <==>  -0.9988 - 0.0491i\n      // Bottom\n      m0 = -t3[3] * twR;\n      m1 = t3[2] * twI;\n      m2 = t3[2] * twR;\n      m3 = t3[3] * twI;\n      \n      *pEnd3-- = m0 - m1;\n      *pEnd3-- = m3 - m2;\n      \n      // COL 4\n      twR = tw4[0];\n      twI = tw4[1];\n      tw4 += twMod4;\n      // Top\n      m0 = t4[0] * twR;\n      m1 = t4[1] * twI;\n      m2 = t4[1] * twR;\n      m3 = t4[0] * twI;\n      \n      *p4++ = m0 + m1;\n      *p4++ = m2 - m3;\n      // use vertical symmetry col 4\n      // 0.9973 - 0.0736i  <==>  -0.0736 + 0.9973i\n      // Bottom\n      m0 = t4[3] * twI;\n      m1 = t4[2] * twR;\n      m2 = t4[2] * twI;\n      m3 = t4[3] * twR;\n      \n      *pEnd4-- = m0 - m1;\n      *pEnd4-- = m2 + m3;\n   }\n\n   //MIDDLE\n   // Twiddle factors are \n   //  1.0000  0.7071-0.7071i  -1.0000i  -0.7071-0.7071i\n   p1ap3_0 = p1[0] + p3[0];\n   p1sp3_0 = p1[0] - p3[0];\n   p1ap3_1 = p1[1] + p3[1];\n   p1sp3_1 = p1[1] - p3[1];\n\n   // col 2\n   t2[0] = p1sp3_0 + p2[1] - p4[1];\n   t2[1] = p1sp3_1 - p2[0] + p4[0];\n   // col 3\n   t3[0] = p1ap3_0 - p2[0] - p4[0];\n   t3[1] = p1ap3_1 - p2[1] - p4[1];\n   // col 4\n   t4[0] = p1sp3_0 - p2[1] + p4[1];\n   t4[1] = p1sp3_1 + p2[0] - p4[0];\n   // col 1 - Top\n   *p1++ = p1ap3_0 + p2[0] + p4[0];\n   *p1++ = p1ap3_1 + p2[1] + p4[1];\n   \n   // COL 2\n   twR = tw2[0];\n   twI = tw2[1];\n   \n   m0 = t2[0] * twR;\n   m1 = t2[1] * twI;\n   m2 = t2[1] * twR;\n   m3 = t2[0] * twI;\n   \n   *p2++ = m0 + m1;\n   *p2++ = m2 - m3;\n      // COL 3\n   twR = tw3[0];\n   twI = tw3[1];\n   \n   m0 = t3[0] * twR;\n   m1 = t3[1] * twI;\n   m2 = t3[1] * twR;\n   m3 = t3[0] * twI;\n   \n   *p3++ = m0 + m1;\n   *p3++ = m2 - m3;\n   // COL 4\n   twR = tw4[0];\n   twI = tw4[1];\n   \n   m0 = t4[0] * twR;\n   m1 = t4[1] * twI;\n   m2 = t4[1] * twR;\n   m3 = t4[0] * twI;\n   \n   *p4++ = m0 + m1;\n   *p4++ = m2 - m3;\n\n   // first col\n   arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);\n   // second col\n   arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);\n   // third col\n   arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);\n   // fourth col\n   arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);\n\n}\n\n/**\n* @addtogroup ComplexFFT   \n* @{   \n*/\n\n/**   \n* @details   \n* @brief       Processing function for the floating-point complex FFT.\n* @param[in]      *S    points to an instance of the floating-point CFFT structure.  \n* @param[in, out] *p1   points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  \n* @return none.  \n*/\n\nvoid arm_cfft_f32( \n   const arm_cfft_instance_f32 * S, \n   float32_t * p1,\n   uint8_t ifftFlag,\n   uint8_t bitReverseFlag)\n{\n\n   uint32_t  L = S->fftLen, l;\n   float32_t invL, * pSrc;\n\n  if(ifftFlag == 1u)\n  {\n\t  /*  Conjugate input data  */\n\t  pSrc = p1 + 1;\n\t  for(l=0; lpTwiddle, 1);\n\t\t\t break;\n\t\t}  \n\n\tif( bitReverseFlag )\n\t\tarm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);\n\n  if(ifftFlag == 1u)\n  {\n\t  invL = 1.0f/(float32_t)L;\n\t  /*  Conjugate and scale output data */\n\t  pSrc = p1;\n\t  for(l=0; l2*fftLen. Processing occurs in-place.  \n* @return none.\n*/\n\nvoid arm_cfft_radix2_f32(\nconst arm_cfft_radix2_instance_f32 * S,\nfloat32_t * pSrc)\n{\n\n   if(S->ifftFlag == 1u)\n   {\n      /*  Complex IFFT radix-2  */\n      arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,\n      S->twidCoefModifier, S->onebyfftLen);\n   }\n   else\n   {\n      /*  Complex FFT radix-2  */\n      arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,\n      S->twidCoefModifier);\n   }\n\n   if(S->bitReverseFlag == 1u)\n   {\n      /*  Bit Reversal */\n      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n   }\n\n}\n\n\n/**    \n* @} end of ComplexFFT group    \n*/\n\n\n\n/* ----------------------------------------------------------------------    \n** Internal helper function used by the FFTs    \n** ------------------------------------------------------------------- */\n\n/*    \n* @brief  Core function for the floating-point CFFT butterfly process.   \n* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   \n* @param[in]      fftLen           length of the FFT.   \n* @param[in]      *pCoef           points to the twiddle coefficient buffer.   \n* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n* @return none.   \n*/\n\nvoid arm_radix2_butterfly_f32(\nfloat32_t * pSrc,\nuint32_t fftLen,\nfloat32_t * pCoef,\nuint16_t twidCoefModifier)\n{\n\n   uint32_t i, j, k, l;\n   uint32_t n1, n2, ia;\n   float32_t xt, yt, cosVal, sinVal;\n   float32_t p0, p1, p2, p3;\n   float32_t a0, a1;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n   /*  Initializations for the first stage */\n   n2 = fftLen >> 1;\n   ia = 0;\n   i = 0;\n\n   // loop for groups \n   for (k = n2; k > 0; k--)\n   {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n\n      /*  Twiddle coefficients index modifier */\n      ia += twidCoefModifier;\n\n      /*  index calculation for the input as, */\n      /*  pSrc[i + 0], pSrc[i + fftLen/1] */\n      l = i + n2;\n\n      /*  Butterfly implementation */\n      a0 = pSrc[2 * i] + pSrc[2 * l];\n      xt = pSrc[2 * i] - pSrc[2 * l];\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n      \n      p0 = xt * cosVal;\n      p1 = yt * sinVal;\n      p2 = yt * cosVal;\n      p3 = xt * sinVal;  \n      \n      pSrc[2 * i]     = a0;   \n      pSrc[2 * i + 1] = a1;       \n      \n      pSrc[2 * l]     = p0 + p1;\n      pSrc[2 * l + 1] = p2 - p3;\n      \n      i++;\n   }                             // groups loop end \n\n   twidCoefModifier <<= 1u;\n\n   // loop for stage \n   for (k = n2; k > 2; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      j = 0;\n      do\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia += twidCoefModifier;\n\n         // loop for butterfly \n         i = j;\n         do\n         {\n            l = i + n2;\n            a0 = pSrc[2 * i] + pSrc[2 * l];\n            xt = pSrc[2 * i] - pSrc[2 * l];\n\n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n            \n            p0 = xt * cosVal;\n            p1 = yt * sinVal;\n            p2 = yt * cosVal;\n            p3 = xt * sinVal;  \n            \n            pSrc[2 * i] = a0;   \n            pSrc[2 * i + 1] = a1;       \n            \n            pSrc[2 * l]     = p0 + p1;\n            pSrc[2 * l + 1] = p2 - p3;\n            \n            i += n1;\n         } while( i < fftLen );                        // butterfly loop end \n         j++;\n      } while( j < n2);                          // groups loop end \n      twidCoefModifier <<= 1u;\n   }                             // stages loop end \n\n   // loop for butterfly \n   for (i = 0; i < fftLen; i += 2)\n   {\n      a0 = pSrc[2 * i] + pSrc[2 * i + 2];\n      xt = pSrc[2 * i] - pSrc[2 * i + 2];\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];\n      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];\n      \n      pSrc[2 * i] = a0;   \n      pSrc[2 * i + 1] = a1;\n      pSrc[2 * i + 2] = xt;\n      pSrc[2 * i + 3] = yt;\n   }                             // groups loop end \n\n#else\n \n   n2 = fftLen;\n\n   // loop for stage \n   for (k = fftLen; k > 1; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      j = 0;\n      do\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia += twidCoefModifier;\n\n         // loop for butterfly \n         i = j;\n         do\n         {\n            l = i + n2;\n            a0 = pSrc[2 * i] + pSrc[2 * l];\n            xt = pSrc[2 * i] - pSrc[2 * l];\n\n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n            \n            p0 = xt * cosVal;\n            p1 = yt * sinVal;\n            p2 = yt * cosVal;\n            p3 = xt * sinVal;  \n            \n            pSrc[2 * i] = a0;   \n            pSrc[2 * i + 1] = a1;       \n            \n            pSrc[2 * l]     = p0 + p1;\n            pSrc[2 * l + 1] = p2 - p3;\n            \n            i += n1;\n         } while(i < fftLen);\n         j++;\n      } while(j < n2);\n      twidCoefModifier <<= 1u;\n   }\n\n#endif //    #ifndef ARM_MATH_CM0_FAMILY\n\n}\n\n\nvoid arm_radix2_butterfly_inverse_f32(\nfloat32_t * pSrc,\nuint32_t fftLen,\nfloat32_t * pCoef,\nuint16_t twidCoefModifier,\nfloat32_t onebyfftLen)\n{\n\n   uint32_t i, j, k, l;\n   uint32_t n1, n2, ia;\n   float32_t xt, yt, cosVal, sinVal;\n   float32_t p0, p1, p2, p3;\n   float32_t a0, a1;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n   n2 = fftLen >> 1;\n   ia = 0;\n\n   // loop for groups \n   for (i = 0; i < n2; i++)\n   {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n      ia += twidCoefModifier;\n\n      l = i + n2;\n      a0 = pSrc[2 * i] + pSrc[2 * l];\n      xt = pSrc[2 * i] - pSrc[2 * l];\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n      \n      p0 = xt * cosVal;\n      p1 = yt * sinVal;\n      p2 = yt * cosVal;\n      p3 = xt * sinVal;  \n      \n      pSrc[2 * i] = a0;   \n      pSrc[2 * i + 1] = a1;       \n      \n      pSrc[2 * l]     = p0 - p1;\n      pSrc[2 * l + 1] = p2 + p3;  \n   }                             // groups loop end \n\n   twidCoefModifier <<= 1u;\n\n   // loop for stage \n   for (k = fftLen / 2; k > 2; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      j = 0;\n      do\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia += twidCoefModifier;\n\n         // loop for butterfly \n         i = j;\n         do\n         {\n            l = i + n2;\n            a0 = pSrc[2 * i] + pSrc[2 * l];\n            xt = pSrc[2 * i] - pSrc[2 * l];\n\n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n            \n            p0 = xt * cosVal;\n            p1 = yt * sinVal;\n            p2 = yt * cosVal;\n            p3 = xt * sinVal;  \n            \n            pSrc[2 * i] = a0;   \n            pSrc[2 * i + 1] = a1;       \n            \n            pSrc[2 * l]     = p0 - p1;\n            pSrc[2 * l + 1] = p2 + p3; \n\n            i += n1;\n         } while( i < fftLen );                 // butterfly loop end \n         j++;\n      } while(j < n2);                      // groups loop end \n\n      twidCoefModifier <<= 1u;\n   }                             // stages loop end \n\n   // loop for butterfly \n   for (i = 0; i < fftLen; i += 2)\n   {   \n      a0 = pSrc[2 * i] + pSrc[2 * i + 2];\n      xt = pSrc[2 * i] - pSrc[2 * i + 2];\n      \n      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];\n      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];\n      \n      p0 = a0 * onebyfftLen;\n      p2 = xt * onebyfftLen;\n      p1 = a1 * onebyfftLen;\n      p3 = yt * onebyfftLen; \n      \n      pSrc[2 * i] = p0;\n      pSrc[2 * i + 1] = p1;  \n      pSrc[2 * i + 2] = p2;       \n      pSrc[2 * i + 3] = p3;\n   }                             // butterfly loop end \n\n#else\n\n   n2 = fftLen;\n\n   // loop for stage \n   for (k = fftLen; k > 2; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      j = 0;\n      do\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia = ia + twidCoefModifier;\n\n         // loop for butterfly \n         i = j;\n         do\n         {\n            l = i + n2;\n            a0 = pSrc[2 * i] + pSrc[2 * l];\n            xt = pSrc[2 * i] - pSrc[2 * l];\n\n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n            \n            p0 = xt * cosVal;\n            p1 = yt * sinVal;\n            p2 = yt * cosVal;\n            p3 = xt * sinVal;  \n            \n            pSrc[2 * i] = a0;   \n            pSrc[2 * i + 1] = a1;       \n            \n            pSrc[2 * l]     = p0 - p1;\n            pSrc[2 * l + 1] = p2 + p3;  \n            \n            i += n1;\n         } while( i < fftLen );                    // butterfly loop end \n         j++;\n      } while( j < n2 );                      // groups loop end \n\n      twidCoefModifier = twidCoefModifier << 1u;\n   }                             // stages loop end \n\n   n1 = n2;\n   n2 = n2 >> 1;\n\n   // loop for butterfly \n   for (i = 0; i < fftLen; i += n1)\n   {\n      l = i + n2;\n      \n      a0 = pSrc[2 * i] + pSrc[2 * l];\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      \n      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      \n      p0 = a0 * onebyfftLen;\n      p2 = xt * onebyfftLen;\n      p1 = a1 * onebyfftLen;\n      p3 = yt * onebyfftLen; \n      \n      pSrc[2 * i] = p0;\n      pSrc[2u * l] = p2;\n     \n      pSrc[2 * i + 1] = p1;    \n      pSrc[2u * l + 1u] = p3;\n   }                             // butterfly loop end \n\n#endif //      #ifndef ARM_MATH_CM0_FAMILY\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t    arm_cfft_radix4_init_f32.c   \n*   \n* Description:\tRadix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**   \n * @ingroup groupTransforms   \n */\n\n/**   \n * @addtogroup ComplexFFT   \n * @{   \n */\n\n/**   \n* @brief  Initialization function for the floating-point CFFT/CIFFT.  \n* @deprecated Do not use this function.  It has been superceded by \\ref arm_cfft_f32 and will be removed\n* in the future.\n* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  \n* @param[in]     fftLen         length of the FFT.  \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  \n*   \n* \\par Description:  \n* \\par   \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.   \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  \n* \\par   \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par   \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   \n* \\par   \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   \n*/\narm_status arm_cfft_radix2_init_f32(\n  arm_cfft_radix2_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (float32_t *) twiddleCoef;\n\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (S->fftLen)\n  {\n\n  case 4096u:\n    /*  Initializations of structure parameters for 4096 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.000244140625;\n    break;\n\n  case 2048u:\n    /*  Initializations of structure parameters for 2048 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 2u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 2u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.00048828125;\n    break;\n\n  case 1024u:\n    /*  Initializations of structure parameters for 1024 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 4u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 4u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.0009765625f;\n    break;\n\n  case 512u:\n    /*  Initializations of structure parameters for 512 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 8u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 8u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.001953125;\n    break;\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n    S->onebyfftLen = 0.00390625f;\n    break;\n\n  case 128u:\n    /*  Initializations of structure parameters for 128 point FFT */\n    S->twidCoefModifier = 32u;\n    S->bitRevFactor = 32u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];\n    S->onebyfftLen = 0.0078125;\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n    S->onebyfftLen = 0.015625f;\n    break;\n\n  case 32u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 128u;\n    S->bitRevFactor = 128u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];\n    S->onebyfftLen = 0.03125;\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n    S->onebyfftLen = 0.0625f;\n    break;\n\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**   \n * @} end of ComplexFFT group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1   \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix2_init_q15.c    \n*    \n* Description:\tRadix-2 Decimation in Frequency Q15 FFT & IFFT initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n/**   \n* @brief Initialization function for the Q15 CFFT/CIFFT.   \n* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   \n* @param[in]     fftLen         length of the FFT.   \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  \n*   \n* \\par Description:  \n* \\par   \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.   \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  \n* \\par   \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par   \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   \n* \\par   \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   \n*/\n\narm_status arm_cfft_radix2_init_q15(\n  arm_cfft_radix2_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (q15_t *) twiddleCoefQ15;\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (S->fftLen)\n  {\n  case 4096u:\n    /*  Initializations of structure parameters for 4096 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n\n    break;\n\n  case 2048u:\n    /*  Initializations of structure parameters for 2048 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 2u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 2u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];\n\n    break;\n\n  case 1024u:\n    /*  Initializations of structure parameters for 1024 point FFT */\n    S->twidCoefModifier = 4u;\n    S->bitRevFactor = 4u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n\n    break;\n\n  case 512u:\n    /*  Initializations of structure parameters for 512 point FFT */\n    S->twidCoefModifier = 8u;\n    S->bitRevFactor = 8u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];\n\n    break;\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n\n    break;\n\n  case 128u:\n    /*  Initializations of structure parameters for 128 point FFT */\n    S->twidCoefModifier = 32u;\n    S->bitRevFactor = 32u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];\n\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n\n    break;\n\n  case 32u:\n    /*  Initializations of structure parameters for 32 point FFT */\n    S->twidCoefModifier = 128u;\n    S->bitRevFactor = 128u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];\n\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n\n    break;\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013\n* $Revision: \tV1.4.1  \n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t    arm_cfft_radix2_init_q31.c   \n*   \n* Description:\tRadix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function   \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**   \n * @ingroup groupTransforms   \n */\n\n/**   \n * @addtogroup ComplexFFT   \n * @{   \n */\n\n\n/**    \n*    \n* @brief  Initialization function for the Q31 CFFT/CIFFT.   \n* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   \n* @param[in]     fftLen         length of the FFT.  \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  \n*   \n* \\par Description:  \n* \\par   \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.   \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  \n* \\par   \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par   \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   \n* \\par   \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   \n*/\n\narm_status arm_cfft_radix2_init_q31(\n  arm_cfft_radix2_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (q31_t *) twiddleCoefQ31;\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of Instance structure depending on the FFT length */\n  switch (S->fftLen)\n  {\n    /*  Initializations of structure parameters for 4096 point FFT */\n  case 4096u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n    break;\n\n    /*  Initializations of structure parameters for 2048 point FFT */\n  case 2048u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 2u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 2u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];\n    break;\n\n    /*  Initializations of structure parameters for 1024 point FFT */\n  case 1024u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 4u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 4u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n    break;\n\n    /*  Initializations of structure parameters for 512 point FFT */\n  case 512u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 8u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 8u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];\n    break;\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n    break;\n\n  case 128u:\n    /*  Initializations of structure parameters for 128 point FFT */\n    S->twidCoefModifier = 32u;\n    S->bitRevFactor = 32u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n    break;\n\n  case 32u:\n    /*  Initializations of structure parameters for 32 point FFT */\n    S->twidCoefModifier = 128u;\n    S->bitRevFactor = 128u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n    break;\n\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**   \n * @} end of ComplexFFT group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t    arm_cfft_radix2_q15.c   \n*   \n* Description:\tRadix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   \n*   \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid arm_radix2_butterfly_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pCoef,\n  uint16_t twidCoefModifier);\n\nvoid arm_radix2_butterfly_inverse_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pCoef,\n  uint16_t twidCoefModifier);\n\t\nvoid arm_bitreversal_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  uint16_t bitRevFactor,\n  uint16_t * pBitRevTab);\n\n/**   \n * @ingroup groupTransforms   \n */\n\n/**   \n * @addtogroup ComplexFFT   \n * @{   \n */\n\n/**   \n * @details   \n * @brief Processing function for the fixed-point CFFT/CIFFT.  \n * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  \n * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  \n * @return none.  \n */\n\nvoid arm_cfft_radix2_q15(\n  const arm_cfft_radix2_instance_q15 * S,\n  q15_t * pSrc)\n{\n\n  if(S->ifftFlag == 1u)\n  {\n    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,\n                                     S->pTwiddle, S->twidCoefModifier);\n  }\n  else\n  {\n    arm_radix2_butterfly_q15(pSrc, S->fftLen,\n                             S->pTwiddle, S->twidCoefModifier);\n  }\n\n  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n}\n\n/**   \n * @} end of ComplexFFT group   \n */\n\nvoid arm_radix2_butterfly_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pCoef,\n  uint16_t twidCoefModifier)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  unsigned i, j, k, l;\n  unsigned n1, n2, ia;\n  q15_t in;\n  q31_t T, S, R;\n  q31_t coeff, out1, out2;\n\n  //N = fftLen; \n  n2 = fftLen;\n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (i = 0; i < n2; i++)\n  {\n    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n    ia = ia + twidCoefModifier;\n\n    l = i + n2;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __SMUAD(coeff, R) >> 16;\n    out2 = __SMUSDX(coeff, R);\n\n#else\n\n    out1 = __SMUSDX(R, coeff) >> 16u;\n    out2 = __SMUAD(coeff, R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    i++;\n    l++;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __SMUAD(coeff, R) >> 16;\n    out2 = __SMUSDX(coeff, R);\n\n#else\n\n    out1 = __SMUSDX(R, coeff) >> 16u;\n    out2 = __SMUAD(coeff, R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n  // loop for stage \n  for (k = fftLen / 2; k > 2; k = k >> 1)\n  {\n    n1 = n2;\n    n2 = n2 >> 1;\n    ia = 0;\n\n    // loop for groups \n    for (j = 0; j < n2; j++)\n    {\n      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n      ia = ia + twidCoefModifier;\n\n      // loop for butterfly \n      for (i = j; i < fftLen; i += n1)\n      {\n        l = i + n2;\n\n        T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n        S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n        R = __QSUB16(T, S);\n\n        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUAD(coeff, R) >> 16;\n        out2 = __SMUSDX(coeff, R);\n\n#else\n\n        out1 = __SMUSDX(R, coeff) >> 16u;\n        out2 = __SMUAD(coeff, R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n        _SIMD32_OFFSET(pSrc + (2u * l)) =\n          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        i += n1;\n\n        l = i + n2;\n\n        T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n        S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n        R = __QSUB16(T, S);\n\n        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUAD(coeff, R) >> 16;\n        out2 = __SMUSDX(coeff, R);\n\n#else\n\n        out1 = __SMUSDX(R, coeff) >> 16u;\n        out2 = __SMUAD(coeff, R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n        _SIMD32_OFFSET(pSrc + (2u * l)) =\n          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n      }                         // butterfly loop end \n\n    }                           // groups loop end \n\n    twidCoefModifier = twidCoefModifier << 1u;\n  }                             // stages loop end \n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n  ia = ia + twidCoefModifier;\n\n  // loop for butterfly \n  for (i = 0; i < fftLen; i += n1)\n  {\n    l = i + n2;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) = R;\n\n    i += n1;\n    l = i + n2;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) = R;\n\n  }                             // groups loop end \n\n\n#else\n\n  unsigned i, j, k, l;\n  unsigned n1, n2, ia;\n  q15_t xt, yt, cosVal, sinVal;\n\n\n  //N = fftLen; \n  n2 = fftLen;\n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (j = 0; j < n2; j++)\n  {\n    cosVal = pCoef[ia * 2];\n    sinVal = pCoef[(ia * 2) + 1];\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    for (i = j; i < fftLen; i += n1)\n    {\n      l = i + n2;\n      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);\n      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;\n\n      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);\n      pSrc[2 * i + 1] =\n        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;\n\n      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +\n                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));\n\n      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -\n                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));\n\n    }                           // butterfly loop end \n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n  // loop for stage \n  for (k = fftLen / 2; k > 2; k = k >> 1)\n  {\n    n1 = n2;\n    n2 = n2 >> 1;\n    ia = 0;\n\n    // loop for groups \n    for (j = 0; j < n2; j++)\n    {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n      ia = ia + twidCoefModifier;\n\n      // loop for butterfly \n      for (i = j; i < fftLen; i += n1)\n      {\n        l = i + n2;\n        xt = pSrc[2 * i] - pSrc[2 * l];\n        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;\n\n        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;\n\n        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +\n                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));\n\n        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -\n                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));\n\n      }                         // butterfly loop end \n\n    }                           // groups loop end \n\n    twidCoefModifier = twidCoefModifier << 1u;\n  }                             // stages loop end \n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (j = 0; j < n2; j++)\n  {\n    cosVal = pCoef[ia * 2];\n    sinVal = pCoef[(ia * 2) + 1];\n\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    for (i = j; i < fftLen; i += n1)\n    {\n      l = i + n2;\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n      pSrc[2u * l] = xt;\n\n      pSrc[2u * l + 1u] = yt;\n\n    }                           // butterfly loop end \n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n#endif //             #ifndef ARM_MATH_CM0_FAMILY\n\n}\n\n\nvoid arm_radix2_butterfly_inverse_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pCoef,\n  uint16_t twidCoefModifier)\n{\n#ifndef ARM_MATH_CM0_FAMILY\n\n  unsigned i, j, k, l;\n  unsigned n1, n2, ia;\n  q15_t in;\n  q31_t T, S, R;\n  q31_t coeff, out1, out2;\n\n  //N = fftLen; \n  n2 = fftLen;\n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (i = 0; i < n2; i++)\n  {\n    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n    ia = ia + twidCoefModifier;\n\n    l = i + n2;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __SMUSD(coeff, R) >> 16;\n    out2 = __SMUADX(coeff, R);\n#else\n\n    out1 = __SMUADX(R, coeff) >> 16u;\n    out2 = __SMUSD(__QSUB(0, coeff), R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    i++;\n    l++;\n\n    T = _SIMD32_OFFSET(pSrc + (2 * i));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    S = _SIMD32_OFFSET(pSrc + (2 * l));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    R = __QSUB16(T, S);\n\n    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    out1 = __SMUSD(coeff, R) >> 16;\n    out2 = __SMUADX(coeff, R);\n#else\n\n    out1 = __SMUADX(R, coeff) >> 16u;\n    out2 = __SMUSD(__QSUB(0, coeff), R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n    _SIMD32_OFFSET(pSrc + (2u * l)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n  // loop for stage \n  for (k = fftLen / 2; k > 2; k = k >> 1)\n  {\n    n1 = n2;\n    n2 = n2 >> 1;\n    ia = 0;\n\n    // loop for groups \n    for (j = 0; j < n2; j++)\n    {\n      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n      ia = ia + twidCoefModifier;\n\n      // loop for butterfly \n      for (i = j; i < fftLen; i += n1)\n      {\n        l = i + n2;\n\n        T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n        S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n        R = __QSUB16(T, S);\n\n        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUSD(coeff, R) >> 16;\n        out2 = __SMUADX(coeff, R);\n\n#else\n\n        out1 = __SMUADX(R, coeff) >> 16u;\n        out2 = __SMUSD(__QSUB(0, coeff), R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n        _SIMD32_OFFSET(pSrc + (2u * l)) =\n          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        i += n1;\n\n        l = i + n2;\n\n        T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n        S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n        R = __QSUB16(T, S);\n\n        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUSD(coeff, R) >> 16;\n        out2 = __SMUADX(coeff, R);\n#else\n\n        out1 = __SMUADX(R, coeff) >> 16u;\n        out2 = __SMUSD(__QSUB(0, coeff), R);\n\n#endif //     #ifndef ARM_MATH_BIG_ENDIAN\n\n        _SIMD32_OFFSET(pSrc + (2u * l)) =\n          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n      }                         // butterfly loop end \n\n    }                           // groups loop end \n\n    twidCoefModifier = twidCoefModifier << 1u;\n  }                             // stages loop end \n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (j = 0; j < n2; j++)\n  {\n    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));\n\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    for (i = j; i < fftLen; i += n1)\n    {\n      l = i + n2;\n\n      T = _SIMD32_OFFSET(pSrc + (2 * i));\n\n      S = _SIMD32_OFFSET(pSrc + (2 * l));\n\n      R = __QSUB16(T, S);\n\n      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);\n\n      _SIMD32_OFFSET(pSrc + (2u * l)) = R;\n\n    }                           // butterfly loop end \n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n#else\n\n\n  unsigned i, j, k, l;\n  unsigned n1, n2, ia;\n  q15_t xt, yt, cosVal, sinVal;\n\n  //N = fftLen; \n  n2 = fftLen;\n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  // loop for groups \n  for (j = 0; j < n2; j++)\n  {\n    cosVal = pCoef[ia * 2];\n    sinVal = pCoef[(ia * 2) + 1];\n    ia = ia + twidCoefModifier;\n\n    // loop for butterfly \n    for (i = j; i < fftLen; i += n1)\n    {\n      l = i + n2;\n      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);\n      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;\n\n      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);\n      pSrc[2 * i + 1] =\n        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;\n\n      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -\n                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));\n\n      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +\n                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));\n\n    }                           // butterfly loop end \n\n  }                             // groups loop end \n\n  twidCoefModifier = twidCoefModifier << 1u;\n\n  // loop for stage \n  for (k = fftLen / 2; k > 2; k = k >> 1)\n  {\n    n1 = n2;\n    n2 = n2 >> 1;\n    ia = 0;\n\n    // loop for groups \n    for (j = 0; j < n2; j++)\n    {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n      ia = ia + twidCoefModifier;\n\n      // loop for butterfly \n      for (i = j; i < fftLen; i += n1)\n      {\n        l = i + n2;\n        xt = pSrc[2 * i] - pSrc[2 * l];\n        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;\n\n        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;\n\n        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -\n                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));\n\n        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +\n                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));\n\n      }                         // butterfly loop end \n\n    }                           // groups loop end \n\n    twidCoefModifier = twidCoefModifier << 1u;\n  }                             // stages loop end \n\n  n1 = n2;\n  n2 = n2 >> 1;\n  ia = 0;\n\n  cosVal = pCoef[ia * 2];\n  sinVal = pCoef[(ia * 2) + 1];\n\n  ia = ia + twidCoefModifier;\n\n  // loop for butterfly \n  for (i = 0; i < fftLen; i += n1)\n  {\n    l = i + n2;\n    xt = pSrc[2 * i] - pSrc[2 * l];\n    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n    pSrc[2u * l] = xt;\n\n    pSrc[2u * l + 1u] = yt;\n\n  }                             // groups loop end \n\n\n#endif //             #ifndef ARM_MATH_CM0_FAMILY\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c",
    "content": "/* ----------------------------------------------------------------------   \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.   \n*   \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*   \n* Project: \t    CMSIS DSP Library   \n* Title:\t    arm_cfft_radix2_q31.c   \n*   \n* Description:\tRadix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   \n*   \n*   \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid arm_radix2_butterfly_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pCoef,\n  uint16_t twidCoefModifier);\n\nvoid arm_radix2_butterfly_inverse_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pCoef,\n  uint16_t twidCoefModifier);\n\nvoid arm_bitreversal_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  uint16_t bitRevFactor,\n  uint16_t * pBitRevTab);\n\n/**   \n* @ingroup groupTransforms   \n*/\n\n/**   \n* @addtogroup ComplexFFT   \n* @{   \n*/\n\n/**   \n* @details   \n* @brief Processing function for the fixed-point CFFT/CIFFT.  \n* @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  \n* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  \n* @return none.  \n*/\n\nvoid arm_cfft_radix2_q31(\nconst arm_cfft_radix2_instance_q31 * S,\nq31_t * pSrc)\n{\n\n   if(S->ifftFlag == 1u)\n   {\n      arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,\n      S->pTwiddle, S->twidCoefModifier);\n   }\n   else\n   {\n      arm_radix2_butterfly_q31(pSrc, S->fftLen,\n      S->pTwiddle, S->twidCoefModifier);\n   }\n\n   arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n}\n\n/**   \n* @} end of ComplexFFT group   \n*/\n\nvoid arm_radix2_butterfly_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint16_t twidCoefModifier)\n{\n\n   unsigned i, j, k, l, m;\n   unsigned n1, n2, ia;\n   q31_t xt, yt, cosVal, sinVal;\n   q31_t p0, p1;\n\n   //N = fftLen; \n   n2 = fftLen;\n\n   n1 = n2;\n   n2 = n2 >> 1;\n   ia = 0;\n\n   // loop for groups \n   for (i = 0; i < n2; i++)\n   {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n      ia = ia + twidCoefModifier;\n\n      l = i + n2;\n      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);\n      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;\n      \n      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);\n      pSrc[2 * i + 1] =\n        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;\n\n      mult_32x32_keep32_R(p0, xt, cosVal);\n      mult_32x32_keep32_R(p1, yt, cosVal);\n      multAcc_32x32_keep32_R(p0, yt, sinVal); \n      multSub_32x32_keep32_R(p1, xt, sinVal);\n      \n      pSrc[2u * l] = p0;\n      pSrc[2u * l + 1u] = p1;\n\n   }                             // groups loop end \n\n   twidCoefModifier <<= 1u;\n\n   // loop for stage \n   for (k = fftLen / 2; k > 2; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      for (j = 0; j < n2; j++)\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia = ia + twidCoefModifier;\n\n         // loop for butterfly \n         i = j;\n         m = fftLen / n1;\n         do\n         {\n            l = i + n2;\n            xt = pSrc[2 * i] - pSrc[2 * l];\n            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;\n            \n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;\n\n            mult_32x32_keep32_R(p0, xt, cosVal);\n            mult_32x32_keep32_R(p1, yt, cosVal);\n            multAcc_32x32_keep32_R(p0, yt, sinVal);\n            multSub_32x32_keep32_R(p1, xt, sinVal);\n            \n            pSrc[2u * l] = p0;\n            pSrc[2u * l + 1u] = p1;\n            i += n1;\n            m--;\n         } while( m > 0);                   // butterfly loop end \n\n      }                           // groups loop end \n\n      twidCoefModifier <<= 1u;\n   }                             // stages loop end \n\n   n1 = n2;\n   n2 = n2 >> 1;\n   ia = 0;\n\n   cosVal = pCoef[ia * 2];\n   sinVal = pCoef[(ia * 2) + 1];\n   ia = ia + twidCoefModifier;\n\n   // loop for butterfly \n   for (i = 0; i < fftLen; i += n1)\n   {\n      l = i + n2;\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n      pSrc[2u * l] = xt;\n\n      pSrc[2u * l + 1u] = yt;\n\n      i += n1;\n      l = i + n2;\n\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n      pSrc[2u * l] = xt;\n\n      pSrc[2u * l + 1u] = yt;\n\n   }                             // butterfly loop end \n\n}\n\n\nvoid arm_radix2_butterfly_inverse_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint16_t twidCoefModifier)\n{\n\n   unsigned i, j, k, l;\n   unsigned n1, n2, ia;\n   q31_t xt, yt, cosVal, sinVal;\n   q31_t p0, p1;\n\n   //N = fftLen; \n   n2 = fftLen;\n\n   n1 = n2;\n   n2 = n2 >> 1;\n   ia = 0;\n\n   // loop for groups \n   for (i = 0; i < n2; i++)\n   {\n      cosVal = pCoef[ia * 2];\n      sinVal = pCoef[(ia * 2) + 1];\n      ia = ia + twidCoefModifier;\n\n      l = i + n2;\n      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);\n      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;\n      \n      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);\n      pSrc[2 * i + 1] =\n        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;\n\n      mult_32x32_keep32_R(p0, xt, cosVal);\n      mult_32x32_keep32_R(p1, yt, cosVal);\n      multSub_32x32_keep32_R(p0, yt, sinVal);\n      multAcc_32x32_keep32_R(p1, xt, sinVal);\n      \n      pSrc[2u * l] = p0;\n      pSrc[2u * l + 1u] = p1;\n   }                             // groups loop end \n\n   twidCoefModifier = twidCoefModifier << 1u;\n\n   // loop for stage \n   for (k = fftLen / 2; k > 2; k = k >> 1)\n   {\n      n1 = n2;\n      n2 = n2 >> 1;\n      ia = 0;\n\n      // loop for groups \n      for (j = 0; j < n2; j++)\n      {\n         cosVal = pCoef[ia * 2];\n         sinVal = pCoef[(ia * 2) + 1];\n         ia = ia + twidCoefModifier;\n\n         // loop for butterfly \n         for (i = j; i < fftLen; i += n1)\n         {\n            l = i + n2;\n            xt = pSrc[2 * i] - pSrc[2 * l];\n            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;\n      \n            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;\n\n            mult_32x32_keep32_R(p0, xt, cosVal);\n            mult_32x32_keep32_R(p1, yt, cosVal);\n            multSub_32x32_keep32_R(p0, yt, sinVal);\n            multAcc_32x32_keep32_R(p1, xt, sinVal);\n            \n            pSrc[2u * l] = p0;\n            pSrc[2u * l + 1u] = p1;\n         }                         // butterfly loop end \n\n      }                           // groups loop end \n\n      twidCoefModifier = twidCoefModifier << 1u;\n   }                             // stages loop end \n\n   n1 = n2;\n   n2 = n2 >> 1;\n   ia = 0;\n\n   cosVal = pCoef[ia * 2];\n   sinVal = pCoef[(ia * 2) + 1];\n   ia = ia + twidCoefModifier;\n\n   // loop for butterfly \n   for (i = 0; i < fftLen; i += n1)\n   {\n      l = i + n2;\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n      pSrc[2u * l] = xt;\n\n      pSrc[2u * l + 1u] = yt;\n\n      i += n1;\n      l = i + n2;\n\n      xt = pSrc[2 * i] - pSrc[2 * l];\n      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);\n\n      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];\n      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);\n\n      pSrc[2u * l] = xt;\n\n      pSrc[2u * l + 1u] = yt;\n\n   }                             // butterfly loop end \n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_f32.c    \n*    \n* Description:\tRadix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function    \n*    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nextern void arm_bitreversal_f32(\nfloat32_t * pSrc,\nuint16_t fftSize,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTab);\n\n/**    \n* @ingroup groupTransforms    \n*/\n\n/* ----------------------------------------------------------------------    \n** Internal helper function used by the FFTs    \n** ------------------------------------------------------------------- */\n\n/*    \n* @brief  Core function for the floating-point CFFT butterfly process.   \n* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   \n* @param[in]      fftLen           length of the FFT.   \n* @param[in]      *pCoef           points to the twiddle coefficient buffer.   \n* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n* @return none.   \n*/\n\nvoid arm_radix4_butterfly_f32(\nfloat32_t * pSrc,\nuint16_t fftLen,\nfloat32_t * pCoef,\nuint16_t twidCoefModifier)\n{\n\n   float32_t co1, co2, co3, si1, si2, si3;\n   uint32_t ia1, ia2, ia3;\n   uint32_t i0, i1, i2, i3;\n   uint32_t n1, n2, j, k;\n\n#ifndef ARM_MATH_CM0_FAMILY_FAMILY\n\n   /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;\n   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,\n   Ybminusd;\n   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;\n   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;\n   float32_t *ptr1;\n   float32_t p0,p1,p2,p3,p4,p5;\n   float32_t a0,a1,a2,a3,a4,a5,a6,a7;\n\n   /*  Initializations for the first stage */\n   n2 = fftLen;\n   n1 = n2;\n\n   /* n2 = fftLen/4 */\n   n2 >>= 2u;\n   i0 = 0u;\n   ia1 = 0u;\n\n   j = n2;\n\n   /*  Calculation of first stage */\n   do\n   {\n      /*  index calculation for the input as, */\n      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n      i1 = i0 + n2;\n      i2 = i1 + n2;\n      i3 = i2 + n2;\n\n      xaIn = pSrc[(2u * i0)];\n      yaIn = pSrc[(2u * i0) + 1u];\n\n      xbIn = pSrc[(2u * i1)];\n      ybIn = pSrc[(2u * i1) + 1u];\n\n      xcIn = pSrc[(2u * i2)];\n      ycIn = pSrc[(2u * i2) + 1u];\n\n      xdIn = pSrc[(2u * i3)];\n      ydIn = pSrc[(2u * i3) + 1u];\n\n      /* xa + xc */\n      Xaplusc = xaIn + xcIn;\n      /* xb + xd */\n      Xbplusd = xbIn + xdIn;\n      /* ya + yc */\n      Yaplusc = yaIn + ycIn;\n      /* yb + yd */\n      Ybplusd = ybIn + ydIn;\n\n      /*  index calculation for the coefficients */\n      ia2 = ia1 + ia1;\n      co2 = pCoef[ia2 * 2u];\n      si2 = pCoef[(ia2 * 2u) + 1u];\n\n      /* xa - xc */\n      Xaminusc = xaIn - xcIn;\n      /* xb - xd */\n      Xbminusd = xbIn - xdIn;\n      /* ya - yc */\n      Yaminusc = yaIn - ycIn;\n      /* yb - yd */\n      Ybminusd = ybIn - ydIn;\n\n      /* xa' = xa + xb + xc + xd */\n      pSrc[(2u * i0)] = Xaplusc + Xbplusd;\n      /* ya' = ya + yb + yc + yd */\n      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;\n\n      /* (xa - xc) + (yb - yd) */\n      Xb12C_out = (Xaminusc + Ybminusd);\n      /* (ya - yc) + (xb - xd) */\n      Yb12C_out = (Yaminusc - Xbminusd);\n      /* (xa + xc) - (xb + xd) */\n      Xc12C_out = (Xaplusc - Xbplusd);\n      /* (ya + yc) - (yb + yd) */\n      Yc12C_out = (Yaplusc - Ybplusd);\n      /* (xa - xc) - (yb - yd) */\n      Xd12C_out = (Xaminusc - Ybminusd);\n      /* (ya - yc) + (xb - xd) */\n      Yd12C_out = (Xbminusd + Yaminusc);\n\n      co1 = pCoef[ia1 * 2u];\n      si1 = pCoef[(ia1 * 2u) + 1u];\n\n      /*  index calculation for the coefficients */\n      ia3 = ia2 + ia1;\n      co3 = pCoef[ia3 * 2u];\n      si3 = pCoef[(ia3 * 2u) + 1u];\n\n      Xb12_out = Xb12C_out * co1;\n      Yb12_out = Yb12C_out * co1;\n      Xc12_out = Xc12C_out * co2;\n      Yc12_out = Yc12C_out * co2;\n      Xd12_out = Xd12C_out * co3;\n      Yd12_out = Yd12C_out * co3;\n         \n      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n      //Xb12_out -= Yb12C_out * si1;\n      p0 = Yb12C_out * si1;\n      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n      //Yb12_out += Xb12C_out * si1;\n      p1 = Xb12C_out * si1;\n      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n      //Xc12_out -= Yc12C_out * si2;\n      p2 = Yc12C_out * si2;\n      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n      //Yc12_out += Xc12C_out * si2;\n      p3 = Xc12C_out * si2;\n      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n      //Xd12_out -= Yd12C_out * si3;\n      p4 = Yd12C_out * si3;\n      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n      //Yd12_out += Xd12C_out * si3;\n      p5 = Xd12C_out * si3;\n      \n      Xb12_out += p0;\n      Yb12_out -= p1;\n      Xc12_out += p2;\n      Yc12_out -= p3;\n      Xd12_out += p4;\n      Yd12_out -= p5;\n\n      /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */\n      pSrc[2u * i1] = Xc12_out;\n\n      /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */\n      pSrc[(2u * i1) + 1u] = Yc12_out;\n\n      /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */\n      pSrc[2u * i2] = Xb12_out;\n\n      /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */\n      pSrc[(2u * i2) + 1u] = Yb12_out;\n\n      /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */\n      pSrc[2u * i3] = Xd12_out;\n\n      /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */\n      pSrc[(2u * i3) + 1u] = Yd12_out;\n\n      /*  Twiddle coefficients index modifier */\n      ia1 += twidCoefModifier;\n\n      /*  Updating input index */\n      i0++;\n\n   }\n   while(--j);\n\n   twidCoefModifier <<= 2u;\n\n   /*  Calculation of second stage to excluding last stage */\n   for (k = fftLen >> 2u; k > 4u; k >>= 2u)\n   {\n      /*  Initializations for the first stage */\n      n1 = n2;\n      n2 >>= 2u;\n      ia1 = 0u;\n\n      /*  Calculation of first stage */\n      j = 0;\n      do\n      {\n         /*  index calculation for the coefficients */\n         ia2 = ia1 + ia1;\n         ia3 = ia2 + ia1;\n         co1 = pCoef[ia1 * 2u];\n         si1 = pCoef[(ia1 * 2u) + 1u];\n         co2 = pCoef[ia2 * 2u];\n         si2 = pCoef[(ia2 * 2u) + 1u];\n         co3 = pCoef[ia3 * 2u];\n         si3 = pCoef[(ia3 * 2u) + 1u];\n\n         /*  Twiddle coefficients index modifier */\n         ia1 += twidCoefModifier;\n      \n         i0 = j;\n         do\n         {\n            /*  index calculation for the input as, */\n            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n            i1 = i0 + n2;\n            i2 = i1 + n2;\n            i3 = i2 + n2;\n\n            xaIn = pSrc[(2u * i0)];\n            yaIn = pSrc[(2u * i0) + 1u];\n\n            xbIn = pSrc[(2u * i1)];\n            ybIn = pSrc[(2u * i1) + 1u];\n\n            xcIn = pSrc[(2u * i2)];\n            ycIn = pSrc[(2u * i2) + 1u];\n\n            xdIn = pSrc[(2u * i3)];\n            ydIn = pSrc[(2u * i3) + 1u];\n\n            /* xa - xc */\n            Xaminusc = xaIn - xcIn;\n            /* (xb - xd) */\n            Xbminusd = xbIn - xdIn;\n            /* ya - yc */\n            Yaminusc = yaIn - ycIn;\n            /* (yb - yd) */\n            Ybminusd = ybIn - ydIn;\n\n            /* xa + xc */\n            Xaplusc = xaIn + xcIn;\n            /* xb + xd */\n            Xbplusd = xbIn + xdIn;\n            /* ya + yc */\n            Yaplusc = yaIn + ycIn;\n            /* yb + yd */\n            Ybplusd = ybIn + ydIn;\n\n            /* (xa - xc) + (yb - yd) */\n            Xb12C_out = (Xaminusc + Ybminusd);\n            /* (ya - yc) -  (xb - xd) */\n            Yb12C_out = (Yaminusc - Xbminusd);\n            /* xa + xc -(xb + xd) */\n            Xc12C_out = (Xaplusc - Xbplusd);\n            /* (ya + yc) - (yb + yd) */\n            Yc12C_out = (Yaplusc - Ybplusd);\n            /* (xa - xc) - (yb - yd) */\n            Xd12C_out = (Xaminusc - Ybminusd);\n            /* (ya - yc) +  (xb - xd) */\n            Yd12C_out = (Xbminusd + Yaminusc);\n\n            pSrc[(2u * i0)] = Xaplusc + Xbplusd;\n            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;\n\n            Xb12_out = Xb12C_out * co1;\n            Yb12_out = Yb12C_out * co1;\n            Xc12_out = Xc12C_out * co2;\n            Yc12_out = Yc12C_out * co2;\n            Xd12_out = Xd12C_out * co3;\n            Yd12_out = Yd12C_out * co3;\n         \n            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n            //Xb12_out -= Yb12C_out * si1;\n            p0 = Yb12C_out * si1;\n            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n            //Yb12_out += Xb12C_out * si1;\n            p1 = Xb12C_out * si1;\n            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n            //Xc12_out -= Yc12C_out * si2;\n            p2 = Yc12C_out * si2;\n            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n            //Yc12_out += Xc12C_out * si2;\n            p3 = Xc12C_out * si2;\n            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n            //Xd12_out -= Yd12C_out * si3;\n            p4 = Yd12C_out * si3;\n            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n            //Yd12_out += Xd12C_out * si3;\n            p5 = Xd12C_out * si3;\n            \n            Xb12_out += p0;\n            Yb12_out -= p1;\n            Xc12_out += p2;\n            Yc12_out -= p3;\n            Xd12_out += p4;\n            Yd12_out -= p5;\n\n            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */\n            pSrc[2u * i1] = Xc12_out;\n\n            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */\n            pSrc[(2u * i1) + 1u] = Yc12_out;\n\n            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */\n            pSrc[2u * i2] = Xb12_out;\n\n            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */\n            pSrc[(2u * i2) + 1u] = Yb12_out;\n\n            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */\n            pSrc[2u * i3] = Xd12_out;\n\n            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */\n            pSrc[(2u * i3) + 1u] = Yd12_out;\n\n            i0 += n1;\n         } while(i0 < fftLen);\n         j++;\n      } while(j <= (n2 - 1u));\n      twidCoefModifier <<= 2u;\n   }\n\n   j = fftLen >> 2;\n   ptr1 = &pSrc[0];\n\n   /*  Calculations of last stage */\n   do\n   {\n      xaIn = ptr1[0];\n      yaIn = ptr1[1];\n      xbIn = ptr1[2];\n      ybIn = ptr1[3];\n      xcIn = ptr1[4];\n      ycIn = ptr1[5];\n      xdIn = ptr1[6];\n      ydIn = ptr1[7];\n\n      /* xa + xc */\n      Xaplusc = xaIn + xcIn;\n\n      /* xa - xc */\n      Xaminusc = xaIn - xcIn;\n\n      /* ya + yc */\n      Yaplusc = yaIn + ycIn;\n\n      /* ya - yc */\n      Yaminusc = yaIn - ycIn;\n\n      /* xb + xd */\n      Xbplusd = xbIn + xdIn;\n\n      /* yb + yd */\n      Ybplusd = ybIn + ydIn;\n\n      /* (xb-xd) */\n      Xbminusd = xbIn - xdIn;\n\n      /* (yb-yd) */\n      Ybminusd = ybIn - ydIn;\n\n      /* xa' = xa + xb + xc + xd */\n      a0 = (Xaplusc + Xbplusd);\n      /* ya' = ya + yb + yc + yd */\n      a1 = (Yaplusc + Ybplusd);\n      /* xc' = (xa-xb+xc-xd) */\n      a2 = (Xaplusc - Xbplusd);\n      /* yc' = (ya-yb+yc-yd) */\n      a3 = (Yaplusc - Ybplusd);\n      /* xb' = (xa+yb-xc-yd) */\n      a4 = (Xaminusc + Ybminusd);\n      /* yb' = (ya-xb-yc+xd) */\n      a5 = (Yaminusc - Xbminusd);\n      /* xd' = (xa-yb-xc+yd)) */\n      a6 = (Xaminusc - Ybminusd);\n      /* yd' = (ya+xb-yc-xd) */\n      a7 = (Xbminusd + Yaminusc);\n   \n      ptr1[0] = a0;\n      ptr1[1] = a1;\n      ptr1[2] = a2;\n      ptr1[3] = a3;\n      ptr1[4] = a4;\n      ptr1[5] = a5;\n      ptr1[6] = a6;\n      ptr1[7] = a7;\n\n      /* increment pointer by 8 */\n      ptr1 += 8u;\n   } while(--j);\n\n#else\n\n   float32_t t1, t2, r1, r2, s1, s2;\n\n   /* Run the below code for Cortex-M0 */\n\n   /*  Initializations for the fft calculation */\n   n2 = fftLen;\n   n1 = n2;\n   for (k = fftLen; k > 1u; k >>= 2u)\n   {\n      /*  Initializations for the fft calculation */\n      n1 = n2;\n      n2 >>= 2u;\n      ia1 = 0u;\n\n      /*  FFT Calculation */\n      j = 0;\n      do\n      {\n         /*  index calculation for the coefficients */\n         ia2 = ia1 + ia1;\n         ia3 = ia2 + ia1;\n         co1 = pCoef[ia1 * 2u];\n         si1 = pCoef[(ia1 * 2u) + 1u];\n         co2 = pCoef[ia2 * 2u];\n         si2 = pCoef[(ia2 * 2u) + 1u];\n         co3 = pCoef[ia3 * 2u];\n         si3 = pCoef[(ia3 * 2u) + 1u];\n\n         /*  Twiddle coefficients index modifier */\n         ia1 = ia1 + twidCoefModifier;\n\n         i0 = j;\n         do\n         {\n            /*  index calculation for the input as, */\n            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n            i1 = i0 + n2;\n            i2 = i1 + n2;\n            i3 = i2 + n2;\n\n            /* xa + xc */\n            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];\n\n            /* xa - xc */\n            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];\n\n            /* ya + yc */\n            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];\n\n            /* ya - yc */\n            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];\n\n            /* xb + xd */\n            t1 = pSrc[2u * i1] + pSrc[2u * i3];\n\n            /* xa' = xa + xb + xc + xd */\n            pSrc[2u * i0] = r1 + t1;\n\n            /* xa + xc -(xb + xd) */\n            r1 = r1 - t1;\n\n            /* yb + yd */\n            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];\n\n            /* ya' = ya + yb + yc + yd */\n            pSrc[(2u * i0) + 1u] = s1 + t2;\n\n            /* (ya + yc) - (yb + yd) */\n            s1 = s1 - t2;\n\n            /* (yb - yd) */\n            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];\n\n            /* (xb - xd) */\n            t2 = pSrc[2u * i1] - pSrc[2u * i3];\n\n            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */\n            pSrc[2u * i1] = (r1 * co2) + (s1 * si2);\n\n            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */\n            pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);\n\n            /* (xa - xc) + (yb - yd) */\n            r1 = r2 + t1;\n\n            /* (xa - xc) - (yb - yd) */\n            r2 = r2 - t1;\n\n            /* (ya - yc) -  (xb - xd) */\n            s1 = s2 - t2;\n\n            /* (ya - yc) +  (xb - xd) */\n            s2 = s2 + t2;\n\n            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */\n            pSrc[2u * i2] = (r1 * co1) + (s1 * si1);\n\n            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */\n            pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);\n\n            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */\n            pSrc[2u * i3] = (r2 * co3) + (s2 * si3);\n\n            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */\n            pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);\n         \n            i0 += n1;\n         } while( i0 < fftLen);\n         j++;\n      } while(j <= (n2 - 1u));\n      twidCoefModifier <<= 2u;\n   }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */\n\n}\n\n/*    \n* @brief  Core function for the floating-point CIFFT butterfly process.   \n* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   \n* @param[in]      fftLen           length of the FFT.   \n* @param[in]      *pCoef           points to twiddle coefficient buffer.   \n* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n* @param[in]      onebyfftLen      value of 1/fftLen.   \n* @return none.   \n*/\n\nvoid arm_radix4_butterfly_inverse_f32(\nfloat32_t * pSrc,\nuint16_t fftLen,\nfloat32_t * pCoef,\nuint16_t twidCoefModifier,\nfloat32_t onebyfftLen)\n{\n   float32_t co1, co2, co3, si1, si2, si3;\n   uint32_t ia1, ia2, ia3;\n   uint32_t i0, i1, i2, i3;\n   uint32_t n1, n2, j, k;\n\n#ifndef ARM_MATH_CM0_FAMILY_FAMILY\n\n   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;\n   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,\n   Ybminusd;\n   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;\n   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;\n   float32_t *ptr1;\n   float32_t p0,p1,p2,p3,p4,p5,p6,p7;\n   float32_t a0,a1,a2,a3,a4,a5,a6,a7;\n\n\n   /*  Initializations for the first stage */\n   n2 = fftLen;\n   n1 = n2;\n\n   /* n2 = fftLen/4 */\n   n2 >>= 2u;\n   i0 = 0u;\n   ia1 = 0u;\n\n   j = n2;\n\n   /*  Calculation of first stage */\n   do\n   {\n      /*  index calculation for the input as, */\n      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n      i1 = i0 + n2;\n      i2 = i1 + n2;\n      i3 = i2 + n2;\n\n      /*  Butterfly implementation */\n      xaIn = pSrc[(2u * i0)];\n      yaIn = pSrc[(2u * i0) + 1u];\n\n      xcIn = pSrc[(2u * i2)];\n      ycIn = pSrc[(2u * i2) + 1u];\n\n      xbIn = pSrc[(2u * i1)];\n      ybIn = pSrc[(2u * i1) + 1u];\n\n      xdIn = pSrc[(2u * i3)];\n      ydIn = pSrc[(2u * i3) + 1u];\n\n      /* xa + xc */\n      Xaplusc = xaIn + xcIn;\n      /* xb + xd */\n      Xbplusd = xbIn + xdIn;\n      /* ya + yc */\n      Yaplusc = yaIn + ycIn;\n      /* yb + yd */\n      Ybplusd = ybIn + ydIn;\n\n      /*  index calculation for the coefficients */\n      ia2 = ia1 + ia1;\n      co2 = pCoef[ia2 * 2u];\n      si2 = pCoef[(ia2 * 2u) + 1u];\n\n      /* xa - xc */\n      Xaminusc = xaIn - xcIn;\n      /* xb - xd */\n      Xbminusd = xbIn - xdIn;\n      /* ya - yc */\n      Yaminusc = yaIn - ycIn;\n      /* yb - yd */\n      Ybminusd = ybIn - ydIn;\n\n      /* xa' = xa + xb + xc + xd */\n      pSrc[(2u * i0)] = Xaplusc + Xbplusd;\n\n      /* ya' = ya + yb + yc + yd */\n      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;\n\n      /* (xa - xc) - (yb - yd) */\n      Xb12C_out = (Xaminusc - Ybminusd);\n      /* (ya - yc) + (xb - xd) */\n      Yb12C_out = (Yaminusc + Xbminusd);\n      /* (xa + xc) - (xb + xd) */\n      Xc12C_out = (Xaplusc - Xbplusd);\n      /* (ya + yc) - (yb + yd) */\n      Yc12C_out = (Yaplusc - Ybplusd);\n      /* (xa - xc) + (yb - yd) */\n      Xd12C_out = (Xaminusc + Ybminusd);\n      /* (ya - yc) - (xb - xd) */\n      Yd12C_out = (Yaminusc - Xbminusd);\n\n      co1 = pCoef[ia1 * 2u];\n      si1 = pCoef[(ia1 * 2u) + 1u];\n\n      /*  index calculation for the coefficients */\n      ia3 = ia2 + ia1;\n      co3 = pCoef[ia3 * 2u];\n      si3 = pCoef[(ia3 * 2u) + 1u];\n\n      Xb12_out = Xb12C_out * co1;\n      Yb12_out = Yb12C_out * co1;\n      Xc12_out = Xc12C_out * co2;\n      Yc12_out = Yc12C_out * co2;\n      Xd12_out = Xd12C_out * co3;\n      Yd12_out = Yd12C_out * co3;\n   \n      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n      //Xb12_out -= Yb12C_out * si1;\n      p0 = Yb12C_out * si1;\n      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n      //Yb12_out += Xb12C_out * si1;\n      p1 = Xb12C_out * si1;\n      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n      //Xc12_out -= Yc12C_out * si2;\n      p2 = Yc12C_out * si2;\n      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n      //Yc12_out += Xc12C_out * si2;\n      p3 = Xc12C_out * si2;\n      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n      //Xd12_out -= Yd12C_out * si3;\n      p4 = Yd12C_out * si3;\n      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n      //Yd12_out += Xd12C_out * si3;\n      p5 = Xd12C_out * si3;\n      \n      Xb12_out -= p0;\n      Yb12_out += p1;\n      Xc12_out -= p2;\n      Yc12_out += p3;\n      Xd12_out -= p4;\n      Yd12_out += p5;\n\n      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n      pSrc[2u * i1] = Xc12_out;\n\n      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n      pSrc[(2u * i1) + 1u] = Yc12_out;\n\n      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n      pSrc[2u * i2] = Xb12_out;\n\n      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n      pSrc[(2u * i2) + 1u] = Yb12_out;\n\n      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n      pSrc[2u * i3] = Xd12_out;\n\n      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n      pSrc[(2u * i3) + 1u] = Yd12_out;\n\n      /*  Twiddle coefficients index modifier */\n      ia1 = ia1 + twidCoefModifier;\n\n      /*  Updating input index */\n      i0 = i0 + 1u;\n\n   } while(--j);\n\n   twidCoefModifier <<= 2u;\n\n   /*  Calculation of second stage to excluding last stage */\n   for (k = fftLen >> 2u; k > 4u; k >>= 2u)\n   {\n      /*  Initializations for the first stage */\n      n1 = n2;\n      n2 >>= 2u;\n      ia1 = 0u;\n\n      /*  Calculation of first stage */\n      j = 0;\n      do\n      {\n         /*  index calculation for the coefficients */\n         ia2 = ia1 + ia1;\n         ia3 = ia2 + ia1;\n         co1 = pCoef[ia1 * 2u];\n         si1 = pCoef[(ia1 * 2u) + 1u];\n         co2 = pCoef[ia2 * 2u];\n         si2 = pCoef[(ia2 * 2u) + 1u];\n         co3 = pCoef[ia3 * 2u];\n         si3 = pCoef[(ia3 * 2u) + 1u];\n\n         /*  Twiddle coefficients index modifier */\n         ia1 = ia1 + twidCoefModifier;\n\n         i0 = j;\n         do\n         {\n            /*  index calculation for the input as, */\n            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n            i1 = i0 + n2;\n            i2 = i1 + n2;\n            i3 = i2 + n2;\n\n            xaIn = pSrc[(2u * i0)];\n            yaIn = pSrc[(2u * i0) + 1u];\n\n            xbIn = pSrc[(2u * i1)];\n            ybIn = pSrc[(2u * i1) + 1u];\n\n            xcIn = pSrc[(2u * i2)];\n            ycIn = pSrc[(2u * i2) + 1u];\n\n            xdIn = pSrc[(2u * i3)];\n            ydIn = pSrc[(2u * i3) + 1u];\n\n            /* xa - xc */\n            Xaminusc = xaIn - xcIn;\n            /* (xb - xd) */\n            Xbminusd = xbIn - xdIn;\n            /* ya - yc */\n            Yaminusc = yaIn - ycIn;\n            /* (yb - yd) */\n            Ybminusd = ybIn - ydIn;\n\n            /* xa + xc */\n            Xaplusc = xaIn + xcIn;\n            /* xb + xd */\n            Xbplusd = xbIn + xdIn;\n            /* ya + yc */\n            Yaplusc = yaIn + ycIn;\n            /* yb + yd */\n            Ybplusd = ybIn + ydIn;\n\n            /* (xa - xc) - (yb - yd) */\n            Xb12C_out = (Xaminusc - Ybminusd);\n            /* (ya - yc) +  (xb - xd) */\n            Yb12C_out = (Yaminusc + Xbminusd);\n            /* xa + xc -(xb + xd) */\n            Xc12C_out = (Xaplusc - Xbplusd);\n            /* (ya + yc) - (yb + yd) */\n            Yc12C_out = (Yaplusc - Ybplusd);\n            /* (xa - xc) + (yb - yd) */\n            Xd12C_out = (Xaminusc + Ybminusd);\n            /* (ya - yc) -  (xb - xd) */\n            Yd12C_out = (Yaminusc - Xbminusd);\n\n            pSrc[(2u * i0)] = Xaplusc + Xbplusd;\n            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;\n\n            Xb12_out = Xb12C_out * co1;\n            Yb12_out = Yb12C_out * co1;\n            Xc12_out = Xc12C_out * co2;\n            Yc12_out = Yc12C_out * co2;\n            Xd12_out = Xd12C_out * co3;\n            Yd12_out = Yd12C_out * co3;\n\n            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n            //Xb12_out -= Yb12C_out * si1;\n            p0 = Yb12C_out * si1;\n            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n            //Yb12_out += Xb12C_out * si1;\n            p1 = Xb12C_out * si1;\n            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n            //Xc12_out -= Yc12C_out * si2;\n            p2 = Yc12C_out * si2;\n            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n            //Yc12_out += Xc12C_out * si2;\n            p3 = Xc12C_out * si2;\n            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n            //Xd12_out -= Yd12C_out * si3;\n            p4 = Yd12C_out * si3;\n            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n            //Yd12_out += Xd12C_out * si3;\n            p5 = Xd12C_out * si3;\n            \n            Xb12_out -= p0;\n            Yb12_out += p1;\n            Xc12_out -= p2;\n            Yc12_out += p3;\n            Xd12_out -= p4;\n            Yd12_out += p5;\n\n            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n            pSrc[2u * i1] = Xc12_out;\n\n            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n            pSrc[(2u * i1) + 1u] = Yc12_out;\n\n            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n            pSrc[2u * i2] = Xb12_out;\n\n            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n            pSrc[(2u * i2) + 1u] = Yb12_out;\n\n            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n            pSrc[2u * i3] = Xd12_out;\n\n            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n            pSrc[(2u * i3) + 1u] = Yd12_out;\n\n            i0 += n1;\n         } while(i0 < fftLen);\n         j++;\n      } while(j <= (n2 - 1u));\n      twidCoefModifier <<= 2u;\n   }\n   /*  Initializations of last stage */\n\n   j = fftLen >> 2;\n   ptr1 = &pSrc[0];\n\n   /*  Calculations of last stage */\n   do\n   {\n      xaIn = ptr1[0];\n      yaIn = ptr1[1];\n      xbIn = ptr1[2];\n      ybIn = ptr1[3];\n      xcIn = ptr1[4];\n      ycIn = ptr1[5];\n      xdIn = ptr1[6];\n      ydIn = ptr1[7];\n\n      /*  Butterfly implementation */\n      /* xa + xc */\n      Xaplusc = xaIn + xcIn;\n\n      /* xa - xc */\n      Xaminusc = xaIn - xcIn;\n\n      /* ya + yc */\n      Yaplusc = yaIn + ycIn;\n\n      /* ya - yc */\n      Yaminusc = yaIn - ycIn;\n\n      /* xb + xd */\n      Xbplusd = xbIn + xdIn;\n\n      /* yb + yd */\n      Ybplusd = ybIn + ydIn;\n\n      /* (xb-xd) */\n      Xbminusd = xbIn - xdIn;\n\n      /* (yb-yd) */\n      Ybminusd = ybIn - ydIn;\n      \n      /* xa' = (xa+xb+xc+xd) * onebyfftLen */\n      a0 = (Xaplusc + Xbplusd);\n      /* ya' = (ya+yb+yc+yd) * onebyfftLen */\n      a1 = (Yaplusc + Ybplusd);\n      /* xc' = (xa-xb+xc-xd) * onebyfftLen */\n      a2 = (Xaplusc - Xbplusd);\n      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */\n      a3 = (Yaplusc - Ybplusd);\n      /* xb' = (xa-yb-xc+yd) * onebyfftLen */\n      a4 = (Xaminusc - Ybminusd);\n      /* yb' = (ya+xb-yc-xd) * onebyfftLen */\n      a5 = (Yaminusc + Xbminusd);\n      /* xd' = (xa-yb-xc+yd) * onebyfftLen */\n      a6 = (Xaminusc + Ybminusd);\n      /* yd' = (ya-xb-yc+xd) * onebyfftLen */\n      a7 = (Yaminusc - Xbminusd);\n   \n      p0 = a0 * onebyfftLen;\n      p1 = a1 * onebyfftLen;\n      p2 = a2 * onebyfftLen;\n      p3 = a3 * onebyfftLen;\n      p4 = a4 * onebyfftLen;\n      p5 = a5 * onebyfftLen;\n      p6 = a6 * onebyfftLen;\n      p7 = a7 * onebyfftLen;\n   \n      /* xa' = (xa+xb+xc+xd) * onebyfftLen */\n      ptr1[0] = p0;\n      /* ya' = (ya+yb+yc+yd) * onebyfftLen */\n      ptr1[1] = p1;\n      /* xc' = (xa-xb+xc-xd) * onebyfftLen */\n      ptr1[2] = p2;\n      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */\n      ptr1[3] = p3;\n      /* xb' = (xa-yb-xc+yd) * onebyfftLen */\n      ptr1[4] = p4;\n      /* yb' = (ya+xb-yc-xd) * onebyfftLen */\n      ptr1[5] = p5;\n      /* xd' = (xa-yb-xc+yd) * onebyfftLen */\n      ptr1[6] = p6;\n      /* yd' = (ya-xb-yc+xd) * onebyfftLen */\n      ptr1[7] = p7;\n\n      /* increment source pointer by 8 for next calculations */\n      ptr1 = ptr1 + 8u;\n\n   } while(--j);\n\n#else\n\n   float32_t t1, t2, r1, r2, s1, s2;\n\n   /* Run the below code for Cortex-M0 */\n\n   /*  Initializations for the first stage */\n   n2 = fftLen;\n   n1 = n2;\n\n   /*  Calculation of first stage */\n   for (k = fftLen; k > 4u; k >>= 2u)\n   {\n      /*  Initializations for the first stage */\n      n1 = n2;\n      n2 >>= 2u;\n      ia1 = 0u;\n\n      /*  Calculation of first stage */\n      j = 0;\n      do\n      {\n         /*  index calculation for the coefficients */\n         ia2 = ia1 + ia1;\n         ia3 = ia2 + ia1;\n         co1 = pCoef[ia1 * 2u];\n         si1 = pCoef[(ia1 * 2u) + 1u];\n         co2 = pCoef[ia2 * 2u];\n         si2 = pCoef[(ia2 * 2u) + 1u];\n         co3 = pCoef[ia3 * 2u];\n         si3 = pCoef[(ia3 * 2u) + 1u];\n\n         /*  Twiddle coefficients index modifier */\n         ia1 = ia1 + twidCoefModifier;\n\n         i0 = j;\n         do\n         {\n            /*  index calculation for the input as, */\n            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n            i1 = i0 + n2;\n            i2 = i1 + n2;\n            i3 = i2 + n2;\n\n            /* xa + xc */\n            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];\n\n            /* xa - xc */\n            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];\n\n            /* ya + yc */\n            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];\n\n            /* ya - yc */\n            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];\n\n            /* xb + xd */\n            t1 = pSrc[2u * i1] + pSrc[2u * i3];\n\n            /* xa' = xa + xb + xc + xd */\n            pSrc[2u * i0] = r1 + t1;\n\n            /* xa + xc -(xb + xd) */\n            r1 = r1 - t1;\n\n            /* yb + yd */\n            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];\n\n            /* ya' = ya + yb + yc + yd */\n            pSrc[(2u * i0) + 1u] = s1 + t2;\n\n            /* (ya + yc) - (yb + yd) */\n            s1 = s1 - t2;\n\n            /* (yb - yd) */\n            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];\n\n            /* (xb - xd) */\n            t2 = pSrc[2u * i1] - pSrc[2u * i3];\n\n            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n            pSrc[2u * i1] = (r1 * co2) - (s1 * si2);\n\n            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n            pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);\n\n            /* (xa - xc) - (yb - yd) */\n            r1 = r2 - t1;\n\n            /* (xa - xc) + (yb - yd) */\n            r2 = r2 + t1;\n\n            /* (ya - yc) +  (xb - xd) */\n            s1 = s2 + t2;\n\n            /* (ya - yc) -  (xb - xd) */\n            s2 = s2 - t2;\n\n            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n            pSrc[2u * i2] = (r1 * co1) - (s1 * si1);\n\n            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n            pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);\n\n            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n            pSrc[2u * i3] = (r2 * co3) - (s2 * si3);\n\n            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n            pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);\n         \n            i0 += n1;\n         } while( i0 < fftLen);\n         j++;\n      } while(j <= (n2 - 1u));\n      twidCoefModifier <<= 2u;\n   }\n   /*  Initializations of last stage */\n   n1 = n2;\n   n2 >>= 2u;\n\n   /*  Calculations of last stage */\n   for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)\n   {\n      /*  index calculation for the input as, */\n      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */\n      i1 = i0 + n2;\n      i2 = i1 + n2;\n      i3 = i2 + n2;\n\n      /*  Butterfly implementation */\n      /* xa + xc */\n      r1 = pSrc[2u * i0] + pSrc[2u * i2];\n\n      /* xa - xc */\n      r2 = pSrc[2u * i0] - pSrc[2u * i2];\n\n      /* ya + yc */\n      s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];\n\n      /* ya - yc */\n      s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];\n\n      /* xc + xd */\n      t1 = pSrc[2u * i1] + pSrc[2u * i3];\n\n      /* xa' = xa + xb + xc + xd */\n      pSrc[2u * i0] = (r1 + t1) * onebyfftLen;\n\n      /* (xa + xb) - (xc + xd) */\n      r1 = r1 - t1;\n\n      /* yb + yd */\n      t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];\n\n      /* ya' = ya + yb + yc + yd */\n      pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;\n\n      /* (ya + yc) - (yb + yd) */\n      s1 = s1 - t2;\n\n      /* (yb-yd) */\n      t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];\n\n      /* (xb-xd) */\n      t2 = pSrc[2u * i1] - pSrc[2u * i3];\n\n      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n      pSrc[2u * i1] = r1 * onebyfftLen;\n\n      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n      pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;\n\n      /* (xa - xc) - (yb-yd) */\n      r1 = r2 - t1;\n\n      /* (xa - xc) + (yb-yd) */\n      r2 = r2 + t1;\n\n      /* (ya - yc) + (xb-xd) */\n      s1 = s2 + t2;\n\n      /* (ya - yc) - (xb-xd) */\n      s2 = s2 - t2;\n\n      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n      pSrc[2u * i2] = r1 * onebyfftLen;\n\n      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n      pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;\n\n      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n      pSrc[2u * i3] = r2 * onebyfftLen;\n\n      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n      pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;\n   }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */\n}\n\n/**    \n* @addtogroup ComplexFFT    \n* @{    \n*/\n\n/**    \n* @details    \n* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.   \n* @deprecated Do not use this function.  It has been superceded by \\ref arm_cfft_f32 and will be removed\n* in the future.\n* @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.   \n* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   \n* @return none.   \n*/\n\nvoid arm_cfft_radix4_f32(\nconst arm_cfft_radix4_instance_f32 * S,\nfloat32_t * pSrc)\n{\n\n   if(S->ifftFlag == 1u)\n   {\n      /*  Complex IFFT radix-4  */\n      arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,\n      S->twidCoefModifier, S->onebyfftLen);\n   }\n   else\n   {\n      /*  Complex FFT radix-4  */\n      arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,\n      S->twidCoefModifier);\n   }\n\n   if(S->bitReverseFlag == 1u)\n   {\n      /*  Bit Reversal */\n      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n   }\n\n}\n\n/**    \n* @} end of ComplexFFT group    \n*/\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_init_f32.c    \n*    \n* Description:\tRadix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n/**    \n* @brief  Initialization function for the floating-point CFFT/CIFFT.   \n* @deprecated Do not use this function.  It has been superceded by \\ref arm_cfft_f32 and will be removed\n* in the future.\n* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.   \n* @param[in]     fftLen         length of the FFT.   \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   \n*    \n* \\par Description:   \n* \\par    \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    \n* \\par    \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    \n* \\par    \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    \n*/\n\narm_status arm_cfft_radix4_init_f32(\n  arm_cfft_radix4_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (float32_t *) twiddleCoef;\n\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (S->fftLen)\n  {\n\n  case 4096u:\n    /*  Initializations of structure parameters for 4096 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.000244140625;\n    break;\n\n  case 1024u:\n    /*  Initializations of structure parameters for 1024 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 4u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 4u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n    /*  Initialise the 1/fftLen Value */\n    S->onebyfftLen = 0.0009765625f;\n    break;\n\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n    S->onebyfftLen = 0.00390625f;\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n    S->onebyfftLen = 0.015625f;\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n    S->onebyfftLen = 0.0625f;\n    break;\n\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_init_q15.c    \n*    \n* Description:\tRadix-4 Decimation in Frequency Q15 FFT & IFFT initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n\n/**    \n* @brief Initialization function for the Q15 CFFT/CIFFT.   \n* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   \n* @param[in]     fftLen         length of the FFT.   \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   \n*    \n* \\par Description:   \n* \\par    \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    \n* \\par    \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    \n* \\par    \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    \n*/\n\narm_status arm_cfft_radix4_init_q15(\n  arm_cfft_radix4_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (q15_t *) twiddleCoefQ15;\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (S->fftLen)\n  {\n  case 4096u:\n    /*  Initializations of structure parameters for 4096 point FFT */\n\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n\n    break;\n\n  case 1024u:\n    /*  Initializations of structure parameters for 1024 point FFT */\n    S->twidCoefModifier = 4u;\n    S->bitRevFactor = 4u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n\n    break;\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n\n    break;\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013 \n* $Revision: \tV1.4.1   \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_init_q31.c    \n*    \n* Description:\tRadix-4 Decimation in Frequency Q31 FFT & IFFT initialization function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n/**    \n*    \n* @brief  Initialization function for the Q31 CFFT/CIFFT.   \n* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   \n* @param[in]     fftLen         length of the FFT.   \n* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   \n*    \n* \\par Description:   \n* \\par    \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    \n* \\par    \n* The parameter fftLen\tSpecifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    \n* \\par    \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    \n*/\n\narm_status arm_cfft_radix4_init_q31(\n  arm_cfft_radix4_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n  /*  Initialise the FFT length */\n  S->fftLen = fftLen;\n  /*  Initialise the Twiddle coefficient pointer */\n  S->pTwiddle = (q31_t *) twiddleCoefQ31;\n  /*  Initialise the Flag for selection of CFFT or CIFFT */\n  S->ifftFlag = ifftFlag;\n  /*  Initialise the Flag for calculation Bit reversal or not */\n  S->bitReverseFlag = bitReverseFlag;\n\n  /*  Initializations of Instance structure depending on the FFT length */\n  switch (S->fftLen)\n  {\n    /*  Initializations of structure parameters for 4096 point FFT */\n  case 4096u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 1u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 1u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) armBitRevTable;\n    break;\n\n    /*  Initializations of structure parameters for 1024 point FFT */\n  case 1024u:\n    /*  Initialise the twiddle coef modifier value */\n    S->twidCoefModifier = 4u;\n    /*  Initialise the bit reversal table modifier */\n    S->bitRevFactor = 4u;\n    /*  Initialise the bit reversal table pointer */\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];\n    break;\n\n  case 256u:\n    /*  Initializations of structure parameters for 256 point FFT */\n    S->twidCoefModifier = 16u;\n    S->bitRevFactor = 16u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];\n    break;\n\n  case 64u:\n    /*  Initializations of structure parameters for 64 point FFT */\n    S->twidCoefModifier = 64u;\n    S->bitRevFactor = 64u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];\n    break;\n\n  case 16u:\n    /*  Initializations of structure parameters for 16 point FFT */\n    S->twidCoefModifier = 256u;\n    S->bitRevFactor = 256u;\n    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];\n    break;\n\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_q15.c    \n*    \n* Description:\tThis file has function definition of Radix-4 FFT & IFFT function and    \n*\t\t\t\tIn-place bit reversal using bit reversal table    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n\nvoid arm_radix4_butterfly_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier);\n\nvoid arm_radix4_butterfly_inverse_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier);\n\nvoid arm_bitreversal_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  uint16_t bitRevFactor,\n  uint16_t * pBitRevTab);\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n\n/**    \n * @details    \n * @brief Processing function for the Q15 CFFT/CIFFT.   \n * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.   \n * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.   \n * @return none.   \n *     \n * \\par Input and output formats:    \n * \\par    \n * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   \n * Hence the output format is different for different FFT sizes.    \n * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   \n * \\par   \n * \\image html CFFTQ15.gif \"Input and Output Formats for Q15 CFFT\"    \n * \\image html CIFFTQ15.gif \"Input and Output Formats for Q15 CIFFT\"    \n */\n\nvoid arm_cfft_radix4_q15(\n  const arm_cfft_radix4_instance_q15 * S,\n  q15_t * pSrc)\n{\n  if(S->ifftFlag == 1u)\n  {\n    /*  Complex IFFT radix-4  */\n    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,\n                                     S->twidCoefModifier);\n  }\n  else\n  {\n    /*  Complex FFT radix-4  */\n    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,\n                             S->twidCoefModifier);\n  }\n\n  if(S->bitReverseFlag == 1u)\n  {\n    /*  Bit Reversal */\n    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n  }\n\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n\n/*    \n* Radix-4 FFT algorithm used is :    \n*    \n* Input real and imaginary data:    \n* x(n) = xa + j * ya    \n* x(n+N/4 ) = xb + j * yb    \n* x(n+N/2 ) = xc + j * yc    \n* x(n+3N 4) = xd + j * yd    \n*    \n*    \n* Output real and imaginary data:    \n* x(4r) = xa'+ j * ya'    \n* x(4r+1) = xb'+ j * yb'    \n* x(4r+2) = xc'+ j * yc'    \n* x(4r+3) = xd'+ j * yd'    \n*    \n*    \n* Twiddle factors for radix-4 FFT:    \n* Wn = co1 + j * (- si1)    \n* W2n = co2 + j * (- si2)    \n* W3n = co3 + j * (- si3)    \n    \n* The real and imaginary output values for the radix-4 butterfly are    \n* xa' = xa + xb + xc + xd    \n* ya' = ya + yb + yc + yd    \n* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    \n* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    \n* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    \n* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    \n* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    \n* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    \n*    \n*/\n\n/**    \n * @brief  Core function for the Q15 CFFT butterfly process.   \n * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   \n * @param[in]      fftLen           length of the FFT.   \n * @param[in]      *pCoef16         points to twiddle coefficient buffer.   \n * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.   \n */\n\nvoid arm_radix4_butterfly_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t R, S, T, U;\n  q31_t C1, C2, C3, out1, out2;\n  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;\n  q15_t in;\n\n  q15_t *ptr1;\n\n\n\n  q31_t xaya, xbyb, xcyc, xdyd;\n\n  /* Total process is divided into three stages */\n\n  /* process first stage, middle stages, & last stage */\n\n  /*  Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n\n  /* Index for twiddle coefficient */\n  ic = 0u;\n\n  /* Index for input read and output write */\n  i0 = 0u;\n  j = n2;\n\n  /* Input is in 1.15(q15) format */\n\n  /*  start of first stage process */\n  do\n  {\n    /*  Butterfly implementation */\n\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n    /* Read ya (real), xa(imag) input */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* Read yc (real), xc(imag) input */\n    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* R = packed((ya + yc), (xa + xc) ) */\n    R = __QADD16(T, S);\n\n    /* S = packed((ya - yc), (xa - xc) ) */\n    S = __QSUB16(T, S);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* Read yb (real), xb(imag) input */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* Read yd (real), xd(imag) input */\n    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n    in = ((int16_t) (U & 0xFFFF)) >> 2;\n    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* T = packed((yb + yd), (xb + xd) ) */\n    T = __QADD16(T, U);\n\n    /*  writing the butterfly processed i0 sample */\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);\n\n    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */\n    R = __QSUB16(R, T);\n\n    /* co2 & si2 are read from SIMD Coefficient pointer */\n    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n    out1 = __SMUAD(C2, R) >> 16u;\n    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n    out2 = __SMUSDX(C2, R);\n\n#else\n\n    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n    out1 = __SMUSDX(R, C2) >> 16u;\n    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n    out2 = __SMUAD(C2, R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /*  Reading i0+fftLen/4 */\n    /* T = packed(yb, xb) */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* writing the butterfly processed i0 + fftLen/4 sample */\n    /* writing output(xc', yc') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    /*  Butterfly calculations */\n    /* U = packed(yd, xd) */\n    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n    in = ((int16_t) (U & 0xFFFF)) >> 2;\n    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* T = packed(yb-yd, xb-xd) */\n    T = __QSUB16(T, U);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n    R = __QASX(S, T);\n    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n    S = __QSAX(S, T);\n\n#else\n\n    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n    R = __QSAX(S, T);\n    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n    S = __QASX(S, T);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* co1 & si1 are read from SIMD Coefficient pointer */\n    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));\n    /*  Butterfly process for the i0+fftLen/2 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n    out1 = __SMUAD(C1, S) >> 16u;\n    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n    out2 = __SMUSDX(C1, S);\n\n#else\n\n    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n    out1 = __SMUSDX(S, C1) >> 16u;\n    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n    out2 = __SMUAD(C1, S);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* writing output(xb', yb') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =\n      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);\n\n\n    /* co3 & si3 are read from SIMD Coefficient pointer */\n    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));\n    /*  Butterfly process for the i0+3fftLen/4 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n    out1 = __SMUAD(C3, R) >> 16u;\n    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n    out2 = __SMUSDX(C3, R);\n\n#else\n\n    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n    out1 = __SMUSDX(R, C3) >> 16u;\n    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n    out2 = __SMUAD(C3, R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* writing output(xd', yd') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =\n      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    /*  Twiddle coefficients index modifier */\n    ic = ic + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n  /* data is in 4.11(q11) format */\n\n  /* end of first stage process */\n\n\n  /* start of middle stage process */\n\n  /*  Twiddle coefficients index modifier */\n  twidCoefModifier <<= 2u;\n\n  /*  Calculation of Middle stage */\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the middle stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ic = 0u;\n\n    for (j = 0u; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));\n      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));\n      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));\n\n      /*  Twiddle coefficients index modifier */\n      ic = ic + twidCoefModifier;\n\n      /*  Butterfly implementation */\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Reading i0, i0+fftLen/2 inputs */\n        /* Read ya (real), xa(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));\n\n        /* Read yc (real), xc(imag) input */\n        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));\n\n        /* R = packed( (ya + yc), (xa + xc)) */\n        R = __QADD16(T, S);\n\n        /* S = packed((ya - yc), (xa - xc)) */\n        S = __QSUB16(T, S);\n\n        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n        /* Read yb (real), xb(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n\n        /* Read yd (real), xd(imag) input */\n        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n\n        /* T = packed( (yb + yd), (xb + xd)) */\n        T = __QADD16(T, U);\n\n        /*  writing the butterfly processed i0 sample */\n\n        /* xa' = xa + xb + xc + xd */\n        /* ya' = ya + yb + yc + yd */\n        out1 = __SHADD16(R, T);\n        in = ((int16_t) (out1 & 0xFFFF)) >> 1;\n        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);\n        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;\n\n        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */\n        R = __SHSUB16(R, T);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */\n        out1 = __SMUAD(C2, R) >> 16u;\n\n        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        out2 = __SMUSDX(C2, R);\n\n#else\n\n        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        out1 = __SMUSDX(R, C2) >> 16u;\n\n        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */\n        out2 = __SMUAD(C2, R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /*  Reading i0+3fftLen/4 */\n        /* Read yb (real), xb(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n\n        /*  writing the butterfly processed i0 + fftLen/4 sample */\n        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        /*  Butterfly calculations */\n\n        /* Read yd (real), xd(imag) input */\n        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n\n        /* T = packed(yb-yd, xb-xd) */\n        T = __QSUB16(T, U);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n        R = __SHASX(S, T);\n\n        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n        S = __SHSAX(S, T);\n\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = __SMUAD(C1, S) >> 16u;\n        out2 = __SMUSDX(C1, S);\n\n#else\n\n        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n        R = __SHSAX(S, T);\n\n        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n        S = __SHASX(S, T);\n\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = __SMUSDX(S, C1) >> 16u;\n        out2 = __SMUAD(C1, S);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        /*  Butterfly process for the i0+3fftLen/4 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUAD(C3, R) >> 16u;\n        out2 = __SMUSDX(C3, R);\n\n#else\n\n        out1 = __SMUSDX(R, C3) >> 16u;\n        out2 = __SMUAD(C3, R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n      }\n    }\n    /*  Twiddle coefficients index modifier */\n    twidCoefModifier <<= 2u;\n  }\n  /* end of middle stage process */\n\n\n  /* data is in 10.6(q6) format for the 1024 point */\n  /* data is in 8.8(q8) format for the 256 point */\n  /* data is in 6.10(q10) format for the 64 point */\n  /* data is in 4.12(q12) format for the 16 point */\n\n  /*  Initializations for the last stage */\n  j = fftLen >> 2;\n\n  ptr1 = &pSrc16[0];\n\n  /* start of last stage process */\n\n  /*  Butterfly implementation */\n  do\n  {\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD32(ptr1)++;\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD32(ptr1)++;\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD32(ptr1)++;\n\n    /* Read xd (real), yd(imag) input */\n    xdyd = *__SIMD32(ptr1)++;\n\n    /* R = packed((ya + yc), (xa + xc)) */\n    R = __QADD16(xaya, xcyc);\n\n    /* T = packed((yb + yd), (xb + xd)) */\n    T = __QADD16(xbyb, xdyd);\n\n    /* pointer updation for writing */\n    ptr1 = ptr1 - 8u;\n\n\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    *__SIMD32(ptr1)++ = __SHADD16(R, T);\n\n    /* T = packed((yb + yd), (xb + xd)) */\n    T = __QADD16(xbyb, xdyd);\n\n    /* xc' = (xa-xb+xc-xd) */\n    /* yc' = (ya-yb+yc-yd) */\n    *__SIMD32(ptr1)++ = __SHSUB16(R, T);\n\n    /* S = packed((ya - yc), (xa - xc)) */\n    S = __QSUB16(xaya, xcyc);\n\n    /* Read yd (real), xd(imag) input */\n    /* T = packed( (yb - yd), (xb - xd))  */\n    U = __QSUB16(xbyb, xdyd);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xb' = (xa+yb-xc-yd) */\n    /* yb' = (ya-xb-yc+xd) */\n    *__SIMD32(ptr1)++ = __SHSAX(S, U);\n\n\n    /* xd' = (xa-yb-xc+yd) */\n    /* yd' = (ya+xb-yc-xd) */\n    *__SIMD32(ptr1)++ = __SHASX(S, U);\n\n#else\n\n    /* xb' = (xa+yb-xc-yd) */\n    /* yb' = (ya-xb-yc+xd) */\n    *__SIMD32(ptr1)++ = __SHASX(S, U);\n\n\n    /* xd' = (xa-yb-xc+yd) */\n    /* yd' = (ya+xb-yc-xd) */\n    *__SIMD32(ptr1)++ = __SHSAX(S, U);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n  } while(--j);\n\n  /* end of last stage process */\n\n  /* output is in 11.5(q5) format for the 1024 point */\n  /* output is in 9.7(q7) format for the 256 point   */\n  /* output is in 7.9(q9) format for the 64 point  */\n  /* output is in 5.11(q11) format for the 16 point  */\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t R0, R1, S0, S1, T0, T1, U0, U1;\n  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;\n  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;\n\n  /* Total process is divided into three stages */\n\n  /* process first stage, middle stages, & last stage */\n\n  /*  Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n\n  /* Index for twiddle coefficient */\n  ic = 0u;\n\n  /* Index for input read and output write */\n  i0 = 0u;\n  j = n2;\n\n  /* Input is in 1.15(q15) format */\n\n  /*  start of first stage process */\n  do\n  {\n    /*  Butterfly implementation */\n\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n\n    /* input is down scale by 4 to avoid overflow */\n    /* Read ya (real), xa(imag) input */\n    T0 = pSrc16[i0 * 2u] >> 2u;\n    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;\n\n    /* input is down scale by 4 to avoid overflow */\n    /* Read yc (real), xc(imag) input */\n    S0 = pSrc16[i2 * 2u] >> 2u;\n    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;\n\n    /* R0 = (ya + yc) */\n    R0 = __SSAT(T0 + S0, 16u);\n    /* R1 = (xa + xc) */\n    R1 = __SSAT(T1 + S1, 16u);\n\n    /* S0 = (ya - yc) */\n    S0 = __SSAT(T0 - S0, 16);\n    /* S1 = (xa - xc) */\n    S1 = __SSAT(T1 - S1, 16);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* input is down scale by 4 to avoid overflow */\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u] >> 2u;\n    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;\n\n    /* input is down scale by 4 to avoid overflow */\n    /* Read yd (real), xd(imag) input */\n    U0 = pSrc16[i3 * 2u] >> 2u;\n    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;\n\n    /* T0 = (yb + yd) */\n    T0 = __SSAT(T0 + U0, 16u);\n    /* T1 = (xb + xd) */\n    T1 = __SSAT(T1 + U1, 16u);\n\n    /*  writing the butterfly processed i0 sample */\n    /* ya' = ya + yb + yc + yd */\n    /* xa' = xa + xb + xc + xd */\n    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);\n    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);\n\n    /* R0 = (ya + yc) - (yb + yd) */\n    /* R1 = (xa + xc) - (xb + xd) */\n    R0 = __SSAT(R0 - T0, 16u);\n    R1 = __SSAT(R1 - T1, 16u);\n\n    /* co2 & si2 are read from Coefficient pointer */\n    Co2 = pCoef16[2u * ic * 2u];\n    Si2 = pCoef16[(2u * ic * 2u) + 1];\n\n    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);\n    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);\n\n    /*  Reading i0+fftLen/4 */\n    /* input is down scale by 4 to avoid overflow */\n    /* T0 = yb, T1 =  xb */\n    T0 = pSrc16[i1 * 2u] >> 2;\n    T1 = pSrc16[(i1 * 2u) + 1] >> 2;\n\n    /* writing the butterfly processed i0 + fftLen/4 sample */\n    /* writing output(xc', yc') in little endian format */\n    pSrc16[i1 * 2u] = out1;\n    pSrc16[(i1 * 2u) + 1] = out2;\n\n    /*  Butterfly calculations */\n    /* input is down scale by 4 to avoid overflow */\n    /* U0 = yd, U1 = xd */\n    U0 = pSrc16[i3 * 2u] >> 2;\n    U1 = pSrc16[(i3 * 2u) + 1] >> 2;\n    /* T0 = yb-yd */\n    T0 = __SSAT(T0 - U0, 16);\n    /* T1 = xb-xd */\n    T1 = __SSAT(T1 - U1, 16);\n\n    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */\n    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);\n    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);\n\n    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */\n    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);\n    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);\n\n    /* co1 & si1 are read from Coefficient pointer */\n    Co1 = pCoef16[ic * 2u];\n    Si1 = pCoef16[(ic * 2u) + 1];\n    /*  Butterfly process for the i0+fftLen/2 sample */\n    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);\n    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);\n\n    /* writing output(xb', yb') in little endian format */\n    pSrc16[i2 * 2u] = out1;\n    pSrc16[(i2 * 2u) + 1] = out2;\n\n    /* Co3 & si3 are read from Coefficient pointer */\n    Co3 = pCoef16[3u * (ic * 2u)];\n    Si3 = pCoef16[(3u * (ic * 2u)) + 1];\n    /*  Butterfly process for the i0+3fftLen/4 sample */\n    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */\n    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);\n    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */\n    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);\n    /* writing output(xd', yd') in little endian format */\n    pSrc16[i3 * 2u] = out1;\n    pSrc16[(i3 * 2u) + 1] = out2;\n\n    /*  Twiddle coefficients index modifier */\n    ic = ic + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n  /* data is in 4.11(q11) format */\n\n  /* end of first stage process */\n\n\n  /* start of middle stage process */\n\n  /*  Twiddle coefficients index modifier */\n  twidCoefModifier <<= 2u;\n\n  /*  Calculation of Middle stage */\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the middle stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ic = 0u;\n\n    for (j = 0u; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      Co1 = pCoef16[ic * 2u];\n      Si1 = pCoef16[(ic * 2u) + 1u];\n      Co2 = pCoef16[2u * (ic * 2u)];\n      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];\n      Co3 = pCoef16[3u * (ic * 2u)];\n      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];\n\n      /*  Twiddle coefficients index modifier */\n      ic = ic + twidCoefModifier;\n\n      /*  Butterfly implementation */\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Reading i0, i0+fftLen/2 inputs */\n        /* Read ya (real), xa(imag) input */\n        T0 = pSrc16[i0 * 2u];\n        T1 = pSrc16[(i0 * 2u) + 1u];\n\n        /* Read yc (real), xc(imag) input */\n        S0 = pSrc16[i2 * 2u];\n        S1 = pSrc16[(i2 * 2u) + 1u];\n\n        /* R0 = (ya + yc), R1 = (xa + xc) */\n        R0 = __SSAT(T0 + S0, 16);\n        R1 = __SSAT(T1 + S1, 16);\n\n        /* S0 = (ya - yc), S1 =(xa - xc) */\n        S0 = __SSAT(T0 - S0, 16);\n        S1 = __SSAT(T1 - S1, 16);\n\n        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n        /* Read yb (real), xb(imag) input */\n        T0 = pSrc16[i1 * 2u];\n        T1 = pSrc16[(i1 * 2u) + 1u];\n\n        /* Read yd (real), xd(imag) input */\n        U0 = pSrc16[i3 * 2u];\n        U1 = pSrc16[(i3 * 2u) + 1u];\n\n\n        /* T0 = (yb + yd), T1 = (xb + xd) */\n        T0 = __SSAT(T0 + U0, 16);\n        T1 = __SSAT(T1 + U1, 16);\n\n        /*  writing the butterfly processed i0 sample */\n\n        /* xa' = xa + xb + xc + xd */\n        /* ya' = ya + yb + yc + yd */\n        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;\n        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;\n\n        pSrc16[i0 * 2u] = out1;\n        pSrc16[(2u * i0) + 1u] = out2;\n\n        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */\n        R0 = (R0 >> 1u) - (T0 >> 1u);\n        R1 = (R1 >> 1u) - (T1 >> 1u);\n\n        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */\n        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);\n\n        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);\n\n        /*  Reading i0+3fftLen/4 */\n        /* Read yb (real), xb(imag) input */\n        T0 = pSrc16[i1 * 2u];\n        T1 = pSrc16[(i1 * 2u) + 1u];\n\n        /*  writing the butterfly processed i0 + fftLen/4 sample */\n        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        pSrc16[i1 * 2u] = out1;\n        pSrc16[(i1 * 2u) + 1u] = out2;\n\n        /*  Butterfly calculations */\n\n        /* Read yd (real), xd(imag) input */\n        U0 = pSrc16[i3 * 2u];\n        U1 = pSrc16[(i3 * 2u) + 1u];\n\n        /* T0 = yb-yd, T1 = xb-xd */\n        T0 = __SSAT(T0 - U0, 16);\n        T1 = __SSAT(T1 - U1, 16);\n\n        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */\n        R0 = (S0 >> 1u) - (T1 >> 1u);\n        R1 = (S1 >> 1u) + (T0 >> 1u);\n\n        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */\n        S0 = (S0 >> 1u) + (T1 >> 1u);\n        S1 = (S1 >> 1u) - (T0 >> 1u);\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);\n\n        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);\n\n        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n        pSrc16[i2 * 2u] = out1;\n        pSrc16[(i2 * 2u) + 1u] = out2;\n\n        /*  Butterfly process for the i0+3fftLen/4 sample */\n        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);\n\n        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);\n        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */\n        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */\n        pSrc16[i3 * 2u] = out1;\n        pSrc16[(i3 * 2u) + 1u] = out2;\n      }\n    }\n    /*  Twiddle coefficients index modifier */\n    twidCoefModifier <<= 2u;\n  }\n  /* end of middle stage process */\n\n\n  /* data is in 10.6(q6) format for the 1024 point */\n  /* data is in 8.8(q8) format for the 256 point */\n  /* data is in 6.10(q10) format for the 64 point */\n  /* data is in 4.12(q12) format for the 16 point */\n\n  /*  Initializations for the last stage */\n  n1 = n2;\n  n2 >>= 2u;\n\n  /* start of last stage process */\n\n  /*  Butterfly implementation */\n  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)\n  {\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n    /* Read ya (real), xa(imag) input */\n    T0 = pSrc16[i0 * 2u];\n    T1 = pSrc16[(i0 * 2u) + 1u];\n\n    /* Read yc (real), xc(imag) input */\n    S0 = pSrc16[i2 * 2u];\n    S1 = pSrc16[(i2 * 2u) + 1u];\n\n    /* R0 = (ya + yc), R1 = (xa + xc) */\n    R0 = __SSAT(T0 + S0, 16u);\n    R1 = __SSAT(T1 + S1, 16u);\n\n    /* S0 = (ya - yc), S1 = (xa - xc) */\n    S0 = __SSAT(T0 - S0, 16u);\n    S1 = __SSAT(T1 - S1, 16u);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u];\n    T1 = pSrc16[(i1 * 2u) + 1u];\n    /* Read yd (real), xd(imag) input */\n    U0 = pSrc16[i3 * 2u];\n    U1 = pSrc16[(i3 * 2u) + 1u];\n\n    /* T0 = (yb + yd), T1 = (xb + xd)) */\n    T0 = __SSAT(T0 + U0, 16u);\n    T1 = __SSAT(T1 + U1, 16u);\n\n    /*  writing the butterfly processed i0 sample */\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);\n    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);\n\n    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */\n    R0 = (R0 >> 1u) - (T0 >> 1u);\n    R1 = (R1 >> 1u) - (T1 >> 1u);\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u];\n    T1 = pSrc16[(i1 * 2u) + 1u];\n\n    /*  writing the butterfly processed i0 + fftLen/4 sample */\n    /* xc' = (xa-xb+xc-xd) */\n    /* yc' = (ya-yb+yc-yd) */\n    pSrc16[i1 * 2u] = R0;\n    pSrc16[(i1 * 2u) + 1u] = R1;\n\n    /* Read yd (real), xd(imag) input */\n    U0 = pSrc16[i3 * 2u];\n    U1 = pSrc16[(i3 * 2u) + 1u];\n    /* T0 = (yb - yd), T1 = (xb - xd)  */\n    T0 = __SSAT(T0 - U0, 16u);\n    T1 = __SSAT(T1 - U1, 16u);\n\n    /*  writing the butterfly processed i0 + fftLen/2 sample */\n    /* xb' = (xa+yb-xc-yd) */\n    /* yb' = (ya-xb-yc+xd) */\n    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);\n    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);\n\n    /*  writing the butterfly processed i0 + 3fftLen/4 sample */\n    /* xd' = (xa-yb-xc+yd) */\n    /* yd' = (ya+xb-yc-xd) */\n    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);\n    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);\n\n  }\n\n  /* end of last stage process */\n\n  /* output is in 11.5(q5) format for the 1024 point */\n  /* output is in 9.7(q7) format for the 256 point   */\n  /* output is in 7.9(q9) format for the 64 point  */\n  /* output is in 5.11(q11) format for the 16 point  */\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n/**    \n * @brief  Core function for the Q15 CIFFT butterfly process.   \n * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   \n * @param[in]      fftLen           length of the FFT.   \n * @param[in]      *pCoef16         points to twiddle coefficient buffer.   \n * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.   \n */\n\n/*    \n* Radix-4 IFFT algorithm used is :    \n*    \n* CIFFT uses same twiddle coefficients as CFFT function    \n*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    \n*    \n*    \n* IFFT is implemented with following changes in equations from FFT    \n*    \n* Input real and imaginary data:    \n* x(n) = xa + j * ya    \n* x(n+N/4 ) = xb + j * yb    \n* x(n+N/2 ) = xc + j * yc    \n* x(n+3N 4) = xd + j * yd    \n*    \n*    \n* Output real and imaginary data:    \n* x(4r) = xa'+ j * ya'    \n* x(4r+1) = xb'+ j * yb'    \n* x(4r+2) = xc'+ j * yc'    \n* x(4r+3) = xd'+ j * yd'    \n*    \n*    \n* Twiddle factors for radix-4 IFFT:    \n* Wn = co1 + j * (si1)    \n* W2n = co2 + j * (si2)    \n* W3n = co3 + j * (si3)    \n    \n* The real and imaginary output values for the radix-4 butterfly are    \n* xa' = xa + xb + xc + xd    \n* ya' = ya + yb + yc + yd    \n* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    \n* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    \n* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    \n* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    \n* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    \n* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    \n*    \n*/\n\nvoid arm_radix4_butterfly_inverse_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier)\n{\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  q31_t R, S, T, U;\n  q31_t C1, C2, C3, out1, out2;\n  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;\n  q15_t in;\n\n  q15_t *ptr1;\n\n\n\n  q31_t xaya, xbyb, xcyc, xdyd;\n\n  /* Total process is divided into three stages */\n\n  /* process first stage, middle stages, & last stage */\n\n  /*  Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n\n  /* Index for twiddle coefficient */\n  ic = 0u;\n\n  /* Index for input read and output write */\n  i0 = 0u;\n  j = n2;\n\n  /* Input is in 1.15(q15) format */\n\n  /*  start of first stage process */\n  do\n  {\n    /*  Butterfly implementation */\n\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n    /* Read ya (real), xa(imag) input */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* Read yc (real), xc(imag) input */\n    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));\n    in = ((int16_t) (S & 0xFFFF)) >> 2;\n    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* R = packed((ya + yc), (xa + xc) ) */\n    R = __QADD16(T, S);\n\n    /* S = packed((ya - yc), (xa - xc) ) */\n    S = __QSUB16(T, S);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* Read yb (real), xb(imag) input */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* Read yd (real), xd(imag) input */\n    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n    in = ((int16_t) (U & 0xFFFF)) >> 2;\n    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* T = packed((yb + yd), (xb + xd) ) */\n    T = __QADD16(T, U);\n\n    /*  writing the butterfly processed i0 sample */\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);\n\n    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */\n    R = __QSUB16(R, T);\n\n    /* co2 & si2 are read from SIMD Coefficient pointer */\n    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n    out1 = __SMUSD(C2, R) >> 16u;\n    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n    out2 = __SMUADX(C2, R);\n\n#else\n\n    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n    out1 = __SMUADX(C2, R) >> 16u;\n    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n    out2 = __SMUSD(__QSUB16(0, C2), R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /*  Reading i0+fftLen/4 */\n    /* T = packed(yb, xb) */\n    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n    in = ((int16_t) (T & 0xFFFF)) >> 2;\n    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* writing the butterfly processed i0 + fftLen/4 sample */\n    /* writing output(xc', yc') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =\n      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    /*  Butterfly calculations */\n    /* U = packed(yd, xd) */\n    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n    in = ((int16_t) (U & 0xFFFF)) >> 2;\n    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);\n\n    /* T = packed(yb-yd, xb-xd) */\n    T = __QSUB16(T, U);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n    R = __QSAX(S, T);\n    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */\n    S = __QASX(S, T);\n\n#else\n\n    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n    R = __QASX(S, T);\n    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n    S = __QSAX(S, T);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* co1 & si1 are read from SIMD Coefficient pointer */\n    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));\n    /*  Butterfly process for the i0+fftLen/2 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n    out1 = __SMUSD(C1, S) >> 16u;\n    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n    out2 = __SMUADX(C1, S);\n\n#else\n\n    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n    out1 = __SMUADX(C1, S) >> 16u;\n    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n    out2 = __SMUSD(__QSUB16(0, C1), S);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* writing output(xb', yb') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =\n      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);\n\n\n    /* co3 & si3 are read from SIMD Coefficient pointer */\n    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));\n    /*  Butterfly process for the i0+3fftLen/4 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n    out1 = __SMUSD(C3, R) >> 16u;\n    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n    out2 = __SMUADX(C3, R);\n\n#else\n\n    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n    out1 = __SMUADX(C3, R) >> 16u;\n    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n    out2 = __SMUSD(__QSUB16(0, C3), R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* writing output(xd', yd') in little endian format */\n    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =\n      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n    /*  Twiddle coefficients index modifier */\n    ic = ic + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n  /* data is in 4.11(q11) format */\n\n  /* end of first stage process */\n\n\n  /* start of middle stage process */\n\n  /*  Twiddle coefficients index modifier */\n  twidCoefModifier <<= 2u;\n\n  /*  Calculation of Middle stage */\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the middle stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ic = 0u;\n\n    for (j = 0u; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));\n      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));\n      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));\n\n      /*  Twiddle coefficients index modifier */\n      ic = ic + twidCoefModifier;\n\n      /*  Butterfly implementation */\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Reading i0, i0+fftLen/2 inputs */\n        /* Read ya (real), xa(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));\n\n        /* Read yc (real), xc(imag) input */\n        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));\n\n        /* R = packed( (ya + yc), (xa + xc)) */\n        R = __QADD16(T, S);\n\n        /* S = packed((ya - yc), (xa - xc)) */\n        S = __QSUB16(T, S);\n\n        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n        /* Read yb (real), xb(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n\n        /* Read yd (real), xd(imag) input */\n        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n\n        /* T = packed( (yb + yd), (xb + xd)) */\n        T = __QADD16(T, U);\n\n        /*  writing the butterfly processed i0 sample */\n\n        /* xa' = xa + xb + xc + xd */\n        /* ya' = ya + yb + yc + yd */\n        out1 = __SHADD16(R, T);\n        in = ((int16_t) (out1 & 0xFFFF)) >> 1;\n        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);\n        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;\n\n        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */\n        R = __SHSUB16(R, T);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */\n        out1 = __SMUSD(C2, R) >> 16u;\n\n        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        out2 = __SMUADX(C2, R);\n\n#else\n\n        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        out1 = __SMUADX(R, C2) >> 16u;\n\n        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */\n        out2 = __SMUSD(__QSUB16(0, C2), R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /*  Reading i0+3fftLen/4 */\n        /* Read yb (real), xb(imag) input */\n        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));\n\n        /*  writing the butterfly processed i0 + fftLen/4 sample */\n        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */\n        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        /*  Butterfly calculations */\n\n        /* Read yd (real), xd(imag) input */\n        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));\n\n        /* T = packed(yb-yd, xb-xd) */\n        T = __QSUB16(T, U);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n        R = __SHSAX(S, T);\n\n        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n        S = __SHASX(S, T);\n\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = __SMUSD(C1, S) >> 16u;\n        out2 = __SMUADX(C1, S);\n\n#else\n\n        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */\n        R = __SHASX(S, T);\n\n        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */\n        S = __SHSAX(S, T);\n\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = __SMUADX(S, C1) >> 16u;\n        out2 = __SMUSD(__QSUB16(0, C1), S);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */\n        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n\n        /*  Butterfly process for the i0+3fftLen/4 sample */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n        out1 = __SMUSD(C3, R) >> 16u;\n        out2 = __SMUADX(C3, R);\n\n#else\n\n        out1 = __SMUADX(C3, R) >> 16u;\n        out2 = __SMUSD(__QSUB16(0, C3), R);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */\n        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */\n        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =\n          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);\n      }\n    }\n    /*  Twiddle coefficients index modifier */\n    twidCoefModifier <<= 2u;\n  }\n  /* end of middle stage process */\n\n  /* data is in 10.6(q6) format for the 1024 point */\n  /* data is in 8.8(q8) format for the 256 point */\n  /* data is in 6.10(q10) format for the 64 point */\n  /* data is in 4.12(q12) format for the 16 point */\n\n  /*  Initializations for the last stage */\n  j = fftLen >> 2;\n\n  ptr1 = &pSrc16[0];\n\n  /* start of last stage process */\n\n  /*  Butterfly implementation */\n  do\n  {\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD32(ptr1)++;\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD32(ptr1)++;\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD32(ptr1)++;\n\n    /* Read xd (real), yd(imag) input */\n    xdyd = *__SIMD32(ptr1)++;\n\n    /* R = packed((ya + yc), (xa + xc)) */\n    R = __QADD16(xaya, xcyc);\n\n    /* T = packed((yb + yd), (xb + xd)) */\n    T = __QADD16(xbyb, xdyd);\n\n    /* pointer updation for writing */\n    ptr1 = ptr1 - 8u;\n\n\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    *__SIMD32(ptr1)++ = __SHADD16(R, T);\n\n    /* T = packed((yb + yd), (xb + xd)) */\n    T = __QADD16(xbyb, xdyd);\n\n    /* xc' = (xa-xb+xc-xd) */\n    /* yc' = (ya-yb+yc-yd) */\n    *__SIMD32(ptr1)++ = __SHSUB16(R, T);\n\n    /* S = packed((ya - yc), (xa - xc)) */\n    S = __QSUB16(xaya, xcyc);\n\n    /* Read yd (real), xd(imag) input */\n    /* T = packed( (yb - yd), (xb - xd))  */\n    U = __QSUB16(xbyb, xdyd);\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* xb' = (xa+yb-xc-yd) */\n    /* yb' = (ya-xb-yc+xd) */\n    *__SIMD32(ptr1)++ = __SHASX(S, U);\n\n\n    /* xd' = (xa-yb-xc+yd) */\n    /* yd' = (ya+xb-yc-xd) */\n    *__SIMD32(ptr1)++ = __SHSAX(S, U);\n\n#else\n\n    /* xb' = (xa+yb-xc-yd) */\n    /* yb' = (ya-xb-yc+xd) */\n    *__SIMD32(ptr1)++ = __SHSAX(S, U);\n\n\n    /* xd' = (xa-yb-xc+yd) */\n    /* yd' = (ya+xb-yc-xd) */\n    *__SIMD32(ptr1)++ = __SHASX(S, U);\n\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n  } while(--j);\n\n  /* end of last stage  process */\n\n  /* output is in 11.5(q5) format for the 1024 point */\n  /* output is in 9.7(q7) format for the 256 point   */\n  /* output is in 7.9(q9) format for the 64 point  */\n  /* output is in 5.11(q11) format for the 16 point  */\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  q15_t R0, R1, S0, S1, T0, T1, U0, U1;\n  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;\n  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;\n\n  /* Total process is divided into three stages */\n\n  /* process first stage, middle stages, & last stage */\n\n  /*  Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n\n  /* Index for twiddle coefficient */\n  ic = 0u;\n\n  /* Index for input read and output write */\n  i0 = 0u;\n\n  j = n2;\n\n  /* Input is in 1.15(q15) format */\n\n  /*  Start of first stage process */\n  do\n  {\n    /*  Butterfly implementation */\n\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n    /* input is down scale by 4 to avoid overflow */\n    /* Read ya (real), xa(imag) input */\n    T0 = pSrc16[i0 * 2u] >> 2u;\n    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;\n    /* input is down scale by 4 to avoid overflow */\n    /* Read yc (real), xc(imag) input */\n    S0 = pSrc16[i2 * 2u] >> 2u;\n    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;\n\n    /* R0 = (ya + yc), R1 = (xa + xc) */\n    R0 = __SSAT(T0 + S0, 16u);\n    R1 = __SSAT(T1 + S1, 16u);\n    /* S0 = (ya - yc), S1 = (xa - xc) */\n    S0 = __SSAT(T0 - S0, 16u);\n    S1 = __SSAT(T1 - S1, 16u);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* input is down scale by 4 to avoid overflow */\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u] >> 2u;\n    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;\n    /* Read yd (real), xd(imag) input */\n    /* input is down scale by 4 to avoid overflow */\n    U0 = pSrc16[i3 * 2u] >> 2u;\n    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;\n\n    /* T0 = (yb + yd), T1 = (xb + xd) */\n    T0 = __SSAT(T0 + U0, 16u);\n    T1 = __SSAT(T1 + U1, 16u);\n\n    /*  writing the butterfly processed i0 sample */\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);\n    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);\n\n    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */\n    R0 = __SSAT(R0 - T0, 16u);\n    R1 = __SSAT(R1 - T1, 16u);\n    /* co2 & si2 are read from Coefficient pointer */\n    Co2 = pCoef16[2u * ic * 2u];\n    Si2 = pCoef16[(2u * ic * 2u) + 1u];\n    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */\n    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);\n    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */\n    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);\n\n    /*  Reading i0+fftLen/4 */\n    /* input is down scale by 4 to avoid overflow */\n    /* T0 = yb, T1 = xb */\n    T0 = pSrc16[i1 * 2u] >> 2u;\n    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;\n\n    /* writing the butterfly processed i0 + fftLen/4 sample */\n    /* writing output(xc', yc') in little endian format */\n    pSrc16[i1 * 2u] = out1;\n    pSrc16[(i1 * 2u) + 1u] = out2;\n\n    /*  Butterfly calculations */\n    /* input is down scale by 4 to avoid overflow */\n    /* U0 = yd, U1 = xd) */\n    U0 = pSrc16[i3 * 2u] >> 2u;\n    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;\n\n    /* T0 = yb-yd, T1 = xb-xd) */\n    T0 = __SSAT(T0 - U0, 16u);\n    T1 = __SSAT(T1 - U1, 16u);\n    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */\n    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);\n    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);\n    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */\n    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);\n    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);\n\n    /* co1 & si1 are read from Coefficient pointer */\n    Co1 = pCoef16[ic * 2u];\n    Si1 = pCoef16[(ic * 2u) + 1u];\n    /*  Butterfly process for the i0+fftLen/2 sample */\n    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */\n    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);\n    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */\n    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);\n    /* writing output(xb', yb') in little endian format */\n    pSrc16[i2 * 2u] = out1;\n    pSrc16[(i2 * 2u) + 1u] = out2;\n\n    /* Co3 & si3 are read from Coefficient pointer */\n    Co3 = pCoef16[3u * ic * 2u];\n    Si3 = pCoef16[(3u * ic * 2u) + 1u];\n    /*  Butterfly process for the i0+3fftLen/4 sample */\n    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */\n    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);\n    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */\n    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);\n    /* writing output(xd', yd') in little endian format */\n    pSrc16[i3 * 2u] = out1;\n    pSrc16[(i3 * 2u) + 1u] = out2;\n\n    /*  Twiddle coefficients index modifier */\n    ic = ic + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n\n  /*  End of first stage process */\n\n  /* data is in 4.11(q11) format */\n\n\n  /*  Start of Middle stage process */\n\n  /*  Twiddle coefficients index modifier */\n  twidCoefModifier <<= 2u;\n\n  /*  Calculation of Middle stage */\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the middle stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ic = 0u;\n\n    for (j = 0u; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      Co1 = pCoef16[ic * 2u];\n      Si1 = pCoef16[(ic * 2u) + 1u];\n      Co2 = pCoef16[2u * ic * 2u];\n      Si2 = pCoef16[2u * ic * 2u + 1u];\n      Co3 = pCoef16[3u * ic * 2u];\n      Si3 = pCoef16[(3u * ic * 2u) + 1u];\n\n      /*  Twiddle coefficients index modifier */\n      ic = ic + twidCoefModifier;\n\n      /*  Butterfly implementation */\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Reading i0, i0+fftLen/2 inputs */\n        /* Read ya (real), xa(imag) input */\n        T0 = pSrc16[i0 * 2u];\n        T1 = pSrc16[(i0 * 2u) + 1u];\n\n        /* Read yc (real), xc(imag) input */\n        S0 = pSrc16[i2 * 2u];\n        S1 = pSrc16[(i2 * 2u) + 1u];\n\n\n        /* R0 = (ya + yc), R1 = (xa + xc) */\n        R0 = __SSAT(T0 + S0, 16u);\n        R1 = __SSAT(T1 + S1, 16u);\n        /* S0 = (ya - yc), S1 = (xa - xc) */\n        S0 = __SSAT(T0 - S0, 16u);\n        S1 = __SSAT(T1 - S1, 16u);\n\n        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n        /* Read yb (real), xb(imag) input */\n        T0 = pSrc16[i1 * 2u];\n        T1 = pSrc16[(i1 * 2u) + 1u];\n\n        /* Read yd (real), xd(imag) input */\n        U0 = pSrc16[i3 * 2u];\n        U1 = pSrc16[(i3 * 2u) + 1u];\n\n        /* T0 = (yb + yd), T1 = (xb + xd) */\n        T0 = __SSAT(T0 + U0, 16u);\n        T1 = __SSAT(T1 + U1, 16u);\n\n        /*  writing the butterfly processed i0 sample */\n        /* xa' = xa + xb + xc + xd */\n        /* ya' = ya + yb + yc + yd */\n        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;\n        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;\n\n        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */\n        R0 = (R0 >> 1u) - (T0 >> 1u);\n        R1 = (R1 >> 1u) - (T1 >> 1u);\n\n        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */\n        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);\n        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */\n        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);\n\n        /*  Reading i0+3fftLen/4 */\n        /* Read yb (real), xb(imag) input */\n        T0 = pSrc16[i1 * 2u];\n        T1 = pSrc16[(i1 * 2u) + 1u];\n\n        /*  writing the butterfly processed i0 + fftLen/4 sample */\n        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */\n        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */\n        pSrc16[i1 * 2u] = out1;\n        pSrc16[(i1 * 2u) + 1u] = out2;\n\n        /*  Butterfly calculations */\n        /* Read yd (real), xd(imag) input */\n        U0 = pSrc16[i3 * 2u];\n        U1 = pSrc16[(i3 * 2u) + 1u];\n\n        /* T0 = yb-yd, T1 = xb-xd) */\n        T0 = __SSAT(T0 - U0, 16u);\n        T1 = __SSAT(T1 - U1, 16u);\n\n        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */\n        R0 = (S0 >> 1u) + (T1 >> 1u);\n        R1 = (S1 >> 1u) - (T0 >> 1u);\n\n        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */\n        S0 = (S0 >> 1u) - (T1 >> 1u);\n        S1 = (S1 >> 1u) + (T0 >> 1u);\n\n        /*  Butterfly process for the i0+fftLen/2 sample */\n        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);\n        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);\n        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */\n        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */\n        pSrc16[i2 * 2u] = out1;\n        pSrc16[(i2 * 2u) + 1u] = out2;\n\n        /*  Butterfly process for the i0+3fftLen/4 sample */\n        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);\n\n        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);\n        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */\n        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */\n        pSrc16[i3 * 2u] = out1;\n        pSrc16[(i3 * 2u) + 1u] = out2;\n\n\n      }\n    }\n    /*  Twiddle coefficients index modifier */\n    twidCoefModifier <<= 2u;\n  }\n  /*  End of Middle stages process */\n\n\n  /* data is in 10.6(q6) format for the 1024 point */\n  /* data is in 8.8(q8) format for the 256 point   */\n  /* data is in 6.10(q10) format for the 64 point  */\n  /* data is in 4.12(q12) format for the 16 point  */\n\n  /* start of last stage process */\n\n\n  /*  Initializations for the last stage */\n  n1 = n2;\n  n2 >>= 2u;\n\n  /*  Butterfly implementation */\n  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)\n  {\n    /*  index calculation for the input as, */\n    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Reading i0, i0+fftLen/2 inputs */\n    /* Read ya (real), xa(imag) input */\n    T0 = pSrc16[i0 * 2u];\n    T1 = pSrc16[(i0 * 2u) + 1u];\n    /* Read yc (real), xc(imag) input */\n    S0 = pSrc16[i2 * 2u];\n    S1 = pSrc16[(i2 * 2u) + 1u];\n\n    /* R0 = (ya + yc), R1 = (xa + xc) */\n    R0 = __SSAT(T0 + S0, 16u);\n    R1 = __SSAT(T1 + S1, 16u);\n    /* S0 = (ya - yc), S1 = (xa - xc) */\n    S0 = __SSAT(T0 - S0, 16u);\n    S1 = __SSAT(T1 - S1, 16u);\n\n    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u];\n    T1 = pSrc16[(i1 * 2u) + 1u];\n    /* Read yd (real), xd(imag) input */\n    U0 = pSrc16[i3 * 2u];\n    U1 = pSrc16[(i3 * 2u) + 1u];\n\n    /* T0 = (yb + yd), T1 = (xb + xd) */\n    T0 = __SSAT(T0 + U0, 16u);\n    T1 = __SSAT(T1 + U1, 16u);\n\n    /*  writing the butterfly processed i0 sample */\n    /* xa' = xa + xb + xc + xd */\n    /* ya' = ya + yb + yc + yd */\n    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);\n    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);\n\n    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */\n    R0 = (R0 >> 1u) - (T0 >> 1u);\n    R1 = (R1 >> 1u) - (T1 >> 1u);\n\n    /* Read yb (real), xb(imag) input */\n    T0 = pSrc16[i1 * 2u];\n    T1 = pSrc16[(i1 * 2u) + 1u];\n\n    /*  writing the butterfly processed i0 + fftLen/4 sample */\n    /* xc' = (xa-xb+xc-xd) */\n    /* yc' = (ya-yb+yc-yd) */\n    pSrc16[i1 * 2u] = R0;\n    pSrc16[(i1 * 2u) + 1u] = R1;\n\n    /* Read yd (real), xd(imag) input */\n    U0 = pSrc16[i3 * 2u];\n    U1 = pSrc16[(i3 * 2u) + 1u];\n    /* T0 = (yb - yd), T1 = (xb - xd) */\n    T0 = __SSAT(T0 - U0, 16u);\n    T1 = __SSAT(T1 - U1, 16u);\n\n    /*  writing the butterfly processed i0 + fftLen/2 sample */\n    /* xb' = (xa-yb-xc+yd) */\n    /* yb' = (ya+xb-yc-xd) */\n    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);\n    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);\n\n\n    /*  writing the butterfly processed i0 + 3fftLen/4 sample */\n    /* xd' = (xa+yb-xc-yd) */\n    /* yd' = (ya-xb-yc+xd) */\n    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);\n    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);\n  }\n  /* end of last stage  process */\n\n  /* output is in 11.5(q5) format for the 1024 point */\n  /* output is in 9.7(q7) format for the 256 point   */\n  /* output is in 7.9(q9) format for the 64 point  */\n  /* output is in 5.11(q11) format for the 16 point  */\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix4_q31.c    \n*    \n* Description:\tThis file has function definition of Radix-4 FFT & IFFT function and    \n*\t\t\t\tIn-place bit reversal using bit reversal table    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid arm_radix4_butterfly_inverse_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint32_t twidCoefModifier);\n\nvoid arm_radix4_butterfly_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint32_t twidCoefModifier);\n\nvoid arm_bitreversal_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTab);\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup ComplexFFT    \n * @{    \n */\n\n/**    \n * @details    \n * @brief Processing function for the Q31 CFFT/CIFFT.    \n * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.   \n * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   \n * @return none.    \n *     \n * \\par Input and output formats:    \n * \\par    \n * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   \n * Hence the output format is different for different FFT sizes.    \n * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   \n * \\par   \n * \\image html CFFTQ31.gif \"Input and Output Formats for Q31 CFFT\"    \n * \\image html CIFFTQ31.gif \"Input and Output Formats for Q31 CIFFT\"    \n *    \n */\n\nvoid arm_cfft_radix4_q31(\n  const arm_cfft_radix4_instance_q31 * S,\n  q31_t * pSrc)\n{\n  if(S->ifftFlag == 1u)\n  {\n    /* Complex IFFT radix-4 */\n    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,\n                                     S->twidCoefModifier);\n  }\n  else\n  {\n    /* Complex FFT radix-4 */\n    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,\n                             S->twidCoefModifier);\n  }\n\n\n  if(S->bitReverseFlag == 1u)\n  {\n    /*  Bit Reversal */\n    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);\n  }\n\n}\n\n/**    \n * @} end of ComplexFFT group    \n */\n\n/*    \n* Radix-4 FFT algorithm used is :    \n*    \n* Input real and imaginary data:    \n* x(n) = xa + j * ya    \n* x(n+N/4 ) = xb + j * yb    \n* x(n+N/2 ) = xc + j * yc    \n* x(n+3N 4) = xd + j * yd    \n*    \n*    \n* Output real and imaginary data:    \n* x(4r) = xa'+ j * ya'    \n* x(4r+1) = xb'+ j * yb'    \n* x(4r+2) = xc'+ j * yc'    \n* x(4r+3) = xd'+ j * yd'    \n*    \n*    \n* Twiddle factors for radix-4 FFT:    \n* Wn = co1 + j * (- si1)    \n* W2n = co2 + j * (- si2)    \n* W3n = co3 + j * (- si3)    \n*    \n*  Butterfly implementation:    \n* xa' = xa + xb + xc + xd    \n* ya' = ya + yb + yc + yd    \n* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    \n* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    \n* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    \n* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    \n* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    \n* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    \n*    \n*/\n\n/**    \n * @brief  Core function for the Q31 CFFT butterfly process.   \n * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   \n * @param[in]      fftLen           length of the FFT.   \n * @param[in]      *pCoef           points to twiddle coefficient buffer.   \n * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.   \n */\n\nvoid arm_radix4_butterfly_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pCoef,\n  uint32_t twidCoefModifier)\n{\n  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;\n  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;\n\n  q31_t xa, xb, xc, xd;\n  q31_t ya, yb, yc, yd;\n  q31_t xa_out, xb_out, xc_out, xd_out;\n  q31_t ya_out, yb_out, yc_out, yd_out;\n\n  q31_t *ptr1;\n  q63_t xaya, xbyb, xcyc, xdyd;\n  /* Total process is divided into three stages */\n\n  /* process first stage, middle stages, & last stage */\n\n\n  /* start of first stage process */\n\n  /*  Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n  i0 = 0u;\n  ia1 = 0u;\n\n  j = n2;\n\n  /*  Calculation of first stage */\n  do\n  {\n    /*  index calculation for the input as, */\n    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /* input is in 1.31(q31) format and provide 4 guard bits for the input */\n\n    /*  Butterfly implementation */\n    /* xa + xc */\n    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);\n    /* xa - xc */\n    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);\n\n    /* xb + xd */\n    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);\n\n    /* ya + yc */\n    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);\n    /* ya - yc */\n    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);\n\n    /* xa' = xa + xb + xc + xd */\n    pSrc[2u * i0] = (r1 + t1);\n    /* (xa + xc) - (xb + xd) */\n    r1 = r1 - t1;\n    /* yb + yd */\n    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);\n\n    /* ya' = ya + yb + yc + yd */\n    pSrc[(2u * i0) + 1u] = (s1 + t2);\n\n    /* (ya + yc) - (yb + yd) */\n    s1 = s1 - t2;\n\n    /* yb - yd */\n    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);\n    /* xb - xd */\n    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);\n\n    /*  index calculation for the coefficients */\n    ia2 = 2u * ia1;\n    co2 = pCoef[ia2 * 2u];\n    si2 = pCoef[(ia2 * 2u) + 1u];\n\n    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */\n    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +\n                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;\n\n    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */\n    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -\n                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;\n\n    /* (xa - xc) + (yb - yd) */\n    r1 = r2 + t1;\n    /* (xa - xc) - (yb - yd) */\n    r2 = r2 - t1;\n\n    /* (ya - yc) - (xb - xd) */\n    s1 = s2 - t2;\n    /* (ya - yc) + (xb - xd) */\n    s2 = s2 + t2;\n\n    co1 = pCoef[ia1 * 2u];\n    si1 = pCoef[(ia1 * 2u) + 1u];\n\n    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */\n    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +\n                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;\n\n    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */\n    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -\n                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;\n\n    /*  index calculation for the coefficients */\n    ia3 = 3u * ia1;\n    co3 = pCoef[ia3 * 2u];\n    si3 = pCoef[(ia3 * 2u) + 1u];\n\n    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */\n    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +\n                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;\n\n    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */\n    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -\n                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;\n\n    /*  Twiddle coefficients index modifier */\n    ia1 = ia1 + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n\n  /* end of first stage process */\n\n  /* data is in 5.27(q27) format */\n\n\n  /* start of Middle stages process */\n\n\n  /* each stage in middle stages provides two down scaling of the input */\n\n  twidCoefModifier <<= 2u;\n\n\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the first stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ia1 = 0u;\n\n    /*  Calculation of first stage */\n    for (j = 0u; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      ia2 = ia1 + ia1;\n      ia3 = ia2 + ia1;\n      co1 = pCoef[ia1 * 2u];\n      si1 = pCoef[(ia1 * 2u) + 1u];\n      co2 = pCoef[ia2 * 2u];\n      si2 = pCoef[(ia2 * 2u) + 1u];\n      co3 = pCoef[ia3 * 2u];\n      si3 = pCoef[(ia3 * 2u) + 1u];\n      /*  Twiddle coefficients index modifier */\n      ia1 = ia1 + twidCoefModifier;\n\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Butterfly implementation */\n        /* xa + xc */\n        r1 = pSrc[2u * i0] + pSrc[2u * i2];\n        /* xa - xc */\n        r2 = pSrc[2u * i0] - pSrc[2u * i2];\n\n        /* ya + yc */\n        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];\n        /* ya - yc */\n        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];\n\n        /* xb + xd */\n        t1 = pSrc[2u * i1] + pSrc[2u * i3];\n\n        /* xa' = xa + xb + xc + xd */\n        pSrc[2u * i0] = (r1 + t1) >> 2u;\n        /* xa + xc -(xb + xd) */\n        r1 = r1 - t1;\n\n        /* yb + yd */\n        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];\n        /* ya' = ya + yb + yc + yd */\n        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;\n\n        /* (ya + yc) - (yb + yd) */\n        s1 = s1 - t2;\n\n        /* (yb - yd) */\n        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];\n        /* (xb - xd) */\n        t2 = pSrc[2u * i1] - pSrc[2u * i3];\n\n        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */\n        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +\n                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;\n\n        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */\n        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -\n                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;\n\n        /* (xa - xc) + (yb - yd) */\n        r1 = r2 + t1;\n        /* (xa - xc) - (yb - yd) */\n        r2 = r2 - t1;\n\n        /* (ya - yc) -  (xb - xd) */\n        s1 = s2 - t2;\n        /* (ya - yc) +  (xb - xd) */\n        s2 = s2 + t2;\n\n        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */\n        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +\n                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;\n\n        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */\n        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -\n                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;\n\n        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */\n        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +\n                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;\n\n        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */\n        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -\n                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;\n      }\n    }\n    twidCoefModifier <<= 2u;\n  }\n\n  /* End of Middle stages process */\n\n  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */\n  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */\n  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */\n  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */\n\n\n  /* start of Last stage process */\n  /*  Initializations for the last stage */\n  j = fftLen >> 2;\n  ptr1 = &pSrc[0];\n\n  /*  Calculations of last stage */\n  do\n  {\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD64(ptr1)++;\n    xa = (q31_t) xaya;\n    ya = (q31_t) (xaya >> 32);\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD64(ptr1)++;\n    xb = (q31_t) xbyb;\n    yb = (q31_t) (xbyb >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD64(ptr1)++;\n    xc = (q31_t) xcyc;\n    yc = (q31_t) (xcyc >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xdyd = *__SIMD64(ptr1)++;\n    xd = (q31_t) xdyd;\n    yd = (q31_t) (xdyd >> 32);\n\n#else\n\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD64(ptr1)++;\n    ya = (q31_t) xaya;\n    xa = (q31_t) (xaya >> 32);\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD64(ptr1)++;\n    yb = (q31_t) xbyb;\n    xb = (q31_t) (xbyb >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD64(ptr1)++;\n    yc = (q31_t) xcyc;\n    xc = (q31_t) (xcyc >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xdyd = *__SIMD64(ptr1)++;\n    yd = (q31_t) xdyd;\n    xd = (q31_t) (xdyd >> 32);\n\n\n#endif\n\n    /* xa' = xa + xb + xc + xd */\n    xa_out = xa + xb + xc + xd;\n\n    /* ya' = ya + yb + yc + yd */\n    ya_out = ya + yb + yc + yd;\n\n    /* pointer updation for writing */\n    ptr1 = ptr1 - 8u;\n\n    /* writing xa' and ya' */\n    *ptr1++ = xa_out;\n    *ptr1++ = ya_out;\n\n    xc_out = (xa - xb + xc - xd);\n    yc_out = (ya - yb + yc - yd);\n\n    /* writing xc' and yc' */\n    *ptr1++ = xc_out;\n    *ptr1++ = yc_out;\n\n    xb_out = (xa + yb - xc - yd);\n    yb_out = (ya - xb - yc + xd);\n\n    /* writing xb' and yb' */\n    *ptr1++ = xb_out;\n    *ptr1++ = yb_out;\n\n    xd_out = (xa - yb - xc + yd);\n    yd_out = (ya + xb - yc - xd);\n\n    /* writing xd' and yd' */\n    *ptr1++ = xd_out;\n    *ptr1++ = yd_out;\n\n\n  } while(--j);\n\n  /* output is in 11.21(q21) format for the 1024 point */\n  /* output is in 9.23(q23) format for the 256 point */\n  /* output is in 7.25(q25) format for the 64 point */\n  /* output is in 5.27(q27) format for the 16 point */\n\n  /* End of last stage process */\n\n}\n\n\n/**    \n * @brief  Core function for the Q31 CIFFT butterfly process.   \n * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   \n * @param[in]      fftLen           length of the FFT.   \n * @param[in]      *pCoef           points to twiddle coefficient buffer.   \n * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.   \n */\n\n\n/*    \n* Radix-4 IFFT algorithm used is :    \n*    \n* CIFFT uses same twiddle coefficients as CFFT Function    \n*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    \n*    \n*    \n* IFFT is implemented with following changes in equations from FFT    \n*    \n* Input real and imaginary data:    \n* x(n) = xa + j * ya    \n* x(n+N/4 ) = xb + j * yb    \n* x(n+N/2 ) = xc + j * yc    \n* x(n+3N 4) = xd + j * yd    \n*    \n*    \n* Output real and imaginary data:    \n* x(4r) = xa'+ j * ya'    \n* x(4r+1) = xb'+ j * yb'    \n* x(4r+2) = xc'+ j * yc'    \n* x(4r+3) = xd'+ j * yd'    \n*    \n*    \n* Twiddle factors for radix-4 IFFT:    \n* Wn = co1 + j * (si1)    \n* W2n = co2 + j * (si2)    \n* W3n = co3 + j * (si3)    \n    \n* The real and imaginary output values for the radix-4 butterfly are    \n* xa' = xa + xb + xc + xd    \n* ya' = ya + yb + yc + yd    \n* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    \n* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    \n* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    \n* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    \n* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    \n* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    \n*    \n*/\n\nvoid arm_radix4_butterfly_inverse_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pCoef,\n  uint32_t twidCoefModifier)\n{\n  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;\n  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;\n  q31_t xa, xb, xc, xd;\n  q31_t ya, yb, yc, yd;\n  q31_t xa_out, xb_out, xc_out, xd_out;\n  q31_t ya_out, yb_out, yc_out, yd_out;\n\n  q31_t *ptr1;\n  q63_t xaya, xbyb, xcyc, xdyd;\n\n  /* input is be 1.31(q31) format for all FFT sizes */\n  /* Total process is divided into three stages */\n  /* process first stage, middle stages, & last stage */\n\n  /* Start of first stage process */\n\n  /* Initializations for the first stage */\n  n2 = fftLen;\n  n1 = n2;\n  /* n2 = fftLen/4 */\n  n2 >>= 2u;\n  i0 = 0u;\n  ia1 = 0u;\n\n  j = n2;\n\n  do\n  {\n\n    /* input is in 1.31(q31) format and provide 4 guard bits for the input */\n\n    /*  index calculation for the input as, */\n    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */\n    i1 = i0 + n2;\n    i2 = i1 + n2;\n    i3 = i2 + n2;\n\n    /*  Butterfly implementation */\n    /* xa + xc */\n    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);\n    /* xa - xc */\n    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);\n\n    /* xb + xd */\n    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);\n\n    /* ya + yc */\n    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);\n    /* ya - yc */\n    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);\n\n    /* xa' = xa + xb + xc + xd */\n    pSrc[2u * i0] = (r1 + t1);\n    /* (xa + xc) - (xb + xd) */\n    r1 = r1 - t1;\n    /* yb + yd */\n    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);\n    /* ya' = ya + yb + yc + yd */\n    pSrc[(2u * i0) + 1u] = (s1 + t2);\n\n    /* (ya + yc) - (yb + yd) */\n    s1 = s1 - t2;\n\n    /* yb - yd */\n    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);\n    /* xb - xd */\n    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);\n\n    /*  index calculation for the coefficients */\n    ia2 = 2u * ia1;\n    co2 = pCoef[ia2 * 2u];\n    si2 = pCoef[(ia2 * 2u) + 1u];\n\n    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -\n                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;\n\n    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +\n                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;\n\n    /* (xa - xc) - (yb - yd) */\n    r1 = r2 - t1;\n    /* (xa - xc) + (yb - yd) */\n    r2 = r2 + t1;\n\n    /* (ya - yc) + (xb - xd) */\n    s1 = s2 + t2;\n    /* (ya - yc) - (xb - xd) */\n    s2 = s2 - t2;\n\n    co1 = pCoef[ia1 * 2u];\n    si1 = pCoef[(ia1 * 2u) + 1u];\n\n    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -\n                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;\n\n    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +\n                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;\n\n    /*  index calculation for the coefficients */\n    ia3 = 3u * ia1;\n    co3 = pCoef[ia3 * 2u];\n    si3 = pCoef[(ia3 * 2u) + 1u];\n\n    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -\n                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;\n\n    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +\n                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;\n\n    /*  Twiddle coefficients index modifier */\n    ia1 = ia1 + twidCoefModifier;\n\n    /*  Updating input index */\n    i0 = i0 + 1u;\n\n  } while(--j);\n\n  /* data is in 5.27(q27) format */\n  /* each stage provides two down scaling of the input */\n\n\n  /* Start of Middle stages process */\n\n  twidCoefModifier <<= 2u;\n\n  /*  Calculation of second stage to excluding last stage */\n  for (k = fftLen / 4u; k > 4u; k >>= 2u)\n  {\n    /*  Initializations for the first stage */\n    n1 = n2;\n    n2 >>= 2u;\n    ia1 = 0u;\n\n    for (j = 0; j <= (n2 - 1u); j++)\n    {\n      /*  index calculation for the coefficients */\n      ia2 = ia1 + ia1;\n      ia3 = ia2 + ia1;\n      co1 = pCoef[ia1 * 2u];\n      si1 = pCoef[(ia1 * 2u) + 1u];\n      co2 = pCoef[ia2 * 2u];\n      si2 = pCoef[(ia2 * 2u) + 1u];\n      co3 = pCoef[ia3 * 2u];\n      si3 = pCoef[(ia3 * 2u) + 1u];\n      /*  Twiddle coefficients index modifier */\n      ia1 = ia1 + twidCoefModifier;\n\n      for (i0 = j; i0 < fftLen; i0 += n1)\n      {\n        /*  index calculation for the input as, */\n        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */\n        i1 = i0 + n2;\n        i2 = i1 + n2;\n        i3 = i2 + n2;\n\n        /*  Butterfly implementation */\n        /* xa + xc */\n        r1 = pSrc[2u * i0] + pSrc[2u * i2];\n        /* xa - xc */\n        r2 = pSrc[2u * i0] - pSrc[2u * i2];\n\n        /* ya + yc */\n        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];\n        /* ya - yc */\n        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];\n\n        /* xb + xd */\n        t1 = pSrc[2u * i1] + pSrc[2u * i3];\n\n        /* xa' = xa + xb + xc + xd */\n        pSrc[2u * i0] = (r1 + t1) >> 2u;\n        /* xa + xc -(xb + xd) */\n        r1 = r1 - t1;\n        /* yb + yd */\n        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];\n        /* ya' = ya + yb + yc + yd */\n        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;\n\n        /* (ya + yc) - (yb + yd) */\n        s1 = s1 - t2;\n\n        /* (yb - yd) */\n        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];\n        /* (xb - xd) */\n        t2 = pSrc[2u * i1] - pSrc[2u * i3];\n\n        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */\n        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -\n                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;\n\n        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */\n        pSrc[(2u * i1) + 1u] =\n          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +\n           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;\n\n        /* (xa - xc) - (yb - yd) */\n        r1 = r2 - t1;\n        /* (xa - xc) + (yb - yd) */\n        r2 = r2 + t1;\n\n        /* (ya - yc) +  (xb - xd) */\n        s1 = s2 + t2;\n        /* (ya - yc) -  (xb - xd) */\n        s2 = s2 - t2;\n\n        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */\n        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -\n                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;\n\n        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */\n        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +\n                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;\n\n        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */\n        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -\n                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;\n\n        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */\n        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +\n                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;\n      }\n    }\n    twidCoefModifier <<= 2u;\n  }\n\n  /* End of Middle stages process */\n\n  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */\n  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */\n  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */\n  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */\n\n\n  /* Start of last stage process */\n\n\n  /*  Initializations for the last stage */\n  j = fftLen >> 2;\n  ptr1 = &pSrc[0];\n\n  /*  Calculations of last stage */\n  do\n  {\n#ifndef ARM_MATH_BIG_ENDIAN\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD64(ptr1)++;\n    xa = (q31_t) xaya;\n    ya = (q31_t) (xaya >> 32);\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD64(ptr1)++;\n    xb = (q31_t) xbyb;\n    yb = (q31_t) (xbyb >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD64(ptr1)++;\n    xc = (q31_t) xcyc;\n    yc = (q31_t) (xcyc >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xdyd = *__SIMD64(ptr1)++;\n    xd = (q31_t) xdyd;\n    yd = (q31_t) (xdyd >> 32);\n\n#else\n\n    /* Read xa (real), ya(imag) input */\n    xaya = *__SIMD64(ptr1)++;\n    ya = (q31_t) xaya;\n    xa = (q31_t) (xaya >> 32);\n\n    /* Read xb (real), yb(imag) input */\n    xbyb = *__SIMD64(ptr1)++;\n    yb = (q31_t) xbyb;\n    xb = (q31_t) (xbyb >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xcyc = *__SIMD64(ptr1)++;\n    yc = (q31_t) xcyc;\n    xc = (q31_t) (xcyc >> 32);\n\n    /* Read xc (real), yc(imag) input */\n    xdyd = *__SIMD64(ptr1)++;\n    yd = (q31_t) xdyd;\n    xd = (q31_t) (xdyd >> 32);\n\n\n#endif\n\n    /* xa' = xa + xb + xc + xd */\n    xa_out = xa + xb + xc + xd;\n\n    /* ya' = ya + yb + yc + yd */\n    ya_out = ya + yb + yc + yd;\n\n    /* pointer updation for writing */\n    ptr1 = ptr1 - 8u;\n\n    /* writing xa' and ya' */\n    *ptr1++ = xa_out;\n    *ptr1++ = ya_out;\n\n    xc_out = (xa - xb + xc - xd);\n    yc_out = (ya - yb + yc - yd);\n\n    /* writing xc' and yc' */\n    *ptr1++ = xc_out;\n    *ptr1++ = yc_out;\n\n    xb_out = (xa - yb - xc + yd);\n    yb_out = (ya + xb - yc - xd);\n\n    /* writing xb' and yb' */\n    *ptr1++ = xb_out;\n    *ptr1++ = yb_out;\n\n    xd_out = (xa + yb - xc - yd);\n    yd_out = (ya - xb - yc + xd);\n\n    /* writing xd' and yd' */\n    *ptr1++ = xd_out;\n    *ptr1++ = yd_out;\n\n\n  } while(--j);\n\n  /* output is in 11.21(q21) format for the 1024 point */\n  /* output is in 9.23(q23) format for the 256 point */\n  /* output is in 7.25(q25) format for the 64 point */\n  /* output is in 5.27(q27) format for the 16 point */\n\n  /* End of last stage process */\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_radix8_f32.c    \n*    \n* Description:\tRadix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function        \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.      \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n* @ingroup groupTransforms    \n*/\n\n/**    \n* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions    \n*    \n* \\par    \n* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).    \n* Computational complexity of CFFT reduces drastically when compared to DFT.    \n* \\par    \n* This set of functions implements CFFT/CIFFT    \n* for floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.    \n* Complex input is stored in input buffer in an interleaved fashion.    \n*    \n* \\par    \n* The functions operate on blocks of input and output data and each call to the function processes    \n* 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.    \n* \\par   \n* The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.    \n* 
 {real[0], imag[0], real[1], imag[1],..} 
    \n*    \n* \\par Lengths supported by the transform:   \n* \\par    \n* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm    \n* and the size of the FFT supported are of the lengths [ 64, 512, 4096].   \n*     \n*    \n* \\par Algorithm:    \n*    \n* Complex Fast Fourier Transform:    \n* \\par     \n* Input real and imaginary data:    \n* 
    \n* x(n) = xa + j * ya    \n* x(n+N/4 ) = xb + j * yb    \n* x(n+N/2 ) = xc + j * yc    \n* x(n+3N 4) = xd + j * yd    \n* 
    \n* where N is length of FFT    \n* \\par    \n* Output real and imaginary data:    \n* 
    \n* X(4r) = xa'+ j * ya'    \n* X(4r+1) = xb'+ j * yb'    \n* X(4r+2) = xc'+ j * yc'    \n* X(4r+3) = xd'+ j * yd'    \n* 
    \n* \\par    \n* Twiddle factors for Radix-8 FFT:    \n* 
    \n* Wn = co1 + j * (- si1)    \n* W2n = co2 + j * (- si2)    \n* W3n = co3 + j * (- si3)    \n* 
    \n*    \n* \\par    \n* \\image html CFFT.gif \"Radix-8 Decimation-in Frequency Complex Fast Fourier Transform\"    \n*    \n* \\par    \n* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.    \n* \\par    \n*  Butterfly CFFT equations:    \n* 
    \n* xa' = xa + xb + xc + xd    \n* ya' = ya + yb + yc + yd    \n* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    \n* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    \n* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    \n* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    \n* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    \n* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    \n* 
    \n*    \n* \\par    \n* where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);    \n* bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);     \n* pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.    \n* twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;     \n* pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.    \n* onebyfftLen value of 1/fftLen to calculate CIFFT;    \n*   \n* \\par Fixed-Point Behavior    \n* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.    \n* Refer to the function specific documentation below for usage guidelines.    \n*/\n\n\n/*    \n* @brief  Core function for the floating-point CFFT butterfly process.   \n* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   \n* @param[in]      fftLen           length of the FFT.   \n* @param[in]      *pCoef           points to the twiddle coefficient buffer.   \n* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n* @return none.   \n*/\n\nvoid arm_radix8_butterfly_f32(\nfloat32_t * pSrc,\nuint16_t fftLen,\nconst float32_t * pCoef,\nuint16_t twidCoefModifier)\n{\n   uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;\n   uint32_t i1, i2, i3, i4, i5, i6, i7, i8;\n   uint32_t id;\n   uint32_t n1, n2, j;\n   \n   float32_t r1, r2, r3, r4, r5, r6, r7, r8;\n   float32_t t1, t2;\n   float32_t s1, s2, s3, s4, s5, s6, s7, s8;\n   float32_t p1, p2, p3, p4;\n   float32_t co2, co3, co4, co5, co6, co7, co8;\n   float32_t si2, si3, si4, si5, si6, si7, si8;\n   const float32_t C81 = 0.70710678118f;\n\n   n2 = fftLen;\n   \n   do \n   {\n      n1 = n2;\n      n2 = n2 >> 3;\n      i1 = 0;\n      \n      do\n      {\n         i2 = i1 + n2;\n         i3 = i2 + n2;\n         i4 = i3 + n2;\n         i5 = i4 + n2;\n         i6 = i5 + n2;\n         i7 = i6 + n2;\n         i8 = i7 + n2;\n         r1 = pSrc[2 * i1] + pSrc[2 * i5];\n         r5 = pSrc[2 * i1] - pSrc[2 * i5];\n         r2 = pSrc[2 * i2] + pSrc[2 * i6];\n         r6 = pSrc[2 * i2] - pSrc[2 * i6];\n         r3 = pSrc[2 * i3] + pSrc[2 * i7];\n         r7 = pSrc[2 * i3] - pSrc[2 * i7];\n         r4 = pSrc[2 * i4] + pSrc[2 * i8];\n         r8 = pSrc[2 * i4] - pSrc[2 * i8];\n         t1 = r1 - r3;\n         r1 = r1 + r3;\n         r3 = r2 - r4;\n         r2 = r2 + r4;\n         pSrc[2 * i1] = r1 + r2;   \n         pSrc[2 * i5] = r1 - r2;\n         r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];\n         s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];\n         r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];\n         s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];\n         s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];\n         s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];\n         r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];\n         s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];\n         t2 = r1 - s3;\n         r1 = r1 + s3;\n         s3 = r2 - r4;\n         r2 = r2 + r4;\n         pSrc[2 * i1 + 1] = r1 + r2;\n         pSrc[2 * i5 + 1] = r1 - r2;\n         pSrc[2 * i3]     = t1 + s3;\n         pSrc[2 * i7]     = t1 - s3;\n         pSrc[2 * i3 + 1] = t2 - r3;\n         pSrc[2 * i7 + 1] = t2 + r3;\n         r1 = (r6 - r8) * C81;\n         r6 = (r6 + r8) * C81;\n         r2 = (s6 - s8) * C81;\n         s6 = (s6 + s8) * C81;\n         t1 = r5 - r1;\n         r5 = r5 + r1;\n         r8 = r7 - r6;\n         r7 = r7 + r6;\n         t2 = s5 - r2;\n         s5 = s5 + r2;\n         s8 = s7 - s6;\n         s7 = s7 + s6;\n         pSrc[2 * i2]     = r5 + s7;\n         pSrc[2 * i8]     = r5 - s7;\n         pSrc[2 * i6]     = t1 + s8;\n         pSrc[2 * i4]     = t1 - s8;\n         pSrc[2 * i2 + 1] = s5 - r7;\n         pSrc[2 * i8 + 1] = s5 + r7;\n         pSrc[2 * i6 + 1] = t2 - r8;\n         pSrc[2 * i4 + 1] = t2 + r8;\n         \n         i1 += n1;\n      } while(i1 < fftLen);\n      \n      if(n2 < 8)\n         break;\n      \n      ia1 = 0;\n      j = 1;\n      \n      do\n      {      \n         /*  index calculation for the coefficients */\n         id  = ia1 + twidCoefModifier;\n         ia1 = id;\n         ia2 = ia1 + id;\n         ia3 = ia2 + id;\n         ia4 = ia3 + id;\n         ia5 = ia4 + id;\n         ia6 = ia5 + id;\n         ia7 = ia6 + id;\n                  \n         co2 = pCoef[2 * ia1];\n         co3 = pCoef[2 * ia2];\n         co4 = pCoef[2 * ia3];\n         co5 = pCoef[2 * ia4];\n         co6 = pCoef[2 * ia5];\n         co7 = pCoef[2 * ia6];\n         co8 = pCoef[2 * ia7];\n         si2 = pCoef[2 * ia1 + 1];\n         si3 = pCoef[2 * ia2 + 1];\n         si4 = pCoef[2 * ia3 + 1];\n         si5 = pCoef[2 * ia4 + 1];\n         si6 = pCoef[2 * ia5 + 1];\n         si7 = pCoef[2 * ia6 + 1];\n         si8 = pCoef[2 * ia7 + 1];         \n         \n         i1 = j;\n         \n         do\n         {\n            /*  index calculation for the input */\n            i2 = i1 + n2;\n            i3 = i2 + n2;\n            i4 = i3 + n2;\n            i5 = i4 + n2;\n            i6 = i5 + n2;\n            i7 = i6 + n2;\n            i8 = i7 + n2;\n            r1 = pSrc[2 * i1] + pSrc[2 * i5];\n            r5 = pSrc[2 * i1] - pSrc[2 * i5];\n            r2 = pSrc[2 * i2] + pSrc[2 * i6];\n            r6 = pSrc[2 * i2] - pSrc[2 * i6];\n            r3 = pSrc[2 * i3] + pSrc[2 * i7];\n            r7 = pSrc[2 * i3] - pSrc[2 * i7];\n            r4 = pSrc[2 * i4] + pSrc[2 * i8];\n            r8 = pSrc[2 * i4] - pSrc[2 * i8];\n            t1 = r1 - r3;\n            r1 = r1 + r3;\n            r3 = r2 - r4;\n            r2 = r2 + r4;\n            pSrc[2 * i1] = r1 + r2;\n            r2 = r1 - r2;\n            s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];\n            s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];\n            s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];\n            s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];\n            s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];\n            s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];\n            s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];\n            s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];\n            t2 = s1 - s3;\n            s1 = s1 + s3;\n            s3 = s2 - s4;\n            s2 = s2 + s4;\n            r1 = t1 + s3;\n            t1 = t1 - s3;\n            pSrc[2 * i1 + 1] = s1 + s2;\n            s2 = s1 - s2;\n            s1 = t2 - r3;\n            t2 = t2 + r3;\n            p1 = co5 * r2;\n            p2 = si5 * s2;\n            p3 = co5 * s2;\n            p4 = si5 * r2;\n            pSrc[2 * i5]     = p1 + p2;\n            pSrc[2 * i5 + 1] = p3 - p4;\n            p1 = co3 * r1;\n            p2 = si3 * s1;\n            p3 = co3 * s1;\n            p4 = si3 * r1;\n            pSrc[2 * i3]     = p1 + p2;\n            pSrc[2 * i3 + 1] = p3 - p4;\n            p1 = co7 * t1;\n            p2 = si7 * t2;\n            p3 = co7 * t2;\n            p4 = si7 * t1;\n            pSrc[2 * i7]     = p1 + p2;\n            pSrc[2 * i7 + 1] = p3 - p4;\n            r1 = (r6 - r8) * C81;\n            r6 = (r6 + r8) * C81;\n            s1 = (s6 - s8) * C81;\n            s6 = (s6 + s8) * C81;\n            t1 = r5 - r1;\n            r5 = r5 + r1;\n            r8 = r7 - r6;\n            r7 = r7 + r6;\n            t2 = s5 - s1;\n            s5 = s5 + s1;\n            s8 = s7 - s6;\n            s7 = s7 + s6;\n            r1 = r5 + s7;\n            r5 = r5 - s7;\n            r6 = t1 + s8;\n            t1 = t1 - s8;\n            s1 = s5 - r7;\n            s5 = s5 + r7;\n            s6 = t2 - r8;\n            t2 = t2 + r8;\n            p1 = co2 * r1;\n            p2 = si2 * s1;\n            p3 = co2 * s1;\n            p4 = si2 * r1;\n            pSrc[2 * i2]     = p1 + p2;\n            pSrc[2 * i2 + 1] = p3 - p4;\n            p1 = co8 * r5;\n            p2 = si8 * s5;\n            p3 = co8 * s5;\n            p4 = si8 * r5;\n            pSrc[2 * i8]     = p1 + p2;\n            pSrc[2 * i8 + 1] = p3 - p4;\n            p1 = co6 * r6;\n            p2 = si6 * s6;\n            p3 = co6 * s6;\n            p4 = si6 * r6;\n            pSrc[2 * i6]     = p1 + p2;\n            pSrc[2 * i6 + 1] = p3 - p4;\n            p1 = co4 * t1;\n            p2 = si4 * t2;\n            p3 = co4 * t2;\n            p4 = si4 * t1;\n            pSrc[2 * i4]     = p1 + p2;\n            pSrc[2 * i4 + 1] = p3 - p4;\n            \n            i1 += n1;\n         } while(i1 < fftLen);\n         \n         j++;\n      } while(j < n2);\n      \n      twidCoefModifier <<= 3;\n   } while(n2 > 7);   \n}\n\n/**    \n* @} end of Radix8_CFFT_CIFFT group    \n*/\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_f32.c    \n*    \n* Description:\tProcessing function of DCT4 & IDCT4 F32.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.      \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @defgroup DCT4_IDCT4 DCT Type IV Functions    \n * Representation of signals by minimum number of values is important for storage and transmission.    \n * The possibility of large discontinuity between the beginning and end of a period of a signal    \n * in DFT can be avoided by extending the signal so that it is even-symmetric.    \n * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the    \n * spectrum and is very widely used in signal and image coding applications.    \n * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.    \n * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.    \n *    \n * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.    \n * Reordering of the input data makes the computation of DCT just a problem of    \n * computing the DFT of a real signal with a few additional operations.    \n * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.    \n *     \n * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.    \n * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.    \n * DCT2 implementation can be described in the following steps:    \n * - Re-ordering input    \n * - Calculating Real FFT    \n * - Multiplication of weights and Real FFT output and getting real part from the product.    \n *    \n * This process is explained by the block diagram below:    \n * \\image html DCT4.gif \"Discrete Cosine Transform - type-IV\"    \n *    \n * \\par Algorithm:    \n * The N-point type-IV DCT is defined as a real, linear transformation by the formula:    \n * \\image html DCT4Equation.gif    \n * where k = 0,1,2,.....N-1    \n *\\par    \n * Its inverse is defined as follows:    \n * \\image html IDCT4Equation.gif    \n * where n = 0,1,2,.....N-1    \n *\\par    \n * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).    \n * The symmetry of the transform matrix indicates that the fast algorithms for the forward    \n * and inverse transform computation are identical.    \n * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.    \n *    \n * \\par Lengths supported by the transform:    \n *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().    \n * The library provides separate functions for Q15, Q31, and floating-point data types.    \n * \\par Instance Structure    \n * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.    \n * A separate instance structure must be defined for each transform.    \n * There are separate instance structure declarations for each of the 3 supported data types.    \n *    \n * \\par Initialization Functions    \n * There is also an associated initialization function for each data type.    \n * The initialization function performs the following operations:    \n * - Sets the values of the internal structure fields.    \n * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().    \n * \\par    \n * Use of the initialization function is optional.    \n * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    \n * To place an instance structure into a const data section, the instance structure must be manually initialized.    \n * Manually initialize the instance structure as follows:    \n * 
    \n *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    \n *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   \n *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   \n * 
   \n * where \\c N is the length of the DCT4; \\c Nby2 is half of the length of the DCT4;   \n * \\c normalize is normalizing factor used and is equal to sqrt(2/N);    \n * \\c pTwiddle points to the twiddle factor table;   \n * \\c pCosFactor points to the cosFactor table;   \n * \\c pRfft points to the real FFT instance;   \n * \\c pCfft points to the complex FFT instance;   \n * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()   \n * and arm_rfft_f32() respectively for details regarding static initialization.   \n *   \n * \\par Fixed-Point Behavior    \n * Care must be taken when using the fixed-point versions of the DCT4 transform functions.    \n * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    \n * Refer to the function specific documentation below for usage guidelines.    \n */\n\n /**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/**    \n * @brief Processing function for the floating-point DCT4/IDCT4.   \n * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.   \n * @param[in]       *pState        points to state buffer.   \n * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   \n * @return none.   \n */\n\nvoid arm_dct4_f32(\n  const arm_dct4_instance_f32 * S,\n  float32_t * pState,\n  float32_t * pInlineBuffer)\n{\n  uint32_t i;                                    /* Loop counter */\n  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */\n  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */\n  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */\n  float32_t in;                                  /* Temporary variable */\n\n\n  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    \n   * along with some pre-processing and post-processing.    \n   * Computational procedure is explained as follows:    \n   * (a) Pre-processing involves multiplying input with cos factor,    \n   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    \n   *              where,    \n   *                 r(n) -- output of preprocessing    \n   *                 u(n) -- input to preprocessing(actual Source buffer)    \n   * (b) Calculation of DCT2 using FFT is divided into three steps:    \n   *                  Step1: Re-ordering of even and odd elements of input.    \n   *                  Step2: Calculating FFT of the re-ordered input.    \n   *                  Step3: Taking the real part of the product of FFT output and weights.    \n   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    \n   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *                        where,    \n   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    \n   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    \n   */\n\n        /*-------- Pre-processing ------------*/\n  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */\n  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);\n  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);\n\n  /* ----------------------------------------------------------------    \n   * Step1: Re-ordering of even and odd elements as,    \n   *             pState[i] =  pInlineBuffer[2*i] and    \n   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    \n   ---------------------------------------------------------------------*/\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */\n  pS2 = pState + (S->N - 1u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */\n  i = (uint32_t) S->Nby2 >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = (uint32_t) S->N >> 2u;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.    \n   * Compute 4 outputs at a time */\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);\n\n        /*----------------------------------------------------------------------    \n\t *  Step3: Multiply the FFT output with the weights.    \n\t *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */\n  i = ((uint32_t) S->N - 1u) >> 2u;\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ * (float32_t) 0.5;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  i = ((uint32_t) S->N - 1u) % 0x4u;\n\n  while(i > 0u)\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n\n        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = (uint32_t) S->N >> 2u;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = in * S->normalize;\n\n    in = *pbuff;\n    *pbuff++ = in * S->normalize;\n\n    in = *pbuff;\n    *pbuff++ = in * S->normalize;\n\n    in = *pbuff;\n    *pbuff++ = in * S->normalize;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Initializing the loop counter to N/2 */\n  i = (uint32_t) S->Nby2;\n\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter */\n  i = (uint32_t) S->N;\n\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);\n\n        /*----------------------------------------------------------------------    \n\t *  Step3: Multiply the FFT output with the weights.    \n\t *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ * (float32_t) 0.5;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  /* Initializing the loop counter */\n  i = ((uint32_t) S->N - 1u);\n\n  do\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter */\n  i = (uint32_t) S->N;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = in * S->normalize;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_init_f32.c    \n*    \n* Description:\tInitialization function of DCT-4 & IDCT4 F32    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/*    \n* @brief  Weights Table    \n*/\n\n/**    \n* \\par    \n* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    \n* \\par    \n* C command to generate the table    \n* 
    \n* for(i = 0; i< N; i++)    \n* {    \n*    weights[2*i]= cos(i*c);    \n*    weights[(2*i)+1]= -sin(i * c);    \n* } 
    \n* \\par    \n* Where N is the Number of weights to be calculated and c is pi/(2*N)    \n* \\par    \n* In the tables below the real and imaginary values are placed alternatively, hence the    \n* array length is 2*N.    \n*/\n\nstatic const float32_t Weights_128[256] = {\n  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,\n  -0.012271538285719925f,\n  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,\n  -0.036807222941358832f,\n  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,\n  -0.061320736302208578f,\n  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,\n  -0.085797312344439894f,\n  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,\n  -0.110222207293883060f,\n  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,\n  -0.134580708507126170f,\n  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,\n  -0.158858143333861450f,\n  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,\n  -0.183039887955140950f,\n  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,\n  -0.207111376192218560f,\n  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,\n  -0.231058108280671110f,\n  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,\n  -0.254865659604514570f,\n  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,\n  -0.278519689385053060f,\n  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,\n  -0.302005949319228080f,\n  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,\n  -0.325310292162262930f,\n  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,\n  -0.348418680249434560f,\n  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,\n  -0.371317193951837540f,\n  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,\n  -0.393992040061048100f,\n  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,\n  -0.416429560097637150f,\n  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,\n  -0.438616238538527660f,\n  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,\n  -0.460538710958240010f,\n  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,\n  -0.482183772079122720f,\n  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,\n  -0.503538383725717580f,\n  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,\n  -0.524589682678468950f,\n  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,\n  -0.545324988422046460f,\n  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,\n  -0.565731810783613120f,\n  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,\n  -0.585797857456438860f,\n  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,\n  -0.605511041404325550f,\n  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,\n  -0.624859488142386340f,\n  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,\n  -0.643831542889791390f,\n  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,\n  -0.662415777590171780f,\n  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,\n  -0.680600997795453020f,\n  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,\n  -0.698376249408972920f,\n  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,\n  -0.715730825283818590f,\n  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,\n  -0.732654271672412820f,\n  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,\n  -0.749136394523459260f,\n  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,\n  -0.765167265622458960f,\n  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,\n  -0.780737228572094380f,\n  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,\n  -0.795836904608883460f,\n  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,\n  -0.810457198252594770f,\n  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,\n  -0.824589302785025290f,\n  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,\n  -0.838224705554837970f,\n  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,\n  -0.851355193105265200f,\n  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,\n  -0.863972856121586700f,\n  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,\n  -0.876070094195406600f,\n  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,\n  -0.887639620402853930f,\n  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,\n  -0.898674465693953820f,\n  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,\n  -0.909167983090522270f,\n  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,\n  -0.919113851690057770f,\n  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,\n  -0.928506080473215480f,\n  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,\n  -0.937339011912574960f,\n  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,\n  -0.945607325380521280f,\n  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,\n  -0.953306040354193750f,\n  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,\n  -0.960430519415565790f,\n  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,\n  -0.966976471044852070f,\n  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,\n  -0.972939952205560070f,\n  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,\n  -0.978317370719627650f,\n  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,\n  -0.983105487431216290f,\n  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,\n  -0.987301418157858430f,\n  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,\n  -0.990902635427780010f,\n  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,\n  -0.993906970002356060f,\n  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,\n  -0.996312612182778000f,\n  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,\n  -0.998118112900149180f,\n  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,\n  -0.999322384588349540f,\n  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,\n  -0.999924701839144500f\n};\n\nstatic const float32_t Weights_512[1024] = {\n  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,\n  -0.003067956762965976f,\n  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,\n  -0.009203754782059819f,\n  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,\n  -0.015339206284988100f,\n  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,\n  -0.021474080275469508f,\n  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,\n  -0.027608145778965740f,\n  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,\n  -0.033741171851377580f,\n  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,\n  -0.039872927587739811f,\n  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,\n  -0.046003182130914623f,\n  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,\n  -0.052131704680283324f,\n  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,\n  -0.058258264500435752f,\n  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,\n  -0.064382630929857465f,\n  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,\n  -0.070504573389613856f,\n  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,\n  -0.076623861392031492f,\n  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,\n  -0.082740264549375692f,\n  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,\n  -0.088853552582524600f,\n  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,\n  -0.094963495329638992f,\n  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,\n  -0.101069862754827820f,\n  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,\n  -0.107172424956808840f,\n  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,\n  -0.113270952177564350f,\n  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,\n  -0.119365214810991350f,\n  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,\n  -0.125454983411546230f,\n  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,\n  -0.131540028702883120f,\n  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,\n  -0.137620121586486040f,\n  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,\n  -0.143695033150294470f,\n  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,\n  -0.149764534677321510f,\n  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,\n  -0.155828397654265230f,\n  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,\n  -0.161886393780111830f,\n  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,\n  -0.167938294974731170f,\n  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,\n  -0.173983873387463820f,\n  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,\n  -0.180022901405699510f,\n  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,\n  -0.186055151663446630f,\n  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,\n  -0.192080397049892440f,\n  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,\n  -0.198098410717953560f,\n  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,\n  -0.204108966092816870f,\n  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,\n  -0.210111836880469610f,\n  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,\n  -0.216106797076219520f,\n  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,\n  -0.222093620973203510f,\n  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,\n  -0.228072083170885730f,\n  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,\n  -0.234041958583543430f,\n  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,\n  -0.240003022448741500f,\n  0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,\n  -0.245955050335794590f,\n  0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,\n  -0.251897818154216970f,\n  0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,\n  -0.257831102162158990f,\n  0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,\n  -0.263754678974831350f,\n  0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f,\n  -0.269668325572915090f,\n  0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f,\n  -0.275571819310958140f,\n  0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f,\n  -0.281464937925757940f,\n  0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f,\n  -0.287347459544729510f,\n  0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f,\n  -0.293219162694258630f,\n  0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f,\n  -0.299079826308040480f,\n  0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f,\n  -0.304929229735402370f,\n  0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f,\n  -0.310767152749611470f,\n  0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f,\n  -0.316593375556165850f,\n  0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f,\n  -0.322407678801069850f,\n  0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f,\n  -0.328209843579092500f,\n  0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f,\n  -0.333999651442009380f,\n  0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f,\n  -0.339776884406826850f,\n  0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f,\n  -0.345541324963989090f,\n  0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f,\n  -0.351292756085567090f,\n  0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f,\n  -0.357030961233429980f,\n  0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f,\n  -0.362755724367397230f,\n  0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f,\n  -0.368466829953372320f,\n  0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f,\n  -0.374164062971457930f,\n  0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f,\n  -0.379847208924051160f,\n  0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f,\n  -0.385516053843918850f,\n  0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f,\n  -0.391170384302253870f,\n  0.919113851690057770f, -0.393992040061048100f, 0.917900775621390500f,\n  -0.396809987416710310f,\n  0.916679059921042700f, -0.399624199845646790f, 0.915448716088267830f,\n  -0.402434650859418430f,\n  0.914209755703530690f, -0.405241314004989860f, 0.912962190428398210f,\n  -0.408044162864978690f,\n  0.911706032005429880f, -0.410843171057903910f, 0.910441292258067250f,\n  -0.413638312238434500f,\n  0.909167983090522380f, -0.416429560097637150f, 0.907886116487666260f,\n  -0.419216888363223910f,\n  0.906595704514915330f, -0.422000270799799680f, 0.905296759318118820f,\n  -0.424779681209108810f,\n  0.903989293123443340f, -0.427555093430282080f, 0.902673318237258830f,\n  -0.430326481340082610f,\n  0.901348847046022030f, -0.433093818853151960f, 0.900015892016160280f,\n  -0.435857079922255470f,\n  0.898674465693953820f, -0.438616238538527660f, 0.897324580705418320f,\n  -0.441371268731716670f,\n  0.895966249756185220f, -0.444122144570429200f, 0.894599485631382700f,\n  -0.446868840162374160f,\n  0.893224301195515320f, -0.449611329654606540f, 0.891840709392342720f,\n  -0.452349587233770890f,\n  0.890448723244757880f, -0.455083587126343840f, 0.889048355854664570f,\n  -0.457813303598877170f,\n  0.887639620402853930f, -0.460538710958240010f, 0.886222530148880640f,\n  -0.463259783551860150f,\n  0.884797098430937790f, -0.465976495767966180f, 0.883363338665731580f,\n  -0.468688822035827900f,\n  0.881921264348355050f, -0.471396736825997640f, 0.880470889052160750f,\n  -0.474100214650549970f,\n  0.879012226428633530f, -0.476799230063322090f, 0.877545290207261350f,\n  -0.479493757660153010f,\n  0.876070094195406600f, -0.482183772079122720f, 0.874586652278176110f,\n  -0.484869248000791060f,\n  0.873094978418290090f, -0.487550160148436000f, 0.871595086655950980f,\n  -0.490226483288291160f,\n  0.870086991108711460f, -0.492898192229784040f, 0.868570705971340900f,\n  -0.495565261825772540f,\n  0.867046245515692650f, -0.498227666972781870f, 0.865513624090569090f,\n  -0.500885382611240710f,\n  0.863972856121586810f, -0.503538383725717580f, 0.862423956111040610f,\n  -0.506186645345155230f,\n  0.860866938637767310f, -0.508830142543106990f, 0.859301818357008470f,\n  -0.511468850437970300f,\n  0.857728610000272120f, -0.514102744193221660f, 0.856147328375194470f,\n  -0.516731799017649870f,\n  0.854557988365400530f, -0.519355990165589640f, 0.852960604930363630f,\n  -0.521975292937154390f,\n  0.851355193105265200f, -0.524589682678468950f, 0.849741768000852550f,\n  -0.527199134781901280f,\n  0.848120344803297230f, -0.529803624686294610f, 0.846490938774052130f,\n  -0.532403127877197900f,\n  0.844853565249707120f, -0.534997619887097150f, 0.843208239641845440f,\n  -0.537587076295645390f,\n  0.841554977436898440f, -0.540171472729892850f, 0.839893794195999520f,\n  -0.542750784864515890f,\n  0.838224705554838080f, -0.545324988422046460f, 0.836547727223512010f,\n  -0.547894059173100190f,\n  0.834862874986380010f, -0.550457972936604810f, 0.833170164701913190f,\n  -0.553016705580027470f,\n  0.831469612302545240f, -0.555570233019602180f, 0.829761233794523050f,\n  -0.558118531220556100f,\n  0.828045045257755800f, -0.560661576197336030f, 0.826321062845663530f,\n  -0.563199344013834090f,\n  0.824589302785025290f, -0.565731810783613120f, 0.822849781375826430f,\n  -0.568258952670131490f,\n  0.821102514991104650f, -0.570780745886967260f, 0.819347520076796900f,\n  -0.573297166698042200f,\n  0.817584813151583710f, -0.575808191417845340f, 0.815814410806733780f,\n  -0.578313796411655590f,\n  0.814036329705948410f, -0.580813958095764530f, 0.812250586585203880f,\n  -0.583308652937698290f,\n  0.810457198252594770f, -0.585797857456438860f, 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0.021474080275469605f,\n  -0.999769405351215280f,\n  0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f,\n  -0.999882347454212560f,\n  0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f,\n  -0.999957644551963900f,\n  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,\n  -0.999995293809576190f\n};\n\nstatic const float32_t Weights_2048[4096] = {\n  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,\n  -0.000766990318742704f,\n  0.999998823451701880f, -0.001533980186284766f, 0.999997352766978210f,\n  -0.002300969151425805f,\n  0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f,\n  -0.003834942569706228f,\n  0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f,\n  -0.005368906963996343f,\n  0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f,\n  -0.006902858724729756f,\n  0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f,\n  -0.008436794242369799f,\n  0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f,\n  -0.009970709907418031f,\n  0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f,\n  -0.011504602110422714f,\n  0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f,\n  -0.013038467241987334f,\n  0.999904701082852900f, -0.013805388528060391f, 0.999893818374418490f,\n  -0.014572301692779064f,\n  0.999882347454212560f, -0.015339206284988100f, 0.999870288328982950f,\n  -0.016106101853537287f,\n  0.999857641005823860f, -0.016872987947281710f, 0.999844405492175240f,\n  -0.017639864115082053f,\n  0.999830581795823400f, -0.018406729905804820f, 0.999816169924900410f,\n  -0.019173584868322623f,\n  0.999801169887884260f, -0.019940428551514441f, 0.999785581693599210f,\n  -0.020707260504265895f,\n  0.999769405351215280f, -0.021474080275469508f, 0.999752640870248840f,\n  -0.022240887414024961f,\n  0.999735288260561680f, -0.023007681468839369f, 0.999717347532362190f,\n  -0.023774461988827555f,\n  0.999698818696204250f, -0.024541228522912288f, 0.999679701762987930f,\n  -0.025307980620024571f,\n  0.999659996743959220f, -0.026074717829103901f, 0.999639703650710200f,\n  -0.026841439699098531f,\n  0.999618822495178640f, -0.027608145778965740f, 0.999597353289648380f,\n  -0.028374835617672099f,\n  0.999575296046749220f, -0.029141508764193722f, 0.999552650779456990f,\n  -0.029908164767516555f,\n  0.999529417501093140f, -0.030674803176636626f, 0.999505596225325310f,\n  -0.031441423540560301f,\n  0.999481186966166950f, -0.032208025408304586f, 0.999456189737977340f,\n  -0.032974608328897335f,\n  0.999430604555461730f, -0.033741171851377580f, 0.999404431433671300f,\n  -0.034507715524795750f,\n  0.999377670388002850f, -0.035274238898213947f, 0.999350321434199440f,\n  -0.036040741520706229f,\n  0.999322384588349540f, -0.036807222941358832f, 0.999293859866887790f,\n  -0.037573682709270494f,\n  0.999264747286594420f, -0.038340120373552694f, 0.999235046864595850f,\n  -0.039106535483329888f,\n  0.999204758618363890f, -0.039872927587739811f, 0.999173882565716380f,\n  -0.040639296235933736f,\n  0.999142418724816910f, -0.041405640977076739f, 0.999110367114174890f,\n  -0.042171961360347947f,\n  0.999077727752645360f, -0.042938256934940820f, 0.999044500659429290f,\n  -0.043704527250063421f,\n  0.999010685854073380f, -0.044470771854938668f, 0.998976283356469820f,\n  -0.045236990298804590f,\n  0.998941293186856870f, -0.046003182130914623f, 0.998905715365818290f,\n  -0.046769346900537863f,\n  0.998869549914283560f, -0.047535484156959303f, 0.998832796853527990f,\n  -0.048301593449480144f,\n  0.998795456205172410f, -0.049067674327418015f, 0.998757527991183340f,\n  -0.049833726340107277f,\n  0.998719012233872940f, -0.050599749036899282f, 0.998679908955899090f,\n  -0.051365741967162593f,\n  0.998640218180265270f, -0.052131704680283324f, 0.998599939930320370f,\n  -0.052897636725665324f,\n  0.998559074229759310f, -0.053663537652730520f, 0.998517621102622210f,\n  -0.054429407010919133f,\n  0.998475580573294770f, -0.055195244349689934f, 0.998432952666508440f,\n  -0.055961049218520569f,\n  0.998389737407340160f, -0.056726821166907748f, 0.998345934821212370f,\n  -0.057492559744367566f,\n  0.998301544933892890f, -0.058258264500435752f, 0.998256567771495180f,\n  -0.059023934984667931f,\n  0.998211003360478190f, -0.059789570746639868f, 0.998164851727646240f,\n  -0.060555171335947788f,\n  0.998118112900149180f, -0.061320736302208578f, 0.998070786905482340f,\n  -0.062086265195060088f,\n  0.998022873771486240f, -0.062851757564161406f, 0.997974373526346990f,\n  -0.063617212959193106f,\n  0.997925286198596000f, -0.064382630929857465f, 0.997875611817110150f,\n  -0.065148011025878833f,\n  0.997825350411111640f, -0.065913352797003805f, 0.997774502010167820f,\n  -0.066678655793001557f,\n  0.997723066644191640f, -0.067443919563664051f, 0.997671044343441000f,\n  -0.068209143658806329f,\n  0.997618435138519550f, -0.068974327628266746f, 0.997565239060375750f,\n  -0.069739471021907307f,\n  0.997511456140303450f, -0.070504573389613856f, 0.997457086409941910f,\n  -0.071269634281296401f,\n  0.997402129901275300f, -0.072034653246889332f, 0.997346586646633230f,\n  -0.072799629836351673f,\n  0.997290456678690210f, -0.073564563599667426f, 0.997233740030466280f,\n  -0.074329454086845756f,\n  0.997176436735326190f, -0.075094300847921305f, 0.997118546826979980f,\n  -0.075859103432954447f,\n  0.997060070339482960f, -0.076623861392031492f, 0.997001007307235290f,\n  -0.077388574275265049f,\n  0.996941357764982160f, -0.078153241632794232f, 0.996881121747813850f,\n  -0.078917863014784942f,\n  0.996820299291165670f, -0.079682437971430126f, 0.996758890430818000f,\n  -0.080446966052950014f,\n  0.996696895202896060f, -0.081211446809592441f, 0.996634313643869900f,\n  -0.081975879791633066f,\n  0.996571145790554840f, -0.082740264549375692f, 0.996507391680110820f,\n  -0.083504600633152432f,\n  0.996443051350042630f, -0.084268887593324071f, 0.996378124838200210f,\n  -0.085033124980280275f,\n  0.996312612182778000f, -0.085797312344439894f, 0.996246513422315520f,\n  -0.086561449236251170f,\n  0.996179828595696980f, -0.087325535206192059f, 0.996112557742151130f,\n  -0.088089569804770507f,\n  0.996044700901251970f, -0.088853552582524600f, 0.995976258112917790f,\n  -0.089617483090022959f,\n  0.995907229417411720f, -0.090381360877864983f, 0.995837614855341610f,\n  -0.091145185496681005f,\n  0.995767414467659820f, -0.091908956497132724f, 0.995696628295663520f,\n  -0.092672673429913310f,\n  0.995625256380994310f, -0.093436335845747787f, 0.995553298765638470f,\n  -0.094199943295393204f,\n  0.995480755491926940f, -0.094963495329638992f, 0.995407626602534900f,\n  -0.095726991499307162f,\n  0.995333912140482280f, -0.096490431355252593f, 0.995259612149133390f,\n  -0.097253814448363271f,\n  0.995184726672196930f, -0.098017140329560604f, 0.995109255753726110f,\n  -0.098780408549799623f,\n  0.995033199438118630f, -0.099543618660069319f, 0.994956557770116380f,\n  -0.100306770211392860f,\n  0.994879330794805620f, -0.101069862754827820f, 0.994801518557617110f,\n  -0.101832895841466530f,\n  0.994723121104325700f, -0.102595869022436280f, 0.994644138481050710f,\n  -0.103358781848899610f,\n  0.994564570734255420f, -0.104121633872054590f, 0.994484417910747600f,\n  -0.104884424643134970f,\n  0.994403680057679100f, -0.105647153713410620f, 0.994322357222545810f,\n  -0.106409820634187680f,\n  0.994240449453187900f, -0.107172424956808840f, 0.994157956797789730f,\n  -0.107934966232653650f,\n  0.994074879304879370f, -0.108697444013138720f, 0.993991217023329380f,\n  -0.109459857849717980f,\n  0.993906970002356060f, -0.110222207293883060f, 0.993822138291519660f,\n  -0.110984491897163390f,\n  0.993736721940724600f, -0.111746711211126590f, 0.993650721000219120f,\n  -0.112508864787378690f,\n  0.993564135520595300f, -0.113270952177564350f, 0.993476965552789190f,\n  -0.114032972933367200f,\n  0.993389211148080650f, -0.114794926606510080f, 0.993300872358093280f,\n  -0.115556812748755260f,\n  0.993211949234794500f, -0.116318630911904750f, 0.993122441830495580f,\n  -0.117080380647800590f,\n  0.993032350197851410f, -0.117842061508324980f, 0.992941674389860470f,\n  -0.118603673045400720f,\n  0.992850414459865100f, -0.119365214810991350f, 0.992758570461551140f,\n  -0.120126686357101500f,\n  0.992666142448948020f, -0.120888087235777080f, 0.992573130476428810f,\n  -0.121649416999105530f,\n  0.992479534598709970f, -0.122410675199216200f, 0.992385354870851670f,\n  -0.123171861388280480f,\n  0.992290591348257370f, -0.123932975118512160f, 0.992195244086673920f,\n  -0.124694015942167640f,\n  0.992099313142191800f, -0.125454983411546230f, 0.992002798571244520f,\n  -0.126215877078990350f,\n  0.991905700430609330f, -0.126976696496885870f, 0.991808018777406430f,\n  -0.127737441217662310f,\n  0.991709753669099530f, -0.128498110793793170f, 0.991610905163495370f,\n  -0.129258704777796140f,\n  0.991511473318743900f, -0.130019222722233350f, 0.991411458193338540f,\n  -0.130779664179711710f,\n  0.991310859846115440f, -0.131540028702883120f, 0.991209678336254060f,\n  -0.132300315844444650f,\n  0.991107913723276890f, -0.133060525157139060f, 0.991005566067049370f,\n  -0.133820656193754720f,\n  0.990902635427780010f, -0.134580708507126170f, 0.990799121866020370f,\n  -0.135340681650134210f,\n  0.990695025442664630f, -0.136100575175706200f, 0.990590346218950150f,\n  -0.136860388636816380f,\n  0.990485084256457090f, -0.137620121586486040f, 0.990379239617108160f,\n  -0.138379773577783890f,\n  0.990272812363169110f, -0.139139344163826200f, 0.990165802557248400f,\n  -0.139898832897777210f,\n  0.990058210262297120f, -0.140658239332849210f, 0.989950035541608990f,\n  -0.141417563022303020f,\n  0.989841278458820530f, -0.142176803519448030f, 0.989731939077910570f,\n  -0.142935960377642670f,\n  0.989622017463200890f, -0.143695033150294470f, 0.989511513679355190f,\n  -0.144454021390860470f,\n  0.989400427791380380f, -0.145212924652847460f, 0.989288759864625170f,\n  -0.145971742489812210f,\n  0.989176509964781010f, -0.146730474455361750f, 0.989063678157881540f,\n  -0.147489120103153570f,\n  0.988950264510302990f, -0.148247678986896030f, 0.988836269088763540f,\n  -0.149006150660348450f,\n  0.988721691960323780f, -0.149764534677321510f, 0.988606533192386450f,\n  -0.150522830591677400f,\n  0.988490792852696590f, -0.151281037957330220f, 0.988374471009341280f,\n  -0.152039156328246050f,\n  0.988257567730749460f, -0.152797185258443440f, 0.988140083085692570f,\n  -0.153555124301993450f,\n  0.988022017143283530f, -0.154312973013020100f, 0.987903369972977790f,\n  -0.155070730945700510f,\n  0.987784141644572180f, -0.155828397654265230f, 0.987664332228205710f,\n  -0.156585972692998430f,\n  0.987543941794359230f, -0.157343455616238250f, 0.987422970413855410f,\n  -0.158100845978376980f,\n  0.987301418157858430f, -0.158858143333861450f, 0.987179285097874340f,\n  -0.159615347237193060f,\n  0.987056571305750970f, -0.160372457242928280f, 0.986933276853677710f,\n  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-0.983524054057571260f,\n  0.180022901405699510f, -0.983662419211730250f, 0.179268388901835880f,\n  -0.983800205702631490f,\n  0.178513770938997590f, -0.983937413449218920f, 0.177759047961107140f,\n  -0.984074042370776450f,\n  0.177004220412148860f, -0.984210092386929030f, 0.176249288736167940f,\n  -0.984345563417641900f,\n  0.175494253377271400f, -0.984480455383220930f, 0.174739114779627310f,\n  -0.984614768204312600f,\n  0.173983873387463850f, -0.984748501801904210f, 0.173228529645070490f,\n  -0.984881656097323700f,\n  0.172473083996796030f, -0.985014231012239840f, 0.171717536887049970f,\n  -0.985146226468662230f,\n  0.170961888760301360f, -0.985277642388941220f, 0.170206140061078120f,\n  -0.985408478695768420f,\n  0.169450291233967930f, -0.985538735312176060f, 0.168694342723617440f,\n  -0.985668412161537550f,\n  0.167938294974731230f, -0.985797509167567370f, 0.167182148432072880f,\n  -0.985926026254321130f,\n  0.166425903540464220f, -0.986053963346195440f, 0.165669560744784140f,\n  -0.986181320367928270f,\n  0.164913120489970090f, -0.986308097244598670f, 0.164156583221015890f,\n  -0.986434293901627070f,\n  0.163399949382973230f, -0.986559910264775410f, 0.162643219420950450f,\n  -0.986684946260146690f,\n  0.161886393780111910f, -0.986809401814185420f, 0.161129472905678780f,\n  -0.986933276853677710f,\n  0.160372457242928400f, -0.987056571305750970f, 0.159615347237193090f,\n  -0.987179285097874340f,\n  0.158858143333861390f, -0.987301418157858430f, 0.158100845978377090f,\n  -0.987422970413855410f,\n  0.157343455616238280f, -0.987543941794359230f, 0.156585972692998590f,\n  -0.987664332228205710f,\n  0.155828397654265320f, -0.987784141644572180f, 0.155070730945700510f,\n  -0.987903369972977790f,\n  0.154312973013020240f, -0.988022017143283530f, 0.153555124301993500f,\n  -0.988140083085692570f,\n  0.152797185258443410f, -0.988257567730749460f, 0.152039156328246160f,\n  -0.988374471009341280f,\n  0.151281037957330250f, -0.988490792852696590f, 0.150522830591677370f,\n  -0.988606533192386450f,\n  0.149764534677321620f, -0.988721691960323780f, 0.149006150660348470f,\n  -0.988836269088763540f,\n  0.148247678986896200f, -0.988950264510302990f, 0.147489120103153680f,\n  -0.989063678157881540f,\n  0.146730474455361750f, -0.989176509964781010f, 0.145971742489812370f,\n  -0.989288759864625170f,\n  0.145212924652847520f, -0.989400427791380380f, 0.144454021390860440f,\n  -0.989511513679355190f,\n  0.143695033150294580f, -0.989622017463200780f, 0.142935960377642700f,\n  -0.989731939077910570f,\n  0.142176803519448000f, -0.989841278458820530f, 0.141417563022303130f,\n  -0.989950035541608990f,\n  0.140658239332849240f, -0.990058210262297120f, 0.139898832897777380f,\n  -0.990165802557248400f,\n  0.139139344163826280f, -0.990272812363169110f, 0.138379773577783890f,\n  -0.990379239617108160f,\n  0.137620121586486180f, -0.990485084256456980f, 0.136860388636816430f,\n  -0.990590346218950150f,\n  0.136100575175706200f, -0.990695025442664630f, 0.135340681650134330f,\n  -0.990799121866020370f,\n  0.134580708507126220f, -0.990902635427780010f, 0.133820656193754690f,\n  -0.991005566067049370f,\n  0.133060525157139180f, -0.991107913723276780f, 0.132300315844444680f,\n  -0.991209678336254060f,\n  0.131540028702883280f, -0.991310859846115440f, 0.130779664179711790f,\n  -0.991411458193338540f,\n  0.130019222722233350f, -0.991511473318743900f, 0.129258704777796270f,\n  -0.991610905163495370f,\n  0.128498110793793220f, -0.991709753669099530f, 0.127737441217662280f,\n  -0.991808018777406430f,\n  0.126976696496885980f, -0.991905700430609330f, 0.126215877078990400f,\n  -0.992002798571244520f,\n  0.125454983411546210f, -0.992099313142191800f, 0.124694015942167770f,\n  -0.992195244086673920f,\n  0.123932975118512200f, -0.992290591348257370f, 0.123171861388280650f,\n  -0.992385354870851670f,\n  0.122410675199216280f, -0.992479534598709970f, 0.121649416999105540f,\n  -0.992573130476428810f,\n  0.120888087235777220f, -0.992666142448948020f, 0.120126686357101580f,\n  -0.992758570461551140f,\n  0.119365214810991350f, -0.992850414459865100f, 0.118603673045400840f,\n  -0.992941674389860470f,\n  0.117842061508325020f, -0.993032350197851410f, 0.117080380647800550f,\n  -0.993122441830495580f,\n  0.116318630911904880f, -0.993211949234794500f, 0.115556812748755290f,\n  -0.993300872358093280f,\n  0.114794926606510250f, -0.993389211148080650f, 0.114032972933367300f,\n  -0.993476965552789190f,\n  0.113270952177564360f, -0.993564135520595300f, 0.112508864787378830f,\n  -0.993650721000219120f,\n  0.111746711211126660f, -0.993736721940724600f, 0.110984491897163380f,\n  -0.993822138291519660f,\n  0.110222207293883180f, -0.993906970002356060f, 0.109459857849718030f,\n  -0.993991217023329380f,\n  0.108697444013138670f, -0.994074879304879370f, 0.107934966232653760f,\n  -0.994157956797789730f,\n  0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f,\n  -0.994322357222545810f,\n  0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f,\n  -0.994484417910747600f,\n  0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f,\n  -0.994644138481050710f,\n  0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f,\n  -0.994801518557617110f,\n  0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f,\n  -0.994956557770116380f,\n  0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f,\n  -0.995109255753726110f,\n  0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f,\n  -0.995259612149133390f,\n  0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f,\n  -0.995407626602534900f,\n  0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f,\n  -0.995553298765638470f,\n  0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f,\n  -0.995696628295663520f,\n  0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f,\n  -0.995837614855341610f,\n  0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f,\n  -0.995976258112917790f,\n  0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f,\n  -0.996112557742151130f,\n  0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f,\n  -0.996246513422315520f,\n  0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f,\n  -0.996378124838200210f,\n  0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f,\n  -0.996507391680110820f,\n  0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f,\n  -0.996634313643869900f,\n  0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f,\n  -0.996758890430818000f,\n  0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f,\n  -0.996881121747813850f,\n  0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f,\n  -0.997001007307235290f,\n  0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f,\n  -0.997118546826979980f,\n  0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f,\n  -0.997233740030466160f,\n  0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f,\n  -0.997346586646633230f,\n  0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f,\n  -0.997457086409941910f,\n  0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f,\n  -0.997565239060375750f,\n  0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f,\n  -0.997671044343441000f,\n  0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f,\n  -0.997774502010167820f,\n  0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f,\n  -0.997875611817110150f,\n  0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f,\n  -0.997974373526346990f,\n  0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f,\n  -0.998070786905482340f,\n  0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f,\n  -0.998164851727646240f,\n  0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f,\n  -0.998256567771495180f,\n  0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f,\n  -0.998345934821212370f,\n  0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f,\n  -0.998432952666508440f,\n  0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f,\n  -0.998517621102622210f,\n  0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f,\n  -0.998599939930320370f,\n  0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f,\n  -0.998679908955899090f,\n  0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f,\n  -0.998757527991183340f,\n  0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f,\n  -0.998832796853527990f,\n  0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f,\n  -0.998905715365818290f,\n  0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f,\n  -0.998976283356469820f,\n  0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f,\n  -0.999044500659429290f,\n  0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f,\n  -0.999110367114174890f,\n  0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f,\n  -0.999173882565716380f,\n  0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f,\n  -0.999235046864595850f,\n  0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f,\n  -0.999293859866887790f,\n  0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f,\n  -0.999350321434199440f,\n  0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f,\n  -0.999404431433671300f,\n  0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f,\n  -0.999456189737977340f,\n  0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f,\n  -0.999505596225325310f,\n  0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f,\n  -0.999552650779456990f,\n  0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f,\n  -0.999597353289648380f,\n  0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f,\n  -0.999639703650710200f,\n  0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f,\n  -0.999679701762987930f,\n  0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f,\n  -0.999717347532362190f,\n  0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f,\n  -0.999752640870248840f,\n  0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f,\n  -0.999785581693599210f,\n  0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f,\n  -0.999816169924900410f,\n  0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f,\n  -0.999844405492175240f,\n  0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f,\n  -0.999870288328982950f,\n  0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f,\n  -0.999893818374418490f,\n  0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f,\n  -0.999914995573113470f,\n  0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f,\n  -0.999933819875236000f,\n  0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f,\n  -0.999950291236490480f,\n  0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f,\n  -0.999964409618118280f,\n  0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f,\n  -0.999976174986897610f,\n  0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f,\n  -0.999985587315143200f,\n  0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f,\n  -0.999992646580707190f,\n  0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f,\n  -0.999997352766978210f,\n  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,\n  -0.999999705862882230f\n};\n\nstatic const float32_t Weights_8192[16384] = {\n  1.000000000000000000, -0.000000000000000000, 0.999999981616429330,\n    -0.000191747597310703,\n  0.999999926465717890, -0.000383495187571396, 0.999999834547867670,\n    -0.000575242763732066,\n  0.999999705862882230, -0.000766990318742704, 0.999999540410766110,\n    -0.000958737845553301,\n  0.999999338191525530, -0.001150485337113849, 0.999999099205167830,\n    -0.001342232786374338,\n  0.999998823451701880, -0.001533980186284766, 0.999998510931137790,\n    -0.001725727529795126,\n  0.999998161643486980, -0.001917474809855419, 0.999997775588762350,\n    -0.002109222019415644,\n  0.999997352766978210, -0.002300969151425805, 0.999996893178149880,\n    -0.002492716198835908,\n  0.999996396822294350, -0.002684463154595962, 0.999995863699429940,\n    -0.002876210011655979,\n  0.999995293809576190, -0.003067956762965976, 0.999994687152754080,\n    -0.003259703401475973,\n  0.999994043728985820, -0.003451449920135994, 0.999993363538295150,\n    -0.003643196311896068,\n  0.999992646580707190, -0.003834942569706228, 0.999991892856248010,\n    -0.004026688686516512,\n  0.999991102364945590, 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-0.015722655225416857, 0.999873358254129260,\n    -0.015914378832040183,\n  0.999870288328982950, -0.016106101853537287, 0.999867181641464380,\n    -0.016297824282859065,\n  0.999864038191687680, -0.016489546112956437, 0.999860857979768540,\n    -0.016681267336780332,\n  0.999857641005823860, -0.016872987947281710, 0.999854387269971890,\n    -0.017064707937411563,\n  0.999851096772332190, -0.017256427300120877, 0.999847769513025900,\n    -0.017448146028360693,\n  0.999844405492175240, -0.017639864115082053, 0.999841004709904000,\n    -0.017831581553236039,\n  0.999837567166337090, -0.018023298335773746, 0.999834092861600960,\n    -0.018215014455646290,\n  0.999830581795823400, -0.018406729905804820, 0.999827033969133420,\n    -0.018598444679200511,\n  0.999823449381661570, -0.018790158768784555, 0.999819828033539420,\n    -0.018981872167508178,\n  0.999816169924900410, -0.019173584868322623, 0.999812475055878780,\n    -0.019365296864179156,\n  0.999808743426610520, -0.019557008148029083, 0.999804975037232870,\n    -0.019748718712823729,\n  0.999801169887884260, -0.019940428551514441, 0.999797327978704690,\n    -0.020132137657052594,\n  0.999793449309835270, -0.020323846022389593, 0.999789533881418780,\n    -0.020515553640476875,\n  0.999785581693599210, -0.020707260504265895, 0.999781592746521670,\n    -0.020898966606708137,\n  0.999777567040332940, -0.021090671940755121, 0.999773504575180990,\n    -0.021282376499358387,\n  0.999769405351215280, -0.021474080275469508, 0.999765269368586450,\n    -0.021665783262040078,\n  0.999761096627446610, -0.021857485452021735, 0.999756887127949080,\n    -0.022049186838366135,\n  0.999752640870248840, -0.022240887414024961, 0.999748357854501780,\n    -0.022432587171949934,\n  0.999744038080865430, -0.022624286105092803, 0.999739681549498660,\n    -0.022815984206405345,\n  0.999735288260561680, -0.023007681468839369, 0.999730858214216030,\n    -0.023199377885346720,\n  0.999726391410624470, -0.023391073448879258, 0.999721887849951310,\n    -0.023582768152388894,\n  0.999717347532362190, -0.023774461988827555, 0.999712770458023870,\n    -0.023966154951147210,\n  0.999708156627104880, -0.024157847032299864, 0.999703506039774650,\n    -0.024349538225237534,\n  0.999698818696204250, -0.024541228522912288, 0.999694094596566000,\n    -0.024732917918276223,\n  0.999689333741033640, -0.024924606404281468, 0.999684536129782140,\n    -0.025116293973880186,\n  0.999679701762987930, -0.025307980620024571, 0.999674830640828740,\n    -0.025499666335666853,\n  0.999669922763483760, -0.025691351113759295, 0.999664978131133310,\n    -0.025883034947254198,\n  0.999659996743959220, -0.026074717829103901, 0.999654978602144690,\n    -0.026266399752260760,\n  0.999649923705874240, -0.026458080709677187, 0.999644832055333610,\n    -0.026649760694305618,\n  0.999639703650710200, -0.026841439699098531, 0.999634538492192300,\n    -0.027033117717008431,\n  0.999629336579970110, -0.027224794740987875, 0.999624097914234570,\n    -0.027416470763989436,\n  0.999618822495178640, -0.027608145778965740, 0.999613510322995950,\n    -0.027799819778869445,\n  0.999608161397882110, -0.027991492756653243, 0.999602775720033530,\n    -0.028183164705269874,\n  0.999597353289648380, -0.028374835617672099, 0.999591894106925950,\n    -0.028566505486812728,\n  0.999586398172067070, -0.028758174305644615, 0.999580865485273700,\n    -0.028949842067120635,\n  0.999575296046749220, -0.029141508764193722, 0.999569689856698580,\n    -0.029333174389816835,\n  0.999564046915327740, -0.029524838936942976, 0.999558367222844300,\n    -0.029716502398525191,\n  0.999552650779456990, -0.029908164767516555, 0.999546897585375960,\n    -0.030099826036870198,\n  0.999541107640812940, -0.030291486199539284, 0.999535280945980540,\n    -0.030483145248477009,\n  0.999529417501093140, -0.030674803176636626, 0.999523517306366350,\n    -0.030866459976971412,\n  0.999517580362016990, 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-0.999954041425129780, 0.009395494088617302,\n    -0.999955861371306100,\n  0.009203754782059960, -0.999957644551963900, 0.009012015137106642,\n    -0.999959390967037450,\n  0.008820275160807512, -0.999961100616462820, 0.008628534860211857,\n    -0.999962773500176930,\n  0.008436794242369860, -0.999964409618118280, 0.008245053314331058,\n    -0.999966008970226920,\n  0.008053312083144991, -0.999967571556443780, 0.007861570555861883,\n    -0.999969097376711580,\n  0.007669828739531077, -0.999970586430974140, 0.007478086641202815,\n    -0.999972038719176730,\n  0.007286344267926684, -0.999973454241265940, 0.007094601626752279,\n    -0.999974832997189810,\n  0.006902858724729877, -0.999976174986897610, 0.006711115568908869,\n    -0.999977480210339940,\n  0.006519372166339549, -0.999978748667468830, 0.006327628524071549,\n    -0.999979980358237650,\n  0.006135884649154515, -0.999981175282601110, 0.005944140548638765,\n    -0.999982333440515350,\n  0.005752396229573737, -0.999983454831937730, 0.005560651699009764,\n    -0.999984539456826970,\n  0.005368906963996303, -0.999985587315143200, 0.005177162031583702,\n    -0.999986598406848000,\n  0.004985416908821652, -0.999987572731904080, 0.004793671602759852,\n    -0.999988510290275690,\n  0.004601926120448672, -0.999989411081928400, 0.004410180468937601,\n    -0.999990275106828920,\n  0.004218434655277024, -0.999991102364945590, 0.004026688686516664,\n    -0.999991892856248010,\n  0.003834942569706248, -0.999992646580707190, 0.003643196311896179,\n    -0.999993363538295150,\n  0.003451449920135975, -0.999994043728985820, 0.003259703401476044,\n    -0.999994687152754080,\n  0.003067956762966138, -0.999995293809576190, 0.002876210011656010,\n    -0.999995863699429940,\n  0.002684463154596083, -0.999996396822294350, 0.002492716198835898,\n    -0.999996893178149880,\n  0.002300969151425887, -0.999997352766978210, 0.002109222019415816,\n    -0.999997775588762350,\n  0.001917474809855460, -0.999998161643486980, 0.001725727529795258,\n    -0.999998510931137790,\n  0.001533980186284766, -0.999998823451701880, 0.001342232786374430,\n    -0.999999099205167830,\n  0.001150485337113809, -0.999999338191525530, 0.000958737845553352,\n    -0.999999540410766110,\n  0.000766990318742846, -0.999999705862882230, 0.000575242763732077,\n    -0.999999834547867670,\n  0.000383495187571497, -0.999999926465717890, 0.000191747597310674,\n    -0.999999981616429330,\n\n};\n\n/**    \n* \\par    \n* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    \n* \\par    \n* C command to generate the table    \n* \\par    \n* 
 for(i = 0; i< N; i++)    \n* {    \n*    cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n* } 
    \n* \\par    \n* where N is the number of factors to generate and c is pi/(2*N)    \n*/\nstatic const float32_t cos_factors_128[128] = {\n  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,\n  0.999077727752645360f,\n  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,\n  0.995767414467659820f,\n  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,\n  0.990058210262297120f,\n  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,\n  0.981963869109555240f,\n  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,\n  0.971503890986251780f,\n  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,\n  0.958703474895871600f,\n  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,\n  0.943593458161960390f,\n  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,\n  0.926210242138311380f,\n  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,\n  0.906595704514915330f,\n  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,\n  0.884797098430937790f,\n  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,\n  0.860866938637767310f,\n  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,\n  0.834862874986380010f,\n  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,\n  0.806847553543799330f,\n  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,\n  0.776888465673232440f,\n  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,\n  0.745057785441466060f,\n  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,\n  0.711432195745216430f,\n  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,\n  0.676092703575316030f,\n  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,\n  0.639124444863775730f,\n  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,\n  0.600616479383868970f,\n  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,\n  0.560661576197336030f,\n  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,\n  0.519355990165589530f,\n  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,\n  0.476799230063322250f,\n  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,\n  0.433093818853152010f,\n  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,\n  0.388345046698826300f,\n  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,\n  0.342660717311994380f,\n  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,\n  0.296150888243623960f,\n  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,\n  0.248927605745720260f,\n  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,\n  0.201104634842091960f,\n  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,\n  0.152797185258443410f,\n  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,\n  0.104121633872054730f,\n  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,\n  0.055195244349690031f,\n  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,\n  0.006135884649154515f\n};\n\nstatic const float32_t cos_factors_512[512] = {\n  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,\n  0.999942349676023910f,\n  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,\n  0.999735288260561680f,\n  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,\n  0.999377670388002850f,\n  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,\n  0.998869549914283560f,\n  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,\n  0.998211003360478190f,\n  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,\n  0.997402129901275300f,\n  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,\n  0.996443051350042630f,\n  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,\n  0.995333912140482280f,\n  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,\n  0.994074879304879370f,\n  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,\n  0.992666142448948020f,\n  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,\n  0.991107913723276890f,\n  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,\n  0.989400427791380380f,\n  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,\n  0.987543941794359230f,\n  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,\n  0.985538735312176060f,\n  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,\n  0.983385110321551180f,\n  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,\n  0.981083391150486710f,\n  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,\n  0.978633924429423210f,\n  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,\n  0.976037079039039020f,\n  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,\n  0.973293246054698250f,\n  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,\n  0.970402838687555500f,\n  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,\n  0.967366292222328510f,\n  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,\n  0.964184063951745830f,\n  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,\n  0.960856633107679660f,\n  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,\n  0.957384500788975860f,\n  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,\n  0.953768189885990330f,\n  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,\n  0.950008245001843000f,\n  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,\n  0.946105232370403450f,\n  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,\n  0.942059739771017310f,\n  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,\n  0.937872376439989890f,\n  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,\n  0.933543772978836170f,\n  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,\n  0.929074581259315860f,\n  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,\n  0.924465474325262600f,\n  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,\n  0.919717146291227360f,\n  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,\n  0.914830312237946200f,\n  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,\n  0.909805708104652220f,\n  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,\n  0.904644090578246240f,\n  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,\n  0.899346236979341570f,\n  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,\n  0.893912945145203250f,\n  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,\n  0.888345033309596350f,\n  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,\n  0.882643339979562790f,\n  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,\n  0.876808723809145650f,\n  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,\n  0.870842063470078980f,\n  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,\n  0.864744257519462380f,\n  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,\n  0.858516224264442740f,\n  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,\n  0.852158901623919830f,\n  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,\n  0.845673246987299070f,\n  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,\n  0.839060237070312740f,\n  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,\n  0.832320867767929680f,\n  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,\n  0.825456154004377550f,\n  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,\n  0.818467129580298660f,\n  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,\n  0.811354847017063730f,\n  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,\n  0.804120377398265810f,\n  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,\n  0.796764810208418830f,\n  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,\n  0.789289253168885650f,\n  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,\n  0.781694832071059390f,\n  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,\n  0.773982690606822900f,\n  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,\n  0.766153990196312920f,\n  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,\n  0.758209909813015280f,\n  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,\n  0.750151645806215070f,\n  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,\n  0.741980411720831070f,\n  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,\n  0.733697438114660370f,\n  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,\n  0.725303972373060770f,\n  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,\n  0.716801278521099540f,\n  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,\n  0.708190637033195400f,\n  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,\n  0.699473344640283770f,\n  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,\n  0.690650714134534720f,\n  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,\n  0.681724074171649820f,\n  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,\n  0.672694769070772970f,\n  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,\n  0.663564158612039880f,\n  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,\n  0.654333617831800550f,\n  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,\n  0.645004536815544040f,\n  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,\n  0.635578320488556230f,\n  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,\n  0.626056388404343520f,\n  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,\n  0.616440174530853650f,\n  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,\n  0.606731127034524480f,\n  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,\n  0.596930708062196500f,\n  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,\n  0.587040393520918080f,\n  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,\n  0.577061672855679550f,\n  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,\n  0.566996048825108680f,\n  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,\n  0.556845037275160100f,\n  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,\n  0.546610166910834860f,\n  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,\n  0.536292979065963180f,\n  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,\n  0.525895027471084740f,\n  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,\n  0.515417878019463150f,\n  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,\n  0.504863108531267480f,\n  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,\n  0.494232308515959730f,\n  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,\n  0.483527078932918740f,\n  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,\n  0.472749031950342900f,\n  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,\n  0.461899790702462840f,\n  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,\n  0.450980989045103810f,\n  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,\n  0.439994271309633260f,\n  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,\n  0.428941292055329550f,\n  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,\n  0.417823715820212380f,\n  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,\n  0.406643216870369140f,\n  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,\n  0.395401478947816300f,\n  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,\n  0.384100195016935040f,\n  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,\n  0.372741067009515810f,\n  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,\n  0.361325805568454340f,\n  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,\n  0.349856129790135030f,\n  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,\n  0.338333766965541290f,\n  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,\n  0.326760452320131790f,\n  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,\n  0.315137928752522440f,\n  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,\n  0.303467946572011370f,\n  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,\n  0.291752263234989370f,\n  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,\n  0.279992643080273380f,\n  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,\n  0.268190857063403180f,\n  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,\n  0.256348682489942910f,\n  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,\n  0.244467902747824210f,\n  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,\n  0.232550307038775330f,\n  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,\n  0.220597690108873650f,\n  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,\n  0.208611851978263460f,\n  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,\n  0.196594597670080220f,\n  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,\n  0.184547736938619640f,\n  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,\n  0.172473083996796030f,\n  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,\n  0.160372457242928400f,\n  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,\n  0.148247678986896200f,\n  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,\n  0.136100575175706200f,\n  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,\n  0.123932975118512200f,\n  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,\n  0.111746711211126660f,\n  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,\n  0.099543618660069444f,\n  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,\n  0.087325535206192226f,\n  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,\n  0.075094300847921291f,\n  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,\n  0.062851757564161420f,\n  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,\n  0.050599749036899337f,\n  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,\n  0.038340120373552791f,\n  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,\n  0.026074717829104040f,\n  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,\n  0.013805388528060349f,\n  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,\n  0.001533980186284766f\n};\n\nstatic const float32_t cos_factors_2048[2048] = {\n  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,\n  0.999996396822294350f,\n  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,\n  0.999983454831937730f,\n  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,\n  0.999961100616462820f,\n  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,\n  0.999929334386276070f,\n  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,\n  0.999888156440373320f,\n  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,\n  0.999837567166337090f,\n  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,\n  0.999777567040332940f,\n  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,\n  0.999708156627104880f,\n  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,\n  0.999629336579970110f,\n  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,\n  0.999541107640812940f,\n  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,\n  0.999443470640077770f,\n  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,\n  0.999336426496761240f,\n  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,\n  0.999219976218403530f,\n  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,\n  0.999094120901079070f,\n  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,\n  0.998958861729386080f,\n  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,\n  0.998814199976435390f,\n  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,\n  0.998660137003838490f,\n  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,\n  0.998496674261694640f,\n  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,\n  0.998323813288577560f,\n  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,\n  0.998141555711520520f,\n  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,\n  0.997949903246001190f,\n  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,\n  0.997748857695925690f,\n  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,\n  0.997538420953611340f,\n  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,\n  0.997318594999768600f,\n  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,\n  0.997089381903483400f,\n  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,\n  0.996850783822196610f,\n  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,\n  0.996602803001684130f,\n  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,\n  0.996345441776035900f,\n  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,\n  0.996078702567633980f,\n  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,\n  0.995802587887129160f,\n  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,\n  0.995517100333418110f,\n  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,\n  0.995222242593618360f,\n  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,\n  0.994918017443043200f,\n  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,\n  0.994604427745175660f,\n  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,\n  0.994281476451641550f,\n  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,\n  0.993949166602181130f,\n  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,\n  0.993607501324621610f,\n  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,\n  0.993256483834846440f,\n  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,\n  0.992896117436765980f,\n  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,\n  0.992526405522286100f,\n  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,\n  0.992147351571276090f,\n  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,\n  0.991758959151536110f,\n  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,\n  0.991361231918763460f,\n  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,\n  0.990954173616518500f,\n  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,\n  0.990537788076188750f,\n  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,\n  0.990112079216953770f,\n  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,\n  0.989677051045747210f,\n  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,\n  0.989232707657220050f,\n  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,\n  0.988779053233701520f,\n  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,\n  0.988316092045159690f,\n  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,\n  0.987843828449161740f,\n  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,\n  0.987362266890832400f,\n  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,\n  0.986871411902812470f,\n  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,\n  0.986371268105216030f,\n  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,\n  0.985861840205586980f,\n  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,\n  0.985343132998854790f,\n  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,\n  0.984815151367289140f,\n  0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,\n  0.984277900280454370f,\n  0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,\n  0.983731384795162090f,\n  0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,\n  0.983175610055424420f,\n  0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,\n  0.982610581292404750f,\n  0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,\n  0.982036303824369020f,\n  0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,\n  0.981452783056635520f,\n  0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,\n  0.980860024481523870f,\n  0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f,\n  0.980258033678303550f,\n  0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,\n  0.979646816313141210f,\n  0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,\n  0.979026378139047580f,\n  0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,\n  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0.043321395278109784f,\n  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,\n  0.040256114872041358f,\n  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,\n  0.037190455560088091f,\n  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,\n  0.034124446197403423f,\n  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,\n  0.031058115642434700f,\n  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,\n  0.027991492756653365f,\n  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,\n  0.024924606404281485f,\n  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,\n  0.021857485452021874f,\n  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,\n  0.018790158768784596f,\n  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,\n  0.015722655225417017f,\n  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,\n  0.012655003694430301f,\n  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,\n  0.009587233049729183f,\n  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,\n  0.006519372166339549f,\n  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,\n  0.003451449920135975f,\n  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,\n  0.000383495187571497f\n};\n\nstatic const float32_t cos_factors_8192[8192] = {\n  1.999999990808214700, 1.999999917273932200, 1.999999770205369800,\n    1.999999549602533100,\n  1.999999255465430200, 1.999998887794072000, 1.999998446588471700,\n    1.999997931848645600,\n  1.999997343574612800, 1.999996681766395000, 1.999995946424016200,\n    1.999995137547503600,\n  1.999994255136887000, 1.999993299192198700, 1.999992269713474200,\n    1.999991166700750800,\n  1.999989990154069600, 1.999988740073473500, 1.999987416459008600,\n    1.999986019310723500,\n  1.999984548628669600, 1.999983004412901000, 1.999981386663474400,\n    1.999979695380449400,\n  1.999977930563888100, 1.999976092213855400, 1.999974180330418700,\n    1.999972194913648900,\n  1.999970135963618400, 1.999968003480403000, 1.999965797464081200,\n    1.999963517914734100,\n  1.999961164832445800, 1.999958738217302300, 1.999956238069392900,\n    1.999953664388809800,\n  1.999951017175647600, 1.999948296430003500, 1.999945502151977600,\n    1.999942634341672600,\n  1.999939692999193900, 1.999936678124649700, 1.999933589718150700,\n    1.999930427779810900,\n  1.999927192309745900, 1.999923883308075200, 1.999920500774920300,\n    1.999917044710405500,\n  1.999913515114657900, 1.999909911987807200, 1.999906235329986100,\n    1.999902485141329400,\n  1.999898661421975400, 1.999894764172064600, 1.999890793391740000,\n    1.999886749081147800,\n  1.999882631240436700, 1.999878439869758200, 1.999874174969266300,\n    1.999869836539117700,\n  1.999865424579472000, 1.999860939090491600, 1.999856380072341000,\n    1.999851747525188200,\n  1.999847041449203300, 1.999842261844559700, 1.999837408711432600,\n    1.999832482050000900,\n  1.999827481860445300, 1.999822408142949900, 1.999817260897701400,\n    1.999812040124888700,\n  1.999806745824704000, 1.999801377997341800, 1.999795936642999600,\n    1.999790421761877400,\n  1.999784833354177900, 1.999779171420106700, 1.999773435959872000,\n    1.999767626973684400,\n  1.999761744461757700, 1.999755788424308200, 1.999749758861554900,\n    1.999743655773719400,\n  1.999737479161026100, 1.999731229023702200, 1.999724905361977200,\n    1.999718508176084000,\n  1.999712037466257600, 1.999705493232735800, 1.999698875475759600,\n    1.999692184195571900,\n  1.999685419392419000, 1.999678581066549400, 1.999671669218214600,\n    1.999664683847668800,\n  1.999657624955168700, 1.999650492540973900, 1.999643286605346800,\n    1.999636007148552400,\n  1.999628654170857900, 1.999621227672533800, 1.999613727653853500,\n    1.999606154115092500,\n  1.999598507056529000, 1.999590786478444600, 1.999582992381123000,\n    1.999575124764850800,\n  1.999567183629917100, 1.999559168976613900, 1.999551080805236100,\n    1.999542919116081000,\n  1.999534683909448600, 1.999526375185641800, 1.999517992944965800,\n    1.999509537187729200,\n  1.999501007914242600, 1.999492405124819700, 1.999483728819776900,\n    1.999474978999432800,\n  1.999466155664109600, 1.999457258814131500, 1.999448288449825500,\n    1.999439244571521700,\n  1.999430127179552500, 1.999420936274252800, 1.999411671855960900,\n    1.999402333925017300,\n  1.999392922481765500, 1.999383437526551300, 1.999373879059723500,\n    1.999364247081633500,\n  1.999354541592635500, 1.999344762593086500, 1.999334910083345700,\n    1.999324984063775700,\n  1.999314984534741100, 1.999304911496609700, 1.999294764949752100,\n    1.999284544894541100,\n  1.999274251331352400, 1.999263884260564600, 1.999253443682558900,\n    1.999242929597719200,\n  1.999232342006432000, 1.999221680909086400, 1.999210946306074500,\n    1.999200138197791100,\n  1.999189256584633600, 1.999178301467001900, 1.999167272845298900,\n    1.999156170719930100,\n  1.999144995091303600, 1.999133745959830600, 1.999122423325924200,\n    1.999111027190001000,\n  1.999099557552479900, 1.999088014413782800, 1.999076397774334000,\n    1.999064707634560700,\n  1.999052943994892300, 1.999041106855761900, 1.999029196217604100,\n    1.999017212080857400,\n  1.999005154445962200, 1.998993023313361700, 1.998980818683502100,\n    1.998968540556831800,\n  1.998956188933802800, 1.998943763814868800, 1.998931265200486900,\n    1.998918693091116200,\n  1.998906047487219600, 1.998893328389261400, 1.998880535797709700,\n    1.998867669713034500,\n  1.998854730135709400, 1.998841717066209400, 1.998828630505013400,\n    1.998815470452602400,\n  1.998802236909460500, 1.998788929876074100, 1.998775549352932400,\n    1.998762095340527400,\n  1.998748567839354000, 1.998734966849909000, 1.998721292372693100,\n    1.998707544408208700,\n  1.998693722956961500, 1.998679828019459300, 1.998665859596213500,\n    1.998651817687737300,\n  1.998637702294547000, 1.998623513417161700, 1.998609251056103100,\n    1.998594915211895600,\n  1.998580505885066100, 1.998566023076144600, 1.998551466785663400,\n    1.998536837014157900,\n  1.998522133762165900, 1.998507357030227900, 1.998492506818887200,\n    1.998477583128690100,\n  1.998462585960185000, 1.998447515313923400, 1.998432371190459500,\n    1.998417153590349900,\n  1.998401862514154200, 1.998386497962434800, 1.998371059935756300,\n    1.998355548434686400,\n  1.998339963459795400, 1.998324305011656600, 1.998308573090845200,\n    1.998292767697940100,\n  1.998276888833522300, 1.998260936498175400, 1.998244910692486000,\n    1.998228811417043700,\n  1.998212638672439900, 1.998196392459269400, 1.998180072778129600,\n    1.998163679629620500,\n  1.998147213014344900, 1.998130672932908000, 1.998114059385918400,\n    1.998097372373986300,\n  1.998080611897725700, 1.998063777957752600, 1.998046870554686100,\n    1.998029889689147700,\n  1.998012835361761900, 1.997995707573155600, 1.997978506323958600,\n    1.997961231614803200,\n  1.997943883446324800, 1.997926461819161000, 1.997908966733952500,\n    1.997891398191342400,\n  1.997873756191977000, 1.997856040736504500, 1.997838251825576400,\n    1.997820389459846700,\n  1.997802453639972300, 1.997784444366612600, 1.997766361640429800,\n    1.997748205462088500,\n  1.997729975832256600, 1.997711672751604200, 1.997693296220804000,\n    1.997674846240532000,\n  1.997656322811466500, 1.997637725934288300, 1.997619055609681600,\n    1.997600311838332500,\n  1.997581494620930300, 1.997562603958166600, 1.997543639850736200,\n    1.997524602299336500,\n  1.997505491304667000, 1.997486306867430900, 1.997467048988333000,\n    1.997447717668082000,\n  1.997428312907388200, 1.997408834706965000, 1.997389283067528800,\n    1.997369657989798400,\n  1.997349959474495200, 1.997330187522343700, 1.997310342134070800,\n    1.997290423310406100,\n  1.997270431052081900, 1.997250365359833200, 1.997230226234397900,\n    1.997210013676516700,\n  1.997189727686932400, 1.997169368266390900, 1.997148935415640600,\n    1.997128429135433400,\n  1.997107849426522600, 1.997087196289665000, 1.997066469725620200,\n    1.997045669735150000,\n  1.997024796319019300, 1.997003849477995600, 1.996982829212848900,\n    1.996961735524351900,\n  1.996940568413280600, 1.996919327880412900, 1.996898013926530000,\n    1.996876626552415400,\n  1.996855165758855600, 1.996833631546639300, 1.996812023916558800,\n    1.996790342869408000,\n  1.996768588405984300, 1.996746760527087700, 1.996724859233520500,\n    1.996702884526087900,\n  1.996680836405598100, 1.996658714872861800, 1.996636519928692000,\n    1.996614251573904900,\n  1.996591909809319400, 1.996569494635756600, 1.996547006054041100,\n    1.996524444064999400,\n  1.996501808669461000, 1.996479099868258400, 1.996456317662226300,\n    1.996433462052202600,\n  1.996410533039027400, 1.996387530623543900, 1.996364454806597500,\n    1.996341305589037100,\n  1.996318082971713500, 1.996294786955480800, 1.996271417541195300,\n    1.996247974729716200,\n  1.996224458521905600, 1.996200868918628100, 1.996177205920750800,\n    1.996153469529144100,\n  1.996129659744680300, 1.996105776568235100, 1.996081820000686500,\n    1.996057790042915500,\n  1.996033686695805300, 1.996009509960242400, 1.995985259837115500,\n    1.995960936327316300,\n  1.995936539431739000, 1.995912069151280800, 1.995887525486841300,\n    1.995862908439323100,\n  1.995838218009630800, 1.995813454198672700, 1.995788617007359100,\n    1.995763706436603200,\n  1.995738722487320600, 1.995713665160430600, 1.995688534456853800,\n    1.995663330377514400,\n  1.995638052923339300, 1.995612702095257400, 1.995587277894201400,\n    1.995561780321105600,\n  1.995536209376907600, 1.995510565062547800, 1.995484847378968600,\n    1.995459056327116000,\n  1.995433191907938000, 1.995407254122385700, 1.995381242971412600,\n    1.995355158455975200,\n  1.995329000577032800, 1.995302769335546500, 1.995276464732481200,\n    1.995250086768804100,\n  1.995223635445484900, 1.995197110763496000, 1.995170512723813100,\n    1.995143841327413400,\n  1.995117096575278200, 1.995090278468390600, 1.995063387007736600,\n    1.995036422194304700,\n  1.995009384029086800, 1.994982272513076600, 1.994955087647271000,\n    1.994927829432669800,\n  1.994900497870274900, 1.994873092961091200, 1.994845614706126400,\n    1.994818063106391000,\n  1.994790438162897600, 1.994762739876662100, 1.994734968248702800,\n    1.994707123280041100,\n  1.994679204971700100, 1.994651213324707000, 1.994623148340090700,\n    1.994595010018883000,\n  1.994566798362118300, 1.994538513370834200, 1.994510155046070700,\n    1.994481723388870100,\n  1.994453218400277900, 1.994424640081342100, 1.994395988433113700,\n    1.994367263456646100,\n  1.994338465152995000, 1.994309593523219600, 1.994280648568381500,\n    1.994251630289544600,\n  1.994222538687776100, 1.994193373764145500, 1.994164135519725000,\n    1.994134823955589800,\n  1.994105439072817700, 1.994075980872488800, 1.994046449355686200,\n    1.994016844523496000,\n  1.993987166377006600, 1.993957414917308700, 1.993927590145496900,\n    1.993897692062667200,\n  1.993867720669919400, 1.993837675968354700, 1.993807557959078600,\n    1.993777366643197900,\n  1.993747102021822900, 1.993716764096066200, 1.993686352867043200,\n    1.993655868335872300,\n  1.993625310503674100, 1.993594679371572200, 1.993563974940692800,\n    1.993533197212164800,\n  1.993502346187119700, 1.993471421866692200, 1.993440424252018900,\n    1.993409353344239600,\n  1.993378209144496700, 1.993346991653935300, 1.993315700873703200,\n    1.993284336804950900,\n  1.993252899448831400, 1.993221388806500900, 1.993189804879117500,\n    1.993158147667842800,\n  1.993126417173840500, 1.993094613398277400, 1.993062736342323000,\n    1.993030786007148800,\n  1.992998762393930000, 1.992966665503844000, 1.992934495338070800,\n    1.992902251897793000,\n  1.992869935184196300, 1.992837545198469000, 1.992805081941801700,\n    1.992772545415388200,\n  1.992739935620424700, 1.992707252558110200, 1.992674496229646500,\n    1.992641666636237700,\n  1.992608763779091000, 1.992575787659416100, 1.992542738278425300,\n    1.992509615637334100,\n  1.992476419737359900, 1.992443150579723500, 1.992409808165648100,\n    1.992376392496359300,\n  1.992342903573086000, 1.992309341397059600, 1.992275705969513800,\n    1.992241997291685400,\n  1.992208215364813700, 1.992174360190140900, 1.992140431768911500,\n    1.992106430102373400,\n  1.992072355191776300, 1.992038207038373300, 1.992003985643419700,\n    1.991969691008174100,\n  1.991935323133897000, 1.991900882021852200, 1.991866367673306200,\n    1.991831780089527500,\n  1.991797119271788300, 1.991762385221362600, 1.991727577939527600,\n    1.991692697427563300,\n  1.991657743686751700, 1.991622716718378400, 1.991587616523731000,\n    1.991552443104099800,\n  1.991517196460778500, 1.991481876595062800, 1.991446483508251500,\n    1.991411017201645500,\n  1.991375477676549100, 1.991339864934268800, 1.991304178976114100,\n    1.991268419803397200,\n  1.991232587417432600, 1.991196681819537900, 1.991160703011033200,\n    1.991124650993241400,\n  1.991088525767488200, 1.991052327335101300, 1.991016055697411900,\n    1.990979710855753900,\n  1.990943292811463000, 1.990906801565878600, 1.990870237120342400,\n    1.990833599476198800,\n  1.990796888634794400, 1.990760104597479400, 1.990723247365606200,\n    1.990686316940529800,\n  1.990649313323608100, 1.990612236516201300, 1.990575086519673200,\n    1.990537863335389400,\n  1.990500566964718400, 1.990463197409031700, 1.990425754669703100,\n    1.990388238748109100,\n  1.990350649645629600, 1.990312987363646000, 1.990275251903543600,\n    1.990237443266709400,\n  1.990199561454533600, 1.990161606468409300, 1.990123578309731700,\n    1.990085476979899000,\n  1.990047302480312300, 1.990009054812374800, 1.989970733977493000,\n    1.989932339977075900,\n  1.989893872812535000, 1.989855332485284800, 1.989816718996742200,\n    1.989778032348326700,\n  1.989739272541461100, 1.989700439577570400, 1.989661533458082100,\n    1.989622554184426800,\n  1.989583501758037700, 1.989544376180350600, 1.989505177452804100,\n    1.989465905576839600,\n  1.989426560553900500, 1.989387142385433900, 1.989347651072888900,\n    1.989308086617717500,\n  1.989268449021374300, 1.989228738285316900, 1.989188954411005100,\n    1.989149097399901500,\n  1.989109167253472000, 1.989069163973184300, 1.989029087560509700,\n    1.988988938016921000,\n  1.988948715343894900, 1.988908419542910100, 1.988868050615448100,\n    1.988827608562993200,\n  1.988787093387032600, 1.988746505089055600, 1.988705843670554500,\n    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0.019749681656531803, 0.019366204797080316, 0.018982727225589285,\n    0.018599248956157190,\n  0.018215770002884327, 0.017832290379869671, 0.017448810101212228,\n    0.017065329181012358,\n  0.016681847633368677, 0.016298365472381587, 0.015914882712149747,\n    0.015531399366773606,\n  0.015147915450352307, 0.014764430976985016, 0.014380945960772247,\n    0.013997460415812761,\n  0.013613974356207112, 0.013230487796054543, 0.012847000749454314,\n    0.012463513230507034,\n  0.012080025253311559, 0.011696536831968529, 0.011313047980577277,\n    0.010929558713237145,\n  0.010546069044048827, 0.010162578987111254, 0.009779088556525145,\n    0.009395597766389905,\n  0.009012106630804949, 0.008628615163871038, 0.008245123379687167,\n    0.007861631292354124,\n  0.007478138915970929, 0.007094646264638386, 0.006711153352455981,\n    0.006327660193523208,\n  0.005944166801940901, 0.005560673191808128, 0.005177179377225743,\n    0.004793685372293270,\n  0.004410191191110246, 0.004026696847777542, 0.003643202356394263,\n    0.003259707731061291,\n  0.002876212985878184, 0.002492718134944503, 0.002109223192361147,\n    0.001725728172227238,\n  0.001342233088643682, 0.000958737955710053, 0.000575242787525925,\n    0.000191747598192208,\n\n};\n\n/**    \n * @brief  Initialization function for the floating-point DCT4/IDCT4.   \n * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.   \n * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.   \n * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.   \n * @param[in]     N\t\t\t length of the DCT4.   \n * @param[in]     Nby2       half of the length of the DCT4.   \n * @param[in]     normalize  normalizing factor.   \n * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.   \n * \\par Normalizing factor:    \n * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    \n * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:    \n * \\image html dct4NormalizingF32Table.gif    \n */\n\narm_status arm_dct4_init_f32(\n  arm_dct4_instance_f32 * S,\n  arm_rfft_instance_f32 * S_RFFT,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  float32_t normalize)\n{\n  /*  Initialize the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /* Initializing the pointer array with the weight table base addresses of different lengths */\n  float32_t *twiddlePtr[4] =\n    { (float32_t *) Weights_128, (float32_t *) Weights_512,\n    (float32_t *) Weights_2048, (float32_t *) Weights_8192\n  };\n\n  /* Initializing the pointer array with the cos factor table base addresses of different lengths */\n  float32_t *pCosFactor[4] =\n    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,\n    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192\n  };\n\n  /* Initialize the DCT4 length */\n  S->N = N;\n\n  /* Initialize the half of DCT4 length */\n  S->Nby2 = Nby2;\n\n  /* Initialize the DCT4 Normalizing factor */\n  S->normalize = normalize;\n\n  /* Initialize Real FFT Instance */\n  S->pRfft = S_RFFT;\n\n  /* Initialize Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  switch (N)\n  {\n    /* Initialize the table modifier values */\n  case 8192u:\n    S->pTwiddle = twiddlePtr[3];\n    S->pCosFactor = pCosFactor[3];\n    break;\n  case 2048u:\n    S->pTwiddle = twiddlePtr[2];\n    S->pCosFactor = pCosFactor[2];\n    break;\n  case 512u:\n    S->pTwiddle = twiddlePtr[1];\n    S->pCosFactor = pCosFactor[1];\n    break;\n  case 128u:\n    S->pTwiddle = twiddlePtr[0];\n    S->pCosFactor = pCosFactor[0];\n    break;\n  default:\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n\n  /* Initialize the RFFT/RIFFT */\n  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);\n\n  /* return the status of DCT4 Init function */\n  return (status);\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_init_q15.c    \n*    \n* Description:\tInitialization function of DCT-4 & IDCT4 Q15    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/*    \n* @brief  Weights Table    \n*/\n\n/**    \n* \\par    \n* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    \n* \\par    \n* C command to generate the table    \n* 
    \n* for(i = 0; i< N; i++)    \n* {    \n*   weights[2*i]= cos(i*c);    \n*   weights[(2*i)+1]= -sin(i * c);    \n* } 
    \n* \\par    \n* where N is the Number of weights to be calculated and c is pi/(2*N)    \n* \\par    \n* Converted the output to q15 format by multiplying with 2^31 and saturated if required.    \n* \\par    \n* In the tables below the real and imaginary values are placed alternatively, hence the    \n* array length is 2*N.    \n*/\n\nstatic const q15_t ALIGN4 WeightsQ15_128[256] = {\n  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,\n  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,\n  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,\n  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,\n  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,\n  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,\n  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,\n  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,\n  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,\n  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,\n  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,\n  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,\n  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,\n  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,\n  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,\n  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,\n  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,\n  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,\n  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,\n  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,\n  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,\n  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,\n  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,\n  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,\n  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,\n  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,\n  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,\n  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,\n  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,\n  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,\n  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,\n  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,\n};\n\nstatic const q15_t ALIGN4 WeightsQ15_512[1024] = {\n  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,\n  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,\n  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,\n  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,\n  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,\n  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,\n  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,\n  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,\n  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,\n  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,\n  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,\n  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,\n  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,\n  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,\n  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,\n  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,\n  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,\n  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,\n  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,\n  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,\n  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,\n  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,\n  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,\n  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,\n  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,\n  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,\n  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,\n  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,\n  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,\n  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,\n  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,\n  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,\n  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,\n  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,\n  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,\n  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,\n  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,\n  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,\n  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,\n  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,\n  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,\n  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,\n  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,\n  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,\n  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,\n  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,\n  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,\n  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,\n  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,\n  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,\n  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,\n  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,\n  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,\n  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,\n  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,\n  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,\n  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,\n  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,\n  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,\n  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,\n  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,\n  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,\n  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,\n  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,\n  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,\n  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,\n  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,\n  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,\n  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,\n  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,\n  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,\n  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,\n  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,\n  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,\n  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,\n  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,\n  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,\n  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,\n  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,\n  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,\n  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,\n  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,\n  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,\n  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,\n  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,\n  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,\n  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,\n  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,\n  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,\n  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,\n  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,\n  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,\n  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,\n  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,\n  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,\n  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,\n  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,\n  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,\n  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,\n  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,\n  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,\n  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,\n  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,\n  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,\n  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,\n  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,\n  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,\n  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,\n  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,\n  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,\n  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,\n  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,\n  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,\n  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,\n  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,\n  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,\n  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,\n  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,\n  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,\n  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,\n  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,\n  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,\n  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,\n  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,\n  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,\n  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,\n  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,\n  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,\n};\n\nstatic const q15_t ALIGN4 WeightsQ15_2048[4096] = {\n  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,\n  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,\n  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,\n  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,\n  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,\n  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,\n  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,\n  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,\n  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,\n  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,\n  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,\n  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,\n  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,\n  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,\n  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,\n  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,\n  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,\n  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,\n  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,\n  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,\n  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,\n  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,\n  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,\n  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,\n  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,\n  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,\n  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,\n  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,\n  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,\n  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,\n  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,\n  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,\n  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,\n  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,\n  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,\n  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,\n  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,\n  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,\n  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,\n  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,\n  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,\n  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,\n  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,\n  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,\n  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,\n  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,\n  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,\n  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,\n  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,\n  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,\n  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,\n  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,\n  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,\n  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,\n  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,\n  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,\n  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,\n  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,\n  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,\n  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,\n  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,\n  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,\n  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,\n  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,\n  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,\n  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,\n  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,\n  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,\n  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,\n  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,\n  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,\n  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,\n  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,\n  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,\n  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,\n  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,\n  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,\n  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,\n  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,\n  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,\n  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,\n  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,\n  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,\n  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,\n  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,\n  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,\n  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,\n  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,\n  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,\n  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,\n  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,\n  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,\n  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,\n  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,\n  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,\n  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,\n  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,\n  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,\n  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,\n  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,\n  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,\n  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,\n  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,\n  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,\n  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,\n  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,\n  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,\n  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,\n  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,\n  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,\n  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,\n  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,\n  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,\n  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,\n  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,\n  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,\n  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,\n  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,\n  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,\n  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,\n  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,\n  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,\n  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,\n  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,\n  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,\n  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,\n  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,\n  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,\n  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,\n  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,\n  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,\n  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,\n  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,\n  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,\n  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,\n  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,\n  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,\n  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,\n  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,\n  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,\n  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,\n  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,\n  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,\n  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,\n  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,\n  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 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0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,\n  0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,\n  0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,\n  0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,\n  0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,\n  0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,\n  0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,\n  0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,\n  0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,\n  0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,\n  0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,\n  0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,\n  0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,\n  0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,\n  0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,\n  0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,\n  0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,\n  0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,\n  0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,\n  0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,\n  0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,\n  0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,\n  0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,\n  0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,\n  0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,\n  0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,\n  0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,\n  0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,\n  0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,\n  0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,\n  0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,\n  0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,\n  0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,\n  0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,\n  0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,\n  0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,\n  0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,\n  0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,\n  0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,\n  0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,\n  0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,\n  0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,\n  0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,\n  0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,\n  0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,\n  0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,\n  0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,\n  0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,\n  0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,\n  0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,\n  0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,\n  0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,\n  0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,\n  0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,\n  0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,\n  0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,\n  0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,\n  0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,\n  0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,\n  0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,\n  0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,\n  0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,\n  0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,\n  0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,\n  0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,\n  0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,\n  0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,\n  0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,\n  0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,\n  0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,\n  0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,\n  0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,\n  0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,\n  0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,\n  0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,\n  0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,\n  0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,\n  0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,\n  0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,\n  0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,\n  0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,\n  0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,\n  0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,\n  0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,\n  0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,\n  0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,\n  0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,\n  0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,\n  0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,\n  0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,\n  0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,\n  0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,\n  0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,\n  0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,\n  0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,\n  0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,\n  0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,\n  0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,\n  0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,\n  0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,\n  0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,\n  0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,\n  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,\n  0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,\n  0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,\n  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,\n  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,\n  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,\n  0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,\n  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,\n  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,\n  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,\n  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,\n  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,\n  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,\n  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,\n  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,\n  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,\n  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,\n  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,\n  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,\n  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,\n  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,\n  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,\n  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,\n  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,\n  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,\n  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,\n  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,\n  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,\n  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,\n  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,\n  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,\n  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,\n  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,\n  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,\n  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,\n  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,\n  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,\n  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,\n  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,\n  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,\n  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,\n  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,\n  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,\n  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,\n  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,\n  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,\n  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,\n  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,\n  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,\n  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,\n  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,\n  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,\n  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,\n  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,\n  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,\n  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,\n  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,\n  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,\n  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,\n  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,\n  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,\n  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,\n  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,\n  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,\n  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,\n  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,\n  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,\n  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,\n  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,\n  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,\n  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,\n  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,\n  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,\n  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,\n  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,\n  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,\n  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,\n  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,\n  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,\n  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,\n  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,\n  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,\n  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,\n  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,\n  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,\n  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,\n  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,\n  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,\n  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,\n  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,\n  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,\n  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,\n  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,\n  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,\n  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,\n  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,\n  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,\n  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,\n  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,\n  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,\n  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,\n  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,\n  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,\n  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,\n  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,\n  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,\n  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,\n  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,\n  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,\n  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,\n  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,\n  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,\n  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,\n  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,\n  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,\n  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,\n};\n\nstatic const q15_t ALIGN4 WeightsQ15_8192[16384] = {\n  0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,\n  0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,\n  0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,\n  0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,\n  0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,\n  0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,\n  0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,\n  0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,\n  0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,\n  0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,\n  0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,\n  0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,\n  0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,\n  0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,\n  0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,\n  0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,\n  0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,\n  0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,\n  0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,\n  0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,\n  0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,\n  0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,\n  0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,\n  0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,\n  0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,\n  0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,\n  0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,\n  0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,\n  0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,\n  0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,\n  0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,\n  0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,\n  0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,\n  0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,\n  0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,\n  0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,\n  0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,\n  0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,\n  0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,\n  0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,\n  0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,\n  0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,\n  0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,\n  0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,\n  0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,\n  0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,\n  0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,\n  0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,\n  0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,\n  0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,\n  0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,\n  0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,\n  0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,\n  0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,\n  0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,\n  0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,\n  0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,\n  0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,\n  0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,\n  0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,\n  0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,\n  0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,\n  0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,\n  0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,\n  0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,\n  0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,\n  0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 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0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,\n  0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,\n  0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,\n  0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,\n  0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,\n  0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,\n  0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,\n  0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,\n  0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,\n  0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,\n  0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,\n  0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,\n  0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,\n  0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,\n  0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,\n  0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,\n  0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,\n  0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,\n  0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,\n  0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,\n  0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,\n  0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,\n  0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,\n  0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,\n  0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,\n  0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,\n  0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,\n  0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,\n  0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,\n  0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,\n  0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,\n  0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,\n  0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,\n  0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,\n  0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,\n  0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,\n  0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,\n  0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,\n  0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,\n  0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,\n  0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,\n  0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,\n  0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,\n  0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,\n  0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,\n  0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,\n  0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,\n  0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,\n  0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,\n  0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,\n  0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,\n  0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,\n  0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,\n  0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,\n  0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,\n  0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,\n  0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,\n  0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,\n  0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,\n  0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,\n  0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,\n  0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,\n  0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,\n  0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,\n  0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,\n  0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,\n  0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,\n  0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,\n  0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,\n  0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,\n  0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,\n  0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,\n  0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,\n  0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,\n  0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,\n  0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,\n  0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,\n  0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,\n  0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,\n  0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,\n  0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,\n  0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,\n  0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,\n  0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,\n  0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,\n  0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,\n  0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,\n  0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,\n  0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,\n  0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,\n  0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,\n  0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,\n  0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,\n  0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,\n  0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,\n  0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,\n  0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,\n  0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,\n  0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,\n  0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,\n  0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,\n  0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,\n  0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,\n  0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,\n  0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,\n  0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,\n  0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,\n  0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,\n  0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,\n  0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,\n  0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,\n  0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,\n  0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,\n  0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,\n  0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,\n  0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,\n  0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,\n  0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,\n  0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,\n  0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,\n  0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,\n  0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,\n  0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,\n  0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,\n  0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,\n  0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,\n  0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,\n  0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,\n  0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,\n  0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,\n  0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,\n  0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,\n  0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,\n  0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,\n  0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,\n  0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,\n  0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,\n  0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,\n  0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,\n  0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,\n  0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,\n  0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,\n  0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,\n  0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,\n  0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,\n  0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,\n  0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,\n  0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,\n  0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,\n  0x7141, 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0xbf41, 0x6e67, 0xbf3b,\n  0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,\n  0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,\n  0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,\n  0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,\n  0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,\n  0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,\n  0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,\n  0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,\n  0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,\n  0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,\n  0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,\n  0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,\n  0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,\n  0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,\n  0x6db0, 0xbe07, 0x6dac, 0xbe02, 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0xac49, 0x60cf, 0xac44,\n  0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,\n  0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,\n  0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,\n  0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,\n  0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,\n  0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,\n  0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,\n  0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,\n  0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,\n  0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,\n  0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,\n  0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,\n  0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,\n  0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,\n  0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,\n  0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,\n  0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,\n  0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,\n  0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,\n  0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,\n  0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,\n  0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,\n  0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,\n  0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,\n  0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,\n  0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,\n  0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,\n  0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,\n  0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,\n  0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,\n  0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,\n  0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,\n  0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,\n  0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,\n  0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,\n  0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,\n  0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,\n  0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,\n  0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,\n  0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,\n  0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,\n  0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,\n  0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,\n  0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,\n  0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,\n  0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,\n  0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,\n  0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,\n  0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,\n  0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,\n  0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,\n  0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,\n  0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,\n  0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,\n  0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,\n  0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,\n  0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,\n  0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,\n  0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,\n  0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,\n  0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,\n  0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,\n  0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,\n  0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,\n  0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,\n  0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,\n  0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,\n  0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,\n  0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,\n  0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,\n  0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,\n  0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,\n  0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,\n  0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,\n  0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,\n  0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,\n  0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,\n  0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,\n  0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,\n  0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,\n  0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,\n  0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,\n  0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,\n  0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,\n  0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,\n  0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,\n  0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,\n  0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,\n  0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,\n  0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,\n  0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,\n  0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,\n  0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,\n  0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,\n  0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,\n  0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,\n  0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,\n  0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,\n  0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,\n  0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,\n  0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,\n  0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,\n  0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,\n  0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,\n  0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,\n  0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,\n  0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,\n  0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,\n  0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,\n  0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,\n  0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,\n  0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,\n  0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,\n  0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,\n  0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,\n  0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,\n  0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,\n  0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,\n  0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,\n  0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,\n  0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,\n  0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,\n  0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,\n  0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,\n  0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,\n  0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,\n  0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,\n  0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,\n  0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,\n  0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,\n  0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,\n  0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,\n  0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,\n  0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,\n  0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,\n  0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,\n  0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,\n  0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,\n  0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,\n  0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,\n  0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,\n  0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,\n  0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,\n  0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,\n  0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,\n  0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,\n  0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,\n  0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,\n  0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,\n  0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,\n  0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,\n  0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,\n  0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,\n  0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,\n  0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,\n  0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,\n  0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,\n  0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,\n  0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,\n  0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,\n  0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,\n  0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,\n  0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,\n  0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,\n  0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,\n  0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,\n  0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,\n  0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,\n  0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,\n  0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,\n  0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,\n  0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,\n  0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,\n  0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,\n  0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,\n  0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,\n  0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,\n  0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,\n  0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,\n  0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,\n  0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,\n  0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,\n  0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,\n  0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,\n  0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,\n  0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,\n  0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,\n  0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,\n  0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,\n  0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,\n  0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,\n  0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,\n  0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,\n  0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,\n  0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,\n  0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,\n  0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,\n  0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,\n  0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,\n  0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,\n  0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,\n  0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,\n  0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,\n  0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,\n  0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,\n  0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,\n  0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,\n  0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,\n  0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,\n  0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,\n  0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,\n  0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,\n  0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,\n  0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,\n  0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,\n  0x51bb, 0x9d7e, 0x51b6, 0x9d7a, 0x51b1, 0x9d76, 0x51ac, 0x9d72,\n  0x51a8, 0x9d6e, 0x51a3, 0x9d6a, 0x519e, 0x9d66, 0x5199, 0x9d62,\n  0x5194, 0x9d5e, 0x518f, 0x9d5a, 0x518b, 0x9d56, 0x5186, 0x9d52,\n  0x5181, 0x9d4e, 0x517c, 0x9d4a, 0x5177, 0x9d46, 0x5172, 0x9d42,\n  0x516e, 0x9d3e, 0x5169, 0x9d3a, 0x5164, 0x9d36, 0x515f, 0x9d32,\n  0x515a, 0x9d2e, 0x5155, 0x9d2a, 0x5150, 0x9d26, 0x514c, 0x9d22,\n  0x5147, 0x9d1e, 0x5142, 0x9d1a, 0x513d, 0x9d16, 0x5138, 0x9d12,\n  0x5133, 0x9d0e, 0x512e, 0x9d0b, 0x512a, 0x9d07, 0x5125, 0x9d03,\n  0x5120, 0x9cff, 0x511b, 0x9cfb, 0x5116, 0x9cf7, 0x5111, 0x9cf3,\n  0x510c, 0x9cef, 0x5108, 0x9ceb, 0x5103, 0x9ce7, 0x50fe, 0x9ce3,\n  0x50f9, 0x9cdf, 0x50f4, 0x9cdb, 0x50ef, 0x9cd7, 0x50ea, 0x9cd3,\n  0x50e5, 0x9ccf, 0x50e1, 0x9ccb, 0x50dc, 0x9cc7, 0x50d7, 0x9cc3,\n  0x50d2, 0x9cbf, 0x50cd, 0x9cbb, 0x50c8, 0x9cb7, 0x50c3, 0x9cb3,\n  0x50bf, 0x9caf, 0x50ba, 0x9cab, 0x50b5, 0x9ca7, 0x50b0, 0x9ca3,\n  0x50ab, 0x9c9f, 0x50a6, 0x9c9b, 0x50a1, 0x9c97, 0x509c, 0x9c93,\n  0x5097, 0x9c8f, 0x5093, 0x9c8b, 0x508e, 0x9c88, 0x5089, 0x9c84,\n  0x5084, 0x9c80, 0x507f, 0x9c7c, 0x507a, 0x9c78, 0x5075, 0x9c74,\n  0x5070, 0x9c70, 0x506c, 0x9c6c, 0x5067, 0x9c68, 0x5062, 0x9c64,\n  0x505d, 0x9c60, 0x5058, 0x9c5c, 0x5053, 0x9c58, 0x504e, 0x9c54,\n  0x5049, 0x9c50, 0x5044, 0x9c4c, 0x503f, 0x9c48, 0x503b, 0x9c44,\n  0x5036, 0x9c40, 0x5031, 0x9c3d, 0x502c, 0x9c39, 0x5027, 0x9c35,\n  0x5022, 0x9c31, 0x501d, 0x9c2d, 0x5018, 0x9c29, 0x5013, 0x9c25,\n  0x500f, 0x9c21, 0x500a, 0x9c1d, 0x5005, 0x9c19, 0x5000, 0x9c15,\n  0x4ffb, 0x9c11, 0x4ff6, 0x9c0d, 0x4ff1, 0x9c09, 0x4fec, 0x9c06,\n  0x4fe7, 0x9c02, 0x4fe2, 0x9bfe, 0x4fdd, 0x9bfa, 0x4fd9, 0x9bf6,\n  0x4fd4, 0x9bf2, 0x4fcf, 0x9bee, 0x4fca, 0x9bea, 0x4fc5, 0x9be6,\n  0x4fc0, 0x9be2, 0x4fbb, 0x9bde, 0x4fb6, 0x9bda, 0x4fb1, 0x9bd7,\n  0x4fac, 0x9bd3, 0x4fa7, 0x9bcf, 0x4fa2, 0x9bcb, 0x4f9e, 0x9bc7,\n  0x4f99, 0x9bc3, 0x4f94, 0x9bbf, 0x4f8f, 0x9bbb, 0x4f8a, 0x9bb7,\n  0x4f85, 0x9bb3, 0x4f80, 0x9baf, 0x4f7b, 0x9bac, 0x4f76, 0x9ba8,\n  0x4f71, 0x9ba4, 0x4f6c, 0x9ba0, 0x4f67, 0x9b9c, 0x4f62, 0x9b98,\n  0x4f5e, 0x9b94, 0x4f59, 0x9b90, 0x4f54, 0x9b8c, 0x4f4f, 0x9b88,\n  0x4f4a, 0x9b85, 0x4f45, 0x9b81, 0x4f40, 0x9b7d, 0x4f3b, 0x9b79,\n  0x4f36, 0x9b75, 0x4f31, 0x9b71, 0x4f2c, 0x9b6d, 0x4f27, 0x9b69,\n  0x4f22, 0x9b65, 0x4f1d, 0x9b62, 0x4f18, 0x9b5e, 0x4f14, 0x9b5a,\n  0x4f0f, 0x9b56, 0x4f0a, 0x9b52, 0x4f05, 0x9b4e, 0x4f00, 0x9b4a,\n  0x4efb, 0x9b46, 0x4ef6, 0x9b43, 0x4ef1, 0x9b3f, 0x4eec, 0x9b3b,\n  0x4ee7, 0x9b37, 0x4ee2, 0x9b33, 0x4edd, 0x9b2f, 0x4ed8, 0x9b2b,\n  0x4ed3, 0x9b27, 0x4ece, 0x9b24, 0x4ec9, 0x9b20, 0x4ec4, 0x9b1c,\n  0x4ebf, 0x9b18, 0x4eba, 0x9b14, 0x4eb6, 0x9b10, 0x4eb1, 0x9b0c,\n  0x4eac, 0x9b09, 0x4ea7, 0x9b05, 0x4ea2, 0x9b01, 0x4e9d, 0x9afd,\n  0x4e98, 0x9af9, 0x4e93, 0x9af5, 0x4e8e, 0x9af1, 0x4e89, 0x9aed,\n  0x4e84, 0x9aea, 0x4e7f, 0x9ae6, 0x4e7a, 0x9ae2, 0x4e75, 0x9ade,\n  0x4e70, 0x9ada, 0x4e6b, 0x9ad6, 0x4e66, 0x9ad3, 0x4e61, 0x9acf,\n  0x4e5c, 0x9acb, 0x4e57, 0x9ac7, 0x4e52, 0x9ac3, 0x4e4d, 0x9abf,\n  0x4e48, 0x9abb, 0x4e43, 0x9ab8, 0x4e3e, 0x9ab4, 0x4e39, 0x9ab0,\n  0x4e34, 0x9aac, 0x4e2f, 0x9aa8, 0x4e2a, 0x9aa4, 0x4e26, 0x9aa1,\n  0x4e21, 0x9a9d, 0x4e1c, 0x9a99, 0x4e17, 0x9a95, 0x4e12, 0x9a91,\n  0x4e0d, 0x9a8d, 0x4e08, 0x9a8a, 0x4e03, 0x9a86, 0x4dfe, 0x9a82,\n  0x4df9, 0x9a7e, 0x4df4, 0x9a7a, 0x4def, 0x9a76, 0x4dea, 0x9a73,\n  0x4de5, 0x9a6f, 0x4de0, 0x9a6b, 0x4ddb, 0x9a67, 0x4dd6, 0x9a63,\n  0x4dd1, 0x9a60, 0x4dcc, 0x9a5c, 0x4dc7, 0x9a58, 0x4dc2, 0x9a54,\n  0x4dbd, 0x9a50, 0x4db8, 0x9a4c, 0x4db3, 0x9a49, 0x4dae, 0x9a45,\n  0x4da9, 0x9a41, 0x4da4, 0x9a3d, 0x4d9f, 0x9a39, 0x4d9a, 0x9a36,\n  0x4d95, 0x9a32, 0x4d90, 0x9a2e, 0x4d8b, 0x9a2a, 0x4d86, 0x9a26,\n  0x4d81, 0x9a23, 0x4d7c, 0x9a1f, 0x4d77, 0x9a1b, 0x4d72, 0x9a17,\n  0x4d6d, 0x9a13, 0x4d68, 0x9a10, 0x4d63, 0x9a0c, 0x4d5e, 0x9a08,\n  0x4d59, 0x9a04, 0x4d54, 0x9a00, 0x4d4f, 0x99fd, 0x4d4a, 0x99f9,\n  0x4d45, 0x99f5, 0x4d40, 0x99f1, 0x4d3b, 0x99ed, 0x4d36, 0x99ea,\n  0x4d31, 0x99e6, 0x4d2c, 0x99e2, 0x4d27, 0x99de, 0x4d22, 0x99da,\n  0x4d1d, 0x99d7, 0x4d18, 0x99d3, 0x4d13, 0x99cf, 0x4d0e, 0x99cb,\n  0x4d09, 0x99c7, 0x4d04, 0x99c4, 0x4cff, 0x99c0, 0x4cfa, 0x99bc,\n  0x4cf5, 0x99b8, 0x4cf0, 0x99b5, 0x4ceb, 0x99b1, 0x4ce6, 0x99ad,\n  0x4ce1, 0x99a9, 0x4cdb, 0x99a5, 0x4cd6, 0x99a2, 0x4cd1, 0x999e,\n  0x4ccc, 0x999a, 0x4cc7, 0x9996, 0x4cc2, 0x9993, 0x4cbd, 0x998f,\n  0x4cb8, 0x998b, 0x4cb3, 0x9987, 0x4cae, 0x9984, 0x4ca9, 0x9980,\n  0x4ca4, 0x997c, 0x4c9f, 0x9978, 0x4c9a, 0x9975, 0x4c95, 0x9971,\n  0x4c90, 0x996d, 0x4c8b, 0x9969, 0x4c86, 0x9965, 0x4c81, 0x9962,\n  0x4c7c, 0x995e, 0x4c77, 0x995a, 0x4c72, 0x9956, 0x4c6d, 0x9953,\n  0x4c68, 0x994f, 0x4c63, 0x994b, 0x4c5e, 0x9947, 0x4c59, 0x9944,\n  0x4c54, 0x9940, 0x4c4f, 0x993c, 0x4c49, 0x9938, 0x4c44, 0x9935,\n  0x4c3f, 0x9931, 0x4c3a, 0x992d, 0x4c35, 0x992a, 0x4c30, 0x9926,\n  0x4c2b, 0x9922, 0x4c26, 0x991e, 0x4c21, 0x991b, 0x4c1c, 0x9917,\n  0x4c17, 0x9913, 0x4c12, 0x990f, 0x4c0d, 0x990c, 0x4c08, 0x9908,\n  0x4c03, 0x9904, 0x4bfe, 0x9900, 0x4bf9, 0x98fd, 0x4bf4, 0x98f9,\n  0x4bef, 0x98f5, 0x4be9, 0x98f2, 0x4be4, 0x98ee, 0x4bdf, 0x98ea,\n  0x4bda, 0x98e6, 0x4bd5, 0x98e3, 0x4bd0, 0x98df, 0x4bcb, 0x98db,\n  0x4bc6, 0x98d7, 0x4bc1, 0x98d4, 0x4bbc, 0x98d0, 0x4bb7, 0x98cc,\n  0x4bb2, 0x98c9, 0x4bad, 0x98c5, 0x4ba8, 0x98c1, 0x4ba3, 0x98bd,\n  0x4b9e, 0x98ba, 0x4b98, 0x98b6, 0x4b93, 0x98b2, 0x4b8e, 0x98af,\n  0x4b89, 0x98ab, 0x4b84, 0x98a7, 0x4b7f, 0x98a3, 0x4b7a, 0x98a0,\n  0x4b75, 0x989c, 0x4b70, 0x9898, 0x4b6b, 0x9895, 0x4b66, 0x9891,\n  0x4b61, 0x988d, 0x4b5c, 0x988a, 0x4b56, 0x9886, 0x4b51, 0x9882,\n  0x4b4c, 0x987e, 0x4b47, 0x987b, 0x4b42, 0x9877, 0x4b3d, 0x9873,\n  0x4b38, 0x9870, 0x4b33, 0x986c, 0x4b2e, 0x9868, 0x4b29, 0x9865,\n  0x4b24, 0x9861, 0x4b1f, 0x985d, 0x4b19, 0x985a, 0x4b14, 0x9856,\n  0x4b0f, 0x9852, 0x4b0a, 0x984e, 0x4b05, 0x984b, 0x4b00, 0x9847,\n  0x4afb, 0x9843, 0x4af6, 0x9840, 0x4af1, 0x983c, 0x4aec, 0x9838,\n  0x4ae7, 0x9835, 0x4ae1, 0x9831, 0x4adc, 0x982d, 0x4ad7, 0x982a,\n  0x4ad2, 0x9826, 0x4acd, 0x9822, 0x4ac8, 0x981f, 0x4ac3, 0x981b,\n  0x4abe, 0x9817, 0x4ab9, 0x9814, 0x4ab4, 0x9810, 0x4aae, 0x980c,\n  0x4aa9, 0x9809, 0x4aa4, 0x9805, 0x4a9f, 0x9801, 0x4a9a, 0x97fe,\n  0x4a95, 0x97fa, 0x4a90, 0x97f6, 0x4a8b, 0x97f3, 0x4a86, 0x97ef,\n  0x4a81, 0x97eb, 0x4a7b, 0x97e8, 0x4a76, 0x97e4, 0x4a71, 0x97e0,\n  0x4a6c, 0x97dd, 0x4a67, 0x97d9, 0x4a62, 0x97d5, 0x4a5d, 0x97d2,\n  0x4a58, 0x97ce, 0x4a52, 0x97cb, 0x4a4d, 0x97c7, 0x4a48, 0x97c3,\n  0x4a43, 0x97c0, 0x4a3e, 0x97bc, 0x4a39, 0x97b8, 0x4a34, 0x97b5,\n  0x4a2f, 0x97b1, 0x4a2a, 0x97ad, 0x4a24, 0x97aa, 0x4a1f, 0x97a6,\n  0x4a1a, 0x97a2, 0x4a15, 0x979f, 0x4a10, 0x979b, 0x4a0b, 0x9798,\n  0x4a06, 0x9794, 0x4a01, 0x9790, 0x49fb, 0x978d, 0x49f6, 0x9789,\n  0x49f1, 0x9785, 0x49ec, 0x9782, 0x49e7, 0x977e, 0x49e2, 0x977a,\n  0x49dd, 0x9777, 0x49d8, 0x9773, 0x49d2, 0x9770, 0x49cd, 0x976c,\n  0x49c8, 0x9768, 0x49c3, 0x9765, 0x49be, 0x9761, 0x49b9, 0x975d,\n  0x49b4, 0x975a, 0x49ae, 0x9756, 0x49a9, 0x9753, 0x49a4, 0x974f,\n  0x499f, 0x974b, 0x499a, 0x9748, 0x4995, 0x9744, 0x4990, 0x9741,\n  0x498a, 0x973d, 0x4985, 0x9739, 0x4980, 0x9736, 0x497b, 0x9732,\n  0x4976, 0x972f, 0x4971, 0x972b, 0x496c, 0x9727, 0x4966, 0x9724,\n  0x4961, 0x9720, 0x495c, 0x971d, 0x4957, 0x9719, 0x4952, 0x9715,\n  0x494d, 0x9712, 0x4948, 0x970e, 0x4942, 0x970b, 0x493d, 0x9707,\n  0x4938, 0x9703, 0x4933, 0x9700, 0x492e, 0x96fc, 0x4929, 0x96f9,\n  0x4923, 0x96f5, 0x491e, 0x96f1, 0x4919, 0x96ee, 0x4914, 0x96ea,\n  0x490f, 0x96e7, 0x490a, 0x96e3, 0x4905, 0x96df, 0x48ff, 0x96dc,\n  0x48fa, 0x96d8, 0x48f5, 0x96d5, 0x48f0, 0x96d1, 0x48eb, 0x96ce,\n  0x48e6, 0x96ca, 0x48e0, 0x96c6, 0x48db, 0x96c3, 0x48d6, 0x96bf,\n  0x48d1, 0x96bc, 0x48cc, 0x96b8, 0x48c7, 0x96b5, 0x48c1, 0x96b1,\n  0x48bc, 0x96ad, 0x48b7, 0x96aa, 0x48b2, 0x96a6, 0x48ad, 0x96a3,\n  0x48a8, 0x969f, 0x48a2, 0x969c, 0x489d, 0x9698, 0x4898, 0x9694,\n  0x4893, 0x9691, 0x488e, 0x968d, 0x4888, 0x968a, 0x4883, 0x9686,\n  0x487e, 0x9683, 0x4879, 0x967f, 0x4874, 0x967b, 0x486f, 0x9678,\n  0x4869, 0x9674, 0x4864, 0x9671, 0x485f, 0x966d, 0x485a, 0x966a,\n  0x4855, 0x9666, 0x484f, 0x9663, 0x484a, 0x965f, 0x4845, 0x965b,\n  0x4840, 0x9658, 0x483b, 0x9654, 0x4836, 0x9651, 0x4830, 0x964d,\n  0x482b, 0x964a, 0x4826, 0x9646, 0x4821, 0x9643, 0x481c, 0x963f,\n  0x4816, 0x963c, 0x4811, 0x9638, 0x480c, 0x9635, 0x4807, 0x9631,\n  0x4802, 0x962d, 0x47fc, 0x962a, 0x47f7, 0x9626, 0x47f2, 0x9623,\n  0x47ed, 0x961f, 0x47e8, 0x961c, 0x47e2, 0x9618, 0x47dd, 0x9615,\n  0x47d8, 0x9611, 0x47d3, 0x960e, 0x47ce, 0x960a, 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0x9538, 0x468f, 0x9535,\n  0x468a, 0x9532, 0x4685, 0x952e, 0x467f, 0x952b, 0x467a, 0x9527,\n  0x4675, 0x9524, 0x4670, 0x9520, 0x466a, 0x951d, 0x4665, 0x9519,\n  0x4660, 0x9516, 0x465b, 0x9512, 0x4655, 0x950f, 0x4650, 0x950c,\n  0x464b, 0x9508, 0x4646, 0x9505, 0x4640, 0x9501, 0x463b, 0x94fe,\n  0x4636, 0x94fa, 0x4631, 0x94f7, 0x462b, 0x94f3, 0x4626, 0x94f0,\n  0x4621, 0x94ed, 0x461c, 0x94e9, 0x4616, 0x94e6, 0x4611, 0x94e2,\n  0x460c, 0x94df, 0x4607, 0x94db, 0x4601, 0x94d8, 0x45fc, 0x94d4,\n  0x45f7, 0x94d1, 0x45f2, 0x94ce, 0x45ec, 0x94ca, 0x45e7, 0x94c7,\n  0x45e2, 0x94c3, 0x45dd, 0x94c0, 0x45d7, 0x94bc, 0x45d2, 0x94b9,\n  0x45cd, 0x94b6, 0x45c7, 0x94b2, 0x45c2, 0x94af, 0x45bd, 0x94ab,\n  0x45b8, 0x94a8, 0x45b2, 0x94a4, 0x45ad, 0x94a1, 0x45a8, 0x949e,\n  0x45a3, 0x949a, 0x459d, 0x9497, 0x4598, 0x9493, 0x4593, 0x9490,\n  0x458d, 0x948d, 0x4588, 0x9489, 0x4583, 0x9486, 0x457e, 0x9482,\n  0x4578, 0x947f, 0x4573, 0x947b, 0x456e, 0x9478, 0x4569, 0x9475,\n  0x4563, 0x9471, 0x455e, 0x946e, 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0x93a3, 0x441b, 0x93a0, 0x4415, 0x939d,\n  0x4410, 0x9399, 0x440b, 0x9396, 0x4405, 0x9393, 0x4400, 0x938f,\n  0x43fb, 0x938c, 0x43f5, 0x9389, 0x43f0, 0x9385, 0x43eb, 0x9382,\n  0x43e5, 0x937f, 0x43e0, 0x937b, 0x43db, 0x9378, 0x43d5, 0x9375,\n  0x43d0, 0x9371, 0x43cb, 0x936e, 0x43c5, 0x936b, 0x43c0, 0x9367,\n  0x43bb, 0x9364, 0x43b5, 0x9361, 0x43b0, 0x935d, 0x43ab, 0x935a,\n  0x43a5, 0x9357, 0x43a0, 0x9353, 0x439b, 0x9350, 0x4395, 0x934d,\n  0x4390, 0x9349, 0x438b, 0x9346, 0x4385, 0x9343, 0x4380, 0x933f,\n  0x437b, 0x933c, 0x4375, 0x9339, 0x4370, 0x9336, 0x436b, 0x9332,\n  0x4365, 0x932f, 0x4360, 0x932c, 0x435b, 0x9328, 0x4355, 0x9325,\n  0x4350, 0x9322, 0x434b, 0x931e, 0x4345, 0x931b, 0x4340, 0x9318,\n  0x433b, 0x9314, 0x4335, 0x9311, 0x4330, 0x930e, 0x432b, 0x930b,\n  0x4325, 0x9307, 0x4320, 0x9304, 0x431b, 0x9301, 0x4315, 0x92fd,\n  0x4310, 0x92fa, 0x430b, 0x92f7, 0x4305, 0x92f4, 0x4300, 0x92f0,\n  0x42fa, 0x92ed, 0x42f5, 0x92ea, 0x42f0, 0x92e6, 0x42ea, 0x92e3,\n  0x42e5, 0x92e0, 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0x921d, 0x419d, 0x9219, 0x4198, 0x9216, 0x4192, 0x9213,\n  0x418d, 0x9210, 0x4188, 0x920d, 0x4182, 0x9209, 0x417d, 0x9206,\n  0x4177, 0x9203, 0x4172, 0x9200, 0x416d, 0x91fc, 0x4167, 0x91f9,\n  0x4162, 0x91f6, 0x415c, 0x91f3, 0x4157, 0x91f0, 0x4152, 0x91ec,\n  0x414c, 0x91e9, 0x4147, 0x91e6, 0x4141, 0x91e3, 0x413c, 0x91e0,\n  0x4136, 0x91dc, 0x4131, 0x91d9, 0x412c, 0x91d6, 0x4126, 0x91d3,\n  0x4121, 0x91d0, 0x411b, 0x91cc, 0x4116, 0x91c9, 0x4111, 0x91c6,\n  0x410b, 0x91c3, 0x4106, 0x91c0, 0x4100, 0x91bc, 0x40fb, 0x91b9,\n  0x40f6, 0x91b6, 0x40f0, 0x91b3, 0x40eb, 0x91b0, 0x40e5, 0x91ad,\n  0x40e0, 0x91a9, 0x40da, 0x91a6, 0x40d5, 0x91a3, 0x40d0, 0x91a0,\n  0x40ca, 0x919d, 0x40c5, 0x9199, 0x40bf, 0x9196, 0x40ba, 0x9193,\n  0x40b5, 0x9190, 0x40af, 0x918d, 0x40aa, 0x918a, 0x40a4, 0x9186,\n  0x409f, 0x9183, 0x4099, 0x9180, 0x4094, 0x917d, 0x408f, 0x917a,\n  0x4089, 0x9177, 0x4084, 0x9173, 0x407e, 0x9170, 0x4079, 0x916d,\n  0x4073, 0x916a, 0x406e, 0x9167, 0x4069, 0x9164, 0x4063, 0x9160,\n  0x405e, 0x915d, 0x4058, 0x915a, 0x4053, 0x9157, 0x404d, 0x9154,\n  0x4048, 0x9151, 0x4043, 0x914d, 0x403d, 0x914a, 0x4038, 0x9147,\n  0x4032, 0x9144, 0x402d, 0x9141, 0x4027, 0x913e, 0x4022, 0x913a,\n  0x401d, 0x9137, 0x4017, 0x9134, 0x4012, 0x9131, 0x400c, 0x912e,\n  0x4007, 0x912b, 0x4001, 0x9128, 0x3ffc, 0x9124, 0x3ff6, 0x9121,\n  0x3ff1, 0x911e, 0x3fec, 0x911b, 0x3fe6, 0x9118, 0x3fe1, 0x9115,\n  0x3fdb, 0x9112, 0x3fd6, 0x910f, 0x3fd0, 0x910b, 0x3fcb, 0x9108,\n  0x3fc5, 0x9105, 0x3fc0, 0x9102, 0x3fbb, 0x90ff, 0x3fb5, 0x90fc,\n  0x3fb0, 0x90f9, 0x3faa, 0x90f5, 0x3fa5, 0x90f2, 0x3f9f, 0x90ef,\n  0x3f9a, 0x90ec, 0x3f94, 0x90e9, 0x3f8f, 0x90e6, 0x3f89, 0x90e3,\n  0x3f84, 0x90e0, 0x3f7f, 0x90dd, 0x3f79, 0x90d9, 0x3f74, 0x90d6,\n  0x3f6e, 0x90d3, 0x3f69, 0x90d0, 0x3f63, 0x90cd, 0x3f5e, 0x90ca,\n  0x3f58, 0x90c7, 0x3f53, 0x90c4, 0x3f4d, 0x90c1, 0x3f48, 0x90bd,\n  0x3f43, 0x90ba, 0x3f3d, 0x90b7, 0x3f38, 0x90b4, 0x3f32, 0x90b1,\n  0x3f2d, 0x90ae, 0x3f27, 0x90ab, 0x3f22, 0x90a8, 0x3f1c, 0x90a5,\n  0x3f17, 0x90a1, 0x3f11, 0x909e, 0x3f0c, 0x909b, 0x3f06, 0x9098,\n  0x3f01, 0x9095, 0x3efb, 0x9092, 0x3ef6, 0x908f, 0x3ef1, 0x908c,\n  0x3eeb, 0x9089, 0x3ee6, 0x9086, 0x3ee0, 0x9083, 0x3edb, 0x907f,\n  0x3ed5, 0x907c, 0x3ed0, 0x9079, 0x3eca, 0x9076, 0x3ec5, 0x9073,\n  0x3ebf, 0x9070, 0x3eba, 0x906d, 0x3eb4, 0x906a, 0x3eaf, 0x9067,\n  0x3ea9, 0x9064, 0x3ea4, 0x9061, 0x3e9e, 0x905e, 0x3e99, 0x905b,\n  0x3e93, 0x9057, 0x3e8e, 0x9054, 0x3e88, 0x9051, 0x3e83, 0x904e,\n  0x3e7d, 0x904b, 0x3e78, 0x9048, 0x3e73, 0x9045, 0x3e6d, 0x9042,\n  0x3e68, 0x903f, 0x3e62, 0x903c, 0x3e5d, 0x9039, 0x3e57, 0x9036,\n  0x3e52, 0x9033, 0x3e4c, 0x9030, 0x3e47, 0x902d, 0x3e41, 0x902a,\n  0x3e3c, 0x9026, 0x3e36, 0x9023, 0x3e31, 0x9020, 0x3e2b, 0x901d,\n  0x3e26, 0x901a, 0x3e20, 0x9017, 0x3e1b, 0x9014, 0x3e15, 0x9011,\n  0x3e10, 0x900e, 0x3e0a, 0x900b, 0x3e05, 0x9008, 0x3dff, 0x9005,\n  0x3dfa, 0x9002, 0x3df4, 0x8fff, 0x3def, 0x8ffc, 0x3de9, 0x8ff9,\n  0x3de4, 0x8ff6, 0x3dde, 0x8ff3, 0x3dd9, 0x8ff0, 0x3dd3, 0x8fed,\n  0x3dce, 0x8fea, 0x3dc8, 0x8fe7, 0x3dc3, 0x8fe3, 0x3dbd, 0x8fe0,\n  0x3db8, 0x8fdd, 0x3db2, 0x8fda, 0x3dad, 0x8fd7, 0x3da7, 0x8fd4,\n  0x3da2, 0x8fd1, 0x3d9c, 0x8fce, 0x3d97, 0x8fcb, 0x3d91, 0x8fc8,\n  0x3d8c, 0x8fc5, 0x3d86, 0x8fc2, 0x3d81, 0x8fbf, 0x3d7b, 0x8fbc,\n  0x3d76, 0x8fb9, 0x3d70, 0x8fb6, 0x3d6b, 0x8fb3, 0x3d65, 0x8fb0,\n  0x3d60, 0x8fad, 0x3d5a, 0x8faa, 0x3d55, 0x8fa7, 0x3d4f, 0x8fa4,\n  0x3d49, 0x8fa1, 0x3d44, 0x8f9e, 0x3d3e, 0x8f9b, 0x3d39, 0x8f98,\n  0x3d33, 0x8f95, 0x3d2e, 0x8f92, 0x3d28, 0x8f8f, 0x3d23, 0x8f8c,\n  0x3d1d, 0x8f89, 0x3d18, 0x8f86, 0x3d12, 0x8f83, 0x3d0d, 0x8f80,\n  0x3d07, 0x8f7d, 0x3d02, 0x8f7a, 0x3cfc, 0x8f77, 0x3cf7, 0x8f74,\n  0x3cf1, 0x8f71, 0x3cec, 0x8f6e, 0x3ce6, 0x8f6b, 0x3ce1, 0x8f68,\n  0x3cdb, 0x8f65, 0x3cd6, 0x8f62, 0x3cd0, 0x8f5f, 0x3cca, 0x8f5c,\n  0x3cc5, 0x8f59, 0x3cbf, 0x8f56, 0x3cba, 0x8f53, 0x3cb4, 0x8f50,\n  0x3caf, 0x8f4d, 0x3ca9, 0x8f4a, 0x3ca4, 0x8f47, 0x3c9e, 0x8f44,\n  0x3c99, 0x8f41, 0x3c93, 0x8f3e, 0x3c8e, 0x8f3b, 0x3c88, 0x8f38,\n  0x3c83, 0x8f35, 0x3c7d, 0x8f32, 0x3c77, 0x8f2f, 0x3c72, 0x8f2d,\n  0x3c6c, 0x8f2a, 0x3c67, 0x8f27, 0x3c61, 0x8f24, 0x3c5c, 0x8f21,\n  0x3c56, 0x8f1e, 0x3c51, 0x8f1b, 0x3c4b, 0x8f18, 0x3c46, 0x8f15,\n  0x3c40, 0x8f12, 0x3c3b, 0x8f0f, 0x3c35, 0x8f0c, 0x3c2f, 0x8f09,\n  0x3c2a, 0x8f06, 0x3c24, 0x8f03, 0x3c1f, 0x8f00, 0x3c19, 0x8efd,\n  0x3c14, 0x8efa, 0x3c0e, 0x8ef7, 0x3c09, 0x8ef4, 0x3c03, 0x8ef1,\n  0x3bfd, 0x8eee, 0x3bf8, 0x8eec, 0x3bf2, 0x8ee9, 0x3bed, 0x8ee6,\n  0x3be7, 0x8ee3, 0x3be2, 0x8ee0, 0x3bdc, 0x8edd, 0x3bd7, 0x8eda,\n  0x3bd1, 0x8ed7, 0x3bcc, 0x8ed4, 0x3bc6, 0x8ed1, 0x3bc0, 0x8ece,\n  0x3bbb, 0x8ecb, 0x3bb5, 0x8ec8, 0x3bb0, 0x8ec5, 0x3baa, 0x8ec2,\n  0x3ba5, 0x8ebf, 0x3b9f, 0x8ebd, 0x3b99, 0x8eba, 0x3b94, 0x8eb7,\n  0x3b8e, 0x8eb4, 0x3b89, 0x8eb1, 0x3b83, 0x8eae, 0x3b7e, 0x8eab,\n  0x3b78, 0x8ea8, 0x3b73, 0x8ea5, 0x3b6d, 0x8ea2, 0x3b67, 0x8e9f,\n  0x3b62, 0x8e9c, 0x3b5c, 0x8e99, 0x3b57, 0x8e97, 0x3b51, 0x8e94,\n  0x3b4c, 0x8e91, 0x3b46, 0x8e8e, 0x3b40, 0x8e8b, 0x3b3b, 0x8e88,\n  0x3b35, 0x8e85, 0x3b30, 0x8e82, 0x3b2a, 0x8e7f, 0x3b25, 0x8e7c,\n  0x3b1f, 0x8e7a, 0x3b19, 0x8e77, 0x3b14, 0x8e74, 0x3b0e, 0x8e71,\n  0x3b09, 0x8e6e, 0x3b03, 0x8e6b, 0x3afe, 0x8e68, 0x3af8, 0x8e65,\n  0x3af2, 0x8e62, 0x3aed, 0x8e5f, 0x3ae7, 0x8e5d, 0x3ae2, 0x8e5a,\n  0x3adc, 0x8e57, 0x3ad7, 0x8e54, 0x3ad1, 0x8e51, 0x3acb, 0x8e4e,\n  0x3ac6, 0x8e4b, 0x3ac0, 0x8e48, 0x3abb, 0x8e45, 0x3ab5, 0x8e43,\n  0x3aaf, 0x8e40, 0x3aaa, 0x8e3d, 0x3aa4, 0x8e3a, 0x3a9f, 0x8e37,\n  0x3a99, 0x8e34, 0x3a94, 0x8e31, 0x3a8e, 0x8e2e, 0x3a88, 0x8e2c,\n  0x3a83, 0x8e29, 0x3a7d, 0x8e26, 0x3a78, 0x8e23, 0x3a72, 0x8e20,\n  0x3a6c, 0x8e1d, 0x3a67, 0x8e1a, 0x3a61, 0x8e17, 0x3a5c, 0x8e15,\n  0x3a56, 0x8e12, 0x3a50, 0x8e0f, 0x3a4b, 0x8e0c, 0x3a45, 0x8e09,\n  0x3a40, 0x8e06, 0x3a3a, 0x8e03, 0x3a34, 0x8e01, 0x3a2f, 0x8dfe,\n  0x3a29, 0x8dfb, 0x3a24, 0x8df8, 0x3a1e, 0x8df5, 0x3a19, 0x8df2,\n  0x3a13, 0x8def, 0x3a0d, 0x8ded, 0x3a08, 0x8dea, 0x3a02, 0x8de7,\n  0x39fd, 0x8de4, 0x39f7, 0x8de1, 0x39f1, 0x8dde, 0x39ec, 0x8ddc,\n  0x39e6, 0x8dd9, 0x39e0, 0x8dd6, 0x39db, 0x8dd3, 0x39d5, 0x8dd0,\n  0x39d0, 0x8dcd, 0x39ca, 0x8dca, 0x39c4, 0x8dc8, 0x39bf, 0x8dc5,\n  0x39b9, 0x8dc2, 0x39b4, 0x8dbf, 0x39ae, 0x8dbc, 0x39a8, 0x8db9,\n  0x39a3, 0x8db7, 0x399d, 0x8db4, 0x3998, 0x8db1, 0x3992, 0x8dae,\n  0x398c, 0x8dab, 0x3987, 0x8da9, 0x3981, 0x8da6, 0x397c, 0x8da3,\n  0x3976, 0x8da0, 0x3970, 0x8d9d, 0x396b, 0x8d9a, 0x3965, 0x8d98,\n  0x395f, 0x8d95, 0x395a, 0x8d92, 0x3954, 0x8d8f, 0x394f, 0x8d8c,\n  0x3949, 0x8d8a, 0x3943, 0x8d87, 0x393e, 0x8d84, 0x3938, 0x8d81,\n  0x3932, 0x8d7e, 0x392d, 0x8d7b, 0x3927, 0x8d79, 0x3922, 0x8d76,\n  0x391c, 0x8d73, 0x3916, 0x8d70, 0x3911, 0x8d6d, 0x390b, 0x8d6b,\n  0x3906, 0x8d68, 0x3900, 0x8d65, 0x38fa, 0x8d62, 0x38f5, 0x8d5f,\n  0x38ef, 0x8d5d, 0x38e9, 0x8d5a, 0x38e4, 0x8d57, 0x38de, 0x8d54,\n  0x38d8, 0x8d51, 0x38d3, 0x8d4f, 0x38cd, 0x8d4c, 0x38c8, 0x8d49,\n  0x38c2, 0x8d46, 0x38bc, 0x8d44, 0x38b7, 0x8d41, 0x38b1, 0x8d3e,\n  0x38ab, 0x8d3b, 0x38a6, 0x8d38, 0x38a0, 0x8d36, 0x389b, 0x8d33,\n  0x3895, 0x8d30, 0x388f, 0x8d2d, 0x388a, 0x8d2b, 0x3884, 0x8d28,\n  0x387e, 0x8d25, 0x3879, 0x8d22, 0x3873, 0x8d1f, 0x386d, 0x8d1d,\n  0x3868, 0x8d1a, 0x3862, 0x8d17, 0x385d, 0x8d14, 0x3857, 0x8d12,\n  0x3851, 0x8d0f, 0x384c, 0x8d0c, 0x3846, 0x8d09, 0x3840, 0x8d07,\n  0x383b, 0x8d04, 0x3835, 0x8d01, 0x382f, 0x8cfe, 0x382a, 0x8cfb,\n  0x3824, 0x8cf9, 0x381e, 0x8cf6, 0x3819, 0x8cf3, 0x3813, 0x8cf0,\n  0x380d, 0x8cee, 0x3808, 0x8ceb, 0x3802, 0x8ce8, 0x37fd, 0x8ce5,\n  0x37f7, 0x8ce3, 0x37f1, 0x8ce0, 0x37ec, 0x8cdd, 0x37e6, 0x8cda,\n  0x37e0, 0x8cd8, 0x37db, 0x8cd5, 0x37d5, 0x8cd2, 0x37cf, 0x8cd0,\n  0x37ca, 0x8ccd, 0x37c4, 0x8cca, 0x37be, 0x8cc7, 0x37b9, 0x8cc5,\n  0x37b3, 0x8cc2, 0x37ad, 0x8cbf, 0x37a8, 0x8cbc, 0x37a2, 0x8cba,\n  0x379c, 0x8cb7, 0x3797, 0x8cb4, 0x3791, 0x8cb1, 0x378b, 0x8caf,\n  0x3786, 0x8cac, 0x3780, 0x8ca9, 0x377a, 0x8ca7, 0x3775, 0x8ca4,\n  0x376f, 0x8ca1, 0x3769, 0x8c9e, 0x3764, 0x8c9c, 0x375e, 0x8c99,\n  0x3758, 0x8c96, 0x3753, 0x8c94, 0x374d, 0x8c91, 0x3747, 0x8c8e,\n  0x3742, 0x8c8b, 0x373c, 0x8c89, 0x3736, 0x8c86, 0x3731, 0x8c83,\n  0x372b, 0x8c81, 0x3725, 0x8c7e, 0x3720, 0x8c7b, 0x371a, 0x8c78,\n  0x3714, 0x8c76, 0x370f, 0x8c73, 0x3709, 0x8c70, 0x3703, 0x8c6e,\n  0x36fe, 0x8c6b, 0x36f8, 0x8c68, 0x36f2, 0x8c65, 0x36ed, 0x8c63,\n  0x36e7, 0x8c60, 0x36e1, 0x8c5d, 0x36dc, 0x8c5b, 0x36d6, 0x8c58,\n  0x36d0, 0x8c55, 0x36cb, 0x8c53, 0x36c5, 0x8c50, 0x36bf, 0x8c4d,\n  0x36ba, 0x8c4b, 0x36b4, 0x8c48, 0x36ae, 0x8c45, 0x36a9, 0x8c43,\n  0x36a3, 0x8c40, 0x369d, 0x8c3d, 0x3698, 0x8c3a, 0x3692, 0x8c38,\n  0x368c, 0x8c35, 0x3686, 0x8c32, 0x3681, 0x8c30, 0x367b, 0x8c2d,\n  0x3675, 0x8c2a, 0x3670, 0x8c28, 0x366a, 0x8c25, 0x3664, 0x8c22,\n  0x365f, 0x8c20, 0x3659, 0x8c1d, 0x3653, 0x8c1a, 0x364e, 0x8c18,\n  0x3648, 0x8c15, 0x3642, 0x8c12, 0x363d, 0x8c10, 0x3637, 0x8c0d,\n  0x3631, 0x8c0a, 0x362b, 0x8c08, 0x3626, 0x8c05, 0x3620, 0x8c02,\n  0x361a, 0x8c00, 0x3615, 0x8bfd, 0x360f, 0x8bfa, 0x3609, 0x8bf8,\n  0x3604, 0x8bf5, 0x35fe, 0x8bf3, 0x35f8, 0x8bf0, 0x35f3, 0x8bed,\n  0x35ed, 0x8beb, 0x35e7, 0x8be8, 0x35e1, 0x8be5, 0x35dc, 0x8be3,\n  0x35d6, 0x8be0, 0x35d0, 0x8bdd, 0x35cb, 0x8bdb, 0x35c5, 0x8bd8,\n  0x35bf, 0x8bd5, 0x35ba, 0x8bd3, 0x35b4, 0x8bd0, 0x35ae, 0x8bce,\n  0x35a8, 0x8bcb, 0x35a3, 0x8bc8, 0x359d, 0x8bc6, 0x3597, 0x8bc3,\n  0x3592, 0x8bc0, 0x358c, 0x8bbe, 0x3586, 0x8bbb, 0x3580, 0x8bb8,\n  0x357b, 0x8bb6, 0x3575, 0x8bb3, 0x356f, 0x8bb1, 0x356a, 0x8bae,\n  0x3564, 0x8bab, 0x355e, 0x8ba9, 0x3558, 0x8ba6, 0x3553, 0x8ba4,\n  0x354d, 0x8ba1, 0x3547, 0x8b9e, 0x3542, 0x8b9c, 0x353c, 0x8b99,\n  0x3536, 0x8b96, 0x3530, 0x8b94, 0x352b, 0x8b91, 0x3525, 0x8b8f,\n  0x351f, 0x8b8c, 0x351a, 0x8b89, 0x3514, 0x8b87, 0x350e, 0x8b84,\n  0x3508, 0x8b82, 0x3503, 0x8b7f, 0x34fd, 0x8b7c, 0x34f7, 0x8b7a,\n  0x34f2, 0x8b77, 0x34ec, 0x8b75, 0x34e6, 0x8b72, 0x34e0, 0x8b6f,\n  0x34db, 0x8b6d, 0x34d5, 0x8b6a, 0x34cf, 0x8b68, 0x34ca, 0x8b65,\n  0x34c4, 0x8b62, 0x34be, 0x8b60, 0x34b8, 0x8b5d, 0x34b3, 0x8b5b,\n  0x34ad, 0x8b58, 0x34a7, 0x8b55, 0x34a1, 0x8b53, 0x349c, 0x8b50,\n  0x3496, 0x8b4e, 0x3490, 0x8b4b, 0x348b, 0x8b49, 0x3485, 0x8b46,\n  0x347f, 0x8b43, 0x3479, 0x8b41, 0x3474, 0x8b3e, 0x346e, 0x8b3c,\n  0x3468, 0x8b39, 0x3462, 0x8b37, 0x345d, 0x8b34, 0x3457, 0x8b31,\n  0x3451, 0x8b2f, 0x344b, 0x8b2c, 0x3446, 0x8b2a, 0x3440, 0x8b27,\n  0x343a, 0x8b25, 0x3435, 0x8b22, 0x342f, 0x8b1f, 0x3429, 0x8b1d,\n  0x3423, 0x8b1a, 0x341e, 0x8b18, 0x3418, 0x8b15, 0x3412, 0x8b13,\n  0x340c, 0x8b10, 0x3407, 0x8b0e, 0x3401, 0x8b0b, 0x33fb, 0x8b08,\n  0x33f5, 0x8b06, 0x33f0, 0x8b03, 0x33ea, 0x8b01, 0x33e4, 0x8afe,\n  0x33de, 0x8afc, 0x33d9, 0x8af9, 0x33d3, 0x8af7, 0x33cd, 0x8af4,\n  0x33c7, 0x8af1, 0x33c2, 0x8aef, 0x33bc, 0x8aec, 0x33b6, 0x8aea,\n  0x33b0, 0x8ae7, 0x33ab, 0x8ae5, 0x33a5, 0x8ae2, 0x339f, 0x8ae0,\n  0x3399, 0x8add, 0x3394, 0x8adb, 0x338e, 0x8ad8, 0x3388, 0x8ad6,\n  0x3382, 0x8ad3, 0x337d, 0x8ad1, 0x3377, 0x8ace, 0x3371, 0x8acb,\n  0x336b, 0x8ac9, 0x3366, 0x8ac6, 0x3360, 0x8ac4, 0x335a, 0x8ac1,\n  0x3354, 0x8abf, 0x334f, 0x8abc, 0x3349, 0x8aba, 0x3343, 0x8ab7,\n  0x333d, 0x8ab5, 0x3338, 0x8ab2, 0x3332, 0x8ab0, 0x332c, 0x8aad,\n  0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,\n  0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,\n  0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,\n  0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,\n  0x32ca, 0x8a83, 0x32c4, 0x8a80, 0x32bf, 0x8a7e, 0x32b9, 0x8a7b,\n  0x32b3, 0x8a79, 0x32ad, 0x8a76, 0x32a8, 0x8a74, 0x32a2, 0x8a71,\n  0x329c, 0x8a6f, 0x3296, 0x8a6c, 0x3290, 0x8a6a, 0x328b, 0x8a67,\n  0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,\n  0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,\n  0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,\n  0x3240, 0x8a47, 0x323a, 0x8a45, 0x3234, 0x8a42, 0x322e, 0x8a40,\n  0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,\n  0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,\n  0x31fa, 0x8a2a, 0x31f4, 0x8a27, 0x31ef, 0x8a25, 0x31e9, 0x8a22,\n  0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,\n  0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,\n  0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,\n  0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,\n  0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,\n  0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,\n  0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,\n  0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,\n  0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,\n  0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,\n  0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,\n  0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,\n  0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,\n  0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,\n  0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,\n  0x3087, 0x898f, 0x3081, 0x898d, 0x307b, 0x898a, 0x3076, 0x8988,\n  0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,\n  0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,\n  0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,\n  0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,\n  0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,\n  0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,\n  0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,\n  0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,\n  0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,\n  0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,\n  0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,\n  0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,\n  0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,\n  0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,\n  0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,\n  0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,\n  0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,\n  0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,\n  0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,\n  0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,\n  0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,\n  0x2e86, 0x88c2, 0x2e80, 0x88bf, 0x2e7a, 0x88bd, 0x2e74, 0x88bb,\n  0x2e6e, 0x88b9, 0x2e68, 0x88b6, 0x2e63, 0x88b4, 0x2e5d, 0x88b2,\n  0x2e57, 0x88af, 0x2e51, 0x88ad, 0x2e4b, 0x88ab, 0x2e45, 0x88a9,\n  0x2e3f, 0x88a6, 0x2e3a, 0x88a4, 0x2e34, 0x88a2, 0x2e2e, 0x88a0,\n  0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,\n  0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,\n  0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,\n  0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,\n  0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,\n  0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,\n  0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,\n  0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,\n  0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,\n  0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,\n  0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,\n  0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,\n  0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,\n  0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,\n  0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,\n  0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,\n  0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,\n  0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,\n  0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,\n  0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,\n  0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,\n  0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,\n  0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,\n  0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,\n  0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,\n  0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,\n  0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,\n  0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,\n  0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,\n  0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,\n  0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,\n  0x2b4e, 0x878d, 0x2b48, 0x878b, 0x2b42, 0x8789, 0x2b3c, 0x8787,\n  0x2b36, 0x8784, 0x2b30, 0x8782, 0x2b2b, 0x8780, 0x2b25, 0x877e,\n  0x2b1f, 0x877c, 0x2b19, 0x877a, 0x2b13, 0x8778, 0x2b0d, 0x8776,\n  0x2b07, 0x8774, 0x2b01, 0x8771, 0x2afb, 0x876f, 0x2af5, 0x876d,\n  0x2aef, 0x876b, 0x2ae9, 0x8769, 0x2ae4, 0x8767, 0x2ade, 0x8765,\n  0x2ad8, 0x8763, 0x2ad2, 0x8761, 0x2acc, 0x875e, 0x2ac6, 0x875c,\n  0x2ac0, 0x875a, 0x2aba, 0x8758, 0x2ab4, 0x8756, 0x2aae, 0x8754,\n  0x2aa8, 0x8752, 0x2aa2, 0x8750, 0x2a9c, 0x874e, 0x2a97, 0x874c,\n  0x2a91, 0x874a, 0x2a8b, 0x8747, 0x2a85, 0x8745, 0x2a7f, 0x8743,\n  0x2a79, 0x8741, 0x2a73, 0x873f, 0x2a6d, 0x873d, 0x2a67, 0x873b,\n  0x2a61, 0x8739, 0x2a5b, 0x8737, 0x2a55, 0x8735, 0x2a4f, 0x8733,\n  0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,\n  0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,\n  0x2a1a, 0x8720, 0x2a14, 0x871e, 0x2a0e, 0x871c, 0x2a08, 0x871a,\n  0x2a02, 0x8718, 0x29fc, 0x8716, 0x29f6, 0x8714, 0x29f0, 0x8712,\n  0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,\n  0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,\n  0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,\n  0x29a3, 0x86f7, 0x299d, 0x86f5, 0x2997, 0x86f3, 0x2991, 0x86f1,\n  0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,\n  0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,\n  0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,\n  0x2944, 0x86d6, 0x293e, 0x86d4, 0x2938, 0x86d2, 0x2932, 0x86d0,\n  0x292c, 0x86ce, 0x2926, 0x86cc, 0x2920, 0x86ca, 0x291b, 0x86c8,\n  0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,\n  0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,\n  0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,\n  0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,\n  0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,\n  0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,\n  0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,\n  0x286e, 0x868e, 0x2868, 0x868c, 0x2862, 0x868a, 0x285c, 0x8688,\n  0x2856, 0x8686, 0x2850, 0x8684, 0x284a, 0x8682, 0x2844, 0x8680,\n  0x283e, 0x867e, 0x2838, 0x867c, 0x2832, 0x867a, 0x282c, 0x8678,\n  0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,\n  0x280e, 0x866e, 0x2808, 0x866d, 0x2802, 0x866b, 0x27fc, 0x8669,\n  0x27f6, 0x8667, 0x27f1, 0x8665, 0x27eb, 0x8663, 0x27e5, 0x8661,\n  0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,\n  0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,\n  0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,\n  0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,\n  0x277f, 0x8640, 0x2779, 0x863e, 0x2773, 0x863c, 0x276d, 0x863a,\n  0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,\n  0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,\n  0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,\n  0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,\n  0x2707, 0x8619, 0x2701, 0x8617, 0x26fb, 0x8615, 0x26f5, 0x8613,\n  0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,\n  0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,\n  0x26c0, 0x8602, 0x26ba, 0x8600, 0x26b4, 0x85fe, 0x26ae, 0x85fc,\n  0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,\n  0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,\n  0x2678, 0x85eb, 0x2672, 0x85ea, 0x266c, 0x85e8, 0x2666, 0x85e6,\n  0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,\n  0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,\n  0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,\n  0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,\n  0x2600, 0x85c6, 0x25fa, 0x85c4, 0x25f4, 0x85c2, 0x25ee, 0x85c0,\n  0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,\n  0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,\n  0x25b8, 0x85b0, 0x25b2, 0x85ae, 0x25ac, 0x85ac, 0x25a6, 0x85aa,\n  0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,\n  0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,\n  0x2570, 0x8599, 0x256a, 0x8598, 0x2564, 0x8596, 0x255e, 0x8594,\n  0x2558, 0x8592, 0x2552, 0x8590, 0x254c, 0x858e, 0x2546, 0x858d,\n  0x2540, 0x858b, 0x253a, 0x8589, 0x2534, 0x8587, 0x252e, 0x8585,\n  0x2528, 0x8583, 0x2522, 0x8582, 0x251c, 0x8580, 0x2516, 0x857e,\n  0x250f, 0x857c, 0x2509, 0x857a, 0x2503, 0x8579, 0x24fd, 0x8577,\n  0x24f7, 0x8575, 0x24f1, 0x8573, 0x24eb, 0x8571, 0x24e5, 0x856f,\n  0x24df, 0x856e, 0x24d9, 0x856c, 0x24d3, 0x856a, 0x24cd, 0x8568,\n  0x24c7, 0x8566, 0x24c1, 0x8565, 0x24bb, 0x8563, 0x24b5, 0x8561,\n  0x24af, 0x855f, 0x24a9, 0x855d, 0x24a3, 0x855c, 0x249d, 0x855a,\n  0x2497, 0x8558, 0x2491, 0x8556, 0x248b, 0x8554, 0x2485, 0x8553,\n  0x247f, 0x8551, 0x2479, 0x854f, 0x2473, 0x854d, 0x246d, 0x854b,\n  0x2467, 0x854a, 0x2461, 0x8548, 0x245b, 0x8546, 0x2455, 0x8544,\n  0x244f, 0x8543, 0x2449, 0x8541, 0x2443, 0x853f, 0x243d, 0x853d,\n  0x2437, 0x853b, 0x2431, 0x853a, 0x242b, 0x8538, 0x2425, 0x8536,\n  0x241f, 0x8534, 0x2419, 0x8533, 0x2413, 0x8531, 0x240d, 0x852f,\n  0x2407, 0x852d, 0x2401, 0x852b, 0x23fa, 0x852a, 0x23f4, 0x8528,\n  0x23ee, 0x8526, 0x23e8, 0x8524, 0x23e2, 0x8523, 0x23dc, 0x8521,\n  0x23d6, 0x851f, 0x23d0, 0x851d, 0x23ca, 0x851c, 0x23c4, 0x851a,\n  0x23be, 0x8518, 0x23b8, 0x8516, 0x23b2, 0x8515, 0x23ac, 0x8513,\n  0x23a6, 0x8511, 0x23a0, 0x850f, 0x239a, 0x850e, 0x2394, 0x850c,\n  0x238e, 0x850a, 0x2388, 0x8508, 0x2382, 0x8507, 0x237c, 0x8505,\n  0x2376, 0x8503, 0x2370, 0x8501, 0x236a, 0x8500, 0x2364, 0x84fe,\n  0x235e, 0x84fc, 0x2358, 0x84fa, 0x2352, 0x84f9, 0x234b, 0x84f7,\n  0x2345, 0x84f5, 0x233f, 0x84f4, 0x2339, 0x84f2, 0x2333, 0x84f0,\n  0x232d, 0x84ee, 0x2327, 0x84ed, 0x2321, 0x84eb, 0x231b, 0x84e9,\n  0x2315, 0x84e7, 0x230f, 0x84e6, 0x2309, 0x84e4, 0x2303, 0x84e2,\n  0x22fd, 0x84e1, 0x22f7, 0x84df, 0x22f1, 0x84dd, 0x22eb, 0x84db,\n  0x22e5, 0x84da, 0x22df, 0x84d8, 0x22d9, 0x84d6, 0x22d3, 0x84d5,\n  0x22cd, 0x84d3, 0x22c7, 0x84d1, 0x22c0, 0x84cf, 0x22ba, 0x84ce,\n  0x22b4, 0x84cc, 0x22ae, 0x84ca, 0x22a8, 0x84c9, 0x22a2, 0x84c7,\n  0x229c, 0x84c5, 0x2296, 0x84c4, 0x2290, 0x84c2, 0x228a, 0x84c0,\n  0x2284, 0x84be, 0x227e, 0x84bd, 0x2278, 0x84bb, 0x2272, 0x84b9,\n  0x226c, 0x84b8, 0x2266, 0x84b6, 0x2260, 0x84b4, 0x225a, 0x84b3,\n  0x2254, 0x84b1, 0x224e, 0x84af, 0x2247, 0x84ae, 0x2241, 0x84ac,\n  0x223b, 0x84aa, 0x2235, 0x84a9, 0x222f, 0x84a7, 0x2229, 0x84a5,\n  0x2223, 0x84a3, 0x221d, 0x84a2, 0x2217, 0x84a0, 0x2211, 0x849e,\n  0x220b, 0x849d, 0x2205, 0x849b, 0x21ff, 0x8499, 0x21f9, 0x8498,\n  0x21f3, 0x8496, 0x21ed, 0x8494, 0x21e7, 0x8493, 0x21e1, 0x8491,\n  0x21da, 0x848f, 0x21d4, 0x848e, 0x21ce, 0x848c, 0x21c8, 0x848a,\n  0x21c2, 0x8489, 0x21bc, 0x8487, 0x21b6, 0x8486, 0x21b0, 0x8484,\n  0x21aa, 0x8482, 0x21a4, 0x8481, 0x219e, 0x847f, 0x2198, 0x847d,\n  0x2192, 0x847c, 0x218c, 0x847a, 0x2186, 0x8478, 0x2180, 0x8477,\n  0x2179, 0x8475, 0x2173, 0x8473, 0x216d, 0x8472, 0x2167, 0x8470,\n  0x2161, 0x846e, 0x215b, 0x846d, 0x2155, 0x846b, 0x214f, 0x846a,\n  0x2149, 0x8468, 0x2143, 0x8466, 0x213d, 0x8465, 0x2137, 0x8463,\n  0x2131, 0x8461, 0x212b, 0x8460, 0x2125, 0x845e, 0x211e, 0x845d,\n  0x2118, 0x845b, 0x2112, 0x8459, 0x210c, 0x8458, 0x2106, 0x8456,\n  0x2100, 0x8454, 0x20fa, 0x8453, 0x20f4, 0x8451, 0x20ee, 0x8450,\n  0x20e8, 0x844e, 0x20e2, 0x844c, 0x20dc, 0x844b, 0x20d6, 0x8449,\n  0x20d0, 0x8447, 0x20c9, 0x8446, 0x20c3, 0x8444, 0x20bd, 0x8443,\n  0x20b7, 0x8441, 0x20b1, 0x843f, 0x20ab, 0x843e, 0x20a5, 0x843c,\n  0x209f, 0x843b, 0x2099, 0x8439, 0x2093, 0x8437, 0x208d, 0x8436,\n  0x2087, 0x8434, 0x2081, 0x8433, 0x207a, 0x8431, 0x2074, 0x842f,\n  0x206e, 0x842e, 0x2068, 0x842c, 0x2062, 0x842b, 0x205c, 0x8429,\n  0x2056, 0x8427, 0x2050, 0x8426, 0x204a, 0x8424, 0x2044, 0x8423,\n  0x203e, 0x8421, 0x2038, 0x8420, 0x2032, 0x841e, 0x202b, 0x841c,\n  0x2025, 0x841b, 0x201f, 0x8419, 0x2019, 0x8418, 0x2013, 0x8416,\n  0x200d, 0x8415, 0x2007, 0x8413, 0x2001, 0x8411, 0x1ffb, 0x8410,\n  0x1ff5, 0x840e, 0x1fef, 0x840d, 0x1fe9, 0x840b, 0x1fe2, 0x840a,\n  0x1fdc, 0x8408, 0x1fd6, 0x8406, 0x1fd0, 0x8405, 0x1fca, 0x8403,\n  0x1fc4, 0x8402, 0x1fbe, 0x8400, 0x1fb8, 0x83ff, 0x1fb2, 0x83fd,\n  0x1fac, 0x83fb, 0x1fa6, 0x83fa, 0x1f9f, 0x83f8, 0x1f99, 0x83f7,\n  0x1f93, 0x83f5, 0x1f8d, 0x83f4, 0x1f87, 0x83f2, 0x1f81, 0x83f1,\n  0x1f7b, 0x83ef, 0x1f75, 0x83ee, 0x1f6f, 0x83ec, 0x1f69, 0x83ea,\n  0x1f63, 0x83e9, 0x1f5d, 0x83e7, 0x1f56, 0x83e6, 0x1f50, 0x83e4,\n  0x1f4a, 0x83e3, 0x1f44, 0x83e1, 0x1f3e, 0x83e0, 0x1f38, 0x83de,\n  0x1f32, 0x83dd, 0x1f2c, 0x83db, 0x1f26, 0x83da, 0x1f20, 0x83d8,\n  0x1f19, 0x83d7, 0x1f13, 0x83d5, 0x1f0d, 0x83d3, 0x1f07, 0x83d2,\n  0x1f01, 0x83d0, 0x1efb, 0x83cf, 0x1ef5, 0x83cd, 0x1eef, 0x83cc,\n  0x1ee9, 0x83ca, 0x1ee3, 0x83c9, 0x1edd, 0x83c7, 0x1ed6, 0x83c6,\n  0x1ed0, 0x83c4, 0x1eca, 0x83c3, 0x1ec4, 0x83c1, 0x1ebe, 0x83c0,\n  0x1eb8, 0x83be, 0x1eb2, 0x83bd, 0x1eac, 0x83bb, 0x1ea6, 0x83ba,\n  0x1ea0, 0x83b8, 0x1e99, 0x83b7, 0x1e93, 0x83b5, 0x1e8d, 0x83b4,\n  0x1e87, 0x83b2, 0x1e81, 0x83b1, 0x1e7b, 0x83af, 0x1e75, 0x83ae,\n  0x1e6f, 0x83ac, 0x1e69, 0x83ab, 0x1e62, 0x83a9, 0x1e5c, 0x83a8,\n  0x1e56, 0x83a6, 0x1e50, 0x83a5, 0x1e4a, 0x83a3, 0x1e44, 0x83a2,\n  0x1e3e, 0x83a0, 0x1e38, 0x839f, 0x1e32, 0x839d, 0x1e2c, 0x839c,\n  0x1e25, 0x839a, 0x1e1f, 0x8399, 0x1e19, 0x8397, 0x1e13, 0x8396,\n  0x1e0d, 0x8394, 0x1e07, 0x8393, 0x1e01, 0x8392, 0x1dfb, 0x8390,\n  0x1df5, 0x838f, 0x1dee, 0x838d, 0x1de8, 0x838c, 0x1de2, 0x838a,\n  0x1ddc, 0x8389, 0x1dd6, 0x8387, 0x1dd0, 0x8386, 0x1dca, 0x8384,\n  0x1dc4, 0x8383, 0x1dbe, 0x8381, 0x1db7, 0x8380, 0x1db1, 0x837e,\n  0x1dab, 0x837d, 0x1da5, 0x837c, 0x1d9f, 0x837a, 0x1d99, 0x8379,\n  0x1d93, 0x8377, 0x1d8d, 0x8376, 0x1d87, 0x8374, 0x1d80, 0x8373,\n  0x1d7a, 0x8371, 0x1d74, 0x8370, 0x1d6e, 0x836f, 0x1d68, 0x836d,\n  0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,\n  0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,\n  0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,\n  0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,\n  0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,\n  0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,\n  0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,\n  0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,\n  0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,\n  0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,\n  0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,\n  0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,\n  0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,\n  0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,\n  0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,\n  0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,\n  0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,\n  0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,\n  0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,\n  0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,\n  0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,\n  0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,\n  0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,\n  0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,\n  0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,\n  0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,\n  0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,\n  0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,\n  0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,\n  0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,\n  0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,\n  0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,\n  0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,\n  0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,\n  0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,\n  0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,\n  0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,\n  0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,\n  0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,\n  0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,\n  0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,\n  0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,\n  0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,\n  0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,\n  0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,\n  0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,\n  0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,\n  0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,\n  0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,\n  0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,\n  0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,\n  0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,\n  0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,\n  0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,\n  0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,\n  0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,\n  0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,\n  0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,\n  0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,\n  0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,\n  0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,\n  0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,\n  0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,\n  0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,\n  0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,\n  0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,\n  0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,\n  0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,\n  0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,\n  0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,\n  0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,\n  0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,\n  0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,\n  0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,\n  0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,\n  0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,\n  0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,\n  0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,\n  0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,\n  0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,\n  0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,\n  0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,\n  0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,\n  0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,\n  0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,\n  0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,\n  0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,\n  0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,\n  0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,\n  0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,\n  0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,\n  0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,\n  0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,\n  0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,\n  0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,\n  0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,\n  0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,\n  0x140b, 0x8195, 0x1404, 0x8194, 0x13fe, 0x8193, 0x13f8, 0x8192,\n  0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,\n  0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,\n  0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,\n  0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,\n  0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,\n  0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,\n  0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,\n  0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,\n  0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,\n  0x1312, 0x816e, 0x130c, 0x816d, 0x1306, 0x816c, 0x12ff, 0x816c,\n  0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,\n  0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,\n  0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,\n  0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,\n  0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,\n  0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,\n  0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,\n  0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,\n  0x1232, 0x814d, 0x122c, 0x814c, 0x1226, 0x814c, 0x1220, 0x814b,\n  0x1219, 0x814a, 0x1213, 0x8149, 0x120d, 0x8148, 0x1207, 0x8147,\n  0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,\n  0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,\n  0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,\n  0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,\n  0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,\n  0x1184, 0x8135, 0x117e, 0x8134, 0x1178, 0x8133, 0x1171, 0x8132,\n  0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,\n  0x1152, 0x812e, 0x114c, 0x812d, 0x1146, 0x812c, 0x1140, 0x812b,\n  0x1139, 0x812b, 0x1133, 0x812a, 0x112d, 0x8129, 0x1127, 0x8128,\n  0x1121, 0x8127, 0x111a, 0x8126, 0x1114, 0x8126, 0x110e, 0x8125,\n  0x1108, 0x8124, 0x1101, 0x8123, 0x10fb, 0x8122, 0x10f5, 0x8121,\n  0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,\n  0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,\n  0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,\n  0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,\n  0x108b, 0x8113, 0x1085, 0x8113, 0x107f, 0x8112, 0x1078, 0x8111,\n  0x1072, 0x8110, 0x106c, 0x810f, 0x1066, 0x810f, 0x105f, 0x810e,\n  0x1059, 0x810d, 0x1053, 0x810c, 0x104d, 0x810b, 0x1047, 0x810b,\n  0x1040, 0x810a, 0x103a, 0x8109, 0x1034, 0x8108, 0x102e, 0x8107,\n  0x1027, 0x8107, 0x1021, 0x8106, 0x101b, 0x8105, 0x1015, 0x8104,\n  0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,\n  0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,\n  0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,\n  0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,\n  0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,\n  0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,\n  0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,\n  0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,\n  0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,\n  0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,\n  0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,\n  0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,\n  0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,\n  0xeca, 0x80dc, 0xec4, 0x80db, 0xebe, 0x80db, 0xeb7, 0x80da,\n  0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,\n  0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,\n  0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,\n  0xe66, 0x80d1, 0xe60, 0x80d0, 0xe5a, 0x80cf, 0xe53, 0x80ce,\n  0xe4d, 0x80ce, 0xe47, 0x80cd, 0xe41, 0x80cc, 0xe3a, 0x80cc,\n  0xe34, 0x80cb, 0xe2e, 0x80ca, 0xe28, 0x80ca, 0xe22, 0x80c9,\n  0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,\n  0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,\n  0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,\n  0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,\n  0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,\n  0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,\n  0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,\n  0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,\n  0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,\n  0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,\n  0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,\n  0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,\n  0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,\n  0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,\n  0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,\n  0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,\n  0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,\n  0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,\n  0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,\n  0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,\n  0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,\n  0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,\n  0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,\n  0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,\n  0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,\n  0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,\n  0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,\n  0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,\n  0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,\n  0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,\n  0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,\n  0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,\n  0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,\n  0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,\n  0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,\n  0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,\n  0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,\n  0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,\n  0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,\n  0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,\n  0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,\n  0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,\n  0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,\n  0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,\n  0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,\n  0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,\n  0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,\n  0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,\n  0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,\n  0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,\n  0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,\n  0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,\n  0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,\n  0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,\n  0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,\n  0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,\n  0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,\n  0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,\n  0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,\n  0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,\n  0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,\n  0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,\n  0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,\n  0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,\n  0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,\n  0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,\n  0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,\n  0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,\n  0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,\n  0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,\n  0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,\n  0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,\n  0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,\n  0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,\n  0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,\n  0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,\n  0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,\n  0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,\n  0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,\n  0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,\n  0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,\n  0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,\n  0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,\n  0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,\n  0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,\n  0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,\n  0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,\n  0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,\n  0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,\n  0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,\n  0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,\n  0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,\n  0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,\n  0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,\n  0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,\n  0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,\n  0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,\n  0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,\n  0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,\n  0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,\n  0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,\n  0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,\n  0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,\n  0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,\n  0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,\n  0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,\n  0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,\n  0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,\n  0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,\n  0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,\n  0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,\n  0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,\n  0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,\n  0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,\n  0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,\n  0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,\n  0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,\n  0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,\n  0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,\n  0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,\n  0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,\n  0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,\n  0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,\n  0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,\n  0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,\n  0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,\n  0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,\n  0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,\n  0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,\n  0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,\n  0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,\n  0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,\n  0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,\n  0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,\n  0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,\n  0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,\n  0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,\n  0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,\n  0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,\n  0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,\n  0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,\n  0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,\n  0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,\n  0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,\n};\n\n\n/**    \n* \\par    \n* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
    \n* \\par    \n* C command to generate the table    \n* 
    \n* for(i = 0; i< N; i++)    \n* {    \n*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n* } 
    \n* \\par    \n* where N is the number of factors to generate and c is pi/(2*N)    \n* \\par    \n* Then converted to q15 format by multiplying with 2^31 and saturated if required.    \n    \n*/\n\nstatic const q15_t ALIGN4 cos_factorsQ15_128[128] = {\n  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,\n  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,\n  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,\n  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,\n  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,\n  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,\n  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,\n  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,\n  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,\n  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,\n  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,\n  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,\n  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,\n  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,\n  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,\n  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9\n};\n\nstatic const q15_t ALIGN4 cos_factorsQ15_512[512] = {\n  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,\n  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,\n  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,\n  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,\n  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,\n  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,\n  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,\n  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,\n  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,\n  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,\n  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,\n  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,\n  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,\n  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,\n  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,\n  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,\n  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,\n  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,\n  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,\n  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,\n  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,\n  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,\n  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,\n  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,\n  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,\n  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,\n  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,\n  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,\n  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,\n  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,\n  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,\n  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,\n  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,\n  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,\n  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,\n  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,\n  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,\n  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,\n  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,\n  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,\n  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,\n  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,\n  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,\n  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,\n  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,\n  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,\n  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,\n  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,\n  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,\n  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,\n  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,\n  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,\n  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,\n  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,\n  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,\n  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,\n  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,\n  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,\n  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,\n  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,\n  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,\n  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,\n  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,\n  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,\n};\n\nstatic const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,\n  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,\n  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,\n  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,\n  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,\n  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,\n  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,\n  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,\n  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,\n  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,\n  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,\n  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,\n  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,\n  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,\n  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,\n  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,\n  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,\n  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,\n  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,\n  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,\n  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,\n  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,\n  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,\n  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,\n  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,\n  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,\n  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,\n  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,\n  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,\n  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,\n  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,\n  0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,\n  0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,\n  0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,\n  0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,\n  0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,\n  0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,\n  0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,\n  0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,\n  0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,\n  0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,\n  0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,\n  0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,\n  0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,\n  0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,\n  0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,\n  0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,\n  0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,\n  0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,\n  0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,\n  0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,\n  0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,\n  0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,\n  0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,\n  0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,\n  0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,\n  0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,\n  0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,\n  0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,\n  0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,\n  0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,\n  0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,\n  0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,\n  0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,\n  0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,\n  0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,\n  0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,\n  0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,\n  0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,\n  0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,\n  0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,\n  0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,\n  0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,\n  0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,\n  0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,\n  0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,\n  0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,\n  0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 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0x377a,\n  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,\n  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,\n  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,\n  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,\n  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,\n  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,\n  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,\n  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,\n  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,\n  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,\n  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,\n  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,\n  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,\n  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,\n  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,\n  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,\n  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,\n  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,\n  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,\n  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,\n  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,\n  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,\n  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,\n  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,\n  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,\n  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,\n  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,\n  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,\n  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,\n  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,\n  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,\n  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,\n  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,\n  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,\n  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,\n  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,\n  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,\n  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,\n  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,\n  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,\n  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,\n  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,\n  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,\n  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,\n  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,\n  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,\n  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,\n  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,\n  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,\n  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,\n  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,\n  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,\n  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,\n  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,\n  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,\n  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,\n  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,\n  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,\n  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,\n  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,\n  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,\n  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,\n  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,\n  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,\n  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,\n  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,\n  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,\n  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,\n  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,\n  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,\n  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,\n  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,\n  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,\n\n};\n\nstatic const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,\n  0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,\n  0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,\n  0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,\n  0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,\n  0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,\n  0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,\n  0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,\n  0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,\n  0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,\n  0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,\n  0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,\n  0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,\n  0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,\n  0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,\n  0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,\n  0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,\n  0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,\n  0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,\n  0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,\n  0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,\n  0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,\n  0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,\n  0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,\n  0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,\n  0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,\n  0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,\n  0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,\n  0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,\n  0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,\n  0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,\n  0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,\n  0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,\n  0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,\n  0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,\n  0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,\n  0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,\n  0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,\n  0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,\n  0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,\n  0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,\n  0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,\n  0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,\n  0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,\n  0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,\n  0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,\n  0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,\n  0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,\n  0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,\n  0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,\n  0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,\n  0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,\n  0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,\n  0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,\n  0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,\n  0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,\n  0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,\n  0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,\n  0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,\n  0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,\n  0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,\n  0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,\n  0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,\n  0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,\n  0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,\n  0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,\n  0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,\n  0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,\n  0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,\n  0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,\n  0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,\n  0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,\n  0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,\n  0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,\n  0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,\n  0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,\n  0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,\n  0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,\n  0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,\n  0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,\n  0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,\n  0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,\n  0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,\n  0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,\n  0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,\n  0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,\n  0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,\n  0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,\n  0x7eb9, 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0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,\n  0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,\n  0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,\n  0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,\n  0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,\n  0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,\n  0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,\n  0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,\n  0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,\n  0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,\n  0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,\n  0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,\n  0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,\n  0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,\n  0x7dcc, 0x7dcb, 0x7dca, 0x7dc9, 0x7dc7, 0x7dc6, 0x7dc5, 0x7dc4,\n  0x7dc3, 0x7dc2, 0x7dc0, 0x7dbf, 0x7dbe, 0x7dbd, 0x7dbc, 0x7dbb,\n  0x7db9, 0x7db8, 0x7db7, 0x7db6, 0x7db5, 0x7db3, 0x7db2, 0x7db1,\n  0x7db0, 0x7daf, 0x7dae, 0x7dac, 0x7dab, 0x7daa, 0x7da9, 0x7da8,\n  0x7da6, 0x7da5, 0x7da4, 0x7da3, 0x7da2, 0x7da0, 0x7d9f, 0x7d9e,\n  0x7d9d, 0x7d9c, 0x7d9a, 0x7d99, 0x7d98, 0x7d97, 0x7d95, 0x7d94,\n  0x7d93, 0x7d92, 0x7d91, 0x7d8f, 0x7d8e, 0x7d8d, 0x7d8c, 0x7d8a,\n  0x7d89, 0x7d88, 0x7d87, 0x7d86, 0x7d84, 0x7d83, 0x7d82, 0x7d81,\n  0x7d7f, 0x7d7e, 0x7d7d, 0x7d7c, 0x7d7a, 0x7d79, 0x7d78, 0x7d77,\n  0x7d75, 0x7d74, 0x7d73, 0x7d72, 0x7d70, 0x7d6f, 0x7d6e, 0x7d6d,\n  0x7d6b, 0x7d6a, 0x7d69, 0x7d68, 0x7d66, 0x7d65, 0x7d64, 0x7d63,\n  0x7d61, 0x7d60, 0x7d5f, 0x7d5e, 0x7d5c, 0x7d5b, 0x7d5a, 0x7d59,\n  0x7d57, 0x7d56, 0x7d55, 0x7d53, 0x7d52, 0x7d51, 0x7d50, 0x7d4e,\n  0x7d4d, 0x7d4c, 0x7d4a, 0x7d49, 0x7d48, 0x7d47, 0x7d45, 0x7d44,\n  0x7d43, 0x7d41, 0x7d40, 0x7d3f, 0x7d3e, 0x7d3c, 0x7d3b, 0x7d3a,\n  0x7d38, 0x7d37, 0x7d36, 0x7d34, 0x7d33, 0x7d32, 0x7d31, 0x7d2f,\n  0x7d2e, 0x7d2d, 0x7d2b, 0x7d2a, 0x7d29, 0x7d27, 0x7d26, 0x7d25,\n  0x7d23, 0x7d22, 0x7d21, 0x7d1f, 0x7d1e, 0x7d1d, 0x7d1b, 0x7d1a,\n  0x7d19, 0x7d17, 0x7d16, 0x7d15, 0x7d13, 0x7d12, 0x7d11, 0x7d0f,\n  0x7d0e, 0x7d0d, 0x7d0b, 0x7d0a, 0x7d09, 0x7d07, 0x7d06, 0x7d05,\n  0x7d03, 0x7d02, 0x7d01, 0x7cff, 0x7cfe, 0x7cfd, 0x7cfb, 0x7cfa,\n  0x7cf9, 0x7cf7, 0x7cf6, 0x7cf4, 0x7cf3, 0x7cf2, 0x7cf0, 0x7cef,\n  0x7cee, 0x7cec, 0x7ceb, 0x7ce9, 0x7ce8, 0x7ce7, 0x7ce5, 0x7ce4,\n  0x7ce3, 0x7ce1, 0x7ce0, 0x7cde, 0x7cdd, 0x7cdc, 0x7cda, 0x7cd9,\n  0x7cd8, 0x7cd6, 0x7cd5, 0x7cd3, 0x7cd2, 0x7cd1, 0x7ccf, 0x7cce,\n  0x7ccc, 0x7ccb, 0x7cca, 0x7cc8, 0x7cc7, 0x7cc5, 0x7cc4, 0x7cc3,\n  0x7cc1, 0x7cc0, 0x7cbe, 0x7cbd, 0x7cbc, 0x7cba, 0x7cb9, 0x7cb7,\n  0x7cb6, 0x7cb5, 0x7cb3, 0x7cb2, 0x7cb0, 0x7caf, 0x7cad, 0x7cac,\n  0x7cab, 0x7ca9, 0x7ca8, 0x7ca6, 0x7ca5, 0x7ca3, 0x7ca2, 0x7ca1,\n  0x7c9f, 0x7c9e, 0x7c9c, 0x7c9b, 0x7c99, 0x7c98, 0x7c97, 0x7c95,\n  0x7c94, 0x7c92, 0x7c91, 0x7c8f, 0x7c8e, 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0x7bd8, 0x7bd6, 0x7bd5, 0x7bd3,\n  0x7bd1, 0x7bd0, 0x7bce, 0x7bcd, 0x7bcb, 0x7bc9, 0x7bc8, 0x7bc6,\n  0x7bc5, 0x7bc3, 0x7bc1, 0x7bc0, 0x7bbe, 0x7bbd, 0x7bbb, 0x7bb9,\n  0x7bb8, 0x7bb6, 0x7bb5, 0x7bb3, 0x7bb1, 0x7bb0, 0x7bae, 0x7bac,\n  0x7bab, 0x7ba9, 0x7ba8, 0x7ba6, 0x7ba4, 0x7ba3, 0x7ba1, 0x7b9f,\n  0x7b9e, 0x7b9c, 0x7b9b, 0x7b99, 0x7b97, 0x7b96, 0x7b94, 0x7b92,\n  0x7b91, 0x7b8f, 0x7b8d, 0x7b8c, 0x7b8a, 0x7b89, 0x7b87, 0x7b85,\n  0x7b84, 0x7b82, 0x7b80, 0x7b7f, 0x7b7d, 0x7b7b, 0x7b7a, 0x7b78,\n  0x7b76, 0x7b75, 0x7b73, 0x7b71, 0x7b70, 0x7b6e, 0x7b6c, 0x7b6b,\n  0x7b69, 0x7b67, 0x7b66, 0x7b64, 0x7b62, 0x7b61, 0x7b5f, 0x7b5d,\n  0x7b5c, 0x7b5a, 0x7b58, 0x7b57, 0x7b55, 0x7b53, 0x7b52, 0x7b50,\n  0x7b4e, 0x7b4d, 0x7b4b, 0x7b49, 0x7b47, 0x7b46, 0x7b44, 0x7b42,\n  0x7b41, 0x7b3f, 0x7b3d, 0x7b3c, 0x7b3a, 0x7b38, 0x7b37, 0x7b35,\n  0x7b33, 0x7b31, 0x7b30, 0x7b2e, 0x7b2c, 0x7b2b, 0x7b29, 0x7b27,\n  0x7b25, 0x7b24, 0x7b22, 0x7b20, 0x7b1f, 0x7b1d, 0x7b1b, 0x7b19,\n  0x7b18, 0x7b16, 0x7b14, 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0x3a16,\n  0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,\n  0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,\n  0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,\n  0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,\n  0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,\n  0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,\n  0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,\n  0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,\n  0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,\n  0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,\n  0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,\n  0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,\n  0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,\n  0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,\n  0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,\n  0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,\n  0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,\n  0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,\n  0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,\n  0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,\n  0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,\n  0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,\n  0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,\n  0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,\n  0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,\n  0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,\n  0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,\n  0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,\n  0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,\n  0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,\n  0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,\n  0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,\n  0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,\n  0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,\n  0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,\n  0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,\n  0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,\n  0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,\n  0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,\n  0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,\n  0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,\n  0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,\n  0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,\n  0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,\n  0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,\n  0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,\n  0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,\n  0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,\n  0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,\n  0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,\n  0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,\n  0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,\n  0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,\n  0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,\n  0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,\n  0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,\n  0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,\n  0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,\n  0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,\n  0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,\n  0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,\n  0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,\n  0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,\n  0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,\n  0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,\n  0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,\n  0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,\n  0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,\n  0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,\n  0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,\n  0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,\n  0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,\n  0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,\n  0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,\n  0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,\n  0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,\n  0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,\n  0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,\n  0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,\n  0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,\n  0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,\n  0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,\n  0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,\n  0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,\n  0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,\n  0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,\n  0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,\n  0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,\n  0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,\n  0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,\n  0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,\n  0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,\n  0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,\n  0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,\n  0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,\n  0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,\n  0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,\n  0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,\n  0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,\n  0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,\n  0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,\n  0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,\n  0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,\n  0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,\n  0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,\n  0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,\n  0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,\n  0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,\n  0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,\n  0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,\n  0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,\n  0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,\n  0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,\n  0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,\n  0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,\n  0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,\n  0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,\n  0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,\n  0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,\n  0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,\n  0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,\n  0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,\n  0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,\n  0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,\n  0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,\n  0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,\n  0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,\n  0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,\n  0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,\n  0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,\n  0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,\n  0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,\n  0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,\n  0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,\n  0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,\n  0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,\n  0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,\n  0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,\n  0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,\n  0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,\n  0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,\n  0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,\n  0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,\n  0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,\n  0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,\n  0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,\n  0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,\n  0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,\n  0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,\n  0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,\n  0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,\n  0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,\n  0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,\n  0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,\n  0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,\n  0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,\n  0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,\n  0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,\n  0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,\n  0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,\n  0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,\n  0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,\n  0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,\n  0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,\n  0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,\n  0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,\n  0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,\n  0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,\n  0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,\n  0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,\n  0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,\n  0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,\n  0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,\n  0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,\n  0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,\n  0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,\n  0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,\n  0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,\n  0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,\n  0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,\n  0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,\n  0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,\n  0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,\n  0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,\n  0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,\n  0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,\n  0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,\n  0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,\n  0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,\n  0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,\n  0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,\n  0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,\n  0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,\n  0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,\n  0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,\n  0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,\n  0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,\n  0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,\n  0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,\n  0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,\n  0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,\n  0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,\n  0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,\n  0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,\n  0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,\n  0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,\n  0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,\n  0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,\n  0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,\n  0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,\n  0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,\n  0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,\n  0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,\n  0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,\n  0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,\n  0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,\n  0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,\n  0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,\n  0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,\n  0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,\n  0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,\n  0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,\n  0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,\n  0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,\n  0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,\n  0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,\n  0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,\n  0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,\n  0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,\n  0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,\n  0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,\n  0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,\n  0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,\n  0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,\n  0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,\n  0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,\n  0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,\n  0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,\n  0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,\n  0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,\n  0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,\n  0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,\n  0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,\n  0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,\n  0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,\n  0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,\n  0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,\n  0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,\n  0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,\n  0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,\n  0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,\n  0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,\n  0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,\n  0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,\n  0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,\n  0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,\n  0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,\n  0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,\n  0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,\n  0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,\n  0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,\n  0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,\n  0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,\n  0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,\n  0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,\n  0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,\n  0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,\n  0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,\n  0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,\n  0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,\n  0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,\n  0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,\n  0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,\n  0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,\n  0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,\n  0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,\n  0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,\n  0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,\n  0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,\n  0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,\n  0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,\n  0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,\n  0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,\n  0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,\n  0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,\n  0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,\n  0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,\n  0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,\n  0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,\n  0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,\n  0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,\n  0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,\n  0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,\n  0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,\n  0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,\n  0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,\n  0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,\n  0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,\n  0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,\n  0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,\n  0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,\n  0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,\n  0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,\n  0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,\n  0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,\n  0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,\n  0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,\n};\n\n/**    \n * @brief  Initialization function for the Q15 DCT4/IDCT4.   \n * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.   \n * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.   \n * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.   \n * @param[in]     N          length of the DCT4.   \n * @param[in]     Nby2       half of the length of the DCT4.   \n * @param[in]     normalize  normalizing factor.   \n * @return  \t  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   \n * \\par Normalizing factor:    \n * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    \n * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:    \n * \\image html dct4NormalizingQ15Table.gif    \n */\n\narm_status arm_dct4_init_q15(\n  arm_dct4_instance_q15 * S,\n  arm_rfft_instance_q15 * S_RFFT,\n  arm_cfft_radix4_instance_q15 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q15_t normalize)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /* Initializing the pointer array with the weight table base addresses of different lengths */\n  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,\n    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192\n  };\n\n  /* Initializing the pointer array with the cos factor table base addresses of different lengths */\n  q15_t *pCosFactor[4] =\n    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,\n    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192\n  };\n\n  /* Initialize the DCT4 length */\n  S->N = N;\n\n  /* Initialize the half of DCT4 length */\n  S->Nby2 = Nby2;\n\n  /* Initialize the DCT4 Normalizing factor */\n  S->normalize = normalize;\n\n  /* Initialize Real FFT Instance */\n  S->pRfft = S_RFFT;\n\n  /* Initialize Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  switch (N)\n  {\n    /* Initialize the table modifier values */\n  case 8192u:\n    S->pTwiddle = twiddlePtr[3];\n    S->pCosFactor = pCosFactor[3];\n    break;\n  case 2048u:\n    S->pTwiddle = twiddlePtr[2];\n    S->pCosFactor = pCosFactor[2];\n    break;\n  case 512u:\n    S->pTwiddle = twiddlePtr[1];\n    S->pCosFactor = pCosFactor[1];\n    break;\n  case 128u:\n    S->pTwiddle = twiddlePtr[0];\n    S->pCosFactor = pCosFactor[0];\n    break;\n  default:\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n\n  /* Initialize the RFFT/RIFFT */\n  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);\n\n  /* return the status of DCT4 Init function */\n  return (status);\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_init_q31.c    \n*    \n* Description:\tInitialization function of DCT-4 & IDCT4 Q31    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/*    \n* @brief  Weights Table    \n*/\n\n/**    \n* \\par    \n* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    \n* \\par    \n* C command to generate the table    \n* 
    \n* for(i = 0; i< N; i++)    \n* {    \n*   weights[2*i]= cos(i*c);    \n*   weights[(2*i)+1]= -sin(i * c);    \n* } 
    \n* \\par    \n* where N is the Number of weights to be calculated and c is pi/(2*N)    \n* \\par    \n* Convert the output to q31 format by multiplying with 2^31 and saturated if required.    \n* \\par    \n* In the tables below the real and imaginary values are placed alternatively, hence the    \n* array length is 2*N.    \n*/\n\nstatic const q31_t WeightsQ31_128[256] = {\n  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,\n  0xfb49e6a3,\n  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,\n  0x7f872bf3, 0xf50497fb,\n  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,\n  0x7ed5e5c6, 0xeec60f31,\n  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,\n  0x7dd6668f, 0xe8922622,\n  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,\n  0x7c894bde, 0xe26cb01b,\n  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,\n  0x7aef6323, 0xdc597781,\n  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,\n  0x7909a92d, 0xd65c3b7b,\n  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,\n  0x76d94989, 0xd078ad9e,\n  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,\n  0x745f9dd1, 0xcab26fa9,\n  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,\n  0x719e2cd2, 0xc50d1149,\n  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,\n  0x6e96a99d, 0xbf8c0de3,\n  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,\n  0x6b4af279, 0xba32ca71,\n  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,\n  0x67bd0fbd, 0xb5049368,\n  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,\n  0x63ef3290, 0xb0049ab3,\n  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,\n  0x5fe3b38d, 0xab35f5b5,\n  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,\n  0x5b9d1154, 0xa69b9b68,\n  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,\n  0x571deefa, 0xa2386284,\n  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,\n  0x5269126e, 0x9e0effc1,\n  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,\n  0x4d8162c4, 0x9a22042d,\n  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,\n  0x4869e665, 0x9673db94,\n  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,\n  0x4325c135, 0x9306cb04,\n  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,\n  0x3db832a6, 0x8fdcef66,\n  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,\n  0x382493b0, 0x8cf83c30,\n  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,\n  0x326e54c7, 0x8a5a7a31,\n  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,\n  0x2c98fbba, 0x88054677,\n  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,\n  0x26a82186, 0x85fa1153,\n  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,\n  0x209f701c, 0x843a1d70,\n  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,\n  0x1a82a026, 0x82c67f14,\n  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,\n  0x145576b1, 0x81a01b6d,\n  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,\n  0xe1bc2e4, 0x80c7a80a,\n  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,\n  0x7d95b9e, 0x803daa6a,\n  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,\n  0x1921d20, 0x800277a6,\n};\n\nstatic const q31_t WeightsQ31_512[1024] = {\n  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,\n  0xfed2694f,\n  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,\n  0x7ff871a2, 0xfd40565c,\n  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,\n  0x7fed5791, 0xfbae5e89,\n  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,\n  0x7fdd4eec, 0xfa1c9157,\n  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,\n  0x7fc85854, 0xf88afe42,\n  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,\n  0x7fae7495, 0xf6f9b4c6,\n  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,\n  0x7f8fa4b0, 0xf568c45b,\n  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,\n  0x7f6be9d4, 0xf3d83c77,\n  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,\n  0x7f434563, 0xf2482c8a,\n  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,\n  0x7f15b8ee, 0xf0b8a401,\n  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,\n  0x7ee34636, 0xef29b243,\n  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,\n  0x7eabef2c, 0xed9b66b2,\n  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,\n  0x7e6fb5f4, 0xec0dd0a8,\n  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,\n  0x7e2e9cdf, 0xea80ff7a,\n  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,\n  0x7de8a670, 0xe8f50273,\n  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,\n  0x7d9dd55a, 0xe769e8d8,\n  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,\n  0x7d4e2c7f, 0xe5dfc1e5,\n  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,\n  0x7cf9aef0, 0xe4569ccb,\n  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,\n  0x7ca05ff1, 0xe2ce88b3,\n  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,\n  0x7c4242f2, 0xe14794ba,\n  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,\n  0x7bdf5b94, 0xdfc1cff3,\n  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,\n  0x7b77ada8, 0xde3d4964,\n  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,\n  0x7b0b3d2c, 0xdcba1008,\n  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,\n  0x7a9a0e50, 0xdb3832cd,\n  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,\n  0x7a24256f, 0xd9b7c094,\n  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,\n  0x79a98715, 0xd838c82d,\n  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,\n  0x792a37fe, 0xd6bb585e,\n  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,\n  0x78a63d11, 0xd53f7fda,\n  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,\n  0x781d9b65, 0xd3c54d47,\n  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,\n  0x7790583e, 0xd24ccf39,\n  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,\n  0x76fe790e, 0xd0d61434,\n  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,\n  0x76680376, 0xcf612aaa,\n  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,\n  0x75ccfd42, 0xcdee20fc,\n  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,\n  0x752d6c6c, 0xcc7d0578,\n  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,\n  0x7489571c, 0xcb0de658,\n  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,\n  0x73e0c3a3, 0xc9a0d1c5,\n  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,\n  0x7333b883, 0xc835d5d0,\n  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,\n  0x72823c67, 0xc6cd0079,\n  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,\n  0x71cc5626, 0xc5665fa9,\n  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,\n  0x71120cc5, 0xc4020133,\n  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,\n  0x70536771, 0xc29ff2d4,\n  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,\n  0x6f906d84, 0xc1404233,\n  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,\n  0x6ec92683, 0xbfe2fcdf,\n  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,\n  0x6dfd9a1c, 0xbe88304f,\n  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,\n  0x6d2dd027, 0xbd2fe9e2,\n  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,\n  0x6c59d0a9, 0xbbda36dd,\n  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,\n  0x6b81a3cd, 0xba87246d,\n  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,\n  0x6aa551e9, 0xb936bfa4,\n  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,\n  0x69c4e37a, 0xb7e9157a,\n  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,\n  0x68e06129, 0xb69e32cd,\n  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,\n  0x67f7d3c5, 0xb556245e,\n  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,\n  0x670b4444, 0xb410f6d3,\n  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,\n  0x661abbc5, 0xb2ceb6b5,\n  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,\n  0x6526438f, 0xb18f7071,\n  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,\n  0x642de50d, 0xb0533055,\n  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,\n  0x6331a9d4, 0xaf1a0293,\n  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,\n  0x62319b9d, 0xade3f33e,\n  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,\n  0x612dc447, 0xacb10e4b,\n  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,\n  0x60262dd6, 0xab815f8d,\n  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,\n  0x5f1ae274, 0xaa54f2ba,\n  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,\n  0x5e0bec6e, 0xa92bd367,\n  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,\n  0x5cf95638, 0xa8060d08,\n  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,\n  0x5be32a67, 0xa6e3aaf2,\n  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,\n  0x5ac973b5, 0xa5c4b855,\n  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,\n  0x59ac3cfd, 0xa4a94043,\n  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,\n  0x588b9140, 0xa3914da8,\n  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,\n  0x57677b9d, 0xa27ceb4f,\n  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,\n  0x56400758, 0xa16c23e1,\n  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,\n  0x55153fd4, 0xa05f01e1,\n  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,\n  0x53e73097, 0x9f558fb0,\n  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,\n  0x52b5e546, 0x9e4fd78a,\n  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,\n  0x518169a5, 0x9d4de385,\n  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,\n  0x5049c999, 0x9c4fbd93,\n  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,\n  0x4f0f1126, 0x9b556f81,\n  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,\n  0x4dd14c6e, 0x9a5f02f5,\n  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,\n  0x4c9087b1, 0x996c816f,\n  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,\n  0x4b4ccf4d, 0x987df449,\n  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,\n  0x4a062fbd, 0x979364b5,\n  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,\n  0x48bcb599, 0x96acdbbe,\n  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,\n  0x47706d93, 0x95ca6247,\n  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,\n  0x4621647d, 0x94ec010b,\n  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,\n  0x44cfa740, 0x9411c09e,\n  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,\n  0x437b42e1, 0x933ba968,\n  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,\n  0x42244481, 0x9269c3ac,\n  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,\n  0x40cab958, 0x919c1781,\n  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,\n  0x3f6eaeb8, 0x90d2acd4,\n  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,\n  0x3e10320d, 0x900d8b69,\n  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,\n  0x3caf50da, 0x8f4cbadb,\n  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,\n  0x3b4c18ba, 0x8e904298,\n  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,\n  0x39e6975e, 0x8dd829e4,\n  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,\n  0x387eda8e, 0x8d2477d8,\n  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,\n  0x3714f02a, 0x8c753362,\n  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,\n  0x35a8e625, 0x8bca6343,\n  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,\n  0x343aca87, 0x8b240e11,\n  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,\n  0x32caab6f, 0x8a823a36,\n  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,\n  0x3158970e, 0x89e4edef,\n  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,\n  0x2fe49ba7, 0x894c2f4c,\n  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,\n  0x2e6ec792, 0x88b80432,\n  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,\n  0x2cf72939, 0x88287256,\n  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,\n  0x2b7dcf17, 0x879d7f41,\n  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,\n  0x2a02c7b8, 0x8717304e,\n  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,\n  0x288621b9, 0x86958aac,\n  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,\n  0x2707ebc7, 0x86189359,\n  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,\n  0x2588349d, 0x85a04f28,\n  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,\n  0x24070b08, 0x852cc2bb,\n  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,\n  0x22847de0, 0x84bdf286,\n  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,\n  0x21009c0c, 0x8453e2cf,\n  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,\n  0x1f7b7481, 0x83ee97ad,\n  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,\n  0x1df5163f, 0x838e1507,\n  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,\n  0x1c6d9053, 0x83325e97,\n  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,\n  0x1ae4f1d6, 0x82db77e5,\n  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,\n  0x195b49ea, 0x8289644b,\n  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,\n  0x17d0a7bc, 0x823c26f3,\n  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,\n  0x16451a83, 0x81f3c2d7,\n  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,\n  0x14b8b17f, 0x81b03ac2,\n  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,\n  0x132b7bf9, 0x8171914e,\n  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,\n  0x119d8941, 0x8137c8e6,\n  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,\n  0x100ee8ad, 0x8102e3c4,\n  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,\n  0xe7fa99e, 0x80d2e3f2,\n  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,\n  0xcefdb76, 0x80a7cb49,\n  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,\n  0xb5f8d9f, 0x80819b74,\n  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,\n  0x9cecf89, 0x806055eb,\n  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,\n  0x83db0a7, 0x8043fbf6,\n  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,\n  0x6ac406f, 0x802c8ead,\n  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,\n  0x51a8e5c, 0x801a0ef8,\n  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,\n  0x388a9ea, 0x800c7d8c,\n  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,\n  0x1f6a297, 0x8003daf1,\n  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,\n  0x6487e3, 0x8000277a,\n};\n\nstatic const q31_t WeightsQ31_2048[4096] = {\n  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,\n  0xffb49a12,\n  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,\n  0x7fff8719, 0xff501258,\n  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,\n  0x7ffed572, 0xfeeb8b0a,\n  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,\n  0x7ffdd4d7, 0xfe870467,\n  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,\n  0x7ffc8549, 0xfe227eac,\n  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,\n  0x7ffae6c7, 0xfdbdfa18,\n  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,\n  0x7ff8f954, 0xfd5976e9,\n  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,\n  0x7ff6bcf0, 0xfcf4f55c,\n  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,\n  0x7ff4319d, 0xfc9075af,\n  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,\n  0x7ff1575d, 0xfc2bf821,\n  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,\n  0x7fee2e30, 0xfbc77cf0,\n  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,\n  0x7feab61a, 0xfb630459,\n  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,\n  0x7fe6ef1c, 0xfafe8e9b,\n  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,\n  0x7fe2d938, 0xfa9a1bf3,\n  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,\n  0x7fde7471, 0xfa35ac9f,\n  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,\n  0x7fd9c0ca, 0xf9d140de,\n  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,\n  0x7fd4be46, 0xf96cd8ed,\n  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,\n  0x7fcf6ce8, 0xf908750a,\n  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,\n  0x7fc9ccb2, 0xf8a41574,\n  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,\n  0x7fc3dda9, 0xf83fba68,\n  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,\n  0x7fbd9fd0, 0xf7db6423,\n  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,\n  0x7fb7132b, 0xf77712e5,\n  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,\n  0x7fb037bf, 0xf712c6ea,\n  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,\n  0x7fa90d8e, 0xf6ae8071,\n  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,\n  0x7fa1949e, 0xf64a3fb8,\n  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,\n  0x7f99ccf4, 0xf5e604fc,\n  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,\n  0x7f91b694, 0xf581d07b,\n  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,\n  0x7f895182, 0xf51da273,\n  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,\n  0x7f809dc5, 0xf4b97b21,\n  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,\n  0x7f779b62, 0xf4555ac5,\n  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,\n  0x7f6e4a5e, 0xf3f1419a,\n  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,\n  0x7f64aabf, 0xf38d2fe0,\n  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,\n  0x7f5abc8a, 0xf32925d3,\n  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,\n  0x7f507fc7, 0xf2c523b2,\n  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,\n  0x7f45f47b, 0xf26129ba,\n  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,\n  0x7f3b1aad, 0xf1fd3829,\n  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,\n  0x7f2ff263, 0xf1994f3d,\n  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,\n  0x7f247ba5, 0xf1356f32,\n  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,\n  0x7f18b679, 0xf0d19848,\n  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,\n  0x7f0ca2e7, 0xf06dcaba,\n  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,\n  0x7f0040f6, 0xf00a06c8,\n  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,\n  0x7ef390ae, 0xefa64cae,\n  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,\n  0x7ee69217, 0xef429caa,\n  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,\n  0x7ed94538, 0xeedef6f9,\n  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,\n  0x7ecbaa1a, 0xee7b5bd9,\n  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,\n  0x7ebdc0c6, 0xee17cb88,\n  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,\n  0x7eaf8943, 0xedb44642,\n  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,\n  0x7ea1039b, 0xed50cc46,\n  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,\n  0x7e922fd6, 0xeced5dd0,\n  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,\n  0x7e830dff, 0xec89fb1e,\n  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,\n  0x7e739e1d, 0xec26a46d,\n  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,\n  0x7e63e03b, 0xebc359fb,\n  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,\n  0x7e53d462, 0xeb601c04,\n  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,\n  0x7e437a9c, 0xeafceac6,\n  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,\n  0x7e32d2f4, 0xea99c67e,\n  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,\n  0x7e21dd73, 0xea36af69,\n  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,\n  0x7e109a24, 0xe9d3a5c5,\n  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,\n  0x7dff0911, 0xe970a9ce,\n  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,\n  0x7ded2a47, 0xe90dbbc2,\n  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,\n  0x7ddafdce, 0xe8aadbde,\n  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,\n  0x7dc883b4, 0xe8480a5d,\n  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,\n  0x7db5bc02, 0xe7e5477f,\n  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,\n  0x7da2a6c6, 0xe782937e,\n  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,\n  0x7d8f4409, 0xe71fee99,\n  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,\n  0x7d7b93da, 0xe6bd590d,\n  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,\n  0x7d679642, 0xe65ad315,\n  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,\n  0x7d534b50, 0xe5f85cef,\n  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,\n  0x7d3eb30f, 0xe595f6d7,\n  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,\n  0x7d29cd8c, 0xe533a10a,\n  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,\n  0x7d149ad5, 0xe4d15bc6,\n  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,\n  0x7cff1af5, 0xe46f2745,\n  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,\n  0x7ce94dfb, 0xe40d03c6,\n  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,\n  0x7cd333f3, 0xe3aaf184,\n  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,\n  0x7cbcccec, 0xe348f0bd,\n  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,\n  0x7ca618f3, 0xe2e701ac,\n  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,\n  0x7c8f1817, 0xe285248d,\n  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,\n  0x7c77ca65, 0xe223599e,\n  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,\n  0x7c602fec, 0xe1c1a11b,\n  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,\n  0x7c4848ba, 0xe15ffb3f,\n  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,\n  0x7c3014de, 0xe0fe6848,\n  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,\n  0x7c179467, 0xe09ce871,\n  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,\n  0x7bfec765, 0xe03b7bf6,\n  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,\n  0x7be5ade6, 0xdfda2314,\n  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,\n  0x7bcc47fa, 0xdf78de07,\n  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,\n  0x7bb295b0, 0xdf17ad0a,\n  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,\n  0x7b989719, 0xdeb69059,\n  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,\n  0x7b7e4c45, 0xde558831,\n  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,\n  0x7b63b543, 0xddf494ce,\n  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,\n  0x7b48d225, 0xdd93b66a,\n  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,\n  0x7b2da2fa, 0xdd32ed43,\n  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,\n  0x7b1227d3, 0xdcd23993,\n  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,\n  0x7af660c2, 0xdc719b96,\n  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,\n  0x7ada4dd8, 0xdc111388,\n  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,\n  0x7abdef25, 0xdbb0a1a4,\n  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,\n  0x7aa144bc, 0xdb504626,\n  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,\n  0x7a844eae, 0xdaf00149,\n  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,\n  0x7a670d0d, 0xda8fd349,\n  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,\n  0x7a497feb, 0xda2fbc61,\n  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,\n  0x7a2ba75a, 0xd9cfbccd,\n  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,\n  0x7a0d836d, 0xd96fd4c7,\n  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,\n  0x79ef1436, 0xd910048a,\n  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,\n  0x79d059c8, 0xd8b04c52,\n  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,\n  0x79b15435, 0xd850ac5a,\n  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,\n  0x79920392, 0xd7f124dd,\n  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,\n  0x797267f2, 0xd791b616,\n  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,\n  0x79528167, 0xd732603f,\n  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,\n  0x79325006, 0xd6d32393,\n  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,\n  0x7911d3e2, 0xd674004e,\n  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,\n  0x78f10d0f, 0xd614f6a9,\n  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,\n  0x78cffba3, 0xd5b606e0,\n  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,\n  0x78ae9fb0, 0xd557312d,\n  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,\n  0x788cf94c, 0xd4f875ca,\n  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,\n  0x786b088c, 0xd499d4f2,\n  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,\n  0x7848cd83, 0xd43b4ee0,\n  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,\n  0x78264849, 0xd3dce3cd,\n  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,\n  0x780378f1, 0xd37e93f4,\n  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,\n  0x77e05f91, 0xd3205f8f,\n  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,\n  0x77bcfc3f, 0xd2c246d8,\n  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,\n  0x77994f11, 0xd2644a0a,\n  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,\n  0x7775581d, 0xd206695d,\n  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,\n  0x77511778, 0xd1a8a50d,\n  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,\n  0x772c8d3a, 0xd14afd52,\n  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,\n  0x7707b979, 0xd0ed7267,\n  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,\n  0x76e29c4b, 0xd0900486,\n  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,\n  0x76bd35c7, 0xd032b3e7,\n  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,\n  0x76978605, 0xcfd580c6,\n  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,\n  0x76718d1c, 0xcf786b5a,\n  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,\n  0x764b4b23, 0xcf1b73de,\n  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,\n  0x7624c031, 0xcebe9a8a,\n  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,\n  0x75fdec60, 0xce61df99,\n  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,\n  0x75d6cfc5, 0xce054343,\n  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,\n  0x75af6a7b, 0xcda8c5c1,\n  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,\n  0x7587bc98, 0xcd4c674d,\n  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,\n  0x755fc635, 0xccf0281f,\n  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,\n  0x7537876c, 0xcc940871,\n  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,\n  0x750f0054, 0xcc38087b,\n  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,\n  0x74e63108, 0xcbdc2876,\n  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,\n  0x74bd199f, 0xcb80689a,\n  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,\n  0x7493ba34, 0xcb24c921,\n  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,\n  0x746a12df, 0xcac94a42,\n  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,\n  0x744023bc, 0xca6dec37,\n  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,\n  0x7415ece2, 0xca12af37,\n  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,\n  0x73eb6e6e, 0xc9b7937a,\n  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,\n  0x73c0a878, 0xc95c993a,\n  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,\n  0x73959b1b, 0xc901c0ae,\n  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,\n  0x736a4671, 0xc8a70a0e,\n  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,\n  0x733eaa96, 0xc84c7593,\n  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,\n  0x7312c7a5, 0xc7f20373,\n  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,\n  0x72e69db7, 0xc797b3e7,\n  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,\n  0x72ba2cea, 0xc73d8727,\n  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,\n  0x728d7557, 0xc6e37d69,\n  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,\n  0x7260771b, 0xc68996e7,\n  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,\n  0x72333251, 0xc62fd3d6,\n  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,\n  0x7205a716, 0xc5d6346f,\n  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,\n  0x71d7d585, 0xc57cb8e9,\n  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,\n  0x71a9bdba, 0xc523617a,\n  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,\n  0x717b5fd3, 0xc4ca2e5b,\n  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,\n  0x714cbbeb, 0xc4711fc2,\n  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,\n  0x711dd220, 0xc41835e6,\n  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,\n  0x70eea28e, 0xc3bf70fd,\n  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,\n  0x70bf2d53, 0xc366d140,\n  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,\n  0x708f728b, 0xc30e56e4,\n  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,\n  0x705f7255, 0xc2b6021f,\n  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,\n  0x702f2ccd, 0xc25dd329,\n  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,\n  0x6ffea212, 0xc205ca38,\n  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,\n  0x6fcdd241, 0xc1ade781,\n  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,\n  0x6f9cbd79, 0xc1562b3d,\n  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,\n  0x6f6b63d8, 0xc0fe959f,\n  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,\n  0x6f39c57d, 0xc0a726df,\n  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,\n  0x6f07e285, 0xc04fdf32,\n  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,\n  0x6ed5bb10, 0xbff8bece,\n  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,\n  0x6ea34f3d, 0xbfa1c5ea,\n  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,\n  0x6e709f2a, 0xbf4af4ba,\n  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,\n  0x6e3daaf8, 0xbef44b74,\n  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,\n  0x6e0a72c5, 0xbe9dca4e,\n  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,\n  0x6dd6f6b1, 0xbe47717c,\n  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,\n  0x6da336dc, 0xbdf14135,\n  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,\n  0x6d6f3365, 0xbd9b39ad,\n  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,\n  0x6d3aec6e, 0xbd455b1a,\n  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,\n  0x6d066215, 0xbcefa5b0,\n  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,\n  0x6cd1947c, 0xbc9a19a5,\n  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,\n  0x6c9c83c3, 0xbc44b72c,\n  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,\n  0x6c67300b, 0xbbef7e7c,\n  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,\n  0x6c319975, 0xbb9a6fc7,\n  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,\n  0x6bfbc021, 0xbb458b43,\n  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,\n  0x6bc5a431, 0xbaf0d125,\n  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,\n  0x6b8f45c7, 0xba9c41a0,\n  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,\n  0x6b58a503, 0xba47dce8,\n  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,\n  0x6b21c208, 0xb9f3a332,\n  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,\n  0x6aea9cf8, 0xb99f94b2,\n  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,\n  0x6ab335f4, 0xb94bb19b,\n  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,\n  0x6a7b8d1e, 0xb8f7fa21,\n  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,\n  0x6a43a29a, 0xb8a46e78,\n  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,\n  0x6a0b7689, 0xb8510ed4,\n  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,\n  0x69d3090e, 0xb7fddb67,\n  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,\n  0x699a5a4c, 0xb7aad465,\n  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,\n  0x69616a65, 0xb757fa01,\n  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,\n  0x6928397e, 0xb7054c6f,\n  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,\n  0x68eec7b9, 0xb6b2cbe2,\n  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,\n  0x68b5153a, 0xb660788c,\n  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,\n  0x687b2224, 0xb60e529f,\n  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,\n  0x6840ee9b, 0xb5bc5a50,\n  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,\n  0x68067ac3, 0xb56a8fd0,\n  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,\n  0x67cbc6c0, 0xb518f351,\n  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,\n  0x6790d2b6, 0xb4c78507,\n  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,\n  0x67559eca, 0xb4764523,\n  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,\n  0x671a2b20, 0xb42533d8,\n  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,\n  0x66de77dc, 0xb3d45157,\n  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,\n  0x66a28524, 0xb3839dd3,\n  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,\n  0x6666531d, 0xb333197c,\n  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,\n  0x6629e1ec, 0xb2e2c486,\n  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,\n  0x65ed31b5, 0xb2929f21,\n  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,\n  0x65b0429f, 0xb242a97e,\n  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,\n  0x657314cf, 0xb1f2e3d0,\n  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,\n  0x6535a86b, 0xb1a34e47,\n  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,\n  0x64f7fd98, 0xb153e915,\n  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,\n  0x64ba147d, 0xb104b46a,\n  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,\n  0x647bed3f, 0xb0b5b077,\n  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,\n  0x643d8806, 0xb066dd6d,\n  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,\n  0x63fee4f8, 0xb0183b7d,\n  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,\n  0x63c0043b, 0xafc9cad7,\n  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,\n  0x6380e5f6, 0xaf7b8bac,\n  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,\n  0x63418a50, 0xaf2d7e2b,\n  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,\n  0x6301f171, 0xaedfa285,\n  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,\n  0x62c21b7e, 0xae91f8eb,\n  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,\n  0x628208a1, 0xae44818b,\n  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,\n  0x6241b8ff, 0xadf73c96,\n  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,\n  0x62012cc2, 0xadaa2a3b,\n  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,\n  0x61c06410, 0xad5d4aaa,\n  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,\n  0x617f5f12, 0xad109e12,\n  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,\n  0x613e1df0, 0xacc424a3,\n  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,\n  0x60fca0d2, 0xac77de8b,\n  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,\n  0x60bae7e1, 0xac2bcbfa,\n  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,\n  0x6078f344, 0xabdfed1f,\n  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,\n  0x6036c325, 0xab944229,\n  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,\n  0x5ff457ad, 0xab48cb46,\n  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,\n  0x5fb1b104, 0xaafd88a4,\n  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,\n  0x5f6ecf53, 0xaab27a73,\n  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,\n  0x5f2bb2c5, 0xaa67a0e0,\n  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,\n  0x5ee85b82, 0xaa1cfc1a,\n  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,\n  0x5ea4c9b3, 0xa9d28c4e,\n  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,\n  0x5e60fd84, 0xa98851ac,\n  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,\n  0x5e1cf71c, 0xa93e4c5f,\n  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,\n  0x5dd8b6a7, 0xa8f47c97,\n  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,\n  0x5d943c4e, 0xa8aae280,\n  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,\n  0x5d4f883b, 0xa8617e48,\n  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,\n  0x5d0a9a9a, 0xa818501c,\n  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,\n  0x5cc57394, 0xa7cf582a,\n  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,\n  0x5c801354, 0xa786969e,\n  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,\n  0x5c3a7a05, 0xa73e0ba5,\n  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,\n  0x5bf4a7d2, 0xa6f5b76d,\n  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,\n  0x5bae9ce7, 0xa6ad9a21,\n  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,\n  0x5b68596d, 0xa665b3ee,\n  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,\n  0x5b21dd90, 0xa61e0501,\n  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,\n  0x5adb297d, 0xa5d68d85,\n  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,\n  0x5a943d5e, 0xa58f4da8,\n  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,\n  0x5a4d1960, 0xa5484594,\n  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,\n  0x5a05bdae, 0xa5017575,\n  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,\n  0x59be2a74, 0xa4badd78,\n  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,\n  0x59765fde, 0xa4747dc7,\n  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,\n  0x592e5e19, 0xa42e568f,\n  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,\n  0x58e62552, 0xa3e867fa,\n  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,\n  0x589db5b3, 0xa3a2b234,\n  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,\n  0x58550f6c, 0xa35d3567,\n  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,\n  0x580c32a7, 0xa317f1bf,\n  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,\n  0x57c31f92, 0xa2d2e766,\n  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,\n  0x5779d65b, 0xa28e1687,\n  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,\n  0x5730572e, 0xa2497f4c,\n  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,\n  0x56e6a239, 0xa20521e0,\n  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,\n  0x569cb7a8, 0xa1c0fe6c,\n  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,\n  0x565297ab, 0xa17d151b,\n  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,\n  0x5608426e, 0xa1396617,\n  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,\n  0x55bdb81f, 0xa0f5f189,\n  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,\n  0x5572f8ed, 0xa0b2b79b,\n  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,\n  0x55280505, 0xa06fb876,\n  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,\n  0x54dcdc96, 0xa02cf444,\n  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,\n  0x54917fce, 0x9fea6b2f,\n  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,\n  0x5445eedb, 0x9fa81d5e,\n  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,\n  0x53fa29ed, 0x9f660afb,\n  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,\n  0x53ae3131, 0x9f24342f,\n  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,\n  0x536204d7, 0x9ee29922,\n  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,\n  0x5315a50e, 0x9ea139fd,\n  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,\n  0x52c91204, 0x9e6016e8,\n  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,\n  0x527c4bea, 0x9e1f300b,\n  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,\n  0x522f52ee, 0x9dde858e,\n  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,\n  0x51e22740, 0x9d9e179a,\n  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,\n  0x5194c910, 0x9d5de656,\n  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,\n  0x5147388c, 0x9d1df1e9,\n  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,\n  0x50f975e6, 0x9cde3a7b,\n  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,\n  0x50ab814d, 0x9c9ec033,\n  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,\n  0x505d5af1, 0x9c5f8339,\n  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,\n  0x500f0302, 0x9c2083b3,\n  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,\n  0x4fc079b1, 0x9be1c1c8,\n  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,\n  0x4f71bf2e, 0x9ba33da0,\n  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,\n  0x4f22d3aa, 0x9b64f760,\n  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,\n  0x4ed3b755, 0x9b26ef2f,\n  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,\n  0x4e846a60, 0x9ae92533,\n  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,\n  0x4e34ecfc, 0x9aab9993,\n  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,\n  0x4de53f5a, 0x9a6e4c74,\n  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,\n  0x4d9561ac, 0x9a313dfc,\n  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,\n  0x4d455422, 0x99f46e51,\n  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,\n  0x4cf516ee, 0x99b7dd99,\n  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,\n  0x4ca4aa41, 0x997b8bf8,\n  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,\n  0x4c540e4e, 0x993f7993,\n  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,\n  0x4c034345, 0x9903a691,\n  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,\n  0x4bb24958, 0x98c81316,\n  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,\n  0x4b6120bb, 0x988cbf46,\n  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,\n  0x4b0fc99d, 0x9851ab46,\n  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,\n  0x4abe4433, 0x9816d73b,\n  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,\n  0x4a6c90ad, 0x97dc4349,\n  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,\n  0x4a1aaf3f, 0x97a1ef94,\n  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,\n  0x49c8a01b, 0x9767dc41,\n  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,\n  0x49766373, 0x972e0971,\n  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,\n  0x4923f97b, 0x96f4774b,\n  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,\n  0x48d16265, 0x96bb25f0,\n  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,\n  0x487e9e64, 0x96821585,\n  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,\n  0x482badab, 0x9649462d,\n  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,\n  0x47d8906d, 0x9610b80a,\n  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,\n  0x478546de, 0x95d86b3f,\n  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,\n  0x4731d131, 0x95a05ff0,\n  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,\n  0x46de2f99, 0x9568963f,\n  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,\n  0x468a624a, 0x95310e4e,\n  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,\n  0x46366978, 0x94f9c83f,\n  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,\n  0x45e24556, 0x94c2c435,\n  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,\n  0x458df619, 0x948c0252,\n  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,\n  0x45397bf4, 0x945582b7,\n  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,\n  0x44e4d71c, 0x941f4585,\n  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,\n  0x449007c4, 0x93e94adf,\n  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,\n  0x443b0e21, 0x93b392e6,\n  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,\n  0x43e5ea68, 0x937e1dbb,\n  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,\n  0x43909ccd, 0x9348eb7e,\n  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,\n  0x433b2585, 0x9313fc51,\n  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,\n  0x42e584c3, 0x92df5054,\n  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,\n  0x428fbabe, 0x92aae7a8,\n  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,\n  0x4239c7aa, 0x9276c26d,\n  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,\n  0x41e3abbc, 0x9242e0c4,\n  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,\n  0x418d6729, 0x920f42cb,\n  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,\n  0x4136fa27, 0x91dbe8a4,\n  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,\n  0x40e064ea, 0x91a8d26d,\n  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,\n  0x4089a7a8, 0x91760047,\n  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,\n  0x4032c297, 0x91437250,\n  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,\n  0x3fdbb5ec, 0x911128a8,\n  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,\n  0x3f8481dd, 0x90df236e,\n  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,\n  0x3f2d26a0, 0x90ad62c0,\n  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,\n  0x3ed5a46b, 0x907be6be,\n  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,\n  0x3e7dfb73, 0x904aaf86,\n  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,\n  0x3e262bee, 0x9019bd36,\n  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,\n  0x3dce3614, 0x8fe90fec,\n  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,\n  0x3d761a19, 0x8fb8a7c7,\n  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,\n  0x3d1dd835, 0x8f8884e4,\n  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,\n  0x3cc5709e, 0x8f58a761,\n  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,\n  0x3c6ce38a, 0x8f290f5c,\n  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,\n  0x3c143130, 0x8ef9bcf2,\n  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,\n  0x3bbb59c7, 0x8ecab040,\n  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,\n  0x3b625d86, 0x8e9be963,\n  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,\n  0x3b093ca3, 0x8e6d6877,\n  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,\n  0x3aaff755, 0x8e3f2d9b,\n  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,\n  0x3a568dd4, 0x8e1138ea,\n  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,\n  0x39fd0056, 0x8de38a80,\n  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,\n  0x39a34f13, 0x8db6227a,\n  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,\n  0x39497a43, 0x8d8900f3,\n  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,\n  0x38ef821c, 0x8d5c2609,\n  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,\n  0x389566d6, 0x8d2f91d5,\n  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,\n  0x383b28a9, 0x8d034474,\n  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,\n  0x37e0c7cc, 0x8cd73e01,\n  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,\n  0x37864477, 0x8cab7e98,\n  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,\n  0x372b9ee3, 0x8c800652,\n  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,\n  0x36d0d746, 0x8c54d54c,\n  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,\n  0x3675edd9, 0x8c29eb9f,\n  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,\n  0x361ae2d3, 0x8bff4966,\n  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,\n  0x35bfb66e, 0x8bd4eebc,\n  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,\n  0x356468e2, 0x8baadbba,\n  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,\n  0x3508fa66, 0x8b81107b,\n  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,\n  0x34ad6b32, 0x8b578d18,\n  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,\n  0x3451bb81, 0x8b2e51ab,\n  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,\n  0x33f5eb89, 0x8b055e4d,\n  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,\n  0x3399fb85, 0x8adcb318,\n  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,\n  0x333debab, 0x8ab45024,\n  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,\n  0x32e1bc36, 0x8a8c358b,\n  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,\n  0x32856d5e, 0x8a646365,\n  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,\n  0x3228ff5c, 0x8a3cd9cc,\n  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,\n  0x31cc7269, 0x8a1598d6,\n  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,\n  0x316fc6be, 0x89eea09d,\n  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,\n  0x3112fc95, 0x89c7f138,\n  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,\n  0x30b61426, 0x89a18ac0,\n  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,\n  0x30590dab, 0x897b6d4c,\n  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,\n  0x2ffbe95d, 0x895598f3,\n  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,\n  0x2f9ea775, 0x89300dce,\n  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,\n  0x2f41482e, 0x890acbf2,\n  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,\n  0x2ee3cbc1, 0x88e5d378,\n  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,\n  0x2e863267, 0x88c12475,\n  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,\n  0x2e287c5a, 0x889cbf01,\n  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,\n  0x2dcaa9d5, 0x8878a332,\n  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,\n  0x2d6cbb10, 0x8854d11e,\n  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,\n  0x2d0eb046, 0x883148db,\n  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,\n  0x2cb089b1, 0x880e0a7f,\n  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,\n  0x2c52478a, 0x87eb1621,\n  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,\n  0x2bf3ea0d, 0x87c86bd5,\n  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,\n  0x2b957173, 0x87a60bb1,\n  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,\n  0x2b36ddf7, 0x8783f5ca,\n  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,\n  0x2ad82fd2, 0x87622a35,\n  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,\n  0x2a796740, 0x8740a907,\n  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,\n  0x2a1a847b, 0x871f7255,\n  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,\n  0x29bb87bc, 0x86fe8633,\n  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,\n  0x295c7140, 0x86dde4b5,\n  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,\n  0x28fd4140, 0x86bd8df0,\n  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,\n  0x289df7f8, 0x869d81f8,\n  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,\n  0x283e95a1, 0x867dc0e0,\n  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,\n  0x27df1a77, 0x865e4abb,\n  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,\n  0x277f86b5, 0x863f1f9e,\n  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,\n  0x271fda96, 0x86203f9c,\n  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,\n  0x26c01655, 0x8601aac7,\n  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,\n  0x26603a2c, 0x85e36132,\n  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,\n  0x26004657, 0x85c562f1,\n  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,\n  0x25a03b11, 0x85a7b015,\n  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,\n  0x25401896, 0x858a48b1,\n  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,\n  0x24dfdf20, 0x856d2cd7,\n  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,\n  0x247f8eec, 0x85505c99,\n  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,\n  0x241f2833, 0x8533d809,\n  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,\n  0x23beab33, 0x85179f39,\n  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,\n  0x235e1826, 0x84fbb239,\n  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,\n  0x22fd6f48, 0x84e0111b,\n  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,\n  0x229cb0d5, 0x84c4bbf0,\n  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,\n  0x223bdd08, 0x84a9b2ca,\n  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,\n  0x21daf41d, 0x848ef5b7,\n  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,\n  0x2179f64f, 0x847484ca,\n  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,\n  0x2118e3dc, 0x845a6012,\n  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,\n  0x20b7bcfe, 0x844087a0,\n  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,\n  0x205681f1, 0x8426fb84,\n  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,\n  0x1ff532f2, 0x840dbbcc,\n  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,\n  0x1f93d03c, 0x83f4c889,\n  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,\n  0x1f325a0b, 0x83dc21cb,\n  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,\n  0x1ed0d09d, 0x83c3c7a0,\n  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,\n  0x1e6f342c, 0x83abba17,\n  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,\n  0x1e0d84f5, 0x8393f940,\n  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,\n  0x1dabc334, 0x837c8528,\n  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,\n  0x1d49ef26, 0x83655ddf,\n  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,\n  0x1ce80906, 0x834e8373,\n  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,\n  0x1c861113, 0x8337f5f1,\n  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,\n  0x1c240786, 0x8321b568,\n  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,\n  0x1bc1ec9e, 0x830bc1e6,\n  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,\n  0x1b5fc097, 0x82f61b77,\n  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,\n  0x1afd83ad, 0x82e0c22a,\n  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,\n  0x1a9b361d, 0x82cbb60b,\n  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,\n  0x1a38d823, 0x82b6f727,\n  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,\n  0x19d669fc, 0x82a2858c,\n  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,\n  0x1973ebe6, 0x828e6146,\n  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,\n  0x19115e1c, 0x827a8a61,\n  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,\n  0x18aec0db, 0x826700e9,\n  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,\n  0x184c1461, 0x8253c4eb,\n  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,\n  0x17e958ea, 0x8240d673,\n  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,\n  0x17868eb3, 0x822e358b,\n  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,\n  0x1723b5f9, 0x821be240,\n  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,\n  0x16c0cef9, 0x8209dc9e,\n  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,\n  0x165dd9f0, 0x81f824ae,\n  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,\n  0x15fad71b, 0x81e6ba7c,\n  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,\n  0x1597c6b7, 0x81d59e13,\n  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,\n  0x1534a901, 0x81c4cf7d,\n  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,\n  0x14d17e36, 0x81b44ec4,\n  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,\n  0x146e4694, 0x81a41bf4,\n  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,\n  0x140b0258, 0x81943715,\n  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,\n  0x13a7b1bf, 0x8184a032,\n  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,\n  0x13445505, 0x81755754,\n  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,\n  0x12e0ec6a, 0x81665c84,\n  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,\n  0x127d7829, 0x8157afcd,\n  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,\n  0x1219f880, 0x81495136,\n  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,\n  0x11b66dad, 0x813b40ca,\n  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,\n  0x1152d7ed, 0x812d7e8f,\n  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,\n  0x10ef377d, 0x81200a90,\n  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,\n  0x108b8c9b, 0x8112e4d4,\n  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,\n  0x1027d784, 0x81060d63,\n  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,\n  0xfc41876, 0x80f98446,\n  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,\n  0xf604faf, 0x80ed4984,\n  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,\n  0xefc7d6b, 0x80e15d24,\n  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,\n  0xe98a1e9, 0x80d5bf2e,\n  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,\n  0xe34bd66, 0x80ca6fa9,\n  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,\n  0xdd0d01f, 0x80bf6e9c,\n  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,\n  0xd6cda53, 0x80b4bc0e,\n  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,\n  0xd08dc3f, 0x80aa5806,\n  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,\n  0xca4d620, 0x80a04289,\n  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,\n  0xc40c835, 0x80967b9f,\n  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,\n  0xbdcb2bb, 0x808d034c,\n  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,\n  0xb7895f0, 0x8083d998,\n  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,\n  0xb147211, 0x807afe87,\n  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,\n  0xab0475c, 0x8072721f,\n  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,\n  0xa4c1610, 0x806a3466,\n  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,\n  0x9e7de6a, 0x80624560,\n  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,\n  0x983a0a7, 0x805aa512,\n  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,\n  0x91f5d06, 0x80535381,\n  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,\n  0x8bb13c5, 0x804c50b2,\n  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,\n  0x856c520, 0x80459ca9,\n  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,\n  0x7f27157, 0x803f376a,\n  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,\n  0x78e18a7, 0x803920f8,\n  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,\n  0x729bb4e, 0x80335959,\n  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,\n  0x6c5598a, 0x802de08e,\n  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,\n  0x660f398, 0x8028b69c,\n  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,\n  0x5fc89b8, 0x8023db86,\n  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,\n  0x5981c26, 0x801f4f4f,\n  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,\n  0x533ab20, 0x801b11fa,\n  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,\n  0x4cf36e5, 0x80172388,\n  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,\n  0x46abfb3, 0x801383fe,\n  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,\n  0x40645c7, 0x8010335c,\n  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,\n  0x3a1c960, 0x800d31a5,\n  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,\n  0x33d4abb, 0x800a7edb,\n  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,\n  0x2d8ca16, 0x80081b00,\n  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,\n  0x27447b0, 0x80060614,\n  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,\n  0x20fc3c6, 0x8004401a,\n  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,\n  0x1ab3e97, 0x8002c912,\n  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,\n  0x146b860, 0x8001a0fd,\n  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,\n  0xe23160, 0x8000c7dc,\n  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,\n  0x80003daf,\n  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,\n  0x80000278,\n};\n\nstatic const q31_t WeightsQ31_8192[16384] = {\n  0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,\n    0xffed2684,\n  0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,\n    0x7ffff872, 0xffd40489,\n  0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,\n    0x7fffed57, 0xffbae290,\n  0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,\n    0x7fffdd4d, 0xffa1c09a,\n  0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,\n    0x7fffc854, 0xff889ea7,\n  0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,\n    0x7fffae6c, 0xff6f7cba,\n  0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,\n    0x7fff8f94, 0xff565ad1,\n  0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,\n    0x7fff6bcd, 0xff3d38ef,\n  0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,\n    0x7fff4317, 0xff241715,\n  0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,\n    0x7fff1572, 0xff0af543,\n  0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,\n    0x7ffee2dd, 0xfef1d37b,\n  0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,\n    0x7ffeab59, 0xfed8b1bd,\n  0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,\n    0x7ffe6ee5, 0xfebf900a,\n  0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,\n    0x7ffe2d83, 0xfea66e64,\n  0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,\n    0x7ffde731, 0xfe8d4ccb,\n  0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,\n    0x7ffd9bf0, 0xfe742b41,\n  0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,\n    0x7ffd4bc0, 0xfe5b09c5,\n  0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,\n    0x7ffcf6a0, 0xfe41e85a,\n  0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,\n    0x7ffc9c92, 0xfe28c700,\n  0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,\n    0x7ffc3d94, 0xfe0fa5b8,\n  0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,\n    0x7ffbd9a7, 0xfdf68484,\n  0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,\n    0x7ffb70cb, 0xfddd6363,\n  0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,\n    0x7ffb0300, 0xfdc44258,\n  0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,\n    0x7ffa9045, 0xfdab2162,\n  0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,\n    0x7ffa189c, 0xfd920084,\n  0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,\n    0x7ff99c03, 0xfd78dfbd,\n  0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,\n    0x7ff91a7b, 0xfd5fbf10,\n  0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,\n    0x7ff89405, 0xfd469e7c,\n  0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,\n    0x7ff8089f, 0xfd2d7e04,\n  0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,\n    0x7ff7784a, 0xfd145da7,\n  0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,\n    0x7ff6e307, 0xfcfb3d67,\n  0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,\n    0x7ff648d4, 0xfce21d45,\n  0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,\n    0x7ff5a9b2, 0xfcc8fd41,\n  0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,\n    0x7ff505a2, 0xfcafdd5e,\n  0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,\n    0x7ff45ca3, 0xfc96bd9b,\n  0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,\n    0x7ff3aeb4, 0xfc7d9df9,\n  0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,\n    0x7ff2fbd7, 0xfc647e7b,\n  0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,\n    0x7ff2440b, 0xfc4b5f20,\n  0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,\n    0x7ff18751, 0xfc323fe9,\n  0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,\n    0x7ff0c5a7, 0xfc1920d8,\n  0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,\n    0x7fefff0f, 0xfc0001ee,\n  0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,\n    0x7fef3388, 0xfbe6e32b,\n  0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,\n    0x7fee6313, 0xfbcdc490,\n  0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,\n    0x7fed8daf, 0xfbb4a61f,\n  0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,\n    0x7fecb35c, 0xfb9b87d8,\n  0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,\n    0x7febd41b, 0xfb8269bd,\n  0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,\n    0x7feaefeb, 0xfb694bce,\n  0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,\n    0x7fea06cd, 0xfb502e0c,\n  0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,\n    0x7fe918c0, 0xfb371078,\n  0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,\n    0x7fe825c5, 0xfb1df314,\n  0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,\n    0x7fe72ddb, 0xfb04d5e0,\n  0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,\n    0x7fe63103, 0xfaebb8dd,\n  0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,\n    0x7fe52f3d, 0xfad29c0c,\n  0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,\n    0x7fe42889, 0xfab97f6e,\n  0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,\n    0x7fe31ce6, 0xfaa06305,\n  0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,\n    0x7fe20c55, 0xfa8746d0,\n  0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,\n    0x7fe0f6d6, 0xfa6e2ad1,\n  0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,\n    0x7fdfdc69, 0xfa550f0a,\n  0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,\n    0x7fdebd0d, 0xfa3bf37a,\n  0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,\n    0x7fdd98c4, 0xfa22d823,\n  0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,\n    0x7fdc6f8d, 0xfa09bd06,\n  0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,\n    0x7fdb4167, 0xf9f0a224,\n  0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,\n    0x7fda0e54, 0xf9d7877e,\n  0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,\n    0x7fd8d653, 0xf9be6d15,\n  0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,\n    0x7fd79965, 0xf9a552e9,\n  0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,\n    0x7fd65788, 0xf98c38fc,\n  0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,\n    0x7fd510be, 0xf9731f4e,\n  0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,\n    0x7fd3c506, 0xf95a05e2,\n  0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,\n    0x7fd27460, 0xf940ecb7,\n  0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,\n    0x7fd11ecd, 0xf927d3ce,\n  0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,\n    0x7fcfc44d, 0xf90ebb29,\n  0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,\n    0x7fce64df, 0xf8f5a2c9,\n  0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,\n    0x7fcd0083, 0xf8dc8aae,\n  0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,\n    0x7fcb973b, 0xf8c372d9,\n  0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,\n    0x7fca2905, 0xf8aa5b4c,\n  0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,\n    0x7fc8b5e1, 0xf8914407,\n  0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,\n    0x7fc73dd1, 0xf8782d0c,\n  0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,\n    0x7fc5c0d3, 0xf85f165b,\n  0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,\n    0x7fc43ee9, 0xf845fff5,\n  0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,\n    0x7fc2b811, 0xf82ce9dc,\n  0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,\n    0x7fc12c4d, 0xf813d410,\n  0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,\n    0x7fbf9b9b, 0xf7fabe92,\n  0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,\n    0x7fbe05fd, 0xf7e1a963,\n  0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,\n    0x7fbc6b72, 0xf7c89484,\n  0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,\n    0x7fbacbfa, 0xf7af7ff6,\n  0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,\n    0x7fb92796, 0xf7966bbb,\n  0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,\n    0x7fb77e45, 0xf77d57d2,\n  0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,\n    0x7fb5d007, 0xf764443d,\n  0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,\n    0x7fb41cdd, 0xf74b30fe,\n  0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,\n    0x7fb264c7, 0xf7321e14,\n  0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,\n    0x7fb0a7c4, 0xf7190b81,\n  0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,\n    0x7faee5d5, 0xf6fff946,\n  0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,\n    0x7fad1efa, 0xf6e6e764,\n  0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,\n    0x7fab5333, 0xf6cdd5dc,\n  0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,\n    0x7fa98280, 0xf6b4c4ae,\n  0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,\n    0x7fa7ace1, 0xf69bb3dd,\n  0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,\n    0x7fa5d256, 0xf682a367,\n  0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,\n    0x7fa3f2df, 0xf6699350,\n  0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,\n    0x7fa20e7c, 0xf6508397,\n  0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,\n    0x7fa0252e, 0xf637743e,\n  0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,\n    0x7f9e36f4, 0xf61e6545,\n  0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,\n    0x7f9c43ce, 0xf60556ae,\n  0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,\n    0x7f9a4bbd, 0xf5ec4879,\n  0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,\n    0x7f984ec1, 0xf5d33aa8,\n  0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,\n    0x7f964cd9, 0xf5ba2d3b,\n  0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,\n    0x7f944606, 0xf5a12034,\n  0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,\n    0x7f923a48, 0xf5881393,\n  0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,\n    0x7f90299f, 0xf56f0759,\n  0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,\n    0x7f8e140a, 0xf555fb88,\n  0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,\n    0x7f8bf98b, 0xf53cf01f,\n  0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,\n    0x7f89da21, 0xf523e521,\n  0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,\n    0x7f87b5cd, 0xf50ada8f,\n  0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,\n    0x7f858c8d, 0xf4f1d068,\n  0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,\n    0x7f835e64, 0xf4d8c6ae,\n  0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,\n    0x7f812b4f, 0xf4bfbd63,\n  0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,\n    0x7f7ef350, 0xf4a6b486,\n  0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,\n    0x7f7cb667, 0xf48dac1a,\n  0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,\n    0x7f7a7494, 0xf474a41f,\n  0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,\n    0x7f782dd6, 0xf45b9c95,\n  0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,\n    0x7f75e22e, 0xf442957e,\n  0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,\n    0x7f73919d, 0xf4298edc,\n  0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,\n    0x7f713c21, 0xf41088ae,\n  0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,\n    0x7f6ee1bc, 0xf3f782f6,\n  0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,\n    0x7f6c826d, 0xf3de7db4,\n  0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,\n    0x7f6a1e34, 0xf3c578eb,\n  0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,\n    0x7f67b512, 0xf3ac749a,\n  0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,\n    0x7f654706, 0xf39370c2,\n  0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,\n    0x7f62d411, 0xf37a6d66,\n  0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,\n    0x7f605c33, 0xf3616a85,\n  0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,\n    0x7f5ddf6b, 0xf3486820,\n  0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,\n    0x7f5b5dbb, 0xf32f6639,\n  0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,\n    0x7f58d721, 0xf31664d1,\n  0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,\n    0x7f564b9f, 0xf2fd63e8,\n  0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,\n    0x7f53bb34, 0xf2e4637f,\n  0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,\n    0x7f5125e0, 0xf2cb6398,\n  0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,\n    0x7f4e8ba4, 0xf2b26433,\n  0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,\n    0x7f4bec7f, 0xf2996551,\n  0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,\n    0x7f494872, 0xf28066f4,\n  0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,\n    0x7f469f7d, 0xf267691b,\n  0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,\n    0x7f43f19f, 0xf24e6bc9,\n  0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,\n    0x7f413ed9, 0xf2356efe,\n  0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,\n    0x7f3e872c, 0xf21c72bc,\n  0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,\n    0x7f3bca96, 0xf2037702,\n  0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,\n    0x7f390919, 0xf1ea7bd2,\n  0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,\n    0x7f3642b4, 0xf1d1812e,\n  0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,\n    0x7f337768, 0xf1b88715,\n  0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,\n    0x7f30a734, 0xf19f8d89,\n  0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,\n    0x7f2dd219, 0xf186948c,\n  0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,\n    0x7f2af817, 0xf16d9c1d,\n  0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,\n    0x7f28192d, 0xf154a43d,\n  0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,\n    0x7f25355d, 0xf13bacef,\n  0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,\n    0x7f224ca6, 0xf122b632,\n  0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,\n    0x7f1f5f08, 0xf109c009,\n  0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,\n    0x7f1c6c83, 0xf0f0ca72,\n  0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,\n    0x7f197518, 0xf0d7d571,\n  0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,\n    0x7f1678c6, 0xf0bee105,\n  0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,\n    0x7f13778e, 0xf0a5ed2f,\n  0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,\n    0x7f107170, 0xf08cf9f1,\n  0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,\n    0x7f0d666c, 0xf074074c,\n  0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,\n    0x7f0a5682, 0xf05b1540,\n  0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,\n    0x7f0741b2, 0xf04223ce,\n  0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,\n    0x7f0427fc, 0xf02932f8,\n  0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,\n    0x7f010961, 0xf01042be,\n  0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,\n    0x7efde5e0, 0xeff75321,\n  0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,\n    0x7efabd7a, 0xefde6423,\n  0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,\n    0x7ef7902f, 0xefc575c3,\n  0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,\n    0x7ef45dfe, 0xefac8804,\n  0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,\n    0x7ef126e9, 0xef939ae6,\n  0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,\n    0x7eedeaee, 0xef7aae6b,\n  0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,\n    0x7eeaaa0f, 0xef61c292,\n  0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,\n    0x7ee7644c, 0xef48d75d,\n  0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,\n    0x7ee419a3, 0xef2feccd,\n  0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,\n    0x7ee0ca17, 0xef1702e4,\n  0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,\n    0x7edd75a6, 0xeefe19a1,\n  0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,\n    0x7eda1c51, 0xeee53105,\n  0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,\n    0x7ed6be18, 0xeecc4913,\n  0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,\n    0x7ed35afb, 0xeeb361cb,\n  0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,\n    0x7ecff2fb, 0xee9a7b2d,\n  0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,\n    0x7ecc8617, 0xee81953b,\n  0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,\n    0x7ec9144f, 0xee68aff6,\n  0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,\n    0x7ec59da5, 0xee4fcb5e,\n  0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,\n    0x7ec22217, 0xee36e775,\n  0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,\n    0x7ebea1a6, 0xee1e043b,\n  0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,\n    0x7ebb1c52, 0xee0521b2,\n  0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,\n    0x7eb7921b, 0xedec3fda,\n  0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,\n    0x7eb40301, 0xedd35eb5,\n  0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,\n    0x7eb06f05, 0xedba7e43,\n  0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,\n    0x7eacd627, 0xeda19e85,\n  0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,\n    0x7ea93867, 0xed88bf7d,\n  0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,\n    0x7ea595c4, 0xed6fe12b,\n  0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,\n    0x7ea1ee3f, 0xed570390,\n  0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,\n    0x7e9e41d9, 0xed3e26ad,\n  0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,\n    0x7e9a9091, 0xed254a84,\n  0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,\n    0x7e96da67, 0xed0c6f14,\n  0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,\n    0x7e931f5c, 0xecf39460,\n  0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,\n    0x7e8f5f70, 0xecdaba67,\n  0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,\n    0x7e8b9aa3, 0xecc1e12c,\n  0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,\n    0x7e87d0f5, 0xeca908ae,\n  0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,\n    0x7e840265, 0xec9030f0,\n  0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,\n    0x7e802ef6, 0xec7759f1,\n  0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,\n    0x7e7c56a5, 0xec5e83b3,\n  0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,\n    0x7e787975, 0xec45ae36,\n  0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,\n    0x7e749764, 0xec2cd97d,\n  0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,\n    0x7e70b073, 0xec140587,\n  0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,\n    0x7e6cc4a2, 0xebfb3256,\n  0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,\n    0x7e68d3f2, 0xebe25fea,\n  0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,\n    0x7e64de62, 0xebc98e45,\n  0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,\n    0x7e60e3f2, 0xebb0bd67,\n  0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,\n    0x7e5ce4a3, 0xeb97ed52,\n  0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,\n    0x7e58e075, 0xeb7f1e06,\n  0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,\n    0x7e54d768, 0xeb664f84,\n  0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,\n    0x7e50c97c, 0xeb4d81ce,\n  0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,\n    0x7e4cb6b1, 0xeb34b4e4,\n  0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,\n    0x7e489f08, 0xeb1be8c8,\n  0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,\n    0x7e448281, 0xeb031d79,\n  0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,\n    0x7e40611b, 0xeaea52fa,\n  0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,\n    0x7e3c3ad7, 0xead1894b,\n  0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,\n    0x7e380fb5, 0xeab8c06c,\n  0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,\n    0x7e33dfb6, 0xea9ff860,\n  0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,\n    0x7e2faad9, 0xea873127,\n  0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,\n    0x7e2b711f, 0xea6e6ac2,\n  0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,\n    0x7e273287, 0xea55a531,\n  0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,\n    0x7e22ef12, 0xea3ce077,\n  0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,\n    0x7e1ea6c1, 0xea241c93,\n  0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,\n    0x7e1a5992, 0xea0b5987,\n  0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,\n    0x7e160787, 0xe9f29753,\n  0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,\n    0x7e11b0a0, 0xe9d9d5fa,\n  0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,\n    0x7e0d54dc, 0xe9c1157a,\n  0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,\n    0x7e08f43d, 0xe9a855d7,\n  0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,\n    0x7e048ec1, 0xe98f9710,\n  0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,\n    0x7e00246a, 0xe976d926,\n  0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,\n    0x7dfbb537, 0xe95e1c1b,\n  0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,\n    0x7df74128, 0xe9455fef,\n  0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,\n    0x7df2c83f, 0xe92ca4a4,\n  0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,\n    0x7dee4a7a, 0xe913ea39,\n  0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,\n    0x7de9c7da, 0xe8fb30b1,\n  0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,\n    0x7de54060, 0xe8e2780d,\n  0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,\n    0x7de0b40b, 0xe8c9c04c,\n  0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,\n    0x7ddc22dc, 0xe8b10971,\n  0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,\n    0x7dd78cd3, 0xe898537b,\n  0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,\n    0x7dd2f1f0, 0xe87f9e6c,\n  0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,\n    0x7dce5232, 0xe866ea46,\n  0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,\n    0x7dc9ad9c, 0xe84e3708,\n  0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,\n    0x7dc5042b, 0xe83584b4,\n  0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,\n    0x7dc055e2, 0xe81cd34b,\n  0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,\n    0x7dbba2bf, 0xe80422ce,\n  0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,\n    0x7db6eac3, 0xe7eb733e,\n  0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,\n    0x7db22def, 0xe7d2c49b,\n  0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,\n    0x7dad6c42, 0xe7ba16e7,\n  0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,\n    0x7da8a5bc, 0xe7a16a22,\n  0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,\n    0x7da3da5f, 0xe788be4e,\n  0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,\n    0x7d9f0a29, 0xe770136b,\n  0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,\n    0x7d9a351c, 0xe757697b,\n  0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,\n    0x7d955b37, 0xe73ec07e,\n  0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,\n    0x7d907c7a, 0xe7261875,\n  0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,\n    0x7d8b98e6, 0xe70d7162,\n  0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,\n    0x7d86b07c, 0xe6f4cb45,\n  0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,\n    0x7d81c33a, 0xe6dc261f,\n  0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,\n    0x7d7cd121, 0xe6c381f1,\n  0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,\n    0x7d77da32, 0xe6aadebc,\n  0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,\n    0x7d72de6d, 0xe6923c82,\n  0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,\n    0x7d6dddd2, 0xe6799b42,\n  0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,\n    0x7d68d860, 0xe660fafe,\n  0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,\n    0x7d63ce19, 0xe6485bb7,\n  0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,\n    0x7d5ebefc, 0xe62fbd6e,\n  0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,\n    0x7d59ab0a, 0xe6172024,\n  0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,\n    0x7d549243, 0xe5fe83d9,\n  0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,\n    0x7d4f74a7, 0xe5e5e88f,\n  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,\n    0x7d4a5236, 0xe5cd4e47,\n  0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,\n    0x7d452af1, 0xe5b4b501,\n  0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,\n    0x7d3ffed7, 0xe59c1cbf,\n  0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,\n    0x7d3acde9, 0xe5838581,\n  0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,\n    0x7d359827, 0xe56aef49,\n  0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,\n    0x7d305d91, 0xe5525a17,\n  0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,\n    0x7d2b1e28, 0xe539c5ec,\n  0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,\n    0x7d25d9eb, 0xe52132c9,\n  0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,\n    0x7d2090db, 0xe508a0b0,\n  0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,\n    0x7d1b42f9, 0xe4f00fa1,\n  0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,\n    0x7d15f043, 0xe4d77f9d,\n  0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,\n    0x7d1098bb, 0xe4bef0a5,\n  0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,\n    0x7d0b3c60, 0xe4a662ba,\n  0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,\n    0x7d05db34, 0xe48dd5dd,\n  0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,\n    0x7d007535, 0xe4754a0e,\n  0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,\n    0x7cfb0a65, 0xe45cbf50,\n  0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,\n    0x7cf59ac4, 0xe44435a2,\n  0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,\n    0x7cf02651, 0xe42bad07,\n  0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,\n    0x7ceaad0c, 0xe413257d,\n  0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,\n    0x7ce52ef7, 0xe3fa9f08,\n  0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,\n    0x7cdfac12, 0xe3e219a7,\n  0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,\n    0x7cda245c, 0xe3c9955b,\n  0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,\n    0x7cd497d5, 0xe3b11226,\n  0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,\n    0x7ccf067f, 0xe3989008,\n  0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,\n    0x7cc97059, 0xe3800f03,\n  0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,\n    0x7cc3d563, 0xe3678f17,\n  0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,\n    0x7cbe359e, 0xe34f1045,\n  0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,\n    0x7cb8910a, 0xe336928e,\n  0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,\n    0x7cb2e7a6, 0xe31e15f4,\n  0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,\n    0x7cad3974, 0xe3059a76,\n  0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,\n    0x7ca78674, 0xe2ed2017,\n  0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,\n    0x7ca1cea5, 0xe2d4a6d6,\n  0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,\n    0x7c9c1208, 0xe2bc2eb5,\n  0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,\n    0x7c96509d, 0xe2a3b7b5,\n  0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,\n    0x7c908a65, 0xe28b41d7,\n  0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,\n    0x7c8abf5f, 0xe272cd1c,\n  0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,\n    0x7c84ef8c, 0xe25a5984,\n  0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,\n    0x7c7f1aed, 0xe241e711,\n  0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,\n    0x7c794180, 0xe22975c4,\n  0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,\n    0x7c736347, 0xe211059d,\n  0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,\n    0x7c6d8041, 0xe1f8969d,\n  0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,\n    0x7c679870, 0xe1e028c6,\n  0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,\n    0x7c61abd3, 0xe1c7bc18,\n  0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,\n    0x7c5bba6a, 0xe1af5094,\n  0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,\n    0x7c55c436, 0xe196e63c,\n  0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,\n    0x7c4fc936, 0xe17e7d0f,\n  0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,\n    0x7c49c96c, 0xe1661510,\n  0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,\n    0x7c43c4d7, 0xe14dae3f,\n  0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,\n    0x7c3dbb78, 0xe135489d,\n  0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,\n    0x7c37ad4e, 0xe11ce42a,\n  0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,\n    0x7c319a5a, 0xe10480e9,\n  0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,\n    0x7c2b829d, 0xe0ec1ed9,\n  0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,\n    0x7c256616, 0xe0d3bdfc,\n  0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,\n    0x7c1f44c6, 0xe0bb5e53,\n  0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,\n    0x7c191ead, 0xe0a2ffde,\n  0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,\n    0x7c12f3cb, 0xe08aa29f,\n  0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,\n    0x7c0cc421, 0xe0724696,\n  0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,\n    0x7c068fae, 0xe059ebc5,\n  0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,\n    0x7c005673, 0xe041922c,\n  0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,\n    0x7bfa1870, 0xe02939cc,\n  0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,\n    0x7bf3d5a6, 0xe010e2a7,\n  0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,\n    0x7bed8e14, 0xdff88cbc,\n  0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,\n    0x7be741bb, 0xdfe0380e,\n  0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,\n    0x7be0f09b, 0xdfc7e49d,\n  0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,\n    0x7bda9ab5, 0xdfaf926a,\n  0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,\n    0x7bd44008, 0xdf974176,\n  0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,\n    0x7bcde095, 0xdf7ef1c2,\n  0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,\n    0x7bc77c5d, 0xdf66a34e,\n  0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,\n    0x7bc1135e, 0xdf4e561c,\n  0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,\n    0x7bbaa59a, 0xdf360a2d,\n  0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,\n    0x7bb43311, 0xdf1dbf82,\n  0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,\n    0x7badbbc3, 0xdf05761b,\n  0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,\n    0x7ba73fb1, 0xdeed2dfa,\n  0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,\n    0x7ba0beda, 0xded4e71f,\n  0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,\n    0x7b9a393f, 0xdebca18b,\n  0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,\n    0x7b93aee0, 0xdea45d40,\n  0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,\n    0x7b8d1fbd, 0xde8c1a3e,\n  0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,\n    0x7b868bd7, 0xde73d886,\n  0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,\n    0x7b7ff32e, 0xde5b9819,\n  0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,\n    0x7b7955c2, 0xde4358f8,\n  0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,\n    0x7b72b393, 0xde2b1b24,\n  0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,\n    0x7b6c0ca2, 0xde12de9e,\n  0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,\n    0x7b6560ee, 0xddfaa367,\n  0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,\n    0x7b5eb079, 0xdde26980,\n  0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,\n    0x7b57fb42, 0xddca30e9,\n  0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,\n    0x7b51414a, 0xddb1f9a4,\n  0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,\n    0x7b4a8291, 0xdd99c3b2,\n  0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,\n    0x7b43bf17, 0xdd818f13,\n  0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,\n    0x7b3cf6dc, 0xdd695bc9,\n  0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,\n    0x7b3629e1, 0xdd5129d4,\n  0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,\n    0x7b2f5826, 0xdd38f935,\n  0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,\n    0x7b2881ac, 0xdd20c9ed,\n  0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,\n    0x7b21a671, 0xdd089bfe,\n  0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,\n    0x7b1ac678, 0xdcf06f68,\n  0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,\n    0x7b13e1bf, 0xdcd8442b,\n  0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,\n    0x7b0cf848, 0xdcc01a4a,\n  0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,\n    0x7b060a12, 0xdca7f1c5,\n  0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,\n    0x7aff171e, 0xdc8fca9c,\n  0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,\n    0x7af81f6c, 0xdc77a4d2,\n  0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,\n    0x7af122fd, 0xdc5f8066,\n  0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,\n    0x7aea21d0, 0xdc475d59,\n  0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,\n    0x7ae31be6, 0xdc2f3bad,\n  0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,\n    0x7adc113f, 0xdc171b63,\n  0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,\n    0x7ad501dc, 0xdbfefc7b,\n  0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,\n    0x7acdedbc, 0xdbe6def6,\n  0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,\n    0x7ac6d4e0, 0xdbcec2d6,\n  0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,\n    0x7abfb749, 0xdbb6a81b,\n  0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,\n    0x7ab894f6, 0xdb9e8ec6,\n  0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,\n    0x7ab16de7, 0xdb8676d8,\n  0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,\n    0x7aaa421e, 0xdb6e6052,\n  0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,\n    0x7aa3119a, 0xdb564b35,\n  0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,\n    0x7a9bdc5c, 0xdb3e3781,\n  0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,\n    0x7a94a264, 0xdb262539,\n  0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,\n    0x7a8d63b2, 0xdb0e145c,\n  0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,\n    0x7a862046, 0xdaf604ec,\n  0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,\n    0x7a7ed821, 0xdaddf6ea,\n  0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,\n    0x7a778b43, 0xdac5ea56,\n  0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,\n    0x7a7039ad, 0xdaaddf31,\n  0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,\n    0x7a68e35e, 0xda95d57d,\n  0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,\n    0x7a618857, 0xda7dcd3a,\n  0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,\n    0x7a5a2898, 0xda65c669,\n  0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,\n    0x7a52c421, 0xda4dc10b,\n  0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,\n    0x7a4b5af3, 0xda35bd22,\n  0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,\n    0x7a43ed0e, 0xda1dbaad,\n  0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,\n    0x7a3c7a73, 0xda05b9ae,\n  0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,\n    0x7a350321, 0xd9edba26,\n  0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,\n    0x7a2d8719, 0xd9d5bc16,\n  0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,\n    0x7a26065b, 0xd9bdbf7e,\n  0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,\n    0x7a1e80e7, 0xd9a5c461,\n  0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,\n    0x7a16f6be, 0xd98dcabd,\n  0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,\n    0x7a0f67e0, 0xd975d295,\n  0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,\n    0x7a07d44e, 0xd95ddbea,\n  0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,\n    0x7a003c07, 0xd945e6bb,\n  0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,\n    0x79f89f0c, 0xd92df30b,\n  0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,\n    0x79f0fd5d, 0xd91600da,\n  0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,\n    0x79e956fb, 0xd8fe1029,\n  0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,\n    0x79e1abe6, 0xd8e620fa,\n  0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,\n    0x79d9fc1d, 0xd8ce334c,\n  0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,\n    0x79d247a2, 0xd8b64720,\n  0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,\n    0x79ca8e75, 0xd89e5c79,\n  0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,\n    0x79c2d095, 0xd8867356,\n  0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,\n    0x79bb0e04, 0xd86e8bb9,\n  0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,\n    0x79b346c2, 0xd856a5a3,\n  0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,\n    0x79ab7ace, 0xd83ec114,\n  0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,\n    0x79a3aa29, 0xd826de0d,\n  0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,\n    0x799bd4d4, 0xd80efc8f,\n  0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,\n    0x7993facf, 0xd7f71c9c,\n  0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,\n    0x798c1c1a, 0xd7df3e34,\n  0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,\n    0x798438b5, 0xd7c76158,\n  0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,\n    0x797c50a1, 0xd7af8609,\n  0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,\n    0x797463de, 0xd797ac48,\n  0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,\n    0x796c726c, 0xd77fd415,\n  0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,\n    0x79647c4c, 0xd767fd72,\n  0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,\n    0x795c817d, 0xd7502860,\n  0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,\n    0x79548201, 0xd73854e0,\n  0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,\n    0x794c7dd7, 0xd72082f2,\n  0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,\n    0x79447500, 0xd708b297,\n  0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,\n    0x793c677d, 0xd6f0e3d1,\n  0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,\n    0x7934554d, 0xd6d916a0,\n  0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,\n    0x792c3e70, 0xd6c14b05,\n  0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,\n    0x792422e8, 0xd6a98101,\n  0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,\n    0x791c02b4, 0xd691b895,\n  0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,\n    0x7913ddd4, 0xd679f1c2,\n  0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,\n    0x790bb44a, 0xd6622c89,\n  0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,\n    0x79038615, 0xd64a68eb,\n  0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,\n    0x78fb5336, 0xd632a6e8,\n  0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,\n    0x78f31bac, 0xd61ae682,\n  0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,\n    0x78eadf79, 0xd60327b9,\n  0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,\n    0x78e29e9d, 0xd5eb6a8f,\n  0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,\n    0x78da5917, 0xd5d3af04,\n  0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,\n    0x78d20ee9, 0xd5bbf519,\n  0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,\n    0x78c9c012, 0xd5a43cd0,\n  0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,\n    0x78c16c93, 0xd58c8628,\n  0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,\n    0x78b9146c, 0xd574d124,\n  0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,\n    0x78b0b79e, 0xd55d1dc3,\n  0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,\n    0x78a85628, 0xd5456c07,\n  0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,\n    0x789ff00c, 0xd52dbbf1,\n  0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,\n    0x78978549, 0xd5160d82,\n  0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,\n    0x788f15e0, 0xd4fe60ba,\n  0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,\n    0x7886a1d1, 0xd4e6b59a,\n  0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,\n    0x787e291d, 0xd4cf0c24,\n  0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,\n    0x7875abc3, 0xd4b76458,\n  0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,\n    0x786d29c5, 0xd49fbe37,\n  0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,\n    0x7864a322, 0xd48819c3,\n  0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,\n    0x785c17db, 0xd47076fb,\n  0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,\n    0x785387ef, 0xd458d5e2,\n  0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,\n    0x784af361, 0xd4413677,\n  0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,\n    0x78425a2f, 0xd42998bc,\n  0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,\n    0x7839bc5a, 0xd411fcb2,\n  0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,\n    0x783119e2, 0xd3fa6259,\n  0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,\n    0x782872c8, 0xd3e2c9b2,\n  0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,\n    0x781fc70d, 0xd3cb32c0,\n  0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,\n    0x781716b0, 0xd3b39d81,\n  0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,\n    0x780e61b1, 0xd39c09f7,\n  0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,\n    0x7805a812, 0xd3847824,\n  0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,\n    0x77fce9d2, 0xd36ce808,\n  0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,\n    0x77f426f2, 0xd35559a4,\n  0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,\n    0x77eb5f71, 0xd33dccf8,\n  0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,\n    0x77e29352, 0xd3264206,\n  0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,\n    0x77d9c293, 0xd30eb8cf,\n  0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,\n    0x77d0ed35, 0xd2f73154,\n  0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,\n    0x77c81339, 0xd2dfab95,\n  0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,\n    0x77bf349f, 0xd2c82793,\n  0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,\n    0x77b65166, 0xd2b0a54f,\n  0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,\n    0x77ad6990, 0xd29924cb,\n  0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,\n    0x77a47d1d, 0xd281a607,\n  0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,\n    0x779b8c0e, 0xd26a2904,\n  0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,\n    0x77929661, 0xd252adc3,\n  0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,\n    0x77899c19, 0xd23b3444,\n  0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,\n    0x77809d35, 0xd223bc8a,\n  0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,\n    0x777799b5, 0xd20c4694,\n  0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,\n    0x776e919a, 0xd1f4d263,\n  0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,\n    0x776584e5, 0xd1dd5ff9,\n  0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,\n    0x775c7395, 0xd1c5ef56,\n  0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,\n    0x77535dab, 0xd1ae807c,\n  0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,\n    0x774a4327, 0xd197136b,\n  0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,\n    0x7741240a, 0xd17fa823,\n  0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,\n    0x77380054, 0xd1683ea7,\n  0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,\n    0x772ed805, 0xd150d6f6,\n  0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,\n    0x7725ab1f, 0xd1397113,\n  0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,\n    0x771c79a0, 0xd1220cfc,\n  0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,\n    0x77134389, 0xd10aaab5,\n  0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,\n    0x770a08dc, 0xd0f34a3d,\n  0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,\n    0x7700c997, 0xd0dbeb95,\n  0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,\n    0x76f785bc, 0xd0c48ebf,\n  0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,\n    0x76ee3d4b, 0xd0ad33ba,\n  0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,\n    0x76e4f044, 0xd095da89,\n  0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,\n    0x76db9ea7, 0xd07e832c,\n  0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,\n    0x76d24876, 0xd0672da3,\n  0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,\n    0x76c8edb0, 0xd04fd9f1,\n  0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,\n    0x76bf8e55, 0xd0388815,\n  0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,\n    0x76b62a66, 0xd0213810,\n  0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,\n    0x76acc1e4, 0xd009e9e4,\n  0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,\n    0x76a354cf, 0xcff29d92,\n  0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,\n    0x7699e326, 0xcfdb531a,\n  0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,\n    0x76906ceb, 0xcfc40a7c,\n  0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,\n    0x7686f21e, 0xcfacc3bb,\n  0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,\n    0x767d72bf, 0xcf957ed7,\n  0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,\n    0x7673eecf, 0xcf7e3bd1,\n  0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,\n    0x766a664d, 0xcf66faa9,\n  0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,\n    0x7660d93b, 0xcf4fbb61,\n  0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,\n    0x76574798, 0xcf387dfa,\n  0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,\n    0x764db166, 0xcf214274,\n  0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,\n    0x764416a4, 0xcf0a08d0,\n  0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,\n    0x763a7752, 0xcef2d110,\n  0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,\n    0x7630d372, 0xcedb9b33,\n  0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,\n    0x76272b03, 0xcec4673c,\n  0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,\n    0x761d7e06, 0xcead352b,\n  0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,\n    0x7613cc7c, 0xce960500,\n  0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,\n    0x760a1664, 0xce7ed6bd,\n  0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,\n    0x76005bbf, 0xce67aa63,\n  0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,\n    0x75f69c8d, 0xce507ff2,\n  0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,\n    0x75ecd8cf, 0xce39576c,\n  0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,\n    0x75e31086, 0xce2230d0,\n  0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,\n    0x75d943b0, 0xce0b0c21,\n  0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,\n    0x75cf7250, 0xcdf3e95f,\n  0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,\n    0x75c59c65, 0xcddcc88b,\n  0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,\n    0x75bbc1ef, 0xcdc5a9a6,\n  0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,\n    0x75b1e2f0, 0xcdae8cb1,\n  0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,\n    0x75a7ff67, 0xcd9771ac,\n  0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,\n    0x759e1755, 0xcd805899,\n  0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,\n    0x75942ab9, 0xcd694178,\n  0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,\n    0x758a3996, 0xcd522c4a,\n  0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,\n    0x758043ea, 0xcd3b1911,\n  0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,\n    0x757649b7, 0xcd2407cc,\n  0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,\n    0x756c4afc, 0xcd0cf87e,\n  0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,\n    0x756247bb, 0xccf5eb26,\n  0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,\n    0x75583ff3, 0xccdedfc7,\n  0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,\n    0x754e33a4, 0xccc7d65f,\n  0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,\n    0x754422d0, 0xccb0cef2,\n  0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,\n    0x753a0d77, 0xcc99c97e,\n  0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,\n    0x752ff399, 0xcc82c607,\n  0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,\n    0x7525d536, 0xcc6bc48b,\n  0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,\n    0x751bb24f, 0xcc54c50c,\n  0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,\n    0x75118ae4, 0xcc3dc78b,\n  0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,\n    0x75075ef5, 0xcc26cc09,\n  0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,\n    0x74fd2e84, 0xcc0fd287,\n  0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,\n    0x74f2f990, 0xcbf8db05,\n  0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,\n    0x74e8c01a, 0xcbe1e585,\n  0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,\n    0x74de8221, 0xcbcaf208,\n  0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,\n    0x74d43fa8, 0xcbb4008d,\n  0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,\n    0x74c9f8ad, 0xcb9d1117,\n  0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,\n    0x74bfad32, 0xcb8623a5,\n  0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,\n    0x74b55d36, 0xcb6f383a,\n  0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,\n    0x74ab08bb, 0xcb584ed6,\n  0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,\n    0x74a0afc0, 0xcb416779,\n  0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,\n    0x74965246, 0xcb2a8224,\n  0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,\n    0x748bf04d, 0xcb139ed9,\n  0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,\n    0x748189d7, 0xcafcbd99,\n  0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,\n    0x74771ee2, 0xcae5de64,\n  0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,\n    0x746caf70, 0xcacf013a,\n  0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,\n    0x74623b80, 0xcab8261e,\n  0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,\n    0x7457c314, 0xcaa14d10,\n  0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,\n    0x744d462c, 0xca8a7610,\n  0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,\n    0x7442c4c8, 0xca73a120,\n  0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,\n    0x74383ee9, 0xca5cce40,\n  0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,\n    0x742db48e, 0xca45fd72,\n  0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,\n    0x742325b9, 0xca2f2eb6,\n  0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,\n    0x74189269, 0xca18620e,\n  0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,\n    0x740dfaa0, 0xca019779,\n  0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,\n    0x74035e5d, 0xc9eacef9,\n  0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,\n    0x73f8bda2, 0xc9d4088f,\n  0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,\n    0x73ee186e, 0xc9bd443c,\n  0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,\n    0x73e36ec1, 0xc9a68200,\n  0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,\n    0x73d8c09d, 0xc98fc1dc,\n  0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,\n    0x73ce0e01, 0xc97903d2,\n  0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,\n    0x73c356ef, 0xc96247e2,\n  0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,\n    0x73b89b66, 0xc94b8e0d,\n  0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,\n    0x73addb67, 0xc934d654,\n  0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,\n    0x73a316f2, 0xc91e20b8,\n  0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,\n    0x73984e07, 0xc9076d39,\n  0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,\n    0x738d80a8, 0xc8f0bbd9,\n  0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,\n    0x7382aed5, 0xc8da0c99,\n  0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,\n    0x7377d88d, 0xc8c35f78,\n  0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,\n    0x736cfdd2, 0xc8acb479,\n  0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,\n    0x73621ea4, 0xc8960b9c,\n  0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,\n    0x73573b03, 0xc87f64e2,\n  0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,\n    0x734c52ef, 0xc868c04b,\n  0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,\n    0x7341666a, 0xc8521dd9,\n  0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,\n    0x73367572, 0xc83b7d8d,\n  0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,\n    0x732b800a, 0xc824df67,\n  0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,\n    0x73208632, 0xc80e4369,\n  0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,\n    0x731587e8, 0xc7f7a992,\n  0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,\n    0x730a8530, 0xc7e111e5,\n  0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,\n    0x72ff7e07, 0xc7ca7c61,\n  0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,\n    0x72f47270, 0xc7b3e909,\n  0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,\n    0x72e9626a, 0xc79d57db,\n  0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,\n    0x72de4df6, 0xc786c8db,\n  0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,\n    0x72d33514, 0xc7703c08,\n  0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,\n    0x72c817c6, 0xc759b163,\n  0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,\n    0x72bcf60a, 0xc74328ed,\n  0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,\n    0x72b1cfe1, 0xc72ca2a7,\n  0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,\n    0x72a6a54d, 0xc7161e92,\n  0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,\n    0x729b764d, 0xc6ff9cae,\n  0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,\n    0x729042e3, 0xc6e91cfd,\n  0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,\n    0x72850b0d, 0xc6d29f80,\n  0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,\n    0x7279cecd, 0xc6bc2437,\n  0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,\n    0x726e8e23, 0xc6a5ab23,\n  0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,\n    0x72634910, 0xc68f3446,\n  0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,\n    0x7257ff94, 0xc678bf9f,\n  0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,\n    0x724cb1b0, 0xc6624d30,\n  0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,\n    0x72415f63, 0xc64bdcf9,\n  0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,\n    0x723608af, 0xc6356efc,\n  0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,\n    0x722aad93, 0xc61f033a,\n  0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,\n    0x721f4e11, 0xc60899b2,\n  0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,\n    0x7213ea28, 0xc5f23267,\n  0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,\n    0x720881d9, 0xc5dbcd59,\n  0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,\n    0x71fd1525, 0xc5c56a89,\n  0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,\n    0x71f1a40c, 0xc5af09f7,\n  0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,\n    0x71e62e8f, 0xc598aba5,\n  0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,\n    0x71dab4ad, 0xc5824f93,\n  0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,\n    0x71cf3667, 0xc56bf5c2,\n  0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,\n    0x71c3b3bf, 0xc5559e34,\n  0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,\n    0x71b82cb3, 0xc53f48e9,\n  0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,\n    0x71aca145, 0xc528f5e1,\n  0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,\n    0x71a11175, 0xc512a51f,\n  0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,\n    0x71957d44, 0xc4fc56a2,\n  0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,\n    0x7189e4b2, 0xc4e60a6b,\n  0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,\n    0x717e47bf, 0xc4cfc07c,\n  0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,\n    0x7172a66c, 0xc4b978d4,\n  0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,\n    0x716700b9, 0xc4a33376,\n  0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,\n    0x715b56a7, 0xc48cf062,\n  0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,\n    0x714fa836, 0xc476af98,\n  0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,\n    0x7143f567, 0xc460711b,\n  0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,\n    0x71383e3a, 0xc44a34e9,\n  0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,\n    0x712c82b0, 0xc433fb05,\n  0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,\n    0x7120c2c8, 0xc41dc36f,\n  0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,\n    0x7114fe84, 0xc4078e28,\n  0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,\n    0x710935e4, 0xc3f15b31,\n  0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,\n    0x70fd68e9, 0xc3db2a8b,\n  0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,\n    0x70f19792, 0xc3c4fc36,\n  0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,\n    0x70e5c1e1, 0xc3aed034,\n  0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,\n    0x70d9e7d5, 0xc398a685,\n  0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,\n    0x70ce096f, 0xc3827f2a,\n  0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,\n    0x70c226b0, 0xc36c5a24,\n  0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,\n    0x70b63f99, 0xc3563774,\n  0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,\n    0x70aa5428, 0xc340171b,\n  0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,\n    0x709e6460, 0xc329f919,\n  0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,\n    0x70927041, 0xc313dd70,\n  0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,\n    0x708677ca, 0xc2fdc420,\n  0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,\n    0x707a7afd, 0xc2e7ad2a,\n  0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,\n    0x706e79d9, 0xc2d1988f,\n  0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,\n    0x70627460, 0xc2bb8650,\n  0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,\n    0x70566a92, 0xc2a5766e,\n  0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,\n    0x704a5c6f, 0xc28f68e9,\n  0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,\n    0x703e49f8, 0xc2795dc3,\n  0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,\n    0x7032332d, 0xc26354fc,\n  0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,\n    0x7026180e, 0xc24d4e95,\n  0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,\n    0x7019f89d, 0xc2374a8f,\n  0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,\n    0x700dd4da, 0xc22148ea,\n  0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,\n    0x7001acc4, 0xc20b49a9,\n  0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,\n    0x6ff5805d, 0xc1f54cca,\n  0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,\n    0x6fe94fa5, 0xc1df5251,\n  0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,\n    0x6fdd1a9c, 0xc1c95a3c,\n  0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,\n    0x6fd0e144, 0xc1b3648d,\n  0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,\n    0x6fc4a39c, 0xc19d7145,\n  0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,\n    0x6fb861a4, 0xc1878065,\n  0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,\n    0x6fac1b5f, 0xc17191ee,\n  0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,\n    0x6f9fd0cb, 0xc15ba5df,\n  0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,\n    0x6f9381e9, 0xc145bc3c,\n  0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,\n    0x6f872eba, 0xc12fd503,\n  0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,\n    0x6f7ad73e, 0xc119f036,\n  0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,\n    0x6f6e7b76, 0xc1040dd6,\n  0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,\n    0x6f621b62, 0xc0ee2de3,\n  0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,\n    0x6f55b703, 0xc0d8505f,\n  0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,\n    0x6f494e5a, 0xc0c2754b,\n  0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,\n    0x6f3ce165, 0xc0ac9ca6,\n  0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,\n    0x6f307027, 0xc096c673,\n  0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,\n    0x6f23faa0, 0xc080f2b1,\n  0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,\n    0x6f1780cf, 0xc06b2162,\n  0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,\n    0x6f0b02b6, 0xc0555287,\n  0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,\n    0x6efe8056, 0xc03f8620,\n  0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,\n    0x6ef1f9ad, 0xc029bc2e,\n  0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,\n    0x6ee56ebe, 0xc013f4b2,\n  0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,\n    0x6ed8df88, 0xbffe2fad,\n  0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,\n    0x6ecc4c0d, 0xbfe86d20,\n  0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,\n    0x6ebfb44b, 0xbfd2ad0b,\n  0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,\n    0x6eb31845, 0xbfbcef70,\n  0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,\n    0x6ea677fa, 0xbfa7344f,\n  0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,\n    0x6e99d36b, 0xbf917ba9,\n  0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,\n    0x6e8d2a99, 0xbf7bc57f,\n  0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,\n    0x6e807d83, 0xbf6611d2,\n  0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,\n    0x6e73cc2b, 0xbf5060a2,\n  0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,\n    0x6e671690, 0xbf3ab1f1,\n  0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,\n    0x6e5a5cb4, 0xbf2505bf,\n  0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,\n    0x6e4d9e97, 0xbf0f5c0d,\n  0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,\n    0x6e40dc39, 0xbef9b4dc,\n  0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,\n    0x6e34159b, 0xbee4102d,\n  0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,\n    0x6e274abe, 0xbece6e00,\n  0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,\n    0x6e1a7ba1, 0xbeb8ce57,\n  0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,\n    0x6e0da845, 0xbea33132,\n  0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,\n    0x6e00d0ac, 0xbe8d9692,\n  0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,\n    0x6df3f4d4, 0xbe77fe78,\n  0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,\n    0x6de714c0, 0xbe6268e5,\n  0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,\n    0x6dda306f, 0xbe4cd5da,\n  0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,\n    0x6dcd47e1, 0xbe374557,\n  0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,\n    0x6dc05b18, 0xbe21b75d,\n  0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,\n    0x6db36a14, 0xbe0c2bed,\n  0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,\n    0x6da674d5, 0xbdf6a309,\n  0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,\n    0x6d997b5b, 0xbde11cb0,\n  0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,\n    0x6d8c7da8, 0xbdcb98e3,\n  0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,\n    0x6d7f7bbc, 0xbdb617a4,\n  0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,\n    0x6d727597, 0xbda098f3,\n  0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,\n    0x6d656b3a, 0xbd8b1cd2,\n  0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,\n    0x6d585ca6, 0xbd75a340,\n  0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,\n    0x6d4b49da, 0xbd602c3f,\n  0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,\n    0x6d3e32d7, 0xbd4ab7cf,\n  0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,\n    0x6d31179e, 0xbd3545f2,\n  0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,\n    0x6d23f830, 0xbd1fd6a8,\n  0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,\n    0x6d16d48c, 0xbd0a69f2,\n  0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,\n    0x6d09acb4, 0xbcf4ffd1,\n  0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,\n    0x6cfc80a7, 0xbcdf9846,\n  0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,\n    0x6cef5067, 0xbcca3351,\n  0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,\n    0x6ce21bf4, 0xbcb4d0f4,\n  0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,\n    0x6cd4e34e, 0xbc9f712e,\n  0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,\n    0x6cc7a676, 0xbc8a1402,\n  0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,\n    0x6cba656c, 0xbc74b96f,\n  0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,\n    0x6cad2031, 0xbc5f6177,\n  0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,\n    0x6c9fd6c6, 0xbc4a0c1b,\n  0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,\n    0x6c92892a, 0xbc34b95b,\n  0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,\n    0x6c85375f, 0xbc1f6938,\n  0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,\n    0x6c77e165, 0xbc0a1bb3,\n  0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,\n    0x6c6a873d, 0xbbf4d0cc,\n  0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,\n    0x6c5d28e6, 0xbbdf8885,\n  0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,\n    0x6c4fc662, 0xbbca42df,\n  0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,\n    0x6c425fb1, 0xbbb4ffda,\n  0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,\n    0x6c34f4d3, 0xbb9fbf77,\n  0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,\n    0x6c2785ca, 0xbb8a81b6,\n  0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,\n    0x6c1a1295, 0xbb754699,\n  0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,\n    0x6c0c9b35, 0xbb600e21,\n  0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,\n    0x6bff1faa, 0xbb4ad84e,\n  0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,\n    0x6bf19ff6, 0xbb35a521,\n  0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,\n    0x6be41c18, 0xbb20749c,\n  0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,\n    0x6bd69412, 0xbb0b46bd,\n  0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,\n    0x6bc907e3, 0xbaf61b88,\n  0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,\n    0x6bbb778d, 0xbae0f2fc,\n  0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,\n    0x6bade30f, 0xbacbcd1a,\n  0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,\n    0x6ba04a6a, 0xbab6a9e3,\n  0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,\n    0x6b92ada0, 0xbaa18958,\n  0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,\n    0x6b850caf, 0xba8c6b79,\n  0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,\n    0x6b776799, 0xba775048,\n  0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,\n    0x6b69be5f, 0xba6237c5,\n  0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,\n    0x6b5c1101, 0xba4d21f2,\n  0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,\n    0x6b4e5f7f, 0xba380ece,\n  0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,\n    0x6b40a9d9, 0xba22fe5b,\n  0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,\n    0x6b32f012, 0xba0df099,\n  0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,\n    0x6b253228, 0xb9f8e58a,\n  0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,\n    0x6b17701d, 0xb9e3dd2e,\n  0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,\n    0x6b09a9f1, 0xb9ced786,\n  0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,\n    0x6afbdfa4, 0xb9b9d493,\n  0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,\n    0x6aee1138, 0xb9a4d455,\n  0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,\n    0x6ae03eac, 0xb98fd6cd,\n  0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,\n    0x6ad26802, 0xb97adbfd,\n  0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,\n    0x6ac48d39, 0xb965e3e5,\n  0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,\n    0x6ab6ae52, 0xb950ee86,\n  0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,\n    0x6aa8cb4e, 0xb93bfbe0,\n  0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,\n    0x6a9ae42e, 0xb9270bf5,\n  0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,\n    0x6a8cf8f1, 0xb9121ec5,\n  0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,\n    0x6a7f0999, 0xb8fd3451,\n  0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,\n    0x6a711625, 0xb8e84c99,\n  0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,\n    0x6a631e97, 0xb8d367a0,\n  0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,\n    0x6a5522ef, 0xb8be8565,\n  0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,\n    0x6a47232e, 0xb8a9a5e9,\n  0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,\n    0x6a391f54, 0xb894c92d,\n  0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,\n    0x6a2b1761, 0xb87fef33,\n  0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,\n    0x6a1d0b57, 0xb86b17f9,\n  0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,\n    0x6a0efb35, 0xb8564383,\n  0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,\n    0x6a00e6fc, 0xb84171cf,\n  0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,\n    0x69f2cead, 0xb82ca2e0,\n  0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,\n    0x69e4b249, 0xb817d6b6,\n  0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,\n    0x69d691cf, 0xb8030d51,\n  0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,\n    0x69c86d41, 0xb7ee46b3,\n  0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,\n    0x69ba449f, 0xb7d982dc,\n  0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,\n    0x69ac17e9, 0xb7c4c1cd,\n  0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,\n    0x699de721, 0xb7b00387,\n  0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,\n    0x698fb246, 0xb79b480b,\n  0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,\n    0x69817959, 0xb7868f59,\n  0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,\n    0x69733c5b, 0xb771d972,\n  0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,\n    0x6964fb4c, 0xb75d2658,\n  0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,\n    0x6956b62d, 0xb748760b,\n  0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,\n    0x69486cfe, 0xb733c88b,\n  0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,\n    0x693a1fc0, 0xb71f1dd9,\n  0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,\n    0x692bce73, 0xb70a75f7,\n  0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,\n    0x691d7919, 0xb6f5d0e5,\n  0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,\n    0x690f1fb1, 0xb6e12ea4,\n  0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,\n    0x6900c23c, 0xb6cc8f35,\n  0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,\n    0x68f260bb, 0xb6b7f298,\n  0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,\n    0x68e3fb2e, 0xb6a358ce,\n  0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,\n    0x68d59196, 0xb68ec1d9,\n  0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,\n    0x68c723f3, 0xb67a2db8,\n  0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,\n    0x68b8b247, 0xb6659c6d,\n  0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,\n    0x68aa3c90, 0xb6510df8,\n  0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,\n    0x689bc2d1, 0xb63c825b,\n  0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,\n    0x688d4509, 0xb627f995,\n  0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,\n    0x687ec339, 0xb61373a9,\n  0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,\n    0x68703d62, 0xb5fef095,\n  0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,\n    0x6861b384, 0xb5ea705d,\n  0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,\n    0x685325a0, 0xb5d5f2ff,\n  0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,\n    0x684493b6, 0xb5c1787e,\n  0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,\n    0x6835fdc7, 0xb5ad00d9,\n  0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,\n    0x682763d4, 0xb5988c12,\n  0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,\n    0x6818c5dd, 0xb5841a29,\n  0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,\n    0x680a23e2, 0xb56fab1f,\n  0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,\n    0x67fb7de5, 0xb55b3ef5,\n  0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,\n    0x67ecd3e5, 0xb546d5ac,\n  0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,\n    0x67de25e3, 0xb5326f45,\n  0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,\n    0x67cf73e1, 0xb51e0bbf,\n  0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,\n    0x67c0bddd, 0xb509ab1d,\n  0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,\n    0x67b203da, 0xb4f54d5f,\n  0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,\n    0x67a345d8, 0xb4e0f285,\n  0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,\n    0x679483d6, 0xb4cc9a90,\n  0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,\n    0x6785bdd6, 0xb4b84582,\n  0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,\n    0x6776f3d9, 0xb4a3f35b,\n  0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,\n    0x676825de, 0xb48fa41c,\n  0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,\n    0x675953e7, 0xb47b57c5,\n  0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,\n    0x674a7df4, 0xb4670e57,\n  0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,\n    0x673ba405, 0xb452c7d4,\n  0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,\n    0x672cc61c, 0xb43e843b,\n  0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,\n    0x671de438, 0xb42a438e,\n  0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,\n    0x670efe5a, 0xb41605ce,\n  0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,\n    0x67001483, 0xb401cafb,\n  0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,\n    0x66f126b4, 0xb3ed9316,\n  0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,\n    0x66e234ed, 0xb3d95e1f,\n  0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,\n    0x66d33f2e, 0xb3c52c19,\n  0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,\n    0x66c44579, 0xb3b0fd02,\n  0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,\n    0x66b547cd, 0xb39cd0dd,\n  0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,\n    0x66a6462b, 0xb388a7aa,\n  0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,\n    0x66974095, 0xb3748169,\n  0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,\n    0x66883709, 0xb3605e1c,\n  0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,\n    0x6679298a, 0xb34c3dc3,\n  0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,\n    0x666a1818, 0xb338205f,\n  0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,\n    0x665b02b3, 0xb32405f1,\n  0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,\n    0x664be95b, 0xb30fee79,\n  0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,\n    0x663ccc12, 0xb2fbd9f9,\n  0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,\n    0x662daad8, 0xb2e7c871,\n  0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,\n    0x661e85ad, 0xb2d3b9e2,\n  0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,\n    0x660f5c93, 0xb2bfae4c,\n  0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,\n    0x66002f89, 0xb2aba5b1,\n  0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,\n    0x65f0fe91, 0xb297a011,\n  0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,\n    0x65e1c9aa, 0xb2839d6d,\n  0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,\n    0x65d290d6, 0xb26f9dc6,\n  0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,\n    0x65c35415, 0xb25ba11d,\n  0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,\n    0x65b41367, 0xb247a771,\n  0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,\n    0x65a4cece, 0xb233b0c5,\n  0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,\n    0x6595864a, 0xb21fbd19,\n  0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,\n    0x658639db, 0xb20bcc6d,\n  0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,\n    0x6576e982, 0xb1f7dec2,\n  0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,\n    0x6567953f, 0xb1e3f41a,\n  0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,\n    0x65583d14, 0xb1d00c75,\n  0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,\n    0x6548e101, 0xb1bc27d3,\n  0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,\n    0x65398105, 0xb1a84636,\n  0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,\n    0x652a1d23, 0xb194679e,\n  0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,\n    0x651ab55b, 0xb1808c0c,\n  0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,\n    0x650b49ac, 0xb16cb380,\n  0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,\n    0x64fbda18, 0xb158ddfd,\n  0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,\n    0x64ec66a0, 0xb1450b81,\n  0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,\n    0x64dcef44, 0xb1313c0e,\n  0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,\n    0x64cd7404, 0xb11d6fa6,\n  0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,\n    0x64bdf4e1, 0xb109a648,\n  0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,\n    0x64ae71dc, 0xb0f5dff5,\n  0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,\n    0x649eeaf5, 0xb0e21cae,\n  0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,\n    0x648f602d, 0xb0ce5c74,\n  0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,\n    0x647fd185, 0xb0ba9f48,\n  0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,\n    0x64703efc, 0xb0a6e52a,\n  0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,\n    0x6460a895, 0xb0932e1b,\n  0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,\n    0x64510e4e, 0xb07f7a1c,\n  0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,\n    0x6441702a, 0xb06bc92e,\n  0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,\n    0x6431ce28, 0xb0581b51,\n  0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,\n    0x6422284a, 0xb0447087,\n  0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,\n    0x64127e8f, 0xb030c8cf,\n  0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,\n    0x6402d0f8, 0xb01d242b,\n  0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,\n    0x63f31f86, 0xb009829c,\n  0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,\n    0x63e36a3a, 0xaff5e421,\n  0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,\n    0x63d3b114, 0xafe248bd,\n  0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,\n    0x63c3f415, 0xafceb06f,\n  0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,\n    0x63b4333d, 0xafbb1b39,\n  0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,\n    0x63a46e8d, 0xafa7891b,\n  0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,\n    0x6394a606, 0xaf93fa16,\n  0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,\n    0x6384d9a7, 0xaf806e2b,\n  0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,\n    0x63750973, 0xaf6ce55a,\n  0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,\n    0x63653569, 0xaf595fa4,\n  0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,\n    0x63555d8a, 0xaf45dd0b,\n  0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,\n    0x634581d6, 0xaf325d8e,\n  0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,\n    0x6335a24f, 0xaf1ee12e,\n  0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,\n    0x6325bef5, 0xaf0b67ed,\n  0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,\n    0x6315d7c8, 0xaef7f1cb,\n  0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,\n    0x6305ecc9, 0xaee47ec9,\n  0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,\n    0x62f5fdf9, 0xaed10ee7,\n  0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,\n    0x62e60b58, 0xaebda227,\n  0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,\n    0x62d614e7, 0xaeaa3888,\n  0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,\n    0x62c61aa7, 0xae96d20c,\n  0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,\n    0x62b61c98, 0xae836eb4,\n  0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,\n    0x62a61aba, 0xae700e80,\n  0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,\n    0x6296150f, 0xae5cb171,\n  0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,\n    0x62860b97, 0xae495787,\n  0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,\n    0x6275fe52, 0xae3600c4,\n  0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,\n    0x6265ed42, 0xae22ad29,\n  0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,\n    0x6255d866, 0xae0f5cb5,\n  0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,\n    0x6245bfc0, 0xadfc0f6a,\n  0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,\n    0x6235a351, 0xade8c548,\n  0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,\n    0x62258317, 0xadd57e51,\n  0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,\n    0x62155f16, 0xadc23a85,\n  0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,\n    0x6205374c, 0xadaef9e4,\n  0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,\n    0x61f50bba, 0xad9bbc70,\n  0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,\n    0x61e4dc62, 0xad888229,\n  0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,\n    0x61d4a944, 0xad754b0f,\n  0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,\n    0x61c47260, 0xad621725,\n  0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,\n    0x61b437b7, 0xad4ee66a,\n  0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,\n    0x61a3f94a, 0xad3bb8df,\n  0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,\n    0x6193b719, 0xad288e85,\n  0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,\n    0x61837126, 0xad15675c,\n  0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,\n    0x61732770, 0xad024366,\n  0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,\n    0x6162d9f8, 0xacef22a3,\n  0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,\n    0x615288be, 0xacdc0514,\n  0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,\n    0x614233c5, 0xacc8eab9,\n  0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,\n    0x6131db0b, 0xacb5d394,\n  0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,\n    0x61217e92, 0xaca2bfa4,\n  0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,\n    0x61111e5b, 0xac8faeec,\n  0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,\n    0x6100ba65, 0xac7ca16b,\n  0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,\n    0x60f052b2, 0xac699722,\n  0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,\n    0x60dfe743, 0xac569012,\n  0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,\n    0x60cf7817, 0xac438c3c,\n  0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,\n    0x60bf0530, 0xac308ba0,\n  0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,\n    0x60ae8e8d, 0xac1d8e40,\n  0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,\n    0x609e1431, 0xac0a941b,\n  0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,\n    0x608d961b, 0xabf79d33,\n  0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,\n    0x607d144c, 0xabe4a988,\n  0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,\n    0x606c8ec5, 0xabd1b91c,\n  0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,\n    0x605c0587, 0xabbecbee,\n  0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,\n    0x604b7891, 0xababe200,\n  0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,\n    0x603ae7e5, 0xab98fb52,\n  0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,\n    0x602a5383, 0xab8617e6,\n  0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,\n    0x6019bb6b, 0xab7337bb,\n  0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,\n    0x60091fa0, 0xab605ad2,\n  0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,\n    0x5ff88021, 0xab4d812d,\n  0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,\n    0x5fe7dcee, 0xab3aaacb,\n  0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,\n    0x5fd73609, 0xab27d7ae,\n  0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,\n    0x5fc68b72, 0xab1507d7,\n  0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,\n    0x5fb5dd29, 0xab023b46,\n  0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,\n    0x5fa52b31, 0xaaef71fb,\n  0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,\n    0x5f947588, 0xaadcabf8,\n  0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,\n    0x5f83bc2f, 0xaac9e93e,\n  0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,\n    0x5f72ff28, 0xaab729cc,\n  0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,\n    0x5f623e73, 0xaaa46da4,\n  0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,\n    0x5f517a11, 0xaa91b4c7,\n  0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,\n    0x5f40b202, 0xaa7eff34,\n  0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,\n    0x5f2fe647, 0xaa6c4cee,\n  0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,\n    0x5f1f16e0, 0xaa599df4,\n  0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,\n    0x5f0e43ce, 0xaa46f248,\n  0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,\n    0x5efd6d13, 0xaa3449e9,\n  0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,\n    0x5eec92ae, 0xaa21a4d9,\n  0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,\n    0x5edbb49f, 0xaa0f0319,\n  0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,\n    0x5ecad2e9, 0xa9fc64a9,\n  0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,\n    0x5eb9ed8b, 0xa9e9c98a,\n  0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,\n    0x5ea90487, 0xa9d731bd,\n  0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,\n    0x5e9817dc, 0xa9c49d42,\n  0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,\n    0x5e87278b, 0xa9b20c1a,\n  0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,\n    0x5e763395, 0xa99f7e46,\n  0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,\n    0x5e653bfc, 0xa98cf3c6,\n  0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,\n    0x5e5440be, 0xa97a6c9c,\n  0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,\n    0x5e4341de, 0xa967e8c7,\n  0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,\n    0x5e323f5b, 0xa9556849,\n  0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,\n    0x5e213936, 0xa942eb23,\n  0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,\n    0x5e102f71, 0xa9307155,\n  0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,\n    0x5dff220b, 0xa91dfadf,\n  0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,\n    0x5dee1105, 0xa90b87c3,\n  0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,\n    0x5ddcfc61, 0xa8f91801,\n  0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,\n    0x5dcbe41d, 0xa8e6ab9a,\n  0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,\n    0x5dbac83d, 0xa8d4428f,\n  0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,\n    0x5da9a8bf, 0xa8c1dce0,\n  0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,\n    0x5d9885a5, 0xa8af7a8e,\n  0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,\n    0x5d875eef, 0xa89d1b99,\n  0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,\n    0x5d76349d, 0xa88ac004,\n  0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,\n    0x5d6506b2, 0xa87867cd,\n  0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,\n    0x5d53d52d, 0xa86612f6,\n  0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,\n    0x5d42a00e, 0xa853c180,\n  0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,\n    0x5d316757, 0xa841736c,\n  0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,\n    0x5d202b09, 0xa82f28b9,\n  0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,\n    0x5d0eeb23, 0xa81ce169,\n  0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,\n    0x5cfda7a7, 0xa80a9d7c,\n  0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,\n    0x5cec6095, 0xa7f85cf3,\n  0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,\n    0x5cdb15ed, 0xa7e61fd0,\n  0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,\n    0x5cc9c7b2, 0xa7d3e611,\n  0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,\n    0x5cb875e3, 0xa7c1afb9,\n  0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,\n    0x5ca72080, 0xa7af7cc8,\n  0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,\n    0x5c95c78b, 0xa79d4d3f,\n  0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,\n    0x5c846b05, 0xa78b211e,\n  0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,\n    0x5c730aed, 0xa778f866,\n  0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,\n    0x5c61a745, 0xa766d317,\n  0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,\n    0x5c50400d, 0xa754b134,\n  0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,\n    0x5c3ed545, 0xa74292bb,\n  0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,\n    0x5c2d66f0, 0xa73077ae,\n  0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,\n    0x5c1bf50d, 0xa71e600d,\n  0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,\n    0x5c0a7f9c, 0xa70c4bda,\n  0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,\n    0x5bf906a0, 0xa6fa3b15,\n  0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,\n    0x5be78a17, 0xa6e82dbe,\n  0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,\n    0x5bd60a03, 0xa6d623d7,\n  0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,\n    0x5bc48666, 0xa6c41d60,\n  0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,\n    0x5bb2ff3e, 0xa6b21a59,\n  0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,\n    0x5ba1748d, 0xa6a01ac4,\n  0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,\n    0x5b8fe654, 0xa68e1ea1,\n  0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,\n    0x5b7e5493, 0xa67c25f0,\n  0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,\n    0x5b6cbf4c, 0xa66a30b3,\n  0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,\n    0x5b5b267e, 0xa6583eeb,\n  0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,\n    0x5b498a2a, 0xa6465097,\n  0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,\n    0x5b37ea51, 0xa63465b9,\n  0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,\n    0x5b2646f4, 0xa6227e50,\n  0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,\n    0x5b14a014, 0xa6109a5f,\n  0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,\n    0x5b02f5b0, 0xa5feb9e6,\n  0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,\n    0x5af147ca, 0xa5ecdce5,\n  0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,\n    0x5adf9663, 0xa5db035c,\n  0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,\n    0x5acde17b, 0xa5c92d4e,\n  0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,\n    0x5abc2912, 0xa5b75aba,\n  0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,\n    0x5aaa6d2b, 0xa5a58ba1,\n  0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,\n    0x5a98adc4, 0xa593c004,\n  0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,\n    0x5a86eadf, 0xa581f7e3,\n  0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,\n    0x5a75247c, 0xa570333f,\n  0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,\n    0x5a635a9d, 0xa55e7219,\n  0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,\n    0x5a518d42, 0xa54cb472,\n  0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,\n    0x5a3fbc6b, 0xa53afa49,\n  0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,\n    0x5a2de81a, 0xa52943a1,\n  0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,\n    0x5a1c104f, 0xa5179079,\n  0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,\n    0x5a0a350a, 0xa505e0d2,\n  0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,\n    0x59f8564c, 0xa4f434ae,\n  0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,\n    0x59e67417, 0xa4e28c0c,\n  0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,\n    0x59d48e6a, 0xa4d0e6ed,\n  0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,\n    0x59c2a547, 0xa4bf4552,\n  0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,\n    0x59b0b8ae, 0xa4ada73c,\n  0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,\n    0x599ec8a0, 0xa49c0cab,\n  0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,\n    0x598cd51d, 0xa48a75a0,\n  0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,\n    0x597ade26, 0xa478e21b,\n  0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,\n    0x5968e3bc, 0xa467521e,\n  0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,\n    0x5956e5e0, 0xa455c5a9,\n  0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,\n    0x5944e492, 0xa4443cbd,\n  0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,\n    0x5932dfd3, 0xa432b75a,\n  0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,\n    0x5920d7a3, 0xa4213581,\n  0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,\n    0x590ecc04, 0xa40fb733,\n  0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,\n    0x58fcbcf6, 0xa3fe3c71,\n  0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,\n    0x58eaaa7a, 0xa3ecc53a,\n  0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,\n    0x58d89490, 0xa3db5190,\n  0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,\n    0x58c67b39, 0xa3c9e174,\n  0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,\n    0x58b45e76, 0xa3b874e5,\n  0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,\n    0x58a23e48, 0xa3a70be6,\n  0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,\n    0x58901aaf, 0xa395a675,\n  0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,\n    0x587df3ab, 0xa3844495,\n  0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,\n    0x586bc93f, 0xa372e646,\n  0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,\n    0x58599b69, 0xa3618b88,\n  0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,\n    0x58476a2c, 0xa350345c,\n  0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,\n    0x58353587, 0xa33ee0c3,\n  0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,\n    0x5822fd7c, 0xa32d90be,\n  0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,\n    0x5810c20b, 0xa31c444c,\n  0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,\n    0x57fe8335, 0xa30afb70,\n  0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,\n    0x57ec40fa, 0xa2f9b629,\n  0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,\n    0x57d9fb5c, 0xa2e87477,\n  0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,\n    0x57c7b25a, 0xa2d7365d,\n  0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,\n    0x57b565f6, 0xa2c5fbda,\n  0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,\n    0x57a31631, 0xa2b4c4f0,\n  0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,\n    0x5790c30a, 0xa2a3919e,\n  0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,\n    0x577e6c84, 0xa29261e5,\n  0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,\n    0x576c129d, 0xa28135c7,\n  0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,\n    0x5759b558, 0xa2700d43,\n  0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,\n    0x574754b5, 0xa25ee85b,\n  0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,\n    0x5734f0b5, 0xa24dc70f,\n  0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,\n    0x57228957, 0xa23ca95f,\n  0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,\n    0x57101e9e, 0xa22b8f4d,\n  0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,\n    0x56fdb08a, 0xa21a78d9,\n  0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,\n    0x56eb3f1a, 0xa2096604,\n  0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,\n    0x56d8ca51, 0xa1f856ce,\n  0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,\n    0x56c6522f, 0xa1e74b38,\n  0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,\n    0x56b3d6b5, 0xa1d64343,\n  0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,\n    0x56a157e3, 0xa1c53ef0,\n  0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,\n    0x568ed5b9, 0xa1b43e3e,\n  0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,\n    0x567c503a, 0xa1a3412f,\n  0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,\n    0x5669c765, 0xa19247c3,\n  0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,\n    0x56573b3b, 0xa18151fb,\n  0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,\n    0x5644abbc, 0xa1705fd8,\n  0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,\n    0x563218eb, 0xa15f715a,\n  0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,\n    0x561f82c7, 0xa14e8682,\n  0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,\n    0x560ce950, 0xa13d9f51,\n  0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,\n    0x55fa4c89, 0xa12cbbc7,\n  0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,\n    0x55e7ac71, 0xa11bdbe4,\n  0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,\n    0x55d50909, 0xa10affab,\n  0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,\n    0x55c26251, 0xa0fa271a,\n  0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,\n    0x55afb84c, 0xa0e95234,\n  0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,\n    0x559d0af9, 0xa0d880f7,\n  0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,\n    0x558a5a58, 0xa0c7b366,\n  0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,\n    0x5577a66c, 0xa0b6e981,\n  0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,\n    0x5564ef34, 0xa0a62348,\n  0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,\n    0x555234b1, 0xa09560bc,\n  0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,\n    0x553f76e4, 0xa084a1de,\n  0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,\n    0x552cb5ce, 0xa073e6af,\n  0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,\n    0x5519f16f, 0xa0632f2e,\n  0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,\n    0x550729c9, 0xa0527b5d,\n  0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,\n    0x54f45edb, 0xa041cb3c,\n  0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,\n    0x54e190a6, 0xa0311ecd,\n  0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,\n    0x54cebf2c, 0xa020760e,\n  0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,\n    0x54bbea6d, 0xa00fd102,\n  0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,\n    0x54a91269, 0x9fff2fa9,\n  0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,\n    0x54963722, 0x9fee9204,\n  0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,\n    0x54835898, 0x9fddf812,\n  0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,\n    0x547076cc, 0x9fcd61d6,\n  0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,\n    0x545d91bf, 0x9fbccf4f,\n  0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,\n    0x544aa971, 0x9fac407e,\n  0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,\n    0x5437bde3, 0x9f9bb563,\n  0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,\n    0x5424cf16, 0x9f8b2e00,\n  0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,\n    0x5411dd0a, 0x9f7aaa55,\n  0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,\n    0x53fee7c1, 0x9f6a2a63,\n  0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,\n    0x53ebef3a, 0x9f59ae29,\n  0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,\n    0x53d8f378, 0x9f4935aa,\n  0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,\n    0x53c5f479, 0x9f38c0e5,\n  0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,\n    0x53b2f240, 0x9f284fdc,\n  0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,\n    0x539feccd, 0x9f17e28e,\n  0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,\n    0x538ce421, 0x9f0778fd,\n  0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,\n    0x5379d83c, 0x9ef71328,\n  0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,\n    0x5366c91f, 0x9ee6b112,\n  0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,\n    0x5353b6cb, 0x9ed652ba,\n  0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,\n    0x5340a140, 0x9ec5f820,\n  0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,\n    0x532d8880, 0x9eb5a146,\n  0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,\n    0x531a6c8b, 0x9ea54e2d,\n  0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,\n    0x53074d62, 0x9e94fed4,\n  0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,\n    0x52f42b05, 0x9e84b33d,\n  0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,\n    0x52e10576, 0x9e746b68,\n  0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,\n    0x52cddcb5, 0x9e642756,\n  0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,\n    0x52bab0c2, 0x9e53e707,\n  0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,\n    0x52a7819f, 0x9e43aa7c,\n  0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,\n    0x52944f4c, 0x9e3371b5,\n  0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,\n    0x528119ca, 0x9e233cb4,\n  0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,\n    0x526de11a, 0x9e130b79,\n  0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,\n    0x525aa53c, 0x9e02de04,\n  0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,\n    0x52476631, 0x9df2b456,\n  0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,\n    0x523423fb, 0x9de28e70,\n  0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,\n    0x5220de99, 0x9dd26c53,\n  0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,\n    0x520d960c, 0x9dc24dfe,\n  0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,\n    0x51fa4a56, 0x9db23373,\n  0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,\n    0x51e6fb76, 0x9da21cb2,\n  0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,\n    0x51d3a96f, 0x9d9209bd,\n  0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,\n    0x51c0543f, 0x9d81fa92,\n  0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,\n    0x51acfbe9, 0x9d71ef34,\n  0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,\n    0x5199a06d, 0x9d61e7a2,\n  0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,\n    0x518641cb, 0x9d51e3dd,\n  0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,\n    0x5172e005, 0x9d41e3e7,\n  0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,\n    0x515f7b1a, 0x9d31e7bf,\n  0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,\n    0x514c130d, 0x9d21ef66,\n  0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,\n    0x5138a7dd, 0x9d11fadd,\n  0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,\n    0x5125398c, 0x9d020a25,\n  0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,\n    0x5111c81a, 0x9cf21d3d,\n  0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,\n    0x50fe5388, 0x9ce23427,\n  0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,\n    0x50eadbd6, 0x9cd24ee4,\n  0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,\n    0x50d76106, 0x9cc26d73,\n  0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,\n    0x50c3e317, 0x9cb28fd5,\n  0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,\n    0x50b0620c, 0x9ca2b60c,\n  0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,\n    0x509cdde4, 0x9c92e017,\n  0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,\n    0x508956a1, 0x9c830df8,\n  0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,\n    0x5075cc43, 0x9c733faf,\n  0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,\n    0x50623ecb, 0x9c63753c,\n  0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,\n    0x504eae39, 0x9c53aea0,\n  0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,\n    0x503b1a8f, 0x9c43ebdc,\n  0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,\n    0x502783cd, 0x9c342cf0,\n  0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,\n    0x5013e9f4, 0x9c2471de,\n  0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,\n    0x50004d04, 0x9c14baa4,\n  0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,\n    0x4fecacff, 0x9c050745,\n  0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,\n    0x4fd909e5, 0x9bf557c1,\n  0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,\n    0x4fc563b7, 0x9be5ac18,\n  0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,\n    0x4fb1ba76, 0x9bd6044b,\n  0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,\n    0x4f9e0e22, 0x9bc6605b,\n  0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,\n    0x4f8a5ebd, 0x9bb6c048,\n  0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,\n    0x4f76ac46, 0x9ba72413,\n  0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,\n    0x4f62f6bf, 0x9b978bbc,\n  0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,\n    0x4f4f3e29, 0x9b87f744,\n  0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,\n    0x4f3b8284, 0x9b7866ab,\n  0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,\n    0x4f27c3d1, 0x9b68d9f3,\n  0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,\n    0x4f140210, 0x9b59511c,\n  0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,\n    0x4f003d43, 0x9b49cc26,\n  0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,\n    0x4eec756b, 0x9b3a4b11,\n  0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,\n    0x4ed8aa87, 0x9b2acde0,\n  0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,\n    0x4ec4dc99, 0x9b1b5492,\n  0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,\n    0x4eb10ba2, 0x9b0bdf27,\n  0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,\n    0x4e9d37a3, 0x9afc6da1,\n  0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,\n    0x4e89609b, 0x9aed0000,\n  0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,\n    0x4e75868c, 0x9add9644,\n  0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,\n    0x4e61a977, 0x9ace306f,\n  0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,\n    0x4e4dc95c, 0x9abece80,\n  0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,\n    0x4e39e63d, 0x9aaf7079,\n  0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,\n    0x4e260019, 0x9aa01659,\n  0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,\n    0x4e1216f2, 0x9a90c022,\n  0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,\n    0x4dfe2ac9, 0x9a816dd5,\n  0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,\n    0x4dea3b9d, 0x9a721f71,\n  0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,\n    0x4dd64971, 0x9a62d4f7,\n  0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,\n    0x4dc25445, 0x9a538e68,\n  0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,\n    0x4dae5c19, 0x9a444bc5,\n  0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,\n    0x4d9a60ee, 0x9a350d0d,\n  0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,\n    0x4d8662c6, 0x9a25d243,\n  0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,\n    0x4d7261a0, 0x9a169b65,\n  0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,\n    0x4d5e5d7e, 0x9a076875,\n  0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,\n    0x4d4a5661, 0x99f83974,\n  0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,\n    0x4d364c48, 0x99e90e62,\n  0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,\n    0x4d223f36, 0x99d9e73f,\n  0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,\n    0x4d0e2f2a, 0x99cac40d,\n  0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,\n    0x4cfa1c26, 0x99bba4cb,\n  0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,\n    0x4ce6062a, 0x99ac897b,\n  0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,\n    0x4cd1ed37, 0x999d721c,\n  0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,\n    0x4cbdd14e, 0x998e5eb1,\n  0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,\n    0x4ca9b26f, 0x997f4f38,\n  0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,\n    0x4c95909c, 0x997043b2,\n  0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,\n    0x4c816bd5, 0x99613c22,\n  0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,\n    0x4c6d441b, 0x99523885,\n  0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,\n    0x4c59196f, 0x994338df,\n  0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,\n    0x4c44ebd1, 0x99343d2e,\n  0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,\n    0x4c30bb42, 0x99254574,\n  0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,\n    0x4c1c87c3, 0x991651b1,\n  0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,\n    0x4c085156, 0x990761e5,\n  0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,\n    0x4bf417f9, 0x98f87612,\n  0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,\n    0x4bdfdbaf, 0x98e98e38,\n  0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,\n    0x4bcb9c79, 0x98daaa57,\n  0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,\n    0x4bb75a56, 0x98cbca70,\n  0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,\n    0x4ba31548, 0x98bcee84,\n  0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,\n    0x4b8ecd4f, 0x98ae1693,\n  0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,\n    0x4b7a826d, 0x989f429e,\n  0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,\n    0x4b6634a2, 0x989072a5,\n  0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,\n    0x4b51e3ee, 0x9881a6a9,\n  0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,\n    0x4b3d9053, 0x9872deaa,\n  0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,\n    0x4b2939d2, 0x98641aa9,\n  0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,\n    0x4b14e06b, 0x98555aa7,\n  0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,\n    0x4b00841f, 0x98469ea4,\n  0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,\n    0x4aec24ee, 0x9837e6a1,\n  0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,\n    0x4ad7c2da, 0x9829329e,\n  0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,\n    0x4ac35de4, 0x981a829c,\n  0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,\n    0x4aaef60b, 0x980bd69b,\n  0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,\n    0x4a9a8b52, 0x97fd2e9c,\n  0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,\n    0x4a861db8, 0x97ee8aa0,\n  0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,\n    0x4a71ad3e, 0x97dfeaa7,\n  0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,\n    0x4a5d39e6, 0x97d14eb2,\n  0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,\n    0x4a48c3b0, 0x97c2b6c1,\n  0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,\n    0x4a344a9d, 0x97b422d4,\n  0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,\n    0x4a1fcead, 0x97a592ed,\n  0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,\n    0x4a0b4fe2, 0x9797070c,\n  0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,\n    0x49f6ce3c, 0x97887f32,\n  0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,\n    0x49e249bc, 0x9779fb5e,\n  0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,\n    0x49cdc263, 0x976b7b92,\n  0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,\n    0x49b93832, 0x975cffcf,\n  0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,\n    0x49a4ab28, 0x974e8813,\n  0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,\n    0x49901b48, 0x97401462,\n  0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,\n    0x497b8892, 0x9731a4ba,\n  0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,\n    0x4966f307, 0x9723391c,\n  0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,\n    0x49525aa7, 0x9714d18a,\n  0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,\n    0x493dbf74, 0x97066e03,\n  0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,\n    0x4929216e, 0x96f80e88,\n  0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,\n    0x49148095, 0x96e9b319,\n  0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,\n    0x48ffdcec, 0x96db5bb8,\n  0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,\n    0x48eb3672, 0x96cd0865,\n  0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,\n    0x48d68d28, 0x96beb91f,\n  0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,\n    0x48c1e10f, 0x96b06de9,\n  0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,\n    0x48ad3228, 0x96a226c2,\n  0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,\n    0x48988074, 0x9693e3ab,\n  0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,\n    0x4883cbf4, 0x9685a4a4,\n  0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,\n    0x486f14a8, 0x967769af,\n  0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,\n    0x485a5a90, 0x966932cb,\n  0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,\n    0x48459daf, 0x965afff9,\n  0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,\n    0x4830de05, 0x964cd139,\n  0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,\n    0x481c1b92, 0x963ea68d,\n  0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,\n    0x48075657, 0x96307ff5,\n  0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,\n    0x47f28e56, 0x96225d71,\n  0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,\n    0x47ddc38e, 0x96143f02,\n  0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,\n    0x47c8f601, 0x960624a9,\n  0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,\n    0x47b425af, 0x95f80e65,\n  0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,\n    0x479f529a, 0x95e9fc38,\n  0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,\n    0x478a7cc2, 0x95dbee21,\n  0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,\n    0x4775a428, 0x95cde423,\n  0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,\n    0x4760c8cd, 0x95bfde3c,\n  0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,\n    0x474beab1, 0x95b1dc6e,\n  0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,\n    0x473709d5, 0x95a3deb9,\n  0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,\n    0x4722263b, 0x9595e51e,\n  0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,\n    0x470d3fe3, 0x9587ef9e,\n  0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,\n    0x46f856cd, 0x9579fe38,\n  0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,\n    0x46e36afb, 0x956c10ed,\n  0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,\n    0x46ce7c6d, 0x955e27bf,\n  0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,\n    0x46b98b24, 0x955042ac,\n  0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,\n    0x46a49722, 0x954261b7,\n  0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,\n    0x468fa066, 0x953484df,\n  0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,\n    0x467aa6f2, 0x9526ac25,\n  0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,\n    0x4665aac6, 0x9518d78a,\n  0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,\n    0x4650abe3, 0x950b070e,\n  0x464b6bbe, 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0x457e2275, 0x9481c557,\n  0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,\n    0x456905ed, 0x94742254,\n  0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,\n    0x4553e6b8, 0x94668376,\n  0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,\n    0x453ec4d7, 0x9458e8bf,\n  0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,\n    0x4529a04b, 0x944b522d,\n  0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,\n    0x45147913, 0x943dbfc3,\n  0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,\n    0x44ff4f32, 0x94303180,\n  0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,\n    0x44ea22a9, 0x9422a766,\n  0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,\n    0x44d4f376, 0x94152174,\n  0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,\n    0x44bfc19d, 0x94079fab,\n  0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,\n    0x44aa8d1d, 0x93fa220b,\n  0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,\n    0x449555f7, 0x93eca896,\n  0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,\n    0x44801c2d, 0x93df334c,\n  0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,\n    0x446adfbe, 0x93d1c22c,\n  0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,\n    0x4455a0ac, 0x93c45539,\n  0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,\n    0x44405ef8, 0x93b6ec71,\n  0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,\n    0x442b1aa2, 0x93a987d6,\n  0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,\n    0x4415d3ab, 0x939c2769,\n  0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,\n    0x44008a14, 0x938ecb29,\n  0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,\n    0x43eb3ddf, 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0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,\n    0x40a4c716, 0x9185daa1,\n  0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,\n    0x408f14a7, 0x91792b6a,\n  0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,\n    0x40795fbc, 0x916c8076,\n  0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,\n    0x4063a854, 0x915fd9c5,\n  0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,\n    0x404dee70, 0x91533758,\n  0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,\n    0x40383212, 0x9146992f,\n  0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,\n    0x4022733a, 0x9139ff4b,\n  0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,\n    0x400cb1e9, 0x912d69ad,\n  0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,\n    0x3ff6ee1f, 0x9120d854,\n  0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,\n    0x3fe127df, 0x91144b41,\n  0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,\n    0x3fcb5f28, 0x9107c276,\n  0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,\n    0x3fb593fb, 0x90fb3df1,\n  0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,\n    0x3f9fc65a, 0x90eebdb4,\n  0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,\n    0x3f89f645, 0x90e241bf,\n  0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,\n    0x3f7423bc, 0x90d5ca13,\n  0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,\n    0x3f5e4ec2, 0x90c956b1,\n  0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,\n    0x3f487755, 0x90bce797,\n  0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,\n    0x3f329d79, 0x90b07cc8,\n  0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,\n    0x3f1cc12c, 0x90a41644,\n  0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,\n    0x3f06e271, 0x9097b40a,\n  0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,\n    0x3ef10148, 0x908b561c,\n  0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,\n    0x3edb1db1, 0x907efc7a,\n  0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,\n    0x3ec537ae, 0x9072a725,\n  0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,\n    0x3eaf4f40, 0x9066561d,\n  0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,\n    0x3e996467, 0x905a0962,\n  0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,\n    0x3e837724, 0x904dc0f5,\n  0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,\n    0x3e6d8778, 0x90417cd6,\n  0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,\n    0x3e579564, 0x90353d06,\n  0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,\n    0x3e41a0e8, 0x90290186,\n  0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,\n    0x3e2baa07, 0x901cca55,\n  0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,\n    0x3e15b0bf, 0x90109775,\n  0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,\n    0x3dffb513, 0x900468e5,\n  0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,\n    0x3de9b703, 0x8ff83ea7,\n  0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,\n    0x3dd3b690, 0x8fec18ba,\n  0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,\n    0x3dbdb3ba, 0x8fdff720,\n  0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,\n    0x3da7ae84, 0x8fd3d9d8,\n  0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,\n    0x3d91a6ed, 0x8fc7c0e3,\n  0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,\n    0x3d7b9cf6, 0x8fbbac42,\n  0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,\n    0x3d6590a0, 0x8faf9bf5,\n  0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,\n    0x3d4f81ec, 0x8fa38ffc,\n  0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,\n    0x3d3970dc, 0x8f978859,\n  0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,\n    0x3d235d6f, 0x8f8b850a,\n  0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,\n    0x3d0d47a6, 0x8f7f8612,\n  0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,\n    0x3cf72f83, 0x8f738b70,\n  0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,\n    0x3ce11507, 0x8f679525,\n  0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,\n    0x3ccaf831, 0x8f5ba331,\n  0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,\n    0x3cb4d904, 0x8f4fb595,\n  0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,\n    0x3c9eb77f, 0x8f43cc50,\n  0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,\n    0x3c8893a4, 0x8f37e765,\n  0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,\n    0x3c726d73, 0x8f2c06d3,\n  0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,\n    0x3c5c44ee, 0x8f202a9a,\n  0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,\n    0x3c461a16, 0x8f1452bb,\n  0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,\n    0x3c2fecea, 0x8f087f37,\n  0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,\n    0x3c19bd6c, 0x8efcb00e,\n  0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,\n    0x3c038b9e, 0x8ef0e540,\n  0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,\n    0x3bed577e, 0x8ee51ece,\n  0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,\n    0x3bd72110, 0x8ed95cb8,\n  0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,\n    0x3bc0e853, 0x8ecd9eff,\n  0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,\n    0x3baaad48, 0x8ec1e5a4,\n  0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,\n    0x3b946ff0, 0x8eb630a6,\n  0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,\n    0x3b7e304c, 0x8eaa8006,\n  0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,\n    0x3b67ee5d, 0x8e9ed3c4,\n  0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,\n    0x3b51aa24, 0x8e932be2,\n  0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,\n    0x3b3b63a1, 0x8e87885f,\n  0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,\n    0x3b251ad6, 0x8e7be93c,\n  0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,\n    0x3b0ecfc3, 0x8e704e79,\n  0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,\n    0x3af88269, 0x8e64b817,\n  0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,\n    0x3ae232c9, 0x8e592617,\n  0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,\n    0x3acbe0e3, 0x8e4d9878,\n  0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,\n    0x3ab58cba, 0x8e420f3b,\n  0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,\n    0x3a9f364d, 0x8e368a61,\n  0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,\n    0x3a88dd9d, 0x8e2b09e9,\n  0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,\n    0x3a7282ac, 0x8e1f8dd6,\n  0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,\n    0x3a5c257a, 0x8e141626,\n  0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,\n    0x3a45c608, 0x8e08a2db,\n  0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,\n    0x3a2f6457, 0x8dfd33f4,\n  0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,\n    0x3a190068, 0x8df1c973,\n  0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,\n    0x3a029a3b, 0x8de66357,\n  0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,\n    0x39ec31d1, 0x8ddb01a1,\n  0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,\n    0x39d5c72c, 0x8dcfa452,\n  0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,\n    0x39bf5a4d, 0x8dc44b6a,\n  0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,\n    0x39a8eb33, 0x8db8f6ea,\n  0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,\n    0x399279e0, 0x8dada6d1,\n  0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,\n    0x397c0655, 0x8da25b21,\n  0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,\n    0x39659092, 0x8d9713d9,\n  0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,\n    0x394f1899, 0x8d8bd0fb,\n  0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,\n    0x39389e6b, 0x8d809286,\n  0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,\n    0x39222208, 0x8d75587b,\n  0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,\n    0x390ba371, 0x8d6a22db,\n  0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,\n    0x38f522a6, 0x8d5ef1a5,\n  0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,\n    0x38de9faa, 0x8d53c4db,\n  0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,\n    0x38c81a7c, 0x8d489c7d,\n  0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,\n    0x38b1931e, 0x8d3d788b,\n  0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,\n    0x389b0991, 0x8d325905,\n  0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,\n    0x38847dd5, 0x8d273ded,\n  0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,\n    0x386defeb, 0x8d1c2742,\n  0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,\n    0x38575fd4, 0x8d111505,\n  0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,\n    0x3840cd90, 0x8d060737,\n  0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,\n    0x382a3922, 0x8cfafdd7,\n  0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,\n    0x3813a28a, 0x8ceff8e6,\n  0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,\n    0x37fd09c8, 0x8ce4f865,\n  0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,\n    0x37e66edd, 0x8cd9fc54,\n  0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,\n    0x37cfd1cb, 0x8ccf04b3,\n  0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,\n    0x37b93292, 0x8cc41184,\n  0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,\n    0x37a29132, 0x8cb922c6,\n  0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,\n    0x378bedae, 0x8cae3879,\n  0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,\n    0x37754806, 0x8ca3529f,\n  0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,\n    0x375ea03a, 0x8c987137,\n  0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,\n    0x3747f64c, 0x8c8d9442,\n  0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,\n    0x37314a3c, 0x8c82bbc0,\n  0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,\n    0x371a9c0b, 0x8c77e7b3,\n  0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,\n    0x3703ebbb, 0x8c6d181a,\n  0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,\n    0x36ed394b, 0x8c624cf5,\n  0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,\n    0x36d684be, 0x8c578645,\n  0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,\n    0x36bfce13, 0x8c4cc40b,\n  0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,\n    0x36a9154c, 0x8c420647,\n  0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,\n    0x36925a69, 0x8c374cf9,\n  0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,\n    0x367b9d6c, 0x8c2c9822,\n  0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,\n    0x3664de55, 0x8c21e7c2,\n  0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,\n    0x364e1d25, 0x8c173bda,\n  0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,\n    0x363759de, 0x8c0c9469,\n  0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,\n    0x3620947f, 0x8c01f171,\n  0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,\n    0x3609cd0a, 0x8bf752f2,\n  0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,\n    0x35f3037f, 0x8becb8ec,\n  0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 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0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,\n    0x34f7d208, 0x8b79425e,\n  0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,\n    0x34e0efc2, 0x8b6ede26,\n  0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,\n    0x34ca0b73, 0x8b647e6d,\n  0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,\n    0x34b3251a, 0x8b5a2333,\n  0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,\n    0x349c3cb9, 0x8b4fcc77,\n  0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,\n    0x34855251, 0x8b457a3c,\n  0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,\n    0x346e65e3, 0x8b3b2c80,\n  0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,\n    0x3457776f, 0x8b30e345,\n  0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,\n    0x344086f6, 0x8b269e8b,\n  0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,\n    0x3429947a, 0x8b1c5e52,\n  0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,\n    0x34129ffb, 0x8b12229b,\n  0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,\n    0x33fba97a, 0x8b07eb66,\n  0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,\n    0x33e4b0f8, 0x8afdb8b3,\n  0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,\n    0x33cdb676, 0x8af38a83,\n  0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,\n    0x33b6b9f4, 0x8ae960d6,\n  0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,\n    0x339fbb74, 0x8adf3bad,\n  0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,\n    0x3388baf7, 0x8ad51b08,\n  0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,\n    0x3371b87d, 0x8acafee8,\n  0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,\n    0x335ab407, 0x8ac0e74c,\n  0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,\n    0x3343ad97, 0x8ab6d435,\n  0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,\n    0x332ca52c, 0x8aacc5a4,\n  0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,\n    0x33159ac8, 0x8aa2bb99,\n  0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,\n    0x32fe8e6d, 0x8a98b614,\n  0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,\n    0x32e7801a, 0x8a8eb516,\n  0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,\n    0x32d06fd0, 0x8a84b89e,\n  0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,\n    0x32b95d91, 0x8a7ac0af,\n  0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,\n    0x32a2495d, 0x8a70cd47,\n  0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,\n    0x328b3336, 0x8a66de68,\n  0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,\n    0x32741b1c, 0x8a5cf411,\n  0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,\n    0x325d0110, 0x8a530e43,\n  0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,\n    0x3245e512, 0x8a492cff,\n  0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,\n    0x322ec725, 0x8a3f5045,\n  0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,\n    0x3217a748, 0x8a357814,\n  0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,\n    0x3200857d, 0x8a2ba46e,\n  0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,\n    0x31e961c5, 0x8a21d554,\n  0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,\n    0x31d23c1f, 0x8a180ac4,\n  0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,\n    0x31bb148f, 0x8a0e44c0,\n  0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,\n    0x31a3eb13, 0x8a048348,\n  0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,\n    0x318cbfad, 0x89fac65d,\n  0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,\n    0x3175925e, 0x89f10dff,\n  0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,\n    0x315e6328, 0x89e75a2d,\n  0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,\n    0x31473209, 0x89ddaae9,\n  0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,\n    0x312fff05, 0x89d40033,\n  0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,\n    0x3118ca1b, 0x89ca5a0c,\n  0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,\n    0x3101934d, 0x89c0b873,\n  0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,\n    0x30ea5a9a, 0x89b71b69,\n  0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,\n    0x30d32006, 0x89ad82ef,\n  0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,\n    0x30bbe38f, 0x89a3ef04,\n  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0x89477c30,\n    0x2fd32028, 0x89452310,\n  0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,\n    0x2fbbcf38, 0x893bc16b,\n  0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,\n    0x2fa47c71, 0x8932645b,\n  0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,\n    0x2f8d27d3, 0x89290bdf,\n  0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,\n    0x2f75d160, 0x891fb7f8,\n  0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,\n    0x2f5e7919, 0x891668a6,\n  0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,\n    0x2f471efe, 0x890d1dea,\n  0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,\n    0x2f2fc310, 0x8903d7c4,\n  0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,\n    0x2f186551, 0x88fa9634,\n  0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,\n    0x2f0105c1, 0x88f1593b,\n  0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,\n    0x2ee9a461, 0x88e820d9,\n  0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,\n    0x2ed24132, 0x88deed0e,\n  0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,\n    0x2ebadc35, 0x88d5bddb,\n  0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,\n    0x2ea3756b, 0x88cc9340,\n  0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,\n    0x2e8c0cd4, 0x88c36d3e,\n  0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,\n    0x2e74a272, 0x88ba4bd4,\n  0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,\n    0x2e5d3646, 0x88b12f04,\n  0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,\n    0x2e45c850, 0x88a816cd,\n  0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,\n    0x2e2e5891, 0x889f0330,\n  0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,\n    0x2e16e70b, 0x8895f42d,\n  0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,\n    0x2dff73bd, 0x888ce9c5,\n  0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,\n    0x2de7feaa, 0x8883e3f8,\n  0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,\n    0x2dd087d1, 0x887ae2c6,\n  0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,\n    0x2db90f35, 0x8871e630,\n  0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,\n    0x2da194d5, 0x8868ee35,\n  0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,\n    0x2d8a18b3, 0x885ffad7,\n  0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,\n    0x2d729acf, 0x88570c16,\n  0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,\n    0x2d5b1b2b, 0x884e21f1,\n  0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,\n    0x2d4399c7, 0x88453c6a,\n  0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,\n    0x2d2c16a4, 0x883c5b81,\n  0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,\n    0x2d1491c4, 0x88337f35,\n  0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,\n    0x2cfd0b26, 0x882aa788,\n  0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,\n    0x2ce582cd, 0x8821d47a,\n  0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,\n    0x2ccdf8b8, 0x8819060a,\n  0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,\n    0x2cb66ce9, 0x88103c3b,\n  0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,\n    0x2c9edf61, 0x8807770a,\n  0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,\n    0x2c875021, 0x87feb67a,\n  0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,\n    0x2c6fbf29, 0x87f5fa8b,\n  0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,\n    0x2c582c7b, 0x87ed433c,\n  0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,\n    0x2c409816, 0x87e4908e,\n  0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,\n    0x2c2901fd, 0x87dbe281,\n  0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,\n    0x2c116a31, 0x87d33916,\n  0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,\n    0x2bf9d0b1, 0x87ca944e,\n  0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,\n    0x2be2357f, 0x87c1f427,\n  0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,\n    0x2bca989d, 0x87b958a4,\n  0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,\n    0x2bb2fa0a, 0x87b0c1c4,\n  0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,\n    0x2b9b59c7, 0x87a82f87,\n  0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,\n    0x2b83b7d7, 0x879fa1ed,\n  0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,\n    0x2b6c1438, 0x879718f8,\n  0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,\n    0x2b546eee, 0x878e94a7,\n  0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,\n    0x2b3cc7f7, 0x878614fb,\n  0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,\n    0x2b251f56, 0x877d99f4,\n  0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,\n    0x2b0d750b, 0x87752392,\n  0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,\n    0x2af5c917, 0x876cb1d6,\n  0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,\n    0x2ade1b7c, 0x876444c1,\n  0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,\n    0x2ac66c39, 0x875bdc51,\n  0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,\n    0x2aaebb50, 0x87537888,\n  0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,\n    0x2a9708c1, 0x874b1966,\n  0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,\n    0x2a7f548e, 0x8742beec,\n  0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,\n    0x2a679eb8, 0x873a6919,\n  0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,\n    0x2a4fe740, 0x873217ee,\n  0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,\n    0x2a382e25, 0x8729cb6b,\n  0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,\n    0x2a20736a, 0x87218391,\n  0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,\n    0x2a08b710, 0x87194060,\n  0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,\n    0x29f0f916, 0x871101d8,\n  0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,\n    0x29d9397f, 0x8708c7fa,\n  0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,\n    0x29c1784a, 0x870092c5,\n  0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,\n    0x29a9b579, 0x86f8623b,\n  0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,\n    0x2991f10e, 0x86f0365c,\n  0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,\n    0x297a2b07, 0x86e80f27,\n  0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,\n    0x29626368, 0x86dfec9d,\n  0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,\n    0x294a9a30, 0x86d7cebf,\n  0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,\n    0x2932cf60, 0x86cfb58c,\n  0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,\n    0x291b02fa, 0x86c7a106,\n  0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,\n    0x290334ff, 0x86bf912c,\n  0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,\n    0x28eb656e, 0x86b785ff,\n  0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,\n    0x28d3944a, 0x86af7f7e,\n  0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,\n    0x28bbc192, 0x86a77dab,\n  0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,\n    0x28a3ed49, 0x869f8086,\n  0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,\n    0x288c176e, 0x8697880f,\n  0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,\n    0x28744004, 0x868f9445,\n  0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,\n    0x285c670a, 0x8687a52b,\n  0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,\n    0x28448c81, 0x867fbabf,\n  0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,\n    0x282cb06c, 0x8677d503,\n  0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,\n    0x2814d2c9, 0x866ff3f6,\n  0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,\n    0x27fcf39c, 0x86681798,\n  0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,\n    0x27e512e3, 0x86603feb,\n  0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,\n    0x27cd30a1, 0x86586cee,\n  0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,\n    0x27b54cd6, 0x86509ea2,\n  0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,\n    0x279d6783, 0x8648d507,\n  0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,\n    0x278580a9, 0x8641101d,\n  0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,\n    0x276d9849, 0x86394fe5,\n  0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,\n    0x2755ae64, 0x8631945e,\n  0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,\n    0x273dc2fa, 0x8629dd8a,\n  0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,\n    0x2725d60e, 0x86222b68,\n  0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,\n    0x270de79f, 0x861a7df9,\n  0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,\n    0x26f5f7ae, 0x8612d53d,\n  0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,\n    0x26de063d, 0x860b3135,\n  0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,\n    0x26c6134d, 0x860391e0,\n  0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,\n    0x26ae1edd, 0x85fbf73f,\n  0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,\n    0x269628f0, 0x85f46152,\n  0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,\n    0x267e3186, 0x85ecd01a,\n  0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,\n    0x266638a1, 0x85e54397,\n  0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,\n    0x264e3e40, 0x85ddbbc9,\n  0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,\n    0x26364265, 0x85d638b0,\n  0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,\n    0x261e4511, 0x85ceba4d,\n  0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,\n    0x26064645, 0x85c740a0,\n  0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,\n    0x25ee4601, 0x85bfcba9,\n  0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,\n    0x25d64447, 0x85b85b68,\n  0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,\n    0x25be4118, 0x85b0efdf,\n  0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,\n    0x25a63c74, 0x85a9890d,\n  0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,\n    0x258e365d, 0x85a226f2,\n  0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,\n    0x25762ed3, 0x859ac98f,\n  0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,\n    0x255e25d7, 0x859370e4,\n  0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,\n    0x25461b6b, 0x858c1cf1,\n  0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,\n    0x252e0f8e, 0x8584cdb7,\n  0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,\n    0x25160243, 0x857d8335,\n  0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,\n    0x24fdf389, 0x85763d6d,\n  0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,\n    0x24e5e363, 0x856efc5e,\n  0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,\n    0x24cdd1d0, 0x8567c009,\n  0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,\n    0x24b5bed2, 0x8560886d,\n  0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,\n    0x249daa6a, 0x8559558c,\n  0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,\n    0x24859498, 0x85522766,\n  0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,\n    0x246d7d5e, 0x854afdfa,\n  0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,\n    0x245564bd, 0x8543d949,\n  0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,\n    0x243d4ab4, 0x853cb954,\n  0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,\n    0x24252f47, 0x85359e1a,\n  0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,\n    0x240d1274, 0x852e879d,\n  0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,\n    0x23f4f43e, 0x852775db,\n  0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,\n    0x23dcd4a4, 0x852068d6,\n  0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,\n    0x23c4b3a9, 0x8519608d,\n  0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,\n    0x23ac914d, 0x85125d02,\n  0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,\n    0x23946d90, 0x850b5e34,\n  0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,\n    0x237c4875, 0x85046423,\n  0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,\n    0x236421fb, 0x84fd6ed0,\n  0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,\n    0x234bfa24, 0x84f67e3b,\n  0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,\n    0x2333d0f1, 0x84ef9265,\n  0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,\n    0x231ba662, 0x84e8ab4d,\n  0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,\n    0x23037a78, 0x84e1c8f3,\n  0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,\n    0x22eb4d36, 0x84daeb5a,\n  0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,\n    0x22d31e9a, 0x84d4127f,\n  0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,\n    0x22baeea7, 0x84cd3e64,\n  0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,\n    0x22a2bd5d, 0x84c66f09,\n  0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,\n    0x228a8abd, 0x84bfa46e,\n  0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,\n    0x227256c8, 0x84b8de94,\n  0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,\n    0x225a217f, 0x84b21d7a,\n  0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,\n    0x2241eae3, 0x84ab6122,\n  0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,\n    0x2229b2f6, 0x84a4a98a,\n  0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,\n    0x221179b7, 0x849df6b4,\n  0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,\n    0x21f93f27, 0x849748a0,\n  0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,\n    0x21e10349, 0x84909f4e,\n  0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,\n    0x21c8c61c, 0x8489fabe,\n  0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,\n    0x21b087a1, 0x84835af0,\n  0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,\n    0x219847da, 0x847cbfe5,\n  0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,\n    0x218006c8, 0x8476299e,\n  0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,\n    0x2167c46b, 0x846f9819,\n  0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,\n    0x214f80c4, 0x84690b58,\n  0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,\n    0x21373bd4, 0x8462835b,\n  0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,\n    0x211ef59d, 0x845c0022,\n  0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,\n    0x2106ae1e, 0x845581ad,\n  0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,\n    0x20ee655a, 0x844f07fd,\n  0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,\n    0x20d61b51, 0x84489311,\n  0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,\n    0x20bdd003, 0x844222eb,\n  0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,\n    0x20a58373, 0x843bb78a,\n  0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,\n    0x208d35a0, 0x843550ee,\n  0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,\n    0x2074e68c, 0x842eef18,\n  0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,\n    0x205c9638, 0x84289209,\n  0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,\n    0x204444a4, 0x842239bf,\n  0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,\n    0x202bf1d2, 0x841be63c,\n  0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,\n    0x20139dc2, 0x84159780,\n  0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,\n    0x1ffb4876, 0x840f4d8a,\n  0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,\n    0x1fe2f1ee, 0x8409085c,\n  0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,\n    0x1fca9a2b, 0x8402c7f6,\n  0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,\n    0x1fb2412f, 0x83fc8c57,\n  0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,\n    0x1f99e6fa, 0x83f65580,\n  0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,\n    0x1f818b8d, 0x83f02371,\n  0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,\n    0x1f692ee9, 0x83e9f62b,\n  0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,\n    0x1f50d10e, 0x83e3cdad,\n  0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,\n    0x1f3871ff, 0x83dda9f9,\n  0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,\n    0x1f2011bc, 0x83d78b0d,\n  0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,\n    0x1f07b045, 0x83d170eb,\n  0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,\n    0x1eef4d9d, 0x83cb5b93,\n  0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,\n    0x1ed6e9c3, 0x83c54b04,\n  0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,\n    0x1ebe84b8, 0x83bf3f3f,\n  0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,\n    0x1ea61e7e, 0x83b93845,\n  0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,\n    0x1e8db716, 0x83b33616,\n  0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,\n    0x1e754e80, 0x83ad38b1,\n  0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,\n    0x1e5ce4be, 0x83a74017,\n  0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,\n    0x1e4479cf, 0x83a14c48,\n  0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,\n    0x1e2c0db6, 0x839b5d45,\n  0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,\n    0x1e13a074, 0x8395730e,\n  0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,\n    0x1dfb3208, 0x838f8da2,\n  0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,\n    0x1de2c275, 0x8389ad03,\n  0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,\n    0x1dca51ba, 0x8383d130,\n  0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,\n    0x1db1dfda, 0x837dfa2a,\n  0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,\n    0x1d996cd4, 0x837827f0,\n  0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,\n    0x1d80f8ab, 0x83725a84,\n  0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,\n    0x1d68835e, 0x836c91e5,\n  0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,\n    0x1d500cef, 0x8366ce14,\n  0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,\n    0x1d37955e, 0x83610f10,\n  0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,\n    0x1d1f1cae, 0x835b54da,\n  0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,\n    0x1d06a2dd, 0x83559f72,\n  0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,\n    0x1cee27ef, 0x834feed9,\n  0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,\n    0x1cd5abe3, 0x834a430e,\n  0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,\n    0x1cbd2eba, 0x83449c12,\n  0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,\n    0x1ca4b075, 0x833ef9e6,\n  0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,\n    0x1c8c3116, 0x83395c88,\n  0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,\n    0x1c73b09d, 0x8333c3fa,\n  0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,\n    0x1c5b2f0c, 0x832e303c,\n  0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,\n    0x1c42ac62, 0x8328a14d,\n  0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,\n    0x1c2a28a2, 0x8323172f,\n  0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,\n    0x1c11a3cb, 0x831d91e1,\n  0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,\n    0x1bf91de0, 0x83181164,\n  0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,\n    0x1be096e0, 0x831295b7,\n  0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,\n    0x1bc80ece, 0x830d1edc,\n  0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,\n    0x1baf85a9, 0x8307acd1,\n  0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,\n    0x1b96fb73, 0x83023f98,\n  0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,\n    0x1b7e702c, 0x82fcd731,\n  0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,\n    0x1b65e3d7, 0x82f7739c,\n  0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,\n    0x1b4d5672, 0x82f214d8,\n  0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,\n    0x1b34c801, 0x82ecbae7,\n  0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,\n    0x1b1c3883, 0x82e765c8,\n  0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,\n    0x1b03a7f9, 0x82e2157c,\n  0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,\n    0x1aeb1665, 0x82dcca02,\n  0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,\n    0x1ad283c7, 0x82d7835c,\n  0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,\n    0x1ab9f020, 0x82d24189,\n  0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,\n    0x1aa15b71, 0x82cd048a,\n  0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,\n    0x1a88c5bc, 0x82c7cc5e,\n  0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,\n    0x1a702f01, 0x82c29906,\n  0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,\n    0x1a579741, 0x82bd6a82,\n  0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,\n    0x1a3efe7c, 0x82b840d2,\n  0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,\n    0x1a2664b5, 0x82b31bf7,\n  0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,\n    0x1a0dc9ec, 0x82adfbf0,\n  0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,\n    0x19f52e22, 0x82a8e0bf,\n  0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,\n    0x19dc9157, 0x82a3ca62,\n  0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,\n    0x19c3f38d, 0x829eb8db,\n  0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,\n    0x19ab54c5, 0x8299ac29,\n  0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,\n    0x1992b4ff, 0x8294a44c,\n  0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,\n    0x197a143e, 0x828fa146,\n  0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,\n    0x19617280, 0x828aa316,\n  0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,\n    0x1948cfc8, 0x8285a9bb,\n  0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,\n    0x19302c17, 0x8280b538,\n  0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,\n    0x1917876d, 0x827bc58a,\n  0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,\n    0x18fee1cb, 0x8276dab4,\n  0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,\n    0x18e63b33, 0x8271f4b5,\n  0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,\n    0x18cd93a5, 0x826d138d,\n  0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,\n    0x18b4eb22, 0x8268373c,\n  0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,\n    0x189c41ab, 0x82635fc2,\n  0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,\n    0x18839742, 0x825e8d21,\n  0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,\n    0x186aebe6, 0x8259bf57,\n  0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,\n    0x18523f9a, 0x8254f666,\n  0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,\n    0x1839925d, 0x8250324d,\n  0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,\n    0x1820e431, 0x824b730c,\n  0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,\n    0x18083518, 0x8246b8a4,\n  0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,\n    0x17ef8511, 0x82420315,\n  0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,\n    0x17d6d41d, 0x823d525e,\n  0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,\n    0x17be223f, 0x8238a681,\n  0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,\n    0x17a56f76, 0x8233ff7e,\n  0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,\n    0x178cbbc4, 0x822f5d54,\n  0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,\n    0x17740729, 0x822ac004,\n  0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,\n    0x175b51a7, 0x8226278d,\n  0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,\n    0x17429b3e, 0x822193f1,\n  0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,\n    0x1729e3f0, 0x821d052f,\n  0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,\n    0x17112bbd, 0x82187b47,\n  0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,\n    0x16f872a7, 0x8213f63a,\n  0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,\n    0x16dfb8ae, 0x820f7608,\n  0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,\n    0x16c6fdd3, 0x820afab1,\n  0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,\n    0x16ae4217, 0x82068435,\n  0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,\n    0x1695857b, 0x82021294,\n  0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,\n    0x167cc801, 0x81fda5cf,\n  0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,\n    0x166409a8, 0x81f93de6,\n  0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,\n    0x164b4a73, 0x81f4dad8,\n  0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,\n    0x16328a61, 0x81f07ca6,\n  0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,\n    0x1619c975, 0x81ec2351,\n  0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,\n    0x160107ae, 0x81e7ced8,\n  0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,\n    0x15e8450e, 0x81e37f3b,\n  0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,\n    0x15cf8196, 0x81df347b,\n  0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,\n    0x15b6bd47, 0x81daee98,\n  0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,\n    0x159df821, 0x81d6ad92,\n  0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,\n    0x15853226, 0x81d27169,\n  0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,\n    0x156c6b57, 0x81ce3a1d,\n  0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,\n    0x1553a3b4, 0x81ca07af,\n  0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,\n    0x153adb3f, 0x81c5da1e,\n  0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,\n    0x152211f8, 0x81c1b16b,\n  0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,\n    0x150947e1, 0x81bd8d97,\n  0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,\n    0x14f07cf9, 0x81b96ea0,\n  0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,\n    0x14d7b144, 0x81b55488,\n  0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,\n    0x14bee4c0, 0x81b13f4e,\n  0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,\n    0x14a61770, 0x81ad2ef2,\n  0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,\n    0x148d4954, 0x81a92376,\n  0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,\n    0x14747a6d, 0x81a51cd8,\n  0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,\n    0x145baabd, 0x81a11b1a,\n  0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,\n    0x1442da43, 0x819d1e3a,\n  0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,\n    0x142a0902, 0x8199263a,\n  0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,\n    0x141136f9, 0x8195331a,\n  0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,\n    0x13f8642a, 0x819144d9,\n  0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,\n    0x13df9097, 0x818d5b78,\n  0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,\n    0x13c6bc3f, 0x818976f8,\n  0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,\n    0x13ade724, 0x81859757,\n  0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,\n    0x13951146, 0x8181bc96,\n  0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,\n    0x137c3aa8, 0x817de6b6,\n  0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,\n    0x13636349, 0x817a15b7,\n  0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,\n    0x134a8b2b, 0x81764998,\n  0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,\n    0x1331b24e, 0x8172825a,\n  0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,\n    0x1318d8b4, 0x816ebffe,\n  0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,\n    0x12fffe5d, 0x816b0282,\n  0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,\n    0x12e7234b, 0x816749e8,\n  0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,\n    0x12ce477f, 0x8163962f,\n  0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,\n    0x12b56af9, 0x815fe758,\n  0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,\n    0x129c8dba, 0x815c3d62,\n  0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,\n    0x1283afc3, 0x8158984e,\n  0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,\n    0x126ad116, 0x8154f81d,\n  0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,\n    0x1251f1b3, 0x81515ccd,\n  0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,\n    0x1239119b, 0x814dc660,\n  0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,\n    0x122030cf, 0x814a34d6,\n  0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,\n    0x12074f50, 0x8146a82e,\n  0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,\n    0x11ee6d20, 0x81432068,\n  0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,\n    0x11d58a3e, 0x813f9d86,\n  0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,\n    0x11bca6ad, 0x813c1f86,\n  0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,\n    0x11a3c26c, 0x8138a66a,\n  0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,\n    0x118add7d, 0x81353230,\n  0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,\n    0x1171f7e2, 0x8131c2db,\n  0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,\n    0x1159119a, 0x812e5868,\n  0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,\n    0x11402aa6, 0x812af2da,\n  0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,\n    0x11274309, 0x8127922f,\n  0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,\n    0x110e5ac2, 0x81243668,\n  0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,\n    0x10f571d3, 0x8120df85,\n  0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,\n    0x10dc883c, 0x811d8d86,\n  0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,\n    0x10c39dff, 0x811a406c,\n  0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,\n    0x10aab31d, 0x8116f836,\n  0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,\n    0x1091c796, 0x8113b4e5,\n  0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,\n    0x1078db6c, 0x81107678,\n  0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,\n    0x105fee9f, 0x810d3cf0,\n  0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,\n    0x10470130, 0x810a084d,\n  0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,\n    0x102e1321, 0x8106d88f,\n  0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,\n    0x10152472, 0x8103adb6,\n  0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,\n    0xffc3524, 0x810087c3,\n  0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,\n    0xfe34539, 0x80fd66b5,\n  0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,\n    0xfca54b1, 0x80fa4a8c,\n  0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,\n    0xfb1638d, 0x80f73349,\n  0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,\n    0xf9871ce, 0x80f420ec,\n  0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,\n    0xf7f7f75, 0x80f11375,\n  0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,\n    0xf668c83, 0x80ee0ae4,\n  0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,\n    0xf4d98f9, 0x80eb0739,\n  0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,\n    0xf34a4d8, 0x80e80874,\n  0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,\n    0xf1bb021, 0x80e50e96,\n  0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,\n    0xf02bad5, 0x80e2199e,\n  0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,\n    0xee9c4f5, 0x80df298c,\n  0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,\n    0xed0ce82, 0x80dc3e62,\n  0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,\n    0xeb7d77c, 0x80d9581e,\n  0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,\n    0xe9edfe5, 0x80d676c1,\n  0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,\n    0xe85e7be, 0x80d39a4b,\n  0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,\n    0xe6cef07, 0x80d0c2bc,\n  0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,\n    0xe53f5c2, 0x80cdf015,\n  0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,\n    0xe3afbf0, 0x80cb2255,\n  0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,\n    0xe220191, 0x80c8597c,\n  0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,\n    0xe0906a7, 0x80c5958b,\n  0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,\n    0xdf00b32, 0x80c2d682,\n  0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,\n    0xdd70f34, 0x80c01c60,\n  0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,\n    0xdbe12ad, 0x80bd6727,\n  0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,\n    0xda5159f, 0x80bab6d5,\n  0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,\n    0xd8c1809, 0x80b80b6c,\n  0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,\n    0xd7319ee, 0x80b564ea,\n  0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,\n    0xd5a1b4f, 0x80b2c351,\n  0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,\n    0xd411c2b, 0x80b026a1,\n  0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,\n    0xd281c85, 0x80ad8ed9,\n  0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,\n    0xd0f1c5d, 0x80aafbf9,\n  0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,\n    0xcf61bb4, 0x80a86e03,\n  0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,\n    0xcdd1a8b, 0x80a5e4f5,\n  0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,\n    0xcc418e3, 0x80a360d0,\n  0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,\n    0xcab16bd, 0x80a0e194,\n  0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,\n    0xc92141a, 0x809e6741,\n  0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,\n    0xc7910fb, 0x809bf1d7,\n  0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,\n    0xc600d61, 0x80998157,\n  0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,\n    0xc47094d, 0x809715c0,\n  0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,\n    0xc2e04c0, 0x8094af13,\n  0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,\n    0xc14ffba, 0x80924d4f,\n  0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,\n    0xbfbfa3d, 0x808ff074,\n  0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,\n    0xbe2f44a, 0x808d9884,\n  0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,\n    0xbc9ede2, 0x808b457d,\n  0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,\n    0xbb0e705, 0x8088f761,\n  0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,\n    0xb97dfb5, 0x8086ae2e,\n  0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,\n    0xb7ed7f2, 0x808469e5,\n  0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,\n    0xb65cfbe, 0x80822a87,\n  0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,\n    0xb4cc719, 0x807ff013,\n  0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,\n    0xb33be05, 0x807dba89,\n  0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,\n    0xb1ab483, 0x807b89ea,\n  0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,\n    0xb01aa92, 0x80795e36,\n  0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,\n    0xae8a036, 0x8077376c,\n  0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,\n    0xacf956d, 0x8075158c,\n  0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,\n    0xab68a3a, 0x8072f898,\n  0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,\n    0xa9d7e9d, 0x8070e08e,\n  0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,\n    0xa847297, 0x806ecd6f,\n  0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,\n    0xa6b662a, 0x806cbf3c,\n  0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,\n    0xa525955, 0x806ab5f3,\n  0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,\n    0xa394c1b, 0x8068b196,\n  0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,\n    0xa203e7c, 0x8066b224,\n  0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,\n    0xa073079, 0x8064b79d,\n  0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,\n    0x9ee2213, 0x8062c202,\n  0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,\n    0x9d5134b, 0x8060d152,\n  0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,\n    0x9bc0421, 0x805ee58e,\n  0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,\n    0x9a2f498, 0x805cfeb5,\n  0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,\n    0x989e4b0, 0x805b1cc8,\n  0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,\n    0x970d46a, 0x80593fc7,\n  0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,\n    0x957c3c6, 0x805767b2,\n  0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,\n    0x93eb2c6, 0x80559489,\n  0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,\n    0x925a16b, 0x8053c64c,\n  0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,\n    0x90c8fb6, 0x8051fcfb,\n  0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,\n    0x8f37da7, 0x80503896,\n  0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,\n    0x8da6b40, 0x804e791d,\n  0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,\n    0x8c15882, 0x804cbe90,\n  0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,\n    0x8a8456d, 0x804b08f0,\n  0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,\n    0x88f3203, 0x8049583d,\n  0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,\n    0x8761e44, 0x8047ac75,\n  0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,\n    0x85d0a32, 0x8046059b,\n  0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,\n    0x843f5cd, 0x804463ad,\n  0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,\n    0x82ae117, 0x8042c6ab,\n  0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,\n    0x811cc10, 0x80412e96,\n  0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,\n    0x7f8b6b9, 0x803f9b6f,\n  0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,\n    0x7dfa114, 0x803e0d34,\n  0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,\n    0x7c68b21, 0x803c83e5,\n  0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,\n    0x7ad74e1, 0x803aff84,\n  0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,\n    0x7945e56, 0x80398010,\n  0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,\n    0x77b4780, 0x80380589,\n  0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,\n    0x762305f, 0x80368fef,\n  0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,\n    0x74918f6, 0x80351f43,\n  0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,\n    0x7300145, 0x8033b383,\n  0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,\n    0x716e94e, 0x80324cb1,\n  0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,\n    0x6fdd110, 0x8030eacd,\n  0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,\n    0x6e4b88d, 0x802f8dd5,\n  0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,\n    0x6cb9fc6, 0x802e35cb,\n  0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,\n    0x6b286bc, 0x802ce2af,\n  0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,\n    0x6996d70, 0x802b9480,\n  0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,\n    0x68053e3, 0x802a4b3f,\n  0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,\n    0x6673a16, 0x802906ec,\n  0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,\n    0x64e2009, 0x8027c786,\n  0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,\n    0x63505be, 0x80268d0e,\n  0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,\n    0x61beb36, 0x80255784,\n  0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,\n    0x602d072, 0x802426e8,\n  0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,\n    0x5e9b572, 0x8022fb3a,\n  0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,\n    0x5d09a38, 0x8021d47a,\n  0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,\n    0x5b77ec5, 0x8020b2a7,\n  0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,\n    0x59e6319, 0x801f95c3,\n  0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,\n    0x5854736, 0x801e7dcd,\n  0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,\n    0x56c2b1c, 0x801d6ac5,\n  0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,\n    0x5530ecd, 0x801c5cab,\n  0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,\n    0x539f249, 0x801b537f,\n  0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,\n    0x520d592, 0x801a4f42,\n  0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,\n    0x507b8a8, 0x80194ff3,\n  0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,\n    0x4ee9b8c, 0x80185592,\n  0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,\n    0x4d57e40, 0x80176020,\n  0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,\n    0x4bc60c4, 0x80166f9c,\n  0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,\n    0x4a34319, 0x80158406,\n  0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,\n    0x48a2540, 0x80149d5f,\n  0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,\n    0x471073b, 0x8013bba7,\n  0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,\n    0x457e90a, 0x8012dedd,\n  0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,\n    0x43ecaae, 0x80120701,\n  0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,\n    0x425ac28, 0x80113414,\n  0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,\n    0x40c8d79, 0x80106616,\n  0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,\n    0x3f36ea2, 0x800f9d07,\n  0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,\n    0x3da4fa4, 0x800ed8e6,\n  0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,\n    0x3c13080, 0x800e19b4,\n  0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,\n    0x3a81137, 0x800d5f71,\n  0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,\n    0x38ef1ca, 0x800caa1c,\n  0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,\n    0x375d23a, 0x800bf9b7,\n  0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,\n    0x35cb288, 0x800b4e40,\n  0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,\n    0x34392b4, 0x800aa7b8,\n  0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,\n    0x32a72c1, 0x800a061f,\n  0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,\n    0x31152ae, 0x80096975,\n  0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,\n    0x2f8327d, 0x8008d1ba,\n  0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,\n    0x2df122e, 0x80083eed,\n  0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,\n    0x2c5f1c3, 0x8007b110,\n  0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,\n    0x2acd13d, 0x80072822,\n  0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,\n    0x293b09c, 0x8006a423,\n  0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,\n    0x27a8fe2, 0x80062513,\n  0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,\n    0x2616f10, 0x8005aaf2,\n  0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,\n    0x2484e26, 0x800535c0,\n  0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,\n    0x22f2d25, 0x8004c57d,\n  0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,\n    0x2160c0f, 0x80045a29,\n  0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,\n    0x1fceae4, 0x8003f3c5,\n  0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,\n    0x1e3c9a6, 0x8003924f,\n  0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,\n    0x1caa855, 0x800335c9,\n  0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,\n    0x1b186f3, 0x8002de32,\n  0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,\n    0x198657f, 0x80028b8a,\n  0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,\n    0x17f43fc, 0x80023dd2,\n  0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,\n    0x166226a, 0x8001f508,\n  0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,\n    0x14d00ca, 0x8001b12e,\n  0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,\n    0x133df1e, 0x80017243,\n  0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,\n    0x11abd66, 0x80013847,\n  0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,\n    0x1019ba2, 0x8001033b,\n  0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,\n    0x8000d31e,\n  0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,\n    0x8000a7f0,\n  0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,\n    0x800081b1,\n  0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,\n    0x80006062,\n  0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,\n    0x80004402,\n  0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,\n    0x80002c91,\n  0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,\n    0x80001a10,\n  0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,\n    0x80000c7e,\n  0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,\n    0x800003db,\n  0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,\n    0x80000027,\n\n};\n\n/**    \n* \\par    \n* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    \n* \\par    \n* C command to generate the table    \n* 
    \n* for(i = 0; i< N; i++)    \n* {    \n*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n* } 
    \n* \\par    \n* where N is the number of factors to generate and c is pi/(2*N)    \n* \\par    \n* Then converted to q31 format by multiplying with 2^31 and saturated if required.    \n*/\n\n\nstatic const q31_t cos_factorsQ31_128[128] = {\n  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,\n  0x7f97cebd, 0x7f754e80,\n  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,\n  0x7dfa98a8, 0x7db0fdf8,\n  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,\n  0x7b26cb4f, 0x7ab6cba4,\n  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,\n  0x77235f2d, 0x768e0ea6,\n  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,\n  0x71fa3949, 0x71410805,\n  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,\n  0x6bb812d1, 0x6adcc964,\n  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,\n  0x646c59bf, 0x637114cc,\n  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,\n  0x5c290acc, 0x5b1035cf,\n  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,\n  0x53028518, 0x51ced46e,\n  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,\n  0x490f57ee, 0x47c3c22f,\n  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,\n  0x3e680b2c, 0x3d07c1d6,\n  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,\n  0x3326e2c3, 0x31b54a5e,\n  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,\n  0x27679df4, 0x25e845b6,\n  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,\n  0x1b4732ef, 0x19bdcbf3,\n  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,\n  0xee38766, 0xd53db92,\n  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,\n  0xc90f88,\n};\n\nstatic const q31_t cos_factorsQ31_512[512] = {\n  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,\n  0x7ff97c18, 0x7ff75370,\n  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,\n  0x7fdf9508, 0x7fdaf519,\n  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,\n  0x7fb1f5fc, 0x7faadf7c,\n  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,\n  0x7f70a5fe, 0x7f671a05,\n  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,\n  0x7f1baf1e, 0x7f0faf25,\n  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,\n  0x7eb31e78, 0x7ea4ac58,\n  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,\n  0x7e37042a, 0x7e26221f,\n  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,\n  0x7da77359, 0x7d9423fc,\n  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,\n  0x7d048228, 0x7ceec873,\n  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,\n  0x7c4e49b7, 0x7c362904,\n  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,\n  0x7b84e61f, 0x7b6a6227,\n  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,\n  0x7aa8766f, 0x7a8b9348,\n  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,\n  0x79b91ca4, 0x7999dec4,\n  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,\n  0x78b6fda8, 0x789569df,\n  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,\n  0x77a24148, 0x777e5cc3,\n  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,\n  0x767b1231, 0x7654e279,\n  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,\n  0x75419de7, 0x751928e0,\n  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,\n  0x73f614c0, 0x73cb60a8,\n  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,\n  0x7298a9dd, 0x726bbd48,\n  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,\n  0x7129931f, 0x70fa74fc,\n  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,\n  0x6fa90921, 0x6f77c0b3,\n  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,\n  0x6e174730, 0x6de3dc11,\n  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,\n  0x6c748b3f, 0x6c3f055d,\n  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,\n  0x6ac115e2, 0x6a897d7d,\n  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,\n  0x68fd2a3d, 0x68c387e9,\n  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,\n  0x67290e02, 0x66ed6aa1,\n  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,\n  0x6545095f, 0x65076e25,\n  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,\n  0x635166f9, 0x6311dd64,\n  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,\n  0x614e73da, 0x610d05b7,\n  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,\n  0x5f3c7f6b, 0x5ef936d1,\n  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,\n  0x5d1bdb65, 0x5cd6c2b5,\n  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,\n  0x5aecdbc5, 0x5aa5fda5,\n  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,\n  0x58afd6bd, 0x58673e1b,\n  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,\n  0x566524aa, 0x561adcb9,\n  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,\n  0x540d2005, 0x53c13439,\n  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,\n  0x51a82555, 0x515aa162,\n  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,\n  0x4f369320, 0x4ee782fb,\n  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,\n  0x4cb8c9dd, 0x4c6839b7,\n  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,\n  0x4a2f2be6, 0x49dd282a,\n  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,\n  0x479a1d67, 0x4746b2bc,\n  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,\n  0x44fa0450, 0x44a53f93,\n  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,\n  0x424f4845, 0x41f93689,\n  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,\n  0x3f9a5290, 0x3f430119,\n  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,\n  0x3cdb8e09, 0x3c830a50,\n  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,\n  0x3a136712, 0x39b9bebc,\n  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,\n  0x37424b7b, 0x36e78c5b,\n  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,\n  0x3468aa76, 0x340ce28b,\n  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,\n  0x3186f487, 0x312a31f8,\n  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,\n  0x2e9d9b70, 0x2e3fec8b,\n  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,\n  0x2bad1221, 0x2b4e8558,\n  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,\n  0x28b5cca5, 0x2856708d,\n  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,\n  0x25b84012, 0x2558235f,\n  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,\n  0x22b4e274, 0x225413f8,\n  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,\n  0x1fac2abf, 0x1f4ab968,\n  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,\n  0x1c9e90b8, 0x1c3c8b8c,\n  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,\n  0x198c8ce7, 0x192a0304,\n  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,\n  0x1676987f, 0x16139918,\n  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,\n  0x135d2d53, 0x12f9c7aa,\n  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,\n  0x1040c5bb, 0xfdd0926,\n  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,\n  0xcbdd865,\n  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,\n  0x99cb0a7,\n  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,\n  0x67a0d76,\n  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,\n  0x3566a96,\n  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,\n  0x3243f5,\n};\n\nstatic const q31_t cos_factorsQ31_2048[2048] = {\n  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,\n  0x7fff97c1, 0x7fff7536,\n  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,\n  0x7ffdf93c, 0x7ffdaf37,\n  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,\n  0x7ffb1ee9, 0x7ffaad6a,\n  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,\n  0x7ff708ce, 0x7ff66fd7,\n  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,\n  0x7ff1b6f6, 0x7ff0f688,\n  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,\n  0x7feb296d, 0x7fea418b,\n  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,\n  0x7fe36045, 0x7fe250ef,\n  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,\n  0x7fda5b8f, 0x7fd924ca,\n  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,\n  0x7fd01b63, 0x7fcebd31,\n  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,\n  0x7fc49fda, 0x7fc31a3d,\n  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,\n  0x7fb7e90f, 0x7fb63c0d,\n  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,\n  0x7fa9f723, 0x7fa822bf,\n  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,\n  0x7f9aca37, 0x7f98ce76,\n  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,\n  0x7f8a6272, 0x7f883f58,\n  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,\n  0x7f78bffb, 0x7f76758e,\n  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,\n  0x7f65e2ff, 0x7f637144,\n  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,\n  0x7f51cbab, 0x7f4f32a9,\n  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,\n  0x7f3c7a31, 0x7f39b9ee,\n  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,\n  0x7f25eec7, 0x7f230749,\n  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,\n  0x7f0e29a3, 0x7f0b1af2,\n  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,\n  0x7ef52b00, 0x7ef1f524,\n  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,\n  0x7edaf31c, 0x7ed7961c,\n  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,\n  0x7ebf8237, 0x7ebbfe1c,\n  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,\n  0x7ea2d896, 0x7e9f2d68,\n  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,\n  0x7e84f67e, 0x7e812447,\n  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,\n  0x7e65dc3b, 0x7e61e303,\n  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,\n  0x7e458a17, 0x7e4169e9,\n  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,\n  0x7e240064, 0x7e1fb94a,\n  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,\n  0x7e013f74, 0x7dfcd178,\n  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,\n  0x7ddd479d, 0x7dd8b2ca,\n  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,\n  0x7db81936, 0x7db35d98,\n  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,\n  0x7d91b49e, 0x7d8cd240,\n  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,\n  0x7d6a1a31, 0x7d65111f,\n  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,\n  0x7d414a51, 0x7d3c1a98,\n  0x7d36e60b, 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0x23e2dcac,\n  0x23cabc09, 0x23b29a05,\n  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,\n  0x23098593, 0x22f158a7,\n  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,\n  0x2247f8aa, 0x222fc111,\n  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,\n  0x2186172b, 0x216dd521,\n  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,\n  0x20c3e2f5, 0x20ab96b5,\n  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,\n  0x20015de7, 0x1fe907ae,\n  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,\n  0x1f3e89e0, 0x1f2629ea,\n  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,\n  0x1e7b68c2, 0x1e62ff4a,\n  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,\n  0x1db7fc6d, 0x1d9f89b1,\n  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,\n  0x1cf446c5, 0x1cdbcb00,\n  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,\n  0x1c3049ac, 0x1c17c51b,\n  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,\n  0x1b6c0705, 0x1b5379e5,\n  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,\n  0x1aa780b6, 0x1a8eeb42,\n  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,\n  0x19e2b8a2, 0x19ca1b17,\n  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,\n  0x191db0af, 0x19050b4b,\n  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,\n  0x18586ac3, 0x183fbdc3,\n  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,\n  0x1792e8c6, 0x177a3466,\n  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,\n  0x16cd2c9f, 0x16b4711b,\n  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,\n  0x16073834, 0x15ee75cb,\n  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,\n  0x15410d70, 0x1528445d,\n  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,\n  0x147aae3a, 0x1461debc,\n  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,\n  0x13b41c7d, 0x139b46d0,\n  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,\n  0x12ed5a21, 0x12d47e83,\n  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,\n  0x12266913, 0x120d87c1,\n  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,\n  0x115f4b3c, 0x11466473,\n  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,\n  0x10980287, 0x107f1686,\n  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,\n  0xfd090e1, 0xfb79fe4,\n  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,\n  0xef0027b,\n  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,\n  0xe284036,\n  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,\n  0xd605b03,\n  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,\n  0xc9854cf,\n  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,\n  0xbd02f87,\n  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,\n  0xb07ed19,\n  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,\n  0xa3f8f73,\n  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,\n  0x9771884,\n  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,\n  0x8ae8a3a,\n  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,\n  0x7e5e685,\n  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,\n  0x71d2f52,\n  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,\n  0x6546692,\n  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,\n  0x58b8e34,\n  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,\n  0x4c2a827,\n  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,\n  0x3f9b65b,\n  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,\n  0x330bac1,\n  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,\n  0x267b747,\n  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,\n  0x19eaddd,\n  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,\n  0xd5a075,\n  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,\n  0xc90fe,\n\n};\n\nstatic const q31_t cos_factorsQ31_8192[8192] = {\n  0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,\n    0x7ffff97c, 0x7ffff753,\n  0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,\n    0x7fffdf94, 0x7fffdaf3,\n  0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,\n    0x7fffb1ee, 0x7fffaad6,\n  0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,\n    0x7fff708b, 0x7fff66fc,\n  0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,\n    0x7fff1b6b, 0x7fff0f64,\n  0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,\n    0x7ffeb28e, 0x7ffea40f,\n  0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,\n    0x7ffe35f4, 0x7ffe24fe,\n  0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,\n    0x7ffda59d, 0x7ffd922f,\n  0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,\n    0x7ffd0189, 0x7ffceba4,\n  0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,\n    0x7ffc49b9, 0x7ffc315b,\n  0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,\n    0x7ffb7e2b, 0x7ffb6356,\n  0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,\n    0x7ffa9ee2, 0x7ffa8195,\n  0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,\n    0x7ff9abdb, 0x7ff98c17,\n  0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,\n    0x7ff8a519, 0x7ff882dd,\n  0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,\n    0x7ff78a9a, 0x7ff765e7,\n  0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,\n    0x7ff65c5f, 0x7ff63535,\n  0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,\n    0x7ff51a69, 0x7ff4f0c7,\n  0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,\n    0x7ff3c4b7, 0x7ff3989e,\n  0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,\n    0x7ff25b4a, 0x7ff22cb9,\n  0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,\n    0x7ff0de22, 0x7ff0ad19,\n  0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,\n    0x7fef4d3e, 0x7fef19bf,\n  0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,\n    0x7feda8a0, 0x7fed72aa,\n  0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,\n    0x7febf048, 0x7febb7da,\n  0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,\n    0x7fea2436, 0x7fe9e950,\n  0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,\n    0x7fe84469, 0x7fe8070d,\n  0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,\n    0x7fe650e3, 0x7fe61110,\n  0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,\n    0x7fe449a4, 0x7fe40759,\n  0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,\n    0x7fe22eac, 0x7fe1e9ea,\n  0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,\n    0x7fdffffb, 0x7fdfb8c2,\n  0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,\n    0x7fddbd92, 0x7fdd73e2,\n  0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,\n    0x7fdb6771, 0x7fdb1b4a,\n  0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,\n    0x7fd8fd98, 0x7fd8aefa,\n  0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,\n    0x7fd68009, 0x7fd62ef4,\n  0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,\n    0x7fd3eec2, 0x7fd39b36,\n  0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,\n    0x7fd149c5, 0x7fd0f3c2,\n  0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,\n    0x7fce9112, 0x7fce3898,\n  0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,\n    0x7fcbc4a9, 0x7fcb69b9,\n  0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,\n    0x7fc8e48b, 0x7fc88724,\n  0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,\n    0x7fc5f0b8, 0x7fc590db,\n  0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,\n    0x7fc2e931, 0x7fc286de,\n  0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,\n    0x7fbfcdf6, 0x7fbf692c,\n  0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,\n    0x7fbc9f08, 0x7fbc37c8,\n  0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,\n    0x7fb95c67, 0x7fb8f2b0,\n  0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,\n    0x7fb60614, 0x7fb599e7,\n  0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,\n    0x7fb29c0f, 0x7fb22d6c,\n  0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,\n    0x7faf1e58, 0x7faead3f,\n  0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,\n    0x7fab8cf1, 0x7fab1962,\n  0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,\n    0x7fa7e7d9, 0x7fa771d4,\n  0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,\n    0x7fa42f12, 0x7fa3b697,\n  0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,\n    0x7fa0629c, 0x7f9fe7ab,\n  0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,\n    0x7f9c8278, 0x7f9c0511,\n  0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,\n    0x7f988ea5, 0x7f980ec8,\n  0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,\n    0x7f948725, 0x7f9404d3,\n  0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,\n    0x7f906bf9, 0x7f8fe731,\n  0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,\n    0x7f8c3d20, 0x7f8bb5e3,\n  0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,\n    0x7f87fa9c, 0x7f8770ea,\n  0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,\n    0x7f83a46e, 0x7f831846,\n  0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,\n    0x7f7f3a95, 0x7f7eabf8,\n  0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,\n    0x7f7abd13, 0x7f7a2c01,\n  0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,\n    0x7f762be8, 0x7f759861,\n  0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,\n    0x7f718715, 0x7f70f119,\n  0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,\n    0x7f6cce9b, 0x7f6c362a,\n  0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,\n    0x7f68027b, 0x7f676795,\n  0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,\n    0x7f6322b4, 0x7f62855a,\n  0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,\n    0x7f5e2f49, 0x7f5d8f7a,\n  0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,\n    0x7f592839, 0x7f5885f6,\n  0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,\n    0x7f540d86, 0x7f5368ce,\n  0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,\n    0x7f4edf30, 0x7f4e3804,\n  0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,\n    0x7f499d38, 0x7f48f398,\n  0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,\n    0x7f44479f, 0x7f439b8b,\n  0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 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0x50ed4af8, 0x50e86ca8,\n  0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,\n    0x50c65301, 0x50c17322,\n  0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,\n    0x509f4e95, 0x509a6d28,\n  0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,\n    0x50783dba, 0x50735abf,\n  0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,\n    0x50512077, 0x504c3bef,\n  0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,\n    0x5029f6d1, 0x502510bd,\n  0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,\n    0x5002c0cd, 0x4ffdd92f,\n  0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,\n    0x4fdb7e74, 0x4fd6954b,\n  0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,\n    0x4fb42fc9, 0x4faf4517,\n  0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,\n    0x4f8cd4d4, 0x4f87e899,\n  0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 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0x46534be5, 0x464e0bd6,\n  0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,\n    0x462946ac, 0x46240542,\n  0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,\n    0x45ff36a1, 0x45f9f3dd,\n  0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,\n    0x45d51bcb, 0x45cfd7ae,\n  0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,\n    0x45aaf630, 0x45a5b0bb,\n  0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,\n    0x4580c5d6, 0x457b7f0a,\n  0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,\n    0x45568ac4, 0x455142a2,\n  0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,\n    0x452c4502, 0x4526fb89,\n  0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,\n    0x4501f494, 0x44fca9c6,\n  0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,\n    0x44d79982, 0x44d24d60,\n  0x44cd0114, 0x44c7b49e, 0x44c267fd, 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0x43286de4,\n  0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,\n    0x4302f8b0, 0x42fd9e28,\n  0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,\n    0x42d81fe9, 0x42d2c417,\n  0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,\n    0x42ad3cd4, 0x42a7dfb8,\n  0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,\n    0x42824f76, 0x427cf112,\n  0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,\n    0x425757d7, 0x4251f82b,\n  0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,\n    0x422c55fd, 0x4226f50a,\n  0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,\n    0x420149ee, 0x41fbe7b5,\n  0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,\n    0x41d633b1, 0x41d0d033,\n  0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,\n    0x41ab134e, 0x41a5ae8b,\n  0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,\n    0x417fe8ca, 0x417a82c3,\n  0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,\n    0x4154b42c, 0x414f4ce2,\n  0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,\n    0x4129757b, 0x41240cef,\n  0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,\n    0x40fe2cbd, 0x40f8c2f1,\n  0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,\n    0x40d2d9f9, 0x40cd6eed,\n  0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,\n    0x40a77d37, 0x40a210eb,\n  0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,\n    0x407c167c, 0x4076a8f1,\n  0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,\n    0x4050a5cf, 0x404b3707,\n  0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,\n    0x40252b37, 0x401fbb32,\n  0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,\n    0x3ff9a6bb, 0x3ff4357a,\n  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0x3afb4c34, 0x3af5b894,\n  0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,\n    0x3aceab40, 0x3ac9167e,\n  0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,\n    0x3aa2013a, 0x3a9c6b57,\n  0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,\n    0x3a754e2a, 0x3a6fb726,\n  0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,\n    0x3a489216, 0x3a42f9f2,\n  0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,\n    0x3a1bcd05, 0x3a1633c1,\n  0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,\n    0x39eefefe, 0x39e9649c,\n  0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,\n    0x39c22808, 0x39bc8c89,\n  0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,\n    0x39954829, 0x398fab8e,\n  0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,\n    0x39685f6a, 0x3962c1b2,\n  0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,\n    0x393b6dd0, 0x3935cefd,\n  0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,\n    0x390e7362, 0x3908d376,\n  0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,\n    0x38e17028, 0x38dbcf23,\n  0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,\n    0x38b46429, 0x38aec20b,\n  0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,\n    0x38874f6b, 0x3881ac36,\n  0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,\n    0x385a31f5, 0x38548daa,\n  0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,\n    0x382d0bce, 0x3827666d,\n  0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,\n    0x37ffdcfe, 0x37fa3688,\n  0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,\n    0x37d2a58b, 0x37ccfe02,\n  0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,\n    0x37a5657c, 0x379fbce0,\n  0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,\n    0x37781cd9, 0x3772732a,\n  0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,\n    0x374acba7, 0x374520e7,\n  0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,\n    0x371d71ef, 0x3717c61f,\n  0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,\n    0x36f00fb7, 0x36ea62d7,\n  0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,\n    0x36c2a506, 0x36bcf718,\n  0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,\n    0x369531e3, 0x368f82e7,\n  0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,\n    0x3667b655, 0x3662064c,\n  0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,\n    0x363a3264, 0x3634814f,\n  0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,\n    0x360ca615, 0x3606f3f5,\n  0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,\n    0x35df1171, 0x35d95e47,\n  0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,\n    0x35b1747e, 0x35abc04b,\n  0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,\n    0x3583cf44, 0x357e1a08,\n  0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,\n    0x355621c9, 0x35506b85,\n  0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,\n    0x35286c14, 0x3522b4c9,\n  0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,\n    0x34faae2c, 0x34f4f5dc,\n  0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,\n    0x34cce819, 0x34c72ec4,\n  0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,\n    0x349f19e2, 0x34995f88,\n  0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,\n    0x3471438d, 0x346b8830,\n  0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,\n    0x34436521, 0x343da8c3,\n  0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,\n    0x34157ea7, 0x340fc147,\n  0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,\n    0x33e79024, 0x33e1d1c4,\n  0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,\n    0x33b999a0, 0x33b3da40,\n  0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,\n    0x338b9b22, 0x3385dac4,\n  0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,\n    0x335d94b2, 0x3357d355,\n  0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,\n    0x332f8655, 0x3329c3fb,\n  0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,\n    0x33017014, 0x32fbacbe,\n  0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,\n    0x32d351f5, 0x32cd8da4,\n  0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,\n    0x32a52bff, 0x329f66b4,\n  0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,\n    0x3276fe3a, 0x327137f6,\n  0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,\n    0x3248c8ad, 0x32430170,\n  0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,\n    0x321a8b5f, 0x3214c32a,\n  0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,\n    0x31ec4657, 0x31e67d2b,\n  0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,\n    0x31bdf99b, 0x31b82f7a,\n  0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,\n    0x318fa535, 0x3189da1e,\n  0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,\n    0x31614929, 0x315b7d1e,\n  0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,\n    0x3132e580, 0x312d1882,\n  0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,\n    0x31047a41, 0x30feac51,\n  0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,\n    0x30d60772, 0x30d03891,\n  0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,\n    0x30a78d1c, 0x30a1bd4a,\n  0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,\n    0x30790b45, 0x30733a83,\n  0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,\n    0x304a81f4, 0x3044b044,\n  0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,\n    0x301bf131, 0x30161e93,\n  0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,\n    0x2fed5902, 0x2fe78577,\n  0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,\n    0x2fbeb970, 0x2fb8e4f9,\n  0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,\n    0x2f901280, 0x2f8a3d1e,\n  0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,\n    0x2f61643b, 0x2f5b8def,\n  0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,\n    0x2f32aea8, 0x2f2cd772,\n  0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,\n    0x2f03f1cd, 0x2efe19ae,\n  0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,\n    0x2ed52db1, 0x2ecf54ac,\n  0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,\n    0x2ea6625d, 0x2ea08871,\n  0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,\n    0x2e778fd8, 0x2e71b506,\n  0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,\n    0x2e48b628, 0x2e42da71,\n  0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,\n    0x2e19d554, 0x2e13f8ba,\n  0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,\n    0x2deaed65, 0x2de50fe8,\n  0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,\n    0x2dbbfe61, 0x2db62001,\n  0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,\n    0x2d8d084f, 0x2d87290f,\n  0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,\n    0x2d5e0b38, 0x2d582b17,\n  0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,\n    0x2d2f0721, 0x2d292620,\n  0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,\n    0x2cfffc12, 0x2cfa1a33,\n  0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,\n    0x2cd0ea13, 0x2ccb0756,\n  0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,\n    0x2ca1d12a, 0x2c9bed91,\n  0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,\n    0x2c72b160, 0x2c6ccceb,\n  0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,\n    0x2c438abb, 0x2c3da56b,\n  0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,\n    0x2c145d42, 0x2c0e7719,\n  0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,\n    0x2be528fd, 0x2bdf41fb,\n  0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,\n    0x2bb5edf4, 0x2bb00619,\n  0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,\n    0x2b86ac2c, 0x2b80c37a,\n  0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,\n    0x2b5763ae, 0x2b517a26,\n  0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,\n    0x2b281482, 0x2b222a24,\n  0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,\n    0x2af8bead, 0x2af2d37b,\n  0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,\n    0x2ac96238, 0x2ac37633,\n  0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,\n    0x2a99ff2a, 0x2a941252,\n  0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,\n    0x2a6a958a, 0x2a64a7e0,\n  0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,\n    0x2a3b2560, 0x2a3536e5,\n  0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,\n    0x2a0baeb2, 0x2a05bf67,\n  0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,\n    0x29dc3188, 0x29d6416f,\n  0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,\n    0x29acadea, 0x29a6bd02,\n  0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,\n    0x297d23df, 0x2977322a,\n  0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,\n    0x294d936d, 0x2947a0ec,\n  0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,\n    0x291dfc9d, 0x29180951,\n  0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,\n    0x28ee5f76, 0x28e86b5f,\n  0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,\n    0x28bebbff, 0x28b8c71f,\n  0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,\n    0x288f123f, 0x28891c97,\n  0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,\n    0x285f623f, 0x28596bce,\n  0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,\n    0x282fac04, 0x2829b4cd,\n  0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,\n    0x27ffef97, 0x27f9f79a,\n  0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,\n    0x27d02cff, 0x27ca343d,\n  0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,\n    0x27a06443, 0x279a6abd,\n  0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,\n    0x2770956a, 0x276a9b21,\n  0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,\n    0x2740c07d, 0x273ac572,\n  0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,\n    0x2710e582, 0x270ae9b6,\n  0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,\n    0x26e10480, 0x26db07f4,\n  0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,\n    0x26b11d80, 0x26ab2034,\n  0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,\n    0x26813088, 0x267b327e,\n  0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,\n    0x26513da1, 0x264b3ed9,\n  0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,\n    0x262144d0, 0x261b454c,\n  0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,\n    0x25f1461e, 0x25eb45de,\n  0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,\n    0x25c14192, 0x25bb4098,\n  0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,\n    0x25913734, 0x258b3580,\n  0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,\n    0x2561270b, 0x255b249e,\n  0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,\n    0x2531111e, 0x252b0df9,\n  0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,\n    0x2500f574, 0x24faf198,\n  0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,\n    0x24d0d416, 0x24cacf84,\n  0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,\n    0x24a0ad0b, 0x249aa7c4,\n  0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,\n    0x24708059, 0x246a7a5e,\n  0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,\n    0x24404e09, 0x243a475a,\n  0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,\n    0x24101622, 0x240a0ec1,\n  0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,\n    0x23dfd8ab, 0x23d9d098,\n  0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,\n    0x23af95ac, 0x23a98ce8,\n  0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,\n    0x237f4d2b, 0x237943b9,\n  0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,\n    0x234eff32, 0x2348f511,\n  0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,\n    0x231eabc7, 0x2318a0f8,\n  0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,\n    0x22ee52f1, 0x22e84775,\n  0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,\n    0x22bdf4b8, 0x22b7e890,\n  0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,\n    0x228d9123, 0x22878451,\n  0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,\n    0x225d283b, 0x22571abe,\n  0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,\n    0x222cba06, 0x2226abe0,\n  0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,\n    0x21fc468b, 0x21f637be,\n  0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,\n    0x21cbcdd3, 0x21c5be5e,\n  0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,\n    0x219b4fe5, 0x21953fca,\n  0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,\n    0x216accc8, 0x2164bc08,\n  0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,\n    0x213a4484, 0x2134331f,\n  0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,\n    0x2109b720, 0x2103a518,\n  0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,\n    0x20d924a4, 0x20d311f9,\n  0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,\n    0x20a88d17, 0x20a279ca,\n  0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,\n    0x2077f080, 0x2071dc93,\n  0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,\n    0x20474ee8, 0x20413a5b,\n  0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,\n    0x2016a856, 0x2010932a,\n  0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,\n    0x1fe5fcd0, 0x1fdfe707,\n  0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,\n    0x1fb54c60, 0x1faf35f9,\n  0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,\n    0x1f84970b, 0x1f7e8009,\n  0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,\n    0x1f53dcdb, 0x1f4dc53d,\n  0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,\n    0x1f231dd5, 0x1f1d059e,\n  0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,\n    0x1ef25a03, 0x1eec4132,\n  0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,\n    0x1ec1916a, 0x1ebb7802,\n  0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,\n    0x1e90c414, 0x1e8aaa14,\n  0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,\n    0x1e5ff206, 0x1e59d770,\n  0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,\n    0x1e2f1b4a, 0x1e29001e,\n  0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,\n    0x1dfe3fe6, 0x1df82426,\n  0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,\n    0x1dcd5fe2, 0x1dc7438e,\n  0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,\n    0x1d9c7b45, 0x1d965e5f,\n  0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,\n    0x1d6b9217, 0x1d6574a0,\n  0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,\n    0x1d3aa460, 0x1d348658,\n  0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,\n    0x1d09b227, 0x1d03938f,\n  0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,\n    0x1cd8bb74, 0x1cd29c4d,\n  0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,\n    0x1ca7c04d, 0x1ca1a099,\n  0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,\n    0x1c76c0bc, 0x1c70a07b,\n  0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,\n    0x1c45bcc7, 0x1c3f9bf9,\n  0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,\n    0x1c14b475, 0x1c0e931d,\n  0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,\n    0x1be3a7cf, 0x1bdd85ed,\n  0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,\n    0x1bb296dc, 0x1bac7471,\n  0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,\n    0x1b8181a4, 0x1b7b5eb0,\n  0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,\n    0x1b50682e, 0x1b4a44b3,\n  0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,\n    0x1b1f4a81, 0x1b192680,\n  0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,\n    0x1aee28a6, 0x1ae8041f,\n  0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,\n    0x1abd02a3, 0x1ab6dd98,\n  0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,\n    0x1a8bd881, 0x1a85b2f3,\n  0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,\n    0x1a5aaa47, 0x1a548436,\n  0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,\n    0x1a2977fc, 0x1a23516a,\n  0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,\n    0x19f841a9, 0x19f21a96,\n  0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,\n    0x19c70754, 0x19c0dfc2,\n  0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,\n    0x1995c906, 0x198fa0f5,\n  0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,\n    0x196486c6, 0x195e5e37,\n  0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,\n    0x1933409b, 0x192d178f,\n  0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,\n    0x1901f68d, 0x18fbcd06,\n  0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,\n    0x18d0a8a4, 0x18ca7ea2,\n  0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,\n    0x189f56e8, 0x18992c6b,\n  0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,\n    0x186e015f, 0x1867d66a,\n  0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,\n    0x183ca812, 0x18367ca5,\n  0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,\n    0x180b4b08, 0x18051f24,\n  0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,\n    0x17d9ea49, 0x17d3bdee,\n  0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,\n    0x17a885dc, 0x17a2590d,\n  0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,\n    0x17771dc9, 0x1770f086,\n  0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,\n    0x1745b218, 0x173f8461,\n  0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,\n    0x171442d0, 0x170e14a7,\n  0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,\n    0x16e2cff9, 0x16dca15f,\n  0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,\n    0x16b1599b, 0x16ab2a90,\n  0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,\n    0x167fdfbc, 0x1679b042,\n  0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,\n    0x164e6266, 0x1648327d,\n  0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,\n    0x161ce19e, 0x1616b148,\n  0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,\n    0x15eb5d6e, 0x15e52cab,\n  0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,\n    0x15b9d5dd, 0x15b3a4ae,\n  0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,\n    0x15884af1, 0x15821958,\n  0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,\n    0x1556bcb4, 0x15508ab1,\n  0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,\n    0x15252b2c, 0x151ef8c0,\n  0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,\n    0x14f39662, 0x14ed638e,\n  0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,\n    0x14c1fe5c, 0x14bbcb22,\n  0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,\n    0x14906323, 0x148a2f82,\n  0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,\n    0x145ec4be, 0x145890b9,\n  0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,\n    0x142d2335, 0x1426eecb,\n  0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,\n    0x13fb7e8f, 0x13f549c3,\n  0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,\n    0x13c9d6d4, 0x13c3a1a6,\n  0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,\n    0x13982c0d, 0x1391f67d,\n  0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,\n    0x13667e3f, 0x13604850,\n  0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,\n    0x1334cd74, 0x132e9725,\n  0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,\n    0x130319b3, 0x12fce305,\n  0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,\n    0x12d16303, 0x12cb2bf8,\n  0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,\n    0x129fa96c, 0x12997205,\n  0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,\n    0x126decf5, 0x1267b533,\n  0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,\n    0x123c2da8, 0x1235f58b,\n  0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,\n    0x120a6b8a, 0x12043314,\n  0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,\n    0x11d8a6a4, 0x11d26dd6,\n  0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,\n    0x11a6defe, 0x11a0a5d8,\n  0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,\n    0x1175149e, 0x116edb22,\n  0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,\n    0x1143478e, 0x113d0dbc,\n  0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,\n    0x111177d4, 0x110b3dad,\n  0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,\n    0x10dfa578, 0x10d96afe,\n  0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,\n    0x10add082, 0x10a795b5,\n  0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,\n    0x107bf8fa, 0x1075bddb,\n  0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,\n    0x104a1ee7, 0x1043e377,\n  0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,\n    0x10184251, 0x10120691,\n  0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,\n    0xfe6633f, 0xfe02730,\n  0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,\n    0xfae455d,\n  0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,\n    0xf7c611f,\n  0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,\n    0xf4a7a7d,\n  0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,\n    0xf189180,\n  0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,\n    0xee6a62f,\n  0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,\n    0xeb4b891,\n  0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,\n    0xe82c8af,\n  0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,\n    0xe50d690,\n  0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,\n    0xe1ee23c,\n  0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,\n    0xdecebba,\n  0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,\n    0xdbaf313,\n  0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,\n    0xd88f84d,\n  0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,\n    0xd56fb71,\n  0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,\n    0xd24fc87,\n  0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,\n    0xcf2fb96,\n  0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,\n    0xcc0f8a5,\n  0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,\n    0xc8ef3bd,\n  0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,\n    0xc5cece5,\n  0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,\n    0xc2ae425,\n  0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,\n    0xbf8d985,\n  0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,\n    0xbc6cd0c,\n  0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,\n    0xb94bec2,\n  0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,\n    0xb62aeaf,\n  0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,\n    0xb309cdb,\n  0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,\n    0xafe894d,\n  0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,\n    0xacc740c,\n  0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,\n    0xa9a5d22,\n  0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,\n    0xa684495,\n  0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,\n    0xa362a6d,\n  0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,\n    0xa040eb1,\n  0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,\n    0x9d1f16b,\n  0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,\n    0x99fd2a0,\n  0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,\n    0x96db25a,\n  0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,\n    0x93b90a0,\n  0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,\n    0x9096d79,\n  0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,\n    0x8d748ed,\n  0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,\n    0x8a52304,\n  0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,\n    0x872fbc6,\n  0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,\n    0x840d33b,\n  0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,\n    0x80ea969,\n  0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,\n    0x7dc7e5a,\n  0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,\n    0x7aa5214,\n  0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,\n    0x77824a0,\n  0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,\n    0x745f604,\n  0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,\n    0x713c64a,\n  0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,\n    0x6e19578,\n  0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,\n    0x6af6396,\n  0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,\n    0x67d30ad,\n  0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,\n    0x64afcc3,\n  0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,\n    0x618c7e1,\n  0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,\n    0x5e6920e,\n  0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,\n    0x5b45b53,\n  0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,\n    0x58223b6,\n  0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,\n    0x54feb3f,\n  0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,\n    0x51db1f7,\n  0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,\n    0x4eb77e5,\n  0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,\n    0x4b93d11,\n  0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,\n    0x4870182,\n  0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,\n    0x454c541,\n  0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,\n    0x4228854,\n  0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,\n    0x3f04ac4,\n  0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,\n    0x3be0c99,\n  0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,\n    0x38bcdda,\n  0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,\n    0x3598e8f,\n  0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,\n    0x3274ec0,\n  0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,\n    0x2f50e74,\n  0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,\n    0x2c2cdb4,\n  0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,\n    0x2908c87,\n  0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,\n    0x25e4af4,\n  0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,\n    0x22c0904,\n  0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,\n    0x1f9c6be,\n  0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,\n    0x1c7842a,\n  0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,\n    0x1954150,\n  0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,\n    0x162fe37,\n  0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,\n    0x130bae7,\n  0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,\n    0xfe7769,\n  0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,\n    0xcc33c3,\n  0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,\n    0x99effe,\n  0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,\n    0x67ac21,\n  0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,\n    0x356835,\n  0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,\n\n};\n\n/**    \n * @brief  Initialization function for the Q31 DCT4/IDCT4.   \n * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.   \n * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure   \n * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure   \n * @param[in]     N          length of the DCT4.   \n * @param[in]     Nby2       half of the length of the DCT4.   \n * @param[in]     normalize  normalizing factor.   \n * @return\t\t  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   \n * \\par Normalizing factor:    \n * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    \n * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:    \n * \\image html dct4NormalizingQ31Table.gif    \n */\n\narm_status arm_dct4_init_q31(\n  arm_dct4_instance_q31 * S,\n  arm_rfft_instance_q31 * S_RFFT,\n  arm_cfft_radix4_instance_q31 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q31_t normalize)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /* Initializing the pointer array with the weight table base addresses of different lengths */\n  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,\n    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192\n  };\n\n  /* Initializing the pointer array with the cos factor table base addresses of different lengths */\n  q31_t *pCosFactor[4] =\n    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,\n    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192\n  };\n\n  /* Initialize the DCT4 length */\n  S->N = N;\n\n  /* Initialize the half of DCT4 length */\n  S->Nby2 = Nby2;\n\n  /* Initialize the DCT4 Normalizing factor */\n  S->normalize = normalize;\n\n  /* Initialize Real FFT Instance */\n  S->pRfft = S_RFFT;\n\n  /* Initialize Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  switch (N)\n  {\n    /* Initialize the table modifier values */\n  case 8192u:\n    S->pTwiddle = twiddlePtr[3];\n    S->pCosFactor = pCosFactor[3];\n    break;\n  case 2048u:\n    S->pTwiddle = twiddlePtr[2];\n    S->pCosFactor = pCosFactor[2];\n    break;\n  case 512u:\n    S->pTwiddle = twiddlePtr[1];\n    S->pCosFactor = pCosFactor[1];\n    break;\n  case 128u:\n    S->pTwiddle = twiddlePtr[0];\n    S->pCosFactor = pCosFactor[0];\n    break;\n  default:\n    status = ARM_MATH_ARGUMENT_ERROR;\n  }\n\n  /* Initialize the RFFT/RIFFT Function */\n  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);\n\n  /* return the status of DCT4 Init function */\n  return (status);\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_q15.c    \n*    \n* Description:\tProcessing function of DCT4 & IDCT4 Q15.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 DCT4/IDCT4.   \n * @param[in]       *S             points to an instance of the Q15 DCT4 structure.   \n * @param[in]       *pState        points to state buffer.   \n * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   \n * @return none.   \n *     \n * \\par Input an output formats:    \n * Internally inputs are downscaled in the RFFT process function to avoid overflows.    \n * Number of bits downscaled, depends on the size of the transform.    \n * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     \n *    \n * \\image html dct4FormatsQ15Table.gif    \n */\n\nvoid arm_dct4_q15(\n  const arm_dct4_instance_q15 * S,\n  q15_t * pState,\n  q15_t * pInlineBuffer)\n{\n  uint32_t i;                                    /* Loop counter */\n  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */\n  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */\n  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */\n  q15_t in;                                      /* Temporary variable */\n\n\n  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    \n   * along with some pre-processing and post-processing.    \n   * Computational procedure is explained as follows:    \n   * (a) Pre-processing involves multiplying input with cos factor,    \n   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    \n   *              where,    \n   *                 r(n) -- output of preprocessing    \n   *                 u(n) -- input to preprocessing(actual Source buffer)    \n   * (b) Calculation of DCT2 using FFT is divided into three steps:    \n   *                  Step1: Re-ordering of even and odd elements of input.    \n   *                  Step2: Calculating FFT of the re-ordered input.    \n   *                  Step3: Taking the real part of the product of FFT output and weights.    \n   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    \n   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *                        where,    \n   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    \n   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    \n   */\n\n        /*-------- Pre-processing ------------*/\n  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */\n  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);\n  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);\n\n  /* ----------------------------------------------------------------    \n   * Step1: Re-ordering of even and odd elements as    \n   *             pState[i] =  pInlineBuffer[2*i] and    \n   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    \n   ---------------------------------------------------------------------*/\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */\n  pS2 = pState + (S->N - 1u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */\n  i = (uint32_t) S->Nby2 >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = (uint32_t) S->N >> 2u;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.    \n   * Compute 4 outputs at a time */\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);\n\n /*----------------------------------------------------------------------    \n  *  Step3: Multiply the FFT output with the weights.    \n  *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);\n\n  /* The output of complex multiplication is in 3.13 format.    \n   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */\n  arm_shift_q15(pState, 2, pState, S->N * 2);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */\n  i = ((uint32_t) S->N - 1u) >> 2u;\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ >> 1u;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  i = ((uint32_t) S->N - 1u) % 0x4u;\n\n  while(i > 0u)\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n\n   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = (uint32_t) S->N >> 2u;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));\n\n    in = *pbuff;\n    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));\n\n    in = *pbuff;\n    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));\n\n    in = *pbuff;\n    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Initializing the loop counter to N/2 */\n  i = (uint32_t) S->Nby2;\n\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter */\n  i = (uint32_t) S->N;\n\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);\n\n /*----------------------------------------------------------------------    \n  *  Step3: Multiply the FFT output with the weights.    \n  *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);\n\n  /* The output of complex multiplication is in 3.13 format.    \n   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */\n  arm_shift_q15(pState, 2, pState, S->N * 2);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* Initializing the loop counter */\n  i = ((uint32_t) S->N - 1u);\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ >> 1u;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  do\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter */\n  i = (uint32_t) S->N;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_dct4_q31.c    \n*    \n* Description:\tProcessing function of DCT4 & IDCT4 Q31.    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @addtogroup DCT4_IDCT4    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 DCT4/IDCT4.   \n * @param[in]       *S             points to an instance of the Q31 DCT4 structure.   \n * @param[in]       *pState        points to state buffer.   \n * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   \n * @return none.   \n * \\par Input an output formats:    \n * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,    \n * as the conversion from DCT2 to DCT4 involves one subtraction.    \n * Internally inputs are downscaled in the RFFT process function to avoid overflows.    \n * Number of bits downscaled, depends on the size of the transform.    \n * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     \n *    \n * \\image html dct4FormatsQ31Table.gif    \n */\n\nvoid arm_dct4_q31(\n  const arm_dct4_instance_q31 * S,\n  q31_t * pState,\n  q31_t * pInlineBuffer)\n{\n  uint16_t i;                                    /* Loop counter */\n  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */\n  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */\n  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */\n  q31_t in;                                      /* Temporary variable */\n\n\n  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    \n   * along with some pre-processing and post-processing.    \n   * Computational procedure is explained as follows:    \n   * (a) Pre-processing involves multiplying input with cos factor,    \n   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    \n   *              where,    \n   *                 r(n) -- output of preprocessing    \n   *                 u(n) -- input to preprocessing(actual Source buffer)    \n   * (b) Calculation of DCT2 using FFT is divided into three steps:    \n   *                  Step1: Re-ordering of even and odd elements of input.    \n   *                  Step2: Calculating FFT of the re-ordered input.    \n   *                  Step3: Taking the real part of the product of FFT output and weights.    \n   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    \n   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *                        where,    \n   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    \n   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    \n   */\n\n        /*-------- Pre-processing ------------*/\n  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */\n  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);\n  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);\n\n  /* ----------------------------------------------------------------    \n   * Step1: Re-ordering of even and odd elements as    \n   *             pState[i] =  pInlineBuffer[2*i] and    \n   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    \n   ---------------------------------------------------------------------*/\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */\n  pS2 = pState + (S->N - 1u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */\n  i = S->Nby2 >> 2u;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    *pS1++ = *pbuff++;\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = S->N >> 2u;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.    \n   * Compute 4 outputs at a time */\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);\n\n  /*----------------------------------------------------------------------    \n   *  Step3: Multiply the FFT output with the weights.    \n   *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);\n\n  /* The output of complex multiplication is in 3.29 format.    \n   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */\n  arm_shift_q31(pState, 2, pState, S->N * 2);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */\n  i = (S->N - 1u) >> 2u;\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ >> 1u;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    \n   ** a second loop below computes the remaining 1 to 3 samples. */\n  do\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    \n   ** No loop unrolling is used. */\n  i = (S->N - 1u) % 0x4u;\n\n  while(i > 0u)\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n\n        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter to N/4 instead of N for loop unrolling */\n  i = S->N >> 2u;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));\n\n    in = *pbuff;\n    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));\n\n    in = *pbuff;\n    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));\n\n    in = *pbuff;\n    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  /* Initializing the loop counter to N/2 */\n  i = S->Nby2;\n\n  do\n  {\n    /* Re-ordering of even and odd elements */\n    /* pState[i] =  pInlineBuffer[2*i] */\n    *pS1++ = *pbuff++;\n    /* pState[N-i-1] = pInlineBuffer[2*i+1] */\n    *pS2-- = *pbuff++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n  /* pbuff initialized to input buffer */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Initializing the loop counter */\n  i = S->N;\n\n  do\n  {\n    /* Writing the re-ordered output back to inplace input buffer */\n    *pbuff++ = *pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n\n  /* ---------------------------------------------------------    \n   *     Step2: Calculate RFFT for N-point input    \n   * ---------------------------------------------------------- */\n  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */\n  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);\n\n  /*----------------------------------------------------------------------    \n   *  Step3: Multiply the FFT output with the weights.    \n   *----------------------------------------------------------------------*/\n  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);\n\n  /* The output of complex multiplication is in 3.29 format.    \n   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */\n  arm_shift_q31(pState, 2, pState, S->N * 2);\n\n  /* ----------- Post-processing ---------- */\n  /* DCT-IV can be obtained from DCT-II by the equation,    \n   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    \n   *       Hence, Y4(0) = Y2(0)/2  */\n  /* Getting only real part from the output and Converting to DCT-IV */\n\n  /* pbuff initialized to input buffer. */\n  pbuff = pInlineBuffer;\n\n  /* pS1 initialized to pState */\n  pS1 = pState;\n\n  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */\n  in = *pS1++ >> 1u;\n  /* input buffer acts as inplace, so output values are stored in the input itself. */\n  *pbuff++ = in;\n\n  /* pState pointer is incremented twice as the real values are located alternatively in the array */\n  pS1++;\n\n  /* Initializing the loop counter */\n  i = (S->N - 1u);\n\n  while(i > 0u)\n  {\n    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */\n    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */\n    in = *pS1++ - in;\n    *pbuff++ = in;\n    /* points to the next real value */\n    pS1++;\n\n    /* Decrement the loop counter */\n    i--;\n  }\n\n\n        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/\n\n  /* Initializing the loop counter */\n  i = S->N;\n\n  /* pbuff initialized to the pInlineBuffer(now contains the output values) */\n  pbuff = pInlineBuffer;\n\n  do\n  {\n    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */\n    in = *pbuff;\n    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));\n\n    /* Decrement the loop counter */\n    i--;\n  } while(i > 0u);\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n/**    \n   * @} end of DCT4_IDCT4 group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_f32.c    \n*    \n* Description:\tRFFT & RIFFT Floating point process function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nextern void arm_radix4_butterfly_f32(\n    float32_t * pSrc,\n    uint16_t fftLen,\n    float32_t * pCoef,\n    uint16_t twidCoefModifier);\n\nextern void arm_radix4_butterfly_inverse_f32(\n    float32_t * pSrc,\n    uint16_t fftLen,\n    float32_t * pCoef,\n    uint16_t twidCoefModifier,\n    float32_t onebyfftLen);\n\nextern void arm_bitreversal_f32(\n    float32_t * pSrc,\n    uint16_t fftSize,\n    uint16_t bitRevFactor,\n    uint16_t * pBitRevTab);\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/*--------------------------------------------------------------------    \n *\t\tInternal functions prototypes    \n *--------------------------------------------------------------------*/\n\nvoid arm_split_rfft_f32(\n  float32_t * pSrc,\n  uint32_t fftLen,\n  float32_t * pATable,\n  float32_t * pBTable,\n  float32_t * pDst,\n  uint32_t modifier);\nvoid arm_split_rifft_f32(\n  float32_t * pSrc,\n  uint32_t fftLen,\n  float32_t * pATable,\n  float32_t * pBTable,\n  float32_t * pDst,\n  uint32_t modifier);\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n/**    \n * @brief Processing function for the floating-point RFFT/RIFFT.   \n * @deprecated Do not use this function.  It has been superceded by \\ref arm_rfft_fast_f32 and will be removed\n * in the future.\n * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.   \n * @param[in]  *pSrc points to the input buffer.   \n * @param[out] *pDst points to the output buffer.   \n * @return none.   \n */\n\nvoid arm_rfft_f32(\n  const arm_rfft_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst)\n{\n  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;\n\n\n  /* Calculation of Real IFFT of input */\n  if(S->ifftFlagR == 1u)\n  {\n    /*  Real IFFT core process */\n    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n\n\n    /* Complex radix-4 IFFT process */\n    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,\n                                     S_CFFT->pTwiddle,\n                                     S_CFFT->twidCoefModifier,\n                                     S_CFFT->onebyfftLen);\n\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_f32(pDst, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n  }\n  else\n  {\n\n    /* Calculation of RFFT of input */\n\n    /* Complex radix-4 FFT process */\n    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,\n                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);\n\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n\n\n    /*  Real FFT core process */\n    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n  }\n\n}\n\n/**    \n   * @} end of RealFFT group    \n   */\n\n/**    \n * @brief  Core Real FFT process    \n * @param[in]   *pSrc \t\t\t\tpoints to the input buffer.    \n * @param[in]   fftLen  \t\t\tlength of FFT.    \n * @param[in]   *pATable \t\t\tpoints to the twiddle Coef A buffer.    \n * @param[in]   *pBTable \t\t\tpoints to the twiddle Coef B buffer.    \n * @param[out]  *pDst \t\t\t\tpoints to the output buffer.    \n * @param[in]   modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.    \n */\n\nvoid arm_split_rfft_f32(\n  float32_t * pSrc,\n  uint32_t fftLen,\n  float32_t * pATable,\n  float32_t * pBTable,\n  float32_t * pDst,\n  uint32_t modifier)\n{\n  uint32_t i;                                    /* Loop Counter */\n  float32_t outR, outI;                          /* Temporary variables for output */\n  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */\n  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */\n  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */\n  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */\n\n  /* Init coefficient pointers */\n  pCoefA = &pATable[modifier * 2u];\n  pCoefB = &pBTable[modifier * 2u];\n\n  i = fftLen - 1u;\n\n  while(i > 0u)\n  {\n    /*    \n       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    \n       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    \n       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n     */\n\n    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */\n\n    /* read pATable[2 * i] */\n    CoefA1 = *pCoefA++;\n    /* pATable[2 * i + 1] */\n    CoefA2 = *pCoefA;\n\n    /* pSrc[2 * i] * pATable[2 * i] */\n    outR = *pSrc1 * CoefA1;\n    /* pSrc[2 * i] * CoefA2 */\n    outI = *pSrc1++ * CoefA2;\n\n    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */\n    outR -= (*pSrc1 + *pSrc2) * CoefA2;\n    /* pSrc[2 * i + 1] * CoefA1 */\n    outI += *pSrc1++ * CoefA1;\n\n    CoefB1 = *pCoefB;\n\n    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */\n    outI -= *pSrc2-- * CoefB1;\n    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */\n    outI -= *pSrc2 * CoefA2;\n\n    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */\n    outR += *pSrc2-- * CoefB1;\n\n    /* write output */\n    *pDst1++ = outR;\n    *pDst1++ = outI;\n\n    /* write complex conjugate output */\n    *pDst2-- = -outI;\n    *pDst2-- = outR;\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (modifier * 2u);\n    pCoefA = pCoefA + ((modifier * 2u) - 1u);\n\n    i--;\n\n  }\n\n  pDst[2u * fftLen] = pSrc[0] - pSrc[1];\n  pDst[(2u * fftLen) + 1u] = 0.0f;\n\n  pDst[0] = pSrc[0] + pSrc[1];\n  pDst[1] = 0.0f;\n\n}\n\n\n/**    \n * @brief  Core Real IFFT process    \n * @param[in]   *pSrc \t\t\t\tpoints to the input buffer.    \n * @param[in]   fftLen  \t\t\tlength of FFT.   \n * @param[in]   *pATable \t\t\tpoints to the twiddle Coef A buffer.   \n * @param[in]   *pBTable \t\t\tpoints to the twiddle Coef B buffer.   \n * @param[out]  *pDst \t\t\t\tpoints to the output buffer.   \n * @param[in]   modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.    \n * @return none.    \n */\n\nvoid arm_split_rifft_f32(\n  float32_t * pSrc,\n  uint32_t fftLen,\n  float32_t * pATable,\n  float32_t * pBTable,\n  float32_t * pDst,\n  uint32_t modifier)\n{\n  float32_t outR, outI;                          /* Temporary variables for output */\n  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */\n  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */\n  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];\n\n  pCoefA = &pATable[0];\n  pCoefB = &pBTable[0];\n\n  while(fftLen > 0u)\n  {\n    /*    \n       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n\n       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    \n\n     */\n\n    CoefA1 = *pCoefA++;\n    CoefA2 = *pCoefA;\n\n    /* outR = (pSrc[2 * i] * CoefA1 */\n    outR = *pSrc1 * CoefA1;\n\n    /* - pSrc[2 * i] * CoefA2 */\n    outI = -(*pSrc1++) * CoefA2;\n\n    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */\n    outR += (*pSrc1 + *pSrc2) * CoefA2;\n\n    /* pSrc[2 * i + 1] * CoefA1 */\n    outI += (*pSrc1++) * CoefA1;\n\n    CoefB1 = *pCoefB;\n\n    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */\n    outI -= *pSrc2-- * CoefB1;\n\n    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */\n    outR += *pSrc2 * CoefB1;\n\n    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */\n    outI += *pSrc2-- * CoefA2;\n\n    /* write output */\n    *pDst++ = outR;\n    *pDst++ = outI;\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (modifier * 2u);\n    pCoefA = pCoefA + ((modifier * 2u) - 1u);\n\n    /* Decrement loop count */\n    fftLen--;\n  }\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c",
    "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.\n*\n* $Date:        17. January 2013\n* $Revision: \tV1.4.1\n*\n* Project: \t    CMSIS DSP Library\n* Title:\t    arm_rfft_f32.c\n*\n* Description:\tRFFT & RIFFT Floating point process function\n*\n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the\n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid stage_rfft_f32(\n  arm_rfft_fast_instance_f32 * S,\n  float32_t * p, float32_t * pOut)\n{\n   uint32_t  k;\t\t\t\t\t\t\t\t   /* Loop Counter                     */\n   float32_t twR, twI;\t\t\t\t\t\t   /* RFFT Twiddle coefficients        */\n   float32_t * pCoeff = S->pTwiddleRFFT;  /* Points to RFFT Twiddle factors   */\n   float32_t *pA = p;\t\t\t\t\t\t   /* increasing pointer               */\n   float32_t *pB = p;\t\t\t\t\t\t   /* decreasing pointer               */\n   float32_t xAR, xAI, xBR, xBI;\t\t\t\t/* temporary variables              */\n   float32_t t1a, t1b;\t\t\t\t         /* temporary variables              */\n   float32_t p0, p1, p2, p3;\t\t\t\t   /* temporary variables              */\n\n\n   k = (S->Sint).fftLen - 1;\t\t\t\t\t\n\n   /* Pack first and last sample of the frequency domain together */\n\n   xBR = pB[0];\n   xBI = pB[1];\n   xAR = pA[0];\n   xAI = pA[1];\n\n   twR = *pCoeff++ ;\n   twI = *pCoeff++ ;\n   \n   // U1 = XA(1) + XB(1); % It is real\n   t1a = xBR + xAR  ;\n   \n   // U2 = XB(1) - XA(1); % It is imaginary\n   t1b = xBI + xAI  ;\n\n   // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);\n   // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);\n   *pOut++ = 0.5f * ( t1a + t1b );\n   *pOut++ = 0.5f * ( t1a - t1b );\n\n   // XA(1) = 1/2*( U1 - imag(U2) +  i*( U1 +imag(U2) ));\n   pB  = p + 2*k;\n   pA += 2;\n\n   do\n   {\n      /*\n         function X = my_split_rfft(X, ifftFlag)\n         % X is a series of real numbers\n         L  = length(X);\n         XC = X(1:2:end) +i*X(2:2:end);\n         XA = fft(XC);\n         XB = conj(XA([1 end:-1:2]));\n         TW = i*exp(-2*pi*i*[0:L/2-1]/L).';\n         for l = 2:L/2\n            XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));\n         end\n         XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));\n         X = XA;\n      */\n\n      xBI = pB[1];\n      xBR = pB[0];\n      xAR = pA[0];\n      xAI = pA[1];\n\n      twR = *pCoeff++;\n      twI = *pCoeff++;\n\n      t1a = xBR - xAR ;\n      t1b = xBI + xAI ;\n\n      // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);\n      // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);\n      p0 = twR * t1a;\n      p1 = twI * t1a;\n      p2 = twR * t1b;\n      p3 = twI * t1b;\n\n      *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR\n      *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI\n\n      pA += 2;\n      pB -= 2;\n      k--;\n   } while(k > 0u);\n}\n\n/* Prepares data for inverse cfft */\nvoid merge_rfft_f32(\narm_rfft_fast_instance_f32 * S,\nfloat32_t * p, float32_t * pOut)\n{\n   uint32_t  k;\t\t\t\t\t\t\t\t/* Loop Counter                     */\n   float32_t twR, twI;\t\t\t\t\t\t/* RFFT Twiddle coefficients        */\n   float32_t *pCoeff = S->pTwiddleRFFT;\t\t/* Points to RFFT Twiddle factors   */\n   float32_t *pA = p;\t\t\t\t\t\t/* increasing pointer               */\n   float32_t *pB = p;\t\t\t\t\t\t/* decreasing pointer               */\n   float32_t xAR, xAI, xBR, xBI;\t\t\t/* temporary variables              */\n   float32_t t1a, t1b, r, s, t, u;\t\t\t/* temporary variables              */\n\n   k = (S->Sint).fftLen - 1;\t\t\t\t\t\n\n   xAR = pA[0];\n   xAI = pA[1];\n\n   pCoeff += 2 ;\n\n   *pOut++ = 0.5f * ( xAR + xAI );\n   *pOut++ = 0.5f * ( xAR - xAI );\n\n   pB  =  p + 2*k ;\n   pA +=  2\t   ;\n\n   while(k > 0u)\n   {\n      /* G is half of the frequency complex spectrum */\n      //for k = 2:N\n      //    Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));\n      xBI =   pB[1]    ;\n      xBR =   pB[0]    ;\n      xAR =  pA[0];\n      xAI =  pA[1];\n\n      twR = *pCoeff++;\n      twI = *pCoeff++;\n\n      t1a = xAR - xBR ;\n      t1b = xAI + xBI ;\n\n      r = twR * t1a;\n      s = twI * t1b;\n      t = twI * t1a;\n      u = twR * t1b;\n\n      // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);\n      // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);\n      *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR\n      *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI\n\n      pA += 2;\n      pB -= 2;\n      k--;\n   }\n\n}\n\n/**\n* @ingroup groupTransforms\n*/\n\n/**\n * @defgroup Fast Real FFT Functions\n *\n * \\par\n * The CMSIS DSP library includes specialized algorithms for computing the\n * FFT of real data sequences.  The FFT is defined over complex data but\n * in many applications the input is real.  Real FFT algorithms take advantage\n * of the symmetry properties of the FFT and have a speed advantage over complex\n * algorithms of the same length.\n * \\par\n * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.\n * \\par\n * The real length N forward FFT of a sequence is computed using the steps shown below.\n * \\par\n * \\image html RFFT.gif \"Real Fast Fourier Transform\"\n * \\par\n * The real sequence is initially treated as if it were complex to perform a CFFT.\n * Later, a processing stage reshapes the data to obtain half of the frequency spectrum\n * in complex format. Except the first complex number that contains the two real numbers\n * X[0] and X[N/2] all the data is complex. In other words, the first complex sample\n * contains two real values packed.\n * \\par\n * The input for the inverse RFFT should keep the same format as the output of the \n * forward RFFT. A first processing stage pre-process the data to later perform an\n * inverse CFFT.\n * \\par    \n * \\image html RIFFT.gif \"Real Inverse Fast Fourier Transform\"    \n * \\par    \n * The algorithms for floating-point, Q15, and Q31 data are slightly different\n * and we describe each algorithm in turn.\n * \\par Floating-point\n * The main functions are arm_rfft_fast_f32()\n * and arm_rfft_fast_init_f32().  The older functions\n * arm_rfft_f32() and arm_rfft_init_f32() have been\n * deprecated but are still documented.\n * \\par\n * The FFT of a real N-point sequence has even symmetry in the frequency\n * domain.  The second half of the data equals the conjugate of the first half\n * flipped in frequency:\n * 
\n *X[0] - real data\n *X[1] - complex data\n *X[2] - complex data\n *... \n *X[fftLen/2-1] - complex data\n *X[fftLen/2] - real data\n *X[fftLen/2+1] - conjugate of X[fftLen/2-1]\n *X[fftLen/2+2] - conjugate of X[fftLen/2-2]\n *... \n *X[fftLen-1] - conjugate of X[1]\n * 
\n * Looking at the data, we see that we can uniquely represent the FFT using only\n * 
\n *N/2+1 samples:\n *X[0] - real data\n *X[1] - complex data\n *X[2] - complex data\n *... \n *X[fftLen/2-1] - complex data\n *X[fftLen/2] - real data\n * 
\n * Looking more closely we see that the first and last samples are real valued.\n * They can be packed together and we can thus represent the FFT of an N-point\n * real sequence by N/2 complex values:\n * 
\n *X[0],X[N/2] - packed real data: X[0] + jX[N/2]\n *X[1] - complex data\n *X[2] - complex data\n *... \n *X[fftLen/2-1] - complex data\n * 
\n * The real FFT functions pack the frequency domain data in this fashion.  The\n * forward transform outputs the data in this form and the inverse transform\n * expects input data in this form.  The function always performs the needed\n * bitreversal so that the input and output data is always in normal order.  The \n * functions support lengths of [32, 64, 128, ..., 4096] samples.\n * \\par\n * The forward and inverse real FFT functions apply the standard FFT scaling; no\n * scaling on the forward transform and 1/fftLen scaling on the inverse\n * transform.\n * \\par Q15 and Q31\n * The real algorithms are defined in a similar manner and utilize N/2 complex\n * transforms behind the scenes.  In the case of fixed-point data, a radix-4\n * complex transform is performed and this limits the allows sequence lengths to\n * 128, 512, and 2048 samples.\n * \\par\n * TBD.  We need to document input and output order of data.\n * \\par\n * The complex transforms used internally include scaling to prevent fixed-point\n * overflows.  The overall scaling equals 1/(fftLen/2).\n * \\par\n * A separate instance structure must be defined for each transform used but \n * twiddle factor and bit reversal tables can be reused.\n * \\par\n * There is also an associated initialization function for each data type. \n * The initialization function performs the following operations:\n * - Sets the values of the internal structure fields.   \n * - Initializes twiddle factor table and bit reversal table pointers.\n * - Initializes the internal complex FFT data structure.\n * \\par   \n * Use of the initialization function is optional.   \n * However, if the initialization function is used, then the instance structure \n * cannot be placed into a const data section. To place an instance structure \n * into a const data section, the instance structure should be manually \n * initialized as follows:\n * 
\n *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    \n *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    \n * 
\n * where fftLenReal is the length of the real transform;\n * fftLenBy2 length of  the internal complex transform.\n * ifftFlagR Selects forward (=0) or inverse (=1) transform.\n * bitReverseFlagR Selects bit reversed output (=0) or normal order\n * output (=1).\n * twidCoefRModifier stride modifier for the twiddle factor table.\n * The value is based on the FFT length;\n * pTwiddleARealpoints to the A array of twiddle coefficients; \n * pTwiddleBRealpoints to the B array of twiddle coefficients;    \n * pCfft points to the CFFT Instance structure. The CFFT structure\n * must also be initialized.  Refer to arm_cfft_radix4_f32() for details regarding    \n * static initialization of the complex FFT instance structure.    \n */\n\n/**\n* @addtogroup RealFFT\n* @{\n*/\n\n/**\n* @brief Processing function for the floating-point real FFT.\n* @param[in]  *S              points to an arm_rfft_fast_instance_f32 structure.\n* @param[in]  *p              points to the input buffer.\n* @param[in]  *pOut           points to an arm_rfft_fast_instance_f32 structure.\n* @param[in]  ifftFlag        RFFT if flag is 0, RIFFT if flag is 1\n* @return none.\n*/\n\nvoid arm_rfft_fast_f32(\narm_rfft_fast_instance_f32 * S,\nfloat32_t * p, float32_t * pOut,\nuint8_t ifftFlag)\n{\n   arm_cfft_instance_f32 * Sint = &(S->Sint);\n   Sint->fftLen = S->fftLenRFFT / 2;\n\n   /* Calculation of Real FFT */\n   if(ifftFlag)\n   {\n      /*  Real FFT comression */\n      merge_rfft_f32(S, p, pOut);\n\n      /* Complex radix-4 IFFT process */\n      arm_cfft_f32( Sint, pOut, ifftFlag, 1);\n   }\n   else\n   {\n      /* Calculation of RFFT of input */\n      arm_cfft_f32( Sint, p, ifftFlag, 1);\n   \n      /*  Real FFT extraction */\n      stage_rfft_f32(S, p, pOut);\n   }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_cfft_init_f32.c   \n*    \n* Description:\tSplit Radix Decimation in Frequency CFFT Floating point processing function   \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.   \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n/**   \n * @ingroup groupTransforms   \n */\n\n/**   \n * @addtogroup RealFFT   \n * @{   \n */\n\n/**   \n* @brief  Initialization function for the floating-point real FFT.  \n* @param[in,out] *S             points to an arm_rfft_fast_instance_f32 structure.\n* @param[in]     fftLen         length of the Real Sequence.  \n* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  \n*   \n* \\par Description:  \n* \\par   \n* The parameter ifftFlag controls whether a forward or inverse transform is computed.   \n* Set(=1) ifftFlag for calculation of CIFFT otherwise  RFFT is calculated  \n* \\par   \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par   \n* The parameter fftLen\tSpecifies length of RFFT/CIFFT process. Supported FFT Lengths are 16, 32, 64, 128, 256, 512, 1024, 2048, 4096.   \n* \\par   \n* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   \n*/\narm_status arm_rfft_fast_init_f32(\n  arm_rfft_fast_instance_f32 * S,\n  uint16_t fftLen)\n{\n  arm_cfft_instance_f32 * Sint;\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n  /*  Initialise the FFT length */\n  Sint = &(S->Sint);\n  Sint->fftLen = fftLen/2;\n  S->fftLenRFFT = fftLen;\n  /*  Initialise the Twiddle coefficient pointer */\n  //  S->pTwiddle = (float32_t *) twiddleCoef;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (Sint->fftLen)\n  {\n  case 4096u:\n    /*  Initializations of structure parameters for 4096 point FFT */\n    /*  Initialise the bit reversal table length */\n    Sint->bitRevLength = ARMBITREVINDEXTABLE4096_TABLE_LENGTH;\n    /*  Initialise the bit reversal table pointer */\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable4096;\n    /*  Initialise the 1/fftLen Value */\n    break;\n  case 2048u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;\n    break;\n  case 1024u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;\n    break;\n  case 512u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;\n    break;\n  case 256u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;\n    break;\n  case 128u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;\n    break;\n  case 64u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;\n    break;\n  case 32u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;\n    break;\n  case 16u:\n    Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;\n    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;\n    break;\n  default:\n    /*  Reporting argument error if fftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  return (status);\n}\n\n/**   \n * @} end of RealFFT group   \n */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_init_f32.c    \n*    \n* Description:\tRFFT & RIFFT Floating point initialisation function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n/**    \n* \\par    \n* Generation of realCoefA array:    \n* \\par    \n* \tn = 4096    \n* 
for (i = 0; i < n; i++)    \n*  {    \n*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n*  } 
    \n*/\n\n\n\nstatic const float32_t realCoefA[8192] = {\n  0.500000000000000f, -0.500000000000000f, 0.499616503715515f,\n    -0.499999850988388f,\n  0.499233007431030f, -0.499999403953552f, 0.498849511146545f,\n    -0.499998688697815f,\n  0.498466014862061f, -0.499997645616531f, 0.498082518577576f,\n    -0.499996334314346f,\n  0.497699022293091f, -0.499994695186615f, 0.497315555810928f,\n    -0.499992787837982f,\n  0.496932059526443f, -0.499990582466125f, 0.496548563241959f,\n    -0.499988079071045f,\n  0.496165096759796f, -0.499985307455063f, 0.495781600475311f,\n    -0.499982208013535f,\n  0.495398133993149f, -0.499978810548782f, 0.495014637708664f,\n    -0.499975144863129f,\n  0.494631171226501f, -0.499971181154251f, 0.494247704744339f,\n    -0.499966919422150f,\n  0.493864238262177f, -0.499962359666824f, 0.493480771780014f,\n    -0.499957501888275f,\n  0.493097305297852f, -0.499952346086502f, 0.492713838815689f,\n    -0.499946922063828f,\n  0.492330402135849f, -0.499941170215607f, 0.491946935653687f,\n    -0.499935150146484f,\n  0.491563498973846f, -0.499928832054138f, 0.491180062294006f,\n    -0.499922215938568f,\n  0.490796625614166f, -0.499915301799774f, 0.490413218736649f,\n    -0.499908089637756f,\n  0.490029782056808f, -0.499900579452515f, 0.489646375179291f,\n    -0.499892801046371f,\n  0.489262968301773f, -0.499884694814682f, 0.488879561424255f,\n    -0.499876320362091f,\n  0.488496154546738f, -0.499867647886276f, 0.488112777471542f,\n    -0.499858677387238f,\n  0.487729400396347f, -0.499849408864975f, 0.487346023321152f,\n    -0.499839842319489f,\n  0.486962646245956f, -0.499830007553101f, 0.486579269170761f,\n    -0.499819844961166f,\n  0.486195921897888f, -0.499809414148331f, 0.485812574625015f,\n    -0.499798685312271f,\n  0.485429257154465f, -0.499787658452988f, 0.485045909881592f,\n    -0.499776333570480f,\n  0.484662592411041f, -0.499764710664749f, 0.484279274940491f,\n    -0.499752789735794f,\n  0.483895987272263f, -0.499740600585938f, 0.483512699604034f,\n    -0.499728083610535f,\n  0.483129411935806f, -0.499715298414230f, 0.482746154069901f,\n    -0.499702215194702f,\n  0.482362866401672f, -0.499688833951950f, 0.481979638338089f,\n    -0.499675154685974f,\n  0.481596380472183f, -0.499661177396774f, 0.481213152408600f,\n    -0.499646931886673f,\n  0.480829954147339f, -0.499632388353348f, 0.480446726083755f,\n    -0.499617516994476f,\n  0.480063527822495f, -0.499602377414703f, 0.479680359363556f,\n    -0.499586939811707f,\n  0.479297190904617f, -0.499571204185486f, 0.478914022445679f,\n    -0.499555170536041f,\n  0.478530883789063f, -0.499538868665695f, 0.478147745132446f,\n    -0.499522238969803f,\n  0.477764606475830f, -0.499505341053009f, 0.477381497621536f,\n    -0.499488145112991f,\n  0.476998418569565f, -0.499470651149750f, 0.476615339517593f,\n    -0.499452859163284f,\n  0.476232260465622f, -0.499434769153595f, 0.475849211215973f,\n    -0.499416410923004f,\n  0.475466161966324f, -0.499397724866867f, 0.475083142518997f,\n    -0.499378770589828f,\n  0.474700123071671f, -0.499359518289566f, 0.474317133426666f,\n    -0.499339967966080f,\n  0.473934143781662f, -0.499320119619370f, 0.473551183938980f,\n    -0.499299973249435f,\n  0.473168224096298f, -0.499279528856277f, 0.472785294055939f,\n    -0.499258816242218f,\n  0.472402364015579f, -0.499237775802612f, 0.472019463777542f,\n    -0.499216467142105f,\n  0.471636593341827f, -0.499194860458374f, 0.471253722906113f,\n    -0.499172955751419f,\n  0.470870882272720f, -0.499150782823563f, 0.470488041639328f,\n    -0.499128282070160f,\n  0.470105201005936f, -0.499105513095856f, 0.469722419977188f,\n    -0.499082416296005f,\n  0.469339638948441f, -0.499059051275253f, 0.468956857919693f,\n    -0.499035388231277f,\n  0.468574106693268f, -0.499011427164078f, 0.468191385269165f,\n    -0.498987197875977f,\n  0.467808693647385f, -0.498962640762329f, 0.467426002025604f,\n    -0.498937815427780f,\n  0.467043310403824f, -0.498912662267685f, 0.466660678386688f,\n    -0.498887240886688f,\n  0.466278046369553f, -0.498861521482468f, 0.465895414352417f,\n    -0.498835533857346f,\n  0.465512841939926f, -0.498809218406677f, 0.465130269527435f,\n    -0.498782604932785f,\n  0.464747726917267f, -0.498755723237991f, 0.464365184307098f,\n    -0.498728543519974f,\n  0.463982671499252f, -0.498701065778732f, 0.463600188493729f,\n    -0.498673290014267f,\n  0.463217705488205f, -0.498645216226578f, 0.462835282087326f,\n    -0.498616874217987f,\n  0.462452858686447f, -0.498588204383850f, 0.462070435285568f,\n    -0.498559266328812f,\n  0.461688071489334f, -0.498530030250549f, 0.461305707693100f,\n    -0.498500496149063f,\n  0.460923373699188f, -0.498470664024353f, 0.460541069507599f,\n    -0.498440563678741f,\n  0.460158795118332f, -0.498410135507584f, 0.459776520729065f,\n    -0.498379439115524f,\n  0.459394276142120f, -0.498348444700241f, 0.459012061357498f,\n    -0.498317152261734f,\n  0.458629876375198f, -0.498285561800003f, 0.458247691392899f,\n    -0.498253703117371f,\n  0.457865566015244f, -0.498221516609192f, 0.457483440637589f,\n    -0.498189061880112f,\n  0.457101345062256f, -0.498156309127808f, 0.456719279289246f,\n    -0.498123258352280f,\n  0.456337243318558f, -0.498089909553528f, 0.455955207347870f,\n    -0.498056292533875f,\n  0.455573230981827f, -0.498022347688675f, 0.455191254615784f,\n    -0.497988134622574f,\n  0.454809308052063f, -0.497953623533249f, 0.454427421092987f,\n    -0.497918814420700f,\n  0.454045534133911f, -0.497883707284927f, 0.453663676977158f,\n    -0.497848302125931f,\n  0.453281819820404f, -0.497812628746033f, 0.452900022268295f,\n    -0.497776657342911f,\n  0.452518254518509f, -0.497740387916565f, 0.452136516571045f,\n    -0.497703820466995f,\n  0.451754778623581f, -0.497666954994202f, 0.451373100280762f,\n    -0.497629791498184f,\n  0.450991421937943f, -0.497592359781265f, 0.450609803199768f,\n    -0.497554630041122f,\n  0.450228184461594f, -0.497516602277756f, 0.449846625328064f,\n    -0.497478276491165f,\n  0.449465066194534f, -0.497439652681351f, 0.449083566665649f,\n    -0.497400760650635f,\n  0.448702067136765f, -0.497361570596695f, 0.448320597410202f,\n    -0.497322082519531f,\n  0.447939187288284f, -0.497282296419144f, 0.447557777166367f,\n    -0.497242212295532f,\n  0.447176426649094f, -0.497201830148697f, 0.446795076131821f,\n    -0.497161179780960f,\n  0.446413785219193f, -0.497120231389999f, 0.446032524108887f,\n    -0.497078984975815f,\n  0.445651292800903f, -0.497037440538406f, 0.445270061492920f,\n    -0.496995598077774f,\n  0.444888889789581f, -0.496953487396240f, 0.444507747888565f,\n    -0.496911078691483f,\n  0.444126635789871f, -0.496868371963501f, 0.443745553493500f,\n    -0.496825367212296f,\n  0.443364530801773f, -0.496782064437866f, 0.442983508110046f,\n    -0.496738493442535f,\n  0.442602545022964f, -0.496694594621658f, 0.442221581935883f,\n    -0.496650427579880f,\n  0.441840678453445f, -0.496605962514877f, 0.441459804773331f,\n    -0.496561229228973f,\n  0.441078960895538f, -0.496516168117523f, 0.440698176622391f,\n    -0.496470838785172f,\n  0.440317392349243f, -0.496425211429596f, 0.439936667680740f,\n    -0.496379286050797f,\n  0.439555943012238f, -0.496333062648773f, 0.439175277948380f,\n    -0.496286571025848f,\n  0.438794672489166f, -0.496239781379700f, 0.438414067029953f,\n    -0.496192663908005f,\n  0.438033521175385f, -0.496145308017731f, 0.437653005123138f,\n    -0.496097624301910f,\n  0.437272518873215f, -0.496049642562866f, 0.436892062425613f,\n    -0.496001392602921f,\n  0.436511665582657f, -0.495952844619751f, 0.436131268739700f,\n    -0.495903998613358f,\n  0.435750931501389f, -0.495854884386063f, 0.435370653867722f,\n    -0.495805442333221f,\n  0.434990376234055f, -0.495755732059479f, 0.434610158205032f,\n    -0.495705723762512f,\n  0.434229999780655f, -0.495655417442322f, 0.433849841356277f,\n    -0.495604842901230f,\n  0.433469742536545f, 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0.463982671499252f, 0.498701065778732f, 0.464365184307098f,\n    0.498728543519974f,\n  0.464747726917267f, 0.498755723237991f, 0.465130269527435f,\n    0.498782604932785f,\n  0.465512841939926f, 0.498809218406677f, 0.465895414352417f,\n    0.498835533857346f,\n  0.466278046369553f, 0.498861521482468f, 0.466660678386688f,\n    0.498887240886688f,\n  0.467043310403824f, 0.498912662267685f, 0.467426002025604f,\n    0.498937815427780f,\n  0.467808693647385f, 0.498962640762329f, 0.468191385269165f,\n    0.498987197875977f,\n  0.468574106693268f, 0.499011427164078f, 0.468956857919693f,\n    0.499035388231277f,\n  0.469339638948441f, 0.499059051275253f, 0.469722419977188f,\n    0.499082416296005f,\n  0.470105201005936f, 0.499105513095856f, 0.470488041639328f,\n    0.499128282070160f,\n  0.470870882272720f, 0.499150782823563f, 0.471253722906113f,\n    0.499172955751419f,\n  0.471636593341827f, 0.499194860458374f, 0.472019463777542f,\n    0.499216467142105f,\n  0.472402364015579f, 0.499237775802612f, 0.472785294055939f,\n    0.499258816242218f,\n  0.473168224096298f, 0.499279528856277f, 0.473551183938980f,\n    0.499299973249435f,\n  0.473934143781662f, 0.499320119619370f, 0.474317133426666f,\n    0.499339967966080f,\n  0.474700123071671f, 0.499359518289566f, 0.475083142518997f,\n    0.499378770589828f,\n  0.475466161966324f, 0.499397724866867f, 0.475849211215973f,\n    0.499416410923004f,\n  0.476232260465622f, 0.499434769153595f, 0.476615339517593f,\n    0.499452859163284f,\n  0.476998418569565f, 0.499470651149750f, 0.477381497621536f,\n    0.499488145112991f,\n  0.477764606475830f, 0.499505341053009f, 0.478147745132446f,\n    0.499522238969803f,\n  0.478530883789063f, 0.499538868665695f, 0.478914022445679f,\n    0.499555170536041f,\n  0.479297190904617f, 0.499571204185486f, 0.479680359363556f,\n    0.499586939811707f,\n  0.480063527822495f, 0.499602377414703f, 0.480446726083755f,\n    0.499617516994476f,\n  0.480829954147339f, 0.499632388353348f, 0.481213152408600f,\n    0.499646931886673f,\n  0.481596380472183f, 0.499661177396774f, 0.481979638338089f,\n    0.499675154685974f,\n  0.482362866401672f, 0.499688833951950f, 0.482746154069901f,\n    0.499702215194702f,\n  0.483129411935806f, 0.499715298414230f, 0.483512699604034f,\n    0.499728083610535f,\n  0.483895987272263f, 0.499740600585938f, 0.484279274940491f,\n    0.499752789735794f,\n  0.484662592411041f, 0.499764710664749f, 0.485045909881592f,\n    0.499776333570480f,\n  0.485429257154465f, 0.499787658452988f, 0.485812574625015f,\n    0.499798685312271f,\n  0.486195921897888f, 0.499809414148331f, 0.486579269170761f,\n    0.499819844961166f,\n  0.486962646245956f, 0.499830007553101f, 0.487346023321152f,\n    0.499839842319489f,\n  0.487729400396347f, 0.499849408864975f, 0.488112777471542f,\n    0.499858677387238f,\n  0.488496154546738f, 0.499867647886276f, 0.488879561424255f,\n    0.499876320362091f,\n  0.489262968301773f, 0.499884694814682f, 0.489646375179291f,\n    0.499892801046371f,\n  0.490029782056808f, 0.499900579452515f, 0.490413218736649f,\n    0.499908089637756f,\n  0.490796625614166f, 0.499915301799774f, 0.491180062294006f,\n    0.499922215938568f,\n  0.491563498973846f, 0.499928832054138f, 0.491946935653687f,\n    0.499935150146484f,\n  0.492330402135849f, 0.499941170215607f, 0.492713838815689f,\n    0.499946922063828f,\n  0.493097305297852f, 0.499952346086502f, 0.493480771780014f,\n    0.499957501888275f,\n  0.493864238262177f, 0.499962359666824f, 0.494247704744339f,\n    0.499966919422150f,\n  0.494631171226501f, 0.499971181154251f, 0.495014637708664f,\n    0.499975144863129f,\n  0.495398133993149f, 0.499978810548782f, 0.495781600475311f,\n    0.499982208013535f,\n  0.496165096759796f, 0.499985307455063f, 0.496548563241959f,\n    0.499988079071045f,\n  0.496932059526443f, 0.499990582466125f, 0.497315555810928f,\n    0.499992787837982f,\n  0.497699022293091f, 0.499994695186615f, 0.498082518577576f,\n    0.499996334314346f,\n  0.498466014862061f, 0.499997645616531f, 0.498849511146545f,\n    0.499998688697815f,\n  0.499233007431030f, 0.499999403953552f, 0.499616503715515f,\n    0.499999850988388f,\n};\n\n\n/**    \n* \\par   \n* Generation of realCoefB array:    \n* \\par   \n* n = 4096    \n* 
for (i = 0; i < n; i++)    \n* {    \n*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n*  } 
    \n*    \n*/\nstatic const float32_t realCoefB[8192] = {\n  0.500000000000000f, 0.500000000000000f, 0.500383496284485f,\n    0.499999850988388f,\n  0.500766992568970f, 0.499999403953552f, 0.501150488853455f,\n    0.499998688697815f,\n  0.501533985137939f, 0.499997645616531f, 0.501917481422424f,\n    0.499996334314346f,\n  0.502300977706909f, 0.499994695186615f, 0.502684473991394f,\n    0.499992787837982f,\n  0.503067970275879f, 0.499990582466125f, 0.503451406955719f,\n    0.499988079071045f,\n  0.503834903240204f, 0.499985307455063f, 0.504218399524689f,\n    0.499982208013535f,\n  0.504601895809174f, 0.499978810548782f, 0.504985332489014f,\n    0.499975144863129f,\n  0.505368828773499f, 0.499971181154251f, 0.505752325057983f,\n    0.499966919422150f,\n  0.506135761737823f, 0.499962359666824f, 0.506519258022308f,\n    0.499957501888275f,\n  0.506902694702148f, 0.499952346086502f, 0.507286131381989f,\n    0.499946922063828f,\n  0.507669627666473f, 0.499941170215607f, 0.508053064346313f,\n    0.499935150146484f,\n  0.508436501026154f, 0.499928832054138f, 0.508819937705994f,\n    0.499922215938568f,\n  0.509203374385834f, 0.499915301799774f, 0.509586811065674f,\n    0.499908089637756f,\n  0.509970188140869f, 0.499900579452515f, 0.510353624820709f,\n    0.499892801046371f,\n  0.510737061500549f, 0.499884694814682f, 0.511120438575745f,\n    0.499876320362091f,\n  0.511503815650940f, 0.499867647886276f, 0.511887252330780f,\n    0.499858677387238f,\n  0.512270629405975f, 0.499849408864975f, 0.512654006481171f,\n    0.499839842319489f,\n  0.513037383556366f, 0.499830007553101f, 0.513420701026917f,\n    0.499819844961166f,\n  0.513804078102112f, 0.499809414148331f, 0.514187395572662f,\n    0.499798685312271f,\n  0.514570772647858f, 0.499787658452988f, 0.514954090118408f,\n    0.499776333570480f,\n  0.515337407588959f, 0.499764710664749f, 0.515720725059509f,\n    0.499752789735794f,\n  0.516103982925415f, 0.499740600585938f, 0.516487300395966f,\n    0.499728083610535f,\n  0.516870558261871f, 0.499715298414230f, 0.517253875732422f,\n    0.499702215194702f,\n  0.517637133598328f, 0.499688833951950f, 0.518020391464233f,\n    0.499675154685974f,\n  0.518403589725494f, 0.499661177396774f, 0.518786847591400f,\n    0.499646931886673f,\n  0.519170045852661f, 0.499632388353348f, 0.519553244113922f,\n    0.499617516994476f,\n  0.519936442375183f, 0.499602377414703f, 0.520319640636444f,\n    0.499586939811707f,\n  0.520702838897705f, 0.499571204185486f, 0.521085977554321f,\n    0.499555170536041f,\n  0.521469116210938f, 0.499538868665695f, 0.521852254867554f,\n    0.499522238969803f,\n  0.522235393524170f, 0.499505341053009f, 0.522618472576141f,\n    0.499488145112991f,\n  0.523001611232758f, 0.499470651149750f, 0.523384690284729f,\n    0.499452859163284f,\n  0.523767769336700f, 0.499434769153595f, 0.524150788784027f,\n    0.499416410923004f,\n  0.524533808231354f, 0.499397724866867f, 0.524916887283325f,\n    0.499378770589828f,\n  0.525299847126007f, 0.499359518289566f, 0.525682866573334f,\n    0.499339967966080f,\n  0.526065826416016f, 0.499320119619370f, 0.526448845863342f,\n    0.499299973249435f,\n  0.526831746101379f, 0.499279528856277f, 0.527214705944061f,\n    0.499258816242218f,\n  0.527597606182098f, 0.499237775802612f, 0.527980506420136f,\n    0.499216467142105f,\n  0.528363406658173f, 0.499194860458374f, 0.528746306896210f,\n    0.499172955751419f,\n  0.529129147529602f, 0.499150782823563f, 0.529511988162994f,\n    0.499128282070160f,\n  0.529894769191742f, 0.499105513095856f, 0.530277609825134f,\n    0.499082416296005f,\n  0.530660390853882f, 0.499059051275253f, 0.531043112277985f,\n    0.499035388231277f,\n  0.531425893306732f, 0.499011427164078f, 0.531808614730835f,\n    0.498987197875977f,\n  0.532191336154938f, 0.498962640762329f, 0.532573997974396f,\n    0.498937815427780f,\n  0.532956659793854f, 0.498912662267685f, 0.533339321613312f,\n    0.498887240886688f,\n  0.533721983432770f, 0.498861521482468f, 0.534104585647583f,\n    0.498835533857346f,\n  0.534487187862396f, 0.498809218406677f, 0.534869730472565f,\n    0.498782604932785f,\n  0.535252273082733f, 0.498755723237991f, 0.535634815692902f,\n    0.498728543519974f,\n  0.536017298698425f, 0.498701065778732f, 0.536399841308594f,\n    0.498673290014267f,\n  0.536782264709473f, 0.498645216226578f, 0.537164747714996f,\n    0.498616874217987f,\n  0.537547171115875f, 0.498588204383850f, 0.537929534912109f,\n    0.498559266328812f,\n  0.538311958312988f, 0.498530030250549f, 0.538694262504578f,\n    0.498500496149063f,\n  0.539076626300812f, 0.498470664024353f, 0.539458930492401f,\n    0.498440563678741f,\n  0.539841234683990f, 0.498410135507584f, 0.540223479270935f,\n    0.498379439115524f,\n  0.540605723857880f, 0.498348444700241f, 0.540987968444824f,\n    0.498317152261734f,\n  0.541370153427124f, 0.498285561800003f, 0.541752278804779f,\n    0.498253703117371f,\n  0.542134463787079f, 0.498221516609192f, 0.542516589164734f,\n    0.498189061880112f,\n  0.542898654937744f, 0.498156309127808f, 0.543280720710754f,\n    0.498123258352280f,\n  0.543662786483765f, 0.498089909553528f, 0.544044792652130f,\n    0.498056292533875f,\n  0.544426798820496f, 0.498022347688675f, 0.544808745384216f,\n    0.497988134622574f,\n  0.545190691947937f, 0.497953623533249f, 0.545572578907013f,\n    0.497918814420700f,\n  0.545954465866089f, 0.497883707284927f, 0.546336352825165f,\n    0.497848302125931f,\n  0.546718180179596f, 0.497812628746033f, 0.547099947929382f,\n    0.497776657342911f,\n  0.547481775283813f, 0.497740387916565f, 0.547863483428955f,\n    0.497703820466995f,\n  0.548245191574097f, 0.497666954994202f, 0.548626899719238f,\n    0.497629791498184f,\n  0.549008548259735f, 0.497592359781265f, 0.549390196800232f,\n    0.497554630041122f,\n  0.549771785736084f, 0.497516602277756f, 0.550153374671936f,\n    0.497478276491165f,\n  0.550534904003143f, 0.497439652681351f, 0.550916433334351f,\n    0.497400760650635f,\n  0.551297962665558f, 0.497361570596695f, 0.551679372787476f,\n    0.497322082519531f,\n  0.552060842514038f, 0.497282296419144f, 0.552442193031311f,\n    0.497242212295532f,\n  0.552823603153229f, 0.497201830148697f, 0.553204894065857f,\n    0.497161179780960f,\n  0.553586184978485f, 0.497120231389999f, 0.553967475891113f,\n    0.497078984975815f,\n  0.554348707199097f, 0.497037440538406f, 0.554729938507080f,\n    0.496995598077774f,\n  0.555111110210419f, 0.496953487396240f, 0.555492222309113f,\n    0.496911078691483f,\n  0.555873334407806f, 0.496868371963501f, 0.556254446506500f,\n    0.496825367212296f,\n  0.556635499000549f, 0.496782064437866f, 0.557016491889954f,\n    0.496738493442535f,\n  0.557397484779358f, 0.496694594621658f, 0.557778418064117f,\n    0.496650427579880f,\n  0.558159291744232f, 0.496605962514877f, 0.558540165424347f,\n    0.496561229228973f,\n  0.558921039104462f, 0.496516168117523f, 0.559301853179932f,\n    0.496470838785172f,\n  0.559682607650757f, 0.496425211429596f, 0.560063362121582f,\n    0.496379286050797f,\n  0.560444056987762f, 0.496333062648773f, 0.560824692249298f,\n    0.496286571025848f,\n  0.561205327510834f, 0.496239781379700f, 0.561585903167725f,\n    0.496192663908005f,\n  0.561966478824615f, 0.496145308017731f, 0.562346994876862f,\n    0.496097624301910f,\n  0.562727510929108f, 0.496049642562866f, 0.563107967376709f,\n    0.496001392602921f,\n  0.563488364219666f, 0.495952844619751f, 0.563868701457977f,\n    0.495903998613358f,\n  0.564249038696289f, 0.495854884386063f, 0.564629375934601f,\n    0.495805442333221f,\n  0.565009593963623f, 0.495755732059479f, 0.565389811992645f,\n    0.495705723762512f,\n  0.565770030021667f, 0.495655417442322f, 0.566150128841400f,\n    0.495604842901230f,\n  0.566530287265778f, 0.495553970336914f, 0.566910326480865f,\n    0.495502769947052f,\n  0.567290365695953f, 0.495451331138611f, 0.567670345306396f,\n    0.495399564504623f,\n  0.568050265312195f, 0.495347499847412f, 0.568430185317993f,\n    0.495295166969299f,\n  0.568810045719147f, 0.495242536067963f, 0.569189906120300f,\n    0.495189607143402f,\n  0.569569647312164f, 0.495136409997940f, 0.569949388504028f,\n    0.495082914829254f,\n  0.570329129695892f, 0.495029091835022f, 0.570708811283112f,\n    0.494975030422211f,\n  0.571088373661041f, 0.494920641183853f, 0.571467995643616f,\n    0.494865983724594f,\n  0.571847498416901f, 0.494810998439789f, 0.572227001190186f,\n    0.494755744934082f,\n  0.572606444358826f, 0.494700223207474f, 0.572985887527466f,\n    0.494644373655319f,\n  0.573365211486816f, 0.494588255882263f, 0.573744535446167f,\n    0.494531840085983f,\n  0.574123859405518f, 0.494475126266479f, 0.574503064155579f,\n    0.494418144226074f,\n  0.574882268905640f, 0.494360834360123f, 0.575261414051056f,\n    0.494303256273270f,\n  0.575640499591827f, 0.494245409965515f, 0.576019585132599f,\n    0.494187235832214f,\n  0.576398611068726f, 0.494128793478012f, 0.576777577400208f,\n    0.494070053100586f,\n  0.577156484127045f, 0.494011014699936f, 0.577535390853882f,\n    0.493951678276062f,\n  0.577914178371429f, 0.493892073631287f, 0.578292965888977f,\n    0.493832170963287f,\n  0.578671753406525f, 0.493771970272064f, 0.579050421714783f,\n    0.493711471557617f,\n  0.579429090023041f, 0.493650704622269f, 0.579807698726654f,\n    0.493589639663696f,\n  0.580186247825623f, 0.493528276681900f, 0.580564737319946f,\n    0.493466645479202f,\n  0.580943167209625f, 0.493404686450958f, 0.581321597099304f,\n    0.493342459201813f,\n  0.581699967384338f, 0.493279963731766f, 0.582078278064728f,\n    0.493217140436172f,\n  0.582456588745117f, 0.493154048919678f, 0.582834780216217f,\n    0.493090659379959f,\n  0.583212971687317f, 0.493026971817017f, 0.583591103553772f,\n    0.492963016033173f,\n  0.583969175815582f, 0.492898762226105f, 0.584347188472748f,\n    0.492834210395813f,\n  0.584725141525269f, 0.492769360542297f, 0.585103094577789f,\n    0.492704242467880f,\n  0.585480928421021f, 0.492638826370239f, 0.585858762264252f,\n    0.492573112249374f,\n  0.586236536502838f, 0.492507129907608f, 0.586614251136780f,\n    0.492440819740295f,\n  0.586991965770721f, 0.492374241352081f, 0.587369561195374f,\n    0.492307394742966f,\n  0.587747097015381f, 0.492240220308304f, 0.588124632835388f,\n    0.492172777652740f,\n  0.588502109050751f, 0.492105036973953f, 0.588879525661469f,\n    0.492037028074265f,\n  0.589256882667542f, 0.491968721151352f, 0.589634180068970f,\n    0.491900116205215f,\n  0.590011477470398f, 0.491831213235855f, 0.590388655662537f,\n    0.491762012243271f,\n  0.590765833854675f, 0.491692543029785f, 0.591142892837524f,\n    0.491622805595398f,\n  0.591519951820374f, 0.491552740335464f, 0.591896951198578f,\n    0.491482406854630f,\n  0.592273890972137f, 0.491411775350571f, 0.592650771141052f,\n    0.491340845823288f,\n  0.593027591705322f, 0.491269648075104f, 0.593404352664948f,\n    0.491198152303696f,\n  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0.552060842514038f, -0.497282296419144f, 0.551679372787476f,\n    -0.497322082519531f,\n  0.551297962665558f, -0.497361570596695f, 0.550916433334351f,\n    -0.497400760650635f,\n  0.550534904003143f, -0.497439652681351f, 0.550153374671936f,\n    -0.497478276491165f,\n  0.549771785736084f, -0.497516602277756f, 0.549390196800232f,\n    -0.497554630041122f,\n  0.549008548259735f, -0.497592359781265f, 0.548626899719238f,\n    -0.497629791498184f,\n  0.548245191574097f, -0.497666954994202f, 0.547863483428955f,\n    -0.497703820466995f,\n  0.547481775283813f, -0.497740387916565f, 0.547099947929382f,\n    -0.497776657342911f,\n  0.546718180179596f, -0.497812628746033f, 0.546336352825165f,\n    -0.497848302125931f,\n  0.545954465866089f, -0.497883707284927f, 0.545572578907013f,\n    -0.497918814420700f,\n  0.545190691947937f, -0.497953623533249f, 0.544808745384216f,\n    -0.497988134622574f,\n  0.544426798820496f, -0.498022347688675f, 0.544044792652130f,\n    -0.498056292533875f,\n  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0.535252273082733f, -0.498755723237991f, 0.534869730472565f,\n    -0.498782604932785f,\n  0.534487187862396f, -0.498809218406677f, 0.534104585647583f,\n    -0.498835533857346f,\n  0.533721983432770f, -0.498861521482468f, 0.533339321613312f,\n    -0.498887240886688f,\n  0.532956659793854f, -0.498912662267685f, 0.532573997974396f,\n    -0.498937815427780f,\n  0.532191336154938f, -0.498962640762329f, 0.531808614730835f,\n    -0.498987197875977f,\n  0.531425893306732f, -0.499011427164078f, 0.531043112277985f,\n    -0.499035388231277f,\n  0.530660390853882f, -0.499059051275253f, 0.530277609825134f,\n    -0.499082416296005f,\n  0.529894769191742f, -0.499105513095856f, 0.529511988162994f,\n    -0.499128282070160f,\n  0.529129147529602f, -0.499150782823563f, 0.528746306896210f,\n    -0.499172955751419f,\n  0.528363406658173f, -0.499194860458374f, 0.527980506420136f,\n    -0.499216467142105f,\n  0.527597606182098f, -0.499237775802612f, 0.527214705944061f,\n    -0.499258816242218f,\n  0.526831746101379f, -0.499279528856277f, 0.526448845863342f,\n    -0.499299973249435f,\n  0.526065826416016f, -0.499320119619370f, 0.525682866573334f,\n    -0.499339967966080f,\n  0.525299847126007f, -0.499359518289566f, 0.524916887283325f,\n    -0.499378770589828f,\n  0.524533808231354f, -0.499397724866867f, 0.524150788784027f,\n    -0.499416410923004f,\n  0.523767769336700f, -0.499434769153595f, 0.523384690284729f,\n    -0.499452859163284f,\n  0.523001611232758f, -0.499470651149750f, 0.522618472576141f,\n    -0.499488145112991f,\n  0.522235393524170f, -0.499505341053009f, 0.521852254867554f,\n    -0.499522238969803f,\n  0.521469116210938f, -0.499538868665695f, 0.521085977554321f,\n    -0.499555170536041f,\n  0.520702838897705f, -0.499571204185486f, 0.520319640636444f,\n    -0.499586939811707f,\n  0.519936442375183f, -0.499602377414703f, 0.519553244113922f,\n    -0.499617516994476f,\n  0.519170045852661f, -0.499632388353348f, 0.518786847591400f,\n    -0.499646931886673f,\n  0.518403589725494f, -0.499661177396774f, 0.518020391464233f,\n    -0.499675154685974f,\n  0.517637133598328f, -0.499688833951950f, 0.517253875732422f,\n    -0.499702215194702f,\n  0.516870558261871f, -0.499715298414230f, 0.516487300395966f,\n    -0.499728083610535f,\n  0.516103982925415f, -0.499740600585938f, 0.515720725059509f,\n    -0.499752789735794f,\n  0.515337407588959f, -0.499764710664749f, 0.514954090118408f,\n    -0.499776333570480f,\n  0.514570772647858f, -0.499787658452988f, 0.514187395572662f,\n    -0.499798685312271f,\n  0.513804078102112f, -0.499809414148331f, 0.513420701026917f,\n    -0.499819844961166f,\n  0.513037383556366f, -0.499830007553101f, 0.512654006481171f,\n    -0.499839842319489f,\n  0.512270629405975f, -0.499849408864975f, 0.511887252330780f,\n    -0.499858677387238f,\n  0.511503815650940f, -0.499867647886276f, 0.511120438575745f,\n    -0.499876320362091f,\n  0.510737061500549f, -0.499884694814682f, 0.510353624820709f,\n    -0.499892801046371f,\n  0.509970188140869f, -0.499900579452515f, 0.509586811065674f,\n    -0.499908089637756f,\n  0.509203374385834f, -0.499915301799774f, 0.508819937705994f,\n    -0.499922215938568f,\n  0.508436501026154f, -0.499928832054138f, 0.508053064346313f,\n    -0.499935150146484f,\n  0.507669627666473f, -0.499941170215607f, 0.507286131381989f,\n    -0.499946922063828f,\n  0.506902694702148f, -0.499952346086502f, 0.506519258022308f,\n    -0.499957501888275f,\n  0.506135761737823f, -0.499962359666824f, 0.505752325057983f,\n    -0.499966919422150f,\n  0.505368828773499f, -0.499971181154251f, 0.504985332489014f,\n    -0.499975144863129f,\n  0.504601895809174f, -0.499978810548782f, 0.504218399524689f,\n    -0.499982208013535f,\n  0.503834903240204f, -0.499985307455063f, 0.503451406955719f,\n    -0.499988079071045f,\n  0.503067970275879f, -0.499990582466125f, 0.502684473991394f,\n    -0.499992787837982f,\n  0.502300977706909f, -0.499994695186615f, 0.501917481422424f,\n    -0.499996334314346f,\n  0.501533985137939f, -0.499997645616531f, 0.501150488853455f,\n    -0.499998688697815f,\n  0.500766992568970f, -0.499999403953552f, 0.500383496284485f,\n    -0.499999850988388f,\n};\n\n\n\n/**    \n* @brief  Initialization function for the floating-point RFFT/RIFFT.   \n* @deprecated Do not use this function.  It has been superceded by \\ref arm_rfft_fast_init_f32 and will be removed\n* in the future.\n* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.   \n* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.   \n* @param[in]     fftLenReal     length of the FFT.   \n* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   \n* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   \n*    \n* \\par Description:   \n* \\par   \n* The parameter fftLenReal\tSpecifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    \n* \\par    \n* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par    \n* This function also initializes Twiddle factor table.     \n*/\n\narm_status arm_rfft_init_f32(\n  arm_rfft_instance_f32 * S,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag)\n{\n\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialize the Real FFT length */\n  S->fftLenReal = (uint16_t) fftLenReal;\n\n  /*  Initialize the Complex FFT length */\n  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;\n\n  /*  Initialize the Twiddle coefficientA pointer */\n  S->pTwiddleAReal = (float32_t *) realCoefA;\n\n  /*  Initialize the Twiddle coefficientB pointer */\n  S->pTwiddleBReal = (float32_t *) realCoefB;\n\n  /*  Initialize the Flag for selection of RFFT or RIFFT */\n  S->ifftFlagR = (uint8_t) ifftFlagR;\n\n  /*  Initialize the Flag for calculation Bit reversal or not */\n  S->bitReverseFlagR = (uint8_t) bitReverseFlag;\n\n  /*  Initializations of structure parameters depending on the FFT length */\n  switch (S->fftLenReal)\n  {\n    /* Init table modifier value */\n  case 8192u:\n    S->twidCoefRModifier = 1u;\n    break;\n  case 2048u:\n    S->twidCoefRModifier = 4u;\n    break;\n  case 512u:\n    S->twidCoefRModifier = 16u;\n    break;\n  case 128u:\n    S->twidCoefRModifier = 64u;\n    break;\n  default:\n    /*  Reporting argument error if rfftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  /* Init Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  if(S->ifftFlagR)\n  {\n    /* Initializes the CIFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);\n  }\n  else\n  {\n    /* Initializes the CFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);\n  }\n\n  /* return the status of RFFT Init function */\n  return (status);\n\n}\n\n  /**    \n   * @} end of RealFFT group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_init_q15.c    \n*    \n* Description:\tRFFT & RIFFT Q15 initialisation function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n\n\n/**    \n* \\par    \n* Generation floating point real_CoefA array:    \n* \\par    \n* n = 4096    \n* 
for (i = 0; i < n; i++)    \n*  {    \n*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n*  } 
    \n* \\par    \n* Convert to fixed point Q15 format    \n*       round(pATable[i] * pow(2, 15))    \n*/\n\n\nstatic const q15_t ALIGN4 realCoefAQ15[8192] = {\n  0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,\n  0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,\n  0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,\n  0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,\n  0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,\n  0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,\n  0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,\n  0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,\n  0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,\n  0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,\n  0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,\n  0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,\n  0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,\n  0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,\n  0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,\n  0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,\n  0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,\n  0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,\n  0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,\n  0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,\n  0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,\n  0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,\n  0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,\n  0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,\n  0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,\n  0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,\n  0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,\n  0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,\n  0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,\n  0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,\n  0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,\n  0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,\n  0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,\n  0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,\n  0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,\n  0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,\n  0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,\n  0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,\n  0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,\n  0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,\n  0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,\n  0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,\n  0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,\n  0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,\n  0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,\n  0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,\n  0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,\n  0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,\n  0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,\n  0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,\n  0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,\n  0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,\n  0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,\n  0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,\n  0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,\n  0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,\n  0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,\n  0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,\n  0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,\n  0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,\n  0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,\n  0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,\n  0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,\n  0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,\n  0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,\n  0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,\n  0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,\n  0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,\n  0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,\n  0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,\n  0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,\n  0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,\n  0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,\n  0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,\n  0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,\n  0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,\n  0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,\n  0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,\n  0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,\n  0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,\n  0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,\n  0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,\n  0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,\n  0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,\n  0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,\n  0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,\n  0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,\n  0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,\n  0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,\n  0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,\n  0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,\n  0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,\n  0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,\n  0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,\n  0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,\n  0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,\n  0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,\n  0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,\n  0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,\n  0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,\n  0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,\n  0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,\n  0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,\n  0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,\n  0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,\n  0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,\n  0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,\n  0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,\n  0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,\n  0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,\n  0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,\n  0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,\n  0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,\n  0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,\n  0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,\n  0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,\n  0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,\n  0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,\n  0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,\n  0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,\n  0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,\n  0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,\n  0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,\n  0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,\n  0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,\n  0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,\n  0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,\n  0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,\n  0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,\n  0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,\n  0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,\n  0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,\n  0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,\n  0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,\n  0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,\n  0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,\n  0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,\n  0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,\n  0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,\n  0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,\n  0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,\n  0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,\n  0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,\n  0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,\n  0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,\n  0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,\n  0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,\n  0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,\n  0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,\n  0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,\n  0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,\n  0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,\n  0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,\n  0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,\n  0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,\n  0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,\n  0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,\n  0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,\n  0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,\n  0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,\n  0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,\n  0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,\n  0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,\n  0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,\n  0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,\n  0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,\n  0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,\n  0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,\n  0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,\n  0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,\n  0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,\n  0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,\n  0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,\n  0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,\n  0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,\n  0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,\n  0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,\n  0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,\n  0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,\n  0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,\n  0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,\n  0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,\n  0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,\n  0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,\n  0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,\n  0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,\n  0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,\n  0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,\n  0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,\n  0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,\n  0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,\n  0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,\n  0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,\n  0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,\n  0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,\n  0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,\n  0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,\n  0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,\n  0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,\n  0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,\n  0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,\n  0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,\n  0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,\n  0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,\n  0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,\n  0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,\n  0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,\n  0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,\n  0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,\n  0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,\n  0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,\n  0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,\n  0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,\n  0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,\n  0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,\n  0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,\n  0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,\n  0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,\n  0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,\n  0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,\n  0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,\n  0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,\n  0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,\n  0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,\n  0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,\n  0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,\n  0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,\n  0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,\n  0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,\n  0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,\n  0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,\n  0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,\n  0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,\n  0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,\n  0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,\n  0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,\n  0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,\n  0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,\n  0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,\n  0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,\n  0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,\n  0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,\n  0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,\n  0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,\n  0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,\n  0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,\n  0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,\n  0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,\n  0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,\n  0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,\n  0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,\n  0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,\n  0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,\n  0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,\n  0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,\n  0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,\n  0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,\n  0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,\n  0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,\n  0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,\n  0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,\n  0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,\n  0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,\n  0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,\n  0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,\n  0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,\n  0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,\n  0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,\n  0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,\n  0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,\n  0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,\n  0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,\n  0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,\n  0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,\n  0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,\n  0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,\n  0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,\n  0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,\n  0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,\n  0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,\n  0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,\n  0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,\n  0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,\n  0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,\n  0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,\n  0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,\n  0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,\n  0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,\n  0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,\n  0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,\n  0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,\n  0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,\n  0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,\n  0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,\n  0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,\n  0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,\n  0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,\n  0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,\n  0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,\n  0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,\n  0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,\n  0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,\n  0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,\n  0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,\n  0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,\n  0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,\n  0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,\n  0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,\n  0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,\n  0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,\n  0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,\n  0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,\n  0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,\n  0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,\n  0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,\n  0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,\n  0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,\n  0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,\n  0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,\n  0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,\n  0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,\n  0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,\n  0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,\n  0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,\n  0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,\n  0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,\n  0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,\n  0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,\n  0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,\n  0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,\n  0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,\n  0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,\n  0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,\n  0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,\n  0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,\n  0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,\n  0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,\n  0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,\n  0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,\n  0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,\n  0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,\n  0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,\n  0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,\n  0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,\n  0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,\n  0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,\n  0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,\n  0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,\n  0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,\n  0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,\n  0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,\n  0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,\n  0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,\n  0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,\n  0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,\n  0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,\n  0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,\n  0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,\n  0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,\n  0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 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0x583, 0xe605,\n  0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,\n  0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,\n  0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,\n  0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,\n  0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,\n  0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,\n  0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,\n  0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,\n  0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,\n  0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,\n  0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,\n  0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,\n  0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,\n  0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,\n  0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,\n  0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,\n  0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,\n  0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,\n  0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,\n  0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,\n  0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,\n  0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,\n  0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,\n  0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,\n  0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,\n  0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,\n  0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,\n  0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,\n  0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,\n  0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,\n  0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,\n  0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,\n  0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,\n  0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,\n  0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,\n  0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,\n  0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,\n  0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,\n  0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,\n  0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,\n  0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,\n  0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,\n  0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,\n  0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,\n  0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,\n  0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,\n  0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,\n  0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,\n  0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,\n  0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,\n  0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,\n  0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,\n  0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,\n  0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,\n  0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,\n  0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,\n  0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,\n  0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,\n  0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,\n  0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,\n  0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,\n  0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,\n  0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,\n  0x199, 0xf1c9, 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0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,\n  0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,\n  0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,\n  0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,\n  0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,\n  0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,\n  0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,\n  0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,\n  0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,\n  0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,\n  0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,\n  0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,\n  0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,\n  0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,\n  0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,\n  0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,\n  0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,\n  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0xfb70,\n  0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,\n  0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,\n  0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,\n  0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,\n  0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,\n  0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,\n  0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,\n  0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,\n  0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,\n  0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,\n  0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,\n  0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,\n  0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,\n  0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,\n  0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,\n  0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,\n  0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,\n  0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,\n  0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,\n  0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,\n  0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,\n  0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,\n  0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,\n  0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,\n  0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,\n  0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,\n  0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,\n  0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,\n  0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,\n  0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,\n  0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,\n  0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,\n  0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,\n  0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,\n  0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,\n  0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,\n  0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,\n  0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,\n  0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,\n  0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,\n  0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,\n  0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,\n  0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,\n  0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,\n  0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,\n  0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,\n  0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,\n  0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,\n  0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,\n  0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,\n  0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,\n  0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,\n  0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,\n  0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,\n  0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,\n  0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,\n  0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,\n  0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,\n  0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,\n  0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,\n  0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,\n  0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,\n  0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,\n  0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,\n  0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,\n  0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,\n  0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,\n  0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,\n  0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,\n  0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,\n  0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,\n  0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,\n  0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,\n  0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,\n  0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,\n  0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,\n  0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,\n  0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,\n  0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,\n  0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,\n  0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,\n  0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,\n  0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,\n  0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,\n  0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,\n  0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,\n  0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,\n  0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,\n  0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,\n  0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,\n  0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,\n  0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,\n  0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,\n  0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,\n  0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,\n  0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,\n  0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,\n  0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,\n  0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,\n  0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,\n  0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,\n  0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,\n  0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,\n  0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,\n  0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,\n  0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,\n  0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,\n  0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,\n  0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,\n  0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,\n  0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,\n  0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,\n  0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,\n  0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,\n  0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,\n  0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,\n  0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,\n  0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,\n  0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,\n  0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,\n  0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,\n  0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,\n  0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,\n  0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,\n  0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,\n  0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,\n  0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,\n  0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,\n  0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,\n  0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,\n  0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,\n  0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,\n  0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,\n  0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,\n  0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,\n  0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,\n  0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,\n  0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,\n  0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,\n  0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,\n  0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,\n  0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,\n  0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,\n  0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,\n  0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,\n  0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,\n  0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,\n  0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,\n  0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,\n  0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,\n  0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,\n  0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,\n  0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,\n  0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,\n  0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,\n  0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,\n  0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,\n  0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,\n  0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,\n  0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,\n  0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,\n  0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,\n  0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,\n  0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,\n  0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,\n  0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,\n  0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,\n  0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,\n  0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,\n  0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,\n  0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,\n  0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,\n  0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,\n  0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,\n  0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,\n  0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,\n  0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,\n  0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,\n  0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,\n  0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,\n  0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,\n  0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,\n  0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,\n  0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,\n  0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,\n  0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,\n  0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,\n  0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,\n  0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,\n  0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,\n  0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,\n  0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,\n  0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,\n  0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,\n  0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,\n  0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,\n  0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,\n  0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,\n  0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,\n  0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,\n  0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,\n  0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,\n  0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,\n  0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,\n  0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,\n  0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,\n  0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,\n  0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,\n  0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,\n  0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,\n  0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,\n  0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,\n  0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,\n  0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,\n  0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,\n  0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,\n  0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,\n  0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,\n  0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,\n  0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,\n  0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,\n  0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,\n  0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,\n  0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,\n  0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,\n  0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,\n  0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,\n  0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,\n  0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,\n  0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,\n  0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,\n  0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,\n  0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,\n  0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,\n  0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,\n  0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,\n  0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,\n  0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,\n  0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,\n  0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,\n  0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,\n  0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,\n  0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,\n  0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,\n  0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,\n  0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,\n  0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,\n  0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,\n  0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,\n  0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,\n  0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,\n  0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,\n  0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,\n  0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,\n  0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,\n  0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,\n  0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,\n  0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,\n  0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,\n  0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,\n  0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,\n  0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,\n  0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,\n  0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,\n  0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,\n  0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,\n  0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,\n  0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,\n  0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,\n  0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,\n  0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,\n  0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,\n  0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,\n  0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,\n  0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,\n  0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,\n  0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,\n  0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,\n  0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,\n  0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,\n  0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,\n  0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,\n  0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,\n  0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,\n  0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,\n  0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,\n  0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,\n  0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,\n  0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,\n  0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,\n  0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,\n  0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,\n  0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,\n  0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,\n  0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,\n  0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,\n  0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,\n  0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,\n  0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,\n  0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,\n  0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,\n  0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,\n  0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,\n  0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,\n  0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,\n  0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,\n  0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,\n  0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,\n  0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,\n  0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,\n  0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,\n  0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,\n  0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,\n  0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,\n  0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,\n  0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,\n  0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,\n  0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,\n  0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,\n  0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,\n  0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,\n  0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,\n  0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,\n  0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,\n  0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,\n  0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,\n  0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,\n  0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,\n  0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,\n  0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,\n  0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,\n  0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,\n  0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,\n  0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,\n  0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,\n  0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,\n  0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,\n  0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,\n  0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,\n  0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,\n  0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,\n  0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,\n  0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,\n  0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,\n  0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,\n  0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,\n  0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,\n  0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,\n  0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,\n  0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,\n  0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,\n  0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,\n  0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,\n  0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,\n  0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,\n  0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,\n  0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,\n  0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,\n  0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,\n  0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,\n  0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,\n  0x1f6f, 0x3718, 0x1f7a, 0x371f, 0x1f85, 0x3725, 0x1f90, 0x372c,\n  0x1f9b, 0x3732, 0x1fa5, 0x3738, 0x1fb0, 0x373f, 0x1fbb, 0x3745,\n  0x1fc6, 0x374b, 0x1fd1, 0x3752, 0x1fdc, 0x3758, 0x1fe7, 0x375e,\n  0x1ff1, 0x3765, 0x1ffc, 0x376b, 0x2007, 0x3771, 0x2012, 0x3777,\n  0x201d, 0x377e, 0x2028, 0x3784, 0x2033, 0x378a, 0x203e, 0x3790,\n  0x2049, 0x3797, 0x2054, 0x379d, 0x205e, 0x37a3, 0x2069, 0x37a9,\n  0x2074, 0x37b0, 0x207f, 0x37b6, 0x208a, 0x37bc, 0x2095, 0x37c2,\n  0x20a0, 0x37c8, 0x20ab, 0x37ce, 0x20b6, 0x37d5, 0x20c1, 0x37db,\n  0x20cc, 0x37e1, 0x20d7, 0x37e7, 0x20e2, 0x37ed, 0x20ed, 0x37f3,\n  0x20f8, 0x37f9, 0x2103, 0x37ff, 0x210e, 0x3805, 0x2119, 0x380b,\n  0x2124, 0x3812, 0x212f, 0x3818, 0x213a, 0x381e, 0x2145, 0x3824,\n  0x2150, 0x382a, 0x215b, 0x3830, 0x2166, 0x3836, 0x2171, 0x383c,\n  0x217c, 0x3842, 0x2187, 0x3848, 0x2192, 0x384e, 0x219d, 0x3854,\n  0x21a8, 0x385a, 0x21b3, 0x3860, 0x21be, 0x3866, 0x21ca, 0x386b,\n  0x21d5, 0x3871, 0x21e0, 0x3877, 0x21eb, 0x387d, 0x21f6, 0x3883,\n  0x2201, 0x3889, 0x220c, 0x388f, 0x2217, 0x3895, 0x2222, 0x389b,\n  0x222d, 0x38a1, 0x2239, 0x38a6, 0x2244, 0x38ac, 0x224f, 0x38b2,\n  0x225a, 0x38b8, 0x2265, 0x38be, 0x2270, 0x38c3, 0x227b, 0x38c9,\n  0x2287, 0x38cf, 0x2292, 0x38d5, 0x229d, 0x38db, 0x22a8, 0x38e0,\n  0x22b3, 0x38e6, 0x22be, 0x38ec, 0x22ca, 0x38f2, 0x22d5, 0x38f7,\n  0x22e0, 0x38fd, 0x22eb, 0x3903, 0x22f6, 0x3909, 0x2301, 0x390e,\n  0x230d, 0x3914, 0x2318, 0x391a, 0x2323, 0x391f, 0x232e, 0x3925,\n  0x233a, 0x392b, 0x2345, 0x3930, 0x2350, 0x3936, 0x235b, 0x393b,\n  0x2367, 0x3941, 0x2372, 0x3947, 0x237d, 0x394c, 0x2388, 0x3952,\n  0x2394, 0x3958, 0x239f, 0x395d, 0x23aa, 0x3963, 0x23b5, 0x3968,\n  0x23c1, 0x396e, 0x23cc, 0x3973, 0x23d7, 0x3979, 0x23e2, 0x397e,\n  0x23ee, 0x3984, 0x23f9, 0x3989, 0x2404, 0x398f, 0x2410, 0x3994,\n  0x241b, 0x399a, 0x2426, 0x399f, 0x2432, 0x39a5, 0x243d, 0x39aa,\n  0x2448, 0x39b0, 0x2454, 0x39b5, 0x245f, 0x39bb, 0x246a, 0x39c0,\n  0x2476, 0x39c5, 0x2481, 0x39cb, 0x248c, 0x39d0, 0x2498, 0x39d6,\n  0x24a3, 0x39db, 0x24ae, 0x39e0, 0x24ba, 0x39e6, 0x24c5, 0x39eb,\n  0x24d0, 0x39f0, 0x24dc, 0x39f6, 0x24e7, 0x39fb, 0x24f3, 0x3a00,\n  0x24fe, 0x3a06, 0x2509, 0x3a0b, 0x2515, 0x3a10, 0x2520, 0x3a16,\n  0x252c, 0x3a1b, 0x2537, 0x3a20, 0x2542, 0x3a25, 0x254e, 0x3a2b,\n  0x2559, 0x3a30, 0x2565, 0x3a35, 0x2570, 0x3a3a, 0x257c, 0x3a3f,\n  0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,\n  0x25b5, 0x3a59, 0x25c0, 0x3a5f, 0x25cc, 0x3a64, 0x25d7, 0x3a69,\n  0x25e3, 0x3a6e, 0x25ee, 0x3a73, 0x25fa, 0x3a78, 0x2605, 0x3a7d,\n  0x2611, 0x3a82, 0x261c, 0x3a88, 0x2628, 0x3a8d, 0x2633, 0x3a92,\n  0x263f, 0x3a97, 0x264a, 0x3a9c, 0x2656, 0x3aa1, 0x2661, 0x3aa6,\n  0x266d, 0x3aab, 0x2678, 0x3ab0, 0x2684, 0x3ab5, 0x268f, 0x3aba,\n  0x269b, 0x3abf, 0x26a6, 0x3ac4, 0x26b2, 0x3ac9, 0x26bd, 0x3ace,\n  0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,\n  0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,\n  0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,\n  0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,\n  0x2782, 0x3b21, 0x278e, 0x3b26, 0x2799, 0x3b2a, 0x27a5, 0x3b2f,\n  0x27b1, 0x3b34, 0x27bc, 0x3b39, 0x27c8, 0x3b3e, 0x27d3, 0x3b42,\n  0x27df, 0x3b47, 0x27eb, 0x3b4c, 0x27f6, 0x3b50, 0x2802, 0x3b55,\n  0x280e, 0x3b5a, 0x2819, 0x3b5f, 0x2825, 0x3b63, 0x2831, 0x3b68,\n  0x283c, 0x3b6d, 0x2848, 0x3b71, 0x2854, 0x3b76, 0x285f, 0x3b7b,\n  0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,\n  0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,\n  0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,\n  0x28f7, 0x3bb6, 0x2903, 0x3bbb, 0x290f, 0x3bbf, 0x291b, 0x3bc4,\n  0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,\n  0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,\n  0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,\n  0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,\n  0x29e3, 0x3c0f, 0x29ee, 0x3c13, 0x29fa, 0x3c17, 0x2a06, 0x3c1c,\n  0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,\n  0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,\n  0x2a70, 0x3c42, 0x2a7c, 0x3c46, 0x2a88, 0x3c4b, 0x2a94, 0x3c4f,\n  0x2aa0, 0x3c53, 0x2aac, 0x3c57, 0x2ab7, 0x3c5b, 0x2ac3, 0x3c60,\n  0x2acf, 0x3c64, 0x2adb, 0x3c68, 0x2ae7, 0x3c6c, 0x2af3, 0x3c70,\n  0x2aff, 0x3c74, 0x2b0a, 0x3c79, 0x2b16, 0x3c7d, 0x2b22, 0x3c81,\n  0x2b2e, 0x3c85, 0x2b3a, 0x3c89, 0x2b46, 0x3c8d, 0x2b52, 0x3c91,\n  0x2b5e, 0x3c95, 0x2b6a, 0x3c99, 0x2b75, 0x3c9d, 0x2b81, 0x3ca1,\n  0x2b8d, 0x3ca5, 0x2b99, 0x3ca9, 0x2ba5, 0x3cad, 0x2bb1, 0x3cb1,\n  0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,\n  0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,\n  0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,\n  0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,\n  0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,\n  0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,\n  0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,\n  0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,\n  0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,\n  0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,\n  0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,\n  0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,\n  0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,\n  0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,\n  0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,\n  0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,\n  0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,\n  0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,\n  0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,\n  0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,\n  0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,\n  0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,\n  0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,\n  0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,\n  0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,\n  0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,\n  0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,\n  0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,\n  0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,\n  0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,\n  0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,\n  0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,\n  0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,\n  0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,\n  0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,\n  0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,\n  0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,\n  0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,\n  0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,\n  0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,\n  0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,\n  0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,\n  0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,\n  0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,\n  0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,\n  0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,\n  0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,\n  0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,\n  0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,\n  0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,\n  0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,\n  0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,\n  0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,\n  0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,\n  0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,\n  0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,\n  0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,\n  0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,\n  0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,\n  0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,\n  0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,\n  0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,\n  0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,\n  0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,\n  0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,\n  0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,\n  0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,\n  0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,\n  0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,\n  0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,\n  0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,\n  0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,\n  0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,\n  0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,\n  0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,\n  0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,\n  0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,\n  0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,\n  0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,\n  0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,\n  0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,\n  0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,\n  0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,\n  0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,\n  0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,\n  0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,\n  0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,\n  0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,\n  0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,\n  0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,\n  0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,\n  0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,\n  0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,\n  0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,\n  0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,\n  0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,\n  0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,\n  0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,\n  0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,\n  0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,\n  0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,\n  0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,\n  0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,\n  0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,\n  0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,\n};\n\n/**    \n* \\par   \n* Generation of real_CoefB array:    \n* \\par    \n* n = 4096    \n* 
for (i = 0; i < n; i++)    \n*  {    \n*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n*  } 
   \n* \\par    \n* Convert to fixed point Q15 format    \n*       round(pBTable[i] * pow(2, 15))    \n*    \n*/\n\nstatic const q15_t ALIGN4 realCoefBQ15[8192] = {\n  0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,\n  0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,\n  0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,\n  0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,\n  0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,\n  0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,\n  0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,\n  0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,\n  0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,\n  0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,\n  0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,\n  0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,\n  0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,\n  0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,\n  0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,\n  0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,\n  0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,\n  0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,\n  0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,\n  0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,\n  0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,\n  0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,\n  0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,\n  0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,\n  0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,\n  0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,\n  0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,\n  0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,\n  0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,\n  0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,\n  0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,\n  0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,\n  0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,\n  0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,\n  0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,\n  0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,\n  0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,\n  0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,\n  0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,\n  0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,\n  0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,\n  0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,\n  0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,\n  0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,\n  0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,\n  0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,\n  0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,\n  0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,\n  0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,\n  0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,\n  0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,\n  0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,\n  0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,\n  0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,\n  0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,\n  0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,\n  0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,\n  0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,\n  0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,\n  0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,\n  0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,\n  0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,\n  0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,\n  0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,\n  0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,\n  0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,\n  0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,\n  0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,\n  0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,\n  0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,\n  0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,\n  0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 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0x5dde, 0xc765,\n  0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,\n  0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,\n  0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,\n  0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,\n  0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,\n  0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,\n  0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,\n  0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,\n  0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,\n  0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,\n  0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,\n  0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,\n  0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,\n  0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,\n  0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,\n  0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,\n  0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,\n  0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,\n  0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,\n  0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,\n  0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,\n  0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,\n  0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,\n  0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,\n  0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,\n  0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,\n  0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,\n  0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,\n  0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,\n  0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,\n  0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,\n  0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,\n  0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,\n  0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,\n  0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,\n  0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,\n  0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,\n  0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,\n  0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,\n  0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,\n  0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,\n  0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,\n  0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,\n  0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,\n  0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,\n  0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,\n  0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,\n  0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,\n  0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,\n  0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,\n  0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,\n  0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,\n  0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,\n  0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,\n  0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,\n  0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,\n  0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,\n  0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,\n  0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,\n  0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,\n  0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,\n  0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,\n  0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,\n  0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,\n  0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,\n  0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,\n  0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,\n  0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,\n  0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,\n  0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,\n  0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,\n  0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,\n  0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,\n  0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,\n  0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,\n  0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,\n  0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,\n  0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,\n  0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,\n  0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,\n  0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,\n  0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,\n  0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,\n  0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,\n  0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,\n  0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,\n  0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,\n  0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,\n  0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,\n  0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,\n  0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,\n  0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,\n  0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,\n  0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,\n  0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,\n  0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,\n  0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,\n  0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,\n  0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,\n  0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,\n  0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,\n  0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,\n  0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,\n  0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,\n  0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,\n  0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,\n  0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,\n  0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,\n  0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,\n  0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,\n  0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,\n  0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,\n  0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,\n  0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,\n  0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,\n  0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,\n  0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,\n  0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,\n  0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,\n  0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,\n  0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,\n  0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,\n  0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,\n  0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,\n  0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,\n  0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,\n  0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,\n  0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,\n  0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,\n  0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,\n  0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,\n  0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,\n  0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,\n  0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,\n  0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,\n  0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,\n  0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,\n  0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,\n  0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,\n  0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,\n  0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,\n  0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,\n  0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,\n  0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,\n  0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,\n  0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,\n  0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,\n  0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,\n  0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,\n  0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,\n  0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,\n  0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,\n  0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,\n  0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,\n  0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,\n  0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,\n  0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,\n  0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,\n};\n\n/**    \n* @brief  Initialization function for the Q15 RFFT/RIFFT.   \n* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.   \n* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.   \n* @param[in]      fftLenReal     length of the FFT.   \n* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   \n* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   \n*    \n* \\par Description:   \n* \\par   \n* The parameter fftLenReal\tSpecifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    \n* \\par    \n* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par    \n* This function also initializes Twiddle factor table.     \n*/\n\narm_status arm_rfft_init_q15(\n  arm_rfft_instance_q15 * S,\n  arm_cfft_radix4_instance_q15 * S_CFFT,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag)\n{\n\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialize the Real FFT length */\n  S->fftLenReal = (uint16_t) fftLenReal;\n\n  /*  Initialize the Complex FFT length */\n  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;\n\n  /*  Initialize the Twiddle coefficientA pointer */\n  S->pTwiddleAReal = (q15_t *) realCoefAQ15;\n\n  /*  Initialize the Twiddle coefficientB pointer */\n  S->pTwiddleBReal = (q15_t *) realCoefBQ15;\n\n  /*  Initialize the Flag for selection of RFFT or RIFFT */\n  S->ifftFlagR = (uint8_t) ifftFlagR;\n\n  /*  Initialize the Flag for calculation Bit reversal or not */\n  S->bitReverseFlagR = (uint8_t) bitReverseFlag;\n\n  /*  Initialization of coef modifier depending on the FFT length */\n  switch (S->fftLenReal)\n  {\n  case 8192:\n    S->twidCoefRModifier = 1u;\n    break;\n  case 2048u:\n    S->twidCoefRModifier = 4u;\n    break;\n  case 512u:\n    S->twidCoefRModifier = 16u;\n    break;\n  case 128u:\n    S->twidCoefRModifier = 64u;\n    break;\n  default:\n    /*  Reporting argument error if rfftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  /* Init Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  if(S->ifftFlagR)\n  {\n    /* Initializes the CIFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);\n  }\n  else\n  {\n    /* Initializes the CFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);\n  }\n\n  /* return the status of RFFT Init function */\n  return (status);\n\n}\n\n  /**    \n   * @} end of RealFFT group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_init_q31.c    \n*    \n* Description:\tRFFT & RIFFT Q31 initialisation function    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.  \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\n/**    \n * @ingroup groupTransforms    \n */\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n/**    \n* \\par    \n* Generation floating point realCoefAQ31 array:    \n* \\par    \n* n = 4096    \n* 
for (i = 0; i < n; i++)    \n* {    \n*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n* }
    \n* \\par    \n* Convert to fixed point Q31 format    \n*     round(pATable[i] * pow(2, 31))    \n*/\n\n\nstatic const q31_t realCoefAQ31[8192] = {\n  0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,\n  0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,\n  0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,\n  0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,\n  0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,\n  0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,\n  0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,\n  0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,\n  0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,\n  0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,\n  0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,\n  0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,\n  0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,\n  0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,\n  0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,\n  0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,\n  0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,\n  0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,\n  0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,\n  0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,\n  0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,\n  0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,\n  0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,\n  0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,\n  0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,\n  0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,\n  0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,\n  0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,\n  0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,\n  0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,\n  0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,\n  0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,\n  0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,\n  0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,\n  0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,\n  0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,\n  0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,\n  0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,\n  0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,\n  0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,\n  0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,\n  0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,\n  0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,\n  0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,\n  0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,\n  0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,\n  0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,\n  0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,\n  0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,\n  0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,\n  0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,\n  0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,\n  0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,\n  0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,\n  0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,\n  0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,\n  0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,\n  0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,\n  0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,\n  0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,\n  0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,\n  0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,\n  0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,\n  0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,\n  0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,\n  0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,\n  0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,\n  0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,\n  0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,\n  0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,\n  0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,\n  0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,\n  0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,\n  0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,\n  0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,\n  0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,\n  0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,\n  0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,\n  0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,\n  0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,\n  0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,\n  0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,\n  0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,\n  0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,\n  0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,\n  0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,\n  0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,\n  0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,\n  0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,\n  0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,\n  0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,\n  0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,\n  0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,\n  0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,\n  0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,\n  0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,\n  0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,\n  0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,\n  0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,\n  0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,\n  0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,\n  0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,\n  0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,\n  0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,\n  0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,\n  0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,\n  0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,\n  0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,\n  0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,\n  0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,\n  0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,\n  0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,\n  0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,\n  0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,\n  0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,\n  0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,\n  0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,\n  0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,\n  0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,\n  0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,\n  0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,\n  0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,\n  0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,\n  0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,\n  0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,\n  0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,\n  0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,\n  0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,\n  0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,\n  0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,\n  0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,\n  0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,\n  0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,\n  0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,\n  0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,\n  0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,\n  0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,\n  0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,\n  0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,\n  0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,\n  0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,\n  0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,\n  0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,\n  0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,\n  0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,\n  0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,\n  0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,\n  0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,\n  0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,\n  0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,\n  0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,\n  0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,\n  0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,\n  0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,\n  0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,\n  0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,\n  0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,\n  0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,\n  0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,\n  0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,\n  0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,\n  0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,\n  0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,\n  0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,\n  0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,\n  0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,\n  0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,\n  0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,\n  0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,\n  0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,\n  0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,\n  0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,\n  0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,\n  0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,\n  0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,\n  0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,\n  0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,\n  0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,\n  0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,\n  0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,\n  0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,\n  0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,\n  0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,\n  0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,\n  0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,\n  0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,\n  0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,\n  0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,\n  0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,\n  0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,\n  0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,\n  0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,\n  0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,\n  0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,\n  0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,\n  0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,\n  0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,\n  0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,\n  0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,\n  0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,\n  0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,\n  0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,\n  0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,\n  0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,\n  0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,\n  0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,\n  0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,\n  0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,\n  0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,\n  0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,\n  0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,\n  0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,\n  0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,\n  0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,\n  0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,\n  0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,\n  0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,\n  0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,\n  0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,\n  0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,\n  0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,\n  0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,\n  0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,\n  0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,\n  0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,\n  0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,\n  0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,\n  0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,\n  0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,\n  0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,\n  0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,\n  0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,\n  0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,\n  0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,\n  0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,\n  0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,\n  0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,\n  0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,\n  0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,\n  0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,\n  0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,\n  0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,\n  0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,\n  0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,\n  0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,\n  0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,\n  0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,\n  0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,\n  0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,\n  0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,\n  0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,\n  0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,\n  0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,\n  0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,\n  0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,\n  0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,\n  0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,\n  0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,\n  0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,\n  0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,\n  0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,\n  0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,\n  0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,\n  0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,\n  0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,\n  0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,\n  0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,\n  0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,\n  0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,\n  0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,\n  0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,\n  0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,\n  0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,\n  0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,\n  0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,\n  0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,\n  0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,\n  0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,\n  0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,\n  0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,\n  0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,\n  0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,\n  0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,\n  0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,\n  0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,\n  0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,\n  0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,\n  0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,\n  0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,\n  0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,\n  0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,\n  0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,\n  0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,\n  0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,\n  0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,\n  0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,\n  0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,\n  0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,\n  0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,\n  0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,\n  0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,\n  0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,\n  0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,\n  0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,\n  0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,\n  0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,\n  0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,\n  0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,\n  0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,\n  0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,\n  0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,\n  0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,\n  0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,\n  0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,\n  0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,\n  0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,\n  0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,\n  0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,\n  0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,\n  0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,\n  0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,\n  0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,\n  0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,\n  0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,\n  0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,\n  0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,\n  0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,\n  0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,\n  0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,\n  0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,\n  0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,\n  0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,\n  0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,\n  0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,\n  0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,\n  0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,\n  0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,\n  0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,\n  0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,\n  0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,\n  0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,\n  0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,\n  0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,\n  0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,\n  0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,\n  0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,\n  0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,\n  0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,\n  0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,\n  0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,\n  0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,\n  0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,\n  0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,\n  0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,\n  0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,\n  0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,\n  0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,\n  0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,\n  0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,\n  0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,\n  0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,\n  0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,\n  0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,\n  0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,\n  0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,\n  0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,\n  0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,\n  0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,\n  0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,\n  0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,\n  0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,\n  0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,\n  0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,\n  0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,\n  0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,\n  0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,\n  0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,\n  0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,\n  0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,\n  0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,\n  0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,\n  0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,\n  0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,\n  0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,\n  0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,\n  0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,\n  0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,\n  0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,\n  0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,\n  0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,\n  0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,\n  0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,\n  0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,\n  0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,\n  0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,\n  0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,\n  0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,\n  0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,\n  0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,\n  0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,\n  0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,\n  0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,\n  0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,\n  0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,\n  0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,\n  0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,\n  0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,\n  0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,\n  0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,\n  0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,\n  0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,\n  0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,\n  0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,\n  0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,\n  0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,\n  0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,\n  0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,\n  0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,\n  0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,\n  0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,\n  0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,\n  0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,\n  0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,\n  0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,\n  0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,\n  0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,\n  0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,\n  0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,\n  0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,\n  0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,\n  0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,\n  0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,\n  0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,\n  0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,\n  0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,\n  0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,\n  0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,\n  0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,\n  0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,\n  0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,\n  0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,\n  0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,\n  0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,\n  0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,\n  0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,\n  0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,\n  0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,\n  0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,\n  0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,\n  0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,\n  0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,\n  0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,\n  0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,\n  0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,\n  0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,\n  0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,\n  0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,\n  0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,\n  0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,\n  0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,\n  0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,\n  0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,\n  0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,\n  0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,\n  0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,\n  0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,\n  0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,\n  0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,\n  0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,\n  0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,\n  0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,\n  0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,\n  0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,\n  0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,\n  0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,\n  0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,\n  0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,\n  0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,\n  0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,\n  0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,\n  0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,\n  0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,\n  0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,\n  0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,\n  0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,\n  0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,\n  0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,\n  0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,\n  0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,\n  0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,\n  0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,\n  0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,\n  0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,\n  0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,\n  0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,\n  0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,\n  0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,\n  0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,\n  0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,\n  0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,\n  0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,\n  0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,\n  0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,\n  0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,\n  0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,\n  0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,\n  0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,\n  0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,\n  0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,\n  0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,\n  0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,\n  0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,\n  0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,\n  0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,\n  0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,\n  0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,\n  0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,\n  0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,\n  0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,\n  0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,\n  0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,\n  0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,\n  0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,\n  0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,\n  0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,\n  0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,\n  0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,\n  0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,\n  0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,\n  0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,\n  0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,\n  0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,\n  0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,\n  0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,\n  0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,\n  0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,\n  0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,\n  0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,\n  0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,\n  0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,\n  0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,\n  0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,\n  0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,\n  0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,\n  0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,\n  0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,\n  0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,\n  0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,\n  0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,\n  0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,\n  0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,\n  0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,\n  0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,\n  0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,\n  0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,\n  0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,\n  0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,\n  0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,\n  0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,\n  0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,\n  0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,\n  0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,\n  0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,\n  0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,\n  0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,\n  0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,\n  0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,\n  0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,\n  0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,\n  0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,\n  0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,\n  0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,\n  0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,\n  0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,\n  0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,\n  0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,\n  0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,\n  0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,\n  0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,\n  0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,\n  0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,\n  0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,\n  0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,\n  0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,\n  0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,\n  0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,\n  0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,\n  0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,\n  0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,\n  0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,\n  0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,\n  0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,\n  0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,\n  0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,\n  0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,\n  0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,\n  0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,\n  0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,\n  0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,\n  0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,\n  0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,\n  0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,\n  0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,\n  0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,\n  0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,\n  0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,\n  0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,\n  0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,\n  0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,\n  0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,\n  0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,\n  0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,\n  0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,\n  0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,\n  0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,\n  0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,\n  0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,\n  0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,\n  0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,\n  0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,\n  0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,\n  0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,\n  0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,\n  0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,\n  0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,\n  0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,\n  0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,\n  0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,\n  0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,\n  0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,\n  0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,\n  0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,\n  0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,\n  0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,\n  0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,\n  0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,\n  0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,\n  0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,\n  0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,\n  0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,\n  0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,\n  0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,\n  0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,\n  0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,\n  0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,\n  0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,\n  0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,\n  0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,\n  0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,\n  0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,\n  0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,\n  0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,\n  0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,\n  0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,\n  0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,\n  0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,\n  0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,\n  0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,\n  0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,\n  0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,\n  0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,\n  0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,\n  0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,\n  0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,\n  0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,\n  0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,\n  0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,\n  0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,\n  0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,\n  0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,\n  0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,\n  0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,\n  0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,\n  0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,\n  0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,\n  0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,\n  0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,\n  0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,\n  0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,\n  0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,\n  0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,\n  0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,\n  0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,\n  0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,\n  0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,\n  0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,\n  0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,\n  0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,\n  0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,\n  0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,\n  0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,\n  0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,\n  0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,\n  0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,\n  0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,\n  0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,\n  0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,\n  0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,\n  0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,\n  0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,\n  0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,\n  0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,\n  0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,\n  0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,\n  0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,\n  0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,\n  0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,\n  0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,\n  0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,\n  0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,\n  0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,\n  0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,\n  0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,\n  0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,\n  0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,\n  0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,\n  0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,\n  0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,\n  0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,\n  0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,\n  0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,\n  0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,\n  0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,\n  0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,\n  0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,\n  0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,\n  0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,\n  0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,\n  0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,\n  0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,\n  0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,\n  0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,\n  0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,\n  0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,\n  0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,\n  0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,\n  0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,\n  0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,\n  0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,\n  0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,\n  0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,\n  0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,\n  0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,\n  0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,\n  0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,\n  0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,\n  0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,\n  0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,\n  0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,\n  0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,\n  0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,\n  0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,\n  0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,\n  0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,\n  0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,\n  0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,\n  0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,\n  0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,\n  0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,\n  0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,\n  0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,\n  0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,\n  0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,\n  0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,\n  0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,\n  0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,\n  0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,\n  0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,\n  0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,\n  0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,\n  0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,\n  0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,\n  0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,\n  0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,\n  0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,\n  0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,\n  0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,\n  0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,\n  0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,\n  0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,\n  0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,\n  0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,\n  0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,\n  0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,\n  0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,\n  0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,\n  0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,\n  0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,\n  0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,\n  0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,\n  0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,\n  0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,\n  0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,\n  0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,\n  0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,\n  0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,\n  0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,\n  0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,\n  0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,\n  0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,\n  0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,\n  0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,\n  0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,\n  0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,\n  0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,\n  0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,\n  0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,\n  0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,\n  0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,\n  0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,\n  0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,\n  0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,\n  0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,\n  0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,\n  0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,\n  0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,\n  0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,\n  0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,\n  0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,\n  0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,\n  0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,\n  0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,\n  0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,\n  0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,\n  0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,\n  0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,\n  0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,\n  0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,\n  0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,\n  0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,\n  0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,\n  0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,\n  0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,\n  0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,\n  0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,\n  0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,\n  0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,\n  0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,\n  0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,\n  0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,\n  0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,\n  0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,\n  0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,\n  0x2737922, 0xee75323c, 0x270088e, 0xee81485c,\n  0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,\n  0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,\n  0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,\n  0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,\n  0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,\n  0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,\n  0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,\n  0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,\n  0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,\n  0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,\n  0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,\n  0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,\n  0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,\n  0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,\n  0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,\n  0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,\n  0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,\n  0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,\n  0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,\n  0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,\n  0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,\n  0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,\n  0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,\n  0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,\n  0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,\n  0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,\n  0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,\n  0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,\n  0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,\n  0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,\n  0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,\n  0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,\n  0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,\n  0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,\n  0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,\n  0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,\n  0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,\n  0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,\n  0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,\n  0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,\n  0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,\n  0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,\n  0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,\n  0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,\n  0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,\n  0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,\n  0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,\n  0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,\n  0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,\n  0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,\n  0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,\n  0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,\n  0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,\n  0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,\n  0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,\n  0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,\n  0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,\n  0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,\n  0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,\n  0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,\n  0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,\n  0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,\n  0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,\n  0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,\n  0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,\n  0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,\n  0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,\n  0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,\n  0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,\n  0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,\n  0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,\n  0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,\n  0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,\n  0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,\n  0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,\n  0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,\n  0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,\n  0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,\n  0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,\n  0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,\n  0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,\n  0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,\n  0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,\n  0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,\n  0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,\n  0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,\n  0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,\n  0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,\n  0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,\n  0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,\n  0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,\n  0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,\n  0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,\n  0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,\n  0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,\n  0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,\n  0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,\n  0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,\n  0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,\n  0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,\n  0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,\n  0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,\n  0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,\n  0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,\n  0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,\n  0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,\n  0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,\n  0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,\n  0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,\n  0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,\n  0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,\n  0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,\n  0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,\n  0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,\n  0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,\n  0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,\n  0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,\n  0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,\n  0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,\n  0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,\n  0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,\n  0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,\n  0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,\n  0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,\n  0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,\n  0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,\n  0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,\n  0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,\n  0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,\n  0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,\n  0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,\n  0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,\n  0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,\n  0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,\n  0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,\n  0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,\n  0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,\n  0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,\n  0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,\n  0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,\n  0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,\n  0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,\n  0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,\n  0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,\n  0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,\n  0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,\n  0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,\n  0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,\n  0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,\n  0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,\n  0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,\n  0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,\n  0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,\n  0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,\n  0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,\n  0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,\n  0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,\n  0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,\n  0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,\n  0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,\n  0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,\n  0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,\n  0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,\n  0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,\n  0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,\n  0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,\n  0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,\n  0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,\n  0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,\n  0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,\n  0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,\n  0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,\n  0x13bd3, 0xff36f170, 0x11594, 0xff438234,\n  0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,\n  0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,\n  0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,\n  0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,\n  0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,\n  0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,\n  0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,\n  0x0, 0x0, 0x13c, 0xc90fe,\n  0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,\n  0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,\n  0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,\n  0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,\n  0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,\n  0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,\n  0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,\n  0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,\n  0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,\n  0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,\n  0x25519, 0x1147271, 0x28c9c, 0x12102f4,\n  0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,\n  0x341f4, 0x146b438, 0x38356, 0x153448c,\n  0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,\n  0x45648, 0x178f536, 0x4a188, 0x1858552,\n  0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,\n  0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,\n  0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,\n  0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,\n  0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,\n  0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,\n  0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,\n  0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,\n  0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,\n  0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,\n  0xd077c, 0x28d472e, 0xd88fd, 0x299d590,\n  0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,\n  0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,\n  0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,\n  0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,\n  0x128574, 0x30ad245, 0x131f9b, 0x3175f91,\n  0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,\n  0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,\n  0x164757, 0x3562038, 0x16f047, 0x362acc5,\n  0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,\n  0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,\n  0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,\n  0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,\n  0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,\n  0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,\n  0x2064ab, 0x405c361, 0x213018, 0x4124dee,\n  0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,\n  0x23a124, 0x437eca4, 0x24766a, 0x444768d,\n  0x254e27, 0x451004d, 0x262859, 0x45d89e2,\n  0x270502, 0x46a134c, 0x27e421, 0x4769c8b,\n  0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,\n  0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,\n  0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,\n  0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,\n  0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,\n  0x321ce0, 0x5007674, 0x331986, 0x50cfd82,\n  0x3418a2, 0x519845e, 0x351a33, 0x5260b08,\n  0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,\n  0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,\n  0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,\n  0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,\n  0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,\n  0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,\n  0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,\n  0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,\n  0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,\n  0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,\n  0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,\n  0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,\n  0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,\n  0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,\n  0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,\n  0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,\n  0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,\n  0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,\n  0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,\n  0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,\n  0x669e18, 0x726dbae, 0x6806ce, 0x7335862,\n  0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,\n  0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,\n  0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,\n  0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,\n  0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,\n  0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,\n  0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,\n  0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,\n  0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,\n  0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,\n  0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,\n  0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,\n  0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,\n  0x91b01d, 0x884104b, 0x935d64, 0x8908483,\n  0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,\n  0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,\n  0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,\n  0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,\n  0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,\n  0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,\n  0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,\n  0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,\n  0xb15502, 0x9640837, 0xb32e42, 0x9707635,\n  0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,\n  0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,\n  0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,\n  0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,\n  0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,\n  0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,\n  0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,\n  0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,\n  0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,\n  0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,\n  0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,\n  0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,\n  0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,\n  0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,\n  0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,\n  0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,\n  0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,\n  0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,\n  0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,\n  0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,\n  0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,\n  0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,\n  0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,\n  0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,\n  0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,\n  0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,\n  0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,\n  0x1278104, 0xc19b374, 0x129e276, 0xc260a31,\n  0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,\n  0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,\n  0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,\n  0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,\n  0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,\n  0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,\n  0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,\n  0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,\n  0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,\n  0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,\n  0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,\n  0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,\n  0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,\n  0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,\n  0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,\n  0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,\n  0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,\n  0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,\n  0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,\n  0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,\n  0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,\n  0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,\n  0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,\n  0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,\n  0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,\n  0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,\n  0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,\n  0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,\n  0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,\n  0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,\n  0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,\n  0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,\n  0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,\n  0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,\n  0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,\n  0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,\n  0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,\n  0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,\n  0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,\n  0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,\n  0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,\n  0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,\n  0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,\n  0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,\n  0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,\n  0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,\n  0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,\n  0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,\n  0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,\n  0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,\n  0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,\n  0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,\n  0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,\n  0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,\n  0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,\n  0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,\n  0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,\n  0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,\n  0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,\n  0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,\n  0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,\n  0x296615d, 0x12038584, 0x299ec05, 0x120f941a,\n  0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,\n  0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,\n  0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,\n  0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,\n  0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,\n  0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,\n  0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,\n  0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,\n  0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,\n  0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,\n  0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,\n  0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,\n  0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,\n  0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,\n  0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,\n  0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,\n  0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,\n  0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,\n  0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,\n  0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,\n  0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,\n  0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,\n  0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,\n  0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,\n  0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,\n  0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,\n  0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,\n  0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,\n  0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,\n  0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,\n  0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,\n  0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,\n  0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,\n  0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,\n  0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,\n  0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,\n  0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,\n  0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,\n  0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,\n  0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,\n  0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,\n  0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,\n  0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,\n  0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,\n  0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,\n  0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,\n  0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,\n  0x414392b, 0x167b949d, 0x418a46d, 0x16875823,\n  0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,\n  0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,\n  0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,\n  0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,\n  0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,\n  0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,\n  0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,\n  0x45c0219, 0x173763c9, 0x460923b, 0x17431933,\n  0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,\n  0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,\n  0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,\n  0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,\n  0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,\n  0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,\n  0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,\n  0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,\n  0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,\n  0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,\n  0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,\n  0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,\n  0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,\n  0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,\n  0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,\n  0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,\n  0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,\n  0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,\n  0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,\n  0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,\n  0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,\n  0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,\n  0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,\n  0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,\n  0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,\n  0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,\n  0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,\n  0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,\n  0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,\n  0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,\n  0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,\n  0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,\n  0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,\n  0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,\n  0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,\n  0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,\n  0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,\n  0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,\n  0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,\n  0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,\n  0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,\n  0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,\n  0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,\n  0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,\n  0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,\n  0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,\n  0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,\n  0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,\n  0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,\n  0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,\n  0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,\n  0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,\n  0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,\n  0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,\n  0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,\n  0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,\n  0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,\n  0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,\n  0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,\n  0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,\n  0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,\n  0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,\n  0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,\n  0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,\n  0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,\n  0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,\n  0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,\n  0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,\n  0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,\n  0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,\n  0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,\n  0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,\n  0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,\n  0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,\n  0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,\n  0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,\n  0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,\n  0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,\n  0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,\n  0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,\n  0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,\n  0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,\n  0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,\n  0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,\n  0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,\n  0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,\n  0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,\n  0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,\n  0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,\n  0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,\n  0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,\n  0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,\n  0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,\n  0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,\n  0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,\n  0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,\n  0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,\n  0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,\n  0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,\n  0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,\n  0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,\n  0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,\n  0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,\n  0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,\n  0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,\n  0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,\n  0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,\n  0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,\n  0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,\n  0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,\n  0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,\n  0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,\n  0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,\n  0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,\n  0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,\n  0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,\n  0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,\n  0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,\n  0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,\n  0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,\n  0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,\n  0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,\n  0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,\n  0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,\n  0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,\n  0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,\n  0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,\n  0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,\n  0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,\n  0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,\n  0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,\n  0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,\n  0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,\n  0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,\n  0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,\n  0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,\n  0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,\n  0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,\n  0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,\n  0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,\n  0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,\n  0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,\n  0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,\n  0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,\n  0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,\n  0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,\n  0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,\n  0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,\n  0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,\n  0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,\n  0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,\n  0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,\n  0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,\n  0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,\n  0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,\n  0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,\n  0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,\n  0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,\n  0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,\n  0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,\n  0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,\n  0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,\n  0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,\n  0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,\n  0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,\n  0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,\n  0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,\n  0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,\n  0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,\n  0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,\n  0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,\n  0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,\n  0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,\n  0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,\n  0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,\n  0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,\n  0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,\n  0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,\n  0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,\n  0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,\n  0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,\n  0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,\n  0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,\n  0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,\n  0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,\n  0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,\n  0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,\n  0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,\n  0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,\n  0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,\n  0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,\n  0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,\n  0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,\n  0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,\n  0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,\n  0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,\n  0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,\n  0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,\n  0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,\n  0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,\n  0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,\n  0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,\n  0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,\n  0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,\n  0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,\n  0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,\n  0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,\n  0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,\n  0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,\n  0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,\n  0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,\n  0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,\n  0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,\n  0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,\n  0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,\n  0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,\n  0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,\n  0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,\n  0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,\n  0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,\n  0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,\n  0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,\n  0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,\n  0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,\n  0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,\n  0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,\n  0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,\n  0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,\n  0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,\n  0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,\n  0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,\n  0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,\n  0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,\n  0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,\n  0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,\n  0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,\n  0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,\n  0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,\n  0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,\n  0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,\n  0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,\n  0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,\n  0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,\n  0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,\n  0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,\n  0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,\n  0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,\n  0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,\n  0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,\n  0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,\n  0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,\n  0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,\n  0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,\n  0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,\n  0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,\n  0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,\n  0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,\n  0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,\n  0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,\n  0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,\n  0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,\n  0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,\n  0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,\n  0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,\n  0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,\n  0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,\n  0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,\n  0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,\n  0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,\n  0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,\n  0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,\n  0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,\n  0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,\n  0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,\n  0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,\n  0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,\n  0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,\n  0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,\n  0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,\n  0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,\n  0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,\n  0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,\n  0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,\n  0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,\n  0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,\n  0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,\n  0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,\n  0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,\n  0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,\n  0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,\n  0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,\n  0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,\n  0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,\n  0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,\n  0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,\n  0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,\n  0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,\n  0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,\n  0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,\n  0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,\n  0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,\n  0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,\n  0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,\n  0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,\n  0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,\n  0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,\n  0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,\n  0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,\n  0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,\n  0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,\n  0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,\n  0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,\n  0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,\n  0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,\n  0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,\n  0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,\n  0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,\n  0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,\n  0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,\n  0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,\n  0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,\n  0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,\n  0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,\n  0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,\n  0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,\n  0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,\n  0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,\n  0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,\n  0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,\n  0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,\n  0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,\n  0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,\n  0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,\n  0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,\n  0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,\n  0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,\n  0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,\n  0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,\n  0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,\n  0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,\n  0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,\n  0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,\n  0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,\n  0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,\n  0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,\n  0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,\n  0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,\n  0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,\n  0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,\n  0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,\n  0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,\n  0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,\n  0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,\n  0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,\n  0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,\n  0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,\n  0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,\n  0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,\n  0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,\n  0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,\n  0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,\n  0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,\n  0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,\n  0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,\n  0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,\n  0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,\n  0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,\n  0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,\n  0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,\n  0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,\n  0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,\n  0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,\n  0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,\n  0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,\n  0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,\n  0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,\n  0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,\n  0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,\n  0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,\n  0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,\n  0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,\n  0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,\n  0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,\n  0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,\n  0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,\n  0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,\n  0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,\n  0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,\n  0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,\n  0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,\n  0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,\n  0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,\n  0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,\n  0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,\n  0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,\n  0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,\n  0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,\n  0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,\n  0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,\n  0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,\n  0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,\n  0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,\n  0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,\n  0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,\n  0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,\n  0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,\n  0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,\n  0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,\n  0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,\n  0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,\n  0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,\n  0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,\n  0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,\n  0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,\n  0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,\n  0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,\n  0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,\n  0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,\n  0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,\n  0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,\n  0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,\n  0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,\n  0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,\n  0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,\n  0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,\n  0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,\n  0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,\n  0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,\n  0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,\n  0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,\n  0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,\n  0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,\n  0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,\n  0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,\n  0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,\n  0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,\n  0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,\n  0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,\n  0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,\n  0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,\n  0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,\n  0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,\n  0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,\n  0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,\n  0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,\n  0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,\n  0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,\n  0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,\n  0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,\n  0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,\n  0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,\n  0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,\n  0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,\n  0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,\n  0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,\n  0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,\n  0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,\n  0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,\n  0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,\n  0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,\n  0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,\n  0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,\n  0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,\n  0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,\n  0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,\n  0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,\n  0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,\n  0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,\n  0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,\n  0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,\n  0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,\n  0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,\n  0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,\n  0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,\n  0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,\n  0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,\n  0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,\n  0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,\n  0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,\n  0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,\n  0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,\n  0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,\n  0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,\n  0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,\n  0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,\n  0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,\n  0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,\n  0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,\n  0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,\n  0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,\n  0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,\n  0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,\n  0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,\n  0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,\n  0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,\n  0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,\n  0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,\n  0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,\n  0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,\n  0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,\n  0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,\n  0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,\n  0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,\n  0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,\n  0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,\n  0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,\n  0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,\n  0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,\n  0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,\n  0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,\n  0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,\n  0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,\n  0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,\n  0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,\n  0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,\n  0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,\n  0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,\n  0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,\n  0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,\n  0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,\n  0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,\n  0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,\n  0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,\n  0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,\n  0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,\n  0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,\n  0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,\n  0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,\n  0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,\n  0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,\n  0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,\n  0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,\n  0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,\n  0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,\n  0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,\n  0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,\n  0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,\n  0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,\n  0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,\n  0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,\n  0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,\n  0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,\n  0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,\n  0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,\n  0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,\n  0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,\n  0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,\n  0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,\n  0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,\n  0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,\n  0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,\n  0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,\n  0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,\n  0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,\n  0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,\n  0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,\n  0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,\n  0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,\n  0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,\n  0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,\n  0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,\n  0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,\n  0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,\n  0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,\n  0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,\n  0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,\n  0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,\n  0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,\n  0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,\n  0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,\n  0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,\n  0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,\n  0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,\n  0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,\n  0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,\n  0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,\n  0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,\n  0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,\n  0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,\n  0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,\n  0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,\n  0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,\n  0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,\n  0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,\n  0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,\n  0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,\n  0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,\n  0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,\n  0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,\n  0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,\n  0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,\n  0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,\n  0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,\n  0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,\n  0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,\n  0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,\n  0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,\n  0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,\n  0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,\n  0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,\n  0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,\n  0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,\n  0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,\n  0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,\n  0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,\n  0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,\n  0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,\n  0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,\n  0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,\n  0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,\n  0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,\n  0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,\n  0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,\n  0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,\n  0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,\n  0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,\n  0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,\n  0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,\n  0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,\n  0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,\n  0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,\n  0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,\n  0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,\n  0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,\n  0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,\n  0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,\n  0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,\n  0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,\n  0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,\n  0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,\n  0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,\n  0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,\n  0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,\n  0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,\n  0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,\n  0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,\n  0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,\n  0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,\n  0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,\n  0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,\n  0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,\n  0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,\n  0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,\n  0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,\n  0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,\n  0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,\n  0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,\n  0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,\n  0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,\n  0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,\n  0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,\n  0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,\n  0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,\n  0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,\n  0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,\n  0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,\n  0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,\n  0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,\n  0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,\n  0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,\n  0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,\n  0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,\n  0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,\n  0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,\n  0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,\n  0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,\n  0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,\n  0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,\n  0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,\n  0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,\n  0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,\n  0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,\n  0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,\n  0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,\n  0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,\n  0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,\n  0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,\n  0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,\n  0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,\n  0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,\n  0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,\n  0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,\n  0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,\n  0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,\n  0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,\n  0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,\n  0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,\n  0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,\n  0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,\n  0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,\n  0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,\n  0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,\n  0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,\n  0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,\n  0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,\n  0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,\n  0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,\n  0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,\n  0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,\n  0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,\n  0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,\n  0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,\n  0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,\n  0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,\n  0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,\n  0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,\n  0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,\n  0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,\n  0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,\n  0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,\n  0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,\n  0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,\n  0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,\n  0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,\n  0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,\n  0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,\n  0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,\n  0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,\n  0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,\n  0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,\n  0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,\n  0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,\n  0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,\n  0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,\n  0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,\n  0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,\n  0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,\n  0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,\n  0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,\n  0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,\n  0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,\n  0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,\n  0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,\n  0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,\n  0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,\n  0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,\n  0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,\n  0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,\n  0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,\n  0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,\n  0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,\n  0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,\n  0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,\n  0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,\n  0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,\n  0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,\n  0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,\n  0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,\n  0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,\n  0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,\n  0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,\n  0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,\n  0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,\n  0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,\n  0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,\n  0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,\n  0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,\n  0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,\n  0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,\n  0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,\n  0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,\n  0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,\n  0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,\n  0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,\n  0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,\n  0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,\n  0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,\n  0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,\n  0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,\n  0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,\n  0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,\n  0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,\n  0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,\n  0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,\n  0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,\n  0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,\n  0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,\n  0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,\n  0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,\n  0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,\n  0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,\n};\n\n\n/**    \n* \\par   \n* Generation of realCoefBQ31 array:    \n* \\par    \n*  n = 4096        \n* 
for (i = 0; i < n; i++)    \n* {    \n*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n* } 
    \n* \\par    \n* Convert to fixed point Q31 format    \n*     round(pBTable[i] * pow(2, 31))    \n*    \n*/\n\nstatic const q31_t realCoefBQ31[8192] = {\n  0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,\n  0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,\n  0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,\n  0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,\n  0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,\n  0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,\n  0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,\n  0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,\n  0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,\n  0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,\n  0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,\n  0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,\n  0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,\n  0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,\n  0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,\n  0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,\n  0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,\n  0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,\n  0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,\n  0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,\n  0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,\n  0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,\n  0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,\n  0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,\n  0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,\n  0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,\n  0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,\n  0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,\n  0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,\n  0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,\n  0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,\n  0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,\n  0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,\n  0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,\n  0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,\n  0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,\n  0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,\n  0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,\n  0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,\n  0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,\n  0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,\n  0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,\n  0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,\n  0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,\n  0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,\n  0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,\n  0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,\n  0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,\n  0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,\n  0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,\n  0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,\n  0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,\n  0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,\n  0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,\n  0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,\n  0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,\n  0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,\n  0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,\n  0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,\n  0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,\n  0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,\n  0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,\n  0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,\n  0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,\n  0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,\n  0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,\n  0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,\n  0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,\n  0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,\n  0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,\n  0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,\n  0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,\n  0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,\n  0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,\n  0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,\n  0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,\n  0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,\n  0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,\n  0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,\n  0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,\n  0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,\n  0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,\n  0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,\n  0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,\n  0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,\n  0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,\n  0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,\n  0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,\n  0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,\n  0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,\n  0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,\n  0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,\n  0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,\n  0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,\n  0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,\n  0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,\n  0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,\n  0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,\n  0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,\n  0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,\n  0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,\n  0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,\n  0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,\n  0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,\n  0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,\n  0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,\n  0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,\n  0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,\n  0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,\n  0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,\n  0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,\n  0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,\n  0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,\n  0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,\n  0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,\n  0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,\n  0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,\n  0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,\n  0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,\n  0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,\n  0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,\n  0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,\n  0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,\n  0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,\n  0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,\n  0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,\n  0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,\n  0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,\n  0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,\n  0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,\n  0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,\n  0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,\n  0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,\n  0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,\n  0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,\n  0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,\n  0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,\n  0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,\n  0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,\n  0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,\n  0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,\n  0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,\n  0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,\n  0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,\n  0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,\n  0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,\n  0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,\n  0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,\n  0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,\n  0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,\n  0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,\n  0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,\n  0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,\n  0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,\n  0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,\n  0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,\n  0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,\n  0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,\n  0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,\n  0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,\n  0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,\n  0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,\n  0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,\n  0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,\n  0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,\n  0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,\n  0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,\n  0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,\n  0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,\n  0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,\n  0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,\n  0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,\n  0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,\n  0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,\n  0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,\n  0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,\n  0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,\n  0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,\n  0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,\n  0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,\n  0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,\n  0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,\n  0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,\n  0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,\n  0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,\n  0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,\n  0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,\n  0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,\n  0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,\n  0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,\n  0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,\n  0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,\n  0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,\n  0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,\n  0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,\n  0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,\n  0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,\n  0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,\n  0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,\n  0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,\n  0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,\n  0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,\n  0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,\n  0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,\n  0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,\n  0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,\n  0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,\n  0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,\n  0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,\n  0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,\n  0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,\n  0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,\n  0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,\n  0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,\n  0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,\n  0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,\n  0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,\n  0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,\n  0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,\n  0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,\n  0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,\n  0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,\n  0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,\n  0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,\n  0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,\n  0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,\n  0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,\n  0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,\n  0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,\n  0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,\n  0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,\n  0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,\n  0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,\n  0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,\n  0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,\n  0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,\n  0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,\n  0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,\n  0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,\n  0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,\n  0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,\n  0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,\n  0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,\n  0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,\n  0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,\n  0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,\n  0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,\n  0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,\n  0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,\n  0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,\n  0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,\n  0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,\n  0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,\n  0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,\n  0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,\n  0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,\n  0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,\n  0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,\n  0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,\n  0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,\n  0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,\n  0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,\n  0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,\n  0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,\n  0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,\n  0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,\n  0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,\n  0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,\n  0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,\n  0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,\n  0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,\n  0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,\n  0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,\n  0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,\n  0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,\n  0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,\n  0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,\n  0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,\n  0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,\n  0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,\n  0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,\n  0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,\n  0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,\n  0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,\n  0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,\n  0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,\n  0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,\n  0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,\n  0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,\n  0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,\n  0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,\n  0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,\n  0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,\n  0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,\n  0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,\n  0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,\n  0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,\n  0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,\n  0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,\n  0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,\n  0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,\n  0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,\n  0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,\n  0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,\n  0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,\n  0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,\n  0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,\n  0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,\n  0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,\n  0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,\n  0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,\n  0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,\n  0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,\n  0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,\n  0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,\n  0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,\n  0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,\n  0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,\n  0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,\n  0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,\n  0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,\n  0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,\n  0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,\n  0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,\n  0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,\n  0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,\n  0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,\n  0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,\n  0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,\n  0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,\n  0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,\n  0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,\n  0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,\n  0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,\n  0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,\n  0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,\n  0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,\n  0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,\n  0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,\n  0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,\n  0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,\n  0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,\n  0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,\n  0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,\n  0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,\n  0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,\n  0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,\n  0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,\n  0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,\n  0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,\n  0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,\n  0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,\n  0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,\n  0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,\n  0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,\n  0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,\n  0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,\n  0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,\n  0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,\n  0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,\n  0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,\n  0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,\n  0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,\n  0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,\n  0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,\n  0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,\n  0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,\n  0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,\n  0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,\n  0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,\n  0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,\n  0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,\n  0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,\n  0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,\n  0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,\n  0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,\n  0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,\n  0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,\n  0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,\n  0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,\n  0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,\n  0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,\n  0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,\n  0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,\n  0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,\n  0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,\n  0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,\n  0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,\n  0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,\n  0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,\n  0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,\n  0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,\n  0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,\n  0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,\n  0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,\n  0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,\n  0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,\n  0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,\n  0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,\n  0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,\n  0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,\n  0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,\n  0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,\n  0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,\n  0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,\n  0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,\n  0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,\n  0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,\n  0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,\n  0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,\n  0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,\n  0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,\n  0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,\n  0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,\n  0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,\n  0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,\n  0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,\n  0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,\n  0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,\n  0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,\n  0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,\n  0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,\n  0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,\n  0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,\n  0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,\n  0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,\n  0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,\n  0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,\n  0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,\n  0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,\n  0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,\n  0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,\n  0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,\n  0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,\n  0x67878893, 0x32554840, 0x679169d5, 0x324d8450,\n  0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,\n  0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,\n  0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,\n  0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,\n  0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,\n  0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,\n  0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,\n  0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,\n  0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,\n  0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,\n  0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,\n  0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,\n  0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,\n  0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,\n  0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,\n  0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,\n  0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,\n  0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,\n  0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,\n  0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,\n  0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,\n  0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,\n  0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,\n  0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,\n  0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,\n  0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,\n  0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,\n  0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,\n  0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,\n  0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,\n  0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,\n  0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,\n  0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,\n  0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,\n  0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,\n  0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,\n  0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,\n  0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,\n  0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,\n  0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,\n  0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,\n  0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,\n  0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,\n  0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,\n  0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,\n  0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,\n  0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,\n  0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,\n  0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,\n  0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,\n  0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,\n  0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,\n  0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,\n  0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,\n  0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,\n  0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,\n  0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,\n  0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,\n  0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,\n  0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,\n  0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,\n  0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,\n  0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,\n  0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,\n  0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,\n  0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,\n  0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,\n  0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,\n  0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,\n  0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,\n  0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,\n  0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,\n  0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,\n  0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,\n  0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,\n  0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,\n  0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,\n  0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,\n  0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,\n  0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,\n  0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,\n  0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,\n  0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,\n  0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,\n  0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,\n  0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,\n  0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,\n  0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,\n  0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,\n  0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,\n  0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,\n  0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,\n  0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,\n  0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,\n  0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,\n  0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,\n  0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,\n  0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,\n  0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,\n  0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,\n  0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,\n  0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,\n  0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,\n  0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,\n  0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,\n  0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,\n  0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,\n  0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,\n  0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,\n  0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,\n  0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,\n  0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,\n  0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,\n  0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,\n  0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,\n  0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,\n  0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,\n  0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,\n  0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,\n  0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,\n  0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,\n  0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,\n  0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,\n  0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,\n  0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,\n  0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,\n  0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,\n  0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,\n  0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,\n  0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,\n  0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,\n  0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,\n  0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,\n  0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,\n  0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,\n  0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,\n  0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,\n  0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,\n  0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,\n  0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,\n  0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,\n  0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,\n  0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,\n  0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,\n  0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,\n  0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,\n  0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,\n  0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,\n  0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,\n  0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,\n  0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,\n  0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,\n  0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,\n  0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,\n  0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,\n  0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,\n  0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,\n  0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,\n  0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,\n  0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,\n  0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,\n  0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,\n  0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,\n  0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,\n  0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,\n  0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,\n  0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,\n  0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,\n  0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,\n  0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,\n  0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,\n  0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,\n  0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,\n  0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,\n  0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,\n  0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,\n  0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,\n  0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,\n  0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,\n  0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,\n  0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,\n  0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,\n  0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,\n  0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,\n  0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,\n  0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,\n  0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,\n  0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,\n  0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,\n  0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,\n  0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,\n  0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,\n  0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,\n  0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,\n  0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,\n  0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,\n  0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,\n  0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,\n  0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,\n  0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,\n  0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,\n  0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,\n  0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,\n  0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,\n  0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,\n  0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,\n  0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,\n  0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,\n  0x75608af1, 0x234facda, 0x756778d9, 0x23453125,\n  0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,\n  0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,\n  0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,\n  0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,\n  0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,\n  0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,\n  0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,\n  0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,\n  0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,\n  0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,\n  0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,\n  0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,\n  0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,\n  0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,\n  0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,\n  0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,\n  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0x7744ffdd, 0x2044d3d4,\n  0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,\n  0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,\n  0x77649341, 0x200e8190, 0x776add88, 0x2003a099,\n  0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,\n  0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,\n  0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,\n  0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,\n  0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,\n  0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,\n  0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,\n  0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,\n  0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,\n  0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,\n  0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,\n  0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,\n  0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,\n  0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,\n  0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,\n  0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,\n  0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,\n  0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,\n  0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,\n  0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,\n  0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,\n  0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,\n  0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,\n  0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,\n  0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,\n  0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,\n  0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,\n  0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,\n  0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,\n  0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,\n  0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,\n  0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,\n  0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,\n  0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,\n  0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,\n  0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,\n  0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,\n  0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,\n  0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,\n  0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,\n  0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,\n  0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,\n  0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,\n  0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,\n  0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,\n  0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,\n  0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,\n  0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,\n  0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,\n  0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,\n  0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,\n  0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,\n  0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,\n  0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,\n  0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,\n  0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,\n  0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,\n  0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,\n  0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,\n  0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,\n  0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,\n  0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,\n  0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,\n  0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,\n  0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,\n  0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,\n  0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,\n  0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,\n  0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,\n  0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,\n  0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,\n  0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,\n  0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,\n  0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,\n  0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,\n  0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,\n  0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,\n  0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,\n  0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,\n  0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,\n  0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,\n  0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,\n  0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,\n  0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,\n  0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,\n  0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,\n  0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,\n  0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,\n  0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,\n  0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,\n  0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,\n  0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,\n  0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,\n  0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,\n  0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,\n  0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,\n  0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,\n  0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,\n  0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,\n  0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,\n  0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,\n  0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,\n  0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,\n  0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,\n  0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,\n  0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,\n  0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,\n  0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,\n  0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,\n  0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,\n  0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,\n  0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,\n  0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,\n  0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,\n  0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,\n  0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,\n  0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,\n  0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,\n  0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,\n  0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,\n  0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,\n  0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,\n  0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,\n  0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,\n  0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,\n  0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,\n  0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,\n  0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,\n  0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,\n  0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,\n  0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,\n  0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,\n  0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,\n  0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,\n  0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,\n  0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,\n  0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,\n  0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,\n  0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,\n  0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,\n  0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,\n  0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,\n  0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,\n  0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,\n  0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,\n  0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,\n  0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,\n  0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,\n  0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,\n  0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,\n  0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,\n  0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,\n  0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,\n  0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,\n  0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,\n  0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,\n  0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,\n  0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,\n  0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,\n  0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,\n  0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,\n  0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,\n  0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,\n  0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,\n  0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,\n  0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,\n  0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,\n  0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,\n  0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,\n  0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,\n  0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,\n  0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,\n  0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,\n  0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,\n  0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,\n  0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,\n  0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,\n  0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,\n  0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,\n  0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,\n  0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,\n  0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,\n  0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,\n  0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,\n  0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,\n  0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,\n  0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,\n  0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,\n  0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,\n  0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,\n  0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,\n  0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,\n  0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,\n  0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,\n  0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,\n  0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,\n  0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,\n  0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,\n  0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,\n  0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,\n  0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,\n  0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,\n  0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,\n  0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,\n  0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,\n  0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,\n  0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,\n  0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,\n  0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,\n  0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,\n  0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,\n  0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,\n  0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,\n  0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,\n  0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,\n  0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,\n  0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,\n  0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,\n  0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,\n  0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,\n  0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,\n  0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,\n  0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,\n  0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,\n  0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,\n  0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,\n  0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,\n  0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,\n  0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,\n  0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,\n  0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,\n  0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,\n  0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,\n  0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,\n  0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,\n  0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,\n  0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,\n  0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,\n  0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,\n  0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,\n  0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,\n  0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,\n  0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,\n  0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,\n  0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,\n  0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,\n  0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,\n  0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,\n  0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,\n  0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,\n  0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,\n  0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,\n  0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,\n  0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,\n  0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,\n  0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,\n  0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,\n  0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,\n  0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,\n  0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,\n  0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,\n  0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,\n  0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,\n  0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,\n  0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,\n  0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,\n  0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,\n  0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,\n  0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,\n  0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,\n  0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,\n  0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,\n  0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,\n  0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,\n  0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,\n  0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,\n  0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,\n  0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,\n  0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,\n  0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,\n  0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,\n  0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,\n  0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,\n  0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,\n  0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,\n  0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,\n  0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,\n  0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,\n  0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,\n  0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,\n  0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,\n  0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,\n  0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,\n  0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,\n  0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,\n  0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,\n  0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,\n  0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,\n  0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,\n  0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,\n  0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,\n  0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,\n  0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,\n  0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,\n  0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,\n  0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,\n  0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,\n  0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,\n  0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,\n  0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,\n  0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,\n  0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,\n  0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,\n  0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,\n  0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,\n  0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,\n  0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,\n  0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,\n  0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,\n  0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,\n  0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,\n  0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,\n  0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,\n  0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,\n  0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,\n  0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,\n  0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,\n  0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,\n  0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,\n  0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,\n  0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,\n  0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,\n  0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,\n  0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,\n  0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,\n  0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,\n  0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,\n  0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,\n  0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,\n  0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,\n  0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,\n  0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,\n  0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,\n  0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,\n  0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,\n  0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,\n  0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,\n  0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,\n  0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,\n  0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,\n  0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,\n  0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,\n  0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,\n  0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,\n  0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,\n  0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,\n  0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,\n  0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,\n  0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,\n  0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,\n  0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,\n  0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,\n  0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,\n  0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,\n  0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,\n  0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,\n  0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,\n  0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,\n  0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,\n  0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,\n  0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,\n  0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,\n  0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,\n  0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,\n  0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,\n  0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,\n  0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,\n  0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,\n  0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,\n  0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,\n  0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,\n  0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,\n  0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,\n  0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,\n  0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,\n  0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,\n  0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,\n  0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,\n  0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,\n  0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,\n  0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,\n  0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,\n  0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,\n  0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,\n  0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,\n  0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,\n  0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,\n  0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,\n  0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,\n  0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,\n  0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,\n  0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,\n  0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,\n  0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,\n  0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,\n  0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,\n  0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,\n  0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,\n  0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,\n  0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,\n  0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,\n  0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,\n  0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,\n  0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,\n  0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,\n  0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,\n  0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,\n  0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,\n  0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,\n  0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,\n  0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,\n  0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,\n  0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,\n  0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,\n  0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,\n  0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,\n  0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,\n  0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,\n  0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,\n  0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,\n  0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,\n  0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,\n  0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,\n  0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,\n  0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,\n  0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,\n  0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,\n  0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,\n  0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,\n  0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,\n  0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,\n  0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,\n  0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,\n  0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,\n  0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,\n  0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,\n  0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,\n  0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,\n  0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,\n  0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,\n  0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,\n  0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,\n  0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,\n  0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,\n  0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,\n  0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,\n  0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,\n  0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,\n  0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,\n  0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,\n  0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,\n  0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,\n  0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,\n  0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,\n  0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,\n  0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,\n  0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,\n  0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,\n  0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,\n  0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,\n  0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,\n  0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,\n  0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,\n  0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,\n  0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,\n  0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,\n  0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,\n  0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,\n  0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,\n  0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,\n  0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,\n  0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,\n  0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,\n  0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,\n  0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,\n  0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,\n  0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,\n  0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,\n  0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,\n  0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,\n  0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,\n  0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,\n  0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,\n  0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,\n  0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,\n  0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,\n  0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,\n  0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,\n  0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,\n  0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,\n  0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,\n  0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,\n  0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,\n  0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,\n  0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,\n  0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,\n  0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,\n  0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,\n  0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,\n  0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,\n  0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,\n  0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,\n  0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,\n  0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,\n  0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,\n  0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,\n  0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,\n  0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,\n  0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,\n  0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,\n  0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,\n  0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,\n  0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,\n  0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,\n  0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,\n  0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,\n  0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,\n  0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,\n  0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,\n  0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,\n  0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,\n  0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,\n  0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,\n  0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,\n  0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,\n  0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,\n  0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,\n  0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,\n  0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,\n  0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,\n  0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,\n  0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,\n  0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,\n  0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,\n  0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,\n  0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,\n  0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,\n  0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,\n  0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,\n  0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,\n  0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,\n  0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,\n  0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,\n  0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,\n  0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,\n  0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,\n  0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,\n  0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,\n  0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,\n  0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,\n  0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,\n  0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,\n  0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,\n  0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,\n  0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,\n  0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,\n  0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,\n  0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,\n  0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,\n  0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,\n  0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,\n  0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,\n  0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,\n  0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,\n  0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,\n  0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,\n  0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,\n  0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,\n  0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,\n  0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,\n  0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,\n  0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,\n  0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,\n  0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,\n  0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,\n  0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,\n  0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,\n  0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,\n  0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,\n  0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,\n  0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,\n  0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,\n  0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,\n  0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,\n  0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,\n  0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,\n  0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,\n  0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,\n  0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,\n  0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,\n  0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,\n  0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,\n  0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,\n  0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,\n  0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,\n  0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,\n  0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,\n  0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,\n  0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,\n  0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,\n  0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,\n  0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,\n  0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,\n  0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,\n  0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,\n  0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,\n  0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,\n  0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,\n  0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,\n  0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,\n  0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,\n  0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,\n  0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,\n  0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,\n  0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,\n  0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,\n  0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,\n  0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,\n  0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,\n  0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,\n  0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,\n  0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,\n  0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,\n  0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,\n  0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,\n  0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,\n  0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,\n  0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,\n  0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,\n  0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,\n  0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,\n  0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,\n  0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,\n  0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,\n  0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,\n  0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,\n  0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,\n  0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,\n  0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,\n  0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,\n  0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,\n  0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,\n  0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,\n  0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,\n  0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,\n  0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,\n  0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,\n  0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,\n  0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,\n  0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,\n  0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,\n  0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,\n  0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,\n  0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,\n  0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,\n  0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,\n  0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,\n  0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,\n  0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,\n  0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,\n  0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,\n  0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,\n  0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,\n  0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,\n  0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,\n  0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,\n  0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,\n  0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,\n  0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,\n  0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,\n  0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,\n  0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,\n  0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,\n  0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,\n  0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,\n  0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,\n  0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,\n  0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,\n  0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,\n  0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,\n  0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,\n  0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,\n  0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,\n  0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,\n  0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,\n  0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,\n  0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,\n  0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,\n  0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,\n  0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,\n  0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,\n  0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,\n  0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,\n  0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,\n  0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,\n  0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,\n  0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,\n  0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,\n  0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,\n  0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,\n  0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,\n  0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,\n  0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,\n  0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,\n  0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,\n  0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,\n  0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,\n  0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,\n  0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,\n  0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,\n  0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,\n  0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,\n  0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,\n  0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,\n  0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,\n  0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,\n  0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,\n  0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,\n  0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,\n  0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,\n  0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,\n  0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,\n  0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,\n  0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,\n  0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,\n  0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,\n  0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,\n  0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,\n  0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,\n  0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,\n  0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,\n  0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,\n  0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,\n  0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,\n  0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,\n  0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,\n  0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,\n  0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,\n  0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,\n  0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,\n  0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,\n  0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,\n  0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,\n  0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,\n  0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,\n  0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,\n  0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,\n  0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,\n  0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,\n  0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,\n  0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,\n  0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,\n  0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,\n  0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,\n  0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,\n  0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,\n  0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,\n  0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,\n  0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,\n  0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,\n  0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,\n  0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,\n  0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,\n  0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,\n  0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,\n  0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,\n  0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,\n  0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,\n  0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,\n  0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,\n  0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,\n  0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,\n  0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,\n  0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,\n  0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,\n  0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,\n  0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,\n  0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,\n  0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,\n  0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,\n  0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,\n  0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,\n  0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,\n  0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,\n  0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,\n  0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,\n  0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,\n  0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,\n  0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,\n  0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,\n  0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,\n  0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,\n  0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,\n  0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,\n  0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,\n  0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,\n  0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,\n  0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,\n  0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,\n  0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,\n  0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,\n  0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,\n  0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,\n  0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,\n  0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,\n  0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,\n  0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,\n  0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,\n  0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,\n  0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,\n  0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,\n  0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,\n  0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,\n  0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,\n  0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,\n  0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,\n  0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,\n  0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,\n  0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,\n  0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,\n  0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,\n  0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,\n  0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,\n  0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,\n  0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,\n  0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,\n  0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,\n  0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,\n  0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,\n  0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,\n  0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,\n  0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,\n  0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,\n  0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,\n  0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,\n  0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,\n  0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,\n  0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,\n  0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,\n  0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,\n  0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,\n  0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,\n  0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,\n  0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,\n  0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,\n  0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,\n  0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,\n  0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,\n  0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,\n  0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,\n  0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,\n  0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,\n  0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,\n  0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,\n  0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,\n  0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,\n  0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,\n  0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,\n  0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,\n  0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,\n  0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,\n  0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,\n  0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,\n  0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,\n  0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,\n  0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,\n  0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,\n  0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,\n  0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,\n  0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,\n  0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,\n  0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,\n  0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,\n  0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,\n  0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,\n  0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,\n  0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,\n  0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,\n  0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,\n  0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,\n  0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,\n  0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,\n  0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,\n  0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,\n  0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,\n  0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,\n  0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,\n  0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,\n  0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,\n  0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,\n  0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,\n  0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,\n  0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,\n  0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,\n  0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,\n  0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,\n  0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,\n  0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,\n  0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,\n  0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,\n  0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,\n  0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,\n  0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,\n  0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,\n  0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,\n  0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,\n  0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,\n  0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,\n  0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,\n  0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,\n  0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,\n  0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,\n  0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,\n  0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,\n  0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,\n  0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,\n  0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,\n  0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,\n  0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,\n  0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,\n  0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,\n  0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,\n  0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,\n  0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,\n  0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,\n  0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,\n  0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,\n  0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,\n  0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,\n  0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,\n  0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,\n  0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,\n  0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,\n  0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,\n  0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,\n  0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,\n  0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,\n  0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,\n  0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,\n  0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,\n  0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,\n  0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,\n  0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,\n  0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,\n  0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,\n  0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,\n  0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,\n  0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,\n  0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,\n  0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,\n  0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,\n  0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,\n  0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,\n  0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,\n  0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,\n  0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,\n  0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,\n  0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,\n  0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,\n  0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,\n  0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,\n  0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,\n  0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,\n  0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,\n  0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,\n  0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,\n  0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,\n  0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,\n  0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,\n  0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,\n  0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,\n  0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,\n  0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,\n  0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,\n  0x634facda, 0xca9f750f, 0x63453125, 0xca988727,\n  0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,\n  0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,\n  0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,\n  0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,\n  0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,\n  0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,\n  0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,\n  0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,\n  0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,\n  0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,\n  0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,\n  0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,\n  0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,\n  0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,\n  0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,\n  0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,\n  0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,\n  0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,\n  0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,\n  0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,\n  0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,\n  0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,\n  0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,\n  0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,\n  0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,\n  0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,\n  0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,\n  0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,\n  0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,\n  0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,\n  0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,\n  0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,\n  0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,\n  0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,\n  0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,\n  0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,\n  0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,\n  0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,\n  0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,\n  0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,\n  0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,\n  0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,\n  0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,\n  0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,\n  0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,\n  0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,\n  0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,\n  0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,\n  0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,\n  0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,\n  0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,\n  0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,\n  0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,\n  0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,\n  0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,\n  0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,\n  0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,\n  0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,\n  0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,\n  0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,\n  0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,\n  0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,\n  0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,\n  0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,\n  0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,\n  0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,\n  0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,\n  0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,\n  0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,\n  0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,\n  0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,\n  0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,\n  0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,\n  0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,\n  0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,\n  0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,\n  0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,\n  0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,\n  0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,\n  0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,\n  0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,\n  0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,\n  0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,\n  0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,\n  0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,\n  0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,\n  0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,\n  0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,\n  0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,\n  0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,\n  0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,\n  0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,\n  0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,\n  0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,\n  0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,\n  0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,\n  0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,\n  0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,\n  0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,\n  0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,\n  0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,\n  0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,\n  0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,\n  0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,\n  0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,\n  0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,\n  0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,\n  0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,\n  0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,\n  0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,\n  0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,\n  0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,\n  0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,\n  0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,\n  0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,\n  0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,\n  0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,\n  0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,\n  0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,\n  0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,\n  0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,\n  0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,\n  0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,\n  0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,\n  0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,\n  0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,\n  0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,\n  0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,\n  0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,\n  0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,\n  0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,\n  0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,\n  0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,\n  0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,\n  0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,\n  0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,\n  0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,\n  0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,\n  0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,\n  0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,\n  0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,\n  0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,\n  0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,\n  0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,\n  0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,\n  0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,\n  0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,\n  0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,\n  0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,\n  0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,\n  0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,\n  0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,\n  0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,\n  0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,\n  0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,\n  0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,\n  0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,\n  0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,\n  0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,\n  0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,\n  0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,\n  0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,\n  0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,\n  0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,\n  0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,\n  0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,\n  0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,\n  0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,\n  0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,\n  0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,\n  0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,\n  0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,\n  0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,\n  0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,\n  0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,\n  0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,\n  0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,\n  0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,\n  0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,\n  0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,\n  0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,\n  0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,\n  0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,\n  0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,\n  0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,\n  0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,\n  0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,\n  0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,\n  0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,\n  0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,\n  0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,\n  0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,\n  0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,\n  0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,\n  0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,\n  0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,\n  0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,\n  0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,\n  0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,\n  0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,\n  0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,\n  0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,\n  0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,\n  0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,\n  0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,\n  0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,\n  0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,\n  0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,\n  0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,\n  0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,\n  0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,\n  0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,\n  0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,\n  0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,\n  0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,\n  0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,\n  0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,\n  0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,\n  0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,\n  0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,\n  0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,\n  0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,\n  0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,\n  0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,\n  0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,\n  0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,\n  0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,\n  0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,\n  0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,\n  0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,\n  0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,\n  0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,\n  0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,\n  0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,\n  0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,\n  0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,\n  0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,\n  0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,\n  0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,\n  0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,\n  0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,\n  0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,\n  0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,\n  0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,\n  0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,\n  0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,\n  0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,\n  0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,\n  0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,\n  0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,\n  0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,\n  0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,\n  0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,\n  0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,\n  0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,\n  0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,\n  0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,\n  0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,\n  0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,\n  0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,\n  0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,\n  0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,\n  0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,\n  0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,\n  0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,\n  0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,\n  0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,\n  0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,\n  0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,\n  0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,\n  0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,\n  0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,\n  0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,\n  0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,\n  0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,\n  0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,\n  0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,\n  0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,\n  0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,\n  0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,\n  0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,\n  0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,\n  0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,\n  0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,\n  0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,\n  0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,\n  0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,\n  0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,\n  0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,\n  0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,\n  0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,\n  0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,\n  0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,\n  0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,\n  0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,\n  0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,\n  0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,\n  0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,\n  0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,\n  0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,\n  0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,\n  0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,\n  0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,\n  0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,\n  0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,\n  0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,\n  0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,\n  0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,\n  0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,\n  0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,\n  0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,\n  0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,\n  0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,\n  0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,\n  0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,\n  0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,\n  0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,\n  0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,\n  0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,\n  0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,\n  0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,\n  0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,\n  0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,\n  0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,\n  0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,\n  0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,\n  0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,\n  0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,\n  0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,\n  0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,\n  0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,\n  0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,\n  0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,\n  0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,\n  0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,\n  0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,\n  0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,\n  0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,\n  0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,\n  0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,\n  0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,\n  0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,\n  0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,\n  0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,\n  0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,\n  0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,\n  0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,\n  0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,\n  0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,\n  0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,\n  0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,\n  0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,\n  0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,\n  0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,\n  0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,\n  0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,\n  0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,\n  0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,\n  0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,\n  0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,\n  0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,\n  0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,\n  0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,\n  0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,\n  0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,\n  0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,\n  0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,\n  0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,\n  0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,\n  0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,\n  0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,\n  0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,\n  0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,\n  0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,\n  0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,\n  0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,\n  0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,\n  0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,\n  0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,\n  0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,\n};\n\n/**    \n* @brief  Initialization function for the Q31 RFFT/RIFFT.   \n* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.   \n* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.   \n* @param[in]      fftLenReal     length of the FFT.   \n* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   \n* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   \n* @return\t\tThe function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   \n*    \n* \\par Description:   \n* \\par   \n* The parameter fftLenReal\tSpecifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    \n* \\par    \n* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    \n* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    \n* \\par    \n* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    \n* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   \n* \\par    \n* This function also initializes Twiddle factor table.    \n*/\n\narm_status arm_rfft_init_q31(\n  arm_rfft_instance_q31 * S,\n  arm_cfft_radix4_instance_q31 * S_CFFT,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag)\n{\n  /*  Initialise the default arm status */\n  arm_status status = ARM_MATH_SUCCESS;\n\n  /*  Initialize the Real FFT length */\n  S->fftLenReal = (uint16_t) fftLenReal;\n\n  /*  Initialize the Complex FFT length */\n  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;\n\n  /*  Initialize the Twiddle coefficientA pointer */\n  S->pTwiddleAReal = (q31_t *) realCoefAQ31;\n\n  /*  Initialize the Twiddle coefficientB pointer */\n  S->pTwiddleBReal = (q31_t *) realCoefBQ31;\n\n  /*  Initialize the Flag for selection of RFFT or RIFFT */\n  S->ifftFlagR = (uint8_t) ifftFlagR;\n\n  /*  Initialize the Flag for calculation Bit reversal or not */\n  S->bitReverseFlagR = (uint8_t) bitReverseFlag;\n\n  /*  Initialization of coef modifier depending on the FFT length */\n  switch (S->fftLenReal)\n  {\n  case 8192:\n    S->twidCoefRModifier = 1u;\n    break;\n  case 2048u:\n    S->twidCoefRModifier = 4u;\n    break;\n  case 512u:\n    S->twidCoefRModifier = 16u;\n    break;\n  case 128u:\n    S->twidCoefRModifier = 64u;\n    break;\n  default:\n    /*  Reporting argument error if rfftSize is not valid value */\n    status = ARM_MATH_ARGUMENT_ERROR;\n    break;\n  }\n\n  /* Init Complex FFT Instance */\n  S->pCfft = S_CFFT;\n\n  if(S->ifftFlagR)\n  {\n    /* Initializes the CIFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);\n  }\n  else\n  {\n    /* Initializes the CFFT Module for fftLenreal/2 length */\n    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);\n  }\n\n  /* return the status of RFFT Init function */\n  return (status);\n\n}\n\n  /**    \n   * @} end of RealFFT group    \n   */\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_q15.c    \n*    \n* Description:\tRFFT & RIFFT Q15 process function    \n*    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.     \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid arm_radix4_butterfly_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier);\n\nvoid arm_radix4_butterfly_inverse_q15(\n  q15_t * pSrc16,\n  uint32_t fftLen,\n  q15_t * pCoef16,\n  uint32_t twidCoefModifier);\n\nvoid arm_bitreversal_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  uint16_t bitRevFactor,\n  uint16_t * pBitRevTab);\n\t\n\t/*--------------------------------------------------------------------    \n*\t\tInternal functions prototypes    \n--------------------------------------------------------------------*/\n\nvoid arm_split_rfft_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pATable,\n  q15_t * pBTable,\n  q15_t * pDst,\n  uint32_t modifier);\n\nvoid arm_split_rifft_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pATable,\n  q15_t * pBTable,\n  q15_t * pDst,\n  uint32_t modifier);\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q15 RFFT/RIFFT.   \n * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.   \n * @param[in]  *pSrc points to the input buffer.   \n * @param[out] *pDst points to the output buffer.   \n * @return none.   \n *    \n * \\par Input an output formats:   \n * \\par    \n * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.    \n * Hence the output format is different for different RFFT sizes.    \n * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   \n * \\par    \n * \\image html RFFTQ15.gif \"Input and Output Formats for Q15 RFFT\"    \n * \\par    \n * \\image html RIFFTQ15.gif \"Input and Output Formats for Q15 RIFFT\"    \n */\n\nvoid arm_rfft_q15(\n  const arm_rfft_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst)\n{\n  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;\n\n  /* Calculation of RIFFT of input */\n  if(S->ifftFlagR == 1u)\n  {\n    /*  Real IFFT core process */\n    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n\n    /* Complex readix-4 IFFT process */\n    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,\n                                     S_CFFT->pTwiddle,\n                                     S_CFFT->twidCoefModifier);\n\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_q15(pDst, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n  }\n  else\n  {\n    /* Calculation of RFFT of input */\n\n    /* Complex readix-4 FFT process */\n    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,\n                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);\n\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n\n    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n  }\n\n}\n\n  /**    \n   * @} end of RealFFT group    \n   */\n\n/**    \n * @brief  Core Real FFT process    \n * @param  *pSrc \t\t\t\tpoints to the input buffer.   \n * @param  fftLen  \t\t\t\tlength of FFT.   \n * @param  *pATable \t\t\tpoints to the A twiddle Coef buffer.    \n * @param  *pBTable \t\t\tpoints to the B twiddle Coef buffer.   \n * @param  *pDst \t\t\t\tpoints to the output buffer.   \n * @param  modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.    \n * The function implements a Real FFT    \n */\n\nvoid arm_split_rfft_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pATable,\n  q15_t * pBTable,\n  q15_t * pDst,\n  uint32_t modifier)\n{\n  uint32_t i;                                    /* Loop Counter */\n  q31_t outR, outI;                              /* Temporary variables for output */\n  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */\n  q15_t *pSrc1, *pSrc2;\n\n\n//  pSrc[2u * fftLen] = pSrc[0]; \n//  pSrc[(2u * fftLen) + 1u] = pSrc[1]; \n\n  pCoefA = &pATable[modifier * 2u];\n  pCoefB = &pBTable[modifier * 2u];\n\n  pSrc1 = &pSrc[2];\n  pSrc2 = &pSrc[(2u * fftLen) - 2u];\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  i = 1u;\n\n  while(i < fftLen)\n  {\n    /*    \n       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    \n       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    \n       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n     */\n\n    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */\n\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */\n    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));\n\n#else\n\n    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */\n    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +    \n       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */\n    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;\n\n    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));\n\n#else\n\n    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */\n    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);\n\n    /* write output */\n    pDst[2u * i] = (q15_t) outR;\n    pDst[(2u * i) + 1u] = outI >> 15u;\n\n    /* write complex conjugate output */\n    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;\n    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (2u * modifier);\n    pCoefA = pCoefA + (2u * modifier);\n\n    i++;\n\n  }\n\n  pDst[2u * fftLen] = pSrc[0] - pSrc[1];\n  pDst[(2u * fftLen) + 1u] = 0;\n\n  pDst[0] = pSrc[0] + pSrc[1];\n  pDst[1] = 0;\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  i = 1u;\n\n  while(i < fftLen)\n  {\n    /*    \n       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    \n       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    \n       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n     */\n\n    outR = *pSrc1 * *pCoefA;\n    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));\n    outR = outR + (*pSrc2 * *pCoefB);\n    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;\n\n\n    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   \n     */\n\n    outI = *pSrc2 * *(pCoefB + 1);\n    outI = outI - (*(pSrc2 + 1) * *pCoefB);\n    outI = outI + (*(pSrc1 + 1) * *pCoefA);\n    outI = outI + (*pSrc1 * *(pCoefA + 1));\n\n    /* update input pointers */\n    pSrc1 += 2u;\n    pSrc2 -= 2u;\n\n    /* write output */\n    pDst[2u * i] = (q15_t) outR;\n    pDst[(2u * i) + 1u] = outI >> 15u;\n\n    /* write complex conjugate output */\n    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;\n    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (2u * modifier);\n    pCoefA = pCoefA + (2u * modifier);\n\n    i++;\n\n  }\n\n  pDst[2u * fftLen] = pSrc[0] - pSrc[1];\n  pDst[(2u * fftLen) + 1u] = 0;\n\n  pDst[0] = pSrc[0] + pSrc[1];\n  pDst[1] = 0;\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n\n\n/**    \n * @brief  Core Real IFFT process    \n * @param[in]   *pSrc \t\t\t\tpoints to the input buffer.    \n * @param[in]   fftLen  \t\t    length of FFT.   \n * @param[in]   *pATable \t\t\tpoints to the twiddle Coef A buffer.   \n * @param[in]   *pBTable \t\t\tpoints to the twiddle Coef B buffer.    \n * @param[out]  *pDst \t\t\t\tpoints to the output buffer.   \n * @param[in]   modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.    \n * The function implements a Real IFFT    \n */\nvoid arm_split_rifft_q15(\n  q15_t * pSrc,\n  uint32_t fftLen,\n  q15_t * pATable,\n  q15_t * pBTable,\n  q15_t * pDst,\n  uint32_t modifier)\n{\n  uint32_t i;                                    /* Loop Counter */\n  q31_t outR, outI;                              /* Temporary variables for output */\n  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */\n  q15_t *pSrc1, *pSrc2;\n  q15_t *pDst1 = &pDst[0];\n\n  pCoefA = &pATable[0];\n  pCoefB = &pBTable[0];\n\n  pSrc1 = &pSrc[0];\n  pSrc2 = &pSrc[2u * fftLen];\n\n#ifndef ARM_MATH_CM0_FAMILY\n\n  /* Run the below code for Cortex-M4 and Cortex-M3 */\n\n  i = fftLen;\n\n  while(i > 0u)\n  {\n\n    /*    \n       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n\n       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    \n\n     */\n\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */\n    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));\n\n#else\n\n    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +  \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */\n    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i] */\n    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;\n\n    /*    \n       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */\n    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));\n\n    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);\n\n#else\n\n    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n    /* write output */\n\n#ifndef ARM_MATH_BIG_ENDIAN\n\n    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);\n\n#else\n\n    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);\n\n#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (2u * modifier);\n    pCoefA = pCoefA + (2u * modifier);\n\n    i--;\n\n  }\n\n\n#else\n\n  /* Run the below code for Cortex-M0 */\n\n  i = fftLen;\n\n  while(i > 0u)\n  {\n\n    /*    \n       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n     */\n\n    outR = *pSrc2 * *pCoefB;\n    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));\n    outR = outR + (*pSrc1 * *pCoefA);\n    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;\n\n    /*   \n       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   \n     */\n\n    outI = *(pSrc1 + 1) * *pCoefA;\n    outI = outI - (*pSrc1 * *(pCoefA + 1));\n    outI = outI - (*pSrc2 * *(pCoefB + 1));\n    outI = outI - (*(pSrc2 + 1) * *(pCoefB));\n\n    /* update input pointers */\n    pSrc1 += 2u;\n    pSrc2 -= 2u;\n\n    /* write output */\n    *pDst1++ = (q15_t) outR;\n    *pDst1++ = (q15_t) (outI >> 15);\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (2u * modifier);\n    pCoefA = pCoefA + (2u * modifier);\n\n    i--;\n\n  }\n\n#endif /* #ifndef ARM_MATH_CM0_FAMILY */\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c",
    "content": "/* ----------------------------------------------------------------------    \n* Copyright (C) 2010-2013 ARM Limited. All rights reserved.    \n*    \n* $Date:        17. January 2013  \n* $Revision: \tV1.4.1  \n*    \n* Project: \t    CMSIS DSP Library    \n* Title:\t    arm_rfft_q31.c    \n*    \n* Description:\tRFFT & RIFFT Q31 process function    \n*    \n*    \n* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\n*  \n* Redistribution and use in source and binary forms, with or without \n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the \n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE \n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.    \n* -------------------------------------------------------------------- */\n\n#include \"arm_math.h\"\n\nvoid arm_radix4_butterfly_inverse_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint32_t twidCoefModifier);\n\nvoid arm_radix4_butterfly_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nq31_t * pCoef,\nuint32_t twidCoefModifier);\n\nvoid arm_bitreversal_q31(\nq31_t * pSrc,\nuint32_t fftLen,\nuint16_t bitRevFactor,\nuint16_t * pBitRevTab);\n\n/*--------------------------------------------------------------------    \n*\t\tInternal functions prototypes    \n--------------------------------------------------------------------*/\n\nvoid arm_split_rfft_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pATable,\n  q31_t * pBTable,\n  q31_t * pDst,\n  uint32_t modifier);\n\nvoid arm_split_rifft_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pATable,\n  q31_t * pBTable,\n  q31_t * pDst,\n  uint32_t modifier);\n\n/**    \n * @addtogroup RealFFT    \n * @{    \n */\n\n/**    \n * @brief Processing function for the Q31 RFFT/RIFFT.   \n * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.   \n * @param[in]  *pSrc points to the input buffer.   \n * @param[out] *pDst points to the output buffer.   \n * @return none.   \n *    \n * \\par Input an output formats:   \n * \\par    \n * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   \n * Hence the output format is different for different RFFT sizes.    \n * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   \n * \\par    \n * \\image html RFFTQ31.gif \"Input and Output Formats for Q31 RFFT\"    \n *    \n * \\par    \n * \\image html RIFFTQ31.gif \"Input and Output Formats for Q31 RIFFT\"    \n */\n\nvoid arm_rfft_q31(\n  const arm_rfft_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst)\n{\n  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;\n\n  /* Calculation of RIFFT of input */\n  if(S->ifftFlagR == 1u)\n  {\n    /*  Real IFFT core process */\n    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n\n    /* Complex readix-4 IFFT process */\n    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,\n                                     S_CFFT->pTwiddle,\n                                     S_CFFT->twidCoefModifier);\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_q31(pDst, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n  }\n  else\n  {\n    /* Calculation of RFFT of input */\n\n    /* Complex readix-4 FFT process */\n    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,\n                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);\n\n    /* Bit reversal process */\n    if(S->bitReverseFlagR == 1u)\n    {\n      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,\n                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);\n    }\n\n    /*  Real FFT core process */\n    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,\n                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);\n  }\n\n}\n\n\n  /**    \n   * @} end of RealFFT group    \n   */\n\n/**    \n * @brief  Core Real FFT process    \n * @param[in]   *pSrc \t\t\t\tpoints to the input buffer.    \n * @param[in]   fftLen  \t\t\tlength of FFT.   \n * @param[in]   *pATable \t\t\tpoints to the twiddle Coef A buffer.    \n * @param[in]   *pBTable \t\t\tpoints to the twiddle Coef B buffer.    \n * @param[out]  *pDst \t\t\t\tpoints to the output buffer.    \n * @param[in]   modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.    \n */\n\nvoid arm_split_rfft_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pATable,\n  q31_t * pBTable,\n  q31_t * pDst,\n  uint32_t modifier)\n{\n  uint32_t i;                                    /* Loop Counter */\n  q31_t outR, outI;                              /* Temporary variables for output */\n  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */\n  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */\n  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];\n  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];\n\n  /* Init coefficient pointers */\n  pCoefA = &pATable[modifier * 2u];\n  pCoefB = &pBTable[modifier * 2u];\n\n  i = fftLen - 1u;\n\n  while(i > 0u)\n  {\n    /*    \n       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    \n       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    \n       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n     */\n\n    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */\n\n    CoefA1 = *pCoefA++;\n    CoefA2 = *pCoefA;\n\n    /* outR = (pSrc[2 * i] * pATable[2 * i] */\n    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));\n\n    /* outI = pIn[2 * i] * pATable[2 * i + 1] */\n    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));\n\n    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);\n\n    /* (pIn[2 * i + 1] * pATable[2 * i] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);\n\n    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);\n    CoefB1 = *pCoefB;\n\n    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);\n\n    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);\n\n    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);\n\n    /* write output */\n    *pOut1++ = (outR << 1u);\n    *pOut1++ = (outI << 1u);\n\n    /* write complex conjugate output */\n    *pOut2-- = -(outI << 1u);\n    *pOut2-- = (outR << 1u);\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (modifier * 2u);\n    pCoefA = pCoefA + ((modifier * 2u) - 1u);\n\n    i--;\n\n  }\n\n  pDst[2u * fftLen] = pSrc[0] - pSrc[1];\n  pDst[(2u * fftLen) + 1u] = 0;\n\n  pDst[0] = pSrc[0] + pSrc[1];\n  pDst[1] = 0;\n\n}\n\n\n/**    \n * @brief  Core Real IFFT process    \n * @param[in]   *pSrc \t\t\t\tpoints to the input buffer.   \n * @param[in]   fftLen  \t\t\tlength of FFT.    \n * @param[in]   *pATable \t\t\tpoints to the twiddle Coef A buffer.   \n * @param[in]   *pBTable \t\t\tpoints to the twiddle Coef B buffer.    \n * @param[out]  *pDst \t\t\t\tpoints to the output buffer.   \n * @param[in]   modifier \t        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   \n * @return none.    \n */\n\nvoid arm_split_rifft_q31(\n  q31_t * pSrc,\n  uint32_t fftLen,\n  q31_t * pATable,\n  q31_t * pBTable,\n  q31_t * pDst,\n  uint32_t modifier)\n{\n  q31_t outR, outI;                              /* Temporary variables for output */\n  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */\n  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */\n  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];\n\n  pCoefA = &pATable[0];\n  pCoefB = &pBTable[0];\n\n  while(fftLen > 0u)\n  {\n    /*    \n       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    \n       pIn[2 * n - 2 * i] * pBTable[2 * i] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    \n\n       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    \n       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    \n       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    \n\n     */\n    CoefA1 = *pCoefA++;\n    CoefA2 = *pCoefA;\n\n    /* outR = (pIn[2 * i] * pATable[2 * i] */\n    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));\n\n    /* - pIn[2 * i] * pATable[2 * i + 1] */\n    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));\n\n    /* pIn[2 * i + 1] * pATable[2 * i + 1] */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);\n\n    /* pIn[2 * i + 1] * pATable[2 * i] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);\n\n    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);\n\n    CoefB1 = *pCoefB;\n\n    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);\n\n    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */\n    outR =\n      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);\n\n    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */\n    outI =\n      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);\n\n    /* write output */\n    *pDst++ = (outR << 1u);\n    *pDst++ = (outI << 1u);\n\n    /* update coefficient pointer */\n    pCoefB = pCoefB + (modifier * 2u);\n    pCoefA = pCoefA + ((modifier * 2u) - 1u);\n\n    /* Decrement loop count */\n    fftLen--;\n\n  }\n\n\n}\n"
  },
  {
    "path": "Libraries/CMSIS/DSP_Lib/license.txt",
    "content": "All files contained in the folders \"CMSIS\\DSP-Lib\\Source\" and \"CMSIS\\DSP-Lib\\Examples\"\nare guided by the following license:\n\nCopyright (C) 2009-2012 ARM Limited. \nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n - Redistributions of source code must retain the above copyright\n   notice, this list of conditions and the following disclaimer.\n - Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n - Neither the name of ARM nor the names of its contributors may be used \n   to endorse or promote products derived from this software without \n   specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "Libraries/CMSIS/Device/ST/STM32F10x/Include/stm32f10x.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f10x.h\n  * @author  MCD Application Team\n  * @version V3.6.1\n  * @date    09-March-2012\n  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \n  *          This file contains all the peripheral register's definitions, bits \n  *          definitions and memory mapping for STM32F10x Connectivity line, \n  *          High density, High density value line, Medium density, \n  *          Medium density Value line, Low density, Low density Value line \n  *          and XL-density devices.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e. \n  *                code will be based on direct access to peripherals registers \n  *                rather than drivers API), this option is controlled by \n  *                \"#define USE_STDPERIPH_DRIVER\"\n  *              - To change few application-specific parameters such as the HSE \n  *                crystal frequency\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripherals registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * 
© COPYRIGHT 2012 STMicroelectronics
\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f10x\n  * @{\n  */\n    \n#ifndef __STM32F10x_H\n#define __STM32F10x_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n  \n/** @addtogroup Library_configuration_section\n  * @{\n  */\n  \n/* Uncomment the line below according to the target STM32 device used in your\n   application \n  */\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) \n  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */\n  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  \n  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */\n  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  \n  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices */\n  /* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  \n  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */\n  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */\n#endif\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n\n - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\n   where the Flash memory density ranges between 16 and 32 Kbytes.\n - Low-density value line devices are STM32F100xx microcontrollers where the Flash\n   memory density ranges between 16 and 32 Kbytes.\n - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\n   where the Flash memory density ranges between 64 and 128 Kbytes.\n - Medium-density value line devices are STM32F100xx microcontrollers where the \n   Flash memory density ranges between 64 and 128 Kbytes.   \n - High-density devices are STM32F101xx and STM32F103xx microcontrollers where\n   the Flash memory density ranges between 256 and 512 Kbytes.\n - High-density value line devices are STM32F100xx microcontrollers where the \n   Flash memory density ranges between 256 and 512 Kbytes.   \n - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where\n   the Flash memory density ranges between 512 and 1024 Kbytes.\n - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\n  */\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)\n #error \"Please select first the target STM32F10x device used in your application (in stm32f10x.h file)\"\n#endif\n\n#if !defined  (USE_STDPERIPH_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will \n   be based on direct access to peripherals registers \n   */\n  /*#define USE_STDPERIPH_DRIVER*/\n#endif /* USE_STDPERIPH_DRIVER */\n\n/**\n * @brief In the following line adjust the value of External High Speed oscillator (HSE)\n   used in your application \n   \n   Tip: To avoid modifying this file each time you need to use different HSE, you\n        can define the HSE value in your toolchain compiler preprocessor.\n  */           \n#if !defined  HSE_VALUE\n #ifdef STM32F10X_CL   \n  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\n #else \n  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\n #endif /* STM32F10X_CL */\n#endif /* HSE_VALUE */\n\n/**\n * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \n   Timeout value \n   */\n#if !defined  (HSE_STARTUP_TIMEOUT) \n  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0500)   /*!< Time out for HSE start up */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n#if !defined  (HSI_VALUE)   \n  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n * @brief STM32F10x Standard Peripheral Library version number\n   */\n#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */\n#define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x06) /*!< [23:16] sub1 version */\n#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */\n#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\n#define __STM32F10X_STDPERIPH_VERSION        ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\\\n                                             |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\\\n                                             |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\\\n                                             |(__STM32F10X_STDPERIPH_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \n */\n#ifdef STM32F10X_XL\n #define __MPU_PRESENT             1      /*!< STM32 XL-density devices provide an MPU      */\n#else\n #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */\n#endif /* STM32F10X_XL */\n#define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */\n#define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */\n\n/**\n * @brief STM32F10x Interrupt Number Definition, according to the selected device \n *        in @ref Library_configuration_section \n */\ntypedef enum IRQn\n{\n/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */\n\n/******  STM32 specific Interrupt Numbers *********************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */\n  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */\n  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */\n  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */\n  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */\n  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */\n  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */\n  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */\n  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */\n  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */\n\n#ifdef STM32F10X_LD\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */    \n#endif /* STM32F10X_LD */  \n\n#ifdef STM32F10X_LD_VL\n  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */\n  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */\n  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */\n  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       \n#endif /* STM32F10X_LD_VL */\n\n#ifdef STM32F10X_MD\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  USBWakeUp_IRQn              = 42      /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */  \n#endif /* STM32F10X_MD */  \n\n#ifdef STM32F10X_MD_VL\n  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */\n  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */\n  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */\n  TIM7_IRQn                   = 55      /*!< TIM7 Interrupt                                       */       \n#endif /* STM32F10X_MD_VL */\n\n#ifdef STM32F10X_HD\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\n  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */\n  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */\n  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */\n  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */\n  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */\n  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */\n  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */\n  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */\n  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */\n#endif /* STM32F10X_HD */  \n\n#ifdef STM32F10X_HD_VL\n  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */\n  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */\n  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */\n  TIM12_IRQn                  = 43,     /*!< TIM12 global Interrupt                               */\n  TIM13_IRQn                  = 44,     /*!< TIM13 global Interrupt                               */\n  TIM14_IRQn                  = 45,     /*!< TIM14 global Interrupt                               */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */  \n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */\n  TIM7_IRQn                   = 55,     /*!< TIM7 Interrupt                                       */  \n  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */\n  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */\n  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */\n  DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */\n  DMA2_Channel5_IRQn          = 60      /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is \n                                             mapped at position 60 only if the MISC_REMAP bit in \n                                             the AFIO_MAPR2 register is set)                      */       \n#endif /* STM32F10X_HD_VL */\n\n#ifdef STM32F10X_XL\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */\n  ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */\n  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */\n  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */\n  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */\n  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */\n  DMA2_Channel4_5_IRQn        = 59      /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */\n#endif /* STM32F10X_XL */  \n\n#ifdef STM32F10X_CL\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  CAN1_TX_IRQn                = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  CAN1_RX0_IRQn               = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */\n  TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */\n  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */\n  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */\n  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */\n  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                      */\n  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                      */\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                            */\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt          */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                    */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                   */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                   */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                   */\n  OTG_FS_IRQn                 = 67      /*!< USB OTG FS global Interrupt                          */\n#endif /* STM32F10X_CL */     \n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm3.h\"\n#include \"system_stm32f10x.h\"\n#include \n\n/** @addtogroup Exported_types\n  * @{\n  */  \n\n/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\ntypedef int32_t  s32;\ntypedef int16_t s16;\ntypedef int8_t  s8;\n\ntypedef const int32_t sc32;  /*!< Read Only */\ntypedef const int16_t sc16;  /*!< Read Only */\ntypedef const int8_t sc8;   /*!< Read Only */\n\ntypedef __IO int32_t  vs32;\ntypedef __IO int16_t  vs16;\ntypedef __IO int8_t   vs8;\n\ntypedef __I int32_t vsc32;  /*!< Read Only */\ntypedef __I int16_t vsc16;  /*!< Read Only */\ntypedef __I int8_t vsc8;   /*!< Read Only */\n\ntypedef uint32_t  u32;\ntypedef uint16_t u16;\ntypedef uint8_t  u8;\n\ntypedef const uint32_t uc32;  /*!< Read Only */\ntypedef const uint16_t uc16;  /*!< Read Only */\ntypedef const uint8_t uc8;   /*!< Read Only */\n\ntypedef __IO uint32_t  vu32;\ntypedef __IO uint16_t vu16;\ntypedef __IO uint8_t  vu8;\n\ntypedef __I uint32_t vuc32;  /*!< Read Only */\ntypedef __I uint16_t vuc16;  /*!< Read Only */\ntypedef __I uint8_t vuc8;   /*!< Read Only */\n\ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\n\ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\n\n/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */\n#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT\n#define HSE_Value            HSE_VALUE\n#define HSI_Value            HSI_VALUE\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */   \n\n/** \n  * @brief Analog to Digital Converter  \n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;\n  __IO uint32_t CR1;\n  __IO uint32_t CR2;\n  __IO uint32_t SMPR1;\n  __IO uint32_t SMPR2;\n  __IO uint32_t JOFR1;\n  __IO uint32_t JOFR2;\n  __IO uint32_t JOFR3;\n  __IO uint32_t JOFR4;\n  __IO uint32_t HTR;\n  __IO uint32_t LTR;\n  __IO uint32_t SQR1;\n  __IO uint32_t SQR2;\n  __IO uint32_t SQR3;\n  __IO uint32_t JSQR;\n  __IO uint32_t JDR1;\n  __IO uint32_t JDR2;\n  __IO uint32_t JDR3;\n  __IO uint32_t JDR4;\n  __IO uint32_t DR;\n} ADC_TypeDef;\n\n/** \n  * @brief Backup Registers  \n  */\n\ntypedef struct\n{\n  uint32_t  RESERVED0;\n  __IO uint16_t DR1;\n  uint16_t  RESERVED1;\n  __IO uint16_t DR2;\n  uint16_t  RESERVED2;\n  __IO uint16_t DR3;\n  uint16_t  RESERVED3;\n  __IO uint16_t DR4;\n  uint16_t  RESERVED4;\n  __IO uint16_t DR5;\n  uint16_t  RESERVED5;\n  __IO uint16_t DR6;\n  uint16_t  RESERVED6;\n  __IO uint16_t DR7;\n  uint16_t  RESERVED7;\n  __IO uint16_t DR8;\n  uint16_t  RESERVED8;\n  __IO uint16_t DR9;\n  uint16_t  RESERVED9;\n  __IO uint16_t DR10;\n  uint16_t  RESERVED10; \n  __IO uint16_t RTCCR;\n  uint16_t  RESERVED11;\n  __IO uint16_t CR;\n  uint16_t  RESERVED12;\n  __IO uint16_t CSR;\n  uint16_t  RESERVED13[5];\n  __IO uint16_t DR11;\n  uint16_t  RESERVED14;\n  __IO uint16_t DR12;\n  uint16_t  RESERVED15;\n  __IO uint16_t DR13;\n  uint16_t  RESERVED16;\n  __IO uint16_t DR14;\n  uint16_t  RESERVED17;\n  __IO uint16_t DR15;\n  uint16_t  RESERVED18;\n  __IO uint16_t DR16;\n  uint16_t  RESERVED19;\n  __IO uint16_t DR17;\n  uint16_t  RESERVED20;\n  __IO uint16_t DR18;\n  uint16_t  RESERVED21;\n  __IO uint16_t DR19;\n  uint16_t  RESERVED22;\n  __IO uint16_t DR20;\n  uint16_t  RESERVED23;\n  __IO uint16_t DR21;\n  uint16_t  RESERVED24;\n  __IO uint16_t DR22;\n  uint16_t  RESERVED25;\n  __IO uint16_t DR23;\n  uint16_t  RESERVED26;\n  __IO uint16_t DR24;\n  uint16_t  RESERVED27;\n  __IO uint16_t DR25;\n  uint16_t  RESERVED28;\n  __IO uint16_t DR26;\n  uint16_t  RESERVED29;\n  __IO uint16_t DR27;\n  uint16_t  RESERVED30;\n  __IO uint16_t DR28;\n  uint16_t  RESERVED31;\n  __IO uint16_t DR29;\n  uint16_t  RESERVED32;\n  __IO uint16_t DR30;\n  uint16_t  RESERVED33; \n  __IO uint16_t DR31;\n  uint16_t  RESERVED34;\n  __IO uint16_t DR32;\n  uint16_t  RESERVED35;\n  __IO uint16_t DR33;\n  uint16_t  RESERVED36;\n  __IO uint16_t DR34;\n  uint16_t  RESERVED37;\n  __IO uint16_t DR35;\n  uint16_t  RESERVED38;\n  __IO uint16_t DR36;\n  uint16_t  RESERVED39;\n  __IO uint16_t DR37;\n  uint16_t  RESERVED40;\n  __IO uint16_t DR38;\n  uint16_t  RESERVED41;\n  __IO uint16_t DR39;\n  uint16_t  RESERVED42;\n  __IO uint16_t DR40;\n  uint16_t  RESERVED43;\n  __IO uint16_t DR41;\n  uint16_t  RESERVED44;\n  __IO uint16_t DR42;\n  uint16_t  RESERVED45;    \n} BKP_TypeDef;\n  \n/** \n  * @brief Controller Area Network TxMailBox \n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;\n  __IO uint32_t TDTR;\n  __IO uint32_t TDLR;\n  __IO uint32_t TDHR;\n} CAN_TxMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FIFOMailBox \n  */\n  \ntypedef struct\n{\n  __IO uint32_t RIR;\n  __IO uint32_t RDTR;\n  __IO uint32_t RDLR;\n  __IO uint32_t RDHR;\n} CAN_FIFOMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FilterRegister \n  */\n  \ntypedef struct\n{\n  __IO uint32_t FR1;\n  __IO uint32_t FR2;\n} CAN_FilterRegister_TypeDef;\n\n/** \n  * @brief Controller Area Network \n  */\n  \ntypedef struct\n{\n  __IO uint32_t MCR;\n  __IO uint32_t MSR;\n  __IO uint32_t TSR;\n  __IO uint32_t RF0R;\n  __IO uint32_t RF1R;\n  __IO uint32_t IER;\n  __IO uint32_t ESR;\n  __IO uint32_t BTR;\n  uint32_t  RESERVED0[88];\n  CAN_TxMailBox_TypeDef sTxMailBox[3];\n  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\n  uint32_t  RESERVED1[12];\n  __IO uint32_t FMR;\n  __IO uint32_t FM1R;\n  uint32_t  RESERVED2;\n  __IO uint32_t FS1R;\n  uint32_t  RESERVED3;\n  __IO uint32_t FFA1R;\n  uint32_t  RESERVED4;\n  __IO uint32_t FA1R;\n  uint32_t  RESERVED5[8];\n#ifndef STM32F10X_CL\n  CAN_FilterRegister_TypeDef sFilterRegister[14];\n#else\n  CAN_FilterRegister_TypeDef sFilterRegister[28];\n#endif /* STM32F10X_CL */  \n} CAN_TypeDef;\n\n/** \n  * @brief Consumer Electronics Control (CEC)\n  */\ntypedef struct\n{\n  __IO uint32_t CFGR;\n  __IO uint32_t OAR;\n  __IO uint32_t PRES;\n  __IO uint32_t ESR;\n  __IO uint32_t CSR;\n  __IO uint32_t TXD;\n  __IO uint32_t RXD;  \n} CEC_TypeDef;\n\n/** \n  * @brief CRC calculation unit \n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;\n  __IO uint8_t  IDR;\n  uint8_t   RESERVED0;\n  uint16_t  RESERVED1;\n  __IO uint32_t CR;\n} CRC_TypeDef;\n\n/** \n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t SWTRIGR;\n  __IO uint32_t DHR12R1;\n  __IO uint32_t DHR12L1;\n  __IO uint32_t DHR8R1;\n  __IO uint32_t DHR12R2;\n  __IO uint32_t DHR12L2;\n  __IO uint32_t DHR8R2;\n  __IO uint32_t DHR12RD;\n  __IO uint32_t DHR12LD;\n  __IO uint32_t DHR8RD;\n  __IO uint32_t DOR1;\n  __IO uint32_t DOR2;\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n  __IO uint32_t SR;\n#endif\n} DAC_TypeDef;\n\n/** \n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;\n  __IO uint32_t CR;\t\n}DBGMCU_TypeDef;\n\n/** \n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CCR;\n  __IO uint32_t CNDTR;\n  __IO uint32_t CPAR;\n  __IO uint32_t CMAR;\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;\n  __IO uint32_t IFCR;\n} DMA_TypeDef;\n\n/** \n  * @brief Ethernet MAC\n  */\n\ntypedef struct\n{\n  __IO uint32_t MACCR;\n  __IO uint32_t MACFFR;\n  __IO uint32_t MACHTHR;\n  __IO uint32_t MACHTLR;\n  __IO uint32_t MACMIIAR;\n  __IO uint32_t MACMIIDR;\n  __IO uint32_t MACFCR;\n  __IO uint32_t MACVLANTR;             /*    8 */\n       uint32_t RESERVED0[2];\n  __IO uint32_t MACRWUFFR;             /*   11 */\n  __IO uint32_t MACPMTCSR;\n       uint32_t RESERVED1[2];\n  __IO uint32_t MACSR;                 /*   15 */\n  __IO uint32_t MACIMR;\n  __IO uint32_t MACA0HR;\n  __IO uint32_t MACA0LR;\n  __IO uint32_t MACA1HR;\n  __IO uint32_t MACA1LR;\n  __IO uint32_t MACA2HR;\n  __IO uint32_t MACA2LR;\n  __IO uint32_t MACA3HR;\n  __IO uint32_t MACA3LR;               /*   24 */\n       uint32_t RESERVED2[40];\n  __IO uint32_t MMCCR;                 /*   65 */\n  __IO uint32_t MMCRIR;\n  __IO uint32_t MMCTIR;\n  __IO uint32_t MMCRIMR;\n  __IO uint32_t MMCTIMR;               /*   69 */\n       uint32_t RESERVED3[14];\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\n  __IO uint32_t MMCTGFMSCCR;\n       uint32_t RESERVED4[5];\n  __IO uint32_t MMCTGFCR;\n       uint32_t RESERVED5[10];\n  __IO uint32_t MMCRFCECR;\n  __IO uint32_t MMCRFAECR;\n       uint32_t RESERVED6[10];\n  __IO uint32_t MMCRGUFCR;\n       uint32_t RESERVED7[334];\n  __IO uint32_t PTPTSCR;\n  __IO uint32_t PTPSSIR;\n  __IO uint32_t PTPTSHR;\n  __IO uint32_t PTPTSLR;\n  __IO uint32_t PTPTSHUR;\n  __IO uint32_t PTPTSLUR;\n  __IO uint32_t PTPTSAR;\n  __IO uint32_t PTPTTHR;\n  __IO uint32_t PTPTTLR;\n       uint32_t RESERVED8[567];\n  __IO uint32_t DMABMR;\n  __IO uint32_t DMATPDR;\n  __IO uint32_t DMARPDR;\n  __IO uint32_t DMARDLAR;\n  __IO uint32_t DMATDLAR;\n  __IO uint32_t DMASR;\n  __IO uint32_t DMAOMR;\n  __IO uint32_t DMAIER;\n  __IO uint32_t DMAMFBOCR;\n       uint32_t RESERVED9[9];\n  __IO uint32_t DMACHTDR;\n  __IO uint32_t DMACHRDR;\n  __IO uint32_t DMACHTBAR;\n  __IO uint32_t DMACHRBAR;\n} ETH_TypeDef;\n\n/** \n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;\n  __IO uint32_t EMR;\n  __IO uint32_t RTSR;\n  __IO uint32_t FTSR;\n  __IO uint32_t SWIER;\n  __IO uint32_t PR;\n} EXTI_TypeDef;\n\n/** \n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;\n  __IO uint32_t KEYR;\n  __IO uint32_t OPTKEYR;\n  __IO uint32_t SR;\n  __IO uint32_t CR;\n  __IO uint32_t AR;\n  __IO uint32_t RESERVED;\n  __IO uint32_t OBR;\n  __IO uint32_t WRPR;\n#ifdef STM32F10X_XL\n  uint32_t RESERVED1[8]; \n  __IO uint32_t KEYR2;\n  uint32_t RESERVED2;   \n  __IO uint32_t SR2;\n  __IO uint32_t CR2;\n  __IO uint32_t AR2; \n#endif /* STM32F10X_XL */  \n} FLASH_TypeDef;\n\n/** \n  * @brief Option Bytes Registers\n  */\n  \ntypedef struct\n{\n  __IO uint16_t RDP;\n  __IO uint16_t USER;\n  __IO uint16_t Data0;\n  __IO uint16_t Data1;\n  __IO uint16_t WRP0;\n  __IO uint16_t WRP1;\n  __IO uint16_t WRP2;\n  __IO uint16_t WRP3;\n} OB_TypeDef;\n\n/** \n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];   \n} FSMC_Bank1_TypeDef; \n\n/** \n  * @brief Flexible Static Memory Controller Bank1E\n  */\n  \ntypedef struct\n{\n  __IO uint32_t BWTR[7];\n} FSMC_Bank1E_TypeDef;\n\n/** \n  * @brief Flexible Static Memory Controller Bank2\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR2;\n  __IO uint32_t SR2;\n  __IO uint32_t PMEM2;\n  __IO uint32_t PATT2;\n  uint32_t  RESERVED0;   \n  __IO uint32_t ECCR2; \n} FSMC_Bank2_TypeDef;  \n\n/** \n  * @brief Flexible Static Memory Controller Bank3\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR3;\n  __IO uint32_t SR3;\n  __IO uint32_t PMEM3;\n  __IO uint32_t PATT3;\n  uint32_t  RESERVED0;   \n  __IO uint32_t ECCR3; \n} FSMC_Bank3_TypeDef; \n\n/** \n  * @brief Flexible Static Memory Controller Bank4\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR4;\n  __IO uint32_t SR4;\n  __IO uint32_t PMEM4;\n  __IO uint32_t PATT4;\n  __IO uint32_t PIO4; \n} FSMC_Bank4_TypeDef; \n\n/** \n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t CRL;\n  __IO uint32_t CRH;\n  __IO uint32_t IDR;\n  __IO uint32_t ODR;\n  __IO uint32_t BSRR;\n  __IO uint32_t BRR;\n  __IO uint32_t LCKR;\n} GPIO_TypeDef;\n\n/** \n  * @brief Alternate Function I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t EVCR;\n  __IO uint32_t MAPR;\n  __IO uint32_t EXTICR[4];\n  uint32_t RESERVED0;\n  __IO uint32_t MAPR2;  \n} AFIO_TypeDef;\n/** \n  * @brief Inter Integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint16_t CR1;\n  uint16_t  RESERVED0;\n  __IO uint16_t CR2;\n  uint16_t  RESERVED1;\n  __IO uint16_t OAR1;\n  uint16_t  RESERVED2;\n  __IO uint16_t OAR2;\n  uint16_t  RESERVED3;\n  __IO uint16_t DR;\n  uint16_t  RESERVED4;\n  __IO uint16_t SR1;\n  uint16_t  RESERVED5;\n  __IO uint16_t SR2;\n  uint16_t  RESERVED6;\n  __IO uint16_t CCR;\n  uint16_t  RESERVED7;\n  __IO uint16_t TRISE;\n  uint16_t  RESERVED8;\n} I2C_TypeDef;\n\n/** \n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;\n  __IO uint32_t PR;\n  __IO uint32_t RLR;\n  __IO uint32_t SR;\n} IWDG_TypeDef;\n\n/** \n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t CSR;\n} PWR_TypeDef;\n\n/** \n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t CFGR;\n  __IO uint32_t CIR;\n  __IO uint32_t APB2RSTR;\n  __IO uint32_t APB1RSTR;\n  __IO uint32_t AHBENR;\n  __IO uint32_t APB2ENR;\n  __IO uint32_t APB1ENR;\n  __IO uint32_t BDCR;\n  __IO uint32_t CSR;\n\n#ifdef STM32F10X_CL  \n  __IO uint32_t AHBRSTR;\n  __IO uint32_t CFGR2;\n#endif /* STM32F10X_CL */ \n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   \n  uint32_t RESERVED0;\n  __IO uint32_t CFGR2;\n#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ \n} RCC_TypeDef;\n\n/** \n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint16_t CRH;\n  uint16_t  RESERVED0;\n  __IO uint16_t CRL;\n  uint16_t  RESERVED1;\n  __IO uint16_t PRLH;\n  uint16_t  RESERVED2;\n  __IO uint16_t PRLL;\n  uint16_t  RESERVED3;\n  __IO uint16_t DIVH;\n  uint16_t  RESERVED4;\n  __IO uint16_t DIVL;\n  uint16_t  RESERVED5;\n  __IO uint16_t CNTH;\n  uint16_t  RESERVED6;\n  __IO uint16_t CNTL;\n  uint16_t  RESERVED7;\n  __IO uint16_t ALRH;\n  uint16_t  RESERVED8;\n  __IO uint16_t ALRL;\n  uint16_t  RESERVED9;\n} RTC_TypeDef;\n\n/** \n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;\n  __IO uint32_t CLKCR;\n  __IO uint32_t ARG;\n  __IO uint32_t CMD;\n  __I uint32_t RESPCMD;\n  __I uint32_t RESP1;\n  __I uint32_t RESP2;\n  __I uint32_t RESP3;\n  __I uint32_t RESP4;\n  __IO uint32_t DTIMER;\n  __IO uint32_t DLEN;\n  __IO uint32_t DCTRL;\n  __I uint32_t DCOUNT;\n  __I uint32_t STA;\n  __IO uint32_t ICR;\n  __IO uint32_t MASK;\n  uint32_t  RESERVED0[2];\n  __I uint32_t FIFOCNT;\n  uint32_t  RESERVED1[13];\n  __IO uint32_t FIFO;\n} SDIO_TypeDef;\n\n/** \n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint16_t CR1;\n  uint16_t  RESERVED0;\n  __IO uint16_t CR2;\n  uint16_t  RESERVED1;\n  __IO uint16_t SR;\n  uint16_t  RESERVED2;\n  __IO uint16_t DR;\n  uint16_t  RESERVED3;\n  __IO uint16_t CRCPR;\n  uint16_t  RESERVED4;\n  __IO uint16_t RXCRCR;\n  uint16_t  RESERVED5;\n  __IO uint16_t TXCRCR;\n  uint16_t  RESERVED6;\n  __IO uint16_t I2SCFGR;\n  uint16_t  RESERVED7;\n  __IO uint16_t I2SPR;\n  uint16_t  RESERVED8;  \n} SPI_TypeDef;\n\n/** \n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint16_t CR1;\n  uint16_t  RESERVED0;\n  __IO uint16_t CR2;\n  uint16_t  RESERVED1;\n  __IO uint16_t SMCR;\n  uint16_t  RESERVED2;\n  __IO uint16_t DIER;\n  uint16_t  RESERVED3;\n  __IO uint16_t SR;\n  uint16_t  RESERVED4;\n  __IO uint16_t EGR;\n  uint16_t  RESERVED5;\n  __IO uint16_t CCMR1;\n  uint16_t  RESERVED6;\n  __IO uint16_t CCMR2;\n  uint16_t  RESERVED7;\n  __IO uint16_t CCER;\n  uint16_t  RESERVED8;\n  __IO uint16_t CNT;\n  uint16_t  RESERVED9;\n  __IO uint16_t PSC;\n  uint16_t  RESERVED10;\n  __IO uint16_t ARR;\n  uint16_t  RESERVED11;\n  __IO uint16_t RCR;\n  uint16_t  RESERVED12;\n  __IO uint16_t CCR1;\n  uint16_t  RESERVED13;\n  __IO uint16_t CCR2;\n  uint16_t  RESERVED14;\n  __IO uint16_t CCR3;\n  uint16_t  RESERVED15;\n  __IO uint16_t CCR4;\n  uint16_t  RESERVED16;\n  __IO uint16_t BDTR;\n  uint16_t  RESERVED17;\n  __IO uint16_t DCR;\n  uint16_t  RESERVED18;\n  __IO uint16_t DMAR;\n  uint16_t  RESERVED19;\n} TIM_TypeDef;\n\n/** \n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n \ntypedef struct\n{\n  __IO uint16_t SR;\n  uint16_t  RESERVED0;\n  __IO uint16_t DR;\n  uint16_t  RESERVED1;\n  __IO uint16_t BRR;\n  uint16_t  RESERVED2;\n  __IO uint16_t CR1;\n  uint16_t  RESERVED3;\n  __IO uint16_t CR2;\n  uint16_t  RESERVED4;\n  __IO uint16_t CR3;\n  uint16_t  RESERVED5;\n  __IO uint16_t GTPR;\n  uint16_t  RESERVED6;\n} USART_TypeDef;\n\n/** \n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t CFR;\n  __IO uint32_t SR;\n} WWDG_TypeDef;\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n\n\n#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\n#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\n#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\n\n#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\n#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\n\n#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)\n#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)\n\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)\n#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)\n#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)\n\n#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)\n#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)\n#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)\n#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)\n#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)\n#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)\n#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)\n#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)\n#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)\n#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)\n#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)\n\n#define SDIO_BASE             (PERIPH_BASE + 0x18000)\n\n#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)\n#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)\n#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)\n#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)\n#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)\n#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)\n#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)\n#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)\n#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)\n#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)\n#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)\n#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)\n#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)\n#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)\n#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)\n#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)\n\n#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */\n#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */\n\n#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)\n#define ETH_MAC_BASE          (ETH_BASE)\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100)\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700)\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000)\n\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */\n#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */\n#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */\n#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */\n\n#define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_declaration\n  * @{\n  */  \n\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define BKP                 ((BKP_TypeDef *) BKP_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE)\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\n#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\n#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\n#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\n#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\n#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\n#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define OB                  ((OB_TypeDef *) OB_BASE) \n#define ETH                 ((ETH_TypeDef *) ETH_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\n#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\n#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n  \n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n    \n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for CRC_DR register  *********************/\n#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for PWR_CR register  ********************/\n#define  PWR_CR_LPDS                         ((uint16_t)0x0001)     /*!< Low-Power Deepsleep */\n#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */\n#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */\n#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */\n#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */\n\n#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */\n#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */\n#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */\n#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */\n\n/*!< PVD level configuration */\n#define  PWR_CR_PLS_2V2                      ((uint16_t)0x0000)     /*!< PVD level 2.2V */\n#define  PWR_CR_PLS_2V3                      ((uint16_t)0x0020)     /*!< PVD level 2.3V */\n#define  PWR_CR_PLS_2V4                      ((uint16_t)0x0040)     /*!< PVD level 2.4V */\n#define  PWR_CR_PLS_2V5                      ((uint16_t)0x0060)     /*!< PVD level 2.5V */\n#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0080)     /*!< PVD level 2.6V */\n#define  PWR_CR_PLS_2V7                      ((uint16_t)0x00A0)     /*!< PVD level 2.7V */\n#define  PWR_CR_PLS_2V8                      ((uint16_t)0x00C0)     /*!< PVD level 2.8V */\n#define  PWR_CR_PLS_2V9                      ((uint16_t)0x00E0)     /*!< PVD level 2.9V */\n\n#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */\n#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */\n#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */\n#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Backup registers                                */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for BKP_DR1 register  ********************/\n#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR2 register  ********************/\n#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR3 register  ********************/\n#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR4 register  ********************/\n#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR5 register  ********************/\n#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR6 register  ********************/\n#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR7 register  ********************/\n#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR8 register  ********************/\n#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR9 register  ********************/\n#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR10 register  *******************/\n#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR11 register  *******************/\n#define  BKP_DR11_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR12 register  *******************/\n#define  BKP_DR12_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR13 register  *******************/\n#define  BKP_DR13_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR14 register  *******************/\n#define  BKP_DR14_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR15 register  *******************/\n#define  BKP_DR15_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR16 register  *******************/\n#define  BKP_DR16_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR17 register  *******************/\n#define  BKP_DR17_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/******************  Bit definition for BKP_DR18 register  ********************/\n#define  BKP_DR18_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR19 register  *******************/\n#define  BKP_DR19_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR20 register  *******************/\n#define  BKP_DR20_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR21 register  *******************/\n#define  BKP_DR21_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR22 register  *******************/\n#define  BKP_DR22_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR23 register  *******************/\n#define  BKP_DR23_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR24 register  *******************/\n#define  BKP_DR24_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR25 register  *******************/\n#define  BKP_DR25_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR26 register  *******************/\n#define  BKP_DR26_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR27 register  *******************/\n#define  BKP_DR27_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR28 register  *******************/\n#define  BKP_DR28_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR29 register  *******************/\n#define  BKP_DR29_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR30 register  *******************/\n#define  BKP_DR30_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR31 register  *******************/\n#define  BKP_DR31_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR32 register  *******************/\n#define  BKP_DR32_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR33 register  *******************/\n#define  BKP_DR33_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR34 register  *******************/\n#define  BKP_DR34_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR35 register  *******************/\n#define  BKP_DR35_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR36 register  *******************/\n#define  BKP_DR36_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR37 register  *******************/\n#define  BKP_DR37_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR38 register  *******************/\n#define  BKP_DR38_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR39 register  *******************/\n#define  BKP_DR39_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR40 register  *******************/\n#define  BKP_DR40_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR41 register  *******************/\n#define  BKP_DR41_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR42 register  *******************/\n#define  BKP_DR42_D                          ((uint16_t)0xFFFF)     /*!< Backup data */\n\n/******************  Bit definition for BKP_RTCCR register  *******************/\n#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */\n#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */\n#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */\n#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */\n\n/********************  Bit definition for BKP_CR register  ********************/\n#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */\n#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */\n\n/*******************  Bit definition for BKP_CSR register  ********************/\n#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */\n#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */\n#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */\n#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */\n#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for RCC_CR register  ********************/\n#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */\n#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */\n#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */\n#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */\n#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */\n#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */\n#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */\n#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */\n#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */\n#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */\n\n#ifdef STM32F10X_CL\n #define  RCC_CR_PLL2ON                       ((uint32_t)0x04000000)        /*!< PLL2 enable */\n #define  RCC_CR_PLL2RDY                      ((uint32_t)0x08000000)        /*!< PLL2 clock ready flag */\n #define  RCC_CR_PLL3ON                       ((uint32_t)0x10000000)        /*!< PLL3 enable */\n #define  RCC_CR_PLL3RDY                      ((uint32_t)0x20000000)        /*!< PLL3 clock ready flag */\n#endif /* STM32F10X_CL */\n\n/*******************  Bit definition for RCC_CFGR register  *******************/\n/*!< SW configuration */\n#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */\n#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */\n\n#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */\n#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */\n#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */\n#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */\n#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */\n#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */\n#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */\n#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */\n#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */\n#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */\n#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */\n#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */\n#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */\n#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */\n#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */\n#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */\n\n#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\n#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */\n#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */\n#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */\n#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */\n\n/*!< ADCPPRE configuration */\n#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */\n#define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */\n#define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */\n\n#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */\n#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */\n#define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */\n#define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */\n\n#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */\n\n#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */\n\n/*!< PLLMUL configuration */\n#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\n#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */\n#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */\n#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */\n\n#ifdef STM32F10X_CL\n #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */\n #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */\n\n #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */\n #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */\n\n #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock * 4 */\n #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock * 5 */\n #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock * 6 */\n #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock * 7 */\n #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock * 8 */\n #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock * 9 */\n #define  RCC_CFGR_PLLMULL6_5                ((uint32_t)0x00340000)        /*!< PLL input clock * 6.5 */\n \n #define  RCC_CFGR_OTGFSPRE                  ((uint32_t)0x00400000)        /*!< USB OTG FS prescaler */\n \n/*!< MCO configuration */\n #define  RCC_CFGR_MCO                       ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */\n #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */\n #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */\n #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */\n #define  RCC_CFGR_MCO_3                     ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */\n #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source */\n #define  RCC_CFGR_MCO_PLLCLK_Div2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */\n #define  RCC_CFGR_MCO_PLL2CLK               ((uint32_t)0x08000000)        /*!< PLL2 clock selected as MCO source*/\n #define  RCC_CFGR_MCO_PLL3CLK_Div2          ((uint32_t)0x09000000)        /*!< PLL3 clock divided by 2 selected as MCO source*/\n #define  RCC_CFGR_MCO_Ext_HSE               ((uint32_t)0x0A000000)        /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */\n #define  RCC_CFGR_MCO_PLL3CLK               ((uint32_t)0x0B000000)        /*!< PLL3 clock selected as MCO source */\n#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */\n #define  RCC_CFGR_PLLSRC_PREDIV1            ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */\n\n #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */\n #define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */\n\n #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */\n #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */\n #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */\n #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */\n #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */\n #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */\n #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */\n #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */\n #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */\n #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */\n #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */\n #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */\n #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */\n #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */\n #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */\n\n/*!< MCO configuration */\n #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */\n #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */\n #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */\n #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */\n\n #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */\n #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */\n #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */\n#else\n #define  RCC_CFGR_PLLSRC_HSI_Div2           ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */\n #define  RCC_CFGR_PLLSRC_HSE                ((uint32_t)0x00010000)        /*!< HSE clock selected as PLL entry clock source */\n\n #define  RCC_CFGR_PLLXTPRE_HSE              ((uint32_t)0x00000000)        /*!< HSE clock not divided for PLL entry */\n #define  RCC_CFGR_PLLXTPRE_HSE_Div2         ((uint32_t)0x00020000)        /*!< HSE clock divided by 2 for PLL entry */\n\n #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */\n #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */\n #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */\n #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */\n #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */\n #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */\n #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */\n #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */\n #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */\n #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */\n #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */\n #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */\n #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */\n #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */\n #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */\n #define  RCC_CFGR_USBPRE                    ((uint32_t)0x00400000)        /*!< USB Device prescaler */\n\n/*!< MCO configuration */\n #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */\n #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */\n #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */\n #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */\n\n #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */\n #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */\n #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */\n #define  RCC_CFGR_MCO_PLL                   ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */\n#endif /* STM32F10X_CL */\n\n/*!<******************  Bit definition for RCC_CIR register  ********************/\n#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */\n#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */\n#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */\n#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */\n#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */\n#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */\n#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */\n#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */\n#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */\n#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */\n#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */\n#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */\n#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */\n#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */\n#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */\n#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */\n#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */\n\n#ifdef STM32F10X_CL\n #define  RCC_CIR_PLL2RDYF                    ((uint32_t)0x00000020)        /*!< PLL2 Ready Interrupt flag */\n #define  RCC_CIR_PLL3RDYF                    ((uint32_t)0x00000040)        /*!< PLL3 Ready Interrupt flag */\n #define  RCC_CIR_PLL2RDYIE                   ((uint32_t)0x00002000)        /*!< PLL2 Ready Interrupt Enable */\n #define  RCC_CIR_PLL3RDYIE                   ((uint32_t)0x00004000)        /*!< PLL3 Ready Interrupt Enable */\n #define  RCC_CIR_PLL2RDYC                    ((uint32_t)0x00200000)        /*!< PLL2 Ready Interrupt Clear */\n #define  RCC_CIR_PLL3RDYC                    ((uint32_t)0x00400000)        /*!< PLL3 Ready Interrupt Clear */\n#endif /* STM32F10X_CL */\n\n/*****************  Bit definition for RCC_APB2RSTR register  *****************/\n#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */\n#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */\n#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */\n#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */\n#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */\n#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */\n\n#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\n#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)        /*!< ADC 2 interface reset */\n#endif\n\n#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */\n#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */\n#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */\n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */\n#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */\n#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */\n#endif\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\n #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */\n#endif /* STM32F10X_LD && STM32F10X_LD_VL */\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\n #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */\n #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */\n #define  RCC_APB2RSTR_TIM8RST               ((uint32_t)0x00002000)        /*!< TIM8 Timer reset */\n #define  RCC_APB2RSTR_ADC3RST               ((uint32_t)0x00008000)        /*!< ADC3 interface reset */\n#endif\n\n#if defined (STM32F10X_HD_VL)\n #define  RCC_APB2RSTR_IOPFRST               ((uint32_t)0x00000080)        /*!< I/O port F reset */\n #define  RCC_APB2RSTR_IOPGRST               ((uint32_t)0x00000100)        /*!< I/O port G reset */\n#endif\n\n#ifdef STM32F10X_XL\n #define  RCC_APB2RSTR_TIM9RST               ((uint32_t)0x00080000)         /*!< TIM9 Timer reset */\n #define  RCC_APB2RSTR_TIM10RST              ((uint32_t)0x00100000)         /*!< TIM10 Timer reset */\n #define  RCC_APB2RSTR_TIM11RST              ((uint32_t)0x00200000)         /*!< TIM11 Timer reset */\n#endif /* STM32F10X_XL */\n\n/*****************  Bit definition for RCC_APB1RSTR register  *****************/\n#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */\n#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */\n#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */\n#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */\n#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */\n\n#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\n#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)        /*!< CAN1 reset */\n#endif\n\n#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */\n#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\n #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */\n #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */\n #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */\n #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */\n#endif /* STM32F10X_LD && STM32F10X_LD_VL */\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined  (STM32F10X_XL)\n #define  RCC_APB1RSTR_USBRST                ((uint32_t)0x00800000)        /*!< USB Device reset */\n#endif\n\n#if defined (STM32F10X_HD) || defined  (STM32F10X_CL) || defined  (STM32F10X_XL)\n #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */\n #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */\n #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */\n #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */\n #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */\n #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */\n #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */\n#endif\n\n#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)\n #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */\n #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */\n #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */\n #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */ \n#endif\n\n#if defined  (STM32F10X_HD_VL)\n #define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */\n #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)        /*!< TIM12 Timer reset */\n #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)        /*!< TIM13 Timer reset */\n #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< TIM14 Timer reset */\n #define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */ \n #define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */\n #define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */ \n#endif\n\n#ifdef STM32F10X_CL\n #define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)        /*!< CAN2 reset */\n#endif /* STM32F10X_CL */\n\n#ifdef STM32F10X_XL\n #define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)         /*!< TIM12 Timer reset */\n #define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)         /*!< TIM13 Timer reset */\n #define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)         /*!< TIM14 Timer reset */\n#endif /* STM32F10X_XL */\n\n/******************  Bit definition for RCC_AHBENR register  ******************/\n#define  RCC_AHBENR_DMA1EN                   ((uint16_t)0x0001)            /*!< DMA1 clock enable */\n#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */\n#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */\n#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined  (STM32F10X_CL) || defined  (STM32F10X_HD_VL)\n #define  RCC_AHBENR_DMA2EN                  ((uint16_t)0x0002)            /*!< DMA2 clock enable */\n#endif\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\n #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */\n #define  RCC_AHBENR_SDIOEN                  ((uint16_t)0x0400)            /*!< SDIO clock enable */\n#endif\n\n#if defined (STM32F10X_HD_VL)\n #define  RCC_AHBENR_FSMCEN                  ((uint16_t)0x0100)            /*!< FSMC clock enable */\n#endif\n\n#ifdef STM32F10X_CL\n #define  RCC_AHBENR_OTGFSEN                 ((uint32_t)0x00001000)         /*!< USB OTG FS clock enable */\n #define  RCC_AHBENR_ETHMACEN                ((uint32_t)0x00004000)         /*!< ETHERNET MAC clock enable */\n #define  RCC_AHBENR_ETHMACTXEN              ((uint32_t)0x00008000)         /*!< ETHERNET MAC Tx clock enable */\n #define  RCC_AHBENR_ETHMACRXEN              ((uint32_t)0x00010000)         /*!< ETHERNET MAC Rx clock enable */\n#endif /* STM32F10X_CL */\n\n/******************  Bit definition for RCC_APB2ENR register  *****************/\n#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */\n#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */\n#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */\n#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */\n#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */\n#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */\n\n#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\n#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)         /*!< ADC 2 interface clock enable */\n#endif\n\n#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */\n#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */\n#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */\n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */\n#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */\n#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */\n#endif\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\n #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */\n#endif /* STM32F10X_LD && STM32F10X_LD_VL */\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\n #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */\n #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */\n #define  RCC_APB2ENR_TIM8EN                 ((uint32_t)0x00002000)         /*!< TIM8 Timer clock enable */\n #define  RCC_APB2ENR_ADC3EN                 ((uint32_t)0x00008000)         /*!< DMA1 clock enable */\n#endif\n\n#if defined (STM32F10X_HD_VL)\n #define  RCC_APB2ENR_IOPFEN                 ((uint32_t)0x00000080)         /*!< I/O port F clock enable */\n #define  RCC_APB2ENR_IOPGEN                 ((uint32_t)0x00000100)         /*!< I/O port G clock enable */\n#endif\n\n#ifdef STM32F10X_XL\n #define  RCC_APB2ENR_TIM9EN                 ((uint32_t)0x00080000)         /*!< TIM9 Timer clock enable  */\n #define  RCC_APB2ENR_TIM10EN                ((uint32_t)0x00100000)         /*!< TIM10 Timer clock enable  */\n #define  RCC_APB2ENR_TIM11EN                ((uint32_t)0x00200000)         /*!< TIM11 Timer clock enable */\n#endif\n\n/*****************  Bit definition for RCC_APB1ENR register  ******************/\n#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/\n#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */\n#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */\n#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */\n#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */\n\n#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\n#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)        /*!< CAN1 clock enable */\n#endif\n\n#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */\n#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */\n\n#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\n #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */\n #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */\n #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */\n #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */\n#endif /* STM32F10X_LD && STM32F10X_LD_VL */\n\n#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined  (STM32F10X_LD)\n #define  RCC_APB1ENR_USBEN                  ((uint32_t)0x00800000)        /*!< USB Device clock enable */\n#endif\n\n#if defined (STM32F10X_HD) || defined  (STM32F10X_CL)\n #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */\n #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */\n #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */\n #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */\n #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */\n #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */\n #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */\n#endif\n\n#if defined (STM32F10X_LD_VL) || defined  (STM32F10X_MD_VL) || defined  (STM32F10X_HD_VL)\n #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */\n #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */\n #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */\n #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */ \n#endif\n\n#ifdef STM32F10X_HD_VL\n #define  RCC_APB1ENR_TIM5EN                 ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */\n #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */\n #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */\n #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */\n #define  RCC_APB1ENR_SPI3EN                 ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */\n #define  RCC_APB1ENR_UART4EN                ((uint32_t)0x00080000)        /*!< UART 4 clock enable */\n #define  RCC_APB1ENR_UART5EN                ((uint32_t)0x00100000)        /*!< UART 5 clock enable */ \n#endif /* STM32F10X_HD_VL */\n\n#ifdef STM32F10X_CL\n #define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)        /*!< CAN2 clock enable */\n#endif /* STM32F10X_CL */\n\n#ifdef STM32F10X_XL\n #define  RCC_APB1ENR_TIM12EN                ((uint32_t)0x00000040)         /*!< TIM12 Timer clock enable  */\n #define  RCC_APB1ENR_TIM13EN                ((uint32_t)0x00000080)         /*!< TIM13 Timer clock enable  */\n #define  RCC_APB1ENR_TIM14EN                ((uint32_t)0x00000100)         /*!< TIM14 Timer clock enable */\n#endif /* STM32F10X_XL */\n\n/*******************  Bit definition for RCC_BDCR register  *******************/\n#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */\n#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */\n#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */\n\n#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */\n#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */\n\n/*!< RTC congiguration */\n#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */\n#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */\n#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */\n#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */\n\n#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */\n#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */\n\n/*******************  Bit definition for RCC_CSR register  ********************/  \n#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */\n#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */\n#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */\n#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */\n#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */\n#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */\n#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */\n#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */\n#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */\n\n#ifdef STM32F10X_CL\n/*******************  Bit definition for RCC_AHBRSTR register  ****************/\n #define  RCC_AHBRSTR_OTGFSRST               ((uint32_t)0x00001000)         /*!< USB OTG FS reset */\n #define  RCC_AHBRSTR_ETHMACRST              ((uint32_t)0x00004000)         /*!< ETHERNET MAC reset */\n\n/*******************  Bit definition for RCC_CFGR2 register  ******************/\n/*!< PREDIV1 configuration */\n #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */\n #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */\n #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */\n #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */\n #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */\n #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */\n #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */\n #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */\n #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */\n #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */\n #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */\n #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */\n #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */\n #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */\n #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */\n #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */\n #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */\n\n/*!< PREDIV2 configuration */\n #define  RCC_CFGR2_PREDIV2                  ((uint32_t)0x000000F0)        /*!< PREDIV2[3:0] bits */\n #define  RCC_CFGR2_PREDIV2_0                ((uint32_t)0x00000010)        /*!< Bit 0 */\n #define  RCC_CFGR2_PREDIV2_1                ((uint32_t)0x00000020)        /*!< Bit 1 */\n #define  RCC_CFGR2_PREDIV2_2                ((uint32_t)0x00000040)        /*!< Bit 2 */\n #define  RCC_CFGR2_PREDIV2_3                ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n #define  RCC_CFGR2_PREDIV2_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV2 input clock not divided */\n #define  RCC_CFGR2_PREDIV2_DIV2             ((uint32_t)0x00000010)        /*!< PREDIV2 input clock divided by 2 */\n #define  RCC_CFGR2_PREDIV2_DIV3             ((uint32_t)0x00000020)        /*!< PREDIV2 input clock divided by 3 */\n #define  RCC_CFGR2_PREDIV2_DIV4             ((uint32_t)0x00000030)        /*!< PREDIV2 input clock divided by 4 */\n #define  RCC_CFGR2_PREDIV2_DIV5             ((uint32_t)0x00000040)        /*!< PREDIV2 input clock divided by 5 */\n #define  RCC_CFGR2_PREDIV2_DIV6             ((uint32_t)0x00000050)        /*!< PREDIV2 input clock divided by 6 */\n #define  RCC_CFGR2_PREDIV2_DIV7             ((uint32_t)0x00000060)        /*!< PREDIV2 input clock divided by 7 */\n #define  RCC_CFGR2_PREDIV2_DIV8             ((uint32_t)0x00000070)        /*!< PREDIV2 input clock divided by 8 */\n #define  RCC_CFGR2_PREDIV2_DIV9             ((uint32_t)0x00000080)        /*!< PREDIV2 input clock divided by 9 */\n #define  RCC_CFGR2_PREDIV2_DIV10            ((uint32_t)0x00000090)        /*!< PREDIV2 input clock divided by 10 */\n #define  RCC_CFGR2_PREDIV2_DIV11            ((uint32_t)0x000000A0)        /*!< PREDIV2 input clock divided by 11 */\n #define  RCC_CFGR2_PREDIV2_DIV12            ((uint32_t)0x000000B0)        /*!< PREDIV2 input clock divided by 12 */\n #define  RCC_CFGR2_PREDIV2_DIV13            ((uint32_t)0x000000C0)        /*!< PREDIV2 input clock divided by 13 */\n #define  RCC_CFGR2_PREDIV2_DIV14            ((uint32_t)0x000000D0)        /*!< PREDIV2 input clock divided by 14 */\n #define  RCC_CFGR2_PREDIV2_DIV15            ((uint32_t)0x000000E0)        /*!< PREDIV2 input clock divided by 15 */\n #define  RCC_CFGR2_PREDIV2_DIV16            ((uint32_t)0x000000F0)        /*!< PREDIV2 input clock divided by 16 */\n\n/*!< PLL2MUL configuration */\n #define  RCC_CFGR2_PLL2MUL                  ((uint32_t)0x00000F00)        /*!< PLL2MUL[3:0] bits */\n #define  RCC_CFGR2_PLL2MUL_0                ((uint32_t)0x00000100)        /*!< Bit 0 */\n #define  RCC_CFGR2_PLL2MUL_1                ((uint32_t)0x00000200)        /*!< Bit 1 */\n #define  RCC_CFGR2_PLL2MUL_2                ((uint32_t)0x00000400)        /*!< Bit 2 */\n #define  RCC_CFGR2_PLL2MUL_3                ((uint32_t)0x00000800)        /*!< Bit 3 */\n\n #define  RCC_CFGR2_PLL2MUL8                 ((uint32_t)0x00000600)        /*!< PLL2 input clock * 8 */\n #define  RCC_CFGR2_PLL2MUL9                 ((uint32_t)0x00000700)        /*!< PLL2 input clock * 9 */\n #define  RCC_CFGR2_PLL2MUL10                ((uint32_t)0x00000800)        /*!< PLL2 input clock * 10 */\n #define  RCC_CFGR2_PLL2MUL11                ((uint32_t)0x00000900)        /*!< PLL2 input clock * 11 */\n #define  RCC_CFGR2_PLL2MUL12                ((uint32_t)0x00000A00)        /*!< PLL2 input clock * 12 */\n #define  RCC_CFGR2_PLL2MUL13                ((uint32_t)0x00000B00)        /*!< PLL2 input clock * 13 */\n #define  RCC_CFGR2_PLL2MUL14                ((uint32_t)0x00000C00)        /*!< PLL2 input clock * 14 */\n #define  RCC_CFGR2_PLL2MUL16                ((uint32_t)0x00000E00)        /*!< PLL2 input clock * 16 */\n #define  RCC_CFGR2_PLL2MUL20                ((uint32_t)0x00000F00)        /*!< PLL2 input clock * 20 */\n\n/*!< PLL3MUL configuration */\n #define  RCC_CFGR2_PLL3MUL                  ((uint32_t)0x0000F000)        /*!< PLL3MUL[3:0] bits */\n #define  RCC_CFGR2_PLL3MUL_0                ((uint32_t)0x00001000)        /*!< Bit 0 */\n #define  RCC_CFGR2_PLL3MUL_1                ((uint32_t)0x00002000)        /*!< Bit 1 */\n #define  RCC_CFGR2_PLL3MUL_2                ((uint32_t)0x00004000)        /*!< Bit 2 */\n #define  RCC_CFGR2_PLL3MUL_3                ((uint32_t)0x00008000)        /*!< Bit 3 */\n\n #define  RCC_CFGR2_PLL3MUL8                 ((uint32_t)0x00006000)        /*!< PLL3 input clock * 8 */\n #define  RCC_CFGR2_PLL3MUL9                 ((uint32_t)0x00007000)        /*!< PLL3 input clock * 9 */\n #define  RCC_CFGR2_PLL3MUL10                ((uint32_t)0x00008000)        /*!< PLL3 input clock * 10 */\n #define  RCC_CFGR2_PLL3MUL11                ((uint32_t)0x00009000)        /*!< PLL3 input clock * 11 */\n #define  RCC_CFGR2_PLL3MUL12                ((uint32_t)0x0000A000)        /*!< PLL3 input clock * 12 */\n #define  RCC_CFGR2_PLL3MUL13                ((uint32_t)0x0000B000)        /*!< PLL3 input clock * 13 */\n #define  RCC_CFGR2_PLL3MUL14                ((uint32_t)0x0000C000)        /*!< PLL3 input clock * 14 */\n #define  RCC_CFGR2_PLL3MUL16                ((uint32_t)0x0000E000)        /*!< PLL3 input clock * 16 */\n #define  RCC_CFGR2_PLL3MUL20                ((uint32_t)0x0000F000)        /*!< PLL3 input clock * 20 */\n\n #define  RCC_CFGR2_PREDIV1SRC               ((uint32_t)0x00010000)        /*!< PREDIV1 entry clock source */\n #define  RCC_CFGR2_PREDIV1SRC_PLL2          ((uint32_t)0x00010000)        /*!< PLL2 selected as PREDIV1 entry clock source */\n #define  RCC_CFGR2_PREDIV1SRC_HSE           ((uint32_t)0x00000000)        /*!< HSE selected as PREDIV1 entry clock source */\n #define  RCC_CFGR2_I2S2SRC                  ((uint32_t)0x00020000)        /*!< I2S2 entry clock source */\n #define  RCC_CFGR2_I2S3SRC                  ((uint32_t)0x00040000)        /*!< I2S3 clock source */\n#endif /* STM32F10X_CL */\n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n/*******************  Bit definition for RCC_CFGR2 register  ******************/\n/*!< PREDIV1 configuration */\n #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */\n #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */\n #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */\n #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */\n #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */\n #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */\n #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */\n #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */\n #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */\n #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */\n #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */\n #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */\n #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */\n #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */\n #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */\n #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */\n #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */\n#endif\n \n/******************************************************************************/\n/*                                                                            */\n/*                General Purpose and Alternate Function I/O                  */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for GPIO_CRL register  *******************/\n#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */\n\n#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\n#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\n#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\n#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\n#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\n#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\n#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\n#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\n#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */\n\n#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\n#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\n#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\n#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\n#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\n#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\n#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\n#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */\n\n#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\n#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */\n#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */\n\n/*******************  Bit definition for GPIO_CRH register  *******************/\n#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */\n\n#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\n#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\n#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\n#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\n#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\n#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\n#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\n#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\n#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */\n\n#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\n#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\n#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\n#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\n#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\n#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\n#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\n#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */\n\n#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\n#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */\n#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */\n\n/*!<******************  Bit definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */\n#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */\n#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */\n#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */\n#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */\n#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */\n#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */\n#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */\n#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */\n#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */\n#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */\n#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */\n#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */\n#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */\n#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */\n#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */\n\n/*******************  Bit definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */\n#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */\n#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */\n#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */\n#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */\n#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */\n#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */\n#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */\n#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */\n#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */\n#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */\n#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */\n#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */\n#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */\n#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */\n#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */\n\n/******************  Bit definition for GPIO_BSRR register  *******************/\n#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */\n#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */\n#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */\n#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */\n#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */\n#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */\n#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */\n#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */\n#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */\n#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */\n#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */\n#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */\n#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */\n#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */\n#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */\n#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */\n\n#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */\n#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */\n#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */\n#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */\n#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */\n#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */\n#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */\n#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */\n#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */\n#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */\n#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */\n#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */\n#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */\n#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */\n#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */\n#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */\n\n/*******************  Bit definition for GPIO_BRR register  *******************/\n#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */\n#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */\n#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */\n#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */\n#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */\n#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */\n#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */\n#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */\n#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */\n#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */\n#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */\n#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */\n#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */\n#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */\n#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */\n#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */\n\n/******************  Bit definition for GPIO_LCKR register  *******************/\n#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */\n#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */\n#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */\n#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */\n#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */\n#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */\n#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */\n#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */\n#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */\n#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */\n#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */\n#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */\n#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */\n#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */\n#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */\n#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */\n#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */\n\n/*----------------------------------------------------------------------------*/\n\n/******************  Bit definition for AFIO_EVCR register  *******************/\n#define AFIO_EVCR_PIN                        ((uint8_t)0x0F)               /*!< PIN[3:0] bits (Pin selection) */\n#define AFIO_EVCR_PIN_0                      ((uint8_t)0x01)               /*!< Bit 0 */\n#define AFIO_EVCR_PIN_1                      ((uint8_t)0x02)               /*!< Bit 1 */\n#define AFIO_EVCR_PIN_2                      ((uint8_t)0x04)               /*!< Bit 2 */\n#define AFIO_EVCR_PIN_3                      ((uint8_t)0x08)               /*!< Bit 3 */\n\n/*!< PIN configuration */\n#define AFIO_EVCR_PIN_PX0                    ((uint8_t)0x00)               /*!< Pin 0 selected */\n#define AFIO_EVCR_PIN_PX1                    ((uint8_t)0x01)               /*!< Pin 1 selected */\n#define AFIO_EVCR_PIN_PX2                    ((uint8_t)0x02)               /*!< Pin 2 selected */\n#define AFIO_EVCR_PIN_PX3                    ((uint8_t)0x03)               /*!< Pin 3 selected */\n#define AFIO_EVCR_PIN_PX4                    ((uint8_t)0x04)               /*!< Pin 4 selected */\n#define AFIO_EVCR_PIN_PX5                    ((uint8_t)0x05)               /*!< Pin 5 selected */\n#define AFIO_EVCR_PIN_PX6                    ((uint8_t)0x06)               /*!< Pin 6 selected */\n#define AFIO_EVCR_PIN_PX7                    ((uint8_t)0x07)               /*!< Pin 7 selected */\n#define AFIO_EVCR_PIN_PX8                    ((uint8_t)0x08)               /*!< Pin 8 selected */\n#define AFIO_EVCR_PIN_PX9                    ((uint8_t)0x09)               /*!< Pin 9 selected */\n#define AFIO_EVCR_PIN_PX10                   ((uint8_t)0x0A)               /*!< Pin 10 selected */\n#define AFIO_EVCR_PIN_PX11                   ((uint8_t)0x0B)               /*!< Pin 11 selected */\n#define AFIO_EVCR_PIN_PX12                   ((uint8_t)0x0C)               /*!< Pin 12 selected */\n#define AFIO_EVCR_PIN_PX13                   ((uint8_t)0x0D)               /*!< Pin 13 selected */\n#define AFIO_EVCR_PIN_PX14                   ((uint8_t)0x0E)               /*!< Pin 14 selected */\n#define AFIO_EVCR_PIN_PX15                   ((uint8_t)0x0F)               /*!< Pin 15 selected */\n\n#define AFIO_EVCR_PORT                       ((uint8_t)0x70)               /*!< PORT[2:0] bits (Port selection) */\n#define AFIO_EVCR_PORT_0                     ((uint8_t)0x10)               /*!< Bit 0 */\n#define AFIO_EVCR_PORT_1                     ((uint8_t)0x20)               /*!< Bit 1 */\n#define AFIO_EVCR_PORT_2                     ((uint8_t)0x40)               /*!< Bit 2 */\n\n/*!< PORT configuration */\n#define AFIO_EVCR_PORT_PA                    ((uint8_t)0x00)               /*!< Port A selected */\n#define AFIO_EVCR_PORT_PB                    ((uint8_t)0x10)               /*!< Port B selected */\n#define AFIO_EVCR_PORT_PC                    ((uint8_t)0x20)               /*!< Port C selected */\n#define AFIO_EVCR_PORT_PD                    ((uint8_t)0x30)               /*!< Port D selected */\n#define AFIO_EVCR_PORT_PE                    ((uint8_t)0x40)               /*!< Port E selected */\n\n#define AFIO_EVCR_EVOE                       ((uint8_t)0x80)               /*!< Event Output Enable */\n\n/******************  Bit definition for AFIO_MAPR register  *******************/\n#define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */\n#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */\n#define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */\n#define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */\n\n#define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\n#define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n/* USART3_REMAP configuration */\n#define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\n\n#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\n#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n/*!< TIM1_REMAP configuration */\n#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\n\n#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\n#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n\n/*!< TIM2_REMAP configuration */\n#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\n\n#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\n#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */\n\n/*!< TIM3_REMAP configuration */\n#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\n\n#define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */\n\n#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\n#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */\n#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */\n\n/*!< CAN_REMAP configuration */\n#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\n#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\n#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\n\n#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\n#define AFIO_MAPR_TIM5CH4_IREMAP             ((uint32_t)0x00010000)        /*!< TIM5 Channel4 Internal Remap */\n#define AFIO_MAPR_ADC1_ETRGINJ_REMAP         ((uint32_t)0x00020000)        /*!< ADC 1 External Trigger Injected Conversion remapping */\n#define AFIO_MAPR_ADC1_ETRGREG_REMAP         ((uint32_t)0x00040000)        /*!< ADC 1 External Trigger Regular Conversion remapping */\n#define AFIO_MAPR_ADC2_ETRGINJ_REMAP         ((uint32_t)0x00080000)        /*!< ADC 2 External Trigger Injected Conversion remapping */\n#define AFIO_MAPR_ADC2_ETRGREG_REMAP         ((uint32_t)0x00100000)        /*!< ADC 2 External Trigger Regular Conversion remapping */\n\n/*!< SWJ_CFG configuration */\n#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\n#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n\n#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\n#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */\n#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */\n\n#ifdef STM32F10X_CL\n/*!< ETH_REMAP configuration */\n #define AFIO_MAPR_ETH_REMAP                  ((uint32_t)0x00200000)        /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */\n\n/*!< CAN2_REMAP configuration */\n #define AFIO_MAPR_CAN2_REMAP                 ((uint32_t)0x00400000)        /*!< CAN2_REMAP bit (CAN2 I/O remapping) */\n\n/*!< MII_RMII_SEL configuration */\n #define AFIO_MAPR_MII_RMII_SEL               ((uint32_t)0x00800000)        /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */\n\n/*!< SPI3_REMAP configuration */\n #define AFIO_MAPR_SPI3_REMAP                 ((uint32_t)0x10000000)        /*!< SPI3_REMAP bit (SPI3 remapping) */\n\n/*!< TIM2ITR1_IREMAP configuration */\n #define AFIO_MAPR_TIM2ITR1_IREMAP            ((uint32_t)0x20000000)        /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */\n\n/*!< PTP_PPS_REMAP configuration */\n #define AFIO_MAPR_PTP_PPS_REMAP              ((uint32_t)0x40000000)        /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */\n#endif\n\n/*****************  Bit definition for AFIO_EXTICR1 register  *****************/\n#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */\n#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */\n#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */\n#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */\n\n/*!< EXTI0 configuration */\n#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */\n#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */\n#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */\n#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */\n#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin */\n#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin */\n#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin */\n\n/*!< EXTI1 configuration */\n#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */\n#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */\n#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */\n#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */\n#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin */\n#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin */\n#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin */\n\n/*!< EXTI2 configuration */  \n#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */\n#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */\n#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */\n#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */\n#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin */\n#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin */\n#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin */\n\n/*!< EXTI3 configuration */\n#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */\n#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */\n#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */\n#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */\n#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin */\n#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin */\n#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin */\n\n/*****************  Bit definition for AFIO_EXTICR2 register  *****************/\n#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */\n#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */\n#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */\n#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */\n\n/*!< EXTI4 configuration */\n#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */\n#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */\n#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */\n#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */\n#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin */\n#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin */\n#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin */\n\n/* EXTI5 configuration */\n#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */\n#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */\n#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */\n#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */\n#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin */\n#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin */\n#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin */\n\n/*!< EXTI6 configuration */  \n#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */\n#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */\n#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */\n#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */\n#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin */\n#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin */\n#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin */\n\n/*!< EXTI7 configuration */\n#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */\n#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */\n#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */\n#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */\n#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin */\n#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin */\n#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin */\n\n/*****************  Bit definition for AFIO_EXTICR3 register  *****************/\n#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */\n#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */\n#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */\n#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */\n\n/*!< EXTI8 configuration */\n#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */\n#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */\n#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */\n#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */\n#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin */\n#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin */\n#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin */\n\n/*!< EXTI9 configuration */\n#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */\n#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */\n#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */\n#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */\n#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin */\n#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin */\n#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin */\n\n/*!< EXTI10 configuration */  \n#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */\n#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */\n#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */\n#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */\n#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin */\n#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin */\n#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin */\n\n/*!< EXTI11 configuration */\n#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */\n#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */\n#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */\n#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */\n#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin */\n#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin */\n#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin */\n\n/*****************  Bit definition for AFIO_EXTICR4 register  *****************/\n#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */\n#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */\n#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */\n#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */\n\n/* EXTI12 configuration */\n#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */\n#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */\n#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */\n#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */\n#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin */\n#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin */\n#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin */\n\n/* EXTI13 configuration */\n#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */\n#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */\n#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */\n#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */\n#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin */\n#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin */\n#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin */\n\n/*!< EXTI14 configuration */  \n#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */\n#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */\n#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */\n#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */\n#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin */\n#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin */\n#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin */\n\n/*!< EXTI15 configuration */\n#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */\n#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */\n#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */\n#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */\n#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin */\n#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin */\n#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin */\n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n/******************  Bit definition for AFIO_MAPR2 register  ******************/\n#define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */\n#define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */\n#define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */\n#define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */\n#define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */\n#endif\n\n#ifdef STM32F10X_HD_VL\n#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */\n#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */\n#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */\n#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */\n#define AFIO_MAPR2_TIM12_REMAP               ((uint32_t)0x00001000)        /*!< TIM12 remapping */\n#define AFIO_MAPR2_MISC_REMAP                ((uint32_t)0x00002000)        /*!< Miscellaneous remapping */\n#endif\n\n#ifdef STM32F10X_XL \n/******************  Bit definition for AFIO_MAPR2 register  ******************/\n#define AFIO_MAPR2_TIM9_REMAP                ((uint32_t)0x00000020)        /*!< TIM9 remapping */\n#define AFIO_MAPR2_TIM10_REMAP               ((uint32_t)0x00000040)        /*!< TIM10 remapping */\n#define AFIO_MAPR2_TIM11_REMAP               ((uint32_t)0x00000080)        /*!< TIM11 remapping */\n#define AFIO_MAPR2_TIM13_REMAP               ((uint32_t)0x00000100)        /*!< TIM13 remapping */\n#define AFIO_MAPR2_TIM14_REMAP               ((uint32_t)0x00000200)        /*!< TIM14 remapping */\n#define AFIO_MAPR2_FSMC_NADV_REMAP           ((uint32_t)0x00000400)        /*!< FSMC NADV remapping */\n#endif\n\n/******************************************************************************/\n/*                                                                            */\n/*                               SystemTick                                   */\n/*                                                                            */\n/******************************************************************************/\n\n/*****************  Bit definition for SysTick_CTRL register  *****************/\n#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */\n#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */\n#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */\n#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */\n\n/*****************  Bit definition for SysTick_LOAD register  *****************/\n#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\n\n/*****************  Bit definition for SysTick_VAL register  ******************/\n#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */\n\n/*****************  Bit definition for SysTick_CALIB register  ****************/\n#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */\n#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */\n#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */\n\n/******************************************************************************/\n/*                                                                            */\n/*                  Nested Vectored Interrupt Controller                      */\n/*                                                                            */\n/******************************************************************************/\n\n/******************  Bit definition for NVIC_ISER register  *******************/\n#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */\n#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\n#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\n#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\n#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\n#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\n#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\n#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\n#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\n#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\n#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\n#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\n#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\n#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\n#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\n#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\n#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\n#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\n#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\n#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\n#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\n#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\n#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\n#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\n#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\n#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\n#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\n#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\n#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\n#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\n#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\n#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\n#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\n\n/******************  Bit definition for NVIC_ICER register  *******************/\n#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */\n#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\n#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\n#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\n#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\n#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\n#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\n#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\n#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\n#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\n#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\n#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\n#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\n#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\n#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\n#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\n#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\n#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\n#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\n#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\n#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\n#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\n#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\n#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\n#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\n#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\n#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\n#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\n#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\n#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\n#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\n#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\n#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\n\n/******************  Bit definition for NVIC_ISPR register  *******************/\n#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */\n#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */\n#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */\n#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */\n#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */\n#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */\n#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */\n#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */\n#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */\n#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */\n#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */\n#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */\n#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */\n#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */\n#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */\n#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */\n#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */\n#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */\n#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */\n#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */\n#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */\n#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */\n#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */\n#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */\n#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */\n#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */\n#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */\n#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */\n#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */\n#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */\n#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */\n#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */\n#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */\n\n/******************  Bit definition for NVIC_ICPR register  *******************/\n#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */\n#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */\n#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */\n#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */\n#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */\n#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */\n#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */\n#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */\n#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */\n#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */\n#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */\n#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */\n#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */\n#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */\n#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */\n#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */\n#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */\n#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */\n#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */\n#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */\n#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */\n#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */\n#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */\n#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */\n#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */\n#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */\n#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */\n#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */\n#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */\n#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */\n#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */\n#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */\n#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */\n\n/******************  Bit definition for NVIC_IABR register  *******************/\n#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */\n#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */\n#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */\n#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */\n#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */\n#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */\n#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */\n#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */\n#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */\n#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */\n#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */\n#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */\n#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */\n#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */\n#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */\n#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */\n#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */\n#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */\n#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */\n#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */\n#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */\n#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */\n#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */\n#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */\n#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */\n#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */\n#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */\n#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */\n#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */\n#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */\n#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */\n#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */\n#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */\n\n/******************  Bit definition for NVIC_PRI0 register  *******************/\n#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */\n#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */\n#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */\n#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */\n\n/******************  Bit definition for NVIC_PRI1 register  *******************/\n#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */\n#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */\n#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */\n#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */\n\n/******************  Bit definition for NVIC_PRI2 register  *******************/\n#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */\n#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */\n#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */\n#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */\n\n/******************  Bit definition for NVIC_PRI3 register  *******************/\n#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */\n#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */\n#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */\n#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */\n\n/******************  Bit definition for NVIC_PRI4 register  *******************/\n#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */\n#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */\n#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */\n#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */\n\n/******************  Bit definition for NVIC_PRI5 register  *******************/\n#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */\n#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */\n#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */\n#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */\n\n/******************  Bit definition for NVIC_PRI6 register  *******************/\n#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */\n#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */\n#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */\n#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */\n\n/******************  Bit definition for NVIC_PRI7 register  *******************/\n#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */\n#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */\n#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */\n#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */\n\n/******************  Bit definition for SCB_CPUID register  *******************/\n#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */\n#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */\n#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */\n#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */\n#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */\n\n/*******************  Bit definition for SCB_ICSR register  *******************/\n#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */\n#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\n#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */\n#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */\n#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */\n#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */\n#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */\n#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */\n#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */\n#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */\n\n/*******************  Bit definition for SCB_VTOR register  *******************/\n#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */\n#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */\n\n/*!<*****************  Bit definition for SCB_AIRCR register  *******************/\n#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */\n#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */\n#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */\n\n#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */\n#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */\n\n/* prority group configuration */\n#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\n#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\n#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\n\n#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */\n#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\n\n/*******************  Bit definition for SCB_SCR register  ********************/\n#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */\n#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */\n#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */\n\n/********************  Bit definition for SCB_CCR register  *******************/\n#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\n#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\n#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */\n#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */\n#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */\n#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\n\n/*******************  Bit definition for SCB_SHPR register ********************/\n#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\n#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\n#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\n#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\n\n/******************  Bit definition for SCB_SHCSR register  *******************/\n#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */\n#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */\n#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */\n#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */\n#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */\n#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */\n#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */\n#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */\n#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */\n#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */\n#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */\n#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */\n#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */\n#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */\n\n/*******************  Bit definition for SCB_CFSR register  *******************/\n/*!< MFSR */\n#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */\n#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */\n#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */\n#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */\n#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */\n/*!< BFSR */\n#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */\n#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */\n#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */\n#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */\n#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */\n#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */\n/*!< UFSR */\n#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */\n#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */\n#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */\n#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */\n#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */\n#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\n\n/*******************  Bit definition for SCB_HFSR register  *******************/\n#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */\n#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\n#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */\n\n/*******************  Bit definition for SCB_DFSR register  *******************/\n#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */\n#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */\n#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */\n#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */\n#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */\n\n/*******************  Bit definition for SCB_MMFAR register  ******************/\n#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */\n\n/*******************  Bit definition for SCB_BFAR register  *******************/\n#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */\n\n/*******************  Bit definition for SCB_afsr register  *******************/\n#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */\n#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */\n#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */\n#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */\n#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */\n#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */\n#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */\n#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */\n#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */\n#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */\n#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */\n#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */\n#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */\n#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */\n#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */\n#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */\n#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */\n#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */\n#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */\n#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */\n#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */\n#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */\n#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */\n#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */\n#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */\n#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */\n#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */\n#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */\n#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */\n#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */\n#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */\n#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */\n#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */\n#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */\n#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */\n#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */\n#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */\n#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */\n#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */\n#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */\n#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */\n#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */\n#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */\n#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */\n#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */\n#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */\n#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */\n#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */\n#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */\n#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */\n#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */\n#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */\n#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */\n#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */\n#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */\n#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */\n#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */\n#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */\n#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */\n#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */\n#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */\n#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */\n#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */\n#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */\n#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */\n#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */\n#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */\n#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */\n#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */\n#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */\n#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */\n#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */\n#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */\n#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */\n#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */\n#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */\n#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */\n#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */\n#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */\n#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */\n#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */\n#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */\n#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */\n#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */\n#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */\n#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */\n#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */\n#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */\n#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */\n#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */\n#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */\n#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */\n#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */\n#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */\n#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */\n#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */\n#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */\n#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */\n#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */\n#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */\n#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */\n#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */\n#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */\n#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */\n#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */\n#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */\n#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */\n#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */\n#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */\n#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */\n#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */\n#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */\n#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */\n#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */\n#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for DMA_ISR register  ********************/\n#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */\n#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */\n#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */\n#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */\n#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */\n#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */\n#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */\n#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */\n#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */\n#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */\n#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */\n#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */\n#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */\n#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */\n#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */\n#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */\n#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */\n#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */\n#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */\n#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */\n#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */\n#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */\n#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */\n#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */\n#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */\n#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */\n#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */\n#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */\n\n/*******************  Bit definition for DMA_IFCR register  *******************/\n#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */\n#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */\n#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */\n#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */\n#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */\n#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */\n#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */\n#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */\n#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */\n#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */\n#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */\n#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */\n#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */\n#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */\n#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */\n#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */\n#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */\n#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */\n#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */\n#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */\n#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */\n#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */\n\n/*******************  Bit definition for DMA_CCR1 register  *******************/\n#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/\n#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */\n#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\n\n/*******************  Bit definition for DMA_CCR2 register  *******************/\n#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\n\n/*******************  Bit definition for DMA_CCR3 register  *******************/\n#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\n\n/*!<******************  Bit definition for DMA_CCR4 register  *******************/\n#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\n\n/******************  Bit definition for DMA_CCR5 register  *******************/\n#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */\n\n/*******************  Bit definition for DMA_CCR6 register  *******************/\n#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */\n\n/*******************  Bit definition for DMA_CCR7 register  *******************/\n#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!< Channel enable */\n#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */\n#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */\n#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */\n#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */\n#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */\n#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */\n#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */\n\n#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */\n#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */\n#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */\n#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode enable */\n\n/******************  Bit definition for DMA_CNDTR1 register  ******************/\n#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR2 register  ******************/\n#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR3 register  ******************/\n#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR4 register  ******************/\n#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR5 register  ******************/\n#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR6 register  ******************/\n#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CNDTR7 register  ******************/\n#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CPAR1 register  *******************/\n#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CPAR2 register  *******************/\n#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CPAR3 register  *******************/\n#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n\n/******************  Bit definition for DMA_CPAR4 register  *******************/\n#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CPAR5 register  *******************/\n#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CPAR6 register  *******************/\n#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n\n/******************  Bit definition for DMA_CPAR7 register  *******************/\n#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CMAR1 register  *******************/\n#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************  Bit definition for DMA_CMAR2 register  *******************/\n#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************  Bit definition for DMA_CMAR3 register  *******************/\n#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n\n/******************  Bit definition for DMA_CMAR4 register  *******************/\n#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************  Bit definition for DMA_CMAR5 register  *******************/\n#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************  Bit definition for DMA_CMAR6 register  *******************/\n#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************  Bit definition for DMA_CMAR7 register  *******************/\n#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!< Analog watchdog flag */\n#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!< End of conversion */\n#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!< Injected channel end of conversion */\n#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!< Injected channel Start flag */\n#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!< Regular channel Start flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\n\n#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */\n#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */\n#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */\n#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */\n#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */\n#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */\n#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */\n#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */\n\n#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */\n#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */\n#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */\n\n#define  ADC_CR1_DUALMOD                     ((uint32_t)0x000F0000)        /*!< DUALMOD[3:0] bits (Dual mode selection) */\n#define  ADC_CR1_DUALMOD_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  ADC_CR1_DUALMOD_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  ADC_CR1_DUALMOD_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  ADC_CR1_DUALMOD_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */\n\n#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */\n#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */\n\n  \n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */\n#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */\n#define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */\n#define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */\n#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */\n#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */\n\n#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */\n#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */\n#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */\n\n#define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */\n\n#define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */\n#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */\n#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */\n#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */\n\n#define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */\n#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */\n#define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */\n#define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */\n\n#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */\n#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */\n#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */\n\n#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */\n#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */\n#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!< Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!< Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */\n#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\n\n#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */\n#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\n#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\n#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\n#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\n#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\n\n#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */\n#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */\n#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\n#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\n#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\n\n#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */\n#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */\n#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */\n\n#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */\n#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */\n\n#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */\n#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */\n#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\n\n#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */\n#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */\n\n#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */\n#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */\n#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */\n#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */\n#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */\n#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */\n#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */\n\n#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */\n\n#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */\n#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */\n\n#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */\n#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */\n\n#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */\n#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */\n#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */\n#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */\n#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */\n#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  \n#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */\n\n#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */\n#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */\n#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */\n#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */\n#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */\n\n#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */\n#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */\n#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */\n#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */\n#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */\n\n#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */\n#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!< Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */\n#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!< ADC2 data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for DAC_CR register  ********************/\n#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */\n#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */\n#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */\n\n#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */\n#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */\n#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */\n\n#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */\n\n#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */\n#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */\n#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */\n#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */\n\n#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */\n#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */\n#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */\n\n#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */\n#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */\n\n#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */\n\n#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\n #define  DAC_CR_DMAUDRIE1                   ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun interrupt enable */\n #define  DAC_CR_DMAUDRIE2                   ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun interrupt enable */\n#endif\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!< DAC channel1 software trigger */\n#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!< DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!< DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!< DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!< DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!< DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!< DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!< DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */\n#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */\n#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!< DAC channel1 8-bit Right aligned data */\n#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!< DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!< DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */\n#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    CEC                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for CEC_CFGR register  ******************/\n#define  CEC_CFGR_PE              ((uint16_t)0x0001)     /*!<  Peripheral Enable */\n#define  CEC_CFGR_IE              ((uint16_t)0x0002)     /*!<  Interrupt Enable */\n#define  CEC_CFGR_BTEM            ((uint16_t)0x0004)     /*!<  Bit Timing Error Mode */\n#define  CEC_CFGR_BPEM            ((uint16_t)0x0008)     /*!<  Bit Period Error Mode */\n\n/********************  Bit definition for CEC_OAR register  ******************/\n#define  CEC_OAR_OA               ((uint16_t)0x000F)     /*!<  OA[3:0]: Own Address */\n#define  CEC_OAR_OA_0             ((uint16_t)0x0001)     /*!<  Bit 0 */\n#define  CEC_OAR_OA_1             ((uint16_t)0x0002)     /*!<  Bit 1 */\n#define  CEC_OAR_OA_2             ((uint16_t)0x0004)     /*!<  Bit 2 */\n#define  CEC_OAR_OA_3             ((uint16_t)0x0008)     /*!<  Bit 3 */\n\n/********************  Bit definition for CEC_PRES register  ******************/\n#define  CEC_PRES_PRES            ((uint16_t)0x3FFF)   /*!<  Prescaler Counter Value */\n\n/********************  Bit definition for CEC_ESR register  ******************/\n#define  CEC_ESR_BTE              ((uint16_t)0x0001)     /*!<  Bit Timing Error */\n#define  CEC_ESR_BPE              ((uint16_t)0x0002)     /*!<  Bit Period Error */\n#define  CEC_ESR_RBTFE            ((uint16_t)0x0004)     /*!<  Rx Block Transfer Finished Error */\n#define  CEC_ESR_SBE              ((uint16_t)0x0008)     /*!<  Start Bit Error */\n#define  CEC_ESR_ACKE             ((uint16_t)0x0010)     /*!<  Block Acknowledge Error */\n#define  CEC_ESR_LINE             ((uint16_t)0x0020)     /*!<  Line Error */\n#define  CEC_ESR_TBTFE            ((uint16_t)0x0040)     /*!<  Tx Block Transfer Finished Error */\n\n/********************  Bit definition for CEC_CSR register  ******************/\n#define  CEC_CSR_TSOM             ((uint16_t)0x0001)     /*!<  Tx Start Of Message */\n#define  CEC_CSR_TEOM             ((uint16_t)0x0002)     /*!<  Tx End Of Message */\n#define  CEC_CSR_TERR             ((uint16_t)0x0004)     /*!<  Tx Error */\n#define  CEC_CSR_TBTRF            ((uint16_t)0x0008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */\n#define  CEC_CSR_RSOM             ((uint16_t)0x0010)     /*!<  Rx Start Of Message */\n#define  CEC_CSR_REOM             ((uint16_t)0x0020)     /*!<  Rx End Of Message */\n#define  CEC_CSR_RERR             ((uint16_t)0x0040)     /*!<  Rx Error */\n#define  CEC_CSR_RBTF             ((uint16_t)0x0080)     /*!<  Rx Block Transfer Finished */\n\n/********************  Bit definition for CEC_TXD register  ******************/\n#define  CEC_TXD_TXD              ((uint16_t)0x00FF)     /*!<  Tx Data register */\n\n/********************  Bit definition for CEC_RXD register  ******************/\n#define  CEC_RXD_RXD              ((uint16_t)0x00FF)     /*!<  Rx Data register */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!< Counter enable */\n#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!< Update disable */\n#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!< Update request source */\n#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!< One pulse mode */\n#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!< Direction */\n\n#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!< CMS[1:0] bits (Center-aligned mode selection) */\n#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!< Bit 0 */\n#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!< Bit 1 */\n\n#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!< Auto-reload preload enable */\n\n#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!< CKD[1:0] bits (clock division) */\n#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!< Bit 1 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!< Capture/Compare Preloaded Control */\n#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!< Capture/Compare Control Update Selection */\n#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!< Capture/Compare DMA Selection */\n\n#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!< MMS[2:0] bits (Master Mode Selection) */\n#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */\n\n#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!< TI1 Selection */\n#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!< Output Idle state 1 (OC1 output) */\n#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!< Output Idle state 1 (OC1N output) */\n#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!< Output Idle state 2 (OC2 output) */\n#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!< Output Idle state 2 (OC2N output) */\n#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!< Output Idle state 3 (OC3 output) */\n#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!< Output Idle state 3 (OC3N output) */\n#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!< Output Idle state 4 (OC4 output) */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!< SMS[2:0] bits (Slave mode selection) */\n#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!< Bit 2 */\n\n#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!< TS[2:0] bits (Trigger selection) */\n#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!< Bit 2 */\n\n#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!< Master/slave mode */\n\n#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!< ETF[3:0] bits (External trigger filter) */\n#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!< Bit 1 */\n#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!< Bit 2 */\n#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!< Bit 3 */\n\n#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!< ETPS[1:0] bits (External trigger prescaler) */\n#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!< External clock enable */\n#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!< External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!< Update interrupt enable */\n#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt enable */\n#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt enable */\n#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt enable */\n#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt enable */\n#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!< COM interrupt enable */\n#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!< Trigger interrupt enable */\n#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!< Break interrupt enable */\n#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!< Update DMA request enable */\n#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!< Capture/Compare 1 DMA request enable */\n#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!< Capture/Compare 2 DMA request enable */\n#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 DMA request enable */\n#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!< Capture/Compare 4 DMA request enable */\n#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!< COM DMA request enable */\n#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!< Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!< Update interrupt Flag */\n#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!< Capture/Compare 1 interrupt Flag */\n#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!< Capture/Compare 2 interrupt Flag */\n#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!< Capture/Compare 3 interrupt Flag */\n#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!< Capture/Compare 4 interrupt Flag */\n#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!< COM interrupt Flag */\n#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!< Trigger interrupt Flag */\n#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!< Break interrupt Flag */\n#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!< Capture/Compare 1 Overcapture Flag */\n#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!< Capture/Compare 2 Overcapture Flag */\n#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!< Capture/Compare 3 Overcapture Flag */\n#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!< Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!< Update Generation */\n#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!< Capture/Compare 1 Generation */\n#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!< Capture/Compare 2 Generation */\n#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!< Capture/Compare 3 Generation */\n#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!< Capture/Compare 4 Generation */\n#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!< Capture/Compare Control Update Generation */\n#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!< Trigger Generation */\n#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!< Break Generation */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */\n\n#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!< Output Compare 1 Fast enable */\n#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!< Output Compare 1 Preload enable */\n\n#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!< OC1M[2:0] bits (Output Compare 1 Mode) */\n#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */\n\n#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!< Output Compare 1Clear Enable */\n\n#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!< Output Compare 2 Fast enable */\n#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!< Output Compare 2 Preload enable */\n\n#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!< OC2M[2:0] bits (Output Compare 2 Mode) */\n#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\n#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */\n\n#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!< Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */\n#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */\n\n#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!< IC1F[3:0] bits (Input Capture 1 Filter) */\n#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */\n#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */\n\n#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!< IC2F[3:0] bits (Input Capture 2 Filter) */\n#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\n#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */\n#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!< Bit 1 */\n\n#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!< Output Compare 3 Fast enable */\n#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!< Output Compare 3 Preload enable */\n\n#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!< OC3M[2:0] bits (Output Compare 3 Mode) */\n#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!< Bit 2 */\n\n#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!< Output Compare 3 Clear Enable */\n\n#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!< Output Compare 4 Fast enable */\n#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!< Output Compare 4 Preload enable */\n\n#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!< OC4M[2:0] bits (Output Compare 4 Mode) */\n#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\n#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!< Bit 2 */\n\n#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!< Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!< Bit 0 */\n#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!< Bit 1 */\n\n#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!< IC3F[3:0] bits (Input Capture 3 Filter) */\n#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!< Bit 2 */\n#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!< Bit 3 */\n\n#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!< Bit 1 */\n\n#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!< IC4F[3:0] bits (Input Capture 4 Filter) */\n#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\n#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!< Bit 2 */\n#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!< Bit 3 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!< Capture/Compare 1 output enable */\n#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!< Capture/Compare 1 output Polarity */\n#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!< Capture/Compare 1 Complementary output enable */\n#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!< Capture/Compare 1 Complementary output Polarity */\n#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!< Capture/Compare 2 output enable */\n#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!< Capture/Compare 2 output Polarity */\n#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!< Capture/Compare 2 Complementary output enable */\n#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!< Capture/Compare 2 Complementary output Polarity */\n#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!< Capture/Compare 3 output enable */\n#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!< Capture/Compare 3 output Polarity */\n#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!< Capture/Compare 3 Complementary output enable */\n#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!< Capture/Compare 3 Complementary output Polarity */\n#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!< Capture/Compare 4 output enable */\n#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!< Capture/Compare 4 output Polarity */\n#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!< Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!< Counter Value */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!< Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!< actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!< Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!< Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!< DTG[0:7] bits (Dead-Time Generator set-up) */\n#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!< Bit 5 */\n#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!< Bit 6 */\n#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!< Bit 7 */\n\n#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!< LOCK[1:0] bits (Lock Configuration) */\n#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!< Off-State Selection for Idle mode */\n#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!< Off-State Selection for Run mode */\n#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!< Break enable */\n#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!< Break Polarity */\n#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!< Automatic Output enable */\n#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!< Main Output enable */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!< DBA[4:0] bits (DMA Base Address) */\n#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!< Bit 4 */\n\n#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!< DBL[4:0] bits (DMA Burst Length) */\n#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!< Bit 1 */\n#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!< Bit 2 */\n#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!< Bit 3 */\n#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!< Bit 4 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!< DMA register for burst accesses */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Real-Time Clock                                */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for RTC_CRH register  ********************/\n#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!< Second Interrupt Enable */\n#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!< Alarm Interrupt Enable */\n#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!< OverfloW Interrupt Enable */\n\n/*******************  Bit definition for RTC_CRL register  ********************/\n#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!< Second Flag */\n#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!< Alarm Flag */\n#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!< OverfloW Flag */\n#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!< Registers Synchronized Flag */\n#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!< Configuration Flag */\n#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!< RTC operation OFF */\n\n/*******************  Bit definition for RTC_PRLH register  *******************/\n#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!< RTC Prescaler Reload Value High */\n\n/*******************  Bit definition for RTC_PRLL register  *******************/\n#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!< RTC Prescaler Reload Value Low */\n\n/*******************  Bit definition for RTC_DIVH register  *******************/\n#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!< RTC Clock Divider High */\n\n/*******************  Bit definition for RTC_DIVL register  *******************/\n#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!< RTC Clock Divider Low */\n\n/*******************  Bit definition for RTC_CNTH register  *******************/\n#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter High */\n\n/*******************  Bit definition for RTC_CNTL register  *******************/\n#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!< RTC Counter Low */\n\n/*******************  Bit definition for RTC_ALRH register  *******************/\n#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm High */\n\n/*******************  Bit definition for RTC_ALRL register  *******************/\n#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!< RTC Alarm Low */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */\n#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */\n#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */\n#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */\n#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */\n#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */\n#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */\n#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */\n#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */\n#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */\n#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */\n\n#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */\n#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */\n#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */\n\n#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */\n#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */\n#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */\n\n#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                       Flexible Static Memory Controller                    */\n/*                                                                            */\n/******************************************************************************/\n\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */\n#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */\n\n#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */\n#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */\n#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */\n#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */\n#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */\n#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */\n#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */\n#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */\n#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */\n#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */\n#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */\n#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */\n\n#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */\n#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */\n#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */\n#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */\n#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */\n#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */\n#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */\n#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */\n#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */\n#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */\n#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */\n#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */\n\n#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */\n#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */\n#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */\n#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit. */\n#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */\n#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */\n#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */\n#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */\n#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */\n#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */\n#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!< Memory bank enable bit */\n#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!< Address/data multiplexing enable bit */\n\n#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!< MTYP[1:0] bits (Memory type) */\n#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!< Bit 0 */\n#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!< Bit 1 */\n\n#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!< MWID[1:0] bits (Memory data bus width) */\n#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!< Flash access enable */\n#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!< Burst enable bit */\n#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!< Wait signal polarity bit */\n#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!< Wrapped burst mode support */\n#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!< Wait timing configuration */\n#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!< Write enable bit */\n#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!< Wait enable bit */\n#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!< Extended mode enable */\n#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)       /*!< Asynchronous wait */\n#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!< Write burst enable */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */\n\n#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */\n\n#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */\n\n#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */\n\n#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1*/\n#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!< ADDSET[3:0] bits (Address setup phase duration) */\n#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */\n\n#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!< ADDHLD[3:0] bits (Address-hold phase duration) */\n#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!< Bit 2 */\n#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!< Bit 3 */\n\n#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!< DATAST [3:0] bits (Data-phase duration) */\n#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!< CLKDIV[3:0] bits (Clock divide ratio) */\n#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!< Bit 0 */\n#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!< Bit 1 */\n#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!< Bit 2 */\n#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!< DATLA[3:0] bits (Data latency) */\n#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!< Bit 3 */\n\n#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!< ACCMOD[1:0] bits (Access mode) */\n#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!< Bit 0 */\n#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!< Bit 1 */\n\n/******************  Bit definition for FSMC_PCR2 register  *******************/\n#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */\n#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */\n\n#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */\n\n#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */\n#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */\n#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */\n#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */\n\n#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */\n#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */\n#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */\n#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */\n\n#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[1:0] bits (ECC page size) */\n#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */\n#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */\n#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */\n\n/******************  Bit definition for FSMC_PCR3 register  *******************/\n#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */\n#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */\n\n#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */\n\n#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */\n#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */\n#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */\n#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */\n\n#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */\n#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */\n#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */\n#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */\n\n#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */\n#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */\n#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */\n#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */\n\n/******************  Bit definition for FSMC_PCR4 register  *******************/\n#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!< Wait feature enable bit */\n#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!< PC Card/NAND Flash memory bank enable bit */\n#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!< Memory type */\n\n#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!< PWID[1:0] bits (NAND Flash databus width) */\n#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */\n\n#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!< ECC computation logic enable bit */\n\n#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!< TCLR[3:0] bits (CLE to RE delay) */\n#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */\n#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */\n#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */\n#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!< Bit 3 */\n\n#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!< TAR[3:0] bits (ALE to RE delay) */\n#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!< Bit 0 */\n#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!< Bit 1 */\n#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!< Bit 2 */\n#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!< Bit 3 */\n\n#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!< ECCPS[2:0] bits (ECC page size) */\n#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!< Bit 0 */\n#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!< Bit 1 */\n#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!< Bit 2 */\n\n/*******************  Bit definition for FSMC_SR2 register  *******************/\n#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */\n#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */\n#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */\n#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */\n#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */\n\n/*******************  Bit definition for FSMC_SR3 register  *******************/\n#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */\n#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */\n#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */\n#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */\n#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */\n\n/*******************  Bit definition for FSMC_SR4 register  *******************/\n#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!< Interrupt Rising Edge status */\n#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!< Interrupt Level status */\n#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!< Interrupt Falling Edge status */\n#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!< Interrupt Rising Edge detection Enable bit */\n#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!< Interrupt Level detection Enable bit */\n#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!< Interrupt Falling Edge detection Enable bit */\n#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!< FIFO empty */\n\n/******************  Bit definition for FSMC_PMEM2 register  ******************/\n#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PMEM3 register  ******************/\n#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PMEM4 register  ******************/\n#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PATT2 register  ******************/\n#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PATT3 register  ******************/\n#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PATT4 register  ******************/\n#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_PIO4 register  *******************/\n#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!< IOSET4[7:0] bits (I/O 4 setup time) */\n#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!< Bit 0 */\n#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!< Bit 1 */\n#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!< Bit 2 */\n#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!< Bit 3 */\n#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!< Bit 4 */\n#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!< Bit 5 */\n#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!< Bit 6 */\n#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!< Bit 7 */\n\n#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!< Bit 0 */\n#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!< Bit 1 */\n#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!< Bit 2 */\n#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!< Bit 3 */\n#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!< Bit 4 */\n#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!< Bit 5 */\n#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!< Bit 6 */\n#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!< Bit 7 */\n\n#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!< Bit 7 */\n\n#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */\n#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */\n#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */\n#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!< Bit 3 */\n#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!< Bit 4 */\n#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!< Bit 5 */\n#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!< Bit 6 */\n#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!< Bit 7 */\n\n/******************  Bit definition for FSMC_ECCR2 register  ******************/\n#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */\n\n/******************  Bit definition for FSMC_ECCR3 register  ******************/\n#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!< ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */\n#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!< Bit 0 */\n#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!< Bit 1 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!< Clock divide factor */\n#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!< Clock enable bit */\n#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!< Power saving configuration bit */\n#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!< Clock divider bypass enable bit */\n\n#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!< Bit 0 */\n#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!< Bit 1 */\n\n#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!< SDIO_CK dephasing selection bit */\n#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!< HW Flow Control enable */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!< Command Index */\n\n#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */\n#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!<  Bit 0 */\n#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!<  Bit 1 */\n\n#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!< CPSM Waits for Interrupt Request */\n#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */\n#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!< SD I/O suspend command */\n#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!< Enable CMD completion */\n#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!< Not Interrupt Enable */\n#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!< CE-ATA command */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!< Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!< Data transfer enabled bit */\n#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!< Data transfer direction selection */\n#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!< Data transfer mode selection */\n#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!< DMA enabled bit */\n\n#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */\n#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!< Bit 1 */\n#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!< Bit 2 */\n#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!< Bit 3 */\n\n#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!< Read wait start */\n#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!< Read wait stop */\n#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!< Read wait mode */\n#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!< SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */\n#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */\n#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */\n#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */\n#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */\n#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */\n#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */\n#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */\n#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */\n#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */\n#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */\n#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */\n#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */\n#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */\n#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */\n#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */\n#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */\n#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */\n#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */\n#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */\n#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */\n#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */\n#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */\n#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */\n#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */\n#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */\n#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */\n#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */\n#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */\n#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */\n#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */\n#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */\n#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */\n#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */\n#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */\n#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */\n#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */\n#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */\n#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */\n#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */\n#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */\n#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */\n#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */\n#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */\n#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */\n#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */\n#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */\n#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */\n#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */\n#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */\n#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */\n#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */\n#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */\n#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */\n#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */\n#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */\n#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                   USB Device FS                            */\n/*                                                                            */\n/******************************************************************************/\n\n/*!< Endpoint-specific registers */\n/*******************  Bit definition for USB_EP0R register  *******************/\n#define  USB_EP0R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP0R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP0R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP0R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP0R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP0R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP0R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP0R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP0R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP0R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP0R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP0R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP0R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP0R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP0R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP0R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP1R register  *******************/\n#define  USB_EP1R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP1R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP1R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP1R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP1R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP1R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP1R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP1R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP1R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP1R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP1R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP1R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP1R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP1R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP1R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP1R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP2R register  *******************/\n#define  USB_EP2R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP2R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP2R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP2R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP2R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP2R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP2R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP2R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP2R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP2R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP2R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP2R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP2R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP2R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP2R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP2R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP3R register  *******************/\n#define  USB_EP3R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP3R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP3R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP3R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP3R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP3R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP3R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP3R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP3R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP3R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP3R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP3R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP3R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP3R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP3R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP3R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP4R register  *******************/\n#define  USB_EP4R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP4R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP4R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP4R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP4R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP4R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP4R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP4R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP4R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP4R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP4R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP4R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP4R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP4R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP4R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP4R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP5R register  *******************/\n#define  USB_EP5R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP5R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP5R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP5R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP5R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP5R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP5R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP5R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP5R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP5R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP5R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP5R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP5R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP5R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP5R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP5R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP6R register  *******************/\n#define  USB_EP6R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP6R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP6R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP6R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP6R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP6R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP6R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP6R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP6R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP6R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP6R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP6R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP6R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP6R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP6R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP6R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP7R register  *******************/\n#define  USB_EP7R_EA                         ((uint16_t)0x000F)            /*!< Endpoint Address */\n\n#define  USB_EP7R_STAT_TX                    ((uint16_t)0x0030)            /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define  USB_EP7R_STAT_TX_0                  ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  USB_EP7R_STAT_TX_1                  ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  USB_EP7R_DTOG_TX                    ((uint16_t)0x0040)            /*!< Data Toggle, for transmission transfers */\n#define  USB_EP7R_CTR_TX                     ((uint16_t)0x0080)            /*!< Correct Transfer for transmission */\n#define  USB_EP7R_EP_KIND                    ((uint16_t)0x0100)            /*!< Endpoint Kind */\n\n#define  USB_EP7R_EP_TYPE                    ((uint16_t)0x0600)            /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define  USB_EP7R_EP_TYPE_0                  ((uint16_t)0x0200)            /*!< Bit 0 */\n#define  USB_EP7R_EP_TYPE_1                  ((uint16_t)0x0400)            /*!< Bit 1 */\n\n#define  USB_EP7R_SETUP                      ((uint16_t)0x0800)            /*!< Setup transaction completed */\n\n#define  USB_EP7R_STAT_RX                    ((uint16_t)0x3000)            /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define  USB_EP7R_STAT_RX_0                  ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USB_EP7R_STAT_RX_1                  ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USB_EP7R_DTOG_RX                    ((uint16_t)0x4000)            /*!< Data Toggle, for reception transfers */\n#define  USB_EP7R_CTR_RX                     ((uint16_t)0x8000)            /*!< Correct Transfer for reception */\n\n/*!< Common registers */\n/*******************  Bit definition for USB_CNTR register  *******************/\n#define  USB_CNTR_FRES                       ((uint16_t)0x0001)            /*!< Force USB Reset */\n#define  USB_CNTR_PDWN                       ((uint16_t)0x0002)            /*!< Power down */\n#define  USB_CNTR_LP_MODE                    ((uint16_t)0x0004)            /*!< Low-power mode */\n#define  USB_CNTR_FSUSP                      ((uint16_t)0x0008)            /*!< Force suspend */\n#define  USB_CNTR_RESUME                     ((uint16_t)0x0010)            /*!< Resume request */\n#define  USB_CNTR_ESOFM                      ((uint16_t)0x0100)            /*!< Expected Start Of Frame Interrupt Mask */\n#define  USB_CNTR_SOFM                       ((uint16_t)0x0200)            /*!< Start Of Frame Interrupt Mask */\n#define  USB_CNTR_RESETM                     ((uint16_t)0x0400)            /*!< RESET Interrupt Mask */\n#define  USB_CNTR_SUSPM                      ((uint16_t)0x0800)            /*!< Suspend mode Interrupt Mask */\n#define  USB_CNTR_WKUPM                      ((uint16_t)0x1000)            /*!< Wakeup Interrupt Mask */\n#define  USB_CNTR_ERRM                       ((uint16_t)0x2000)            /*!< Error Interrupt Mask */\n#define  USB_CNTR_PMAOVRM                    ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun Interrupt Mask */\n#define  USB_CNTR_CTRM                       ((uint16_t)0x8000)            /*!< Correct Transfer Interrupt Mask */\n\n/*******************  Bit definition for USB_ISTR register  *******************/\n#define  USB_ISTR_EP_ID                      ((uint16_t)0x000F)            /*!< Endpoint Identifier */\n#define  USB_ISTR_DIR                        ((uint16_t)0x0010)            /*!< Direction of transaction */\n#define  USB_ISTR_ESOF                       ((uint16_t)0x0100)            /*!< Expected Start Of Frame */\n#define  USB_ISTR_SOF                        ((uint16_t)0x0200)            /*!< Start Of Frame */\n#define  USB_ISTR_RESET                      ((uint16_t)0x0400)            /*!< USB RESET request */\n#define  USB_ISTR_SUSP                       ((uint16_t)0x0800)            /*!< Suspend mode request */\n#define  USB_ISTR_WKUP                       ((uint16_t)0x1000)            /*!< Wake up */\n#define  USB_ISTR_ERR                        ((uint16_t)0x2000)            /*!< Error */\n#define  USB_ISTR_PMAOVR                     ((uint16_t)0x4000)            /*!< Packet Memory Area Over / Underrun */\n#define  USB_ISTR_CTR                        ((uint16_t)0x8000)            /*!< Correct Transfer */\n\n/*******************  Bit definition for USB_FNR register  ********************/\n#define  USB_FNR_FN                          ((uint16_t)0x07FF)            /*!< Frame Number */\n#define  USB_FNR_LSOF                        ((uint16_t)0x1800)            /*!< Lost SOF */\n#define  USB_FNR_LCK                         ((uint16_t)0x2000)            /*!< Locked */\n#define  USB_FNR_RXDM                        ((uint16_t)0x4000)            /*!< Receive Data - Line Status */\n#define  USB_FNR_RXDP                        ((uint16_t)0x8000)            /*!< Receive Data + Line Status */\n\n/******************  Bit definition for USB_DADDR register  *******************/\n#define  USB_DADDR_ADD                       ((uint8_t)0x7F)               /*!< ADD[6:0] bits (Device Address) */\n#define  USB_DADDR_ADD0                      ((uint8_t)0x01)               /*!< Bit 0 */\n#define  USB_DADDR_ADD1                      ((uint8_t)0x02)               /*!< Bit 1 */\n#define  USB_DADDR_ADD2                      ((uint8_t)0x04)               /*!< Bit 2 */\n#define  USB_DADDR_ADD3                      ((uint8_t)0x08)               /*!< Bit 3 */\n#define  USB_DADDR_ADD4                      ((uint8_t)0x10)               /*!< Bit 4 */\n#define  USB_DADDR_ADD5                      ((uint8_t)0x20)               /*!< Bit 5 */\n#define  USB_DADDR_ADD6                      ((uint8_t)0x40)               /*!< Bit 6 */\n\n#define  USB_DADDR_EF                        ((uint8_t)0x80)               /*!< Enable Function */\n\n/******************  Bit definition for USB_BTABLE register  ******************/    \n#define  USB_BTABLE_BTABLE                   ((uint16_t)0xFFF8)            /*!< Buffer Table */\n\n/*!< Buffer descriptor table */\n/*****************  Bit definition for USB_ADDR0_TX register  *****************/\n#define  USB_ADDR0_TX_ADDR0_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 0 */\n\n/*****************  Bit definition for USB_ADDR1_TX register  *****************/\n#define  USB_ADDR1_TX_ADDR1_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 1 */\n\n/*****************  Bit definition for USB_ADDR2_TX register  *****************/\n#define  USB_ADDR2_TX_ADDR2_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 2 */\n\n/*****************  Bit definition for USB_ADDR3_TX register  *****************/\n#define  USB_ADDR3_TX_ADDR3_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 3 */\n\n/*****************  Bit definition for USB_ADDR4_TX register  *****************/\n#define  USB_ADDR4_TX_ADDR4_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 4 */\n\n/*****************  Bit definition for USB_ADDR5_TX register  *****************/\n#define  USB_ADDR5_TX_ADDR5_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 5 */\n\n/*****************  Bit definition for USB_ADDR6_TX register  *****************/\n#define  USB_ADDR6_TX_ADDR6_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 6 */\n\n/*****************  Bit definition for USB_ADDR7_TX register  *****************/\n#define  USB_ADDR7_TX_ADDR7_TX               ((uint16_t)0xFFFE)            /*!< Transmission Buffer Address 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_COUNT0_TX register  ****************/\n#define  USB_COUNT0_TX_COUNT0_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 0 */\n\n/*****************  Bit definition for USB_COUNT1_TX register  ****************/\n#define  USB_COUNT1_TX_COUNT1_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 1 */\n\n/*****************  Bit definition for USB_COUNT2_TX register  ****************/\n#define  USB_COUNT2_TX_COUNT2_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 2 */\n\n/*****************  Bit definition for USB_COUNT3_TX register  ****************/\n#define  USB_COUNT3_TX_COUNT3_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 3 */\n\n/*****************  Bit definition for USB_COUNT4_TX register  ****************/\n#define  USB_COUNT4_TX_COUNT4_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 4 */\n\n/*****************  Bit definition for USB_COUNT5_TX register  ****************/\n#define  USB_COUNT5_TX_COUNT5_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 5 */\n\n/*****************  Bit definition for USB_COUNT6_TX register  ****************/\n#define  USB_COUNT6_TX_COUNT6_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 6 */\n\n/*****************  Bit definition for USB_COUNT7_TX register  ****************/\n#define  USB_COUNT7_TX_COUNT7_TX             ((uint16_t)0x03FF)            /*!< Transmission Byte Count 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/\n#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */\n\n/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/\n#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */\n\n/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/\n#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */\n\n/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/\n#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */\n\n/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/\n#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */\n\n/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/\n#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */\n\n/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/\n#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint16_t)0x000003FF)        /*!< Transmission Byte Count 3 (low) */\n\n/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/\n#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint16_t)0x03FF0000)        /*!< Transmission Byte Count 3 (high) */\n\n/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/\n#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */\n\n/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/\n#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */\n\n/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/\n#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */\n\n/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/\n#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */\n\n/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/\n#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */\n\n/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/\n#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */\n\n/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/\n#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */\n\n/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/\n#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_ADDR0_RX register  *****************/\n#define  USB_ADDR0_RX_ADDR0_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 0 */\n\n/*****************  Bit definition for USB_ADDR1_RX register  *****************/\n#define  USB_ADDR1_RX_ADDR1_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 1 */\n\n/*****************  Bit definition for USB_ADDR2_RX register  *****************/\n#define  USB_ADDR2_RX_ADDR2_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 2 */\n\n/*****************  Bit definition for USB_ADDR3_RX register  *****************/\n#define  USB_ADDR3_RX_ADDR3_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 3 */\n\n/*****************  Bit definition for USB_ADDR4_RX register  *****************/\n#define  USB_ADDR4_RX_ADDR4_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 4 */\n\n/*****************  Bit definition for USB_ADDR5_RX register  *****************/\n#define  USB_ADDR5_RX_ADDR5_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 5 */\n\n/*****************  Bit definition for USB_ADDR6_RX register  *****************/\n#define  USB_ADDR6_RX_ADDR6_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 6 */\n\n/*****************  Bit definition for USB_ADDR7_RX register  *****************/\n#define  USB_ADDR7_RX_ADDR7_RX               ((uint16_t)0xFFFE)            /*!< Reception Buffer Address 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_COUNT0_RX register  ****************/\n#define  USB_COUNT0_RX_COUNT0_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT0_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT0_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT1_RX register  ****************/\n#define  USB_COUNT1_RX_COUNT1_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT1_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT1_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT2_RX register  ****************/\n#define  USB_COUNT2_RX_COUNT2_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT2_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT2_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT3_RX register  ****************/\n#define  USB_COUNT3_RX_COUNT3_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT3_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT3_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT4_RX register  ****************/\n#define  USB_COUNT4_RX_COUNT4_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT4_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT4_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT5_RX register  ****************/\n#define  USB_COUNT5_RX_COUNT5_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT5_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT5_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT6_RX register  ****************/\n#define  USB_COUNT6_RX_COUNT6_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT6_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT6_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT7_RX register  ****************/\n#define  USB_COUNT7_RX_COUNT7_RX             ((uint16_t)0x03FF)            /*!< Reception Byte Count */\n\n#define  USB_COUNT7_RX_NUM_BLOCK             ((uint16_t)0x7C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint16_t)0x0400)            /*!< Bit 0 */\n#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint16_t)0x0800)            /*!< Bit 1 */\n#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint16_t)0x1000)            /*!< Bit 2 */\n#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint16_t)0x2000)            /*!< Bit 3 */\n#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint16_t)0x4000)            /*!< Bit 4 */\n\n#define  USB_COUNT7_RX_BLSIZE                ((uint16_t)0x8000)            /*!< BLock SIZE */\n\n/*----------------------------------------------------------------------------*/\n\n/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/\n#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/\n#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/\n#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/\n#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/\n#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/\n#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/\n#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/\n#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/\n#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/\n#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/\n#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/\n#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/\n#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/\n#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/\n#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */\n\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */\n#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */\n\n#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */\n\n/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/\n#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */\n\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */\n#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */\n\n#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n\n/*!< CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!< Initialization Request */\n#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!< Sleep Mode Request */\n#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!< Transmit FIFO Priority */\n#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!< Receive FIFO Locked Mode */\n#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!< No Automatic Retransmission */\n#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!< Automatic Wakeup Mode */\n#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!< Automatic Bus-Off Management */\n#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!< Time Triggered Communication Mode */\n#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!< CAN software master reset */\n\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!< Initialization Acknowledge */\n#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!< Sleep Acknowledge */\n#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!< Error Interrupt */\n#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!< Wakeup Interrupt */\n#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!< Sleep Acknowledge Interrupt */\n#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!< Transmit Mode */\n#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!< Receive Mode */\n#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!< Last Sample Point */\n#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!< CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!< Request Completed Mailbox0 */\n#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!< Transmission OK of Mailbox0 */\n#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!< Arbitration Lost for Mailbox0 */\n#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!< Transmission Error of Mailbox0 */\n#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!< Abort Request for Mailbox0 */\n#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!< Request Completed Mailbox1 */\n#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!< Transmission OK of Mailbox1 */\n#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!< Arbitration Lost for Mailbox1 */\n#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!< Transmission Error of Mailbox1 */\n#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!< Abort Request for Mailbox 1 */\n#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!< Request Completed Mailbox2 */\n#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!< Transmission OK of Mailbox 2 */\n#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!< Arbitration Lost for mailbox 2 */\n#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!< Transmission Error of Mailbox 2 */\n#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!< Abort Request for Mailbox 2 */\n#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!< Mailbox Code */\n\n#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!< TME[2:0] bits */\n#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!< Transmit Mailbox 0 Empty */\n#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!< Transmit Mailbox 1 Empty */\n#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!< Transmit Mailbox 2 Empty */\n\n#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!< LOW[2:0] bits */\n#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!< Lowest Priority Flag for Mailbox 0 */\n#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!< Lowest Priority Flag for Mailbox 1 */\n#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!< Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!< FIFO 0 Message Pending */\n#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!< FIFO 0 Full */\n#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!< FIFO 0 Overrun */\n#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!< Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!< FIFO 1 Message Pending */\n#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!< FIFO 1 Full */\n#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!< FIFO 1 Overrun */\n#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!< Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Empty Interrupt Enable */\n#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!< FIFO Message Pending Interrupt Enable */\n#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!< FIFO Full Interrupt Enable */\n#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!< FIFO Overrun Interrupt Enable */\n#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!< FIFO Message Pending Interrupt Enable */\n#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!< FIFO Full Interrupt Enable */\n#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!< FIFO Overrun Interrupt Enable */\n#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!< Error Warning Interrupt Enable */\n#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!< Error Passive Interrupt Enable */\n#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!< Bus-Off Interrupt Enable */\n#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!< Last Error Code Interrupt Enable */\n#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!< Error Interrupt Enable */\n#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!< Wakeup Interrupt Enable */\n#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!< Sleep Interrupt Enable */\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!< Error Warning Flag */\n#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!< Error Passive Flag */\n#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!< Bus-Off Flag */\n\n#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!< LEC[2:0] bits (Last Error Code) */\n#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!< Bit 0 */\n#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!< Bit 1 */\n#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!< Bit 2 */\n\n#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!< Least significant byte of the 9-bit Transmit Error Counter */\n#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!< Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!< Baud Rate Prescaler */\n#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!< Time Segment 1 */\n#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!< Time Segment 2 */\n#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!< Resynchronization Jump Width */\n#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!< Loop Back Mode (Debug) */\n#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!< Silent Mode */\n\n/*!< Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */\n#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */\n#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */\n#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */\n#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */\n#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */\n#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */\n#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */\n#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */\n#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */\n#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */\n#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */\n#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */\n#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */\n#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */\n#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */\n#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */\n#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */\n#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */\n#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */\n#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */\n#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */\n#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */\n#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */\n#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!< Transmit Mailbox Request */\n#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */\n#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */\n#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */\n#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/  \n#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */\n#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!< Transmit Global Time */\n#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */\n#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */\n#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */\n#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */\n#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */\n#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */\n#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */\n#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */\n#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended Identifier */\n#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */\n#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */\n#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */\n#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */\n#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */\n#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */\n#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */\n#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */\n#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!< Remote Transmission Request */\n#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!< Identifier Extension */\n#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!< Extended identifier */\n#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!< Data Length Code */\n#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!< Filter Match Index */\n#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!< Data byte 0 */\n#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!< Data byte 1 */\n#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!< Data byte 2 */\n#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!< Data byte 4 */\n#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!< Data byte 5 */\n#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!< Data byte 6 */\n#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!< Data byte 7 */\n\n/*!< CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!< Filter Init Mode */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!< Filter Mode */\n#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!< Filter Init Mode bit 0 */\n#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!< Filter Init Mode bit 1 */\n#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!< Filter Init Mode bit 2 */\n#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!< Filter Init Mode bit 3 */\n#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!< Filter Init Mode bit 4 */\n#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!< Filter Init Mode bit 5 */\n#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!< Filter Init Mode bit 6 */\n#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!< Filter Init Mode bit 7 */\n#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!< Filter Init Mode bit 8 */\n#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!< Filter Init Mode bit 9 */\n#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!< Filter Init Mode bit 10 */\n#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!< Filter Init Mode bit 11 */\n#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!< Filter Init Mode bit 12 */\n#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!< Filter Init Mode bit 13 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!< Filter Scale Configuration */\n#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!< Filter Scale Configuration bit 0 */\n#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!< Filter Scale Configuration bit 1 */\n#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!< Filter Scale Configuration bit 2 */\n#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!< Filter Scale Configuration bit 3 */\n#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!< Filter Scale Configuration bit 4 */\n#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!< Filter Scale Configuration bit 5 */\n#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!< Filter Scale Configuration bit 6 */\n#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!< Filter Scale Configuration bit 7 */\n#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!< Filter Scale Configuration bit 8 */\n#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!< Filter Scale Configuration bit 9 */\n#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!< Filter Scale Configuration bit 10 */\n#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!< Filter Scale Configuration bit 11 */\n#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!< Filter Scale Configuration bit 12 */\n#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!< Filter Scale Configuration bit 13 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!< Filter FIFO Assignment */\n#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!< Filter FIFO Assignment for Filter 0 */\n#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!< Filter FIFO Assignment for Filter 1 */\n#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!< Filter FIFO Assignment for Filter 2 */\n#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!< Filter FIFO Assignment for Filter 3 */\n#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!< Filter FIFO Assignment for Filter 4 */\n#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!< Filter FIFO Assignment for Filter 5 */\n#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!< Filter FIFO Assignment for Filter 6 */\n#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!< Filter FIFO Assignment for Filter 7 */\n#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!< Filter FIFO Assignment for Filter 8 */\n#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!< Filter FIFO Assignment for Filter 9 */\n#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!< Filter FIFO Assignment for Filter 10 */\n#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!< Filter FIFO Assignment for Filter 11 */\n#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!< Filter FIFO Assignment for Filter 12 */\n#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!< Filter FIFO Assignment for Filter 13 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!< Filter Active */\n#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!< Filter 0 Active */\n#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!< Filter 1 Active */\n#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!< Filter 2 Active */\n#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!< Filter 3 Active */\n#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!< Filter 4 Active */\n#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!< Filter 5 Active */\n#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!< Filter 6 Active */\n#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!< Filter 7 Active */\n#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!< Filter 8 Active */\n#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!< Filter 9 Active */\n#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!< Filter 10 Active */\n#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!< Filter 11 Active */\n#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!< Filter 12 Active */\n#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!< Filter 13 Active */\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!< Filter bit 0 */\n#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!< Filter bit 1 */\n#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!< Filter bit 2 */\n#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!< Filter bit 3 */\n#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!< Filter bit 4 */\n#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!< Filter bit 5 */\n#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!< Filter bit 6 */\n#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!< Filter bit 7 */\n#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!< Filter bit 8 */\n#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!< Filter bit 9 */\n#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!< Filter bit 10 */\n#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!< Filter bit 11 */\n#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!< Filter bit 12 */\n#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!< Filter bit 13 */\n#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!< Filter bit 14 */\n#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!< Filter bit 15 */\n#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!< Filter bit 16 */\n#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!< Filter bit 17 */\n#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!< Filter bit 18 */\n#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!< Filter bit 19 */\n#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!< Filter bit 20 */\n#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!< Filter bit 21 */\n#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!< Filter bit 22 */\n#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!< Filter bit 23 */\n#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!< Filter bit 24 */\n#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!< Filter bit 25 */\n#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!< Filter bit 26 */\n#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!< Filter bit 27 */\n#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!< Filter bit 28 */\n#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!< Filter bit 29 */\n#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!< Filter bit 30 */\n#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!< Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */\n#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */\n#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */\n\n#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */\n#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */\n#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */\n#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */\n\n#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */\n#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */\n#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */\n#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */\n#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */\n#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!< Data Frame Format */\n#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */\n#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */\n#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */\n#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!< Rx Buffer DMA Enable */\n#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!< Tx Buffer DMA Enable */\n#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!< SS Output Enable */\n#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!< Error Interrupt Enable */\n#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!< RX buffer Not Empty Interrupt Enable */\n#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!< Tx buffer Empty Interrupt Enable */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!< Receive buffer Not Empty */\n#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!< Transmit buffer Empty */\n#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!< Channel side */\n#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!< Underrun flag */\n#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!< CRC Error flag */\n#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!< Mode fault */\n#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!< Overrun flag */\n#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!< Busy flag */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!< Channel length (number of bits per audio channel) */\n\n#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!< DATLEN[1:0] bits (Data length to be transferred) */\n#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!< Bit 0 */\n#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!< Bit 1 */\n\n#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!< steady state clock polarity */\n\n#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!< I2SSTD[1:0] bits (I2S standard selection) */\n#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!< Bit 0 */\n#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!< Bit 1 */\n\n#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!< PCM frame synchronization */\n\n#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!< I2SCFG[1:0] bits (I2S configuration mode) */\n#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!< Bit 0 */\n#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!< Bit 1 */\n\n#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!< I2S Enable */\n#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!< I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!< I2S Linear prescaler */\n#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!< Odd factor for the prescaler */\n#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!< Master Clock Output Enable */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!< Peripheral Enable */\n#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!< SMBus Mode */\n#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!< SMBus Type */\n#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!< ARP Enable */\n#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!< PEC Enable */\n#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!< General Call Enable */\n#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!< Clock Stretching Disable (Slave mode) */\n#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!< Start Generation */\n#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!< Stop Generation */\n#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!< Acknowledge Enable */\n#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!< Acknowledge/PEC Position (for data reception) */\n#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!< Packet Error Checking */\n#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!< SMBus Alert */\n#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!< Software Reset */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\n#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!< Bit 5 */\n\n#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!< Error Interrupt Enable */\n#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!< Event Interrupt Enable */\n#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!< Buffer Interrupt Enable */\n#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!< DMA Requests Enable */\n#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!< DMA Last Transfer */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!< Interface Address */\n#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!< Interface Address */\n\n#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!< Bit 5 */\n#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!< Bit 6 */\n#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!< Bit 7 */\n#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!< Bit 8 */\n#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!< Bit 9 */\n\n#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!< Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!< Dual addressing mode enable */\n#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!< Interface address */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!< 8-bit Data Register */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!< Start Bit (Master mode) */\n#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!< Address sent (master mode)/matched (slave mode) */\n#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!< Byte Transfer Finished */\n#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!< 10-bit header sent (Master mode) */\n#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!< Stop detection (Slave mode) */\n#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!< Data Register not Empty (receivers) */\n#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!< Data Register Empty (transmitters) */\n#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!< Bus Error */\n#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!< Arbitration Lost (master mode) */\n#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!< Acknowledge Failure */\n#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!< Overrun/Underrun */\n#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!< PEC Error in reception */\n#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!< Timeout or Tlow Error */\n#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!< SMBus Alert */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!< Master/Slave */\n#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!< Bus Busy */\n#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!< Transmitter/Receiver */\n#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!< General Call Address (Slave mode) */\n#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!< SMBus Device Default Address (Slave mode) */\n#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!< SMBus Host Header (Slave mode) */\n#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!< Dual Flag (Slave mode) */\n#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!< Packet Error Checking Register */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */\n#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!< Fast Mode Duty Cycle */\n#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!< I2C Master Mode Selection */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for USART_SR register  *******************/\n#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!< Parity Error */\n#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!< Framing Error */\n#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!< Noise Error Flag */\n#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!< OverRun Error */\n#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!< IDLE line detected */\n#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!< Read Data Register Not Empty */\n#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!< Transmission Complete */\n#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!< Transmit Data Register Empty */\n#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!< LIN Break Detection Flag */\n#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!< CTS Flag */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!< Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!< Fraction of USARTDIV */\n#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!< Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!< Send Break */\n#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!< Receiver wakeup */\n#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!< Receiver Enable */\n#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!< Transmitter Enable */\n#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!< IDLE Interrupt Enable */\n#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!< RXNE Interrupt Enable */\n#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!< Transmission Complete Interrupt Enable */\n#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!< PE Interrupt Enable */\n#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!< PE Interrupt Enable */\n#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!< Parity Selection */\n#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!< Parity Control Enable */\n#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!< Wakeup method */\n#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!< Word length */\n#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!< USART Enable */\n#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!< USART Oversmapling 8-bits */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!< Address of the USART node */\n#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!< LIN Break Detection Length */\n#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!< LIN Break Detection Interrupt Enable */\n#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!< Last Bit Clock pulse */\n#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!< Clock Phase */\n#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!< Clock Polarity */\n#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!< Clock Enable */\n\n#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!< STOP[1:0] bits (STOP bits) */\n#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!< Bit 0 */\n#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!< Bit 1 */\n\n#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!< LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!< Error Interrupt Enable */\n#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!< IrDA mode Enable */\n#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!< IrDA Low-Power */\n#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!< Half-Duplex Selection */\n#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!< Smartcard NACK enable */\n#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!< Smartcard mode enable */\n#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!< DMA Enable Receiver */\n#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!< DMA Enable Transmitter */\n#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!< RTS Enable */\n#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!< CTS Enable */\n#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!< CTS Interrupt Enable */\n#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!< One Bit method */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!< PSC[7:0] bits (Prescaler value) */\n#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!< Bit 0 */\n#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!< Bit 1 */\n#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!< Bit 2 */\n#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!< Bit 3 */\n#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!< Bit 4 */\n#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!< Bit 5 */\n#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!< Bit 6 */\n#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!< Bit 7 */\n\n#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!< Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 Debug MCU                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************  Bit definition for DBGMCU_IDCODE register  *****************/\n#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */\n\n#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */\n#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */\n#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */\n#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */\n#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */\n#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */\n#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */\n#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */\n#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */\n#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */\n#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */\n#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */\n#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */\n#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */\n#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */\n#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */\n#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */\n\n/******************  Bit definition for DBGMCU_CR register  *******************/\n#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */\n#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */\n#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */\n#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */\n\n#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\n#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */\n#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */\n\n#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */\n#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_CAN1_STOP             ((uint32_t)0x00004000)        /*!< Debug CAN1 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */\n#define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM8_STOP             ((uint32_t)0x00020000)        /*!< TIM8 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM5_STOP             ((uint32_t)0x00040000)        /*!< TIM5 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM6_STOP             ((uint32_t)0x00080000)        /*!< TIM6 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_TIM7_STOP             ((uint32_t)0x00100000)        /*!< TIM7 counter stopped when core is halted */\n#define  DBGMCU_CR_DBG_CAN2_STOP             ((uint32_t)0x00200000)        /*!< Debug CAN2 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM12_STOP            ((uint32_t)0x02000000)        /*!< Debug TIM12 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM13_STOP            ((uint32_t)0x04000000)        /*!< Debug TIM13 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM14_STOP            ((uint32_t)0x08000000)        /*!< Debug TIM14 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM9_STOP             ((uint32_t)0x10000000)        /*!< Debug TIM9 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM10_STOP            ((uint32_t)0x20000000)        /*!< Debug TIM10 stopped when Core is halted */\n#define  DBGMCU_CR_DBG_TIM11_STOP            ((uint32_t)0x40000000)        /*!< Debug TIM11 stopped when Core is halted */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      FLASH and Option Bytes Registers                      */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for FLASH_ACR register  ******************/\n#define  FLASH_ACR_LATENCY                   ((uint8_t)0x03)               /*!< LATENCY[2:0] bits (Latency) */\n#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x00)               /*!< Bit 0 */\n#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x01)               /*!< Bit 0 */\n#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x02)               /*!< Bit 1 */\n\n#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!< Flash Half Cycle Access Enable */\n#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!< Prefetch Buffer Enable */\n#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!< Prefetch Buffer Status */\n\n/******************  Bit definition for FLASH_KEYR register  ******************/\n#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */\n\n/******************  FLASH Keys  **********************************************/\n#define RDP_Key                  ((uint16_t)0x00A5)\n#define FLASH_KEY1               ((uint32_t)0x45670123)\n#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)\n\n/*****************  Bit definition for FLASH_OPTKEYR register  ****************/\n#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */\n\n/******************  Bit definition for FLASH_SR register  *******************/\n#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!< Busy */\n#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!< Programming Error */\n#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!< Write Protection Error */\n#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!< End of operation */\n\n/*******************  Bit definition for FLASH_CR register  *******************/\n#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!< Programming */\n#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!< Page Erase */\n#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!< Mass Erase */\n#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!< Option Byte Programming */\n#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!< Option Byte Erase */\n#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!< Start */\n#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!< Lock */\n#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!< Option Bytes Write Enable */\n#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!< Error Interrupt Enable */\n#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!< End of operation interrupt enable */\n\n/*******************  Bit definition for FLASH_AR register  *******************/\n#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */\n\n/******************  Bit definition for FLASH_OBR register  *******************/\n#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!< Option Byte Error */\n#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!< Read protection */\n\n#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!< User Option Bytes */\n#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!< WDG_SW */\n#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!< nRST_STOP */\n#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!< nRST_STDBY */\n#define  FLASH_OBR_BFB2                      ((uint16_t)0x0020)            /*!< BFB2 */\n\n/******************  Bit definition for FLASH_WRPR register  ******************/\n#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */\n\n/*----------------------------------------------------------------------------*/\n\n/******************  Bit definition for FLASH_RDP register  *******************/\n#define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */\n#define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */\n\n/******************  Bit definition for FLASH_USER register  ******************/\n#define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */\n#define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */\n\n/******************  Bit definition for FLASH_Data0 register  *****************/\n#define  FLASH_Data0_Data0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */\n#define  FLASH_Data0_nData0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */\n\n/******************  Bit definition for FLASH_Data1 register  *****************/\n#define  FLASH_Data1_Data1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */\n#define  FLASH_Data1_nData1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */\n\n/******************  Bit definition for FLASH_WRP0 register  ******************/\n#define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */\n#define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP1 register  ******************/\n#define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */\n#define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP2 register  ******************/\n#define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */\n#define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP3 register  ******************/\n#define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */\n#define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */\n\n#ifdef STM32F10X_CL\n/******************************************************************************/\n/*                Ethernet MAC Registers bits definitions                     */\n/******************************************************************************/\n/* Bit definition for Ethernet MAC Control Register register */\n#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */\n#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */\n#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */\n  #define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */\n  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */\n  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */\n  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */\n  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        \n  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */\n  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */\n  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              \n#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */\n#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */\n#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */\n#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */\n#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */\n#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */\n#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */\n#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */\n#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\n  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */\n  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */\n  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */\n  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ \n#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */\n#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */\n#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */\n\n/* Bit definition for Ethernet MAC Frame Filter Register */\n#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ \n#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ \n#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ \n#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ \n#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */\n  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */\n  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */\n  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ \n#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ \n#define ETH_MACFFR_PAM \t  ((uint32_t)0x00000010)  /* Pass all mutlicast */ \n#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ \n#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ \n#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */\n#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */\n\n/* Bit definition for Ethernet MAC Hash Table High Register */\n#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */\n\n/* Bit definition for Ethernet MAC Hash Table Low Register */\n#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */\n\n/* Bit definition for Ethernet MAC MII Address Register */\n#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ \n#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ \n#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ \n  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-72 MHz; MDC clock= HCLK/42 */\n  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\n  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\n#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ \n#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ \n  \n/* Bit definition for Ethernet MAC MII Data Register */\n#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */\n\n/* Bit definition for Ethernet MAC Flow Control Register */\n#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */\n#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */\n#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */\n  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */\n  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */\n  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */\n  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      \n#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */\n#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */\n#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */\n#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */\n\n/* Bit definition for Ethernet MAC VLAN Tag Register */\n#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */\n#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */\n\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \n#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \n                              RSVD - Filter1 Command - RSVD - Filter0 Command\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\n\n/* Bit definition for Ethernet MAC PMT Control and Status Register */ \n#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */\n#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */\n#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */\n#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */\n#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */\n#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */\n#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */\n\n/* Bit definition for Ethernet MAC Status Register */\n#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */\n#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */\n#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */\n#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */\n#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */\n\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\n#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */\n#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */\n\n/* Bit definition for Ethernet MAC Address0 High Register */\n#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */\n\n/* Bit definition for Ethernet MAC Address0 Low Register */\n#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */\n\n/* Bit definition for Ethernet MAC Address1 High Register */\n#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */\n#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */\n#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\n  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\n  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\n  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\n  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\n  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\n  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ \n#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address1 Low Register */\n#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */\n\n/* Bit definition for Ethernet MAC Address2 High Register */\n#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */\n#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */\n#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */\n  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\n  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\n  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\n  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\n  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\n  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */\n#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address2 Low Register */\n#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */\n\n/* Bit definition for Ethernet MAC Address3 High Register */\n#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */\n#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */\n#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */\n  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\n  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\n  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\n  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\n  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\n  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */\n#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */\n\n/* Bit definition for Ethernet MAC Address3 Low Register */\n#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */\n\n/******************************************************************************/\n/*                Ethernet MMC Registers bits definition                      */\n/******************************************************************************/\n\n/* Bit definition for Ethernet MMC Contol Register */\n#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */\n#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */\n#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */\n#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\n#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\n#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\n#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\n#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\n#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\n#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\n#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */\n\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\n#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */\n\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\n#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */\n\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\n#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */\n\n/******************************************************************************/\n/*               Ethernet PTP Registers bits definition                       */\n/******************************************************************************/\n\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\n#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */\n#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */\n#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */\n#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */\n#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */\n#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */\n\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\n#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */\n\n/* Bit definition for Ethernet PTP Time Stamp High Register */\n#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\n#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */\n#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\n#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\n#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */\n#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\n#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */\n\n/* Bit definition for Ethernet PTP Target Time High Register */\n#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */\n\n/* Bit definition for Ethernet PTP Target Time Low Register */\n#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */\n\n/******************************************************************************/\n/*                 Ethernet DMA Registers bits definition                     */\n/******************************************************************************/\n\n/* Bit definition for Ethernet DMA Bus Mode Register */\n#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */\n#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */\n#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */\n#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */\n  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\n  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\n  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                \n  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\n  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  \n#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */\n#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */\n  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */\n  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */\n  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */\n  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  \n#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */\n  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\n  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\n  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \n  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\n  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\n#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */\n#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */\n#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */\n\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\n#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */\n\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\n#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */\n\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\n#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */\n\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\n#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */\n\n/* Bit definition for Ethernet DMA Status Register */\n#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */\n#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */\n#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */\n#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */\n  /* combination with EBS[2:0] for GetFlagStatus function */\n  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */\n  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */\n  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */\n#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */\n  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */\n  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */\n  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */\n  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */\n  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */\n  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */\n#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */\n  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */\n  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */\n  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */\n  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */\n  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */\n  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */\n#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */\n#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */\n#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */\n#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */\n#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */\n#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */\n#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */\n#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */\n#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */\n#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */\n#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */\n#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */\n#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */\n#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */\n#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */\n\n/* Bit definition for Ethernet DMA Operation Mode Register */\n#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */\n#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */\n#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */\n#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */\n#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */\n#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */\n  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */\n  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */\n  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */\n  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */\n  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */\n  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */\n  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */\n  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */\n#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */\n#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */\n#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */\n#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */\n  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */\n  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */\n  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */\n  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */\n#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */\n#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */\n\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\n#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */\n#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */\n#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */\n#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */\n#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */\n#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */\n#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */\n#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */\n#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */\n#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */\n#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */\n#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */\n#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */\n#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */\n#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */\n\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\n#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */\n#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */\n#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */\n#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\n#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\n#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\n#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\n#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */\n#endif /* STM32F10X_CL */\n\n/**\n  * @}\n  */\n\n /**\n  * @}\n  */ \n\n#ifdef USE_STDPERIPH_DRIVER\n  #include \"stm32f10x_conf.h\"\n#endif\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F10x_H */\n\n/**\n  * @}\n  */\n\n  /**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "Libraries/CMSIS/Device/ST/STM32F10x/Include/system_stm32f10x.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f10x.h\n  * @author  MCD Application Team\n  * @version V3.6.1\n  * @date    09-March-2012\n  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\n  ******************************************************************************\n  * @attention\n  *\n  * 
© COPYRIGHT 2012 STMicroelectronics
\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f10x_system\n  * @{\n  */  \n  \n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F10X_H\n#define __SYSTEM_STM32F10X_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup STM32F10x_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F10x_System_Exported_types\n  * @{\n  */\n\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Functions\n  * @{\n  */\n  \nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F10X_H */\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */  \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "Libraries/CMSIS/Device/ST/STM32F10x/Release_Notes.html",
    "content": "\n\n\n\n\n\n\n\n\n\n\n\nRelease Notes for STM32F10x CMSIS\n\n\n\n\n\n
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Release\nNotes for STM32F10x CMSIS
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Copyright 2012 STMicroelectronics
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Contents
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    \n
  1. STM32F10x CMSIS\nupdate History
    2. \n
  2. License
    3. \n
\n\n
STM32F10x CMSIS\nupdate History
V3.6.1 / 09-March-2012
\n            
Main\nChanges
\n\n            
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
V3.6.0 / 27-January-2012
\n            
Main\nChanges
\n\n            
  • Update directory structure to be compliant with CMSIS V2.1
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f10x.h
    • Add define for Cortex-M3 revision __CM3_REV
    • Allow\nmodification of some constants by the application code, definition of\nthese constants is now bracketed by              #if !defined. The concerned constant are HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT
    • Add missing bits definition for DAC CR register
    • Add missing bits definition for FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4 registers
    • Definition for Flash keys moved from stm32f10x_flash.c to stm32f10x.h
  • Add startup file for TASKING toolchain
  • V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1) compatibility update
    • Due to the  directory structure difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to V3.6.0 you need to perform the following update:
      • In\nthe compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3\nCMSIS files are included by default in your development toolchain
      • Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler
      • In the compiler preprocessor, update path of STM32F10x CMSIS include files from  Libraries\\CMSIS\\CM3\\DeviceSupport\\ST\\STM32F10x to Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Include
      • In the project settings, update path of startup_stm32f10x_xx.s file from Libraries\\CMSIS\\CM3\\DeviceSupport\\ST\\STM32F10x\\startup\\”Compiler” to Libraries\\CMSIS\\Device\\ST\\STM32F10x\\Source\\Templates\\”Compiler”
where, \"Compiler\" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO
\n            
V3.5.0 / 11-March-2011
\n            
Main\nChanges
\n\n            
    \n
  • stm32f10x.h\nand startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt\ndefinition for STM32F10x High-density Value line devices.
    \n
    • \n              
  • system_stm32f10x.c file provided within the CMSIS folder. 
    \n
    • \n\n            
\n\n            
3.4.0\n- 10/15/2010
\n\n            
    \n
  1. General
    2. \n            
\n\n            
    \n              
  • Add support\nfor STM32F10x High-density Value line devices.
    • \n            
\n            
    \n              
  1. STM32F10x CMSIS Device Peripheral Access Layer 
    2. \n            
\n\n\n            \n            
    \n
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    \n              
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
        • \n                  
      • RCC, AFIO, FSMC bits definition updated
        • \n
      \n                
    • \n\n                  All\nSTM32 devices definitions are commented by default. User has to select the\nappropriate device before starting else an error will be signaled on compile\ntime.
      • \n                
    • Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.
      • \n                
    • \"bool\" type removed.
      \n                  
      • \n
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    \n                
    • \n              
      \n
    • \"system_stm32f10x.c\" moved to to \"STM32F10x_StdPeriph_Template\" directory. This file is also moved to each example directory under \"STM32F10x_StdPeriph_Examples\".
      \n
      • \n                
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • \n                
    • Add \"VECT_TAB_SRAM\" inside \"system_stm32f10x.c\"\nto select if the user want to place the Vector Table in internal SRAM.\nAn additional define is also to specify the Vector Table offset \"VECT_TAB_OFFSET\".
      \n                  
      • \n\n              
    \n
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three\nstartup files for STM32 High-density Value line devices:\n                  startup_stm32f10x_hd_vl.s
    \n            
\n            
3.3.0\n- 04/16/2010
\n\n
  1. General
\n
  • Add support\nfor STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer 
\n\n            
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    \n              
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma \",\" at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    \n                
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      \n                  
  • STM32F10x CMSIS startup files:
    • add three\nstartup files for STM32 XL-density devices:\n                  startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
\n
3.2.0\n- 03/01/2010
\n
    \n
  1. General
    2. \n
\n
    \n\n              
  • STM32F10x CMSIS files updated to CMSIS V1.30 release
    • \n              
  • Directory structure updated to be aligned with CMSIS V1.30
    \n                
    • \n              
  • Add support\nfor STM32 Low-density Value line (STM32F100x4/6) and\nMedium-density Value line (STM32F100x8/B) devices. 
    • \n\n
\n
    \n
  1. CMSIS Core Peripheral Access Layer
\n            \n            
    \n              
  1. STM32F10x CMSIS Device Peripheral Access Layer 
    2. \n\n            
\n\n            
    \n\n              
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    \n              
    • \n              
      \n                
    • Update\nthe stm32f10x.h file to support new Value line devices features: CEC\nperipheral, new General purpose timers TIM15, TIM16 and TIM17.
      • \n                
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      \n                  
      • \n                
    • HSE_Value,\nHSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,\nHSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy\npurposes.
      \n                  
      • \n              
    \n              
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    \n                
    • \n              
      \n                
    • SystemFrequency variable name changed to SystemCoreClock
      \n                  
      • \n                
    • Default\n                  SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices. 
      \n                  
      • \n                
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      \n                  
      • \n                
    • Additional function void SystemCoreClockUpdate (void) is provided.
      \n                  
      • \n              
    \n              
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • \n              
      \n                
    • Add new\nstartup files for STM32 Low-density Value line devices:\n                  startup_stm32f10x_ld_vl.s
      • \n                
    • Add new startup\nfiles for STM32 Medium-density Value line devices:\n                  startup_stm32f10x_md_vl.s
      • \n                
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      \nTo reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file 
      \n
      • \n                
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      \n
      • \n              
    \n\n            
\n\n
    \n
\n
License
\n
Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless\nrequired by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS, 
WITHOUT\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\nthe License for the specific language governing permissions and\nlimitations under the License.\n
\n
\n
For\ncomplete documentation on STM32 Microcontrollers\nvisit www.st.com/STM32
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/_c_o_r_e__m_i_s_r_a__exceptions_pg.html",
    "content": "\n\n\n\n\nCMSIS-CORE: MISRA-C:2004 Compliance Exceptions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE support for Cortex-M processor-based devices
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MISRA-C:2004 Compliance Exceptions 
  
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CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction .
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CMSIS-CORE violates the following MISRA-C:2004 rules:
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  • Required Rule 8.5, object/function definition in header file.
    \n Violated since function definitions in header files are used to allow 'inlining'.
    • \n
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  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    \n Violated since unions are used for effective representation of core registers.
    • \n
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  • Advisory Rule 19.7, Function-like macro defined.
    \n Violated since function-like macros are used to allow more efficient code. 
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/_reg_map_pg.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Register Mapping\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE support for Cortex-M processor-based devices
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Register Mapping 
  
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The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
CMSIS Register Name Cortex-M3 and Cortex-M4 Cortex-M0 and Cortex-M0+ Register Name  
Nested Vectored Interrupt Controller (NVIC) Register Access  
NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers  
NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers  
NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers  
NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers  
NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register  
NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register  
NVIC->STIR STIR - Software Triggered Interrupt Register  
System Control Block (SCB) Register Access  
SCB->CPUID CPUID CPUID CPUID Base Register  
SCB->ICSR ICSR ICSR Interrupt Control and State Register  
SCB->VTOR VTOR - Vector Table Offset Register  
SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register  
SCB->SCR SCR SCR System Control Register  
SCB->CCR CCR CCR Configuration and Control Register  
SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers  
SCB->SHCSR SHCSR SHCSR System Handler Control and State Register  
SCB->CFSR CFSR - Configurable Fault Status Registers  
SCB->HFSR HFSR - HardFault Status Register  
SCB->DFSR DFSR - Debug Fault Status Register  
SCB->MMFAR MMFAR - MemManage Fault Address Register  
SCB->BFAR BFAR - BusFault Address Register  
SCB->AFSR AFSR - Auxiliary Fault Status Register  
SCB->PFR[] ID_PFR0..1 - Processor Feature Registers  
SCB->DFR ID_DFR0 - Debug Feature Register  
SCB->ADR ID_AFR0 - Auxiliary Feature Register  
SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers  
SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers  
SCB->CPACR CPACR - Coprocessor Access Control Register  
System Control and ID Registers not in the SCB (SCnSCB) Register Access  
SCnSCB->ICTR ICTR - Interrupt Controller Type Register  
SCnSCB->ACTLR ACTLR - Auxiliary Control Register  
System Timer (SysTick) Control and Status Register Access  
SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register  
SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register  
SysTick->VAL STCVR SYST_CVR SysTick Current Value Register  
SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register  
Data Watchpoint and Trace (DWT) Register Access  
DWT->CTRL DWT_CTRL - Control Register  
DWT->CYCCNT DWT_CYCCNT - Cycle Count Register  
DWT->CPICNT DWT_CPICNT - CPI Count Register  
DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register  
DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register  
DWT->LSUCNT DWT_LSUCNT - LSU Count Register  
DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register  
DWT->PCSR DWT_PCSR - Program Counter Sample Register  
DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3  
DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3  
DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3  
Instrumentation Trace Macrocell (ITM) Register Access  
ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers  
ITM->TER ITM_TER - Trace Enable Register  
ITM->TPR ITM_TPR - ITM Trace Privilege Register  
ITM->TCR ITM_TCR - Trace Control Register  
Trace Port Interface (TPIU) Register Access  
TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register  
TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register  
TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register  
TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register  
TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register  
TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register  
TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register  
TPI->TRIGGER TRIGGER - TRIGGER  
TPI->FIFO0 FIFO data 0 - Integration ETM Data  
TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2  
TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0  
TPI->FIFO1 FIFO data 1 - Integration ITM Data  
TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control  
TPI->CLAIMSET CLAIMSET - Claim tag set  
TPI->CLAIMCLR CLAIMCLR - Claim tag clear  
TPI->DEVID TPIU_DEVID - TPIU_DEVID  
TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE  
Memory Protection Unit (MPU) Register Access  
MPU->TYPE MPU_TYPE - MPU Type Register  
MPU->CTRL MPU_CTRL - MPU Control Register  
MPU->RNR MPU_RNR - MPU Region Number Register  
MPU->RBAR MPU_RBAR - MPU Region Base Address Register  
MPU->RASR MPU_RASR - MPU Region Attribute and Size Register  
MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register  
MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register  
Floating Point Unit (FPU) Register Access [only Cortex-M4 with FPU]  
FPU->FPCCR FPCCR - FP Context Control Register  
FPU->FPCAR FPCAR - FP Context Address Register  
FPU->FPDSCR FPDSCR - FP Default Status Control Register  
FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers  
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    "content": "\n\n\n\n\nCMSIS-CORE: Template Files\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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Template Files 
  
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ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliancy. These template files include the following:
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  • Register names of the Core Peripherals and names of the Core Exception Vectors.
    • \n
  • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4)
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  • Generic startup code and system configuration code.
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The detailed file structure of the CMSIS-CORE is shown in the following picture.
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\n\"CMSIS_CORE_Files.png\"/\n
\nCMSIS-CORE File Structure
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\nTemplate Files
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The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:
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    \n
  • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
    • \n
  • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
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  • Interrupt vectors in the startup file that are device specific.
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Template File Description  
\".\\Device_Template_Vendor\\Vendor\\Device\\Source\\ARM\\startup_Device.s\" Startup file template for ARM C/C++ Compiler.  
\".\\Device_Template_Vendor\\Vendor\\Device\\Source\\GCC\\startup_Device.s\" Startup file template for GNU GCC ARM Embedded Compiler.  
\".\\Device_Template_Vendor\\Vendor\\Device\\Source\\G++\\startup_Device.s\" Startup file template for GNU Sourcery G++ Compiler.  
\".\\Device_Template_Vendor\\Vendor\\Device\\Source\\IAR\\startup_Device.s\" Startup file template for IAR C/C++ Compiler.  
\".\\Device_Template_Vendor\\Vendor\\Device\\Source\\system_Device.c\" Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).  
\".\\Device_Template_Vendor\\Vendor\\Device\\Include\\Device.h\" Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.  
\".\\Device_Template_Vendor\\Vendor\\Device\\Include\\system_Device.h\" Generic system device configuration include file.  
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In addition ARM provides the following core header files that do not need any modifications.
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Core Header Files Description  
core_<cpu>.h Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
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  • core_cm0.h: for the Cortex-M0 processor
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  • core_cm0plus.h: for the Cortex-M0+ processor
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  • core_cm3.h: for the Cortex-M0 processor
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  • core_cm4.h: for the Cortex-M0 processor
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  • core_sc000.h: for the SecurCore SC000 processor
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  • core_sc300.h: for the SecurCore SC300 processor   
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core_cmInstr.h Defines intrinsic functions to access special Cortex-M instructions.  
core_cmFunc.h Defines functions to access the Cortex-M core peripherals.  
core_cm4_simd.h Defines intrinsic functions to access the Cortex-M4 SIMD instructions.  
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\nAdaption of Template Files to Devices
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Copy the complete folder including files and replace:
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  • folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
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  • folder name 'Device' with the specific device name e.g.: LPC17xx.
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  • in the filenames 'Device' with the specific device name e.g.: LPC17xx.
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Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:
\n\n\n\n\n\n\n\n\n\n\n\n
Placeholder Replaced with  
<Device> the specific device name or device family name; i.e. LPC17xx.  
<DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1. 
<DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.  
Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.  
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The adaption of the template files is described in detail on the following pages:
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    "content": "var _templates_pg =\n[\n    [ \"Template Files\", \"_templates_pg.html#template_files_sec\", null ],\n    [ \"Adaption of Template Files to Devices\", \"_templates_pg.html#adapt_template_files_sec\", null ],\n    [ \"Startup File startup_.s\", \"startup_s_pg.html\", [\n      [ \"startup_Device.s Template File\", \"startup_s_pg.html#startup_s_sec\", null ]\n    ] ],\n    [ \"System Configuration Files system_.c and system_.h\", \"system_c_pg.html\", [\n      [ \"system_Device.c Template File\", \"system_c_pg.html#system_Device_sec\", null ],\n      [ \"system_Device.h Template File\", \"system_c_pg.html#system_Device_h_sec\", null ]\n    ] ],\n    [ \"Device Header File \", \"device_h_pg.html\", [\n      [ \"Interrupt Number Definition\", \"device_h_pg.html#interrupt_number_sec\", null ],\n      [ \"Configuration of the Processor and Core Peripherals\", \"device_h_pg.html#core_config_sect\", null ],\n      [ \"CMSIS Version and Processor Information\", \"device_h_pg.html#core_version_sect\", null ],\n      [ \"Device Peripheral Access Layer\", \"device_h_pg.html#device_access\", null ],\n      [ \"Device.h Template File\", \"device_h_pg.html#device_h_sec\", null ]\n    ] ]\n];"
  },
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    "path": "Libraries/CMSIS/Documentation/Core/html/_using__a_r_m_pg.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Using CMSIS with generic ARM Processors\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Using CMSIS with generic ARM Processors 
  
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ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.
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Folder Processor Description  
\".\\Device\\ARM\\ARMCM0\" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.   
\".\\Device\\ARM\\ARMCM0plus\" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.   
\".\\Device\\ARM\\ARMCM3\" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.   
\".\\Device\\ARM\\ARMCM4\" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.   
\".\\Device\\ARM\\ARMSC000\" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.   
\".\\Device\\ARM\\ARMSC300\" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.   
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\nCreate generic Libraries with CMSIS
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The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP  Libraries are an example for such a generic library.
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To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.
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Example: 
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The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, or Cortex-M4. To select the processor the source code uses the define CORTEX_M4, CORTEX_M3, or CORTEX_M0. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4], and Debug Access.
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#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
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  #include "core_cm4.h"
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#elif defined (CORTEX_M0)
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  #include "core_cm0.h"
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#elif defined (CORTEX_M0PLUS)
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  #include "core_cm0plus.h"
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#else
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#endif
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Using CMSIS in Embedded Applications 
  
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To use the CMSIS-CORE the following files are added to the embedded application:
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Note
The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
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The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.
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The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.
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The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:
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\nCMSIS-CORE User Files
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 The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device. Using CMSIS with generic ARM Processors explains how to use CMSIS-CORE for ARM processors.
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For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:
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File Description  
\".\\ARM\\Startup\\ST\\STM32F10x\\startup_stm32f10x_cl.s\" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.  
\".\\ARM\\Startup\\ST\\STM32F10x\\system_stmf10x.c\" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.  
\".\\ARM\\INC\\ST\\STM32F10x\\stm32f10x.h\" Device Header File <device.h> for the STM32F10x device families.  
\".\\ARM\\INC\\ST\\STM32F10x\\system_stm32f10x.h\" system_Device.h Template File for the STM32F10x device families.  
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Note
The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.
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Thereafter, the functions described under Reference  can be used in the application.
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A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.
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#include <stm32f10x.h>                           // File name depends on device used
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uint32_t volatile msTicks;                       // Counter for millisecond Interval
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void SysTick_Handler (void) {                    // SysTick Interrupt Handler
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}
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void WaitForTick (void)  {
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    __WFE ();                                    // Power-Down until next Event/Interrupt
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}
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void TIM1_UP_IRQHandler (void) {                 // Timer Interrupt Handler
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  ;                                              // Add user code here
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}
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void timer1_init(int frequency) {                // Set up Timer (device specific)
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  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
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  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
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}
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void Device_Initialization (void)  {             // Configure & Initialize MCU
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  if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
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       : // Handle Error 
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  timer1_init ();                                // setup device-specific timer
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}
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// The processor clock is initialized by CMSIS startup + system file
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void main (void) {                                   // user application starts here
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  Device_Initialization ();                      // Configure & Initialize MCU
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  while (1)  {                                   // Endless Loop (the Super-Loop)
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    __disable_irq ();                            // Disable all interrupts
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    Get_InputValues ();                          // Read Values
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    __enable_irq ();                             // Enable all interrupts 
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    Calculation_Response ();                     // Calculate Results
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    Output_Response ();                          // Output Results
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    WaitForTick ();                              // Synchronize to SysTick Timer
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Data Structures
  
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Here are the data structures with brief descriptions:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\"o\"\"C\"APSR_TypeUnion type to access the Application Program Status Register (APSR)
\"o\"\"C\"CONTROL_TypeUnion type to access the Control Registers (CONTROL)
\"o\"\"C\"CoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
\"o\"\"C\"DWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
\"o\"\"C\"FPU_TypeStructure type to access the Floating Point Unit (FPU)
\"o\"\"C\"IPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
\"o\"\"C\"ITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
\"o\"\"C\"MPU_TypeStructure type to access the Memory Protection Unit (MPU)
\"o\"\"C\"NVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
\"o\"\"C\"SCB_TypeStructure type to access the System Control Block (SCB)
\"o\"\"C\"SCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
\"o\"\"C\"SysTick_TypeStructure type to access the System Timer (SysTick)
\"o\"\"C\"TPI_TypeStructure type to access the Trace Port Interface Register (TPI)
\"\\\"\"C\"xPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
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    "content": "var annotated =\n[\n    [ \"APSR_Type\", \"union_a_p_s_r___type.html\", \"union_a_p_s_r___type\" ],\n    [ \"CONTROL_Type\", \"union_c_o_n_t_r_o_l___type.html\", \"union_c_o_n_t_r_o_l___type\" ],\n    [ \"CoreDebug_Type\", \"struct_core_debug___type.html\", \"struct_core_debug___type\" ],\n    [ \"DWT_Type\", \"struct_d_w_t___type.html\", \"struct_d_w_t___type\" ],\n    [ \"FPU_Type\", \"struct_f_p_u___type.html\", \"struct_f_p_u___type\" ],\n    [ \"IPSR_Type\", \"union_i_p_s_r___type.html\", \"union_i_p_s_r___type\" ],\n    [ \"ITM_Type\", \"struct_i_t_m___type.html\", \"struct_i_t_m___type\" ],\n    [ \"MPU_Type\", \"struct_m_p_u___type.html\", \"struct_m_p_u___type\" ],\n    [ \"NVIC_Type\", \"struct_n_v_i_c___type.html\", \"struct_n_v_i_c___type\" ],\n    [ \"SCB_Type\", \"struct_s_c_b___type.html\", \"struct_s_c_b___type\" ],\n    [ \"SCnSCB_Type\", \"struct_s_cn_s_c_b___type.html\", \"struct_s_cn_s_c_b___type\" ],\n    [ \"SysTick_Type\", \"struct_sys_tick___type.html\", \"struct_sys_tick___type\" ],\n    [ \"TPI_Type\", \"struct_t_p_i___type.html\", \"struct_t_p_i___type\" ],\n    [ \"xPSR_Type\", \"unionx_p_s_r___type.html\", \"unionx_p_s_r___type\" ]\n];"
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    "content": "\n\n\n\n\nCMSIS-CORE: Data Structure Index\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Data Structure Index
  
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A | C | D | F | I | M | N | S | T | X
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  A  
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\n		ITM_Type   
  S  
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APSR_Type   DWT_Type   SCB_Type   xPSR_Type   
  C  
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  F  
\n		MPU_Type   SCnSCB_Type   
  N  
\n		SysTick_Type   
CONTROL_Type   FPU_Type   
  T  
\n
CoreDebug_Type   
  I  
\n		NVIC_Type   
TPI_Type   
IPSR_Type   
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A | C | D | F | I | M | N | S | T | X
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    "path": "Libraries/CMSIS/Documentation/Core/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #2D4068;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n\theight: 28px;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\n\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #354E81;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: 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border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 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    "content": "\n\n\n\n\nCMSIS-CORE: Device Header File <device.h>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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Device Header File <device.h> 
  
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The Device Header File <device.h> contains the following sections that are device specific:
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  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • \n
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
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  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
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  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
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Reference  describes the standard features and functions of the Device Header File <device.h> in detail.
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\nInterrupt Number Definition
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Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.
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  • Negative IRQn values represent processor core exceptions (internal interrupts).
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  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
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Example: 
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The following example shows the extension of the interrupt vector table for the LPC1100 device family.
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typedef enum IRQn
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{
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/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
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  NonMaskableInt_IRQn           = -14,      
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  HardFault_IRQn                = -13,      
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  SVCall_IRQn                   = -5,       
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  PendSV_IRQn                   = -2,       
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  SysTick_IRQn                  = -1,       
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/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
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  WAKEUP0_IRQn                  = 0,        
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  WAKEUP1_IRQn                  = 1,        
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  WAKEUP2_IRQn                  = 2,
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                 :       :
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                 :       :
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  EINT1_IRQn                    = 30,       
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  EINT0_IRQn                    = 31,       
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} IRQn_Type;
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\nConfiguration of the Processor and Core Peripherals
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The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.
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The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.
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core_cm0.h 
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#define Value Range Default Description  
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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core_cm0plus.h 
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#define Value Range Default Description  
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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core_cm3.h 
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#define Value Range Default Description  
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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core_cm4.h 
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#define Value Range Default Description  
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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core_sc000.h 
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#define Value Range Default Description  
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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core_sc300.h 
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#define Value Range Default Description  
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)  
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)  
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not  
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.  
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Example 
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The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.
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#define __CM4_REV                 0x0001    /* Core revision r0p1                                 */
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#define __MPU_PRESENT             1         /* MPU present or not                                 */
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#define __NVIC_PRIO_BITS          3         /* Number of Bits used for Priority Levels            */
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#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used       */
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#define __FPU_PRESENT             1         /* FPU present or not                                 */
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#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */
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\nCMSIS Version and Processor Information
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Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.
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core_cm0.h 
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#define __CM0_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
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#define __CM0_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
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#define __CM0_CMSIS_VERSION         ((__CM0_CMSIS_VERSION_MAIN << 16) | \\
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                                      __CM0_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
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...    
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#define __CORTEX_M                  (0x00)                                   /* Cortex-M Core                    */
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core_cm0plus.h 
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#define __CM0PLUS_CMSIS_VERSION_MAIN   (0x03)                                /* [31:16] CMSIS HAL main version   */
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#define __CM0PLUS_CMSIS_VERSION_SUB    (0x00)                                /* [15:0]  CMSIS HAL sub version    */
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#define __CM0PLUS_CMSIS_VERSION        ((__CM0P_CMSIS_VERSION_MAIN << 16) | \\
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                                     __CM0P_CMSIS_VERSION_SUB          )  /* CMSIS HAL version number         */
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...    
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#define __CORTEX_M                  (0x00)                                /* Cortex-M Core                    */
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core_cm3.h 
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#define __CM3_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
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#define __CM3_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
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#define __CM3_CMSIS_VERSION         ((__CM3_CMSIS_VERSION_MAIN << 16) | \\
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                                      __CM3_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
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...    
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#define __CORTEX_M                  (0x03)                                   /* Cortex-M Core                    */
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core_cm4.h 
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#define __CM4_CMSIS_VERSION_MAIN    (0x03)                                   /* [31:16] CMSIS HAL main version   */
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#define __CM4_CMSIS_VERSION_SUB     (0x00)                                   /* [15:0]  CMSIS HAL sub version    */
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#define __CM4_CMSIS_VERSION         ((__CM4_CMSIS_VERSION_MAIN << 16) | \\
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                                      __CM4_CMSIS_VERSION_SUB          )     /* CMSIS HAL version number         */
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...    
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#define __CORTEX_M                  (0x04)                                   /* Cortex-M Core                    */
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core_sc000.h 
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#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
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#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
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#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \\
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                                      __SC000_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
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...    
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#define __CORTEX_SC                 (0)                                      /* Cortex secure core             */
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core_sc300.h 
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#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /* [31:16] CMSIS HAL main version */
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#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /* [15:0]  CMSIS HAL sub version  */
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#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \\
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                                      __SC300_CMSIS_VERSION_SUB          )   /* CMSIS HAL version number       */
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...    
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#define __CORTEX_SC                 (300)                                    /* Cortex secure core             */
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\nDevice Peripheral Access Layer
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The Device Header File <device.h> contains for each peripheral:
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  • Register Layout Typedef
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  • Base Address
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  • Access Definitions
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The section Peripheral Access shows examples for peripheral definitions.
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\nDevice.h Template File
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The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.
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/**************************************************************************//**\n * @file     <Device>.h\n * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for\n *           Device <Device>\n * @version  V3.10\n * @date     23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2012 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */\n#define <Device>_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */\n/** @addtogroup <Device>_Definitions <Device> Definitions\n  This file defines all structures and symbols for <Device>:\n    - registers and bitfields\n    - peripheral base address\n    - peripheral ID\n    - Peripheral definitions\n  @{\n*/\n\n\n/******************************************************************************/\n/*                Processor and Core Peripherals                              */\n/******************************************************************************/\n/** @addtogroup <Device>_CMSIS Device CMSIS Definitions\n  Configuration of the Cortex-M# Processor and Core Peripherals\n  @{\n*/\n\n/*\n * ==========================================================================\n * ---------- Interrupt Number Definition -----------------------------------\n * ==========================================================================\n */\n\ntypedef enum IRQn\n{\n/******  Cortex-M# Processor Exceptions Numbers ***************************************************/\n\n/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */\n  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */\n  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */\n  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */\n  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */\n  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */\n\n/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */\n  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */\n  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */\n  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */\n  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */\n  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */\n  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */\n  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */\n  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */\n\n/******  Device Specific Interrupt Numbers ********************************************************/\n/* ToDo: add here your device specific external interrupt numbers\n         according the interrupt handlers defined in startup_Device.s\n         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */\n  <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */\n} IRQn_Type;\n\n\n/*\n * ==========================================================================\n * ----------- Processor and Core Peripheral Section ------------------------\n * ==========================================================================\n */\n\n/* Configuration of the Cortex-M# Processor and Core Peripherals */\n/* ToDo: set the defines according your Device                                                    */\n/* ToDo: define the correct core revision\n         __CM0_REV if your device is a CORTEX-M0 device\n         __CM3_REV if your device is a CORTEX-M3 device\n         __CM4_REV if your device is a CORTEX-M4 device                                           */\n#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */\n#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */\n#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */\n#define __MPU_PRESENT             0         /*!< MPU present or not                               */\n/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */\n#define __FPU_PRESENT             0        /*!< FPU present or not                                */\n\n/*@}*/ /* end of group <Device>_CMSIS */\n\n\n/* ToDo: include the correct core_cm#.h file\n         core_cm0.h if your device is a CORTEX-M0 device\n         core_cm3.h if your device is a CORTEX-M3 device\n         core_cm4.h if your device is a CORTEX-M4 device                                          */\n#include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */\n/* ToDo: include your system_<Device>.h file\n         replace '<Device>' with your device name                                                 */\n#include \"system_<Device>.h\"                /* <Device> System  include file                      */\n\n\n/******************************************************************************/\n/*                Device Specific Peripheral registers structures             */\n/******************************************************************************/\n/** @addtogroup <Device>_Peripherals <Device> Peripherals\n  <Device> Device Specific Peripheral registers structures\n  @{\n*/\n\n#if defined ( __CC_ARM   )\n#pragma anon_unions\n#endif\n\n/* ToDo: add here your device specific peripheral access structure typedefs\n         following is an example for a timer                                  */\n\n/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/\n/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)\n  @{\n*/\ntypedef struct\n{\n  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */\n  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */\n  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */\n  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */\n       uint32_t RESERVED0[1];\n  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */\n  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */\n  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */\n  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */\n       uint32_t RESERVED1[2];\n  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */\n} <DeviceAbbreviation>_TMR_TypeDef;\n/*@}*/ /* end of group <Device>_TMR */\n\n\n#if defined ( __CC_ARM   )\n#pragma no_anon_unions\n#endif\n\n/*@}*/ /* end of group <Device>_Peripherals */\n\n\n/******************************************************************************/\n/*                         Peripheral memory map                              */\n/******************************************************************************/\n/* ToDo: add here your device peripherals base addresses\n         following is an example for timer                                    */\n/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping\n  @{\n*/\n\n/* Peripheral and SRAM base address */\n#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */\n#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */\n#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */\n\n/* Peripheral memory map */\n#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */\n#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */\n#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */\n/*@}*/ /* end of group <Device>_MemoryMap */\n\n\n/******************************************************************************/\n/*                         Peripheral declaration                             */\n/******************************************************************************/\n/* ToDo: add here your device peripherals pointer definitions\n         following is an example for timer                                    */\n\n/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration\n  @{\n*/\n\n#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n/*@}*/ /* end of group <Device>_PeripheralDecl */\n\n/*@}*/ /* end of group <Device>_Definitions */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* <Device>_H */\n
 
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    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l\n\n\n\n\nCMSIS-CORE: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\nFunctions  
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Core Register Access
  
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\nFunctions
uint32_t __get_CONTROL (void)
 Read the CONTROL register.  More...
 
void __set_CONTROL (uint32_t control)
 Set the CONTROL Register.  More...
 
uint32_t __get_IPSR (void)
 Read the IPSR register.  More...
 
uint32_t __get_APSR (void)
 Read the APSR register.  More...
 
uint32_t __get_xPSR (void)
 Read the xPSR register.  More...
 
uint32_t __get_PSP (void)
 Read the PSP register.  More...
 
void __set_PSP (uint32_t topOfProcStack)
 Set the PSP register.  More...
 
uint32_t __get_MSP (void)
 Read the MSP register.  More...
 
void __set_MSP (uint32_t topOfMainStack)
 Set the MSP register.  More...
 
uint32_t __get_PRIMASK (void)
 Read the PRIMASK register bit.  More...
 
void __set_PRIMASK (uint32_t priMask)
 Set the Priority Mask bit.  More...
 
uint32_t __get_BASEPRI (void)
 Read the BASEPRI register [not for Cortex-M0 variants].  More...
 
void __set_BASEPRI (uint32_t basePri)
 Set the BASEPRI register [not for Cortex-M0 variants].  More...
 
uint32_t __get_FAULTMASK (void)
 Read the FAULTMASK register [not for Cortex-M0 variants].  More...
 
void __set_FAULTMASK (uint32_t faultMask)
 Set the FAULTMASK register [not for Cortex-M0 variants].  More...
 
uint32_t __get_FPSCR (void)
 Read the FPSCR register [only for Cortex-M4].  More...
 
void __set_FPSCR (uint32_t fpscr)
 Set the FPSC register [only for Cortex-M4].  More...
 
void __enable_irq (void)
 Globally enables interrupts and configurable fault handlers.  More...
 
void __disable_irq (void)
 Globally disables interrupts and configurable fault handlers.  More...
 
void __enable_fault_irq (void)
 Enables interrupts and all fault handlers [not for Cortex-M0 variants].  More...
 
void __disable_fault_irq (void)
 Disables interrupts and all fault handlers [not for Cortex-M0 variants].  More...
 
\n
Description
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The following functions provide access to Cortex-M core registers. 
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Function Documentation
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void __disable_fault_irq (void )
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The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.
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Remarks
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  • not for Cortex-M0 variants.
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  • Can be executed in privileged mode only.
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void __disable_irq (void )
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The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.
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Remarks
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void __enable_fault_irq (void )
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The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.
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Remarks
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void __enable_irq (void )
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The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.
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uint32_t __get_APSR (void )
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The function reads the Application Program Status Register (APSR) using the instruction MRS. 
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\n The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:
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    \n
  • N (APSR[31]) (Negative flag)
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    • =1 The instruction result has a negative value (when interpreted as signed integer).
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    • =0 The instruction result has a positive value or equal zero. 
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  • Z (APSR[30]) (Zero flag)
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    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. 
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  • C (APSR[29]) (Carry or borrow flag)
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    • =inverse of borrow output status For unsigned subtract operations. 
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  • V (APSR[28]) (Overflow flag)
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    • =1 A signed overflow occurred (for signed additions or subtractions). 
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  • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
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    • =1 When saturation or an overflow occurred. 
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  • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
      \n
    • Can be set by the parallel add and subtract instructions.
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    • Are used by the SEL instruction to perform byte-based selection from two registers.
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Returns
APSR register value
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Remarks
    \n
  • Some instructions update all flags; some instructions update a subset of the flags.
    • \n
  • If a flag is not updated, the original value is preserved.
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  • Conditional instructions that are not executed have no effect on the flags.
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  • The CMSIS does not provide a function to update this register.
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uint32_t __get_BASEPRI (void )
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The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS. 
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\n BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
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Returns
BASEPRI register value
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  • not for Cortex-M0 variants.
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uint32_t __get_CONTROL (void )
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The function reads the CONTROL register value using the instruction MRS. 
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\n The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: 
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  • CONTROL[2] [only Cortex-M4]
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    • =0 FPU not active
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    • =1 FPU active 
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  • CONTROL[1]
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    • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
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    • =0 In thread mode - Default stack pointer MSP is used.
      • \n
    • =1 In thread mode - Alternate stack pointer PSP is used. 
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    • \n
  • CONTROL[0] [not Cortex-M0]
      \n
    • =0 In thread mode and privileged state.
      • \n
    • =1 In thread mode and user state.
      • \n
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Returns
CONTROL register value
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Remarks
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  • The processor can be in user state or privileged state when running in thread mode.
    • \n
  • Exception handlers always run in privileged state.
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  • On reset, the processor is in thread mode with privileged access rights.
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uint32_t __get_FAULTMASK (void )
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The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS. 
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\n FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).
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Returns
FAULTMASK register value
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Remarks
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  • not for Cortex-M0 variants.
    • \n
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
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See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_FPSCR (void )
\n
\n
The function reads the Floating-Point Status Control Register (FPSCR) value. 
\n
\n FPSCR provides all necessary User level controls of the floating-point system.
\n
Returns
    \n
  • FPSCR register value, when __FPU_PRESENT=1
    • \n
  • =0, when __FPU_PRESENT=0
    • \n
\n
\n
Remarks
    \n
  • Only for Cortex-M4.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_IPSR (void )
\n
\n
The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS. 
\n
\n The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:
\n
    \n
  • ISR_NUMBER (IPSR[8:0])
      \n
    • =0 Thread mode
      • \n
    • =1 Reserved
      • \n
    • =2 NMI
      • \n
    • =3 HardFault
      • \n
    • =4 MemManage
      • \n
    • =5 BusFault
      • \n
    • =6 UsageFault
      • \n
    • =7-10 Reserved
      • \n
    • =11 SVCall
      • \n
    • =12 Reserved for Debug
      • \n
    • =13 Reserved
      • \n
    • =14 PendSV
      • \n
    • =15 SysTick
      • \n
    • =16 IRQ0
      • \n
    • ...
      • \n
    • =n+15 IRQ(n-1)
      • \n
    \n
    • \n
\n
Returns
ISPR register value
\n
Remarks
    \n
  • This register is read-only.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_MSP (void )
\n
\n
The function reads the Main Status Pointer (MSP) value using the instruction MRS. 
\n
\n Physically two different stack pointers (SP) exist:
\n
    \n
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • \n
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • \n
\n
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
\n
    \n
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • \n
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • \n
\n
Returns
MSP Register value
\n
Remarks
    \n
  • Only one of the two SPs is visible at a time.
    • \n
  • For many applications, the system can completely rely on the MSP.
    • \n
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_PRIMASK (void )
\n
\n
The function reads the Priority Mask register (PRIMASK) value using the instruction MRS. 
\n
\n PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
\n
Returns
PRIMASK register value
    \n
  • =0 no effect
    • \n
  • =1 prevents the activation of all exceptions with configurable priority
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_PSP (void )
\n
\n
The function reads the Program Status Pointer (PSP) value using the instruction MRS. 
\n
\n Physically two different stack pointers (SP) exist:
\n
    \n
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • \n
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • \n
\n
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
\n
    \n
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • \n
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • \n
\n
Returns
PSP register value
\n
Remarks
    \n
  • Only one of the two SPs is visible at a time.
    • \n
  • For many applications, the system can completely rely on the MSP.
    • \n
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __get_xPSR (void )
\n
\n
The function reads the combined Program Status Register (xPSR) using the instruction MRS. 
\n
\n xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: 
\n
    \n
  • Application Program Status Register (APSR) 
    • \n
  • Interrupt Program Status Register (IPSR) 
    • \n
  • Execution Program Status Register (EPSR)
    • \n
\n
In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:
\n
    \n
  • IT (xPSR[26:25]) (If-Then condition instruction)
      \n
    • Contains up to four instructions following an IT instruction.
      • \n
    • Each instruction in the block is conditional.
      • \n
    • The conditions for the instructions are either all the same, or some can be the inverse of others. 
      \n
      \n
      • \n
    \n
    • \n
  • T (xPSR[24]) (Thumb bit)
      \n
    • =1 Indicates that that the processor is in Thumb state.
      • \n
    • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
      • \n
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      • \n
    \n
    • \n
\n
Returns
xPSR register value
\n
Remarks
    \n
  • The CMSIS does not provide functions that access EPSR.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_BASEPRI (uint32_t basePri)
\n
\n
The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR. 
\n
\n BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.
\n
Parameters
\n  \n    \n  
[in]basePriBASEPRI value to set
\n  
\n
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
  • Cannot be set in user state.
    • \n
  • Useful for changing the masking level or disabling the masking.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_CONTROL (uint32_t control)
\n
\n
The function sets the CONTROL register value using the instruction MSR. 
\n
\n The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: 
\n
\n
    \n
  • CONTROL[2] [only Cortex-M4]
      \n
    • =0 FPU not active
      • \n
    • =1 FPU active 
      \n
      \n
      • \n
    \n
    • \n
  • CONTROL[1]
      \n
    • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
      • \n
    • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
      • \n
    • =0 In thread mode - Default stack pointer MSP is used.
      • \n
    • =1 In thread mode - Alternate stack pointer PSP is used. 
      \n
      \n
      • \n
    \n
    • \n
  • CONTROL[0] [not writeable for Cortex-M0]
      \n
    • Writeable only when the processor is in privileged state.
      • \n
    • Can be used to switch the processor to user state (thread mode).
      • \n
    • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
      • \n
    • =0 In thread mode and privileged state.
      • \n
    • =1 In thread mode and user state.
      • \n
    \n
    • \n
\n
Parameters
\n  \n    \n  
[in]controlCONTROL register value to set
\n  
\n
\n
Remarks
    \n
  • The processor can be in user state or privileged state when running in thread mode.
    • \n
  • Exception handlers always run in privileged state.
    • \n
  • On reset, the processor is in thread mode with privileged access rights.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_FAULTMASK (uint32_t faultMask)
\n
\n
The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR. 
\n
\n FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:
\n
    \n
  1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
    2. \n
  2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
    3. \n
\n
Parameters
\n  \n    \n  
[in]faultMaskFAULTMASK register value to set
\n  
\n
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • \n
  • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
    • \n
  • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
    • \n
  • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_FPSCR (uint32_t fpscr)
\n
\n
The function sets the Floating-Point Status Control Register (FPSCR) value. 
\n
\n FPSCR provides all necessary User level control of the floating-point system. 
\n
\n
    \n
  • N (FPSC[31]) (Negative flag)
      \n
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • \n
    • =0 The instruction result has a positive value or equal zero. 
      \n
      \n
      • \n
    \n
    • \n
  • Z (FPSC[30]) (Zero flag)
      \n
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. 
      \n
      \n
      • \n
    \n
    • \n
  • C (FPSC[29]) (Carry or borrow flag)
      \n
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • \n
    • =inverse of borrow output status For unsigned subtract operations. 
      \n
      \n
      • \n
    \n
    • \n
  • V (FPSC[28]) (Overflow flag)
      \n
    • =1 A signed overflow occurred (for signed additions or subtractions). 
      \n
      \n
      • \n
    \n
    • \n
  • AHP (FPSC[26]) (Alternative half-precision flag)
      \n
    • =1 Alternative half-precision format selected.
      • \n
    • =0 IEEE half-precision format selected. 
      \n
      \n
      • \n
    \n
    • \n
  • DN (FPSC[25]) (Default NaN mode control flag)
      \n
    • =1 Any operation involving one or more NaNs returns the Default NaN.
      • \n
    • =0 NaN operands propagate through to the output of a floating-point operation. 
      \n
      \n
      • \n
    \n
    • \n
  • FZ (FPSC[24]) (Flush-to-zero mode control flag)
      \n
    • =1 Flush-to-zero mode enabled.
      • \n
    • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 
      \n
      \n
      • \n
    \n
    • \n
  • RMode (FPSC[23:22]) (Rounding Mode control flags)
      \n
    • =0b00 Round to Nearest (RN) mode.
      • \n
    • =0b01 Round towards Plus Infinity (RP) mode.
      • \n
    • =0b10 Round towards Minus Infinity (RM) mode.
      • \n
    • =0b11 Round towards Zero (RZ) mode.
      • \n
    • The specified rounding mode is used by almost all floating-point instructions. 
      \n
      \n
      • \n
    \n
    • \n
  • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
      \n
    • See Cumulative exception bits (FPSC[4:0]). 
      \n
      \n
      • \n
    \n
    • \n
  • IXC (FPSC[4]) (Inexact cumulative exception flag)
      \n
    • =1 Exception occurred.
      • \n
    • =0 Value has to be set explicitly.
      • \n
    • Flag is not cleared automatically. 
      \n
      \n
      • \n
    \n
    • \n
  • UFC (FPSC[3]) (Underflow cumulative exception flag)
      \n
    • =1 Exception occurred.
      • \n
    • =0 Value has to be set explicitly.
      • \n
    • Flag is not cleared automatically. 
      \n
      \n
      • \n
    \n
    • \n
  • OFC (FPSC[2]) (Overflow cumulative exception flag)
      \n
    • =1 Exception occurred.
      • \n
    • =0 Value has to be set explicitly.
      • \n
    • Flag is not cleared automatically. 
      \n
      \n
      • \n
    \n
    • \n
  • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
      \n
    • =1 Exception occurred.
      • \n
    • =0 Value has to be set explicitly.
      • \n
    • Flag is not cleared automatically. 
      \n
      \n
      • \n
    \n
    • \n
  • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
      \n
    • =1 Exception occurred.
      • \n
    • =0 Value has to be set explicitly.
      • \n
    • Flag is not cleared automatically.
      • \n
    \n
    • \n
\n
Parameters
\n  \n    \n  
[in]fpscrFPSCR value to set
\n  
\n
\n
Remarks
    \n
  • Only for Cortex-M4.
    • \n
  • The variable __FPU_PRESENT has to be set to 1.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_MSP (uint32_t topOfMainStack)
\n
\n
The function sets the Main Status Pointer (MSP) value using the instruction MSR. 
\n
\n Physically two different stack pointers (SP) exist:
\n
    \n
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • \n
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • \n
\n
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
\n
    \n
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • \n
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • \n
\n
Parameters
\n  \n    \n  
[in]topOfMainStackMSP value to set
\n  
\n
\n
Remarks
    \n
  • Only one of the two SPs is visible at a time.
    • \n
  • For many applications, the system can completely rely on the MSP.
    • \n
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_PRIMASK (uint32_t priMask)
\n
\n
The function sets the Priority Mask register (PRIMASK) value using the instruction MSR. 
\n
\n PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.
\n
Parameters
\n  \n    \n  
[in]priMaskPriority Mask
    \n
  • =0 no effect
    • \n
  • =1 prevents the activation of all exceptions with configurable priority
    • \n
\n
\n  
\n
\n
Remarks
    \n
  • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
    • \n
  • When set and a fault occurs, the hard fault handler will be executed.
    • \n
  • Useful for temprorarily disabling all interrupts for timing critical tasks.
    • \n
  • Does not have the ability to mask BusFault or bypass MPU.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __set_PSP (uint32_t topOfProcStack)
\n
\n
The function sets the Program Status Pointer (PSP) value using the instruction MSR. 
\n
\n Physically two different stack pointers (SP) exist:
\n
    \n
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • \n
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • \n
\n
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
\n
    \n
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • \n
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • \n
\n
Parameters
\n  \n    \n  
[in]topOfProcStackPSP value to set
\n  
\n
\n
Remarks
    \n
  • Only one of the two SPs is visible at a time.
    • \n
  • For many applications, the system can completely rely on the MSP.
    • \n
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
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    "content": "\n\n\n\n\nCMSIS-CORE: Debug Access\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
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\n  
\nFunctions |\nVariables  
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\n
Debug Access
  
\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
uint32_t ITM_SendChar (uint32_t ch)
 Transmits a character via channel 0.  More...
 
int32_t ITM_ReceiveChar (void)
 ITM Receive Character.  More...
 
int32_t ITM_CheckChar (void)
 ITM Check Character.  More...
 
\n\n\n\n\n
\nVariables
volatile int32_t ITM_RxBuffer
 external variable to receive characters  More...
 
\n
Description
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CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.
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The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:
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    \n
  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
    • \n
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  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
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Remarks
    \n
  • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
    • \n
  • The ITM channel 0 can be enabled for the user task.
    • \n
  • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
    • \n
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\n
\n 
\nITM Debug Support in uVision
\n
In a debug session, uVision uses the Debug (printf) Viewer window to display data.
\n
Direction: Microcontroller –> uVision:
\n
    \n
  • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
    • \n
\n
Direction: uVision –> Microcontroller:
\n
    \n
  • Check if ITM_RxBuffer variable is available (only performed once).
    • \n
  • Read the character from the Debug (printf) Viewer window.
    • \n
  • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
    • \n
\n
Note
The current solution does not use a buffer mechanism for transmitting the characters.
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\n 
\nExample:
\n
Example for the usage of the ITM Channel 31 for RTOS Kernels:
\n
// check if debugger connected and ITM channel enabled for tracing
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if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
\n
    (ITM->TCR & ITM_TCR_ITMENA) &&
\n
    (ITM->TER & (1UL >> 31))) {
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\n
    // transmit trace data
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    while (ITM->PORT31_U32 == 0);
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    ITM->PORT[31].u8 = task_id;      // id of next task
\n
    while (ITM->PORT[31].u32 == 0);
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    ITM->PORT[31].u32 = task_status; // status information
\n
}
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Function Documentation
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
int32_t ITM_CheckChar (void )
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\n
This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.
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Returns
    \n
  • =0 - No character available
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  • =1 - Character available 
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int32_t ITM_ReceiveChar (void )
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\n
This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.
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Returns
    \n
  • Received character
    • \n
  • =1 - No character received 
    • \n
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uint32_t ITM_SendChar (uint32_t ch)
\n
\n
This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.
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Parameters
\n  \n    \n  
[in]chCharacter to transmit
\n  
\n
\n
Returns
Character to transmit 
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Variable Documentation
\n\n
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\n      \n        \n          \n        \n      
volatile int32_t ITM_RxBuffer
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    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group___i_t_m___debug__gr.js",
    "content": "var group___i_t_m___debug__gr =\n[\n    [ \"ITM_CheckChar\", \"group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535\", null ],\n    [ \"ITM_ReceiveChar\", \"group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c\", null ],\n    [ \"ITM_SendChar\", \"group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1\", null ],\n    [ \"ITM_RxBuffer\", \"group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group___n_v_i_c__gr.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Interrupts and Exceptions (NVIC)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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\nEnumerations |\nFunctions  
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Interrupts and Exceptions (NVIC)
  
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Describes programming of interrupts and exception functions.  \nMore...
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\nEnumerations
enum  IRQn_Type { 
\n  NonMaskableInt_IRQn = -14, \n
\n  HardFault_IRQn = -13, \n
\n  MemoryManagement_IRQn = -12, \n
\n  BusFault_IRQn = -11, \n
\n  UsageFault_IRQn = -10, \n
\n  SVCall_IRQn = -5, \n
\n  DebugMonitor_IRQn = -4, \n
\n  PendSV_IRQn = -2, \n
\n  SysTick_IRQn = -1, \n
\n  WWDG_STM_IRQn = 0, \n
\n  PVD_STM_IRQn = 1\n
\n }
 Definition of IRQn numbers.  More...
 
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\nFunctions
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0 variants].  More...
 
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0 variants].  More...
 
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable an external interrupt.  More...
 
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable an external interrupt.  More...
 
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending interrupt.  More...
 
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set an interrupt to pending.  More...
 
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear an interrupt from pending.  More...
 
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the interrupt active status [not for Cortex-M0 variants].  More...
 
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt.  More...
 
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt.  More...
 
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0 variants].  More...
 
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0 variants].  More...
 
void NVIC_SystemReset (void)
 Reset the system.  More...
 
\n
Description
\n
ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.
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The table below describes the core exception names and their availability in various Cortex-M cores.
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Core Exception Name IRQn Value M0 M0p M3 M4 SC000 SC300 Description  
NonMaskableInt_IRQn -14 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		Non Maskable Interrupt  
HardFault_IRQn -13 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		Hard Fault Interrupt  
MemoryManagement_IRQn -12     
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		  
\n\"available\"/\n
\n 		Memory Management Interrupt  
BusFault_IRQn -11     
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		  
\n\"available\"/\n
\n 		Bus Fault Interrupt  
UsageFault_IRQn -10     
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		  
\n\"available\"/\n
\n 		Usage Fault Interrupt  
SVCall_IRQn -5 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		SV Call Interrupt   
DebugMonitor_IRQn -4     
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		  
\n\"available\"/\n
\n 		Debug Monitor Interrupt  
PendSV_IRQn -2 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		Pend SV Interrupt  
SysTick_IRQn -1 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 
\n\"available\"/\n
\n 		System Tick Interrupt  
\n
\nFor Cortex-M0 and Cortex-M0+
\n
The following exception names are fixed and define the start of the vector table for Cortex-M0 variants:
\n
__Vectors       DCD     __initial_sp              ; Top of Stack
\n
                DCD     Reset_Handler             ; Reset Handler
\n
                DCD     NMI_Handler               ; NMI Handler
\n
                DCD     HardFault_Handler         ; Hard Fault Handler
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     SVC_Handler               ; SVCall Handler
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     PendSV_Handler            ; PendSV Handler
\n
                DCD     SysTick_Handler           ; SysTick Handler
\n
\nFor Cortex-M3
\n
The following exception names are fixed and define the start of the vector table for a Cortex-M3:
\n
__Vectors       DCD     __initial_sp              ; Top of Stack
\n
                DCD     Reset_Handler             ; Reset Handler
\n
                DCD     NMI_Handler               ; NMI Handler
\n
                DCD     HardFault_Handler         ; Hard Fault Handler
\n
                DCD     MemManage_Handler         ; MPU Fault Handler
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                DCD     BusFault_Handler          ; Bus Fault Handler
\n
                DCD     UsageFault_Handler        ; Usage Fault Handler
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     0                         ; Reserved
\n
                DCD     SVC_Handler               ; SVCall Handler
\n
                DCD     DebugMon_Handler          ; Debug Monitor Handler
\n
                DCD     0                         ; Reserved
\n
                DCD     PendSV_Handler            ; PendSV Handler
\n
                DCD     SysTick_Handler           ; SysTick Handler
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\nExample
\n
The following is an examples for device-specific interrupts:
\n
; External Interrupts
\n
                DCD     WWDG_IRQHandler           ; Window Watchdog
\n
                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
\n
                DCD     TAMPER_IRQHandler         ; Tamper
\n
Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.
\n
Default_Handler PROC
\n
                EXPORT WWDG_IRQHandler   [WEAK]
\n
                EXPORT PVD_IRQHandler    [WEAK]
\n
                EXPORT TAMPER_IRQHandler [WEAK]
\n
                :
\n
                :
\n
                WWDG_IRQHandler
\n
                PVD_IRQHandler
\n
                TAMPER_IRQHandler
\n
                :
\n
                :
\n
                B .
\n
                ENDP
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The user application may simply define an interrupt handler function by using the handler name as shown below.
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void WWDG_IRQHandler(void)
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{
\n
  ...
\n
}
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\nCode Example 1
\n
The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.
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#include "LPC17xx.h"
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\n
uint32_t priorityGroup;                                     /* Variables to store priority group and priority */
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uint32_t priority;
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uint32_t preemptPriority;
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uint32_t subPriority;
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int main (void)  {
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  NVIC_SetPriorityGrouping(5);                              /* Set priority group to 5:
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                                                               Bit[7..6] preempt priority Bits, 
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                                                               Bit[5..3] subpriority Bits 
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                                                               (valid for five priority bits) */
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  priorityGroup =  NVIC_GetPriorityGrouping();              /* Get used priority grouping */
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  priority = NVIC_EncodePriority(priorityGroup, 1, 6);      /* Encode priority with 6 for subpriority and 1 for preempt priority
\n
                                                               Note: priority depends on the used priority grouping */
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  NVIC_SetPriority(UART0_IRQn, priority);                   /* Set new priority */
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\n
  priority =  NVIC_GetPriority(UART0_IRQn);                 /* Retrieve priority again */    
\n
\n
  NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
\n
\n
  while(1);
\n
}
\n
\nCode Example 2
\n
The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.
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#include "LPC17xx.h"
\n
\n
uint32_t active;                                            /* Variable to store interrupt active state */
\n
\n
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void TIMER0_IRQHandler(void)  {                             /* Timer 0 interrupt handler  */
\n
\n
  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occured */ 
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    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occured */
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  }
\n
  active = NVIC_GetActive(TIMER0_IRQn);                     /* Get interrupt active state of timer 0 */
\n
}
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int main (void) {
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                                                            /* Set match channel register MR0 to 1 millisecond */
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  LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1);     /* 1 ms? */
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  LPC_TIM0->MCR = (3 << 0);                                 /* Enable interrupt and reset for match channel MR0 */
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  NVIC_EnableIRQ(TIMER0_IRQn);                              /* Enable NVIC interrupt for timer 0 */
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\n
  LPC_TIM0->TCR = (1 << 0);                                 /* Enable timer 0 */
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  while(1);
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}
\n
 
Enumeration Type Documentation
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\n      \n        \n          \n        \n      
enum IRQn_Type
\n
\n
The core exception enumeration names for IRQn values are defined in the file device.h. 
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Negative IRQn values represent processor core exceptions (internal interrupts).\nPositive IRQn values represent device-specific exceptions (external interrupts). \nThe first device-specific interrupt has the IRQn value 0.\n
The table below describes the core exception names and their availability in various Cortex-M cores. 
\n\n\n\n\n\n\n\n\n\n\n\n\n
Enumerator
NonMaskableInt_IRQn \n
Exception 2: Non Maskable Interrupt. 
\n
HardFault_IRQn \n
Exception 3: Hard Fault Interrupt. 
\n
MemoryManagement_IRQn \n
Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. 
\n
BusFault_IRQn \n
Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. 
\n
UsageFault_IRQn \n
Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. 
\n
SVCall_IRQn \n
Exception 11: SV Call Interrupt. 
\n
DebugMonitor_IRQn \n
Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. 
\n
PendSV_IRQn \n
Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. 
\n
SysTick_IRQn \n
Exception 15: System Tick Interrupt. 
\n
WWDG_STM_IRQn \n
Device Interrupt 0: Window WatchDog Interrupt. 
\n
PVD_STM_IRQn \n
Device Interrupt 1: PVD through EXTI Line detection Interrupt. 
\n
\n\n
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Function Documentation
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
\n
\n
This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.
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Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Remarks
    \n
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • \n
  • An interrupt can have the status pending though it is not active.
    • \n
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See Also
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void NVIC_DecodePriority (uint32_t Priority, 
uint32_t PriorityGroup, 
uint32_t * pPreemptPriority, 
uint32_t * pSubPriority 
)
\n
\n
This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]PriorityPriority 
[in]PriorityGroupPriority group 
[out]*pPreemptPriorityPreemptive priority value (starting from 0) 
[out]*pSubPrioritySubpriority value (starting from 0)
\n  
\n
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
\n
\n
See Also
\n
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void NVIC_DisableIRQ (IRQn_Type IRQn)
\n
\n
This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.
\n
Parameters
\n  \n    \n  
[in]IRQnNumber of the external interrupt to disable
\n  
\n
\n
Remarks
    \n
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • \n
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See Also
\n
\n\n
\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
void NVIC_EnableIRQ (IRQn_Type IRQn)
\n
\n
This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.
\n
Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Remarks
    \n
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • \n
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: 
    \n ICTR[4:0]
      \n
    • =0 - 32 interrupts supported
      • \n
    • =1 - 64 interrupts supported
      • \n
    • ...
      • \n
    \n
    • \n
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See Also
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uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, 
uint32_t PreemptPriority, 
uint32_t SubPriority 
)
\n
\n
This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\n
Parameters
\n  \n    \n    \n    \n  
[in]PriorityGroupPriority group 
[in]PreemptPriorityPreemptive priority value (starting from 0) 
[in]SubPrioritySubpriority value (starting from 0)
\n  
\n
\n
Returns
Encoded priority for the interrupt
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
\n
\n
See Also
\n
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\n
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\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t NVIC_GetActive (IRQn_Type IRQn)
\n
\n
This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.
\n
Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Returns
    \n
  • =0 Interrupt is not active
    • \n
  • =1 Interrupt is active, or active and pending
    • \n
\n
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • \n
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • \n
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See Also
\n
\n\n
\n
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\n
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uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
\n
\n
This function returns the pending status of the specified interrupt IRQn.
\n
Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Returns
    \n
  • =0 Interrupt is not pending
    • \n
  • =1 Interrupt is pending
    • \n
\n
\n
Remarks
    \n
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
\n
\n
This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.
\n
The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.
\n
Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Returns
Interrupt priority
\n
Remarks
    \n
  • Each external interrupt has an associated priority-level register.
    • \n
  • Unimplemented bits are read as zero.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t NVIC_GetPriorityGrouping (void )
\n
\n
This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).
\n
Returns
Priority grouping field
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
  • By default, priority group setting is zero.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
\n
\n
This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.
\n
Parameters
\n  \n    \n  
[in]IRQnInterrupt number
\n  
\n
\n
Remarks
    \n
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
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\n
See Also
\n
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\n
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void NVIC_SetPriority (IRQn_Type IRQn, 
uint32_t priority 
)
\n
\n
Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.
\n
The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.
\n
Parameters
\n  \n    \n    \n  
[in]IRQnInterrupt Number 
[in]priorityPriority to set
\n  
\n
\n
Remarks
    \n
  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
    • \n
  • Writes to unimplemented bits are ignored.
    • \n
  • For Cortex-M0:
      \n
    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
      • \n
    • Supports 0 to 192 priority levels.
      • \n
    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
      • \n
    \n
    • \n
  • For Cortex-M3 and Cortex-M4:
      \n
    • Dynamic switching of interrupt priority levels is supported.
      • \n
    • Supports 0 to 255 priority levels.
      • \n
    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
      • \n
    \n
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
\n
\n
The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\n
Parameters
\n  \n    \n  
[in]PriorityGroupPriority group
\n  
\n
\n
Remarks
    \n
  • not for Cortex-M0 variants.
    • \n
  • By default, priority group setting is zero.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void NVIC_SystemReset (void )
\n
\n
This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.
\n
Remarks
    \n
  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
    • \n
\n
\n
See Also
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Systick Timer (SYSTICK)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
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\nFunctions  
\n  
\n
Systick Timer (SYSTICK)
  
\n
\n
\n\n
Initialize and start the SysTick timer.  \nMore...
\n\n\n\n\n\n
\nFunctions
uint32_t SysTick_Config (uint32_t ticks)
 System Tick Timer Configuration.  More...
 
\n
Description
\n
The System Tick Time (SysTick) generates interrupt requests on a regular basis.\nThis allows an OS to carry out context switching to support multiple tasking. For applications\nthat do not require an OS, the SysTick can be used for time keeping, time measurement, or as an \ninterrupt source for tasks that need to be executed regularly.\n
\nCode Example
\n
The code below shows the usage of the function SysTick_Config() with an LPC1700.
\n
#include "LPC17xx.h"
\n
\n
uint32_t msTicks = 0;                                       /* Variable to store millisecond ticks */
\n
\n
                                            
\n
void SysTick_Handler(void)  {                               /* SysTick interrupt Handler.
\n
  msTicks++;                                                   See startup file startup_LPC17xx.s for SysTick vector */ 
\n
}
\n
\n
\n
int main (void)  {
\n
  uint32_t returnCode;
\n
\n
  returnCode = SysTick_Config(SystemCoreClock / 1000);      /* Configure SysTick to generate an interrupt every millisecond */
\n
\n
  if (returnCode != 0)  {                                   /* Check return code for errors */
\n
    // Error Handling 
\n
  }
\n
\n
  while(1);
\n
}
\n
 
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t SysTick_Config (uint32_t ticks)
\n
\n
Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.
\n
Parameters
\n  \n    \n  
[in]ticksNumber of ticks between two interrupts
\n  
\n
\n
Returns
0 - success 
\n
\n1 - failure
\n
Note
When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. 
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group___sys_tick__gr.js",
    "content": "var group___sys_tick__gr =\n[\n    [ \"SysTick_Config\", \"group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group__intrinsic___c_p_u__gr.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Intrinsic Functions for CPU Instructions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
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\nFunctions  
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Intrinsic Functions for CPU Instructions
  
\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
void __NOP (void)
 No Operation.  More...
 
void __WFI (void)
 Wait For Interrupt.  More...
 
void __WFE (void)
 Wait For Event.  More...
 
void __SEV (void)
 Send Event.  More...
 
void __BKPT (uint8_t value)
 Set Breakpoint.  More...
 
void __ISB (void)
 Instruction Synchronization Barrier.  More...
 
void __DSB (void)
 Data Synchronization Barrier.  More...
 
void __DMB (void)
 Data Memory Barrier.  More...
 
uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit)  More...
 
uint32_t __REV16 (uint32_t value)
 Reverse byte order (16 bit)  More...
 
int32_t __REVSH (int32_t value)
 Reverse byte order in signed short value.  More...
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value [not for Cortex-M0 variants].  More...
 
uint32_t __ROR (uint32_t value, uint32_t shift)
 Rotate a value right by a number of bits.  More...
 
uint8_t __LDREXB (volatile uint8_t *addr)
 LDR Exclusive (8 bit) [not for Cortex-M0 variants].  More...
 
uint16_t __LDREXH (volatile uint16_t *addr)
 LDR Exclusive (16 bit) [not for Cortex-M0 variants].  More...
 
uint32_t __LDREXW (volatile uint32_t *addr)
 LDR Exclusive (32 bit) [not for Cortex-M0 variants].  More...
 
uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
 STR Exclusive (8 bit) [not for Cortex-M0 variants].  More...
 
uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
 STR Exclusive (16 bit) [not for Cortex-M0 variants].  More...
 
uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
 STR Exclusive (32 bit) [not for Cortex-M0 variants].  More...
 
void __CLREX (void)
 Remove the exclusive lock [not for Cortex-M0 variants].  More...
 
uint32_t __SSAT (unint32_t value, uint32_t sat)
 Signed Saturate [not for Cortex-M0 variants].  More...
 
uint32_t __USAT (uint32_t value, uint32_t sat)
 Unsigned Saturate [not for Cortex-M0 variants].  More...
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros [not for Cortex-M0 variants].  More...
 
\n
Description
\n
The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __BKPT (uint8_t value)
\n
\n
This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\n
Parameters
\n  \n    \n  
[in]valueis ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint. 
\n  
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void __CLREX (void )
\n
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This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants]. 
\n\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint8_t __CLZ (uint32_t value)
\n
\n
This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n  
[in]valueValue to count the leading zeros 
\n  
\n
\n
Returns
number of leading zeros in value 
\n\n
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void __DMB (void )
\n
\n
This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. 
\n\n
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void __DSB (void )
\n
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This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. 
\n\n
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void __ISB (void )
\n
\n
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. 
\n\n
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uint8_t __LDREXB (volatile uint8_t * addr)
\n
\n
This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n  
[in]*addrPointer to data 
\n  
\n
\n
Returns
value of type uint8_t at (*addr) 
\n\n
\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint16_t __LDREXH (volatile uint16_t * addr)
\n
\n
This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n  
[in]*addrPointer to data 
\n  
\n
\n
Returns
value of type uint16_t at (*addr) 
\n\n
\n
\n\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __LDREXW (volatile uint32_t * addr)
\n
\n
This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n  
[in]*addrPointer to data 
\n  
\n
\n
Returns
value of type uint32_t at (*addr) 
\n\n
\n
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void __NOP (void )
\n
\n
This function does nothing. This instruction can be used for code alignment purposes. 
\n\n
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uint32_t __RBIT (uint32_t value)
\n
\n
This function reverses the bit order of the given value [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n  
[in]valueValue to reverse 
\n  
\n
\n
Returns
Reversed value 
\n\n
\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __REV (uint32_t value)
\n
\n
This function reverses the byte order in integer value.
\n
Parameters
\n  \n    \n  
[in]valueValue to reverse 
\n  
\n
\n
Returns
Reversed value 
\n\n
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uint32_t __REV16 (uint32_t value)
\n
\n
This function reverses the byte order in two unsigned short values.\n
Parameters
\n  \n    \n  
[in]valueValue to reverse 
\n  
\n
\n
Returns
Reversed value 
\n
Note
The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example: 
#ifndef __NO_EMBEDDED_ASM
\n
        __REV16(0x1);
\n
#endif
\n
 
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int32_t __REVSH (int32_t value)
\n
\n
This function reverses the byte order in a signed short value with sign extension to integer.\n
Parameters
\n  \n    \n  
[in]valueValue to reverse 
\n  
\n
\n
Returns
Reversed value 
\n
Note
The function can be disabled by defining the compile time flag __NO_EMBEDDED_ASM. This rule applies to the ARM toolchain. For example: 
#ifndef __NO_EMBEDDED_ASM
\n
        __REVSH(0x1);
\n
#endif
\n
 
\n\n
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uint32_t __ROR (uint32_t value, 
uint32_t shift 
)
\n
\n
This function rotates a value right by a specified number of bits.
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to be shifted right 
[in]shiftNumber of bits in the range [1..31] 
\n  
\n
\n
Returns
Rotated value 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __SEV (void )
\n
\n
Send Event is a hint instruction. It causes an event to be signaled to the CPU. 
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uint32_t __SSAT (unint32_t value, 
uint32_t sat 
)
\n
\n
This function saturates a signed value [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to be saturated 
[in]satBit position to saturate to [1..32] 
\n  
\n
\n
Returns
Saturated value 
\n\n
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uint32_t __STREXB (uint8_t value, 
volatile uint8_t * addr 
)
\n
\n
This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to store 
[in]*addrPointer to location 
\n  
\n
\n
Returns
0 Function succeeded 
\n
\n1 Function failed 
\n\n
\n
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uint32_t __STREXH (uint16_t value, 
volatile uint16_t * addr 
)
\n
\n
This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to store 
[in]*addrPointer to location 
\n  
\n
\n
Returns
0 Function succeeded 
\n
\n1 Function failed 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __STREXW (uint32_t value, 
volatile uint32_t * addr 
)
\n
\n
This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to store 
[in]*addrPointer to location 
\n  
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\n
Returns
0 Function succeeded 
\n
\n1 Function failed 
\n\n
\n
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uint32_t __USAT (uint32_t value, 
uint32_t sat 
)
\n
\n
This function saturates an unsigned value [not for Cortex-M0 variants].
\n
Parameters
\n  \n    \n    \n  
[in]valueValue to be saturated 
[in]satBit position to saturate to [0..31] 
\n  
\n
\n
Returns
Saturated value 
\n\n
\n
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\n
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void __WFE (void )
\n
\n
Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: 
\n
    \n
  • If the event register is 0, then WFE suspends execution until one of the following events occurs:
      \n
    • An exception, unless masked by the exception mask registers or the current priority level.
      • \n
    • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
      • \n
    • A Debug Entry request, if Debug is enabled.
      • \n
    • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
      • \n
    \n
    • \n
\n
    \n
  • If the event register is 1, then WFE clears it to 0 and returns immediately. 
    • \n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void __WFI (void )
\n
\n
WFI is a hint instruction that suspends execution until one of the following events occurs:
\n
    \n
  • A non-masked interrupt occurs and is taken.
    • \n
  • An interrupt masked by PRIMASK becomes pending.
    • \n
  • A Debug Entry request. 
    • \n
\n\n
\n
\n
\n
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\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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    "content": "\n\n\n\n\nCMSIS-CORE: Intrinsic Functions for SIMD Instructions [only Cortex-M4]\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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\nFunctions  
\n  
\n
Intrinsic Functions for SIMD Instructions [only Cortex-M4]
  
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Access to dedicated SIMD instructions.  \nMore...
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\nFunctions
uint32_t __SADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed addition.  More...
 
uint32_t __QADD8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating addition.  More...
 
uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed addition with halved results.  More...
 
uint32_t __UADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned addition.  More...
 
uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating addition.  More...
 
uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned addition with halved results.  More...
 
uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed subtraction.  More...
 
uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating subtract.  More...
 
uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed subtraction with halved results.  More...
 
uint32_t __USUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned subtract.  More...
 
uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating subtraction.  More...
 
uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned subtraction with halved results.  More...
 
uint32_t __SADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed addition.  More...
 
uint32_t __QADD16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating addition.  More...
 
uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition with halved results.  More...
 
uint32_t __UADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition.  More...
 
uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition.  More...
 
uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition with halved results.  More...
 
uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction.  More...
 
uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating subtract.  More...
 
uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction with halved results.  More...
 
uint32_t __USUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract.  More...
 
uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction.  More...
 
uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction with halved results.  More...
 
uint32_t __SASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit addition and subtraction with exchange.  More...
 
uint32_t __QASX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit add and subtract with exchange.  More...
 
uint32_t __SHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition and subtraction with halved results.  More...
 
uint32_t __UASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition and subtraction with exchange.  More...
 
uint32_t __UQASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition and subtraction with exchange.  More...
 
uint32_t __UHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition and subtraction with halved results and exchange.  More...
 
uint32_t __SSAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction and addition with exchange.  More...
 
uint32_t __QSAX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit subtract and add with exchange.  More...
 
uint32_t __SHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction and addition with halved results.  More...
 
uint32_t __USAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract and add with exchange.  More...
 
uint32_t __UQSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction and addition with exchange.  More...
 
uint32_t __UHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction and addition with halved results and exchange.  More...
 
uint32_t __USAD8 (uint32_t val1, uint32_t val2)
 Unsigned sum of quad 8-bit unsigned absolute difference.  More...
 
uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
 Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.  More...
 
uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit saturate.  More...
 
uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit unsigned saturate.  More...
 
uint32_t __UXTB16 (uint32_t val)
 Dual extract 8-bits and zero-extend to 16-bits.  More...
 
uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
 Extracted 16-bit to 32-bit unsigned addition.  More...
 
uint32_t __SXTB16 (uint32_t val)
 Dual extract 8-bits and sign extend each to 16-bits.  More...
 
uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
 Dual extracted 8-bit to 16-bit signed addition.  More...
 
uint32_t __SMUAD (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply.  More...
 
uint32_t __SMUADX (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply with exchange.  More...
 
uint32_t __SMMLA (int32_t val1, int32_t val2, int32_t val3)
 32-bit signed multiply with 32-bit truncated accumulator.  More...
 
uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with single 32-bit accumulator.  More...
 
uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.  More...
 
uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
 Dual 16-bit signed multiply with single 64-bit accumulator.  More...
 
unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Dual 16-bit signed multiply with exchange with single 64-bit accumulator.  More...
 
uint32_t __SMUSD (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply returning difference.  More...
 
uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply with exchange returning difference.  More...
 
uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply subtract with 32-bit accumulate.  More...
 
uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.  More...
 
uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
 Q setting dual 16-bit signed multiply subtract with 64-bit accumulate.  More...
 
unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.  More...
 
uint32_t __SEL (uint32_t val1, uint32_t val2)
 Select bytes based on GE bits.  More...
 
uint32_t __QADD (uint32_t val1, uint32_t val2)
 Q setting saturating add.  More...
 
uint32_t __QSUB (uint32_t val1, uint32_t val2)
 Q setting saturating subtract.  More...
 
uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3.  More...
 
uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3.  More...
 
\n
Description
\n
Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.
\n
SIMD Features:
\n
    \n
  • Simultaneous computation of 2x16-bit or 4x8-bit operands
    • \n
  • Fractional arithmetic
    • \n
  • User definable saturation modes (arbitrary word-width)
    • \n
  • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
    • \n
  • Simultaneous 8/16-bit select operations
    • \n
  • Performance up to 3.2 GOPS at 800MHz
    • \n
  • Performance is achieved with a \"near zero\" increase in power consumption on a typical implementation
    • \n
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Examples: 
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Addition: Add two values using SIMD function
\n
uint32_t add_halfwords(uint32_t val1, uint32_t val2)
\n
{
\n
  return __SADD16(val1, val2);
\n
}
\n
Subtraction: Subtract two values using SIMD function
\n
uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
\n
{
\n
  return __SSUB16(val1, val2);
\n
}
\n
Multiplication: Performing a multiplication using SIMD function
\n
uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
\n
{
\n
  return __SMUAD(val1, val2);
\n
}
\n
 
Function Documentation
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uint32_t __PKHBT (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands 
val2second 16-bit operands 
val3value for left-shifting val2. Value range [0..31].
\n  
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Returns
the combination of halfwords.
\n
Operation:
res[15:0]  = val1[15:0]
\n
res[31:16] = val2[31:16]<<val3 
\n
 
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uint32_t __PKHTB (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.
\n
Parameters
\n  \n    \n    \n    \n  
val1second 16-bit operands 
val2first 16-bit operands 
val3value for right-shifting val2. Value range [1..32].
\n  
\n
\n
Returns
the combination of halfwords.
\n
Operation:
res[15:0]  = val2[15:0]>>val3
\n
res[31:16] = val1[31:16] 
\n
 
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uint32_t __QADD (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to obtain the saturating add of two integers.
\n The Q bit is set if the operation saturates.
\n
Parameters
\n  \n    \n    \n  
val1first summand of the saturating add operation. 
val2second summand of the saturating add operation.
\n  
\n
\n
Returns
the saturating addition of val1 and val2.
\n
Operation:
res[31:0] = SAT(val1 + SAT(val2 * 2))
\n
 
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uint32_t __QADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands. 
val2second two 16-bit summands.
\n  
\n
\n
Returns
    \n
  • the saturated addition of the low halfwords, in the low halfword of the return value. 
    • \n
  • the saturated addition of the high halfwords, in the high halfword of the return value.
    • \n
\n
\n
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0]
\n
res[31:16] = val1[31:16] + val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1. 
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands. 
val2second four 8-bit summands.
\n  
\n
\n
Returns
    \n
  • the saturated addition of the first byte of each operand in the first byte of the return value. 
    • \n
  • the saturated addition of the second byte of each operand in the second byte of the return value. 
    • \n
  • the saturated addition of the third byte of each operand in the third byte of the return value. 
    • \n
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value. 
    • \n
\n
\n
The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0] 
\n
res[15:8]  = val1[15:8]  + val2[15:8] 
\n
res[23:16] = val1[23:16] + val2[23:16] 
\n
res[31:24] = val1[31:24] + val2[31:24]          
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
\n  
\n
\n
Returns
    \n
  • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • \n
\n
\n
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  - val2[31:16]   
\n
res[31:16] = val1[31:16] + val2[15:0]  
\n
 
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\n
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QSAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
\n  
\n
\n
Returns
    \n
  • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. 
    • \n
  • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. 
    • \n
\n
\n
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  + val2[31:16]
\n
res[31:16] = val1[31:16] - val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QSUB (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to obtain the saturating subtraction of two integers.
\n The Q bit is set if the operation saturates.
\n
Parameters
\n  \n    \n    \n  
val1minuend of the saturating subtraction operation. 
val2subtrahend of the saturating subtraction operation.
\n  
\n
\n
Returns
the saturating subtraction of val1 and val2.
\n
Operation:
res[31:0] = SAT(val1 - SAT(val2 * 2))
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QSUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands. 
val2second two 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. 
    • \n
  • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • \n
\n
\n
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]
\n
res[31:16] = val1[31:16] - val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __QSUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands. 
val2second four 8-bit operands.
\n  
\n
\n
Returns
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0] 
\n
res[15:8]  = val1[15:8]  - val2[15:8]
\n
res[23:16] = val1[23:16] - val2[23:16]
\n
res[31:24] = val1[31:24] - val2[31:24]
\n
 
\n\n
\n
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed integer additions.
\n The GE bits in the APSR are set according to the results of the additions.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands. 
val2second two 16-bit summands.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfwords in the low halfword of the return value. 
    • \n
  • the addition of the high halfwords in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0]
\n
res[31:16] = val1[31:16] + val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. 
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands. 
val2second four 8-bit summands.
\n  
\n
\n
Returns
    \n
  • the addition of the first bytes from each operand, in the first byte of the return value. 
    • \n
  • the addition of the second bytes of each operand, in the second byte of the return value. 
    • \n
  • the addition of the third bytes of each operand, in the third byte of the return value. 
    • \n
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value. 
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 
    • \n
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • \n
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • \n
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0] 
\n
res[15:8]  = val1[15:8]  + val2[15:8] 
\n
res[23:16] = val1[23:16] + val2[23:16] 
\n
res[31:24] = val1[31:24] + val2[31:24]          
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
\n The GE bits in the APRS are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
\n  
\n
\n
Returns
    \n
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[31:16]   
\n
res[31:16] = val1[31:16] + val2[15:0]  
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SEL (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.
\n
Parameters
\n  \n    \n    \n  
val1four selectable 8-bit values. 
val2four selectable 8-bit values.
\n  
\n
\n
Returns
The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria: 
    \n
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] 
    • \n
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] 
    • \n
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] 
    • \n
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] 
    • \n
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two signed 16-bit integer additions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands. 
val2second two 16-bit summands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the low halfwords, in the low halfword of the return value. 
    • \n
  • the halved addition of the high halfwords, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0]  >> 1
\n
res[31:16] = val1[31:16] + val2[31:16] >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four signed 8-bit integer additions, halving the results. 
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands. 
val2second four 8-bit summands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the first bytes from each operand, in the first byte of the return value. 
    • \n
  • the halved addition of the second bytes from each operand, in the second byte of the return value. 
    • \n
  • the halved addition of the third bytes from each operand, in the third byte of the return value. 
    • \n
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0]  >> 1
\n
res[15:8]  = val1[15:8]  + val2[15:8] >> 1
\n
res[23:16] = val1[23:16] + val2[23:16] >> 1
\n
res[31:24] = val1[31:24] + val2[31:24] >> 1         
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands. 
val2second 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1  
\n
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHSAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands. 
val2second 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • \n
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
\n
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHSUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two signed 16-bit integer subtractions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands. 
val2second two 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. 
    • \n
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
\n
res[31:16] = val1[31:16] - val2[31:16]  >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SHSUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four signed 8-bit integer subtractions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands. 
val2second four 8-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0]   >> 1
\n
res[15:8]  = val1[15:8]  - val2[15:8]  >> 1
\n
res[23:16] = val1[23:16] - val2[23:16] >> 1
\n
res[31:24] = val1[31:24] - val2[31:24] >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMLAD (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
\n The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the product of each multiplication added to the accumulate value, as a 32-bit integer.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
res[31:0] = p1 + p2 + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMLADX (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
\n The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
res[31:0] = p1 + p2 + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint64_t __SMLALD (uint32_t val1, 
uint32_t val2, 
uint64_t val3 
)
\n
\n
This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the product of each multiplication added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
sum = p1 + p2 + val3[63:32][31:0]
\n
res[63:32] = sum[63:32]
\n
res[31:0]  = sum[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
unsigned long long __SMLALDX (uint32_t val1, 
uint32_t val2, 
unsigned long long val3 
)
\n
\n
This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the product of each multiplication added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
sum = p1 + p2 + val3[63:32][31:0]
\n
res[63:32] = sum[63:32]
\n
res[31:0] = sum[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMLSD (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
\n The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the difference of the product of each multiplication, added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
res[31:0] = p1 - p2 + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMLSDX (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
\n The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the difference of the product of each multiplication, added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
res[31:0] = p1 - p2 + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint64_t __SMLSLD (uint32_t val1, 
uint32_t val2, 
uint64_t val3 
)
\n
\n
This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the difference of the product of each multiplication, added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
res[63:0] = p1 - p2 + val3[63:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
unsigned long long __SMLSLDX (uint32_t val1, 
uint32_t val2, 
unsigned long long val3 
)
\n
\n
This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.
\n
Parameters
\n  \n    \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the difference of the product of each multiplication, added to the accumulate value.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
res[63:0] = p1 - p2 + val3[63:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMMLA (int32_t val1, 
int32_t val2, 
int32_t val3 
)
\n
\n
This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
\n
\n
Parameters
\n  \n    \n    \n    \n  
val1first operand for multiplication. 
val2second operand for multiplication. 
val3accumulate value.
\n  
\n
\n
Returns
the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
\n
Operation:
p = val1 * val2
\n
res[31:0] = p[61:32] + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMUAD (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed multiplications, adding the products together.
\n The Q bit is set if the addition overflows.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.
\n  
\n
\n
Returns
the sum of the products of the two 16-bit signed multiplications.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
res[31:0] = p1 + p2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMUADX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
\n The Q bit is set if the addition overflows.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.
\n  
\n
\n
Returns
the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
res[31:0] = p1 + p2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMUSD (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.
\n  
\n
\n
Returns
the difference of the products of the two 16-bit signed multiplications.
\n
Operation:
p1 = val1[15:0]  * val2[15:0]
\n
p2 = val1[31:16] * val2[31:16]
\n
res[31:0] = p1 - p2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SMUSDX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operands for each multiplication. 
val2second 16-bit operands for each multiplication.
\n  
\n
\n
Returns
the difference of the products of the two 16-bit signed multiplications.
\n
Operation:
p1 = val1[15:0]  * val2[31:16]
\n
p2 = val1[31:16] * val2[15:0]
\n
res[31:0] = p1 - p2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SSAT16 (uint32_t val1, 
const uint32_t val2 
)
\n
\n
This function enables you to saturate two signed 16-bit values to a selected signed range.
\n The Q bit is set if either operation saturates.
\n
Parameters
\n  \n    \n    \n  
val1two signed 16-bit values to be saturated. 
val2bit position for saturation, an integral constant expression in the range 1 to 16.
\n  
\n
\n
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value: 
    \n
  • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. 
    • \n
  • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • \n
\n
\n
Operation:
Saturate halfwords in val1 to the signed range specified by the bit position in val2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SSAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[31:16]
\n
res[31:16] = val1[31:16] - val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SSUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit signed integer subtractions.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands of each subtraction. 
val2second two 16-bit operands of each subtraction.
\n  
\n
\n
Returns
    \n
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If
    \n
  • res is the return value, then: 
    • \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]
\n
res[31:16] = val1[31:16] - val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SSUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four 8-bit signed integer subtractions.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands of each subtraction. 
val2second four 8-bit operands of each subtraction.
\n  
\n
\n
Returns
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
the results of the operation.
\n
If res is the return value, then: 
    \n
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 
    • \n
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • \n
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • \n
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0] 
\n
res[15:8]  = val1[15:8]  - val2[15:8]
\n
res[23:16] = val1[23:16] - val2[23:16]
\n
res[31:24] = val1[31:24] - val2[31:24]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __SXTAB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.
\n
Parameters
\n  \n    \n    \n  
val1values added to the zero-extended to 16-bit values. 
val2two 8-bit values to be extracted and zero-extended.
\n  
\n
\n
Returns
the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
\n
Operation:
res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
\n
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __SXTB16 (uint32_t val)
\n
\n
This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.
\n
Parameters
\n  \n    \n  
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\n  
\n
\n
Returns
the 8-bit values sign-extended to 16-bit values. 
    \n
  • sign-extended value of val[7:0] in the low halfword of the return value. 
    • \n
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = SignExtended(val[7:0]
\n
res[31:16] = SignExtended(val[23:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit unsigned integer additions.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands for each addition. 
val2second two 16-bit summands for each addition.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfwords in each operand, in the low halfword of the return value. 
    • \n
  • the addition of the high halfwords in each operand, in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 
    • \n
  • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0] 
\n
res[31:16] = val1[31:16] + val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands for each addition. 
val2second four 8-bit summands for each addition.
\n  
\n
\n
Returns
    \n
  • the halved addition of the first bytes from each operand, in the first byte of the return value. 
    • \n
  • the halved addition of the second bytes from each operand, in the second byte of the return value. 
    • \n
  • the halved addition of the third bytes from each operand, in the third byte of the return value. 
    • \n
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
\n
If res is the return value, then: 
    \n
  • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 
    • \n
  • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 
    • \n
  • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 
    • \n
  • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0] 
\n
res[15:8]  = val1[15:8]  + val2[15:8]
\n
res[23:16] = val1[23:16] + val2[23:16]
\n
res[31:24] = val1[31:24] + val2[31:24]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
\n  
\n
\n
Returns
    \n
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
\n
If res is the return value, then:
    \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[31:16]
\n
res[31:16] = val1[31:16] + val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two unsigned 16-bit integer additions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands. 
val2second two 16-bit summands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the low halfwords in each operand, in the low halfword of the return value. 
    • \n
  • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0]   >> 1
\n
res[31:16] = val1[31:16] + val2[31:16]  >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit integer additions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands. 
val2second four 8-bit summands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the first bytes in each operand, in the first byte of the return value. 
    • \n
  • the halved addition of the second bytes in each operand, in the second byte of the return value. 
    • \n
  • the halved addition of the third bytes in each operand, in the third byte of the return value. 
    • \n
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0]   >> 1
\n
res[15:8]  = val1[15:8]  + val2[15:8]  >> 1
\n
res[23:16] = val1[23:16] + val2[23:16] >> 1
\n
res[31:24] = val1[31:24] + val2[31:24] >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. 
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. 
    • \n
  • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
    • \n
\n
\n
Operation:
res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
\n
res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHSAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
\n  
\n
\n
Returns
    \n
  • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
\n
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHSUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands. 
val2second two 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]   >> 1
\n
res[31:16] = val1[31:16] - val2[31:16]  >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UHSUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands. 
val2second four 8-bit operands.
\n  
\n
\n
Returns
    \n
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0]    >> 1
\n
res[15:8]  = val1[15:8]  - val2[15:8]   >> 1
\n
res[23:16] = val1[23:16] - val2[23:16]  >> 1
\n
res[31:24] = val1[31:24] - val2[31:24]  >> 1
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQADD16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit summands. 
val2second two 16-bit summands.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. 
    • \n
  • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
    • \n
\n
\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  + val2[15:0] 
\n
res[31:16] = val1[31:16] + val2[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQADD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit summands. 
val2second four 8-bit summands.
\n  
\n
\n
Returns
    \n
  • the halved addition of the first bytes in each operand, in the first byte of the return value. 
    • \n
  • the halved addition of the second bytes in each operand, in the second byte of the return value. 
    • \n
  • the halved addition of the third bytes in each operand, in the third byte of the return value. 
    • \n
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • \n
\n
\n
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
\n
Operation:
res[7:0]   = val1[7:0]   + val2[7:0] 
\n
res[15:8]  = val1[15:8]  + val2[15:8]
\n
res[23:16] = val1[23:16] + val2[23:16]
\n
res[31:24] = val1[31:24] + val2[31:24]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQASX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands. 
val2second two 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  - val2[31:16]
\n
res[31:16] = val1[31:16] + val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQSAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. 
val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • \n
\n
\n
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  + val2[31:16]
\n
res[31:16] = val1[31:16] - val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQSUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands for each subtraction. 
val2second two 16-bit operands for each subtraction.
\n  
\n
\n
Returns
    \n
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]   
\n
res[31:16] = val1[31:16] - val2[31:16]  
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __UQSUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands. 
val2second four 8-bit operands.
\n  
\n
\n
Returns
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0]
\n
res[15:8]  = val1[15:8]  - val2[15:8]
\n
res[23:16] = val1[23:16] - val2[23:16]
\n
res[31:24] = val1[31:24] - val2[31:24]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __USAD8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands for the subtractions. 
val2second four 8-bit operands for the subtractions.
\n  
\n
\n
Returns
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. 
    • \n
\n
\n
The sum is returned as a single unsigned integer.
\n
Operation:
absdiff1  = val1[7:0]   - val2[7:0]
\n
absdiff2  = val1[15:8]  - val2[15:8]
\n
absdiff3  = val1[23:16] - val2[23:16]
\n
absdiff4  = val1[31:24] - val2[31:24]
\n
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __USADA8 (uint32_t val1, 
uint32_t val2, 
uint32_t val3 
)
\n
\n
This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.
\n
Parameters
\n  \n    \n    \n    \n  
val1first four 8-bit operands for the subtractions. 
val2second four 8-bit operands for the subtractions. 
val3accumulation value.
\n  
\n
\n
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value: 
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • \n
\n
\n
Operation:
absdiff1  = val1[7:0]   - val2[7:0]
\n
absdiff2  = val1[15:8]  - val2[15:8]
\n
absdiff3  = val1[23:16] - val2[23:16]
\n
absdiff4  = val1[31:24] - val2[31:24]
\n
sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
\n
res[31:0] = sum[31:0] + val3[31:0]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __USAT16 (uint32_t val1, 
const uint32_t val2 
)
\n
\n
This function enables you to saturate two signed 16-bit values to a selected unsigned range.
\n The Q bit is set if either operation saturates.
\n
Parameters
\n  \n    \n    \n  
val1two 16-bit values that are to be saturated. 
val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.
\n  
\n
\n
Returns
the saturation of the two signed 16-bit values, as non-negative values. 
    \n
  • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value. 
    • \n
  • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • \n
\n
\n
Operation:
Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __USAX (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. 
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
\n  
\n
\n
Returns
    \n
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. 
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. 
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  + val2[31:16]
\n
res[31:16] = val1[31:16] - val2[15:0] 
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
uint32_t __USUB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform two 16-bit unsigned integer subtractions.
\n The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first two 16-bit operands. 
val2second two 16-bit operands.
\n  
\n
\n
Returns
    \n
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. 
    • \n
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
\n
If res is the return value, then: 
    \n
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 
    • \n
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • \n
\n
\n
Operation:
res[15:0]  = val1[15:0]  - val2[15:0]   
\n
res[31:16] = val1[31:16] - val2[31:16]  
\n
 
\n\n
\n
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uint32_t __USUB8 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.
\n
Parameters
\n  \n    \n    \n  
val1first four 8-bit operands. 
val2second four 8-bit operands.
\n  
\n
\n
Returns
    \n
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. 
    • \n
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. 
    • \n
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. 
    • \n
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • \n
\n
\n
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
\n
If res is the return value, then: 
    \n
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 
    • \n
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 
    • \n
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 
    • \n
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • \n
\n
\n
Operation:
res[7:0]   = val1[7:0]   - val2[7:0]
\n
res[15:8]  = val1[15:8]  - val2[15:8]
\n
res[23:16] = val1[23:16] - val2[23:16]
\n
res[31:24] = val1[31:24] - val2[31:24]
\n
 
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uint32_t __UXTAB16 (uint32_t val1, 
uint32_t val2 
)
\n
\n
This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.
\n
Parameters
\n  \n    \n    \n  
val1value added to the zero-extended to 16-bit values. 
val2two 8-bit values to be extracted and zero-extended.
\n  
\n
\n
Returns
the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
\n
Operation:
res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
\n
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
\n
 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t __UXTB16 (uint32_t val)
\n
\n
This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.
\n
Parameters
\n  \n    \n  
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
\n  
\n
\n
Returns
the 8-bit values zero-extended to 16-bit values. 
    \n
  • zero-extended value of val[7:0] in the low halfword of the return value. 
    • \n
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • \n
\n
\n
Operation:
res[15:0]  = ZeroExtended(val[7:0]  )
\n
res[31:16] = ZeroExtended(val[23:16])
\n
 
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\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group__peripheral__gr.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Peripheral Access\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
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\n
Peripheral Access
  
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\n\n
Describes naming conventions, requirements, and optional features for accessing peripherals.  \nMore...
\n
Each peripheral provides a data type definition with a name that is composed of a prefix <device abbreviation>_ and the <peripheral name>_, for example LPC_UART for the device LPC and the peripheral UART. The intention is to avoid name collisions caused by short names. If more peripherals exist of the same type, identifiers have a postfix consisting of a digit or letter, for example LPC_UART0, LPC_UART1.
\n
    \n
  • The data type definition uses the standard C data types from the ANSI C header file <stdint.h>. IO Type Qualifiers are used to specify the access to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of debug information of peripheral registers and are defined as shown below:
    \n 
    #define   __I     volatile const       
    \n
    #define   __O     volatile             
    \n
    #define   __IO    volatile             
    \n
    • \n
\n
    \n
  • The following typedef is an example for a UART. <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels in a device. 
    \n 
    typedef struct
    \n
    {
    \n
      union {
    \n
      __I  uint8_t  RBR;                  /* Offset: 0x000 (R/ )  Receiver Buffer Register            */
    \n
      __O  uint8_t  THR;                  /* Offset: 0x000 ( /W)  Transmit Holding Register           */
    \n
      __IO uint8_t  DLL;                  /* Offset: 0x000 (R/W)  Divisor Latch LSB                   */
    \n
           uint32_t RESERVED0;
    \n
      };
    \n
      union {
    \n
      __IO uint8_t  DLM;                  /* Offset: 0x004 (R/W)  Divisor Latch MSB                   */
    \n
      __IO uint32_t IER;                  /* Offset: 0x004 (R/W)  Interrupt Enable Register           */
    \n
      };
    \n
      union {
    \n
      __I  uint32_t IIR;                  /* Offset: 0x008 (R/ )  Interrupt ID Register               */
    \n
      __O  uint8_t  FCR;                  /* Offset: 0x008 ( /W)  FIFO Control Register               */
    \n
      };
    \n
      __IO uint8_t  LCR;                  /* Offset: 0x00C (R/W)  Line Control Register               */
    \n
           uint8_t  RESERVED1[7];
    \n
      __I  uint8_t  LSR;                  /* Offset: 0x014 (R/ )  Line Status Register                */
    \n
           uint8_t  RESERVED2[7];
    \n
      __IO uint8_t  SCR;                  /* Offset: 0x01C (R/W)  Scratch Pad Register                */
    \n
           uint8_t  RESERVED3[3];
    \n
      __IO uint32_t ACR;                  /* Offset: 0x020 (R/W)  Autobaud Control Register           */
    \n
      __IO uint8_t  ICR;                  /* Offset: 0x024 (R/W)  IrDA Control Register               */
    \n
           uint8_t  RESERVED4[3];
    \n
      __IO uint8_t  FDR;                  /* Offset: 0x028 (R/W)  Fractional Divider Register         */
    \n
           uint8_t  RESERVED5[7];
    \n
      __IO uint8_t  TER;                  /* Offset: 0x030 (R/W)  Transmit Enable Register            */
    \n
           uint8_t  RESERVED6[39];
    \n
      __I  uint8_t  FIFOLVL;              /* Offset: 0x058 (R/ )  FIFO Level Register                 */
    \n
    } LPC_UART_TypeDef;
    \n
    • \n
\n
    \n
  • To access the registers of the UART defined above, pointers to a register structure are defined. In this example <device abbreviation>_UART# are two pointers to UARTs defined with above register structure. 
    \n 
    #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
    \n
    #define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    \n
    • \n
\n
    \n
  • The registers in the various UARTs can now be referred in the user code as shown below:
    \n 
    LPC_UART1->DR   // is the data register of UART1.
    \n
    • \n
\n
\n
\nMinimal Requirements
\n
To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum: 
\n
\n
\n
    \n
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. 
    \n
    \n Example: 
    typedef struct
    \n
    {
    \n
      __IO uint32_t CTRL;                 /* Offset: 0x000 (R/W)  SysTick Control and Status Register */
    \n
      __IO uint32_t LOAD;                 /* Offset: 0x004 (R/W)  SysTick Reload Value Register       */
    \n
      __IO uint32_t VAL;                  /* Offset: 0x008 (R/W)  SysTick Current Value Register      */
    \n
      __I  uint32_t CALIB;                /* Offset: 0x00C (R/ )  SysTick Calibration Register        */
    \n
    } SysTick_Type;
    \n
    • \n
\n
    \n
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined). 
    \n
    \n Example: 
    #define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address     */    
    \n
    • \n
\n
    \n
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2). 
    \n
    \n Example: 
    #define SysTick ((SysTick_Type *) Systick_BASE)    /* SysTick access definition */
    \n
    • \n
\n
These definitions allow accessing peripheral registers with simple assignments.
\n
Example: 
\n 
\n
SysTick->CTRL = 0;    
\n
\n
\nOptional Features
\n
Optionally, the file device.h may define:
\n
    \n
  • #define constants, which simplify access to peripheral registers. These constants define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for such #define constants.
    • \n
\n
    \n
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_. 
    • \n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/group__system__init__gr.html",
    "content": "\n\n\n\n\nCMSIS-CORE: System and Clock Configuration\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
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\nFunctions |\nVariables  
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System and Clock Configuration
  
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\n\n\n\n\n\n\n\n\n
\nFunctions
void SystemInit (void)
 Function to Initialize the system.  More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock.  More...
 
\n\n\n\n\n
\nVariables
uint32_t SystemCoreClock
 Variable to hold the system core clock value.  More...
 
\n
Description
\n
ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by \nthe silicon vendor to match their actual device. As a <b>minimum requirement</b>, \nthis file must provide:\n-  A device-specific system configuration function, \\ref SystemInit().\n-  A global variable that contains the system frequency, \\ref SystemCoreClock. \n\nThe file configures the device and, typically, initializes the oscillator (PLL) that is part \nof the microcontroller device. This file might export other functions or variables that provide \na more flexible configuration of the microcontroller system.\n
\nCode Example
\n
The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.
\n
#include "LPC17xx.h"
\n
\n
uint32_t coreClock_1 = 0;                       /* Variables to store core clock values */
\n
uint32_t coreClock_2 = 0;
\n
\n
\n
int main (void)  {
\n
\n
  coreClock_1 = SystemCoreClock;                /* Store value of predefined SystemCoreClock */
\n
\n
  SystemCoreClockUpdate();                      /* Update SystemCoreClock according to register settings */
\n
\n
  coreClock_2 = SystemCoreClock;                /* Store value of calculated SystemCoreClock */
\n
\n
  if (coreClock_2 != coreClock_1)  {            /* Without changing the clock setting both core clock values should be the same */ 
\n
    // Error Handling
\n
  }
\n
\n
  while(1);
\n
}
\n
 
Function Documentation
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void SystemCoreClockUpdate (void )
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Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. 
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void SystemInit (void )
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Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device. 
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Variable Documentation
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uint32_t SystemCoreClock
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Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.
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Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. 
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  },
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    "path": "Libraries/CMSIS/Documentation/Core/html/index.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Overview\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
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CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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Overview 
  
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CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:
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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
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This chapter provides details about the CMSIS-CORE and contains the following sections:
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\nCortex-M Reference Manuals
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The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.
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\nTested and Verified Toolchains
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The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:
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  • ARM: MDK-ARM Version 4.70 (or greater)
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  • GNU: GNU Tools ARM Embedded 4.7 2012.q4 (or greater)
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  • GNU: Sourcery G++ Lite Edition for ARM 2011.03-42 (or greater)
    • \n
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10 (or greater)
    • \n
\n
\n
Revision History of CMSIS-CORE
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Version Description  
V3.20 Added: __BKPT instruction intrinsic.
\n Added: __SMMLA instruction intrinsic for Cortex-M4.
\n Corrected: ITM_SendChar.
\n Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
\n Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
\n   
V3.01 Added support for Cortex-M0+ processor. 
\n Integration of CMSIS DSP Library version 1.1.0 
\n   
V3.00 Added support for GNU GCC ARM Embedded Compiler. 
\n Added function __ROR.
\n Added Register Mapping for TPIU, DWT. 
\n Added support for SC000 and SC300 processors.
\n Corrected ITM_SendChar function. 
\n Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section. 
\n Documentation restructured.   
V2.10 Updated documentation.
\n Updated CMSIS core include files.
\n Changed CMSIS/Device folder structure.
\n Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
\n Reworked CMSIS DSP library examples.   
V2.00 Added support for Cortex-M4 processor.  
V1.30 Reworked Startup Concept.
\n Added additional Debug Functionality.
\n Changed folder structure.
\n Added doxygen comments.
\n Added definitions for bit.   
V1.01 Added support for Cortex-M0 processor.  
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX  
V1.00 Initial Release for Cortex-M3 processor.  
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
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d=c.toLowerCase();f.fn[\"inner\"+c]=function(){var a=this[0];return a?a.style?parseFloat(f.css(a,d,\"padding\")):this[d]():null},f.fn[\"outer\"+c]=function(a){var b=this[0];return b?b.style?parseFloat(f.css(b,d,a?\"margin\":\"border\")):this[d]():null},f.fn[d]=function(a){var e=this[0];if(!e)return a==null?null:this;if(f.isFunction(a))return this.each(function(b){var c=f(this);c[d](a.call(this,b,c[d]()))});if(f.isWindow(e)){var g=e.document.documentElement[\"client\"+c],h=e.document.body;return e.document.compatMode===\"CSS1Compat\"&&g||h&&h[\"client\"+c]||g}if(e.nodeType===9)return Math.max(e.documentElement[\"client\"+c],e.body[\"scroll\"+c],e.documentElement[\"scroll\"+c],e.body[\"offset\"+c],e.documentElement[\"offset\"+c]);if(a===b){var i=f.css(e,d),j=parseFloat(i);return f.isNumeric(j)?j:i}return this.css(d,typeof a==\"string\"?a:a+\"px\")}}),a.jQuery=a.$=f,typeof define==\"function\"&&define.amd&&define.amd.jQuery&&define(\"jquery\",[],function(){return f})})(window);\n/*!\n * jQuery UI 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI\n */\n(function(a,b){function d(b){return!a(b).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}function c(b,c){var e=b.nodeName.toLowerCase();if(\"area\"===e){var f=b.parentNode,g=f.name,h;if(!b.href||!g||f.nodeName.toLowerCase()!==\"map\")return!1;h=a(\"img[usemap=#\"+g+\"]\")[0];return!!h&&d(h)}return(/input|select|textarea|button|object/.test(e)?!b.disabled:\"a\"==e?b.href||c:c)&&d(b)}a.ui=a.ui||{};a.ui.version||(a.extend(a.ui,{version:\"1.8.18\",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}}),a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(b,c){return typeof b==\"number\"?this.each(function(){var d=this;setTimeout(function(){a(d).focus(),c&&c.call(d)},b)}):this._focus.apply(this,arguments)},scrollParent:function(){var b;a.browser.msie&&/(static|relative)/.test(this.css(\"position\"))||/absolute/.test(this.css(\"position\"))?b=this.parents().filter(function(){return/(relative|absolute|fixed)/.test(a.curCSS(this,\"position\",1))&&/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0):b=this.parents().filter(function(){return/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0);return/fixed/.test(this.css(\"position\"))||!b.length?a(document):b},zIndex:function(c){if(c!==b)return this.css(\"zIndex\",c);if(this.length){var d=a(this[0]),e,f;while(d.length&&d[0]!==document){e=d.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){f=parseInt(d.css(\"zIndex\"),10);if(!isNaN(f)&&f!==0)return f}d=d.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(a){a.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}}),a.each([\"Width\",\"Height\"],function(c,d){function h(b,c,d,f){a.each(e,function(){c-=parseFloat(a.curCSS(b,\"padding\"+this,!0))||0,d&&(c-=parseFloat(a.curCSS(b,\"border\"+this+\"Width\",!0))||0),f&&(c-=parseFloat(a.curCSS(b,\"margin\"+this,!0))||0)});return c}var e=d===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],f=d.toLowerCase(),g={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};a.fn[\"inner\"+d]=function(c){if(c===b)return g[\"inner\"+d].call(this);return this.each(function(){a(this).css(f,h(this,c)+\"px\")})},a.fn[\"outer\"+d]=function(b,c){if(typeof b!=\"number\")return g[\"outer\"+d].call(this,b);return this.each(function(){a(this).css(f,h(this,b,!0,c)+\"px\")})}}),a.extend(a.expr[\":\"],{data:function(b,c,d){return!!a.data(b,d[3])},focusable:function(b){return c(b,!isNaN(a.attr(b,\"tabindex\")))},tabbable:function(b){var d=a.attr(b,\"tabindex\"),e=isNaN(d);return(e||d>=0)&&c(b,!e)}}),a(function(){var b=document.body,c=b.appendChild(c=document.createElement(\"div\"));c.offsetHeight,a.extend(c.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0}),a.support.minHeight=c.offsetHeight===100,a.support.selectstart=\"onselectstart\"in c,b.removeChild(c).style.display=\"none\"}),a.extend(a.ui,{plugin:{add:function(b,c,d){var e=a.ui[b].prototype;for(var f in d)e.plugins[f]=e.plugins[f]||[],e.plugins[f].push([c,d[f]])},call:function(a,b,c){var d=a.plugins[b];if(!!d&&!!a.element[0].parentNode)for(var e=0;e0)return!0;b[d]=1,e=b[d]>0,b[d]=0;return e},isOverAxis:function(a,b,c){return a>b&&a=9)&&!b.button)return this._mouseUp(b);if(this._mouseStarted){this._mouseDrag(b);return b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+\".preventClickEvent\",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery);\n/*\n * jQuery UI Resizable 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Resizables\n *\n * Depends:\n *\tjquery.ui.core.js\n *\tjquery.ui.mouse.js\n *\tjquery.ui.widget.js\n */\n(function(a,b){a.widget(\"ui.resizable\",a.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:!1,animate:!1,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:\"e,s,se\",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass(\"ui-resizable\"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||\"ui-resizable-helper\":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")})),this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css(\"resize\"),this.originalElement.css(\"resize\",\"none\"),this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"})),this.originalElement.css({margin:this.originalElement.css(\"margin\")}),this._proportionallyResize()),this.handles=c.handles||(a(\".ui-resizable-handle\",this.element).length?{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"}:\"e,s,se\");if(this.handles.constructor==String){this.handles==\"all\"&&(this.handles=\"n,e,s,w,se,sw,ne,nw\");var d=this.handles.split(\",\");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),\"se\"==f&&h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\"),this.handles[f]=\".ui-resizable-\"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=[\"padding\",/ne|nw|n/.test(c)?\"Top\":/se|sw|s/.test(c)?\"Bottom\":/^e$/.test(c)?\"Right\":\"Left\"].join(\"\");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(\".ui-resizable-handle\",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:\"se\"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass(\"ui-resizable-autohide\").hover(function(){c.disabled||(a(this).removeClass(\"ui-resizable-autohide\"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass(\"ui-resizable-autohide\"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css(\"position\"),width:c.outerWidth(),height:c.outerHeight(),top:c.css(\"top\"),left:c.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(\".ui-draggable\")||/absolute/.test(f.css(\"position\")))&&f.css({position:\"absolute\",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css(\"left\")),h=c(this.helper.css(\"top\"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio==\"number\"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(\".ui-resizable-\"+this.axis).css(\"cursor\");a(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i),f.addClass(\"ui-resizable-resizing\"),this._propagate(\"start\",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate(\"resize\",b),c.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger(\"resize\",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],\"left\")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a(\"body\").css(\"cursor\",\"auto\"),this.element.removeClass(\"ui-resizable-resizing\"),this._propagate(\"stop\",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:\"absolute\",left:this.elementOffset.left-e+\"px\",top:this.elementOffset.top-e+\"px\",zIndex:++c.zIndex}),this.helper.appendTo(\"body\").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!=\"resize\"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:\"1.8.18\"}),a.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data(\"resizable-alsoresize\",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css(\"left\"),10),top:parseInt(b.css(\"top\"),10)})})};typeof e.alsoResize==\"object\"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data(\"resizable-alsoresize\"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?[\"width\",\"height\"]:[\"width\",\"height\",\"top\",\"left\"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof 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\n  
\n
Reference
  
\n
\n
\n
Here is a list of all modules:
\n
\n\n\n\n\n\n\n\n\n
\"o\"Peripheral AccessDescribes naming conventions, requirements, and optional features for accessing peripherals
\"o\"System and Clock Configuration
\"o\"Interrupts and Exceptions (NVIC)Describes programming of interrupts and exception functions
\"o\"Core Register Access
\"o\"Intrinsic Functions for CPU Instructions
\"o\"Intrinsic Functions for SIMD Instructions [only Cortex-M4]Access to dedicated SIMD instructions
\"o\"Systick Timer (SYSTICK)Initialize and start the SysTick timer
\"\\\"Debug Access
\n\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
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    "content": "// Search script generated by doxygen\n// Copyright (C) 2009 by Dimitri van Heesch.\n\n// The code in this file is loosly based on main.js, part of Natural Docs,\n// which is Copyright (C) 2003-2008 Greg Valure\n// Natural Docs is licensed under the GPL.\n\nvar indexSectionsWithContent =\n{\n  0: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  1: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  2: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  3: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  4: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  5: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  6: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  7: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100001000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\",\n  8: \"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000101001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\"\n};\n\nvar indexSectionNames =\n{\n  0: \"all\",\n  1: \"classes\",\n  2: \"files\",\n  3: \"functions\",\n  4: \"variables\",\n  5: \"enums\",\n  6: \"enumvalues\",\n  7: \"groups\",\n  8: \"pages\"\n};\n\nfunction convertToId(search)\n{\n  var result = '';\n  for (i=0;i do a search\n    {\n      this.Search();\n    }\n  }\n\n  this.OnSearchSelectKey = function(evt)\n  {\n    var e = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 && this.searchIndex0) // Up\n    {\n      this.searchIndex--;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==13 || e.keyCode==27)\n    {\n      this.OnSelectItem(this.searchIndex);\n      this.CloseSelectionWindow();\n      this.DOMSearchField().focus();\n    }\n    return false;\n  }\n\n  // --------- Actions\n\n  // Closes the results window.\n  this.CloseResultsWindow = function()\n  {\n    this.DOMPopupSearchResultsWindow().style.display = 'none';\n    this.DOMSearchClose().style.display = 'none';\n    this.Activate(false);\n  }\n\n  this.CloseSelectionWindow = function()\n  {\n    this.DOMSearchSelectWindow().style.display = 'none';\n  }\n\n  // Performs a search.\n  this.Search = function()\n  {\n    this.keyTimeout = 0;\n\n    // strip leading whitespace\n    var searchValue = this.DOMSearchField().value.replace(/^ +/, \"\");\n\n    var code = searchValue.toLowerCase().charCodeAt(0);\n    var hexCode;\n    if (code<16) \n    {\n      hexCode=\"0\"+code.toString(16);\n    }\n    else \n    {\n      hexCode=code.toString(16);\n    }\n\n    var resultsPage;\n    var resultsPageWithSearch;\n    var hasResultsPage;\n\n    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')\n    {\n       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';\n       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);\n       hasResultsPage = true;\n    }\n    else // nothing available for this search term\n    {\n       resultsPage = this.resultsPath + '/nomatches.html';\n       resultsPageWithSearch = resultsPage;\n       hasResultsPage = false;\n    }\n\n    window.frames.MSearchResults.location = resultsPageWithSearch; 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If there is no parameter,\n    // it takes it from the URL query.\n    //\n    // Always returns true, since other documents may try to call it\n    // and that may or may not be possible.\n    this.Search = function(search)\n    {\n      if (!search) // get search word from URL\n      {\n        search = window.location.search;\n        search = search.substring(1);  // Remove the leading '?'\n        search = unescape(search);\n      }\n\n      search = search.replace(/^ +/, \"\"); // strip leading spaces\n      search = search.replace(/ +$/, \"\"); // strip trailing spaces\n      search = search.toLowerCase();\n      search = convertToId(search);\n\n      var resultRows = document.getElementsByTagName(\"div\");\n      var matches = 0;\n\n      var i = 0;\n      while (i < resultRows.length)\n      {\n        var row = resultRows.item(i);\n        if (row.className == \"SRResult\")\n        {\n          var rowMatchName = row.id.toLowerCase();\n          rowMatchName = rowMatchName.replace(/^sr\\d*_/, ''); // strip 'sr123_'\n\n          if (search.length<=rowMatchName.length && \n             rowMatchName.substr(0, search.length)==search)\n          {\n            row.style.display = 'block';\n            matches++;\n          }\n          else\n          {\n            row.style.display = 'none';\n          }\n        }\n        i++;\n      }\n      document.getElementById(\"Searching\").style.display='none';\n      if (matches == 0) // no results\n      {\n        document.getElementById(\"NoMatches\").style.display='block';\n      }\n      else // at least one result\n      {\n        document.getElementById(\"NoMatches\").style.display='none';\n      }\n      this.lastMatchCount = matches;\n      return true;\n    }\n\n    // return the first item with index index or higher that is visible\n    this.NavNext = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index++;\n      }\n      return focusItem;\n    }\n\n    this.NavPrev = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index--;\n      }\n      return focusItem;\n    }\n\n    this.ProcessKeys = function(e)\n    {\n      if (e.type == \"keydown\") \n      {\n        this.repeatOn = false;\n        this.lastKey = e.keyCode;\n      }\n      else if (e.type == \"keypress\")\n      {\n        if (!this.repeatOn)\n        {\n          if (this.lastKey) this.repeatOn = true;\n          return false; // ignore first keypress after keydown\n        }\n      }\n      else if (e.type == \"keyup\")\n      {\n        this.lastKey = 0;\n        this.repeatOn = false;\n      }\n      return this.lastKey!=0;\n    }\n\n    this.Nav = function(evt,itemIndex) \n    {\n      var e  = (evt) ? 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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/startup_s_pg.html",
    "content": "\n\n\n\n\nCMSIS-CORE: Startup File startup_<device>.s\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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Startup File startup_<device>.s 
  
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The Startup File startup_<device>.s contains:
\n
    \n
  • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
    • \n
  • The setup values for the Main Stack Pointer (MSP).
    • \n
  • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
    • \n
  • Interrupt vectors that are device specific with weak functions that implement default routines.
    • \n
\n
The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.
\n
To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.
\n
Example: 
\n
The following example shows the extension of the interrupt vector table for the LPC1100 device family.
\n
                ; External Interrupts
\n
                DCD     WAKEUP0_IRQHandler       ; 16+ 0: Wakeup PIO0.0
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                DCD     WAKEUP1_IRQHandler       ; 16+ 1: Wakeup PIO0.1
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                DCD     WAKEUP2_IRQHandler       ; 16+ 2: Wakeup PIO0.2
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                 :       :
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                 :       :
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                DCD     EINT1_IRQHandler         ; 16+30: PIO INT1
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                DCD     EINT0_IRQHandler         ; 16+31: PIO INT0
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         :  
\n
         :
\n
                EXPORT  WAKEUP0_IRQHandler       [WEAK]
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                EXPORT  WAKEUP1_IRQHandler       [WEAK]
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                EXPORT  WAKEUP2_IRQHandler       [WEAK]
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                 :       :
\n
                 :       :                                               
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                EXPORT  EINT1_IRQHandler         [WEAK]
\n
                EXPORT  EINT0_IRQHandler         [WEAK]
\n
\n
WAKEUP0_IRQHandler
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WAKEUP1_IRQHandler
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WAKEUP1_IRQHandler
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      :
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      :
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EINT1_IRQHandler
\n
EINT0_IRQHandler
\n
                B       .
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\nstartup_Device.s Template File
\n
The startup_Device.s Template File for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
\n
;/**************************************************************************//**\n; * @file     startup_<Device>.s\n; * @brief    CMSIS Cortex-M# Core Device Startup File for\n; *           Device <Device>\n; * @version  V3.10\n; * @date     23. November 2012\n; *\n; * @note\n; *\n; ******************************************************************************/\n;/* Copyright (c) 2012 ARM LIMITED\n;\n;   All rights reserved.\n;   Redistribution and use in source and binary forms, with or without\n;   modification, are permitted provided that the following conditions are met:\n;   - Redistributions of source code must retain the above copyright\n;     notice, this list of conditions and the following disclaimer.\n;   - Redistributions in binary form must reproduce the above copyright\n;     notice, this list of conditions and the following disclaimer in the\n;     documentation and/or other materials provided with the distribution.\n;   - Neither the name of ARM nor the names of its contributors may be used\n;     to endorse or promote products derived from this software without\n;     specific prior written permission.\n;   *\n;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n;   POSSIBILITY OF SUCH DAMAGE.\n;   ---------------------------------------------------------------------------*/\n;/*\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n;*/\n\n\n; <h> Stack Configuration\n;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n\nStack_Size      EQU     0x00000400\n\n                AREA    STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem       SPACE   Stack_Size\n__initial_sp\n\n\n; <h> Heap Configuration\n;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n\nHeap_Size       EQU     0x00000100\n\n                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE   Heap_Size\n__heap_limit\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    RESET, DATA, READONLY\n                EXPORT  __Vectors\n                EXPORT  __Vectors_End\n                EXPORT  __Vectors_Size\n\n__Vectors       DCD     __initial_sp              ; Top of Stack\n                DCD     Reset_Handler             ; Reset Handler\n                DCD     NMI_Handler               ; NMI Handler\n                DCD     HardFault_Handler         ; Hard Fault Handler\n                DCD     MemManage_Handler         ; MPU Fault Handler\n                DCD     BusFault_Handler          ; Bus Fault Handler\n                DCD     UsageFault_Handler        ; Usage Fault Handler\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     SVC_Handler               ; SVCall Handler\n                DCD     DebugMon_Handler          ; Debug Monitor Handler\n                DCD     0                         ; Reserved\n                DCD     PendSV_Handler            ; PendSV Handler\n                DCD     SysTick_Handler           ; SysTick Handler\n\n                ; External Interrupts\n; ToDo:  Add here the vectors for the device specific external interrupts handler\n                DCD     <DeviceInterrupt>_IRQHandler       ;  0: Default\n__Vectors_End\n\n__Vectors_Size  EQU     __Vectors_End - __Vectors\n\n                AREA    |.text|, CODE, READONLY\n\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT  Reset_Handler             [WEAK]\n                IMPORT  SystemInit\n                IMPORT  __main\n                LDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =__main\n                BX      R0\n                ENDP\n\n\n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler     PROC\n                EXPORT  NMI_Handler               [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler          [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler        [WEAK]\n                B       .\n                ENDP\nSVC_Handler     PROC\n                EXPORT  SVC_Handler               [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler          [WEAK]\n                B       .\n                ENDP\nPendSV_Handler\\\n                PROC\n                EXPORT  PendSV_Handler            [WEAK]\n                B       .\n                ENDP\nSysTick_Handler\\\n                PROC\n                EXPORT  SysTick_Handler           [WEAK]\n                B       .\n                ENDP\n\nDefault_Handler PROC\n; ToDo:  Add here the export definition for the device specific external interrupts handler\n                EXPORT  <DeviceInterrupt>_IRQHandler         [WEAK]\n\n; ToDo:  Add here the names for the device specific external interrupts handler\n<DeviceInterrupt>_IRQHandler\n                B       .\n                ENDP\n\n\n                ALIGN\n\n\n; User Initial Stack & Heap\n\n                IF      :DEF:__MICROLIB\n\n                EXPORT  __initial_sp\n                EXPORT  __heap_base\n                EXPORT  __heap_limit\n\n                ELSE\n\n                IMPORT  __use_two_region_memory\n                EXPORT  __user_initial_stackheap\n\n__user_initial_stackheap PROC\n                LDR     R0, =  Heap_Mem\n                LDR     R1, =(Stack_Mem + Stack_Size)\n                LDR     R2, = (Heap_Mem +  Heap_Size)\n                LDR     R3, = Stack_Mem\n                BX      LR\n                ENDP\n\n                ALIGN\n\n                ENDIF\n\n\n                END\n
 
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  • Template Files
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: CoreDebug_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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CoreDebug_Type Struct Reference
  
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Structure type to access the Core Debug Register (CoreDebug).  \n
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\nData Fields
__IO uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register.  More...
 
__O uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register.  More...
 
__IO uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register.  More...
 
__IO uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.  More...
 
\n
Field Documentation
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\n      \n        \n          \n        \n      
__IO uint32_t CoreDebug_Type::DCRDR
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__O uint32_t CoreDebug_Type::DCRSR
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__IO uint32_t CoreDebug_Type::DEMCR
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__IO uint32_t CoreDebug_Type::DHCSR
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    \n    
  • CoreDebug_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_core_debug___type.js",
    "content": "var struct_core_debug___type =\n[\n    [ \"DCRDR\", \"struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9\", null ],\n    [ \"DCRSR\", \"struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983\", null ],\n    [ \"DEMCR\", \"struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d\", null ],\n    [ \"DHCSR\", \"struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: DWT_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
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DWT_Type Struct Reference
  
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Structure type to access the Data Watchpoint and Trace Register (DWT).  \n
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\nData Fields
__IO uint32_t CTRL
 Offset: 0x000 (R/W) Control Register.  More...
 
__IO uint32_t CYCCNT
 Offset: 0x004 (R/W) Cycle Count Register.  More...
 
__IO uint32_t CPICNT
 Offset: 0x008 (R/W) CPI Count Register.  More...
 
__IO uint32_t EXCCNT
 Offset: 0x00C (R/W) Exception Overhead Count Register.  More...
 
__IO uint32_t SLEEPCNT
 Offset: 0x010 (R/W) Sleep Count Register.  More...
 
__IO uint32_t LSUCNT
 Offset: 0x014 (R/W) LSU Count Register.  More...
 
__IO uint32_t FOLDCNT
 Offset: 0x018 (R/W) Folded-instruction Count Register.  More...
 
__I uint32_t PCSR
 Offset: 0x01C (R/ ) Program Counter Sample Register.  More...
 
__IO uint32_t COMP0
 Offset: 0x020 (R/W) Comparator Register 0.  More...
 
__IO uint32_t MASK0
 Offset: 0x024 (R/W) Mask Register 0.  More...
 
__IO uint32_t FUNCTION0
 Offset: 0x028 (R/W) Function Register 0.  More...
 
uint32_t RESERVED0 [1]
 Reserved.  More...
 
__IO uint32_t COMP1
 Offset: 0x030 (R/W) Comparator Register 1.  More...
 
__IO uint32_t MASK1
 Offset: 0x034 (R/W) Mask Register 1.  More...
 
__IO uint32_t FUNCTION1
 Offset: 0x038 (R/W) Function Register 1.  More...
 
uint32_t RESERVED1 [1]
 Reserved.  More...
 
__IO uint32_t COMP2
 Offset: 0x040 (R/W) Comparator Register 2.  More...
 
__IO uint32_t MASK2
 Offset: 0x044 (R/W) Mask Register 2.  More...
 
__IO uint32_t FUNCTION2
 Offset: 0x048 (R/W) Function Register 2.  More...
 
uint32_t RESERVED2 [1]
 Reserved.  More...
 
__IO uint32_t COMP3
 Offset: 0x050 (R/W) Comparator Register 3.  More...
 
__IO uint32_t MASK3
 Offset: 0x054 (R/W) Mask Register 3.  More...
 
__IO uint32_t FUNCTION3
 Offset: 0x058 (R/W) Function Register 3.  More...
 
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Field Documentation
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__IO uint32_t DWT_Type::COMP0
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__IO uint32_t DWT_Type::COMP1
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__IO uint32_t DWT_Type::COMP2
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__IO uint32_t DWT_Type::COMP3
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__IO uint32_t DWT_Type::CPICNT
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__IO uint32_t DWT_Type::CTRL
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__IO uint32_t DWT_Type::CYCCNT
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__IO uint32_t DWT_Type::EXCCNT
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__IO uint32_t DWT_Type::FOLDCNT
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__IO uint32_t DWT_Type::FUNCTION0
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__IO uint32_t DWT_Type::FUNCTION1
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__IO uint32_t DWT_Type::FUNCTION2
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__IO uint32_t DWT_Type::FUNCTION3
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__IO uint32_t DWT_Type::LSUCNT
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__IO uint32_t DWT_Type::MASK0
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__IO uint32_t DWT_Type::MASK1
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__IO uint32_t DWT_Type::MASK2
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__IO uint32_t DWT_Type::MASK3
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__I uint32_t DWT_Type::PCSR
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uint32_t DWT_Type::RESERVED0[1]
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uint32_t DWT_Type::RESERVED1[1]
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uint32_t DWT_Type::RESERVED2[1]
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__IO uint32_t DWT_Type::SLEEPCNT
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  • DWT_Type
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_d_w_t___type.js",
    "content": "var struct_d_w_t___type =\n[\n    [ \"COMP0\", \"struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904\", null ],\n    [ \"COMP1\", \"struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c\", null ],\n    [ \"COMP2\", \"struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332\", null ],\n    [ \"COMP3\", \"struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f\", null ],\n    [ \"CPICNT\", \"struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc\", null ],\n    [ \"CTRL\", \"struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d\", null ],\n    [ \"CYCCNT\", \"struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4\", null ],\n    [ \"EXCCNT\", \"struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82\", null ],\n    [ \"FOLDCNT\", \"struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab\", null ],\n    [ \"FUNCTION0\", \"struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729\", null ],\n    [ \"FUNCTION1\", \"struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747\", null ],\n    [ \"FUNCTION2\", \"struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b\", null ],\n    [ \"FUNCTION3\", \"struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890\", null ],\n    [ \"LSUCNT\", \"struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35\", null ],\n    [ \"MASK0\", \"struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f\", null ],\n    [ \"MASK1\", \"struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef\", null ],\n    [ \"MASK2\", \"struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e\", null ],\n    [ \"MASK3\", \"struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba\", null ],\n    [ \"PCSR\", \"struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5\", null ],\n    [ \"RESERVED0\", \"struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59\", null ],\n    [ \"RESERVED1\", \"struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4\", null ],\n    [ \"RESERVED2\", \"struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738\", null ],\n    [ \"SLEEPCNT\", \"struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: FPU_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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FPU_Type Struct Reference
  
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Structure type to access the Floating Point Unit (FPU).  \n
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uint32_t RESERVED0 [1]
 Reserved.  More...
 
__IO uint32_t FPCCR
 Offset: 0x004 (R/W) Floating-Point Context Control Register.  More...
 
__IO uint32_t FPCAR
 Offset: 0x008 (R/W) Floating-Point Context Address Register.  More...
 
__IO uint32_t FPDSCR
 Offset: 0x00C (R/W) Floating-Point Default Status Control Register.  More...
 
__I uint32_t MVFR0
 Offset: 0x010 (R/ ) Media and FP Feature Register 0.  More...
 
__I uint32_t MVFR1
 Offset: 0x014 (R/ ) Media and FP Feature Register 1.  More...
 
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Field Documentation
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__IO uint32_t FPU_Type::FPCAR
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__IO uint32_t FPU_Type::FPCCR
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__IO uint32_t FPU_Type::FPDSCR
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__I uint32_t FPU_Type::MVFR0
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__I uint32_t FPU_Type::MVFR1
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uint32_t FPU_Type::RESERVED0[1]
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_f_p_u___type.js",
    "content": "var struct_f_p_u___type =\n[\n    [ \"FPCAR\", \"struct_f_p_u___type.html#aa48253f088dc524de80c42fbc995f66b\", null ],\n    [ \"FPCCR\", \"struct_f_p_u___type.html#a22054423086a3daf2077fb2f3fe2a8b8\", null ],\n    [ \"FPDSCR\", \"struct_f_p_u___type.html#a4d58ef3ebea69a5ec5acd8c90a9941b6\", null ],\n    [ \"MVFR0\", \"struct_f_p_u___type.html#a135577b0a76bd3164be2a02f29ca46f1\", null ],\n    [ \"MVFR1\", \"struct_f_p_u___type.html#a776e8625853e1413c4e8330ec85c256d\", null ],\n    [ \"RESERVED0\", \"struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: ITM_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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ITM_Type Struct Reference
  
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Structure type to access the Instrumentation Trace Macrocell Register (ITM).  \n
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\nData Fields
union {
   __O uint8_t   u8
 Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.  More...
 
   __O uint16_t   u16
 Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.  More...
 
   __O uint32_t   u32
 Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.  More...
 
} PORT [32]
 Offset: 0x000 ( /W) ITM Stimulus Port Registers.  More...
 
uint32_t RESERVED0 [864]
 Reserved.  More...
 
__IO uint32_t TER
 Offset: 0xE00 (R/W) ITM Trace Enable Register.  More...
 
uint32_t RESERVED1 [15]
 Reserved.  More...
 
__IO uint32_t TPR
 Offset: 0xE40 (R/W) ITM Trace Privilege Register.  More...
 
uint32_t RESERVED2 [15]
 Reserved.  More...
 
__IO uint32_t TCR
 Offset: 0xE80 (R/W) ITM Trace Control Register.  More...
 
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Field Documentation
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__O { ... }    ITM_Type::PORT[32]
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uint32_t ITM_Type::RESERVED0[864]
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uint32_t ITM_Type::RESERVED1[15]
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uint32_t ITM_Type::RESERVED2[15]
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__IO uint32_t ITM_Type::TCR
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__IO uint32_t ITM_Type::TER
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__IO uint32_t ITM_Type::TPR
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__O uint16_t ITM_Type::u16
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__O uint32_t ITM_Type::u32
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__O uint8_t ITM_Type::u8
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  • ITM_Type
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  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_i_t_m___type.js",
    "content": "var struct_i_t_m___type =\n[\n    [ \"PORT\", \"struct_i_t_m___type.html#afe056e8c8f8c5519d9b47611fa3a4c46\", null ],\n    [ \"RESERVED0\", \"struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e\", null ],\n    [ \"RESERVED1\", \"struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce\", null ],\n    [ \"RESERVED2\", \"struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b\", null ],\n    [ \"TCR\", \"struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45\", null ],\n    [ \"TER\", \"struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589\", null ],\n    [ \"TPR\", \"struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa\", null ],\n    [ \"u16\", \"struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4\", null ],\n    [ \"u32\", \"struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df\", null ],\n    [ \"u8\", \"struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: MPU_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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MPU_Type Struct Reference
  
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Structure type to access the Memory Protection Unit (MPU).  \n
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\nData Fields
__I uint32_t TYPE
 Offset: 0x000 (R/ ) MPU Type Register.  More...
 
__IO uint32_t CTRL
 Offset: 0x004 (R/W) MPU Control Register.  More...
 
__IO uint32_t RNR
 Offset: 0x008 (R/W) MPU Region RNRber Register.  More...
 
__IO uint32_t RBAR
 Offset: 0x00C (R/W) MPU Region Base Address Register.  More...
 
__IO uint32_t RASR
 Offset: 0x010 (R/W) MPU Region Attribute and Size Register.  More...
 
__IO uint32_t RBAR_A1
 Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.  More...
 
__IO uint32_t RASR_A1
 Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.  More...
 
__IO uint32_t RBAR_A2
 Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.  More...
 
__IO uint32_t RASR_A2
 Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.  More...
 
__IO uint32_t RBAR_A3
 Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.  More...
 
__IO uint32_t RASR_A3
 Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.  More...
 
\n
Field Documentation
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__IO uint32_t MPU_Type::CTRL
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__IO uint32_t MPU_Type::RASR
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__IO uint32_t MPU_Type::RASR_A1
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__IO uint32_t MPU_Type::RASR_A2
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__IO uint32_t MPU_Type::RASR_A3
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__IO uint32_t MPU_Type::RBAR
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__IO uint32_t MPU_Type::RBAR_A1
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\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t MPU_Type::RBAR_A2
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t MPU_Type::RBAR_A3
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t MPU_Type::RNR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t MPU_Type::TYPE
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • MPU_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_m_p_u___type.js",
    "content": "var struct_m_p_u___type =\n[\n    [ \"CTRL\", \"struct_m_p_u___type.html#aab33593671948b93b1c0908d78779328\", null ],\n    [ \"RASR\", \"struct_m_p_u___type.html#adc65d266d15ce9ba57b3d127e8267f03\", null ],\n    [ \"RASR_A1\", \"struct_m_p_u___type.html#a94222f9a8637b5329016e18f08af7185\", null ],\n    [ \"RASR_A2\", \"struct_m_p_u___type.html#a0aac7727a6225c6aa00627c36d51d014\", null ],\n    [ \"RASR_A3\", \"struct_m_p_u___type.html#aced0b908173b9a4bae4f59452f0cdb0d\", null ],\n    [ \"RBAR\", \"struct_m_p_u___type.html#a3f2e2448a77aadacd9f394f6c4c708d9\", null ],\n    [ \"RBAR_A1\", \"struct_m_p_u___type.html#a4dbcffa0a71c31e521b645b34b40e639\", null ],\n    [ \"RBAR_A2\", \"struct_m_p_u___type.html#a8703a00626dba046b841c0db6c78c395\", null ],\n    [ \"RBAR_A3\", \"struct_m_p_u___type.html#a9fda17c37b85ef317c7c8688ff8c5804\", null ],\n    [ \"RNR\", \"struct_m_p_u___type.html#afd8de96a5d574c3953e2106e782f9833\", null ],\n    [ \"TYPE\", \"struct_m_p_u___type.html#a6ae8a8c3a4909ae41447168d793608f7\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: NVIC_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
NVIC_Type Struct Reference
  
\n
\n
\n\n
Structure type to access the Nested Vectored Interrupt Controller (NVIC).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
__IO uint32_t ISER [8]
 Offset: 0x000 (R/W) Interrupt Set Enable Register.  More...
 
uint32_t RESERVED0 [24]
 Reserved.  More...
 
__IO uint32_t ICER [8]
 Offset: 0x080 (R/W) Interrupt Clear Enable Register.  More...
 
uint32_t RSERVED1 [24]
 Reserved.  More...
 
__IO uint32_t ISPR [8]
 Offset: 0x100 (R/W) Interrupt Set Pending Register.  More...
 
uint32_t RESERVED2 [24]
 Reserved.  More...
 
__IO uint32_t ICPR [8]
 Offset: 0x180 (R/W) Interrupt Clear Pending Register.  More...
 
uint32_t RESERVED3 [24]
 Reserved.  More...
 
__IO uint32_t IABR [8]
 Offset: 0x200 (R/W) Interrupt Active bit Register.  More...
 
uint32_t RESERVED4 [56]
 Reserved.  More...
 
__IO uint8_t IP [240]
 Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)  More...
 
uint32_t RESERVED5 [644]
 Reserved.  More...
 
__O uint32_t STIR
 Offset: 0xE00 ( /W) Software Trigger Interrupt Register.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t NVIC_Type::IABR[8]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t NVIC_Type::ICER[8]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t NVIC_Type::ICPR[8]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint8_t NVIC_Type::IP[240]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t NVIC_Type::ISER[8]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t NVIC_Type::ISPR[8]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RESERVED0[24]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RESERVED2[24]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RESERVED3[24]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RESERVED4[56]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RESERVED5[644]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t NVIC_Type::RSERVED1[24]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__O uint32_t NVIC_Type::STIR
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • NVIC_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_n_v_i_c___type.js",
    "content": "var struct_n_v_i_c___type =\n[\n    [ \"IABR\", \"struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11\", null ],\n    [ \"ICER\", \"struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5\", null ],\n    [ \"ICPR\", \"struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5\", null ],\n    [ \"IP\", \"struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c\", null ],\n    [ \"ISER\", \"struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f\", null ],\n    [ \"ISPR\", \"struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90\", null ],\n    [ \"RESERVED0\", \"struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80\", null ],\n    [ \"RESERVED2\", \"struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72\", null ],\n    [ \"RESERVED3\", \"struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab\", null ],\n    [ \"RESERVED4\", \"struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790\", null ],\n    [ \"RESERVED5\", \"struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8\", null ],\n    [ \"RSERVED1\", \"struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe\", null ],\n    [ \"STIR\", \"struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: SCB_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
SCB_Type Struct Reference
  
\n
\n
\n\n
Structure type to access the System Control Block (SCB).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
__I uint32_t CPUID
 Offset: 0x000 (R/ ) CPUID Base Register.  More...
 
__IO uint32_t ICSR
 Offset: 0x004 (R/W) Interrupt Control and State Register.  More...
 
__IO uint32_t VTOR
 Offset: 0x008 (R/W) Vector Table Offset Register.  More...
 
__IO uint32_t AIRCR
 Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.  More...
 
__IO uint32_t SCR
 Offset: 0x010 (R/W) System Control Register.  More...
 
__IO uint32_t CCR
 Offset: 0x014 (R/W) Configuration Control Register.  More...
 
__IO uint8_t SHP [12]
 Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)  More...
 
__IO uint32_t SHCSR
 Offset: 0x024 (R/W) System Handler Control and State Register.  More...
 
__IO uint32_t CFSR
 Offset: 0x028 (R/W) Configurable Fault Status Register.  More...
 
__IO uint32_t HFSR
 Offset: 0x02C (R/W) HardFault Status Register.  More...
 
__IO uint32_t DFSR
 Offset: 0x030 (R/W) Debug Fault Status Register.  More...
 
__IO uint32_t MMFAR
 Offset: 0x034 (R/W) MemManage Fault Address Register.  More...
 
__IO uint32_t BFAR
 Offset: 0x038 (R/W) BusFault Address Register.  More...
 
__IO uint32_t AFSR
 Offset: 0x03C (R/W) Auxiliary Fault Status Register.  More...
 
__I uint32_t PFR [2]
 Offset: 0x040 (R/ ) Processor Feature Register.  More...
 
__I uint32_t DFR
 Offset: 0x048 (R/ ) Debug Feature Register.  More...
 
__I uint32_t ADR
 Offset: 0x04C (R/ ) Auxiliary Feature Register.  More...
 
__I uint32_t MMFR [4]
 Offset: 0x050 (R/ ) Memory Model Feature Register.  More...
 
__I uint32_t ISAR [5]
 Offset: 0x060 (R/ ) Instruction Set Attributes Register.  More...
 
uint32_t RESERVED0 [5]
 Reserved.  More...
 
__IO uint32_t CPACR
 Offset: 0x088 (R/W) Coprocessor Access Control Register.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::ADR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::AFSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::AIRCR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::BFAR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::CCR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::CFSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::CPACR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::CPUID
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::DFR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::DFSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::HFSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::ICSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::ISAR[5]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::MMFAR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::MMFR[4]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCB_Type::PFR[2]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t SCB_Type::RESERVED0[5]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::SCR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::SHCSR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint8_t SCB_Type::SHP[12]
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCB_Type::VTOR
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • SCB_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_s_c_b___type.js",
    "content": "var struct_s_c_b___type =\n[\n    [ \"ADR\", \"struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2\", null ],\n    [ \"AFSR\", \"struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef\", null ],\n    [ \"AIRCR\", \"struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d\", null ],\n    [ \"BFAR\", \"struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a\", null ],\n    [ \"CCR\", \"struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8\", null ],\n    [ \"CFSR\", \"struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4\", null ],\n    [ \"CPACR\", \"struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85\", null ],\n    [ \"CPUID\", \"struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032\", null ],\n    [ \"DFR\", \"struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86\", null ],\n    [ \"DFSR\", \"struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d\", null ],\n    [ \"HFSR\", \"struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d\", null ],\n    [ \"ICSR\", \"struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a\", null ],\n    [ \"ISAR\", \"struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f\", null ],\n    [ \"MMFAR\", \"struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd\", null ],\n    [ \"MMFR\", \"struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976\", null ],\n    [ \"PFR\", \"struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7\", null ],\n    [ \"RESERVED0\", \"struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6\", null ],\n    [ \"SCR\", \"struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16\", null ],\n    [ \"SHCSR\", \"struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f\", null ],\n    [ \"SHP\", \"struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4\", null ],\n    [ \"VTOR\", \"struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: SCnSCB_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
SCnSCB_Type Struct Reference
  
\n
\n
\n\n
Structure type to access the System Control and ID Register not in the SCB.  \n
\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t RESERVED0 [1]
 Reserved.  More...
 
__I uint32_t ICTR
 Offset: 0x004 (R/ ) Interrupt Controller Type Register.  More...
 
__IO uint32_t ACTLR
 Offset: 0x008 (R/W) Auxiliary Control Register.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
__IO uint32_t SCnSCB_Type::ACTLR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
__I uint32_t SCnSCB_Type::ICTR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t SCnSCB_Type::RESERVED0[1]
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • SCnSCB_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_s_cn_s_c_b___type.js",
    "content": "var struct_s_cn_s_c_b___type =\n[\n    [ \"ACTLR\", \"struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d\", null ],\n    [ \"ICTR\", \"struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98\", null ],\n    [ \"RESERVED0\", \"struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: SysTick_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
SysTick_Type Struct Reference
  
\n
\n
\n\n
Structure type to access the System Timer (SysTick).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
__IO uint32_t CTRL
 Offset: 0x000 (R/W) SysTick Control and Status Register.  More...
 
__IO uint32_t LOAD
 Offset: 0x004 (R/W) SysTick Reload Value Register.  More...
 
__IO uint32_t VAL
 Offset: 0x008 (R/W) SysTick Current Value Register.  More...
 
__I uint32_t CALIB
 Offset: 0x00C (R/ ) SysTick Calibration Register.  More...
 
\n
Field Documentation
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__I uint32_t SysTick_Type::CALIB
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__IO uint32_t SysTick_Type::CTRL
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__IO uint32_t SysTick_Type::LOAD
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__IO uint32_t SysTick_Type::VAL
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_sys_tick___type.js",
    "content": "var struct_sys_tick___type =\n[\n    [ \"CALIB\", \"struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238\", null ],\n    [ \"CTRL\", \"struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f\", null ],\n    [ \"LOAD\", \"struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f\", null ],\n    [ \"VAL\", \"struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: TPI_Type Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE\n    Version 3.20\n   
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TPI_Type Struct Reference
  
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Structure type to access the Trace Port Interface Register (TPI).  \n
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\nData Fields
__IO uint32_t SSPSR
 Offset: 0x000 (R/ ) Supported Parallel Port Size Register.  More...
 
__IO uint32_t CSPSR
 Offset: 0x004 (R/W) Current Parallel Port Size Register.  More...
 
uint32_t RESERVED0 [2]
 Reserved.  More...
 
__IO uint32_t ACPR
 Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.  More...
 
uint32_t RESERVED1 [55]
 Reserved.  More...
 
__IO uint32_t SPPR
 Offset: 0x0F0 (R/W) Selected Pin Protocol Register.  More...
 
uint32_t RESERVED2 [131]
 Reserved.  More...
 
__I uint32_t FFSR
 Offset: 0x300 (R/ ) Formatter and Flush Status Register.  More...
 
__IO uint32_t FFCR
 Offset: 0x304 (R/W) Formatter and Flush Control Register.  More...
 
__I uint32_t FSCR
 Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.  More...
 
uint32_t RESERVED3 [759]
 Reserved.  More...
 
__I uint32_t TRIGGER
 Offset: 0xEE8 (R/ ) TRIGGER.  More...
 
__I uint32_t FIFO0
 Offset: 0xEEC (R/ ) Integration ETM Data.  More...
 
__I uint32_t ITATBCTR2
 Offset: 0xEF0 (R/ ) ITATBCTR2.  More...
 
uint32_t RESERVED4 [1]
 Reserved.  More...
 
__I uint32_t ITATBCTR0
 Offset: 0xEF8 (R/ ) ITATBCTR0.  More...
 
__I uint32_t FIFO1
 Offset: 0xEFC (R/ ) Integration ITM Data.  More...
 
__IO uint32_t ITCTRL
 Offset: 0xF00 (R/W) Integration Mode Control.  More...
 
uint32_t RESERVED5 [39]
 Reserved.  More...
 
__IO uint32_t CLAIMSET
 Offset: 0xFA0 (R/W) Claim tag set.  More...
 
__IO uint32_t CLAIMCLR
 Offset: 0xFA4 (R/W) Claim tag clear.  More...
 
uint32_t RESERVED7 [8]
 Reserved.  More...
 
__I uint32_t DEVID
 Offset: 0xFC8 (R/ ) TPIU_DEVID.  More...
 
__I uint32_t DEVTYPE
 Offset: 0xFCC (R/ ) TPIU_DEVTYPE.  More...
 
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Field Documentation
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__IO uint32_t TPI_Type::ACPR
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__IO uint32_t TPI_Type::CLAIMCLR
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__IO uint32_t TPI_Type::CLAIMSET
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__IO uint32_t TPI_Type::CSPSR
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__I uint32_t TPI_Type::DEVID
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__I uint32_t TPI_Type::DEVTYPE
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__IO uint32_t TPI_Type::FFCR
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__I uint32_t TPI_Type::FFSR
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__I uint32_t TPI_Type::FIFO0
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__I uint32_t TPI_Type::FIFO1
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__I uint32_t TPI_Type::FSCR
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__I uint32_t TPI_Type::ITATBCTR0
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__I uint32_t TPI_Type::ITATBCTR2
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__IO uint32_t TPI_Type::ITCTRL
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uint32_t TPI_Type::RESERVED0[2]
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uint32_t TPI_Type::RESERVED1[55]
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uint32_t TPI_Type::RESERVED2[131]
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uint32_t TPI_Type::RESERVED3[759]
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uint32_t TPI_Type::RESERVED4[1]
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uint32_t TPI_Type::RESERVED5[39]
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uint32_t TPI_Type::RESERVED7[8]
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__IO uint32_t TPI_Type::SPPR
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__IO uint32_t TPI_Type::SSPSR
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__I uint32_t TPI_Type::TRIGGER
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/struct_t_p_i___type.js",
    "content": "var struct_t_p_i___type =\n[\n    [ \"ACPR\", \"struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab\", null ],\n    [ \"CLAIMCLR\", \"struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad\", null ],\n    [ \"CLAIMSET\", \"struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84\", null ],\n    [ \"CSPSR\", \"struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a\", null ],\n    [ \"DEVID\", \"struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d\", null ],\n    [ \"DEVTYPE\", \"struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35\", null ],\n    [ \"FFCR\", \"struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880\", null ],\n    [ \"FFSR\", \"struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd\", null ],\n    [ \"FIFO0\", \"struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10\", null ],\n    [ \"FIFO1\", \"struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e\", null ],\n    [ \"FSCR\", \"struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef\", null ],\n    [ \"ITATBCTR0\", \"struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0\", null ],\n    [ \"ITATBCTR2\", \"struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d\", null ],\n    [ \"ITCTRL\", \"struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198\", null ],\n    [ \"RESERVED0\", \"struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9\", null ],\n    [ \"RESERVED1\", \"struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12\", null ],\n    [ \"RESERVED2\", \"struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096\", null ],\n    [ \"RESERVED3\", \"struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c\", null ],\n    [ \"RESERVED4\", \"struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46\", null ],\n    [ \"RESERVED5\", \"struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30\", null ],\n    [ \"RESERVED7\", \"struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550\", null ],\n    [ \"SPPR\", \"struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e\", null ],\n    [ \"SSPSR\", \"struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912\", null ],\n    [ \"TRIGGER\", \"struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/system_c_pg.html",
    "content": "\n\n\n\n\nCMSIS-CORE: System Configuration Files system_<device>.c and system_<device>.h\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-CORE\n    Version 3.20\n   
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CMSIS-CORE support for Cortex-M processor-based devices
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System Configuration Files system_<device>.c and system_<device>.h 
  
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The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.
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For devices with external memory BUS the system_<device>.c also configures the BUS system.
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The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.
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\nsystem_Device.c Template File
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The system_Device.c Template File for the Cortex-M3 is shown below.
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/**************************************************************************//**\n * @file     system_<Device>.c\n * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for\n *           Device <Device>\n * @version  V3.10\n * @date     23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2012 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#include <stdint.h>\n#include \"<Device>.h\"\n\n\n/*----------------------------------------------------------------------------\n  DEFINES\n *----------------------------------------------------------------------------*/\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n/* ToDo: add here your necessary defines for device initialization\n         following is an example for different system frequencies             */\n#define __HSI             ( 6000000UL)\n#define __XTAL            (12000000UL)    /* Oscillator frequency             */\n#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */\n\n#define __SYSTEM_CLOCK    (4*__XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Clock Variable definitions\n *----------------------------------------------------------------------------*/\n/* ToDo: initialize SystemCoreClock with the system core clock frequency value\n         achieved after system intitialization.\n         This means system core clock frequency after call to SystemInit()    */\nuint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/\n\n\n/*----------------------------------------------------------------------------\n  Clock functions\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */\n{\n/* ToDo: add code to calculate the system frequency based upon the current\n         register settings.\n         This function can be used to retrieve the system core clock frequeny\n         after user changed register sittings.                                */\n  SystemCoreClock = __SYSTEM_CLOCK;\n}\n\n/**\n * Initialize the system\n *\n * @param  none\n * @return none\n *\n * @brief  Setup the microcontroller system.\n *         Initialize the System.\n */\nvoid SystemInit (void)\n{\n/* ToDo: add code to initialize the system\n         do not use global variables because this function is called before\n         reaching pre-main. RW section maybe overwritten afterwards.          */\n  SystemCoreClock = __SYSTEM_CLOCK;\n}\n
\nsystem_Device.h Template File
\n
The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.
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/**************************************************************************//**\n * @file     system_<Device>.h\n * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for\n *           Device <Device>\n * @version  V3.10\n * @date     23. November 2012\n *\n * @note\n *\n ******************************************************************************/\n/* Copyright (c) 2012 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */\n#define SYSTEM_<Device>_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n\n/**\n * Initialize the system\n *\n * @param  none\n * @return none\n *\n * @brief  Setup the microcontroller system.\n *         Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n/**\n * Update SystemCoreClock variable\n *\n * @param  none\n * @return none\n *\n * @brief  Updates the SystemCoreClock with current core Clock\n *         retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_<Device>_H */\n
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: APSR_Type Union Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
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APSR_Type Union Reference
  
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Union type to access the Application Program Status Register (APSR).  \n
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\nData Fields
struct {
   uint32_t   _reserved0:27
 bit: 0..26 Reserved  More...
 
   uint32_t   Q:1
 bit: 27 Saturation condition flag  More...
 
   uint32_t   V:1
 bit: 28 Overflow condition code flag  More...
 
   uint32_t   C:1
 bit: 29 Carry condition code flag  More...
 
   uint32_t   Z:1
 bit: 30 Zero condition code flag  More...
 
   uint32_t   N:1
 bit: 31 Negative condition code flag  More...
 
} b
 Structure used for bit access.  More...
 
uint32_t w
 Type used for word access.  More...
 
\n
Field Documentation
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uint32_t APSR_Type::_reserved0
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
struct { ... }   APSR_Type::b
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::C
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::N
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::Q
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::V
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::w
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t APSR_Type::Z
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • APSR_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_a_p_s_r___type.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: CONTROL_Type Union Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
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\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
CONTROL_Type Union Reference
  
\n
\n
\n\n
Union type to access the Control Registers (CONTROL).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
struct {
   uint32_t   nPRIV:1
 bit: 0 Execution privilege in Thread mode  More...
 
   uint32_t   SPSEL:1
 bit: 1 Stack to be used  More...
 
   uint32_t   FPCA:1
 bit: 2 FP extension active flag  More...
 
   uint32_t   _reserved0:29
 bit: 3..31 Reserved  More...
 
} b
 Structure used for bit access.  More...
 
uint32_t w
 Type used for word access.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t CONTROL_Type::_reserved0
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
struct { ... }   CONTROL_Type::b
\n
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint32_t CONTROL_Type::FPCA
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t CONTROL_Type::nPRIV
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t CONTROL_Type::SPSEL
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t CONTROL_Type::w
\n
\n\n
\n
\n
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\n\n
\n  
    \n    
  • CONTROL_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: IPSR_Type Union Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
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\nData Fields  
\n  
\n
IPSR_Type Union Reference
  
\n
\n
\n\n
Union type to access the Interrupt Program Status Register (IPSR).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number  More...
 
   uint32_t   _reserved0:23
 bit: 9..31 Reserved  More...
 
} b
 Structure used for bit access.  More...
 
uint32_t w
 Type used for word access.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t IPSR_Type::_reserved0
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
struct { ... }   IPSR_Type::b
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t IPSR_Type::ISR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t IPSR_Type::w
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • IPSR_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/union_i_p_s_r___type.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.html",
    "content": "\n\n\n\n\nCMSIS-CORE: xPSR_Type Union Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-CORE\n    Version 3.20\n   
\n   
CMSIS-CORE support for Cortex-M processor-based devices
\n  
\n
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\n    \n  
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\nData Fields  
\n  
\n
xPSR_Type Union Reference
  
\n
\n
\n\n
Union type to access the Special-Purpose Program Status Registers (xPSR).  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
struct {
   uint32_t   ISR:9
 bit: 0.. 8 Exception number  More...
 
   uint32_t   _reserved0:15
 bit: 9..23 Reserved  More...
 
   uint32_t   T:1
 bit: 24 Thumb bit (read 0)  More...
 
   uint32_t   IT:2
 bit: 25..26 saved IT state (read 0)  More...
 
   uint32_t   Q:1
 bit: 27 Saturation condition flag  More...
 
   uint32_t   V:1
 bit: 28 Overflow condition code flag  More...
 
   uint32_t   C:1
 bit: 29 Carry condition code flag  More...
 
   uint32_t   Z:1
 bit: 30 Zero condition code flag  More...
 
   uint32_t   N:1
 bit: 31 Negative condition code flag  More...
 
} b
 Structure used for bit access.  More...
 
uint32_t w
 Type used for word access.  More...
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::_reserved0
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
struct { ... }   xPSR_Type::b
\n
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::C
\n
\n\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::ISR
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::IT
\n
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::N
\n
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::Q
\n
\n\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::T
\n
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\n      \n        \n          \n        \n      
uint32_t xPSR_Type::V
\n
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\n      \n        \n          \n        \n      
uint32_t xPSR_Type::w
\n
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\n
\n      \n        \n          \n        \n      
uint32_t xPSR_Type::Z
\n
\n\n
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\n
\n\n
\n  
    \n    
  • xPSR_Type
    • \n    
  • Generated on Mon Mar 18 2013 13:37:41 for CMSIS-CORE by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/Core/html/unionx_p_s_r___type.js",
    "content": "var unionx_p_s_r___type =\n[\n    [ \"_reserved0\", \"unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5\", null ],\n    [ \"b\", \"unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70\", null ],\n    [ \"C\", \"unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d\", null ],\n    [ \"ISR\", \"unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970\", null ],\n    [ \"IT\", \"unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328\", null ],\n    [ \"N\", \"unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5\", null ],\n    [ \"Q\", \"unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c\", null ],\n    [ \"T\", \"unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658\", null ],\n    [ \"V\", \"unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a\", null ],\n    [ \"w\", \"unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2\", null ],\n    [ \"Z\", \"unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/_change_01_log_8txt.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Change Log.txt File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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  • Change Log.txt
    • \n    
  • Generated on Mon Mar 18 2013 13:37:55 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/_change_log_pg.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Change Log\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
Change Log 
  
\n
\n
\n
\n
 Version 1.4.1 2013/02/20
\n
Updated licenses in headers to 2013
\n
Fixed ALIGN4 macro in arm_math.h
\n
Added files to Cortex-M0 projects so that all projects have same file list
\n
Fixed bugs in
\n\n
\n
 Version 1.4.0 2013/01/09
\n
Updated with more optimizations, bug fixes and new license information in headers
\n
Optimized functions:
\n
    \n
  • arm_biquad_cascade_df2T_f32
    • \n
  • arm_biquad_cascade_df1_q31
    • \n
  • arm_fir_f32
    • \n
  • arm_fir_fast_q31
    • \n
  • arm_cfft_f32
    • \n
  • arm_cfft_radix2_q31
    • \n
  • arm_rfft_fast_f32 (new function)
    • \n
\n
Fixed compiler warnings in arm_math.h for comparing signed and unsigned ints
\n
Fixed a saturation bug in arm_rms_q15
\n
Simplified the code in arm_sin_cos_q31
\n
Added a preprocessor directive to treat the Cortex M0+ just like the Cortex M0
\n
The following functions were deprecated and will be removed in a future version
\n
    \n
  • arm_cfft_radix2_f32
    • \n
  • arm_cfft_radix2_init_f32
    • \n
  • arm_cfft_radix4_f32
    • \n
  • arm_cfft_radix4_init_f32
    • \n
\n
\n
 Version 1.3.0
\n
Added CMSIS DSP Software Library
\n
The CMSIS DSP Software Library is a suite of common signal processing functions targeted to Cortex-M processor based microcontrollers. Even though the code has been specifically optimized towards using the extended DSP instruction set of the Cortex-M4 processor, the library can be compiled for any Cortex-M processor.
\n
For more information please see CMSIS DSP Library documentation. Added Cortex-M4 Core Support
\n
Additional folder CM4, containing the Cortex-M4 core support files, has been added. CM0 CM3 CM4 CoreSupport DeviceSupport
\n
New naming for Core Support Files
\n
The new Core Support Files are:
\n
    \n
  • core_cm#.h (# = 0, 3, 4)
    • \n
  • core_cmFunc.h (Cortex-M Core Register access functions)
    • \n
  • core_cmInstr.h (Cortex-M Core instructions)
    • \n
  • core_cm4_simd.h (Cortex-M4 SIMD instructions)
    • \n
\n
\n
 Version 1.2.0
\n
Removed CMSIS Middelware packages
\n
CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. SystemFrequency renamed to SystemCoreClock
\n
The variable name SystemCoreClock is more precise than SystemFrequency because the variable holds the clock value at which the core is running. Changed startup concept
\n
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit from main) has the weakness that it does not work for controllers which need a already configuerd clock system to configure the external memory controller.
\n
Changed startup concept
\n
    \n
  • SystemInit() is called from startup file before premain.
    • \n
  • SystemInit() configures the clock system and also configures an existing external memory controller.
    • \n
  • SystemInit() must not use global variables.
    • \n
  • SystemCoreClock is initialized with a correct predefined value.
    • \n
  • Additional function void SystemCoreClockUpdate (void) is provided.
    • \n
  • SystemCoreClockUpdate() updates the variable SystemCoreClock and must be called whenever the core clock is changed.
    • \n
  • SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock.
    • \n
\n
Advanced Debug Functions
\n
ITM communication channel is only capable for OUT direction. To allow also communication for IN direction a simple concept is provided.
\n
    \n
  • Global variable volatile int ITM_RxBuffer used for IN data.
    • \n
  • Function int ITM_CheckChar (void) checks if a new character is available.
    • \n
  • Function int ITM_ReceiveChar (void) retrieves the new character.
    • \n
\n
For detailed explanation see file CMSIS debug support.htm.
\n
Core Register Bit Definitions
\n
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the defines correspond with the Cortex-M Technical Reference Manual.
\n
e.g. SysTick structure with bit definitions
\n
\n
typedef struct
\n
{
\n
  __IO uint32_t CTRL;                         
\n
  __IO uint32_t LOAD;                         
\n
  __IO uint32_t VAL;                          
\n
  __I  uint32_t CALIB;                        
\n
} SysTick_Type;
\n
\n
/* SysTick Control / Status Register Definitions */
\n
#define SysTick_CTRL_COUNTFLAG_Pos     16                                      
\n
#define SysTick_CTRL_COUNTFLAG_Msk    (1ul << SysTick_CTRL_COUNTFLAG_Pos)      
\n
#define SysTick_CTRL_CLKSOURCE_Pos      2                                      
\n
#define SysTick_CTRL_CLKSOURCE_Msk     (1ul << SysTick_CTRL_CLKSOURCE_Pos)     
\n
#define SysTick_CTRL_TICKINT_Pos        1                                      
\n
#define SysTick_CTRL_TICKINT_Msk       (1ul << SysTick_CTRL_TICKINT_Pos)       
\n
#define SysTick_CTRL_ENABLE_Pos         0                                      
\n
#define SysTick_CTRL_ENABLE_Msk        (1ul << SysTick_CTRL_ENABLE_Pos)        
\n
/* SysTick Reload Register Definitions */
\n
#define SysTick_LOAD_RELOAD_Pos         0                                      
\n
#define SysTick_LOAD_RELOAD_Msk        (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) 
\n
/* SysTick Current Register Definitions */
\n
#define SysTick_VAL_CURRENT_Pos         0                                      
\n
#define SysTick_VAL_CURRENT_Msk        (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) 
\n
/* SysTick Calibration Register Definitions */
\n
#define SysTick_CALIB_NOREF_Pos        31                                      
\n
#define SysTick_CALIB_NOREF_Msk       (1ul << SysTick_CALIB_NOREF_Pos)         
\n
#define SysTick_CALIB_SKEW_Pos         30                                      
\n
#define SysTick_CALIB_SKEW_Msk        (1ul << SysTick_CALIB_SKEW_Pos)          
\n
#define SysTick_CALIB_TENMS_Pos         0                                      
\n
#define SysTick_CALIB_TENMS_Msk        (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) 
\n
 /* end of group CMSIS_CM3_SysTick */
\n
DoxyGen Tags
\n
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation using DoxyGen. Folder Structure
\n
The folder structure is changed to differentiate the single support packages. 
\n
CM0\nCM3\n    CoreSupport\n    DeviceSupport\n        Vendor\n            Device\n                Startup\n                    Toolchain\n                    Toolchain\n                    ...\n            Device\n            ...\n        Vendor\n        ...\n    Example (optional)\n        Toolchain\n            Device\n            Device\n            ...\n        Toolchain\n        ...\nDocumentation\n
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 Version 1.1.0 2012/02/15
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Updated with more optimizations, bug fixes and minor API changes.
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 Version 1.0.11 2011/10/18
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Bug Fix in conv, correlation, partial convolution.
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 Version 1.0.10 2011/7/15
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Big Endian support added and Merged M0 and M3/M4 Source code.
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 Version 1.0.3 2010/11/29
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Re-organized the CMSIS folders and updated documentation.
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 Version 1.0.2 2010/11/11
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Documentation updated.
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 Version 1.0.1 2010/10/05
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Production release and review comments incorporated.
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 Version 1.0.0 2010/09/20
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Production release and review comments incorporated.
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 Version 0.0.9 2010/08/27
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Added files: arm_biquad_cascade_df1_fast_q15.c arm_biquad_cascade_df1_fast_q31.c arm_fir_fast_q31.c arm_fir_fast_q15.c
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 Version 0.0.7 2010/06/10
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Misra-C changes done
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 Version 0.0.5 2010/04/26
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incorporated review comments and updated with latest CMSIS layer
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 Version 0.0.3 2010/03/10 DP
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Initial version 
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  • Generated on Mon Mar 18 2013 13:37:55 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/annotated.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Structures\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Data Structures
  
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Here are the data structures with brief descriptions:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\"o\"\"C\"arm_bilinear_interp_instance_f32Instance structure for the floating-point bilinear interpolation function
\"o\"\"C\"arm_bilinear_interp_instance_q15Instance structure for the Q15 bilinear interpolation function
\"o\"\"C\"arm_bilinear_interp_instance_q31Instance structure for the Q31 bilinear interpolation function
\"o\"\"C\"arm_bilinear_interp_instance_q7Instance structure for the Q15 bilinear interpolation function
\"o\"\"C\"arm_biquad_cas_df1_32x64_ins_q31Instance structure for the high precision Q31 Biquad cascade filter
\"o\"\"C\"arm_biquad_cascade_df2T_instance_f32Instance structure for the floating-point transposed direct form II Biquad cascade filter
\"o\"\"C\"arm_biquad_casd_df1_inst_f32Instance structure for the floating-point Biquad cascade filter
\"o\"\"C\"arm_biquad_casd_df1_inst_q15Instance structure for the Q15 Biquad cascade filter
\"o\"\"C\"arm_biquad_casd_df1_inst_q31Instance structure for the Q31 Biquad cascade filter
\"o\"\"C\"arm_cfft_instance_f32Instance structure for the floating-point CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix2_instance_f32Instance structure for the floating-point CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix2_instance_q15Instance structure for the Q15 CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix2_instance_q31Instance structure for the Radix-2 Q31 CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix4_instance_f32Instance structure for the floating-point CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix4_instance_q15Instance structure for the Q15 CFFT/CIFFT function
\"o\"\"C\"arm_cfft_radix4_instance_q31Instance structure for the Q31 CFFT/CIFFT function
\"o\"\"C\"arm_dct4_instance_f32Instance structure for the floating-point DCT4/IDCT4 function
\"o\"\"C\"arm_dct4_instance_q15Instance structure for the Q15 DCT4/IDCT4 function
\"o\"\"C\"arm_dct4_instance_q31Instance structure for the Q31 DCT4/IDCT4 function
\"o\"\"C\"arm_fir_decimate_instance_f32Instance structure for the floating-point FIR decimator
\"o\"\"C\"arm_fir_decimate_instance_q15Instance structure for the Q15 FIR decimator
\"o\"\"C\"arm_fir_decimate_instance_q31Instance structure for the Q31 FIR decimator
\"o\"\"C\"arm_fir_instance_f32Instance structure for the floating-point FIR filter
\"o\"\"C\"arm_fir_instance_q15Instance structure for the Q15 FIR filter
\"o\"\"C\"arm_fir_instance_q31Instance structure for the Q31 FIR filter
\"o\"\"C\"arm_fir_instance_q7Instance structure for the Q7 FIR filter
\"o\"\"C\"arm_fir_interpolate_instance_f32Instance structure for the floating-point FIR interpolator
\"o\"\"C\"arm_fir_interpolate_instance_q15Instance structure for the Q15 FIR interpolator
\"o\"\"C\"arm_fir_interpolate_instance_q31Instance structure for the Q31 FIR interpolator
\"o\"\"C\"arm_fir_lattice_instance_f32Instance structure for the floating-point FIR lattice filter
\"o\"\"C\"arm_fir_lattice_instance_q15Instance structure for the Q15 FIR lattice filter
\"o\"\"C\"arm_fir_lattice_instance_q31Instance structure for the Q31 FIR lattice filter
\"o\"\"C\"arm_fir_sparse_instance_f32Instance structure for the floating-point sparse FIR filter
\"o\"\"C\"arm_fir_sparse_instance_q15Instance structure for the Q15 sparse FIR filter
\"o\"\"C\"arm_fir_sparse_instance_q31Instance structure for the Q31 sparse FIR filter
\"o\"\"C\"arm_fir_sparse_instance_q7Instance structure for the Q7 sparse FIR filter
\"o\"\"C\"arm_iir_lattice_instance_f32Instance structure for the floating-point IIR lattice filter
\"o\"\"C\"arm_iir_lattice_instance_q15Instance structure for the Q15 IIR lattice filter
\"o\"\"C\"arm_iir_lattice_instance_q31Instance structure for the Q31 IIR lattice filter
\"o\"\"C\"arm_linear_interp_instance_f32Instance structure for the floating-point Linear Interpolate function
\"o\"\"C\"arm_lms_instance_f32Instance structure for the floating-point LMS filter
\"o\"\"C\"arm_lms_instance_q15Instance structure for the Q15 LMS filter
\"o\"\"C\"arm_lms_instance_q31Instance structure for the Q31 LMS filter
\"o\"\"C\"arm_lms_norm_instance_f32Instance structure for the floating-point normalized LMS filter
\"o\"\"C\"arm_lms_norm_instance_q15Instance structure for the Q15 normalized LMS filter
\"o\"\"C\"arm_lms_norm_instance_q31Instance structure for the Q31 normalized LMS filter
\"o\"\"C\"arm_matrix_instance_f32Instance structure for the floating-point matrix structure
\"o\"\"C\"arm_matrix_instance_q15Instance structure for the Q15 matrix structure
\"o\"\"C\"arm_matrix_instance_q31Instance structure for the Q31 matrix structure
\"o\"\"C\"arm_pid_instance_f32Instance structure for the floating-point PID Control
\"o\"\"C\"arm_pid_instance_q15Instance structure for the Q15 PID Control
\"o\"\"C\"arm_pid_instance_q31Instance structure for the Q31 PID Control
\"o\"\"C\"arm_rfft_fast_instance_f32Instance structure for the floating-point RFFT/RIFFT function
\"o\"\"C\"arm_rfft_instance_f32Instance structure for the floating-point RFFT/RIFFT function
\"o\"\"C\"arm_rfft_instance_q15Instance structure for the Q15 RFFT/RIFFT function
\"\\\"\"C\"arm_rfft_instance_q31Instance structure for the Q31 RFFT/RIFFT function
\n
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/annotated.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__abs__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_abs_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__abs__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_abs_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_abs_q15.c File Reference
  
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void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__abs__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_abs_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__abs__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_abs_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__add__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_add_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__add__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_add_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_add_q15.c File Reference
  
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void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  More...
 
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arm_add_q31.c File Reference
  
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void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  More...
 
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arm_add_q7.c File Reference
  
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void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  More...
 
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arm_biquad_cascade_df1_32x64_init_q31.c File Reference
  
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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
 
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arm_biquad_cascade_df1_32x64_q31.c File Reference
  
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void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 
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arm_biquad_cascade_df1_f32.c File Reference
  
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void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  More...
 
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arm_biquad_cascade_df1_fast_q15.c File Reference
  
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void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
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arm_biquad_cascade_df1_fast_q31.c File Reference
  
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void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
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arm_biquad_cascade_df1_init_f32.c File Reference
  
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void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  More...
 
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arm_biquad_cascade_df1_init_q15.c File Reference
  
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void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  More...
 
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arm_biquad_cascade_df1_init_q31.c File Reference
  
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void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  More...
 
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arm_biquad_cascade_df1_q15.c File Reference
  
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void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  More...
 
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arm_biquad_cascade_df1_q31.c File Reference
  
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void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  More...
 
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arm_biquad_cascade_df2T_f32.c File Reference
  
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LOW_OPTIMIZATION_ENTER void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
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arm_biquad_cascade_df2T_init_f32.c File Reference
  
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void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
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arm_bitreversal.c File Reference
  
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void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTable)
 
void arm_bitreversal_q15 (q15_t *pSrc16, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
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void arm_bitreversal_f32 (float32_t * pSrc, 
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void arm_bitreversal_q15 (q15_t * pSrc16, 
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Referenced by arm_cfft_radix2_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
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void arm_bitreversal_q31 (q31_t * pSrc, 
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Referenced by arm_cfft_radix2_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cfft__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_f32.c File Reference
  
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void arm_radix8_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, const float32_t *pCoef, uint16_t twidCoefModifier)
 
void arm_bitreversal_32 (uint32_t *pSrc, const uint16_t bitRevLen, const uint16_t *pBitRevTable)
 
void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 *S, float32_t *p1)
 
void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 *S, float32_t *p1)
 
void arm_cfft_f32 (const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Processing function for the floating-point complex FFT.  More...
 
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void arm_bitreversal_32 (uint32_t * pSrc, 
const uint16_t bitRevLen, 
const uint16_t * pBitRevTable 
)
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Referenced by arm_cfft_f32().
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void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, 
float32_t * p1 
)
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References arm_radix8_butterfly_f32(), arm_cfft_instance_f32::fftLen, and arm_cfft_instance_f32::pTwiddle.
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Referenced by arm_cfft_f32().
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void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, 
float32_t * p1 
)
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References arm_radix8_butterfly_f32(), arm_cfft_instance_f32::fftLen, and arm_cfft_instance_f32::pTwiddle.
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Referenced by arm_cfft_f32().
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void arm_radix8_butterfly_f32 (float32_t * pSrc, 
uint16_t fftLen, 
const float32_t * pCoef, 
uint16_t twidCoefModifier 
)
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Referenced by arm_cfft_f32(), arm_cfft_radix8by2_f32(), and arm_cfft_radix8by4_f32().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix2_f32.c File Reference
  
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void arm_radix2_butterfly_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 
void arm_radix2_butterfly_inverse_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Radix-2 CFFT/CIFFT.  More...
 
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void arm_bitreversal_f32 (float32_t * pSrc, 
uint16_t fftSize, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix2_butterfly_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)
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end of ComplexFFT group 
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Referenced by arm_cfft_radix2_f32().
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void arm_radix2_butterfly_inverse_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)
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Referenced by arm_cfft_radix2_f32().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_init_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix2_init_f32.c File Reference
  
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arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix2_init_q15.c File Reference
  
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arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix2_init_q31.c File Reference
  
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arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
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arm_cfft_radix2_q15.c File Reference
  
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void arm_radix2_butterfly_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 
void arm_radix2_butterfly_inverse_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pCoef, uint16_t twidCoefModifier)
 
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_q15 (q15_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix2_butterfly_inverse_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)
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References _SIMD32_OFFSET.
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Referenced by arm_cfft_radix2_q15().
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void arm_radix2_butterfly_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pCoef, 
uint16_t twidCoefModifier 
)
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end of ComplexFFT group 
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References _SIMD32_OFFSET.
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Referenced by arm_cfft_radix2_q15().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix2_q31.c File Reference
  
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void arm_radix2_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 
void arm_radix2_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint16_t twidCoefModifier)
 
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
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void arm_bitreversal_q31 (q31_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix2_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)
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Referenced by arm_cfft_radix2_q31().
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void arm_radix2_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint16_t twidCoefModifier 
)
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end of ComplexFFT group 
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Referenced by arm_cfft_radix2_q31().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix4_f32.c File Reference
  
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void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-4 CFFT/CIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_f32 (float32_t * pSrc, 
uint16_t fftSize, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix4_butterfly_inverse_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
float32_t onebyfftLen 
)
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Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().
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arm_cfft_radix4_init_f32.c File Reference
  
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arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix4_init_q15.c File Reference
  
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arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cfft__radix4__init__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cfft_radix4_init_q31.c File Reference
  
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arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_cfft_radix4_q15.c File Reference
  
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void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CFFT butterfly process.  More...
 
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CIFFT butterfly process.  More...
 
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_q15 (q15_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix4_butterfly_inverse_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD32, and _SIMD32_OFFSET.
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Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().
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void arm_radix4_butterfly_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)
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end of ComplexFFT group 
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Parameters
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[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD32, and _SIMD32_OFFSET.
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Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cfft__radix4__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_cfft_radix4_q31.c File Reference
  
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void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CIFFT butterfly process.  More...
 
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CFFT butterfly process.  More...
 
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_q31 (q31_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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void arm_radix4_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD64.
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Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().
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void arm_radix4_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)
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end of ComplexFFT group 
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Parameters
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[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD64.
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Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cfft__radix8__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix8_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_cfft_radix8_f32.c File Reference
  
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void arm_radix8_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, const float32_t *pCoef, uint16_t twidCoefModifier)
 
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Function Documentation
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void arm_radix8_butterfly_f32 (float32_t * pSrc, 
uint16_t fftLen, 
const float32_t * pCoef, 
uint16_t twidCoefModifier 
)
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Referenced by arm_cfft_f32(), arm_cfft_radix8by2_f32(), and arm_cfft_radix8by4_f32().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__class__marks__example__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_class_marks_example_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_class_marks_example_f32.c File Reference
  
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\nMacros
#define USE_STATIC_INIT
 
#define TEST_LENGTH_SAMPLES
 
#define NUMSTUDENTS
 
#define NUMSUBJECTS
 
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int32_t main ()
 
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const float32_t testMarks_f32 [TEST_LENGTH_SAMPLES]
 
const float32_t testUnity_f32 [4]
 
static float32_t testOutput [TEST_LENGTH_SAMPLES]
 
uint32_t numStudents
 
uint32_t numSubjects
 
float32_t max_marks
 
float32_t min_marks
 
float32_t mean
 
float32_t std
 
float32_t var
 
uint32_t student_num
 
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Macro Definition Documentation
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#define NUMSTUDENTS
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Examples: 
arm_class_marks_example_f32.c.
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#define NUMSUBJECTS
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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#define TEST_LENGTH_SAMPLES
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Examples: 
arm_class_marks_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_linear_interp_example_f32.c, and arm_signal_converge_example_f32.c.
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#define USE_STATIC_INIT
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Function Documentation
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int32_t main (void )
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Examples: 
arm_class_marks_example_f32.c, arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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References arm_mat_init_f32(), arm_mat_mult_f32(), arm_max_f32(), arm_mean_f32(), arm_min_f32(), arm_std_f32(), arm_var_f32(), max_marks, mean, min_marks, NUMSTUDENTS, numStudents, NUMSUBJECTS, numSubjects, std, student_num, testMarks_f32, testOutput, testUnity_f32, and var.
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Variable Documentation
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float32_t max_marks
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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float32_t mean
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Examples: 
arm_class_marks_example_f32.c, and arm_variance_example_f32.c.
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Referenced by arm_std_f32(), arm_std_q15(), arm_std_q31(), arm_var_f32(), arm_var_q15(), arm_var_q31(), and main().
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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Examples: 
arm_class_marks_example_f32.c.
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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const float32_t testMarks_f32[TEST_LENGTH_SAMPLES]
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Examples: 
arm_class_marks_example_f32.c.
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Examples: 
arm_class_marks_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.
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const float32_t testUnity_f32[4]
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by main().
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Examples: 
arm_class_marks_example_f32.c.
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Referenced by arm_std_f32(), and main().
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cmplx__conj__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_conj_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  More...
 
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arm_cmplx_conj_q15.c File Reference
  
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void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_conj_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_conj_q31.c File Reference
  
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void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_dot_prod_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_dot_prod_f32.c File Reference
  
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void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_dot_prod_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_dot_prod_q15.c File Reference
  
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void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cmplx__dot__prod__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_dot_prod_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_dot_prod_q31.c File Reference
  
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void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  More...
 
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arm_cmplx_mag_f32.c File Reference
  
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void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  More...
 
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arm_cmplx_mag_q15.c File Reference
  
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void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  More...
 
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arm_cmplx_mag_q31.c File Reference
  
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void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  More...
 
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arm_cmplx_mag_squared_f32.c File Reference
  
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void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  More...
 
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arm_cmplx_mag_squared_q15.c File Reference
  
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void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  More...
 
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arm_cmplx_mag_squared_q31.c File Reference
  
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void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  More...
 
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arm_cmplx_mult_cmplx_f32.c File Reference
  
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void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  More...
 
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arm_cmplx_mult_cmplx_q15.c File Reference
  
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void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  More...
 
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arm_cmplx_mult_cmplx_q31.c File Reference
  
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void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_mult_real_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_mult_real_f32.c File Reference
  
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void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  More...
 
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arm_cmplx_mult_real_q15.c File Reference
  
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void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cmplx_mult_real_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_cmplx_mult_real_q31.c File Reference
  
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void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_common_tables.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\nVariables
const uint16_t armBitRevTable [1024]
 
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const float32_t twiddleCoef_32 [64]
 
const float32_t twiddleCoef_64 [128]
 
const float32_t twiddleCoef_128 [256]
 
const float32_t twiddleCoef_256 [512]
 
const float32_t twiddleCoef_512 [1024]
 
const float32_t twiddleCoef_1024 [2048]
 
const float32_t twiddleCoef_2048 [4096]
 
const float32_t twiddleCoef_4096 [8192]
 
const q31_t twiddleCoefQ31 [6144]
 
const q15_t ALIGN4 twiddleCoefQ15 [6144]
 
const q15_t ALIGN4 armRecipTableQ15 [64]
 
const q31_t armRecipTableQ31 [64]
 
const uint16_t armBitRevIndexTable16 [ARMBITREVINDEXTABLE__16_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable32 [ARMBITREVINDEXTABLE__32_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable64 [ARMBITREVINDEXTABLE__64_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable128 [ARMBITREVINDEXTABLE_128_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable256 [ARMBITREVINDEXTABLE_256_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable512 [ARMBITREVINDEXTABLE_512_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable1024 [ARMBITREVINDEXTABLE1024_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable2048 [ARMBITREVINDEXTABLE2048_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable4096 [ARMBITREVINDEXTABLE4096_TABLE_LENGTH]
 
const float32_t twiddleCoef_rfft_32 [32]
 
const float32_t twiddleCoef_rfft_64 [64]
 
const float32_t twiddleCoef_rfft_128 [128]
 
const float32_t twiddleCoef_rfft_256 [256]
 
const float32_t twiddleCoef_rfft_512 [512]
 
const float32_t twiddleCoef_rfft_1024 [1024]
 
const float32_t twiddleCoef_rfft_2048 [2048]
 
const float32_t twiddleCoef_rfft_4096 [4096]
 
\n
Variable Documentation
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const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const q15_t ALIGN4 armRecipTableQ15[64]
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end of CFFT_CIFFT group 
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Referenced by arm_lms_norm_init_q15().
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const q31_t armRecipTableQ31[64]
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Referenced by arm_lms_norm_init_q31().
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const float32_t twiddleCoef_rfft_1024[1024]
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const float32_t twiddleCoef_rfft_128[128]
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const float32_t twiddleCoef_rfft_2048[2048]
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const float32_t twiddleCoef_rfft_256[256]
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const float32_t twiddleCoef_rfft_32[32]
\n
\n
Example code for Floating-point RFFT Twiddle factors Generation: 
\n
TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' 
 
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Real and Imag values are in interleaved fashion 
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const float32_t twiddleCoef_rfft_4096[4096]
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const float32_t twiddleCoef_rfft_512[512]
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const float32_t twiddleCoef_rfft_64[64]
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__common__tables_8h.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_common_tables.h File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_common_tables.h File Reference
  
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\nMacros
#define twiddleCoef
 
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH
 
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nVariables
const uint16_t armBitRevTable [1024]
 
const q15_t armRecipTableQ15 [64]
 
const q31_t armRecipTableQ31 [64]
 
const q31_t realCoefAQ31 [1024]
 
const q31_t realCoefBQ31 [1024]
 
const float32_t twiddleCoef_16 [32]
 
const float32_t twiddleCoef_32 [64]
 
const float32_t twiddleCoef_64 [128]
 
const float32_t twiddleCoef_128 [256]
 
const float32_t twiddleCoef_256 [512]
 
const float32_t twiddleCoef_512 [1024]
 
const float32_t twiddleCoef_1024 [2048]
 
const float32_t twiddleCoef_2048 [4096]
 
const float32_t twiddleCoef_4096 [8192]
 
const q31_t twiddleCoefQ31 [6144]
 
const q15_t twiddleCoefQ15 [6144]
 
const float32_t twiddleCoef_rfft_32 [32]
 
const float32_t twiddleCoef_rfft_64 [64]
 
const float32_t twiddleCoef_rfft_128 [128]
 
const float32_t twiddleCoef_rfft_256 [256]
 
const float32_t twiddleCoef_rfft_512 [512]
 
const float32_t twiddleCoef_rfft_1024 [1024]
 
const float32_t twiddleCoef_rfft_2048 [2048]
 
const float32_t twiddleCoef_rfft_4096 [4096]
 
const uint16_t armBitRevIndexTable16 [ARMBITREVINDEXTABLE__16_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable32 [ARMBITREVINDEXTABLE__32_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable64 [ARMBITREVINDEXTABLE__64_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable128 [ARMBITREVINDEXTABLE_128_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable256 [ARMBITREVINDEXTABLE_256_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable512 [ARMBITREVINDEXTABLE_512_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable1024 [ARMBITREVINDEXTABLE1024_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable2048 [ARMBITREVINDEXTABLE2048_TABLE_LENGTH]
 
const uint16_t armBitRevIndexTable4096 [ARMBITREVINDEXTABLE4096_TABLE_LENGTH]
 
\n
Macro Definition Documentation
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH
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Referenced by arm_rfft_fast_init_f32().
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#define twiddleCoef
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Referenced by arm_cfft_radix2_init_f32(), and arm_cfft_radix4_init_f32().
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Variable Documentation
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const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]
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Referenced by arm_rfft_fast_init_f32().
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const q15_t armRecipTableQ15[64]
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end of CFFT_CIFFT group 
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Referenced by arm_lms_norm_init_q15().
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const q31_t armRecipTableQ31[64]
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Referenced by arm_lms_norm_init_q31().
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const q31_t realCoefAQ31[1024]
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const q31_t realCoefBQ31[1024]
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const float32_t twiddleCoef_rfft_1024[1024]
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const float32_t twiddleCoef_rfft_128[128]
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const float32_t twiddleCoef_rfft_2048[2048]
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const float32_t twiddleCoef_rfft_256[256]
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const float32_t twiddleCoef_rfft_32[32]
\n
\n
Example code for Floating-point RFFT Twiddle factors Generation: 
\n
TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' 
 
\n
Real and Imag values are in interleaved fashion 
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const float32_t twiddleCoef_rfft_4096[4096]
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const float32_t twiddleCoef_rfft_512[512]
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const float32_t twiddleCoef_rfft_64[64]
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__const__structs_8h.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_const_structs.h File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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arm_const_structs.h File Reference
  
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\nVariables
const arm_cfft_instance_f32 arm_cfft_sR_f32_len16
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len32
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len64
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len128
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len256
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len512
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048
 
const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096
 
\n
Variable Documentation
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024
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Examples: 
arm_fft_bin_example_f32.c.
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Referenced by main().
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len128
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len16
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len256
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len32
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len512
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const arm_cfft_instance_f32 arm_cfft_sR_f32_len64
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_conv_f32.c File Reference
  
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\nFunctions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  More...
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__fast__opt__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_fast_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_fast_opt_q15.c File Reference
  
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void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_fast_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_conv_fast_q15.c File Reference
  
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void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__fast__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_fast_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_conv_fast_q31.c File Reference
  
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void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__opt__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_opt_q15.c File Reference
  
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void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__opt__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_opt_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_conv_opt_q7.c File Reference
  
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void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_f32.c File Reference
  
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arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__opt__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_fast_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_fast_opt_q15.c File Reference
  
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arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_fast_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_fast_q15.c File Reference
  
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arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__fast__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_fast_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_fast_q31.c File Reference
  
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arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_conv_partial_opt_q15.c File Reference
  
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arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__opt__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_opt_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_opt_q7.c File Reference
  
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arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_q15.c File Reference
  
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arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_q31.c File Reference
  
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arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__partial__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_partial_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_partial_q7.c File Reference
  
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arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_q15.c File Reference
  
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void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_q31.c File Reference
  
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void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__conv__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_conv_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_conv_q7.c File Reference
  
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void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__convolution__example__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_convolution_example_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_convolution_example_f32.c File Reference
  
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#define MAX_BLOCKSIZE
 
#define DELTA
 
#define SNR_THRESHOLD
 
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int32_t main (void)
 
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float32_t Ak [MAX_BLOCKSIZE]
 
float32_t Bk [MAX_BLOCKSIZE]
 
float32_t AxB [MAX_BLOCKSIZE *2]
 
float32_t testInputA_f32 [64]
 
float32_t testInputB_f32 [64]
 
const float testRefOutput_f32 [126]
 
uint32_t srcALen
 
uint32_t srcBLen
 
uint32_t outLen
 
float32_t snr
 
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Macro Definition Documentation
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#define DELTA
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Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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#define MAX_BLOCKSIZE
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Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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#define SNR_THRESHOLD
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Examples: 
arm_convolution_example_f32.c, and arm_matrix_example_f32.c.
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Function Documentation
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int32_t main (void )
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References Ak, arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), arm_cmplx_mult_cmplx_f32(), arm_copy_f32(), arm_fill_f32(), ARM_MATH_SUCCESS, arm_snr_f32(), AxB, Bk, MAX_BLOCKSIZE, outLen, snr, SNR_THRESHOLD, srcALen, srcBLen, status, testInputA_f32, testInputB_f32, and testRefOutput_f32.
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Variable Documentation
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float32_t Ak[MAX_BLOCKSIZE]
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Examples: 
arm_convolution_example_f32.c.
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float32_t AxB[MAX_BLOCKSIZE *2]
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Examples: 
arm_convolution_example_f32.c.
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float32_t Bk[MAX_BLOCKSIZE]
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Examples: 
arm_convolution_example_f32.c.
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uint32_t outLen
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Examples: 
arm_convolution_example_f32.c.
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float32_t snr
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Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_matrix_example_f32.c.
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uint32_t srcALen
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Examples: 
arm_convolution_example_f32.c.
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Referenced by arm_conv_f32(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_fast_q31(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_conv_q15(), arm_conv_q31(), arm_conv_q7(), arm_correlate_f32(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_fast_q31(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_correlate_q31(), arm_correlate_q7(), and main().
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uint32_t srcBLen
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Examples: 
arm_convolution_example_f32.c.
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Referenced by arm_conv_f32(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_fast_q31(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_conv_q15(), arm_conv_q31(), arm_conv_q7(), arm_correlate_f32(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_fast_q31(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_correlate_q31(), arm_correlate_q7(), and main().
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arm_convolution_example_f32.c.
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arm_convolution_example_f32.c.
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const float testRefOutput_f32[126]
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arm_convolution_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_sin_cos_example_f32.c.
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void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  More...
 
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arm_copy_q15.c File Reference
  
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void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  More...
 
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void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  More...
 
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void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  More...
 
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void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_correlate_fast_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_correlate_fast_opt_q15.c File Reference
  
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void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_correlate_fast_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_correlate_fast_q31.c File Reference
  
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void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_correlate_opt_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_correlate_opt_q15.c File Reference
  
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void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  More...
 
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arm_correlate_opt_q7.c File Reference
  
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void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  More...
 
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arm_correlate_q15.c File Reference
  
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void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_correlate_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  More...
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__correlate__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_correlate_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_correlate_q7.c File Reference
  
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void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cos__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cos_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_cos_f32.c File Reference
  
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float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  More...
 
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static const float32_t cosTable [260]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cos__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cos_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_cos_q15.c File Reference
  
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q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  More...
 
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static const q15_t cosTableQ15 [259]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__cos__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cos_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_cos_q31.c File Reference
  
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q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  More...
 
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static const q31_t cosTableQ31 [259]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__dct4__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_dct4_f32.c File Reference
  
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void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  More...
 
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_dct4_init_f32.c File Reference
  
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arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  More...
 
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static const float32_t Weights_128 [256]
 
static const float32_t Weights_512 [1024]
 
static const float32_t Weights_2048 [4096]
 
static const float32_t Weights_8192 [16384]
 
static const float32_t cos_factors_128 [128]
 
static const float32_t cos_factors_512 [512]
 
static const float32_t cos_factors_2048 [2048]
 
static const float32_t cos_factors_8192 [8192]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__dct4__init__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_dct4_init_q15.c File Reference
  
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arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  More...
 
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static const q15_t ALIGN4 WeightsQ15_128 [256]
 
static const q15_t ALIGN4 WeightsQ15_512 [1024]
 
static const q15_t ALIGN4 WeightsQ15_2048 [4096]
 
static const q15_t ALIGN4 WeightsQ15_8192 [16384]
 
static const q15_t ALIGN4 cos_factorsQ15_128 [128]
 
static const q15_t ALIGN4 cos_factorsQ15_512 [512]
 
static const q15_t ALIGN4 cos_factorsQ15_2048 [2048]
 
static const q15_t ALIGN4 cos_factorsQ15_8192 [8192]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__dct4__init__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_dct4_init_q31.c File Reference
  
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arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  More...
 
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static const q31_t WeightsQ31_128 [256]
 
static const q31_t WeightsQ31_512 [1024]
 
static const q31_t WeightsQ31_2048 [4096]
 
static const q31_t WeightsQ31_8192 [16384]
 
static const q31_t cos_factorsQ31_128 [128]
 
static const q31_t cos_factorsQ31_512 [512]
 
static const q31_t cos_factorsQ31_2048 [2048]
 
static const q31_t cos_factorsQ31_8192 [8192]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__dct4__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_dct4_q15.c File Reference
  
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void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  More...
 
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arm_dct4_q31.c File Reference
  
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void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  More...
 
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arm_dot_prod_f32.c File Reference
  
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void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_dot_prod_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_dot_prod_q15.c File Reference
  
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void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  More...
 
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arm_dot_prod_q31.c File Reference
  
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void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_dot_prod_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_dot_prod_q7.c File Reference
  
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void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_dotproduct_example_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_dotproduct_example_f32.c File Reference
  
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#define MAX_BLOCKSIZE
 
#define DELTA
 
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int32_t main (void)
 
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float32_t srcA_buf_f32 [MAX_BLOCKSIZE]
 
float32_t srcB_buf_f32 [MAX_BLOCKSIZE]
 
float32_t refDotProdOut
 
float32_t multOutput [MAX_BLOCKSIZE]
 
float32_t testOutput
 
arm_status status
 
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Macro Definition Documentation
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#define DELTA
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#define MAX_BLOCKSIZE
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Function Documentation
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int32_t main (void )
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References arm_add_f32(), ARM_MATH_TEST_FAILURE, arm_mult_f32(), DELTA, MAX_BLOCKSIZE, multOutput, refDotProdOut, srcA_buf_f32, srcB_buf_f32, status, and testOutput.
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Variable Documentation
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float32_t multOutput[MAX_BLOCKSIZE]
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Examples: 
arm_dotproduct_example_f32.c.
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Referenced by main().
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float32_t refDotProdOut
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Examples: 
arm_dotproduct_example_f32.c.
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float32_t srcA_buf_f32[MAX_BLOCKSIZE]
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Examples: 
arm_dotproduct_example_f32.c.
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float32_t srcB_buf_f32[MAX_BLOCKSIZE]
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Examples: 
arm_dotproduct_example_f32.c.
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Referenced by main().
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arm_status status
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Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), arm_cfft_radix4_init_q31(), arm_conv_partial_f32(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_fast_q31(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_partial_q31(), arm_conv_partial_q7(), arm_dct4_init_f32(), arm_dct4_init_q15(), arm_dct4_init_q31(), arm_fir_decimate_init_f32(), arm_fir_decimate_init_q15(), arm_fir_decimate_init_q31(), arm_fir_init_q15(), arm_fir_interpolate_init_f32(), arm_fir_interpolate_init_q15(), arm_fir_interpolate_init_q31(), arm_mat_add_f32(), arm_mat_add_q15(), arm_mat_add_q31(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_mult_fast_q15(), arm_mat_mult_fast_q31(), arm_mat_mult_q15(), arm_mat_mult_q31(), arm_mat_scale_f32(), arm_mat_scale_q15(), arm_mat_scale_q31(), arm_mat_sub_f32(), arm_mat_sub_q15(), arm_mat_sub_q31(), arm_mat_trans_f32(), arm_mat_trans_q15(), arm_mat_trans_q31(), arm_rfft_fast_init_f32(), arm_rfft_init_f32(), arm_rfft_init_q15(), arm_rfft_init_q31(), and main().
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__fft__bin__data_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fft_bin_data.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fft_bin_data.c File Reference
  
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float32_t testInput_f32_10khz [2048]
 
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Variable Documentation
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float32_t testInput_f32_10khz[2048]
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Examples: 
arm_fft_bin_example_f32.c.
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arm_fft_bin_example_f32.c File Reference
  
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#define TEST_LENGTH_SAMPLES
 
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int32_t main (void)
 
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float32_t testInput_f32_10khz [TEST_LENGTH_SAMPLES]
 
static float32_t testOutput [TEST_LENGTH_SAMPLES/2]
 
uint32_t fftSize
 
uint32_t ifftFlag
 
uint32_t doBitReverse
 
uint32_t refIndex
 
uint32_t testIndex
 
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#define TEST_LENGTH_SAMPLES
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int32_t main (void )
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References arm_cfft_f32(), arm_cfft_sR_f32_len1024, arm_cmplx_mag_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_max_f32(), doBitReverse, fftSize, ifftFlag, refIndex, status, testIndex, testInput_f32_10khz, and testOutput.
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uint32_t doBitReverse
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arm_fft_bin_example_f32.c.
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uint32_t fftSize
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Examples: 
arm_fft_bin_example_f32.c.
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uint32_t ifftFlag
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Examples: 
arm_fft_bin_example_f32.c.
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Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), arm_cfft_radix4_init_q31(), and main().
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Examples: 
arm_fft_bin_example_f32.c.
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Examples: 
arm_fft_bin_example_f32.c.
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float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]
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void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  More...
 
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void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  More...
 
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void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  More...
 
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void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  More...
 
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float32_t testInput_f32_1kHz_15kHz [320]
 
float32_t refOutput [320]
 
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arm_fir_example_f32.c.
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arm_fir_example_f32.c.
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void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__fir__decimate__fast__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_fast_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_decimate_fast_q15.c File Reference
  
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void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_fast_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_decimate_fast_q31.c File Reference
  
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void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__fir__decimate__init__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_init_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_decimate_init_f32.c File Reference
  
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arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_decimate_init_q15.c File Reference
  
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arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  More...
 
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arm_fir_decimate_init_q31.c File Reference
  
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arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__fir__decimate__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_decimate_q15.c File Reference
  
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void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  More...
 
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arm_fir_decimate_q31.c File Reference
  
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void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_example_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_example_f32.c File Reference
  
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#define TEST_LENGTH_SAMPLES
 
#define SNR_THRESHOLD_F32
 
#define BLOCK_SIZE
 
#define NUM_TAPS
 
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int32_t main (void)
 
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float32_t testInput_f32_1kHz_15kHz [TEST_LENGTH_SAMPLES]
 
float32_t refOutput [TEST_LENGTH_SAMPLES]
 
static float32_t testOutput [TEST_LENGTH_SAMPLES]
 
static float32_t firStateF32 [BLOCK_SIZE+NUM_TAPS-1]
 
const float32_t firCoeffs32 [NUM_TAPS]
 
uint32_t blockSize
 
uint32_t numBlocks
 
float32_t snr
 
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arm_fir_example_f32.c.
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#define NUM_TAPS
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arm_fir_example_f32.c.
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#define SNR_THRESHOLD_F32
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arm_fir_example_f32.c, and arm_graphic_equalizer_example_q31.c.
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int32_t main (void )
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References arm_fir_f32(), arm_fir_init_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_snr_f32(), blockSize, firCoeffs32, firStateF32, NUM_TAPS, numBlocks, refOutput, snr, SNR_THRESHOLD_F32, status, TEST_LENGTH_SAMPLES, testInput_f32_1kHz_15kHz, and testOutput.
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arm_fir_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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Referenced by arm_abs_f32(), arm_abs_q15(), arm_abs_q31(), arm_abs_q7(), arm_add_f32(), arm_add_q15(), arm_add_q31(), arm_add_q7(), arm_biquad_cas_df1_32x64_q31(), arm_biquad_cascade_df1_f32(), arm_biquad_cascade_df1_q31(), arm_biquad_cascade_df2T_f32(), arm_circularRead_f32(), arm_circularRead_q15(), arm_circularRead_q7(), arm_circularWrite_f32(), arm_circularWrite_q15(), arm_circularWrite_q7(), arm_copy_f32(), arm_copy_q15(), arm_copy_q31(), arm_copy_q7(), arm_dot_prod_f32(), arm_dot_prod_q15(), arm_dot_prod_q31(), arm_dot_prod_q7(), arm_fill_f32(), arm_fill_q15(), arm_fill_q31(), arm_fill_q7(), arm_fir_lattice_f32(), arm_fir_lattice_q15(), arm_fir_q31(), arm_fir_q7(), arm_fir_sparse_f32(), arm_fir_sparse_q15(), arm_fir_sparse_q31(), arm_fir_sparse_q7(), arm_float_to_q15(), arm_float_to_q31(), arm_float_to_q7(), arm_iir_lattice_f32(), arm_iir_lattice_q15(), arm_iir_lattice_q31(), arm_lms_f32(), arm_lms_norm_f32(), arm_lms_norm_q15(), arm_lms_norm_q31(), arm_lms_q15(), arm_lms_q31(), arm_mean_f32(), arm_mean_q15(), arm_mean_q31(), arm_mean_q7(), arm_mult_f32(), arm_mult_q15(), arm_mult_q31(), arm_mult_q7(), arm_negate_f32(), arm_negate_q15(), arm_negate_q31(), arm_negate_q7(), arm_offset_f32(), arm_offset_q15(), arm_offset_q31(), arm_offset_q7(), arm_power_f32(), arm_power_q15(), arm_power_q31(), arm_power_q7(), arm_provide_guard_bits_q15(), arm_provide_guard_bits_q31(), arm_provide_guard_bits_q7(), arm_q15_to_float(), arm_q15_to_q31(), arm_q15_to_q7(), arm_q31_to_float(), arm_q31_to_q15(), arm_q31_to_q7(), arm_q7_to_float(), arm_q7_to_q15(), arm_q7_to_q31(), arm_rms_f32(), arm_rms_q15(), arm_rms_q31(), arm_scale_f32(), arm_scale_q15(), arm_scale_q31(), arm_scale_q7(), arm_shift_q15(), arm_shift_q31(), arm_shift_q7(), arm_std_f32(), arm_std_q15(), arm_std_q31(), arm_sub_f32(), arm_sub_q15(), arm_sub_q31(), arm_sub_q7(), arm_var_f32(), arm_var_q15(), arm_var_q31(), and main().
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const float32_t firCoeffs32[NUM_TAPS]
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arm_fir_example_f32.c.
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arm_fir_example_f32.c.
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float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]
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void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  More...
 
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void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
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IAR_ONLY_LOW_OPTIMIZATION_ENTER 
\nvoid 		arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
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void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  More...
 
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arm_fir_init_q15.c File Reference
  
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arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  More...
 
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void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  More...
 
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void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  More...
 
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void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  More...
 
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arm_fir_interpolate_init_f32.c File Reference
  
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arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  More...
 
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arm_fir_interpolate_init_q15.c File Reference
  
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arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_interpolate_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_interpolate_init_q31.c File Reference
  
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arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  More...
 
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arm_fir_interpolate_q15.c File Reference
  
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void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  More...
 
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arm_fir_interpolate_q31.c File Reference
  
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void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_lattice_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_lattice_f32.c File Reference
  
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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  More...
 
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arm_fir_lattice_init_f32.c File Reference
  
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void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  More...
 
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arm_fir_lattice_init_q15.c File Reference
  
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void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  More...
 
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arm_fir_lattice_init_q31.c File Reference
  
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void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  More...
 
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arm_fir_lattice_q15.c File Reference
  
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void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  More...
 
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arm_fir_lattice_q31.c File Reference
  
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void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  More...
 
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arm_fir_q15.c File Reference
  
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void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  More...
 
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arm_fir_q31.c File Reference
  
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void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  More...
 
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arm_fir_q7.c File Reference
  
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void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  More...
 
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arm_fir_sparse_f32.c File Reference
  
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void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  More...
 
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arm_fir_sparse_init_f32.c File Reference
  
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void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_sparse_init_q15.c File Reference
  
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void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_sparse_init_q31.c File Reference
  
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void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_init_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  More...
 
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arm_fir_sparse_q15.c File Reference
  
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void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_sparse_q31.c File Reference
  
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void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_fir_sparse_q7.c File Reference
  
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void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_float_to_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_float_to_q15.c File Reference
  
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void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  More...
 
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arm_float_to_q31.c File Reference
  
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void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  More...
 
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void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  More...
 
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arm_graphic_equalizer_data.c File Reference
  
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float32_t testRefOutput_f32 [320]
 
float32_t testInput_f32 [320]
 
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Variable Documentation
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float32_t testInput_f32[320]
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Examples: 
arm_graphic_equalizer_example_q31.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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arm_graphic_equalizer_example_q31.c File Reference
  
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#define TESTLENGTH
 
#define BLOCKSIZE
 
#define NUMBLOCKS
 
#define NUMSTAGES
 
#define SNR_THRESHOLD_F32
 
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int32_t main (void)
 
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float32_t testInput_f32 [TESTLENGTH]
 
static float32_t testOutput [TESTLENGTH]
 
float32_t testRefOutput_f32 [TESTLENGTH]
 
static q63_t biquadStateBand1Q31 [4 *2]
 
static q63_t biquadStateBand2Q31 [4 *2]
 
static q31_t biquadStateBand3Q31 [4 *2]
 
static q31_t biquadStateBand4Q31 [4 *2]
 
static q31_t biquadStateBand5Q31 [4 *2]
 
q31_t inputQ31 [BLOCKSIZE]
 
q31_t outputQ31 [BLOCKSIZE]
 
const q31_t coeffTable [950]
 
int gainDB [5]
 
float32_t snr
 
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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int32_t main (void )
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References arm_biquad_cas_df1_32x64_init_q31(), arm_biquad_cas_df1_32x64_q31(), arm_biquad_cascade_df1_init_q31(), arm_biquad_cascade_df1_q31(), arm_float_to_q31(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_q31_to_float(), arm_scale_f32(), arm_scale_q31(), arm_snr_f32(), biquadStateBand1Q31, biquadStateBand2Q31, biquadStateBand3Q31, biquadStateBand4Q31, biquadStateBand5Q31, BLOCKSIZE, coeffTable, gainDB, inputQ31, NUMBLOCKS, NUMSTAGES, outputQ31, snr, SNR_THRESHOLD_F32, status, testInput_f32, TESTLENGTH, testOutput, and testRefOutput_f32.
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q63_t biquadStateBand1Q31[4 *2]
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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const q31_t coeffTable[950]
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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arm_graphic_equalizer_example_q31.c.
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void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  More...
 
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void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  More...
 
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arm_iir_lattice_init_q15.c File Reference
  
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void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  More...
 
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void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__iir__lattice__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_iir_lattice_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_iir_lattice_q15.c File Reference
  
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void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_iir_lattice_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_iir_lattice_q31.c File Reference
  
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void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_linear_interp_data.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_linear_interp_data.c File Reference
  
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float arm_linear_interep_table [188495]
 
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float arm_linear_interep_table[188495]
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arm_linear_interp_example_f32.c.
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arm_linear_interp_example_f32.c File Reference
  
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#define SNR_THRESHOLD
 
#define TEST_LENGTH_SAMPLES
 
#define XSPACING
 
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int32_t main (void)
 
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float32_t testInputSin_f32 [TEST_LENGTH_SAMPLES]
 
float32_t testRefSinOutput32_f32 [TEST_LENGTH_SAMPLES]
 
float32_t testOutput [TEST_LENGTH_SAMPLES]
 
float32_t testLinIntOutput [TEST_LENGTH_SAMPLES]
 
float arm_linear_interep_table [188495]
 
float32_t snr1
 
float32_t snr2
 
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#define SNR_THRESHOLD
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arm_linear_interp_example_f32.c.
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int32_t main (void )
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References arm_linear_interep_table, arm_linear_interp_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_sin_f32(), arm_snr_f32(), snr1, snr2, status, TEST_LENGTH_SAMPLES, testInputSin_f32, testLinIntOutput, testOutput, testRefSinOutput32_f32, and XSPACING.
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float arm_linear_interep_table[188495]
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float32_t snr1
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arm_linear_interp_example_f32.c.
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arm_linear_interp_example_f32.c.
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arm_linear_interp_example_f32.c.
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arm_linear_interp_example_f32.c.
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float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES]
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arm_linear_interp_example_f32.c.
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  More...
 
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void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  More...
 
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arm_lms_init_q15.c File Reference
  
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void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  More...
 
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void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  More...
 
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void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  More...
 
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void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  More...
 
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void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_norm_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  More...
 
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void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_norm_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  More...
 
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arm_lms_q15.c File Reference
  
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void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__lms__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_q31.c File Reference
  
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void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__add__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_add_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mat_add_f32.c File Reference
  
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arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__add__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_add_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mat_add_q15.c File Reference
  
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arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__add__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_add_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mat_add_q31.c File Reference
  
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arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__init__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_init_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mat_init_f32.c File Reference
  
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void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  More...
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__init__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mat_init_q15.c File Reference
  
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void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__init__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mat_init_q31.c File Reference
  
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void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__inverse__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_inverse_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mat_inverse_f32.c File Reference
  
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arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix inverse.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__mult__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_mult_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mat_mult_f32.c File Reference
  
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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  More...
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_mult_fast_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_mult_fast_q15.c File Reference
  
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arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__mult__fast__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_mult_fast_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_mult_fast_q31.c File Reference
  
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arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__mult__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_mult_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_mult_q15.c File Reference
  
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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState CMSIS_UNUSED)
 Q15 matrix multiplication.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__mult__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_mult_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_mult_q31.c File Reference
  
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arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__scale__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_scale_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mat_scale_f32.c File Reference
  
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arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__scale__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_scale_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_scale_q15.c File Reference
  
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arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__scale__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_scale_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_scale_q31.c File Reference
  
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arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__sub__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_sub_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_sub_f32.c File Reference
  
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arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mat__sub__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mat_sub_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_mat_sub_q15.c File Reference
  
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arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  More...
 
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arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  More...
 
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arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  More...
 
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arm_mat_trans_q15.c File Reference
  
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arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  More...
 
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arm_mat_trans_q31.c File Reference
  
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arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  More...
 
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arm_math.h File Reference
  
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\nData Structures
struct  arm_fir_instance_q7
 Instance structure for the Q7 FIR filter.  More...
 
struct  arm_fir_instance_q15
 Instance structure for the Q15 FIR filter.  More...
 
struct  arm_fir_instance_q31
 Instance structure for the Q31 FIR filter.  More...
 
struct  arm_fir_instance_f32
 Instance structure for the floating-point FIR filter.  More...
 
struct  arm_biquad_casd_df1_inst_q15
 Instance structure for the Q15 Biquad cascade filter.  More...
 
struct  arm_biquad_casd_df1_inst_q31
 Instance structure for the Q31 Biquad cascade filter.  More...
 
struct  arm_biquad_casd_df1_inst_f32
 Instance structure for the floating-point Biquad cascade filter.  More...
 
struct  arm_matrix_instance_f32
 Instance structure for the floating-point matrix structure.  More...
 
struct  arm_matrix_instance_q15
 Instance structure for the Q15 matrix structure.  More...
 
struct  arm_matrix_instance_q31
 Instance structure for the Q31 matrix structure.  More...
 
struct  arm_pid_instance_q15
 Instance structure for the Q15 PID Control.  More...
 
struct  arm_pid_instance_q31
 Instance structure for the Q31 PID Control.  More...
 
struct  arm_pid_instance_f32
 Instance structure for the floating-point PID Control.  More...
 
struct  arm_linear_interp_instance_f32
 Instance structure for the floating-point Linear Interpolate function.  More...
 
struct  arm_bilinear_interp_instance_f32
 Instance structure for the floating-point bilinear interpolation function.  More...
 
struct  arm_bilinear_interp_instance_q31
 Instance structure for the Q31 bilinear interpolation function.  More...
 
struct  arm_bilinear_interp_instance_q15
 Instance structure for the Q15 bilinear interpolation function.  More...
 
struct  arm_bilinear_interp_instance_q7
 Instance structure for the Q15 bilinear interpolation function.  More...
 
struct  arm_cfft_radix2_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
 
struct  arm_cfft_radix4_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
 
struct  arm_cfft_radix2_instance_q31
 Instance structure for the Radix-2 Q31 CFFT/CIFFT function.  More...
 
struct  arm_cfft_radix4_instance_q31
 Instance structure for the Q31 CFFT/CIFFT function.  More...
 
struct  arm_cfft_radix2_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
 
struct  arm_cfft_radix4_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
 
struct  arm_cfft_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
 
struct  arm_rfft_instance_q15
 Instance structure for the Q15 RFFT/RIFFT function.  More...
 
struct  arm_rfft_instance_q31
 Instance structure for the Q31 RFFT/RIFFT function.  More...
 
struct  arm_rfft_instance_f32
 Instance structure for the floating-point RFFT/RIFFT function.  More...
 
struct  arm_rfft_fast_instance_f32
 Instance structure for the floating-point RFFT/RIFFT function.  More...
 
struct  arm_dct4_instance_f32
 Instance structure for the floating-point DCT4/IDCT4 function.  More...
 
struct  arm_dct4_instance_q31
 Instance structure for the Q31 DCT4/IDCT4 function.  More...
 
struct  arm_dct4_instance_q15
 Instance structure for the Q15 DCT4/IDCT4 function.  More...
 
struct  arm_fir_decimate_instance_q15
 Instance structure for the Q15 FIR decimator.  More...
 
struct  arm_fir_decimate_instance_q31
 Instance structure for the Q31 FIR decimator.  More...
 
struct  arm_fir_decimate_instance_f32
 Instance structure for the floating-point FIR decimator.  More...
 
struct  arm_fir_interpolate_instance_q15
 Instance structure for the Q15 FIR interpolator.  More...
 
struct  arm_fir_interpolate_instance_q31
 Instance structure for the Q31 FIR interpolator.  More...
 
struct  arm_fir_interpolate_instance_f32
 Instance structure for the floating-point FIR interpolator.  More...
 
struct  arm_biquad_cas_df1_32x64_ins_q31
 Instance structure for the high precision Q31 Biquad cascade filter.  More...
 
struct  arm_biquad_cascade_df2T_instance_f32
 Instance structure for the floating-point transposed direct form II Biquad cascade filter.  More...
 
struct  arm_fir_lattice_instance_q15
 Instance structure for the Q15 FIR lattice filter.  More...
 
struct  arm_fir_lattice_instance_q31
 Instance structure for the Q31 FIR lattice filter.  More...
 
struct  arm_fir_lattice_instance_f32
 Instance structure for the floating-point FIR lattice filter.  More...
 
struct  arm_iir_lattice_instance_q15
 Instance structure for the Q15 IIR lattice filter.  More...
 
struct  arm_iir_lattice_instance_q31
 Instance structure for the Q31 IIR lattice filter.  More...
 
struct  arm_iir_lattice_instance_f32
 Instance structure for the floating-point IIR lattice filter.  More...
 
struct  arm_lms_instance_f32
 Instance structure for the floating-point LMS filter.  More...
 
struct  arm_lms_instance_q15
 Instance structure for the Q15 LMS filter.  More...
 
struct  arm_lms_instance_q31
 Instance structure for the Q31 LMS filter.  More...
 
struct  arm_lms_norm_instance_f32
 Instance structure for the floating-point normalized LMS filter.  More...
 
struct  arm_lms_norm_instance_q31
 Instance structure for the Q31 normalized LMS filter.  More...
 
struct  arm_lms_norm_instance_q15
 Instance structure for the Q15 normalized LMS filter.  More...
 
struct  arm_fir_sparse_instance_f32
 Instance structure for the floating-point sparse FIR filter.  More...
 
struct  arm_fir_sparse_instance_q31
 Instance structure for the Q31 sparse FIR filter.  More...
 
struct  arm_fir_sparse_instance_q15
 Instance structure for the Q15 sparse FIR filter.  More...
 
struct  arm_fir_sparse_instance_q7
 Instance structure for the Q7 sparse FIR filter.  More...
 
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\nMacros
#define __CMSIS_GENERIC
 
#define DELTA_Q31
 Macros required for reciprocal calculation in Normalized LMS.  More...
 
#define DELTA_Q15
 
#define INDEX_MASK
 
#define PI
 
#define TABLE_SIZE
 Macros required for SINE and COSINE Fast math approximations.  More...
 
#define TABLE_SPACING_Q31
 
#define TABLE_SPACING_Q15
 
#define INPUT_SPACING
 Macros required for SINE and COSINE Controller functions.  More...
 
#define ALIGN4
 Macro for Unaligned Support.  More...
 
#define __SIMD32(addr)
 definition to read/write two 16 bit values.  More...
 
#define __SIMD32_CONST(addr)
 
#define _SIMD32_OFFSET(addr)
 
#define __SIMD64(addr)
 
#define __PACKq7(v0, v1, v2, v3)
 definition to pack four 8 bit values.  More...
 
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typedef int8_t q7_t
 8-bit fractional data type in 1.7 format.  More...
 
typedef int16_t q15_t
 16-bit fractional data type in 1.15 format.  More...
 
typedef int32_t q31_t
 32-bit fractional data type in 1.31 format.  More...
 
typedef int64_t q63_t
 64-bit fractional data type in 1.63 format.  More...
 
typedef float float32_t
 32-bit floating-point type definition.  More...
 
typedef double float64_t
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enum  arm_status 
 Error status returned by some functions in the library.  More...
 
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\nFunctions
static __INLINE q31_t clip_q63_to_q31 (q63_t x)
 Clips Q63 to Q31 values.  More...
 
static __INLINE q15_t clip_q63_to_q15 (q63_t x)
 Clips Q63 to Q15 values.  More...
 
static __INLINE q7_t clip_q31_to_q7 (q31_t x)
 Clips Q31 to Q7 values.  More...
 
static __INLINE q15_t clip_q31_to_q15 (q31_t x)
 Clips Q31 to Q15 values.  More...
 
static __INLINE q63_t mult32x64 (q63_t x, q31_t y)
 Multiplies 32 X 64 and returns 32 bit result in 2.30 format.  More...
 
static __INLINE uint32_t arm_recip_q31 (q31_t in, q31_t *dst, q31_t *pRecipTable)
 Function to Calculates 1/in (reciprocal) value of Q31 Data type.  More...
 
static __INLINE uint32_t arm_recip_q15 (q15_t in, q15_t *dst, q15_t *pRecipTable)
 Function to Calculates 1/in (reciprocal) value of Q15 Data type.  More...
 
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  More...
 
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  More...
 
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  More...
 
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  More...
 
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  More...
 
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  More...
 
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  More...
 
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  More...
 
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  More...
 
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  More...
 
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  More...
 
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  More...
 
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  More...
 
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  More...
 
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  More...
 
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  More...
 
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication.  More...
 
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  More...
 
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  More...
 
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  More...
 
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  More...
 
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  More...
 
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  More...
 
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  More...
 
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  More...
 
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  More...
 
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  More...
 
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  More...
 
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  More...
 
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  More...
 
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  More...
 
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  More...
 
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  More...
 
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  More...
 
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  More...
 
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  More...
 
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  More...
 
arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Radix-2 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-4 CFFT/CIFFT.  More...
 
void arm_cfft_f32 (const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Processing function for the floating-point complex FFT.  More...
 
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  More...
 
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  More...
 
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  More...
 
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  More...
 
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  More...
 
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  More...
 
arm_status arm_rfft_fast_init_f32 (arm_rfft_fast_instance_f32 *S, uint16_t fftLen)
 Initialization function for the floating-point real FFT.  More...
 
void arm_rfft_fast_f32 (arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, uint8_t ifftFlag)
 Processing function for the floating-point real FFT.  More...
 
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  More...
 
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  More...
 
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  More...
 
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  More...
 
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  More...
 
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  More...
 
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  More...
 
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  More...
 
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  More...
 
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  More...
 
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  More...
 
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  More...
 
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  More...
 
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  More...
 
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  More...
 
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  More...
 
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  More...
 
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  More...
 
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  More...
 
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  More...
 
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  More...
 
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  More...
 
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  More...
 
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  More...
 
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  More...
 
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  More...
 
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  More...
 
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  More...
 
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  More...
 
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  More...
 
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  More...
 
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  More...
 
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  More...
 
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  More...
 
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  More...
 
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  More...
 
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  More...
 
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  More...
 
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  More...
 
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  More...
 
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  More...
 
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  More...
 
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  More...
 
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  More...
 
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  More...
 
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  More...
 
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  More...
 
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  More...
 
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  More...
 
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  More...
 
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  More...
 
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  More...
 
arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  More...
 
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  More...
 
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  More...
 
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  More...
 
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  More...
 
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  More...
 
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  More...
 
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  More...
 
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  More...
 
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  More...
 
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  More...
 
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  More...
 
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  More...
 
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  More...
 
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
 
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  More...
 
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  More...
 
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  More...
 
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  More...
 
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  More...
 
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  More...
 
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  More...
 
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  More...
 
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  More...
 
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  More...
 
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  More...
 
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  More...
 
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  More...
 
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  More...
 
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  More...
 
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  More...
 
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  More...
 
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  More...
 
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  More...
 
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  More...
 
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  More...
 
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  More...
 
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  More...
 
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  More...
 
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  More...
 
void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  More...
 
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  More...
 
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  More...
 
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  More...
 
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  More...
 
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  More...
 
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  More...
 
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  More...
 
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  More...
 
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  More...
 
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  More...
 
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  More...
 
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  More...
 
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCcosVal)
 Floating-point sin_cos function.  More...
 
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  More...
 
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  More...
 
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  More...
 
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  More...
 
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  More...
 
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  More...
 
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  More...
 
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
 Process function for the floating-point PID Control.  More...
 
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
 Process function for the Q31 PID Control.  More...
 
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
 Process function for the Q15 PID Control.  More...
 
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst)
 Floating-point matrix inverse.  More...
 
static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
 Floating-point Clarke transform.  More...
 
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
 Clarke transform for Q31 version.  More...
 
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  More...
 
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
 Floating-point Inverse Clarke transform.  More...
 
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
 Inverse Clarke transform for Q31 version.  More...
 
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  More...
 
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
 Floating-point Park transform.  More...
 
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
 Park transform for Q31 version.  More...
 
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  More...
 
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
 Floating-point Inverse Park transform.  More...
 
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
 Inverse Park transform for Q31 version.  More...
 
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  More...
 
static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
 Process function for the floating-point Linear Interpolation Function.  More...
 
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q31 Linear Interpolation Function.  More...
 
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q15 Linear Interpolation Function.  More...
 
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q7 Linear Interpolation Function.  More...
 
float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  More...
 
q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  More...
 
q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  More...
 
float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  More...
 
q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  More...
 
q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  More...
 
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
 Floating-point square root function.  More...
 
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  More...
 
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  More...
 
static __INLINE void arm_circularWrite_f32 (int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize)
 floating-point Circular write function.  More...
 
static __INLINE void arm_circularRead_f32 (int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 floating-point Circular Read function.  More...
 
static __INLINE void arm_circularWrite_q15 (q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize)
 Q15 Circular write function.  More...
 
static __INLINE void arm_circularRead_q15 (q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 Q15 Circular Read function.  More...
 
static __INLINE void arm_circularWrite_q7 (q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize)
 Q7 Circular write function.  More...
 
static __INLINE void arm_circularRead_q7 (q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
 Q7 Circular Read function.  More...
 
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  More...
 
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  More...
 
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  More...
 
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  More...
 
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  More...
 
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  More...
 
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Mean value of a Q31 vector.  More...
 
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  More...
 
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  More...
 
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  More...
 
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  More...
 
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  More...
 
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  More...
 
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  More...
 
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  More...
 
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  More...
 
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  More...
 
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  More...
 
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  More...
 
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  More...
 
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  More...
 
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  More...
 
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  More...
 
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  More...
 
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  More...
 
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  More...
 
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index)
 Minimum value of a Q7 vector.  More...
 
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  More...
 
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  More...
 
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  More...
 
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  More...
 
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  More...
 
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  More...
 
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  More...
 
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  More...
 
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  More...
 
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  More...
 
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  More...
 
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  More...
 
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  More...
 
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  More...
 
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  More...
 
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  More...
 
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  More...
 
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  More...
 
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
 Floating-point bilinear interpolation.  More...
 
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
 Q31 bilinear interpolation.  More...
 
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
 Q15 bilinear interpolation.  More...
 
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)
 Q7 bilinear interpolation.  More...
 
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Macro Definition Documentation
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#define __CMSIS_GENERIC
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#define __PACKq7( v0, 
 v1, 
 v2, 
 v3 
)
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Referenced by arm_conv_opt_q7(), arm_conv_partial_opt_q7(), arm_fill_q7(), arm_fir_sparse_q7(), arm_mult_q7(), arm_offset_q7(), arm_q31_to_q7(), arm_scale_q7(), and arm_shift_q7().
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#define __SIMD32( addr)
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Referenced by arm_add_q15(), arm_add_q7(), arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_q15(), arm_cmplx_conj_q15(), arm_cmplx_mag_q15(), arm_cmplx_mag_squared_q15(), arm_cmplx_mult_real_q15(), arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_q15(), arm_copy_q15(), arm_copy_q7(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_dot_prod_q15(), arm_dot_prod_q7(), arm_fill_q15(), arm_fill_q7(), arm_fir_decimate_fast_q15(), arm_fir_decimate_q15(), arm_fir_fast_q15(), arm_fir_interpolate_q15(), arm_fir_lattice_q15(), arm_fir_q15(), arm_fir_sparse_q15(), arm_fir_sparse_q7(), arm_iir_lattice_q15(), arm_lms_norm_q15(), arm_lms_q15(), arm_mat_add_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_sub_q15(), arm_mat_trans_q15(), arm_mean_q15(), arm_mean_q7(), arm_mult_q15(), arm_mult_q7(), arm_negate_q7(), arm_offset_q15(), arm_offset_q7(), arm_power_q15(), arm_power_q7(), arm_q15_to_q31(), arm_q15_to_q7(), arm_q31_to_q15(), arm_q31_to_q7(), arm_q7_to_q15(), arm_q7_to_q31(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_rms_q15(), arm_scale_q15(), arm_scale_q7(), arm_shift_q15(), arm_shift_q7(), arm_split_rfft_q15(), arm_split_rifft_q15(), arm_std_q15(), arm_sub_q15(), arm_sub_q7(), and arm_var_q15().
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#define __SIMD32_CONST( addr)
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Referenced by arm_abs_q15(), and arm_pid_q15().
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#define __SIMD64( addr)
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Referenced by arm_radix4_butterfly_inverse_q31(), and arm_radix4_butterfly_q31().
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#define _SIMD32_OFFSET( addr)
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Referenced by arm_conv_fast_opt_q15(), arm_conv_fast_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_fast_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_conv_partial_q15(), arm_conv_q15(), arm_correlate_fast_opt_q15(), arm_correlate_fast_q15(), arm_correlate_opt_q15(), arm_correlate_opt_q7(), arm_correlate_q15(), arm_fir_fast_q15(), arm_fir_q15(), arm_mat_scale_q15(), arm_negate_q15(), arm_radix2_butterfly_inverse_q15(), arm_radix2_butterfly_q15(), arm_radix4_butterfly_inverse_q15(), and arm_radix4_butterfly_q15().
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#define ALIGN4
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#define DELTA_Q15
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Referenced by arm_lms_norm_q15().
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#define DELTA_Q31
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Referenced by arm_lms_norm_q31().
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#define INDEX_MASK
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Referenced by arm_recip_q15(), and arm_recip_q31().
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#define INPUT_SPACING
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Referenced by arm_sin_cos_q31().
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#define PI
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#define TABLE_SIZE
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Referenced by arm_cos_f32(), and arm_sin_f32().
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#define TABLE_SPACING_Q15
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Referenced by arm_cos_q15(), and arm_sin_q15().
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#define TABLE_SPACING_Q31
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Referenced by arm_cos_q31(), and arm_sin_q31().
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Typedef Documentation
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typedef float float32_t
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typedef double float64_t
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typedef int16_t q15_t
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typedef int32_t q31_t
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typedef int64_t q63_t
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typedef int8_t q7_t
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Enumeration Type Documentation
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enum arm_status
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Enumerator
ARM_MATH_SUCCESS \n
No error 
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ARM_MATH_ARGUMENT_ERROR \n
One or more arguments are incorrect 
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ARM_MATH_LENGTH_ERROR \n
Length of data buffer is incorrect 
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ARM_MATH_SIZE_MISMATCH \n
Size of matrices is not compatible with the operation. 
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ARM_MATH_NANINF \n
Not-a-number (NaN) or infinity is generated 
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ARM_MATH_SINGULAR \n
Generated by matrix inversion if the input matrix is singular and cannot be inverted. 
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ARM_MATH_TEST_FAILURE \n
Test Failed 
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Function Documentation
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static __INLINE void arm_circularRead_f32 (int32_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
int32_t * dst, 
int32_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)
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References blockSize.
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_q31().
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static __INLINE void arm_circularRead_q15 (q15_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
q15_t * dst, 
q15_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)
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References blockSize.
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Referenced by arm_fir_sparse_q15().
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static __INLINE void arm_circularRead_q7 (q7_t * circBuffer, 
int32_t L, 
int32_t * readOffset, 
int32_t bufferInc, 
q7_t * dst, 
q7_t * dst_base, 
int32_t dst_length, 
int32_t dstInc, 
uint32_t blockSize 
)
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References blockSize.
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Referenced by arm_fir_sparse_q7().
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static __INLINE void arm_circularWrite_f32 (int32_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const int32_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)
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end of SQRT group 
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References blockSize.
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_q31().
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static __INLINE void arm_circularWrite_q15 (q15_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const q15_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)
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References blockSize.
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Referenced by arm_fir_sparse_q15().
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static __INLINE void arm_circularWrite_q7 (q7_t * circBuffer, 
int32_t L, 
uint16_t * writeOffset, 
int32_t bufferInc, 
const q7_t * src, 
int32_t srcInc, 
uint32_t blockSize 
)
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References blockSize.
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Referenced by arm_fir_sparse_q7().
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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst, 
q15_t * pState 
)
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Parameters
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[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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static __INLINE uint32_t arm_recip_q15 (q15_t in, 
q15_t * dst, 
q15_t * pRecipTable 
)
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References INDEX_MASK.
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Referenced by arm_lms_norm_q15().
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static __INLINE uint32_t arm_recip_q31 (q31_t in, 
q31_t * dst, 
q31_t * pRecipTable 
)
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References clip_q63_to_q31(), and INDEX_MASK.
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static __INLINE q15_t clip_q31_to_q15 (q31_t x)
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static __INLINE q7_t clip_q31_to_q7 (q31_t x)
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static __INLINE q15_t clip_q63_to_q15 (q63_t x)
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static __INLINE q31_t clip_q63_to_q31 (q63_t x)
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Referenced by arm_add_q31(), arm_cmplx_mult_real_q31(), arm_float_to_q31(), arm_iir_lattice_q31(), arm_lms_norm_q31(), arm_lms_q31(), arm_mult_q31(), arm_offset_q31(), arm_pid_init_q31(), arm_recip_q31(), arm_shift_q31(), and arm_sub_q31().
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static __INLINE q63_t mult32x64 (q63_t x, 
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Referenced by arm_biquad_cas_df1_32x64_q31().
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  • Include
  • arm_math.h
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__matrix__example__f32_8c.html",
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arm_matrix_example_f32.c File Reference
  
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#define SNR_THRESHOLD
 
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int32_t main (void)
 
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const float32_t B_f32 [4]
 
const float32_t A_f32 [16]
 
float32_t AT_f32 [16]
 
float32_t ATMA_f32 [16]
 
float32_t ATMAI_f32 [16]
 
float32_t X_f32 [4]
 
const float32_t xRef_f32 [4]
 
float32_t snr
 
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Macro Definition Documentation
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#define SNR_THRESHOLD
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Referenced by main().
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Function Documentation
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int32_t main (void )
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References A_f32, arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_trans_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_snr_f32(), AT_f32, ATMA_f32, ATMAI_f32, B_f32, snr, SNR_THRESHOLD, status, X_f32, and xRef_f32.
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Variable Documentation
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const float32_t A_f32[16]
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arm_matrix_example_f32.c.
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float32_t AT_f32[16]
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arm_matrix_example_f32.c.
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float32_t ATMA_f32[16]
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arm_matrix_example_f32.c.
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float32_t ATMAI_f32[16]
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arm_matrix_example_f32.c.
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arm_matrix_example_f32.c.
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float32_t X_f32[4]
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arm_matrix_example_f32.c.
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arm_matrix_example_f32.c.
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void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  More...
 
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void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  More...
 
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void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  More...
 
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void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  More...
 
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void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  More...
 
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void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  More...
 
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void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  More...
 
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void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  More...
 
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void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  More...
 
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void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  More...
 
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void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Minimum value of a Q7 vector.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_mult_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mult_f32.c File Reference
  
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void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mult__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mult_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mult_q15.c File Reference
  
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void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mult__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mult_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_mult_q31.c File Reference
  
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void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__mult__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_mult_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_mult_q7.c File Reference
  
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void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__negate__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_negate_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_negate_f32.c File Reference
  
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void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__negate__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_negate_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_negate_q15.c File Reference
  
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void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__negate__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_negate_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_negate_q31.c File Reference
  
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void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  More...
 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__negate__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_negate_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_negate_q7.c File Reference
  
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void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__offset__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_offset_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_offset_f32.c File Reference
  
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void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__offset__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_offset_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_offset_q15.c File Reference
  
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void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__offset__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_offset_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_offset_q31.c File Reference
  
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void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__offset__q7_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_offset_q7.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_offset_q7.c File Reference
  
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void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__init__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_init_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_pid_init_f32.c File Reference
  
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void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__init__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_pid_init_q15.c File Reference
  
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void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__init__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_pid_init_q31.c File Reference
  
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void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__reset__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_reset_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_pid_reset_f32.c File Reference
  
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void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__reset__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_reset_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_pid_reset_q15.c File Reference
  
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void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  More...
 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__pid__reset__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_reset_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  More...
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__power__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_power_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_power_f32.c File Reference
  
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void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  More...
 
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arm_power_q15.c File Reference
  
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void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  More...
 
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arm_power_q31.c File Reference
  
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void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  More...
 
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arm_power_q7.c File Reference
  
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void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  More...
 
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arm_q15_to_float.c File Reference
  
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void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  More...
 
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arm_q15_to_q31.c File Reference
  
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void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  More...
 
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arm_q15_to_q7.c File Reference
  
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void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  More...
 
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arm_q31_to_float.c File Reference
  
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void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  More...
 
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arm_q31_to_q15.c File Reference
  
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void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  More...
 
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arm_q31_to_q7.c File Reference
  
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void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  More...
 
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void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  More...
 
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arm_q7_to_q15.c File Reference
  
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void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  More...
 
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void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  More...
 
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arm_rfft_f32.c File Reference
  
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void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
 
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_split_rfft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
 Core Real FFT process.  More...
 
void arm_split_rifft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
 Core Real IFFT process.  More...
 
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  More...
 
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void arm_bitreversal_f32 (float32_t * pSrc, 
uint16_t fftSize, 
uint16_t bitRevFactor, 
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Referenced by arm_cfft_radix2_f32(), arm_cfft_radix4_f32(), and arm_rfft_f32().
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void arm_radix4_butterfly_inverse_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier, 
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Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().
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void arm_split_rifft_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pATable, 
float32_t * pBTable, 
float32_t * pDst, 
uint32_t modifier 
)
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Parameters
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[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Referenced by arm_rfft_f32().
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arm_rfft_fast_f32.c File Reference
  
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void stage_rfft_f32 (arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut)
 
void merge_rfft_f32 (arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut)
 
void arm_rfft_fast_f32 (arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, uint8_t ifftFlag)
 Processing function for the floating-point real FFT.  More...
 
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void merge_rfft_f32 (arm_rfft_fast_instance_f32 * S, 
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References arm_rfft_fast_instance_f32::pTwiddleRFFT, and arm_rfft_fast_instance_f32::Sint.
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void stage_rfft_f32 (arm_rfft_fast_instance_f32 * S, 
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References arm_rfft_fast_instance_f32::pTwiddleRFFT, and arm_rfft_fast_instance_f32::Sint.
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_rfft_fast_init_f32.c File Reference
  
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arm_status arm_rfft_fast_init_f32 (arm_rfft_fast_instance_f32 *S, uint16_t fftLen)
 Initialization function for the floating-point real FFT.  More...
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_init_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_rfft_init_f32.c File Reference
  
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arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  More...
 
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static const float32_t realCoefA [8192]
 
static const float32_t realCoefB [8192]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__rfft__init__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_init_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_rfft_init_q15.c File Reference
  
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arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  More...
 
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static const q15_t ALIGN4 realCoefAQ15 [8192]
 
static const q15_t ALIGN4 realCoefBQ15 [8192]
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__rfft__init__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_init_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_rfft_init_q31.c File Reference
  
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arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  More...
 
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static const q31_t realCoefAQ31 [8192]
 
static const q31_t realCoefBQ31 [8192]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__rfft__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_rfft_q15.c File Reference
  
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void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CFFT butterfly process.  More...
 
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
 Core function for the Q15 CIFFT butterfly process.  More...
 
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_split_rfft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
 Core Real FFT process.  More...
 
void arm_split_rifft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
 Core Real IFFT process.  More...
 
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_q15 (q15_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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Referenced by arm_cfft_radix2_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
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void arm_radix4_butterfly_inverse_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)
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Parameters
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[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD32, and _SIMD32_OFFSET.
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Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().
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void arm_radix4_butterfly_q15 (q15_t * pSrc16, 
uint32_t fftLen, 
q15_t * pCoef16, 
uint32_t twidCoefModifier 
)
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end of ComplexFFT group 
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Parameters
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[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD32, and _SIMD32_OFFSET.
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Referenced by arm_cfft_radix4_q15(), and arm_rfft_q15().
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void arm_split_rfft_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pATable, 
q15_t * pBTable, 
q15_t * pDst, 
uint32_t modifier 
)
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end of RealFFT group 
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
*pSrcpoints to the input buffer. 
fftLenlength of FFT. 
*pATablepoints to the A twiddle Coef buffer. 
*pBTablepoints to the B twiddle Coef buffer. 
*pDstpoints to the output buffer. 
modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. The function implements a Real FFT 
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References __SIMD32.
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Referenced by arm_rfft_q15().
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void arm_split_rifft_q15 (q15_t * pSrc, 
uint32_t fftLen, 
q15_t * pATable, 
q15_t * pBTable, 
q15_t * pDst, 
uint32_t modifier 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. The function implements a Real IFFT 
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References __SIMD32.
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Referenced by arm_rfft_q15().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__rfft__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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arm_rfft_q31.c File Reference
  
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void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CIFFT butterfly process.  More...
 
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
 Core function for the Q31 CFFT butterfly process.  More...
 
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
 
void arm_split_rfft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
 Core Real FFT process.  More...
 
void arm_split_rifft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
 Core Real IFFT process.  More...
 
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  More...
 
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Function Documentation
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void arm_bitreversal_q31 (q31_t * pSrc, 
uint32_t fftLen, 
uint16_t bitRevFactor, 
uint16_t * pBitRevTab 
)
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Referenced by arm_cfft_radix2_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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void arm_radix4_butterfly_inverse_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)
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Parameters
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[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD64.
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Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().
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void arm_radix4_butterfly_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pCoef, 
uint32_t twidCoefModifier 
)
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end of ComplexFFT group 
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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References __SIMD64.
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Referenced by arm_cfft_radix4_q31(), and arm_rfft_q31().
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void arm_split_rfft_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pATable, 
q31_t * pBTable, 
q31_t * pDst, 
uint32_t modifier 
)
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end of RealFFT group 
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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Referenced by arm_rfft_q31().
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void arm_split_rifft_q31 (q31_t * pSrc, 
uint32_t fftLen, 
q31_t * pATable, 
q31_t * pBTable, 
q31_t * pDst, 
uint32_t modifier 
)
\n
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Parameters
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[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Returns
none. 
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Referenced by arm_rfft_q31().
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__rms__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rms_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  More...
 
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void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  More...
 
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arm_rms_q31.c File Reference
  
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void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  More...
 
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arm_scale_f32.c File Reference
  
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void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  More...
 
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arm_scale_q15.c File Reference
  
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void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  More...
 
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arm_scale_q31.c File Reference
  
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void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  More...
 
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arm_scale_q7.c File Reference
  
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void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  More...
 
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arm_shift_q15.c File Reference
  
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void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  More...
 
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void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  More...
 
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void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  More...
 
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arm_signal_converge_data.c File Reference
  
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float32_t testInput_f32 [1536]
 
float32_t lmsNormCoeff_f32 [32]
 
const float32_t FIRCoeff_f32 [32]
 
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Variable Documentation
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const float32_t FIRCoeff_f32[32]
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arm_signal_converge_example_f32.c.
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float32_t lmsNormCoeff_f32[32]
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arm_signal_converge_example_f32.c.
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float32_t testInput_f32[1536]
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arm_signal_converge_example_f32.c File Reference
  
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#define TEST_LENGTH_SAMPLES
 
#define NUMTAPS
 
#define BLOCKSIZE
 
#define DELTA_ERROR
 
#define DELTA_COEFF
 
#define MU
 
#define NUMFRAMES
 
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arm_status test_signal_converge_example (void)
 
arm_status test_signal_converge (float32_t *err_signal, uint32_t blockSize)
 
void getinput (float32_t *input, uint32_t fr_cnt, uint32_t blockSize)
 
int32_t main (void)
 
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float32_t firStateF32 [NUMTAPS+BLOCKSIZE]
 
arm_fir_instance_f32 LPF_instance
 
float32_t lmsStateF32 [NUMTAPS+BLOCKSIZE]
 
float32_t errOutput [TEST_LENGTH_SAMPLES]
 
arm_lms_norm_instance_f32 lmsNorm_instance
 
float32_t testInput_f32 [TEST_LENGTH_SAMPLES]
 
float32_t lmsNormCoeff_f32 [32]
 
const float32_t FIRCoeff_f32 [32]
 
float32_t wire1 [BLOCKSIZE]
 
float32_t wire2 [BLOCKSIZE]
 
float32_t wire3 [BLOCKSIZE]
 
float32_t err_signal [BLOCKSIZE]
 
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Macro Definition Documentation
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#define BLOCKSIZE
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#define DELTA_COEFF
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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#define TEST_LENGTH_SAMPLES
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Function Documentation
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void getinput (float32_t * input, 
uint32_t fr_cnt, 
uint32_t blockSize 
)
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arm_signal_converge_example_f32.c.
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int32_t main (void )
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References arm_abs_f32(), arm_copy_f32(), arm_fir_f32(), arm_fir_init_f32(), arm_lms_norm_f32(), arm_lms_norm_init_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_min_f32(), arm_scale_f32(), arm_sub_f32(), BLOCKSIZE, DELTA_COEFF, DELTA_ERROR, err_signal, FIRCoeff_f32, firStateF32, lmsNormCoeff_f32, lmsStateF32, MU, NUMFRAMES, NUMTAPS, status, testInput_f32, wire1, wire2, and wire3.
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arm_status test_signal_converge (float32_t * err_signal, 
uint32_t blockSize 
)
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arm_signal_converge_example_f32.c.
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arm_status test_signal_converge_example (void )
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arm_signal_converge_example_f32.c.
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Variable Documentation
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float32_t err_signal[BLOCKSIZE]
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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const float32_t FIRCoeff_f32[32]
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float32_t firStateF32[NUMTAPS+BLOCKSIZE]
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arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.
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arm_lms_norm_instance_f32 lmsNorm_instance
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arm_signal_converge_example_f32.c.
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arm_signal_converge_example_f32.c.
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arm_fir_instance_f32 LPF_instance
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arm_signal_converge_example_f32.c.
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#define MAX_BLOCKSIZE
 
#define DELTA
 
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int32_t main (void)
 
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const float32_t testInput_f32 [MAX_BLOCKSIZE]
 
const float32_t testRefOutput_f32
 
uint32_t blockSize
 
float32_t testOutput
 
float32_t cosOutput
 
float32_t sinOutput
 
float32_t cosSquareOutput
 
float32_t sinSquareOutput
 
arm_status status
 
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Macro Definition Documentation
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#define DELTA
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Referenced by main().
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#define MAX_BLOCKSIZE
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Function Documentation
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int32_t main (void )
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References arm_add_f32(), arm_cos_f32(), ARM_MATH_TEST_FAILURE, arm_mult_f32(), arm_sin_f32(), blockSize, cosOutput, cosSquareOutput, DELTA, sinOutput, sinSquareOutput, status, testInput_f32, testOutput, and testRefOutput_f32.
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Variable Documentation
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uint32_t blockSize
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float32_t cosOutput
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Examples: 
arm_sin_cos_example_f32.c.
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Referenced by main().
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float32_t cosSquareOutput
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Examples: 
arm_sin_cos_example_f32.c.
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Referenced by main().
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float32_t sinOutput
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Examples: 
arm_sin_cos_example_f32.c.
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float32_t sinSquareOutput
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Examples: 
arm_sin_cos_example_f32.c.
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Referenced by main().
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arm_status status
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const float32_t testInput_f32[MAX_BLOCKSIZE]
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float32_t testOutput
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const float32_t testRefOutput_f32
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__sin__cos__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_cos_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_sin_cos_f32.c File Reference
  
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void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
 Floating-point sin_cos function.  More...
 
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static const float32_t cosTable [360]
 
static const float32_t sinTable [360]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__sin__cos__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_cos_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_sin_cos_q31.c File Reference
  
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void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  More...
 
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static const int32_t sinTableQ31 [360]
 
static const int32_t cosTableQ31 [360]
 
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  },
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_sin_f32.c File Reference
  
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float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  More...
 
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static const float32_t sinTable [259]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__sin__q15_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_q15.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_sin_q15.c File Reference
  
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q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  More...
 
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static const q15_t sinTableQ15 [259]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__sin__q31_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_q31.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_sin_q31.c File Reference
  
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q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  More...
 
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static const q31_t sinTableQ31 [259]
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__sqrt__q15_8c.html",
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arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  More...
 
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arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  More...
 
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void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  More...
 
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void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  More...
 
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void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  More...
 
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void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  More...
 
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void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  More...
 
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void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  More...
 
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void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  More...
 
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void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  More...
 
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void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  More...
 
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arm_var_q31.c File Reference
  
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\n\n\n\n\n\n
\nFunctions
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  More...
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm__variance__example__f32_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_variance_example_f32.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_variance_example_f32.c File Reference
  
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\n\n\n\n\n\n\n
\nMacros
#define MAX_BLOCKSIZE
 
#define DELTA
 
\n\n\n\n
\nFunctions
int32_t main (void)
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nVariables
float32_t wire1 [MAX_BLOCKSIZE]
 
float32_t wire2 [MAX_BLOCKSIZE]
 
float32_t wire3 [MAX_BLOCKSIZE]
 
float32_t testInput_f32 [32]
 
uint32_t blockSize
 
float32_t refVarianceOut
 
\n
Macro Definition Documentation
\n\n
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\n      \n        \n          \n        \n      
#define DELTA
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Referenced by main().
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#define MAX_BLOCKSIZE
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Function Documentation
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
int32_t main (void )
\n
\n\n
References arm_copy_f32(), arm_dot_prod_f32(), arm_fill_f32(), ARM_MATH_SUCCESS, ARM_MATH_TEST_FAILURE, arm_mult_f32(), arm_sub_f32(), blockSize, DELTA, mean, refVarianceOut, status, testInput_f32, wire1, wire2, and wire3.
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Variable Documentation
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uint32_t blockSize
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float32_t refVarianceOut
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Examples: 
arm_variance_example_f32.c.
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Referenced by main().
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float32_t testInput_f32[32]
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float32_t wire1[MAX_BLOCKSIZE]
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float32_t wire2[MAX_BLOCKSIZE]
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float32_t wire3[MAX_BLOCKSIZE]
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_class_marks_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_class_marks_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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arm_class_marks_example_f32.c
  
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
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*
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* $Date:         17. January 2013
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* $Revision:     V1.4.0
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*
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* Project:       CMSIS DSP Library
\n
* Title:         arm_class_marks_example_f32.c
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*
\n
* Description:   Example code to calculate Minimum, Maximum
\n
*                Mean, std and variance of marks obtained in a class
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
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*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#define USE_STATIC_INIT
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 /* ----------------------------------------------------------------------
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** Global defines
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** ------------------------------------------------------------------- */
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#define TEST_LENGTH_SAMPLES   (20*4)
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/* ----------------------------------------------------------------------
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** List of Marks scored by 20 students for 4 subjects
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** ------------------------------------------------------------------- */
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const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =
\n
{
\n
  42.000000,  37.000000,  81.000000,  28.000000,
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  83.000000,  72.000000,  36.000000,  38.000000,
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  32.000000,  51.000000,  63.000000,  64.000000,
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  97.000000,  82.000000,  95.000000,  90.000000,
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  66.000000,  51.000000,  54.000000,  42.000000,
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  67.000000,  56.000000,  45.000000,  57.000000,
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  67.000000,  69.000000,  35.000000,  52.000000,
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  29.000000,  81.000000,  58.000000,  47.000000,
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  38.000000,  76.000000, 100.000000,  29.000000,
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  33.000000,  47.000000,  29.000000,  50.000000,
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  34.000000,  41.000000,  61.000000,  46.000000,
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  52.000000,  50.000000,  48.000000,  36.000000,
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  47.000000,  55.000000,  44.000000,  40.000000,
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 100.000000,  94.000000,  84.000000,  37.000000,
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  32.000000,  71.000000,  47.000000,  77.000000,
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  31.000000,  50.000000,  49.000000,  35.000000,
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  63.000000,  67.000000,  40.000000,  31.000000,
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  29.000000,  68.000000,  61.000000,  38.000000,
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  31.000000,  28.000000,  28.000000,  76.000000,
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  55.000000,  33.000000,  29.000000,  39.000000
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};
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/* ----------------------------------------------------------------------
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* Number of subjects X 1
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* ------------------------------------------------------------------- */
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const float32_t testUnity_f32[4] =
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{
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  1.000,  1.000,   1.000,  1.000
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};
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/* ----------------------------------------------------------------------
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** f32 Output buffer
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** ------------------------------------------------------------------- */
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static float32_t testOutput[TEST_LENGTH_SAMPLES];
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/* ------------------------------------------------------------------
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* Global defines
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*------------------------------------------------------------------- */
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#define   NUMSTUDENTS  20
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#define     NUMSUBJECTS  4
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/* ------------------------------------------------------------------
\n
* Global variables
\n
*------------------------------------------------------------------- */
\n
\n
 uint32_t    numStudents = 20;
\n
 uint32_t    numSubjects = 4;
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float32_t    max_marks, min_marks, mean, std, var;
\n
 uint32_t    student_num;
\n
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/* ----------------------------------------------------------------------------------
\n
* Main f32 test function.  It returns maximum marks secured and student number
\n
* ------------------------------------------------------------------------------- */
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int32_t main()
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{
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#ifndef  USE_STATIC_INIT
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  arm_matrix_instance_f32 srcA;
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  arm_matrix_instance_f32 srcB;
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  arm_matrix_instance_f32 dstC;
\n
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  /* Input and output matrices initializations */
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  arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);
\n
  arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);
\n
  arm_mat_init_f32(&dstC, numStudents, 1, testOutput);
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#else
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  /* Static Initializations of Input and output matrix sizes and array */
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  arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32};
\n
  arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32};
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  arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput};
\n
\n
#endif
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  /* ----------------------------------------------------------------------
\n
  *Call the Matrix multiplication process function
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  * ------------------------------------------------------------------- */
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  arm_mat_mult_f32(&srcA, &srcB, &dstC);
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  /* ----------------------------------------------------------------------
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  ** Call the Max function to calculate max marks among numStudents
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  ** ------------------------------------------------------------------- */
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  arm_max_f32(testOutput, numStudents, &max_marks, &student_num);
\n
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  /* ----------------------------------------------------------------------
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  ** Call the Min function to calculate min marks among numStudents
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  ** ------------------------------------------------------------------- */
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  arm_min_f32(testOutput, numStudents, &min_marks, &student_num);
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  /* ----------------------------------------------------------------------
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  ** Call the Mean function to calculate mean
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  ** ------------------------------------------------------------------- */
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  arm_mean_f32(testOutput, numStudents, &mean);
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  /* ----------------------------------------------------------------------
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  ** Call the std function to calculate standard deviation
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  ** ------------------------------------------------------------------- */
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  arm_std_f32(testOutput, numStudents, &std);
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  /* ----------------------------------------------------------------------
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  ** Call the var function to calculate variance
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  ** ------------------------------------------------------------------- */
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  arm_var_f32(testOutput, numStudents, &var);
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  while(1);                             /* main function does not return */
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}
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_convolution_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_convolution_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_convolution_example_f32.c
  
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
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*
\n
* $Date:         17. January 2013
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* $Revision:     V1.4.0
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*
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* Project:       CMSIS DSP Library
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* Title:         arm_convolution_example_f32.c
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*
\n
* Description:   Example code demonstrating Convolution of two input signals using fft.
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
* -------------------------------------------------------------------- */
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\n
#include "arm_math.h"
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#include "math_helper.h"
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/* ----------------------------------------------------------------------
\n
* Defines each of the tests performed
\n
* ------------------------------------------------------------------- */
\n
#define MAX_BLOCKSIZE  128
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#define DELTA           (0.000001f)
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#define SNR_THRESHOLD   90
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/* ----------------------------------------------------------------------
\n
* Declare I/O buffers
\n
* ------------------------------------------------------------------- */
\n
float32_t Ak[MAX_BLOCKSIZE];    /* Input A */
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float32_t Bk[MAX_BLOCKSIZE];    /* Input B */
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float32_t AxB[MAX_BLOCKSIZE * 2];  /* Output */
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/* ----------------------------------------------------------------------
\n
* Test input data for Floating point Convolution example for 32-blockSize
\n
* Generated by the MATLAB randn() function
\n
* ------------------------------------------------------------------- */
\n
float32_t testInputA_f32[64] =
\n
{
\n
  -0.808920,   1.357369,   1.180861,  -0.504544,   1.762637,  -0.703285,
\n
   1.696966,   0.620571,  -0.151093,  -0.100235,  -0.872382,  -0.403579,
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  -0.860749,  -0.382648,  -1.052338,   0.128113,  -0.646269,   1.093377,
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  -2.209198,   0.471706,   0.408901,   1.266242,   0.598252,   1.176827,
\n
  -0.203421,   0.213596,  -0.851964,  -0.466958,   0.021841,  -0.698938,
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  -0.604107,   0.461778,  -0.318219,   0.942520,   0.577585,   0.417619,
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   0.614665,   0.563679,  -1.295073,  -0.764437,   0.952194,  -0.859222,
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  -0.618554,  -2.268542,  -1.210592,   1.655853,  -2.627219,  -0.994249,
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  -1.374704,   0.343799,   0.025619,   1.227481,  -0.708031,   0.069355,
\n
  -1.845228,  -1.570886,   1.010668,  -1.802084,   1.630088,   1.286090,
\n
  -0.161050,  -0.940794,   0.367961,   0.291907
\n
\n
};
\n
\n
float32_t testInputB_f32[64] =
\n
{
\n
   0.933724,   0.046881,   1.316470,   0.438345,   0.332682,   2.094885,
\n
   0.512081,   0.035546,   0.050894,  -2.320371,   0.168711,  -1.830493,
\n
  -0.444834,  -1.003242,  -0.531494,  -1.365600,  -0.155420,  -0.757692,
\n
  -0.431880,  -0.380021,   0.096243,  -0.695835,   0.558850,  -1.648962,
\n
   0.020369,  -0.363630,   0.887146,   0.845503,  -0.252864,  -0.330397,
\n
   1.269131,  -1.109295,  -1.027876,   0.135940,   0.116721,  -0.293399,
\n
  -1.349799,   0.166078,  -0.802201,   0.369367,  -0.964568,  -2.266011,
\n
   0.465178,   0.651222,  -0.325426,   0.320245,  -0.784178,  -0.579456,
\n
   0.093374,   0.604778,  -0.048225,   0.376297,  -0.394412,   0.578182,
\n
  -1.218141,  -1.387326,   0.692462,  -0.631297,   0.153137,  -0.638952,
\n
  0.635474,   -0.970468,   1.334057,  -0.111370
\n
};
\n
\n
const float testRefOutput_f32[126] =
\n
{
\n
   -0.818943,    1.229484,  -0.533664,    1.016604,   0.341875,  -1.963656,
\n
    5.171476,    3.478033,   7.616361,    6.648384,   0.479069,   1.792012,
\n
   -1.295591,   -7.447818,   0.315830,  -10.657445,  -2.483469,  -6.524236,
\n
   -7.380591,   -3.739005,  -8.388957,    0.184147,  -1.554888,   3.786508,
\n
   -1.684421,    5.400610,  -1.578126,    7.403361,   8.315999,   2.080267,
\n
   11.077776,    2.749673,   7.138962,    2.748762,   0.660363,   0.981552,
\n
    1.442275,    0.552721,  -2.576892,    4.703989,   0.989156,   8.759344,
\n
   -0.564825,   -3.994680,   0.954710,   -5.014144,   6.592329,   1.599488,
\n
  -13.979146,   -0.391891,  -4.453369,   -2.311242,  -2.948764,   1.761415,
\n
   -0.138322,   10.433007,  -2.309103,    4.297153,   8.535523,   3.209462,
\n
    8.695819,    5.569919,   2.514304,    5.582029,   2.060199,   0.642280,
\n
    7.024616,    1.686615,  -6.481756,    1.343084,  -3.526451,   1.099073,
\n
   -2.965764,   -0.173723,  -4.111484,    6.528384,  -6.965658,   1.726291,
\n
    1.535172,   11.023435,   2.338401,   -4.690188,   1.298210,   3.943885,
\n
    8.407885,    5.168365,   0.684131,    1.559181,   1.859998,   2.852417,
\n
    8.574070,   -6.369078,   6.023458,   11.837963,  -6.027632,   4.469678,
\n
   -6.799093,   -2.674048,   6.250367,   -6.809971,  -3.459360,   9.112410,
\n
   -2.711621,   -1.336678,   1.564249,   -1.564297,  -1.296760,   8.904013,
\n
   -3.230109,    6.878013,  -7.819823,    3.369909,  -1.657410,  -2.007358,
\n
   -4.112825,    1.370685,  -3.420525,   -6.276605,   3.244873,  -3.352638,
\n
    1.545372,    0.902211,   0.197489,   -1.408732,   0.523390,   0.348440
\n
};
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare Global variables
\n
* ------------------------------------------------------------------- */
\n
uint32_t srcALen = 64;   /* Length of Input A */
\n
uint32_t srcBLen = 64;   /* Length of Input B */
\n
uint32_t outLen;     /* Length of convolution output */
\n
float32_t snr;        /* output SNR */
\n
\n
int32_t main(void)
\n
{
\n
  arm_status status;     /* Status of the example */
\n
  arm_cfft_radix4_instance_f32 cfft_instance;  /* CFFT Structure instance */
\n
\n
  /* CFFT Structure instance pointer */
\n
  arm_cfft_radix4_instance_f32 *cfft_instance_ptr =
\n
      (arm_cfft_radix4_instance_f32*) &cfft_instance;
\n
\n
  /* output length of convolution */
\n
  outLen = srcALen + srcBLen - 1;
\n
\n
  /* Initialise the fft input buffers with all zeros */
\n
  arm_fill_f32(0.0,  Ak, MAX_BLOCKSIZE);
\n
  arm_fill_f32(0.0,  Bk, MAX_BLOCKSIZE);
\n
\n
  /* Copy the input values to the fft input buffers */
\n
  arm_copy_f32(testInputA_f32,  Ak, MAX_BLOCKSIZE/2);
\n
  arm_copy_f32(testInputB_f32,  Bk, MAX_BLOCKSIZE/2);
\n
\n
  /* Initialize the CFFT function to compute 64 point fft */
\n
  status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1);
\n
\n
  /* Transform input a[n] from time domain to frequency domain A[k] */
\n
  arm_cfft_radix4_f32(cfft_instance_ptr, Ak);
\n
  /* Transform input b[n] from time domain to frequency domain B[k] */
\n
  arm_cfft_radix4_f32(cfft_instance_ptr, Bk);
\n
\n
  /* Complex Multiplication of the two input buffers in frequency domain */
\n
  arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);
\n
\n
  /* Initialize the CIFFT function to compute 64 point ifft */
\n
  status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1);
\n
\n
  /* Transform the multiplication output from frequency domain to time domain,
\n
     that gives the convolved output  */
\n
  arm_cfft_radix4_f32(cfft_instance_ptr, AxB);
\n
\n
  /* SNR Calculation */
\n
  snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1);
\n
\n
  /* Compare the SNR with threshold to test whether the
\n
     computed output is matched with the reference output values. */
\n
  if( snr > SNR_THRESHOLD)
\n
  {
\n
    status = ARM_MATH_SUCCESS;
\n
  }
\n
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_dotproduct_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dotproduct_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
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\n
arm_dotproduct_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_dotproduct_example_f32.c
\n
*
\n
* Description:   Example code computing dot product of two vectors.
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
 * -------------------------------------------------------------------- */
\n
\n
#include <math.h>
\n
#include "arm_math.h"
\n
\n
/* ----------------------------------------------------------------------
\n
* Defines each of the tests performed
\n
* ------------------------------------------------------------------- */
\n
#define MAX_BLOCKSIZE     32
\n
#define DELTA           (0.000001f)
\n
\n
/* ----------------------------------------------------------------------
\n
* Test input data for Floating point Dot Product example for 32-blockSize
\n
* Generated by the MATLAB randn() function
\n
* ------------------------------------------------------------------- */
\n
/* ----------------------------------------------------------------------
\n
** Test input data of srcA for blockSize 32
\n
** ------------------------------------------------------------------- */
\n
float32_t srcA_buf_f32[MAX_BLOCKSIZE] =
\n
{
\n
  -0.4325648115282207,  -1.6655843782380970,  0.1253323064748307,
\n
   0.2876764203585489,  -1.1464713506814637,  1.1909154656429988,
\n
   1.1891642016521031,  -0.0376332765933176,  0.3272923614086541,
\n
   0.1746391428209245,  -0.1867085776814394,  0.7257905482933027,
\n
  -0.5883165430141887,   2.1831858181971011, -0.1363958830865957,
\n
   0.1139313135208096,   1.0667682113591888,  0.0592814605236053,
\n
  -0.0956484054836690,  -0.8323494636500225,  0.2944108163926404,
\n
  -1.3361818579378040,   0.7143245518189522,  1.6235620644462707,
\n
  -0.6917757017022868,   0.8579966728282626,  1.2540014216025324,
\n
  -1.5937295764474768,  -1.4409644319010200,  0.5711476236581780,
\n
  -0.3998855777153632,   0.6899973754643451
\n
};
\n
\n
/* ----------------------------------------------------------------------
\n
** Test input data of srcB for blockSize 32
\n
** ------------------------------------------------------------------- */
\n
float32_t srcB_buf_f32[MAX_BLOCKSIZE] =
\n
{
\n
   1.7491401329284098,  0.1325982188803279,   0.3252281811989881,
\n
  -0.7938091410349637,  0.3149236145048914,  -0.5272704888029532,
\n
   0.9322666565031119,  1.1646643544607362,  -2.0456694357357357,
\n
  -0.6443728590041911,  1.7410657940825480,   0.4867684246821860,
\n
   1.0488288293660140,  1.4885752747099299,   1.2705014969484090,
\n
  -1.8561241921210170,  2.1343209047321410,  1.4358467535865909,
\n
  -0.9173023332875400, -1.1060770780029008,   0.8105708062681296,
\n
   0.6985430696369063, -0.4015827425012831,   1.2687512030669628,
\n
  -0.7836083053674872,  0.2132664971465569,   0.7878984786088954,
\n
   0.8966819356782295, -0.1869172943544062,   1.0131816724341454,
\n
   0.2484350696132857,  0.0596083377937976
\n
};
\n
\n
/* Reference dot product output */
\n
float32_t  refDotProdOut = 5.9273644806352142;
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare Global variables
\n
* ------------------------------------------------------------------- */
\n
float32_t multOutput[MAX_BLOCKSIZE];  /* Intermediate output */
\n
float32_t testOutput;  /* Final ouput */
\n
\n
arm_status status;   /* Status of the example */
\n
\n
int32_t main(void)
\n
{
\n
  uint32_t i;       /* Loop counter */
\n
  float32_t diff;     /* Difference between reference and test outputs */
\n
\n
  /* Multiplication of two input buffers */
\n
  arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE);
\n
\n
  /* Accumulate the multiplication output values to
\n
     get the dot product of the two inputs */
\n
  for(i=0; i< MAX_BLOCKSIZE; i++)
\n
  {
\n
    arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);
\n
  }
\n
\n
  /* absolute value of difference between ref and test */
\n
  diff = fabsf(refDotProdOut - testOutput);
\n
\n
  /* Comparison of dot product value with reference */
\n
  if(diff > DELTA)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
  if( status == ARM_MATH_TEST_FAILURE)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_fft_bin_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fft_bin_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
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\n  
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\n\n\n\n\n
\n\n
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\n  
\n
arm_fft_bin_example_f32.c
  
\n
\n
\n
/* ---------------------------------------------------------------------- 
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.   
\n
*  
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
*  
\n
* Description:   Example code demonstrating calculation of Max energy bin of  
\n
*               frequency domain of input signal. 
\n
* 
\n
* Target Processor: Cortex-M4/Cortex-M3  
\n
*
\n
* Redistribution and use in source and binary forms, with or without 
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the 
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.  
\n
 * -------------------------------------------------------------------- */
\n
 
\n
#include "arm_math.h" 
\n
#include "arm_const_structs.h"
\n
 
\n
#define TEST_LENGTH_SAMPLES 2048 
\n
 
\n
/* ------------------------------------------------------------------- 
\n
* External Input and Output buffer Declarations for FFT Bin Example 
\n
* ------------------------------------------------------------------- */ 
\n
extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; 
\n
static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; 
\n
 
\n
/* ------------------------------------------------------------------ 
\n
* Global variables for FFT Bin Example 
\n
* ------------------------------------------------------------------- */ 
\n
uint32_t fftSize = 1024; 
\n
uint32_t ifftFlag = 0; 
\n
uint32_t doBitReverse = 1; 
\n
 
\n
/* Reference index at which max energy of bin ocuurs */ 
\n
uint32_t refIndex = 213, testIndex = 0; 
\n
 
\n
/* ---------------------------------------------------------------------- 
\n
* Max magnitude FFT Bin test 
\n
* ------------------------------------------------------------------- */ 
\n
 
\n
int32_t main(void) 
\n
{ 
\n
   
\n
  arm_status status; 
\n
  float32_t maxValue; 
\n
   
\n
  status = ARM_MATH_SUCCESS; 
\n
   
\n
  /* Process the data through the CFFT/CIFFT module */ 
\n
  arm_cfft_f32(&arm_cfft_sR_f32_len1024, testInput_f32_10khz, ifftFlag, doBitReverse);
\n
   
\n
  /* Process the data through the Complex Magnitude Module for  
\n
  calculating the magnitude at each bin */ 
\n
  arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize);  
\n
   
\n
  /* Calculates maxValue and returns corresponding BIN value */ 
\n
  arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); 
\n
   
\n
  if(testIndex !=  refIndex) 
\n
  { 
\n
    status = ARM_MATH_TEST_FAILURE; 
\n
  } 
\n
   
\n
  /* ---------------------------------------------------------------------- 
\n
  ** Loop here if the signals fail the PASS check. 
\n
  ** This denotes a test failure 
\n
  ** ------------------------------------------------------------------- */ 
\n
   
\n
  if( status != ARM_MATH_SUCCESS) 
\n
  { 
\n
    while(1); 
\n
  } 
\n
\n
  while(1);                             /* main function does not return */
\n
} 
\n
 
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_fir_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
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arm_fir_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
 *
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
 * Title:        arm_fir_example_f32.c
\n
 *
\n
 * Description:  Example code demonstrating how an FIR filter can be used
\n
 *               as a low pass filter.
\n
 *
\n
 * Target Processor: Cortex-M4/Cortex-M3
\n
 *
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
 * -------------------------------------------------------------------- */
\n
\n
/* ----------------------------------------------------------------------
\n
** Include Files
\n
** ------------------------------------------------------------------- */
\n
\n
#include "arm_math.h"
\n
#include "math_helper.h"
\n
\n
/* ----------------------------------------------------------------------
\n
** Macro Defines
\n
** ------------------------------------------------------------------- */
\n
\n
#define TEST_LENGTH_SAMPLES  320
\n
#define SNR_THRESHOLD_F32    140.0f
\n
#define BLOCK_SIZE            32
\n
#define NUM_TAPS              29
\n
\n
/* -------------------------------------------------------------------
\n
 * The input signal and reference output (computed with MATLAB)
\n
 * are defined externally in arm_fir_lpf_data.c.
\n
 * ------------------------------------------------------------------- */
\n
\n
extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES];
\n
extern float32_t refOutput[TEST_LENGTH_SAMPLES];
\n
\n
/* -------------------------------------------------------------------
\n
 * Declare Test output buffer
\n
 * ------------------------------------------------------------------- */
\n
\n
static float32_t testOutput[TEST_LENGTH_SAMPLES];
\n
\n
/* -------------------------------------------------------------------
\n
 * Declare State buffer of size (numTaps + blockSize - 1)
\n
 * ------------------------------------------------------------------- */
\n
\n
static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1];
\n
\n
/* ----------------------------------------------------------------------
\n
** FIR Coefficients buffer generated using fir1() MATLAB function.
\n
** fir1(28, 6/24)
\n
** ------------------------------------------------------------------- */
\n
\n
const float32_t firCoeffs32[NUM_TAPS] = {
\n
  -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f,
\n
  -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f,
\n
  +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f,
\n
  +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f
\n
};
\n
\n
/* ------------------------------------------------------------------
\n
 * Global variables for FIR LPF Example
\n
 * ------------------------------------------------------------------- */
\n
\n
uint32_t blockSize = BLOCK_SIZE;
\n
uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE;
\n
\n
float32_t  snr;
\n
\n
/* ----------------------------------------------------------------------
\n
 * FIR LPF Example
\n
 * ------------------------------------------------------------------- */
\n
\n
int32_t main(void)
\n
{
\n
  uint32_t i;
\n
  arm_fir_instance_f32 S;
\n
  arm_status status;
\n
  float32_t  *inputF32, *outputF32;
\n
\n
  /* Initialize input and output buffer pointers */
\n
  inputF32 = &testInput_f32_1kHz_15kHz[0];
\n
  outputF32 = &testOutput[0];
\n
\n
  /* Call FIR init function to initialize the instance structure. */
\n
  arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize);
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Call the FIR process function for every blockSize samples
\n
  ** ------------------------------------------------------------------- */
\n
\n
  for(i=0; i < numBlocks; i++)
\n
  {
\n
    arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Compare the generated output against the reference output computed
\n
  ** in MATLAB.
\n
  ** ------------------------------------------------------------------- */
\n
\n
  snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES);
\n
\n
  if (snr < SNR_THRESHOLD_F32)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
  else
\n
  {
\n
    status = ARM_MATH_SUCCESS;
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Loop here if the signal does not match the reference output.
\n
  ** ------------------------------------------------------------------- */
\n
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_graphic_equalizer_example_q31_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_graphic_equalizer_example_q31.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_graphic_equalizer_example_q31.c
  
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
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*
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* $Date:         17. January 2013
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* $Revision:     V1.4.0
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*
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* Project:       CMSIS DSP Library
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* Title:         arm_graphic_equalizer_example_q31.c
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*
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* Description:   Example showing an audio graphic equalizer constructed
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*                out of Biquad filters.
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*   - Redistributions of source code must retain the above copyright
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*     notice, this list of conditions and the following disclaimer.
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*   - Redistributions in binary form must reproduce the above copyright
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*     notice, this list of conditions and the following disclaimer in
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*     the documentation and/or other materials provided with the
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*     distribution.
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*   - Neither the name of ARM LIMITED nor the names of its contributors
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*     may be used to endorse or promote products derived from this
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*     software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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 * -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "math_helper.h"
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/* Length of the overall data in the test */
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#define TESTLENGTH 320
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/* Block size for the underlying processing */
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#define BLOCKSIZE 32
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/* Total number of blocks to run */
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#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
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/* Number of 2nd order Biquad stages per filter */
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#define NUMSTAGES 2
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#define SNR_THRESHOLD_F32  98
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/* -------------------------------------------------------------------
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 * External Declarations for Input and Output buffers
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 * ------------------------------------------------------------------- */
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extern float32_t testInput_f32[TESTLENGTH];
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static float32_t testOutput[TESTLENGTH];
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extern float32_t testRefOutput_f32[TESTLENGTH];
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/* ----------------------------------------------------------------------
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** Q31 state buffers for Band1, Band2, Band3, Band4, Band5
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** ------------------------------------------------------------------- */
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static q63_t biquadStateBand1Q31[4 * 2];
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static q63_t biquadStateBand2Q31[4 * 2];
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static q31_t biquadStateBand3Q31[4 * 2];
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static q31_t biquadStateBand4Q31[4 * 2];
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static q31_t biquadStateBand5Q31[4 * 2];
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/* ----------------------------------------------------------------------
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** Q31 input and output buffers
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** ------------------------------------------------------------------- */
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q31_t inputQ31[BLOCKSIZE];
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q31_t outputQ31[BLOCKSIZE];
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/* ----------------------------------------------------------------------
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** Entire coefficient table.  There are 10 coefficients per 4th order Biquad
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** cascade filter.  The first 10 coefficients correspond to the -9 dB gain
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** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
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** setting of band 1; and so on.  There are 10*19=190 coefficients in total
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** for band 1 (gains = -9, -8, -7, ..., 9).  After this come the 190 coefficients
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** for band 2.
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**
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** The coefficients are in Q29 format and require a postShift of 2.
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** ------------------------------------------------------------------- */
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const q31_t coeffTable[950] = {
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  /* Band 1, -9 dB gain */
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  535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981,
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  /* Band 1, -8 dB gain */
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  535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778,
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  535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686,
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  536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972,
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  536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897,
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  536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716,
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  536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676,
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  536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017,
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  536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975,
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  536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777,
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  537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648,
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  537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803,
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  537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454,
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  537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806,
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  537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059,
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  537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409,
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  537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045,
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  538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151,
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  538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907,
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  /* Band 2, -9 dB gain */
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  531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
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  /* Band 2, -8 dB gain */
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  532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122,
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  532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090,
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  533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573,
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  534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887,
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  534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373,
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  535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399,
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  535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368,
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  536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724,
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  536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953,
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  537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588,
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  537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208,
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  538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437,
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  539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946,
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  539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450,
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  540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700,
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  540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484,
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  541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621,
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  542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956,
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  518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571,
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  520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158,
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  522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225,
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  524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221,
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  526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897,
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  528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319,
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  530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872,
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  532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254,
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  534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474,
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  536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839,
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  538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937,
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  540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621,
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  542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987,
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  544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351,
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  547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226,
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  549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298,
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  551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401,
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  553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495,
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  555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644,
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  494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750,
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  498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942,
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  503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028,
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  508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289,
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  512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811,
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  517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485,
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  522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012,
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  527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882,
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  531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352,
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  536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420,
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  541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786,
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  546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816,
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  551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495,
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  556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389,
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  562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597,
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  567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710,
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  572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767,
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  577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214,
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  583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865,
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  387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270,
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  401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316,
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  416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319,
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  431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540,
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  447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528,
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  464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141,
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  481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559,
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  499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296,
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  517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221,
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  536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566,
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  556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943,
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  577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360,
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  598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230,
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  620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383,
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  643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077,
\n
  667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004,
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  692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294,
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  717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515,
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  744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673
\n
\n
};
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/* ----------------------------------------------------------------------
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** Desired gains, in dB, per band
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** ------------------------------------------------------------------- */
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int gainDB[5] = {0, -3, 6, 4, -6};
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float32_t snr;
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/* ----------------------------------------------------------------------
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 * Graphic equalizer Example
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 * ------------------------------------------------------------------- */
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int32_t main(void)
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{
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  float32_t  *inputF32, *outputF32;
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  arm_biquad_cas_df1_32x64_ins_q31 S1;
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  arm_biquad_cas_df1_32x64_ins_q31 S2;
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  arm_biquad_casd_df1_inst_q31 S3;
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  arm_biquad_casd_df1_inst_q31 S4;
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  arm_biquad_casd_df1_inst_q31 S5;
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  int i;
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  int32_t status;
\n
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  inputF32 = &testInput_f32[0];
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  outputF32 = &testOutput[0];
\n
\n
  /* Initialize the state and coefficient buffers for all Biquad sections */
\n
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  arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES,
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            (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
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            &biquadStateBand1Q31[0], 2);
\n
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  arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES,
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            (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
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            &biquadStateBand2Q31[0], 2);
\n
\n
  arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES,
\n
          (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
\n
          &biquadStateBand3Q31[0], 2);
\n
\n
  arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES,
\n
          (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
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          &biquadStateBand4Q31[0], 2);
\n
\n
  arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES,
\n
          (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
\n
          &biquadStateBand5Q31[0], 2);
\n
\n
\n
  /* Call the process functions and needs to change filter coefficients
\n
     for varying the gain of each band */
\n
\n
  for(i=0; i < NUMBLOCKS; i++)
\n
  {
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Convert block of input data from float to Q31
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Scale down by 1/8.  This provides additional headroom so that the
\n
    ** graphic EQ can apply gain.
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE);
\n
    arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE);
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE);
\n
    arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);
\n
    arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE);
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Convert Q31 result back to float
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
\n
\n
    /* ----------------------------------------------------------------------
\n
    ** Scale back up
\n
    ** ------------------------------------------------------------------- */
\n
\n
    arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
\n
  };
\n
\n
  snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
\n
\n
  if (snr < SNR_THRESHOLD_F32)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
  else
\n
  {
\n
    status = ARM_MATH_SUCCESS;
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Loop here if the signal does not match the reference output.
\n
  ** ------------------------------------------------------------------- */
\n
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_linear_interp_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_linear_interp_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
arm_linear_interp_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_linear_interp_example_f32.c
\n
*
\n
* Description:   Example code demonstrating usage of sin function
\n
*                and uses linear interpolation to get higher precision
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
 * -------------------------------------------------------------------- */
\n
\n
\n
#include "arm_math.h"
\n
#include "math_helper.h"
\n
\n
#define SNR_THRESHOLD           90
\n
#define TEST_LENGTH_SAMPLES     10
\n
#define XSPACING               (0.00005f)
\n
\n
/* ----------------------------------------------------------------------
\n
* Test input data for F32 SIN function
\n
* Generated by the MATLAB rand() function
\n
* randn('state', 0)
\n
* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
\n
* --------------------------------------------------------------------*/
\n
float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =
\n
{
\n
   -0.649716504673081170, -2.501723745497831200,
\n
    0.188250329003310100,  0.432092748487532540,
\n
   -1.722010988459680800,  1.788766476323060600,
\n
    1.786136060975809500, -0.056525543169408797,
\n
    0.491596272728153760,  0.262309671126153390
\n
};
\n
\n
/*------------------------------------------------------------------------------
\n
*  Reference out of SIN F32 function for Block Size = 10
\n
*  Calculated from sin(testInputSin_f32)
\n
*------------------------------------------------------------------------------*/
\n
float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =
\n
{
\n
   -0.604960695383043530, -0.597090287967934840,
\n
    0.187140422442966500,  0.418772124875992690,
\n
   -0.988588831792106880,  0.976338412038794010,
\n
    0.976903856413481100, -0.056495446835214236,
\n
    0.472033731854734240,  0.259311907228582830
\n
};
\n
\n
/*------------------------------------------------------------------------------
\n
*  Method 1: Test out Buffer Calculated from Cubic Interpolation
\n
*------------------------------------------------------------------------------*/
\n
float32_t testOutput[TEST_LENGTH_SAMPLES];
\n
\n
/*------------------------------------------------------------------------------
\n
*  Method 2: Test out buffer Calculated from Linear Interpolation
\n
*------------------------------------------------------------------------------*/
\n
float32_t testLinIntOutput[TEST_LENGTH_SAMPLES];
\n
\n
/*------------------------------------------------------------------------------
\n
*  External table used for linear interpolation
\n
*------------------------------------------------------------------------------*/
\n
extern float arm_linear_interep_table[188495];
\n
\n
/* ----------------------------------------------------------------------
\n
* Global Variables for caluclating SNR's for Method1 & Method 2
\n
* ------------------------------------------------------------------- */
\n
float32_t snr1;
\n
float32_t snr2;
\n
\n
/* ----------------------------------------------------------------------------
\n
* Calculation of Sine values from Cubic Interpolation and Linear interpolation
\n
* ---------------------------------------------------------------------------- */
\n
int32_t main(void)
\n
{
\n
  uint32_t i;
\n
  arm_status status;
\n
\n
  arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]};
\n
\n
  /*------------------------------------------------------------------------------
\n
  *  Method 1: Test out Calculated from Cubic Interpolation
\n
  *------------------------------------------------------------------------------*/
\n
  for(i=0; i< TEST_LENGTH_SAMPLES; i++)
\n
  {
\n
    testOutput[i] = arm_sin_f32(testInputSin_f32[i]);
\n
  }
\n
\n
  /*------------------------------------------------------------------------------
\n
  *  Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation
\n
  *------------------------------------------------------------------------------*/
\n
\n
  for(i=0; i< TEST_LENGTH_SAMPLES; i++)
\n
  {
\n
      testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
\n
  }
\n
\n
  /*------------------------------------------------------------------------------
\n
  *            SNR calculation for method 1
\n
  *------------------------------------------------------------------------------*/
\n
  snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2);
\n
\n
  /*------------------------------------------------------------------------------
\n
  *            SNR calculation for method 2
\n
  *------------------------------------------------------------------------------*/
\n
  snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2);
\n
\n
  /*------------------------------------------------------------------------------
\n
  *            Initialise status depending on SNR calculations
\n
  *------------------------------------------------------------------------------*/
\n
  if( snr2 > snr1)
\n
  {
\n
    status = ARM_MATH_SUCCESS;
\n
  }
\n
  else
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Loop here if the signals fail the PASS check.
\n
  ** This denotes a test failure
\n
  ** ------------------------------------------------------------------- */
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_matrix_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_matrix_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
arm_matrix_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_matrix_example_f32.c
\n
*
\n
* Description:   Example code demonstrating least square fit to data
\n
*                using matrix functions
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
 * -------------------------------------------------------------------- */
\n
\n
#include "arm_math.h"
\n
#include "math_helper.h"
\n
\n
#define SNR_THRESHOLD   90
\n
\n
/* --------------------------------------------------------------------------------
\n
* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize
\n
* and tapSize
\n
* --------------------------------------------------------------------------------- */
\n
\n
const float32_t B_f32[4] =
\n
{
\n
  782.0, 7577.0, 470.0, 4505.0
\n
};
\n
\n
/* --------------------------------------------------------------------------------
\n
* Formula to fit is  C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize
\n
* -------------------------------------------------------------------------------- */
\n
\n
const float32_t A_f32[16] =
\n
{
\n
  /* Const,   numTaps,   blockSize,   numTaps*blockSize */
\n
  1.0,     32.0,      4.0,     128.0,
\n
  1.0,     32.0,     64.0,    2048.0,
\n
  1.0,     16.0,      4.0,      64.0,
\n
  1.0,     16.0,     64.0,    1024.0,
\n
};
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Temporary buffers  for storing intermediate values
\n
* ------------------------------------------------------------------- */
\n
/* Transpose of A Buffer */
\n
float32_t AT_f32[16];
\n
/* (Transpose of A * A) Buffer */
\n
float32_t ATMA_f32[16];
\n
/* Inverse(Transpose of A * A)  Buffer */
\n
float32_t ATMAI_f32[16];
\n
/* Test Output Buffer */
\n
float32_t X_f32[4];
\n
\n
/* ----------------------------------------------------------------------
\n
* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB
\n
* ------------------------------------------------------------------- */
\n
const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875};
\n
\n
float32_t snr;
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Max magnitude FFT Bin test
\n
* ------------------------------------------------------------------- */
\n
\n
int32_t main(void)
\n
{
\n
\n
  arm_matrix_instance_f32 A;      /* Matrix A Instance */
\n
  arm_matrix_instance_f32 AT;     /* Matrix AT(A transpose) instance */
\n
  arm_matrix_instance_f32 ATMA;   /* Matrix ATMA( AT multiply with A) instance */
\n
  arm_matrix_instance_f32 ATMAI;  /* Matrix ATMAI(Inverse of ATMA) instance */
\n
  arm_matrix_instance_f32 B;      /* Matrix B instance */
\n
  arm_matrix_instance_f32 X;      /* Matrix X(Unknown Matrix) instance */
\n
\n
  uint32_t srcRows, srcColumns;  /* Temporary variables */
\n
  arm_status status;
\n
\n
  /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 4;
\n
  arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32);
\n
\n
  /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 4;
\n
  arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32);
\n
\n
  /* calculation of A transpose */
\n
  status = arm_mat_trans_f32(&A, &AT);
\n
\n
\n
  /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 4;
\n
  arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32);
\n
\n
  /* calculation of AT Multiply with A */
\n
  status = arm_mat_mult_f32(&AT, &A, &ATMA);
\n
\n
  /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 4;
\n
  arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32);
\n
\n
  /* calculation of Inverse((Transpose(A) * A) */
\n
  status = arm_mat_inverse_f32(&ATMA, &ATMAI);
\n
\n
  /* calculation of (Inverse((Transpose(A) * A)) *  Transpose(A)) */
\n
  status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA);
\n
\n
  /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 1;
\n
  arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);
\n
\n
  /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */
\n
  srcRows = 4;
\n
  srcColumns = 1;
\n
  arm_mat_init_f32(&X, srcRows, srcColumns, X_f32);
\n
\n
  /* calculation ((Inverse((Transpose(A) * A)) *  Transpose(A)) * B) */
\n
  status = arm_mat_mult_f32(&ATMA, &B, &X);
\n
\n
  /* Comparison of reference with test output */
\n
  snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4);
\n
\n
  /*------------------------------------------------------------------------------
\n
  *            Initialise status depending on SNR calculations
\n
  *------------------------------------------------------------------------------*/
\n
  if( snr > SNR_THRESHOLD)
\n
  {
\n
    status = ARM_MATH_SUCCESS;
\n
  }
\n
  else
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
\n
  /* ----------------------------------------------------------------------
\n
  ** Loop here if the signals fail the PASS check.
\n
  ** This denotes a test failure
\n
  ** ------------------------------------------------------------------- */
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_signal_converge_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_signal_converge_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
arm_signal_converge_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_signal_converge_example_f32.c
\n
*
\n
* Description:   Example code demonstrating convergence of an adaptive
\n
*                filter.
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
 * -------------------------------------------------------------------- */
\n
\n
#include "arm_math.h"
\n
#include "math_helper.h"
\n
\n
/* ----------------------------------------------------------------------
\n
** Global defines for the simulation
\n
* ------------------------------------------------------------------- */
\n
\n
#define TEST_LENGTH_SAMPLES 1536
\n
#define NUMTAPS               32
\n
#define BLOCKSIZE             32
\n
#define DELTA_ERROR         0.000001f
\n
#define DELTA_COEFF         0.0001f
\n
#define MU                  0.5f
\n
\n
#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE)
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare FIR state buffers and structure
\n
* ------------------------------------------------------------------- */
\n
\n
float32_t firStateF32[NUMTAPS + BLOCKSIZE];
\n
arm_fir_instance_f32 LPF_instance;
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare LMSNorm state buffers and structure
\n
* ------------------------------------------------------------------- */
\n
\n
float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];
\n
float32_t errOutput[TEST_LENGTH_SAMPLES];
\n
arm_lms_norm_instance_f32 lmsNorm_instance;
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Function Declarations for Signal Convergence Example
\n
* ------------------------------------------------------------------- */
\n
\n
arm_status test_signal_converge_example( void );
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Internal functions
\n
* ------------------------------------------------------------------- */
\n
arm_status test_signal_converge(float32_t* err_signal,
\n
                        uint32_t blockSize);
\n
\n
void getinput(float32_t* input,
\n
     uint32_t fr_cnt,
\n
          uint32_t blockSize);
\n
\n
/* ----------------------------------------------------------------------
\n
* External Declarations for FIR F32 module Test
\n
* ------------------------------------------------------------------- */
\n
extern float32_t testInput_f32[TEST_LENGTH_SAMPLES];
\n
extern float32_t lmsNormCoeff_f32[32];
\n
extern const float32_t FIRCoeff_f32[32];
\n
extern arm_lms_norm_instance_f32 lmsNorm_instance;
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare I/O buffers
\n
* ------------------------------------------------------------------- */
\n
\n
float32_t wire1[BLOCKSIZE];
\n
float32_t wire2[BLOCKSIZE];
\n
float32_t wire3[BLOCKSIZE];
\n
float32_t err_signal[BLOCKSIZE];
\n
\n
/* ----------------------------------------------------------------------
\n
* Signal converge test
\n
* ------------------------------------------------------------------- */
\n
\n
int32_t main(void)
\n
{
\n
  uint32_t i;
\n
  arm_status status;
\n
  uint32_t index;
\n
  float32_t minValue;
\n
\n
  /* Initialize the LMSNorm data structure */
\n
  arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE);
\n
\n
  /* Initialize the FIR data structure */
\n
  arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE);
\n
\n
  /* ----------------------------------------------------------------------
\n
  * Loop over the frames of data and execute each of the processing
\n
  * functions in the system.
\n
  * ------------------------------------------------------------------- */
\n
\n
  for(i=0; i < NUMFRAMES; i++)
\n
  {
\n
    /* Read the input data - uniformly distributed random noise - into wire1 */
\n
    arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE);
\n
\n
    /* Execute the FIR processing function.  Input wire1 and output wire2 */
\n
    arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE);
\n
\n
    /* Execute the LMS Norm processing function*/
\n
\n
    arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */
\n
         wire1,                         /* Input signal */
\n
         wire2,                         /* Reference Signal */
\n
         wire3,                         /* Converged Signal */
\n
         err_signal,                    /* Error Signal, this will become small as the signal converges */
\n
         BLOCKSIZE);                    /* BlockSize */
\n
\n
    /* apply overall gain */
\n
    arm_scale_f32(wire3, 5, wire3, BLOCKSIZE);   /* in-place buffer */
\n
  }
\n
\n
  status = ARM_MATH_SUCCESS;
\n
\n
  /* -------------------------------------------------------------------------------
\n
  * Test whether the error signal has reached towards 0.
\n
  * ----------------------------------------------------------------------------- */
\n
\n
  arm_abs_f32(err_signal, err_signal, BLOCKSIZE);
\n
  arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index);
\n
\n
  if (minValue > DELTA_ERROR)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  * Test whether the filter coefficients have converged.
\n
  * ------------------------------------------------------------------- */
\n
\n
  arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);
\n
\n
  arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS);
\n
  arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index);
\n
\n
  if (minValue > DELTA_COEFF)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
  /* ----------------------------------------------------------------------
\n
  * Loop here if the signals did not pass the convergence check.
\n
  * This denotes a test failure
\n
  * ------------------------------------------------------------------- */
\n
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_sin_cos_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_cos_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
arm_sin_cos_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_sin_cos_example_f32.c
\n
*
\n
* Description:   Example code demonstrating sin and cos calculation of input signal.
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
* -------------------------------------------------------------------- */
\n
\n
#include <math.h>
\n
#include "arm_math.h"
\n
\n
/* ----------------------------------------------------------------------
\n
* Defines each of the tests performed
\n
* ------------------------------------------------------------------- */
\n
#define MAX_BLOCKSIZE   32
\n
#define DELTA           (0.000001f)
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Test input data for Floating point sin_cos example for 32-blockSize
\n
* Generated by the MATLAB randn() function
\n
* ------------------------------------------------------------------- */
\n
\n
const float32_t testInput_f32[MAX_BLOCKSIZE] =
\n
{
\n
  -1.244916875853235400,  -4.793533929171324800,   0.360705030233248850,   0.827929644170887320,  -3.299532218312426900,   3.427441903227623800,   3.422401784294607700,  -0.108308165334010680,
\n
   0.941943896490312180,   0.502609575000365850,  -0.537345278736373500,   2.088817392965764500,  -1.693168684143455700,   6.283185307179590700,  -0.392545884746175080,   0.327893095115825040,
\n
   3.070147440456292300,   0.170611405884662230,  -0.275275082396073010,  -2.395492805446796300,   0.847311163536506600,  -3.845517018083148800,   2.055818378415868300,   4.672594161978930800,
\n
  -1.990923030266425800,   2.469305197656249500,   3.609002606064021000,  -4.586736582331667500,  -4.147080139136136300,   1.643756718868359500,  -1.150866392366494800,   1.985805026477433800
\n
\n
\n
};
\n
\n
const float32_t testRefOutput_f32 = 1.000000000;
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare Global variables
\n
* ------------------------------------------------------------------- */
\n
uint32_t blockSize = 32;
\n
float32_t  testOutput;
\n
float32_t  cosOutput;
\n
float32_t  sinOutput;
\n
float32_t  cosSquareOutput;
\n
float32_t  sinSquareOutput;
\n
\n
/* ----------------------------------------------------------------------
\n
* Max magnitude FFT Bin test
\n
* ------------------------------------------------------------------- */
\n
\n
arm_status status;
\n
\n
int32_t main(void)
\n
{
\n
  float32_t diff;
\n
  uint32_t i;
\n
\n
  for(i=0; i< blockSize; i++)
\n
  {
\n
    cosOutput = arm_cos_f32(testInput_f32[i]);
\n
    sinOutput = arm_sin_f32(testInput_f32[i]);
\n
\n
    arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1);
\n
    arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1);
\n
\n
    arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
\n
\n
    /* absolute value of difference between ref and test */
\n
    diff = fabsf(testRefOutput_f32 - testOutput);
\n
\n
    /* Comparison of sin_cos value with reference */
\n
    if(diff > DELTA)
\n
    {
\n
     status = ARM_MATH_TEST_FAILURE;
\n
    }
\n
\n
    if( status == ARM_MATH_TEST_FAILURE)
\n
    {
\n
       while(1);
\n
    }
\n
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/arm_variance_example_f32_8c-example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_variance_example_f32.c\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
arm_variance_example_f32.c
  
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
\n
*
\n
* $Date:         17. January 2013
\n
* $Revision:     V1.4.0
\n
*
\n
* Project:       CMSIS DSP Library
\n
* Title:         arm_variance_example_f32.c
\n
*
\n
* Description:   Example code demonstrating variance calculation of input sequence.
\n
*
\n
* Target Processor: Cortex-M4/Cortex-M3
\n
*
\n
* Redistribution and use in source and binary forms, with or without
\n
* modification, are permitted provided that the following conditions
\n
* are met:
\n
*   - Redistributions of source code must retain the above copyright
\n
*     notice, this list of conditions and the following disclaimer.
\n
*   - Redistributions in binary form must reproduce the above copyright
\n
*     notice, this list of conditions and the following disclaimer in
\n
*     the documentation and/or other materials provided with the
\n
*     distribution.
\n
*   - Neither the name of ARM LIMITED nor the names of its contributors
\n
*     may be used to endorse or promote products derived from this
\n
*     software without specific prior written permission.
\n
*
\n
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\n
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\n
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
\n
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
\n
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
\n
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
\n
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
\n
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\n
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
\n
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
\n
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
\n
* POSSIBILITY OF SUCH DAMAGE.
\n
* -------------------------------------------------------------------- */
\n
\n
#include <math.h>
\n
#include "arm_math.h"
\n
\n
/* ----------------------------------------------------------------------
\n
* Defines each of the tests performed
\n
* ------------------------------------------------------------------- */
\n
#define MAX_BLOCKSIZE   32
\n
#define DELTA           (0.000001f)
\n
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare I/O buffers
\n
* ------------------------------------------------------------------- */
\n
float32_t wire1[MAX_BLOCKSIZE];
\n
float32_t wire2[MAX_BLOCKSIZE];
\n
float32_t wire3[MAX_BLOCKSIZE];
\n
\n
/* ----------------------------------------------------------------------
\n
* Test input data for Floating point Variance example for 32-blockSize
\n
* Generated by the MATLAB randn() function
\n
* ------------------------------------------------------------------- */
\n
\n
float32_t testInput_f32[32] =
\n
{
\n
  -0.432564811528221,  -1.665584378238097,   0.125332306474831,   0.287676420358549,
\n
  -1.146471350681464,   1.190915465642999,   1.189164201652103,  -0.037633276593318,
\n
   0.327292361408654,   0.174639142820925,  -0.186708577681439,   0.725790548293303,
\n
  -0.588316543014189,   2.183185818197101,  -0.136395883086596,   0.113931313520810,
\n
   1.066768211359189,   0.059281460523605,  -0.095648405483669,  -0.832349463650022,
\n
   0.294410816392640,  -1.336181857937804,   0.714324551818952,   1.623562064446271,
\n
  -0.691775701702287,   0.857996672828263,   1.254001421602532,  -1.593729576447477,
\n
  -1.440964431901020,   0.571147623658178,  -0.399885577715363,   0.689997375464345
\n
\n
};
\n
\n
/* ----------------------------------------------------------------------
\n
* Declare Global variables
\n
* ------------------------------------------------------------------- */
\n
uint32_t blockSize = 32;
\n
float32_t  refVarianceOut = 0.903941793931839;
\n
\n
/* ----------------------------------------------------------------------
\n
* Variance calculation test
\n
* ------------------------------------------------------------------- */
\n
\n
int32_t main(void)
\n
{
\n
  arm_status status;
\n
  float32_t mean, oneByBlockSize;
\n
  float32_t variance;
\n
  float32_t diff;
\n
\n
  status = ARM_MATH_SUCCESS;
\n
\n
  /* Calculation of mean value of input */
\n
\n
  /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
\n
\n
  /* Fill wire1 buffer with 1.0 value */
\n
  arm_fill_f32(1.0,  wire1, blockSize);
\n
\n
  /* Calculate the dot product of wire1 and wire2 */
\n
  /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
\n
  arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
\n
\n
  /* Calculation of 1/blockSize */
\n
  oneByBlockSize = 1.0 / (blockSize);
\n
\n
  /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1)  */
\n
  arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
\n
\n
\n
  /* Calculation of variance value of input */
\n
\n
  /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
\n
\n
  /* Fill wire2 with mean value x' */
\n
  arm_fill_f32(mean,  wire2, blockSize);
\n
\n
  /* wire3 contains (x-x') */
\n
  arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
\n
\n
  /* wire2 contains (x-x') */
\n
  arm_copy_f32(wire3, wire2, blockSize);
\n
\n
  /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
\n
  arm_dot_prod_f32(wire2, wire3, blockSize, &variance);
\n
\n
    /* Calculation of 1/blockSize */
\n
  oneByBlockSize = 1.0 / (blockSize - 1);
\n
\n
  /* Calculation of variance */
\n
  arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
\n
\n
  /* absolute value of difference between ref and test */
\n
  diff = fabsf(refVarianceOut - variance);
\n
\n
  /* Comparison of variance value with reference */
\n
  if(diff > DELTA)
\n
  {
\n
    status = ARM_MATH_TEST_FAILURE;
\n
  }
\n
\n
  if( status != ARM_MATH_SUCCESS)
\n
  {
\n
    while(1);
\n
  }
\n
\n
  while(1);                             /* main function does not return */
\n
}
\n
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:53 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/classes.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Structure Index\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
Data Structure Index
  
\n
\n
\n
B | C | D | F | I | L | M | P | R
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
  B  
\n		arm_cfft_radix2_instance_q15   arm_fir_instance_f32   arm_iir_lattice_instance_q15   arm_matrix_instance_q31   
arm_cfft_radix2_instance_q31   arm_fir_instance_q15   arm_iir_lattice_instance_q31   
  P  
\n
arm_bilinear_interp_instance_f32   arm_cfft_radix4_instance_f32   arm_fir_instance_q31   
  L  
\n
arm_bilinear_interp_instance_q15   arm_cfft_radix4_instance_q15   arm_fir_instance_q7   arm_pid_instance_f32   
arm_bilinear_interp_instance_q31   arm_cfft_radix4_instance_q31   arm_fir_interpolate_instance_f32   arm_linear_interp_instance_f32   arm_pid_instance_q15   
arm_bilinear_interp_instance_q7   
  D  
\n		arm_fir_interpolate_instance_q15   arm_lms_instance_f32   arm_pid_instance_q31   
arm_biquad_cas_df1_32x64_ins_q31   arm_fir_interpolate_instance_q31   arm_lms_instance_q15   
  R  
\n
arm_biquad_cascade_df2T_instance_f32   arm_dct4_instance_f32   arm_fir_lattice_instance_f32   arm_lms_instance_q31   
arm_biquad_casd_df1_inst_f32   arm_dct4_instance_q15   arm_fir_lattice_instance_q15   arm_lms_norm_instance_f32   arm_rfft_fast_instance_f32   
arm_biquad_casd_df1_inst_q15   arm_dct4_instance_q31   arm_fir_lattice_instance_q31   arm_lms_norm_instance_q15   arm_rfft_instance_f32   
arm_biquad_casd_df1_inst_q31   
  F  
\n		arm_fir_sparse_instance_f32   arm_lms_norm_instance_q31   arm_rfft_instance_q15   
  C  
\n		arm_fir_sparse_instance_q15   
  M  
\n		arm_rfft_instance_q31   
arm_fir_decimate_instance_f32   arm_fir_sparse_instance_q31   
arm_cfft_instance_f32   arm_fir_decimate_instance_q15   arm_fir_sparse_instance_q7   arm_matrix_instance_f32   
arm_cfft_radix2_instance_f32   arm_fir_decimate_instance_q31   
  I  
\n		arm_matrix_instance_q15   
arm_iir_lattice_instance_f32   
\n
B | C | D | F | I | L | M | P | R
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    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #2D4068;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n\theight: 28px;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\n\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #354E81;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/deprecated.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Deprecated List\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Deprecated List 
  
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Global arm_cfft_radix2_f32  (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
\n
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future.  
\n
Global arm_cfft_radix2_init_f32  (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
\n
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future.  
\n
Global arm_cfft_radix4_f32  (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
\n
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future.  
\n
Global arm_cfft_radix4_init_f32  (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
\n
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future.  
\n
Global arm_rfft_f32  (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
\n
Do not use this function. It has been superceded by arm_rfft_fast_f32 and will be removed in the future.  
\n
Global arm_rfft_init_f32  (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
\n
Do not use this function. It has been superceded by arm_rfft_fast_init_f32 and will be removed in the future. 
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_0bd53153155fe3870c529e4f415d4a7e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_convolution_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_convolution_example Directory Reference
  
\n
\n
\n\n\n\n\n
\nFiles
file  arm_convolution_example_f32.c
 
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\n  \n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_1a6938f21b9d3ee9631dba1cb5e9a79b.html",
    "content": "\n\n\n\n\nCMSIS-DSP: BasicMathFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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BasicMathFunctions Directory Reference
  
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\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFiles
file  arm_abs_f32.c
 
file  arm_abs_q15.c
 
file  arm_abs_q31.c
 
file  arm_abs_q7.c
 
file  arm_add_f32.c
 
file  arm_add_q15.c
 
file  arm_add_q31.c
 
file  arm_add_q7.c
 
file  arm_dot_prod_f32.c
 
file  arm_dot_prod_q15.c
 
file  arm_dot_prod_q31.c
 
file  arm_dot_prod_q7.c
 
file  arm_mult_f32.c
 
file  arm_mult_q15.c
 
file  arm_mult_q31.c
 
file  arm_mult_q7.c
 
file  arm_negate_f32.c
 
file  arm_negate_q15.c
 
file  arm_negate_q31.c
 
file  arm_negate_q7.c
 
file  arm_offset_f32.c
 
file  arm_offset_q15.c
 
file  arm_offset_q31.c
 
file  arm_offset_q7.c
 
file  arm_scale_f32.c
 
file  arm_scale_q15.c
 
file  arm_scale_q31.c
 
file  arm_scale_q7.c
 
file  arm_shift_q15.c
 
file  arm_shift_q31.c
 
file  arm_shift_q7.c
 
file  arm_sub_f32.c
 
file  arm_sub_q15.c
 
file  arm_sub_q31.c
 
file  arm_sub_q7.c
 
\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_2540fe3bf997579a35b40d050fd58db0.html",
    "content": "\n\n\n\n\nCMSIS-DSP: ControllerFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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ControllerFunctions Directory Reference
  
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\nFiles
file  arm_pid_init_f32.c
 
file  arm_pid_init_q15.c
 
file  arm_pid_init_q31.c
 
file  arm_pid_reset_f32.c
 
file  arm_pid_reset_q15.c
 
file  arm_pid_reset_q31.c
 
file  arm_sin_cos_f32.c
 
file  arm_sin_cos_q31.c
 
\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_277e8c030ad55801c3a0b8702cd5e7d0.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Common Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Common Directory Reference
  
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\nDirectories
directory  Include
 
directory  Source
 
\n\n\n\n\n\n\n\n\n\n\n
\nFiles
file  system_ARMCM0.c
 CMSIS Device System Source File for ARMCM0 Device Series. 
 
file  system_ARMCM3.c
 CMSIS Device System Source File for ARMCM3 Device Series. 
 
file  system_ARMCM4.c
 CMSIS Device System Source File for ARMCM4 Device Series. 
 
\n
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  • DSP_Lib
  • Examples
  • Common
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    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_2c6bf793c39a551cb3665287541dc62d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: FilteringFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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FilteringFunctions Directory Reference
  
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\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFiles
file  arm_biquad_cascade_df1_32x64_init_q31.c
 
file  arm_biquad_cascade_df1_32x64_q31.c
 
file  arm_biquad_cascade_df1_f32.c
 
file  arm_biquad_cascade_df1_fast_q15.c
 
file  arm_biquad_cascade_df1_fast_q31.c
 
file  arm_biquad_cascade_df1_init_f32.c
 
file  arm_biquad_cascade_df1_init_q15.c
 
file  arm_biquad_cascade_df1_init_q31.c
 
file  arm_biquad_cascade_df1_q15.c
 
file  arm_biquad_cascade_df1_q31.c
 
file  arm_biquad_cascade_df2T_f32.c
 
file  arm_biquad_cascade_df2T_init_f32.c
 
file  arm_conv_f32.c
 
file  arm_conv_fast_opt_q15.c
 
file  arm_conv_fast_q15.c
 
file  arm_conv_fast_q31.c
 
file  arm_conv_opt_q15.c
 
file  arm_conv_opt_q7.c
 
file  arm_conv_partial_f32.c
 
file  arm_conv_partial_fast_opt_q15.c
 
file  arm_conv_partial_fast_q15.c
 
file  arm_conv_partial_fast_q31.c
 
file  arm_conv_partial_opt_q15.c
 
file  arm_conv_partial_opt_q7.c
 
file  arm_conv_partial_q15.c
 
file  arm_conv_partial_q31.c
 
file  arm_conv_partial_q7.c
 
file  arm_conv_q15.c
 
file  arm_conv_q31.c
 
file  arm_conv_q7.c
 
file  arm_correlate_f32.c
 
file  arm_correlate_fast_opt_q15.c
 
file  arm_correlate_fast_q15.c
 
file  arm_correlate_fast_q31.c
 
file  arm_correlate_opt_q15.c
 
file  arm_correlate_opt_q7.c
 
file  arm_correlate_q15.c
 
file  arm_correlate_q31.c
 
file  arm_correlate_q7.c
 
file  arm_fir_decimate_f32.c
 
file  arm_fir_decimate_fast_q15.c
 
file  arm_fir_decimate_fast_q31.c
 
file  arm_fir_decimate_init_f32.c
 
file  arm_fir_decimate_init_q15.c
 
file  arm_fir_decimate_init_q31.c
 
file  arm_fir_decimate_q15.c
 
file  arm_fir_decimate_q31.c
 
file  arm_fir_f32.c
 
file  arm_fir_fast_q15.c
 
file  arm_fir_fast_q31.c
 
file  arm_fir_init_f32.c
 
file  arm_fir_init_q15.c
 
file  arm_fir_init_q31.c
 
file  arm_fir_init_q7.c
 
file  arm_fir_interpolate_f32.c
 
file  arm_fir_interpolate_init_f32.c
 
file  arm_fir_interpolate_init_q15.c
 
file  arm_fir_interpolate_init_q31.c
 
file  arm_fir_interpolate_q15.c
 
file  arm_fir_interpolate_q31.c
 
file  arm_fir_lattice_f32.c
 
file  arm_fir_lattice_init_f32.c
 
file  arm_fir_lattice_init_q15.c
 
file  arm_fir_lattice_init_q31.c
 
file  arm_fir_lattice_q15.c
 
file  arm_fir_lattice_q31.c
 
file  arm_fir_q15.c
 
file  arm_fir_q31.c
 
file  arm_fir_q7.c
 
file  arm_fir_sparse_f32.c
 
file  arm_fir_sparse_init_f32.c
 
file  arm_fir_sparse_init_q15.c
 
file  arm_fir_sparse_init_q31.c
 
file  arm_fir_sparse_init_q7.c
 
file  arm_fir_sparse_q15.c
 
file  arm_fir_sparse_q31.c
 
file  arm_fir_sparse_q7.c
 
file  arm_iir_lattice_f32.c
 
file  arm_iir_lattice_init_f32.c
 
file  arm_iir_lattice_init_q15.c
 
file  arm_iir_lattice_init_q31.c
 
file  arm_iir_lattice_q15.c
 
file  arm_iir_lattice_q31.c
 
file  arm_lms_f32.c
 
file  arm_lms_init_f32.c
 
file  arm_lms_init_q15.c
 
file  arm_lms_init_q31.c
 
file  arm_lms_norm_f32.c
 
file  arm_lms_norm_init_f32.c
 
file  arm_lms_norm_init_q15.c
 
file  arm_lms_norm_init_q31.c
 
file  arm_lms_norm_q15.c
 
file  arm_lms_norm_q31.c
 
file  arm_lms_q15.c
 
file  arm_lms_q31.c
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_38d31328c42027cc5452e7496de7b88f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fft_bin_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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\nFiles
file  arm_fft_bin_data.c
 
file  arm_fft_bin_example_f32.c
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_4714731cfbb1de4dc44e33e6cd6e4a5c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: FastMathFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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\nFiles
file  arm_cos_f32.c
 
file  arm_cos_q15.c
 
file  arm_cos_q31.c
 
file  arm_sin_f32.c
 
file  arm_sin_q15.c
 
file  arm_sin_q31.c
 
file  arm_sqrt_q15.c
 
file  arm_sqrt_q31.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_50f4d4f91ce5cd72cb6928b47e85a7f8.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Examples Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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\nDirectories
directory  arm_class_marks_example
 
directory  arm_convolution_example
 
directory  arm_dotproduct_example
 
directory  arm_fft_bin_example
 
directory  arm_fir_example
 
directory  arm_graphic_equalizer_example
 
directory  arm_linear_interp_example
 
directory  arm_matrix_example
 
directory  arm_signal_converge_example
 
directory  arm_sin_cos_example
 
directory  arm_variance_example
 
directory  Common
 
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_56cec670f0bb78d679862f48f54d3df2.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_class_marks_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_class_marks_example_f32.c
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_6128d62f89366c4b8843a6e619831037.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_matrix_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_matrix_example Directory Reference
  
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file  arm_matrix_example_f32.c
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_640aa2eed9b78c9534642de10c55cd76.html",
    "content": "\n\n\n\n\nCMSIS-DSP: ComplexMathFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_7e8aa87db1ad6b3d9b1f25792e7c5208.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Source Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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\nDirectories
directory  BasicMathFunctions
 
directory  CommonTables
 
directory  ComplexMathFunctions
 
directory  ControllerFunctions
 
directory  FastMathFunctions
 
directory  FilteringFunctions
 
directory  MatrixFunctions
 
directory  StatisticsFunctions
 
directory  SupportFunctions
 
directory  TransformFunctions
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_82f440d47881c253175a7975df0d431b.html",
    "content": "\n\n\n\n\nCMSIS-DSP: CommonTables Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_common_tables.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_856524284ebe840938865dc061f982fb.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Include Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Include Directory Reference
  
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file  arm_common_tables.h
 
file  arm_const_structs.h
 
file  arm_math.h
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_8ddec3780f04ee1aa048aaa2e17393b1.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Source Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  math_helper.c
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_9aca731d350c1cdbae92b5821b7281b6.html",
    "content": "\n\n\n\n\nCMSIS-DSP: SupportFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\nFiles
file  arm_copy_f32.c
 
file  arm_copy_q15.c
 
file  arm_copy_q31.c
 
file  arm_copy_q7.c
 
file  arm_fill_f32.c
 
file  arm_fill_q15.c
 
file  arm_fill_q31.c
 
file  arm_fill_q7.c
 
file  arm_float_to_q15.c
 
file  arm_float_to_q31.c
 
file  arm_float_to_q7.c
 
file  arm_q15_to_float.c
 
file  arm_q15_to_q31.c
 
file  arm_q15_to_q7.c
 
file  arm_q31_to_float.c
 
file  arm_q31_to_q15.c
 
file  arm_q31_to_q7.c
 
file  arm_q7_to_float.c
 
file  arm_q7_to_q15.c
 
file  arm_q7_to_q31.c
 
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    "content": "\n\n\n\n\nCMSIS-DSP: TransformFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\nFiles
file  arm_bitreversal.c
 
file  arm_cfft_f32.c
 
file  arm_cfft_radix2_f32.c
 
file  arm_cfft_radix2_init_f32.c
 
file  arm_cfft_radix2_init_q15.c
 
file  arm_cfft_radix2_init_q31.c
 
file  arm_cfft_radix2_q15.c
 
file  arm_cfft_radix2_q31.c
 
file  arm_cfft_radix4_f32.c
 
file  arm_cfft_radix4_init_f32.c
 
file  arm_cfft_radix4_init_q15.c
 
file  arm_cfft_radix4_init_q31.c
 
file  arm_cfft_radix4_q15.c
 
file  arm_cfft_radix4_q31.c
 
file  arm_cfft_radix8_f32.c
 
file  arm_dct4_f32.c
 
file  arm_dct4_init_f32.c
 
file  arm_dct4_init_q15.c
 
file  arm_dct4_init_q31.c
 
file  arm_dct4_q15.c
 
file  arm_dct4_q31.c
 
file  arm_rfft_f32.c
 
file  arm_rfft_fast_f32.c
 
file  arm_rfft_fast_init_f32.c
 
file  arm_rfft_init_f32.c
 
file  arm_rfft_init_q15.c
 
file  arm_rfft_init_q31.c
 
file  arm_rfft_q15.c
 
file  arm_rfft_q31.c
 
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    "content": "\n\n\n\n\nCMSIS-DSP: StatisticsFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\nFiles
file  arm_max_f32.c
 
file  arm_max_q15.c
 
file  arm_max_q31.c
 
file  arm_max_q7.c
 
file  arm_mean_f32.c
 
file  arm_mean_q15.c
 
file  arm_mean_q31.c
 
file  arm_mean_q7.c
 
file  arm_min_f32.c
 
file  arm_min_q15.c
 
file  arm_min_q31.c
 
file  arm_min_q7.c
 
file  arm_power_f32.c
 
file  arm_power_q15.c
 
file  arm_power_q31.c
 
file  arm_power_q7.c
 
file  arm_rms_f32.c
 
file  arm_rms_q15.c
 
file  arm_rms_q31.c
 
file  arm_std_f32.c
 
file  arm_std_q15.c
 
file  arm_std_q31.c
 
file  arm_var_f32.c
 
file  arm_var_q15.c
 
file  arm_var_q31.c
 
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    "content": "\n\n\n\n\nCMSIS-DSP: Include Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  math_helper.h
 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_be2d3df67661aefe0e3f0071a1d6f8f1.html",
    "content": "\n\n\n\n\nCMSIS-DSP: DSP_Lib Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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\nDirectories
directory  Examples
 
directory  Source
 
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  • DSP_Lib
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_cc6125d285775e245d68db3d4ce69092.html",
    "content": "\n\n\n\n\nCMSIS-DSP: MatrixFunctions Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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MatrixFunctions Directory Reference
  
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\nFiles
file  arm_mat_add_f32.c
 
file  arm_mat_add_q15.c
 
file  arm_mat_add_q31.c
 
file  arm_mat_init_f32.c
 
file  arm_mat_init_q15.c
 
file  arm_mat_init_q31.c
 
file  arm_mat_inverse_f32.c
 
file  arm_mat_mult_f32.c
 
file  arm_mat_mult_fast_q15.c
 
file  arm_mat_mult_fast_q31.c
 
file  arm_mat_mult_q15.c
 
file  arm_mat_mult_q31.c
 
file  arm_mat_scale_f32.c
 
file  arm_mat_scale_q15.c
 
file  arm_mat_scale_q31.c
 
file  arm_mat_sub_f32.c
 
file  arm_mat_sub_q15.c
 
file  arm_mat_sub_q31.c
 
file  arm_mat_trans_f32.c
 
file  arm_mat_trans_q15.c
 
file  arm_mat_trans_q31.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_cf417d728100a167f563acfac33cb7c7.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_linear_interp_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_linear_interp_example_f32.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_d1af19de43f00bd515b519c982d49d68.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_sin_cos_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_dotproduct_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_fir_data.c
 
file  arm_fir_example_f32.c
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_variance_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_variance_example Directory Reference
  
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file  arm_variance_example_f32.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dir_e4eb7b834609f1fe20523c66b23e4a87.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_graphic_equalizer_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_graphic_equalizer_data.c
 
file  arm_graphic_equalizer_example_q31.c
 
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_signal_converge_example Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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file  arm_signal_converge_data.c
 
file  arm_signal_converge_example_f32.c
 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l\n\n\n\n\nCMSIS-DSP: Examples\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/files.html",
    "content": "\n\n\n\n\nCMSIS-DSP: File List\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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File List
  
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Here is a list of all files with brief descriptions:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\"o\"\"*\"arm_abs_f32.c
\"o\"\"*\"arm_abs_q15.c
\"o\"\"*\"arm_abs_q31.c
\"o\"\"*\"arm_abs_q7.c
\"o\"\"*\"arm_add_f32.c
\"o\"\"*\"arm_add_q15.c
\"o\"\"*\"arm_add_q31.c
\"o\"\"*\"arm_add_q7.c
\"o\"\"*\"arm_biquad_cascade_df1_32x64_init_q31.c
\"o\"\"*\"arm_biquad_cascade_df1_32x64_q31.c
\"o\"\"*\"arm_biquad_cascade_df1_f32.c
\"o\"\"*\"arm_biquad_cascade_df1_fast_q15.c
\"o\"\"*\"arm_biquad_cascade_df1_fast_q31.c
\"o\"\"*\"arm_biquad_cascade_df1_init_f32.c
\"o\"\"*\"arm_biquad_cascade_df1_init_q15.c
\"o\"\"*\"arm_biquad_cascade_df1_init_q31.c
\"o\"\"*\"arm_biquad_cascade_df1_q15.c
\"o\"\"*\"arm_biquad_cascade_df1_q31.c
\"o\"\"*\"arm_biquad_cascade_df2T_f32.c
\"o\"\"*\"arm_biquad_cascade_df2T_init_f32.c
\"o\"\"*\"arm_bitreversal.c
\"o\"\"*\"arm_cfft_f32.c
\"o\"\"*\"arm_cfft_radix2_f32.c
\"o\"\"*\"arm_cfft_radix2_init_f32.c
\"o\"\"*\"arm_cfft_radix2_init_q15.c
\"o\"\"*\"arm_cfft_radix2_init_q31.c
\"o\"\"*\"arm_cfft_radix2_q15.c
\"o\"\"*\"arm_cfft_radix2_q31.c
\"o\"\"*\"arm_cfft_radix4_f32.c
\"o\"\"*\"arm_cfft_radix4_init_f32.c
\"o\"\"*\"arm_cfft_radix4_init_q15.c
\"o\"\"*\"arm_cfft_radix4_init_q31.c
\"o\"\"*\"arm_cfft_radix4_q15.c
\"o\"\"*\"arm_cfft_radix4_q31.c
\"o\"\"*\"arm_cfft_radix8_f32.c
\"o\"\"*\"arm_class_marks_example_f32.c
\"o\"\"*\"arm_cmplx_conj_f32.c
\"o\"\"*\"arm_cmplx_conj_q15.c
\"o\"\"*\"arm_cmplx_conj_q31.c
\"o\"\"*\"arm_cmplx_dot_prod_f32.c
\"o\"\"*\"arm_cmplx_dot_prod_q15.c
\"o\"\"*\"arm_cmplx_dot_prod_q31.c
\"o\"\"*\"arm_cmplx_mag_f32.c
\"o\"\"*\"arm_cmplx_mag_q15.c
\"o\"\"*\"arm_cmplx_mag_q31.c
\"o\"\"*\"arm_cmplx_mag_squared_f32.c
\"o\"\"*\"arm_cmplx_mag_squared_q15.c
\"o\"\"*\"arm_cmplx_mag_squared_q31.c
\"o\"\"*\"arm_cmplx_mult_cmplx_f32.c
\"o\"\"*\"arm_cmplx_mult_cmplx_q15.c
\"o\"\"*\"arm_cmplx_mult_cmplx_q31.c
\"o\"\"*\"arm_cmplx_mult_real_f32.c
\"o\"\"*\"arm_cmplx_mult_real_q15.c
\"o\"\"*\"arm_cmplx_mult_real_q31.c
\"o\"\"*\"arm_common_tables.c
\"o\"\"*\"arm_common_tables.h
\"o\"\"*\"arm_const_structs.h
\"o\"\"*\"arm_conv_f32.c
\"o\"\"*\"arm_conv_fast_opt_q15.c
\"o\"\"*\"arm_conv_fast_q15.c
\"o\"\"*\"arm_conv_fast_q31.c
\"o\"\"*\"arm_conv_opt_q15.c
\"o\"\"*\"arm_conv_opt_q7.c
\"o\"\"*\"arm_conv_partial_f32.c
\"o\"\"*\"arm_conv_partial_fast_opt_q15.c
\"o\"\"*\"arm_conv_partial_fast_q15.c
\"o\"\"*\"arm_conv_partial_fast_q31.c
\"o\"\"*\"arm_conv_partial_opt_q15.c
\"o\"\"*\"arm_conv_partial_opt_q7.c
\"o\"\"*\"arm_conv_partial_q15.c
\"o\"\"*\"arm_conv_partial_q31.c
\"o\"\"*\"arm_conv_partial_q7.c
\"o\"\"*\"arm_conv_q15.c
\"o\"\"*\"arm_conv_q31.c
\"o\"\"*\"arm_conv_q7.c
\"o\"\"*\"arm_convolution_example_f32.c
\"o\"\"*\"arm_copy_f32.c
\"o\"\"*\"arm_copy_q15.c
\"o\"\"*\"arm_copy_q31.c
\"o\"\"*\"arm_copy_q7.c
\"o\"\"*\"arm_correlate_f32.c
\"o\"\"*\"arm_correlate_fast_opt_q15.c
\"o\"\"*\"arm_correlate_fast_q15.c
\"o\"\"*\"arm_correlate_fast_q31.c
\"o\"\"*\"arm_correlate_opt_q15.c
\"o\"\"*\"arm_correlate_opt_q7.c
\"o\"\"*\"arm_correlate_q15.c
\"o\"\"*\"arm_correlate_q31.c
\"o\"\"*\"arm_correlate_q7.c
\"o\"\"*\"arm_cos_f32.c
\"o\"\"*\"arm_cos_q15.c
\"o\"\"*\"arm_cos_q31.c
\"o\"\"*\"arm_dct4_f32.c
\"o\"\"*\"arm_dct4_init_f32.c
\"o\"\"*\"arm_dct4_init_q15.c
\"o\"\"*\"arm_dct4_init_q31.c
\"o\"\"*\"arm_dct4_q15.c
\"o\"\"*\"arm_dct4_q31.c
\"o\"\"*\"arm_dot_prod_f32.c
\"o\"\"*\"arm_dot_prod_q15.c
\"o\"\"*\"arm_dot_prod_q31.c
\"o\"\"*\"arm_dot_prod_q7.c
\"o\"\"*\"arm_dotproduct_example_f32.c
\"o\"\"*\"arm_fft_bin_data.c
\"o\"\"*\"arm_fft_bin_example_f32.c
\"o\"\"*\"arm_fill_f32.c
\"o\"\"*\"arm_fill_q15.c
\"o\"\"*\"arm_fill_q31.c
\"o\"\"*\"arm_fill_q7.c
\"o\"\"*\"arm_fir_data.c
\"o\"\"*\"arm_fir_decimate_f32.c
\"o\"\"*\"arm_fir_decimate_fast_q15.c
\"o\"\"*\"arm_fir_decimate_fast_q31.c
\"o\"\"*\"arm_fir_decimate_init_f32.c
\"o\"\"*\"arm_fir_decimate_init_q15.c
\"o\"\"*\"arm_fir_decimate_init_q31.c
\"o\"\"*\"arm_fir_decimate_q15.c
\"o\"\"*\"arm_fir_decimate_q31.c
\"o\"\"*\"arm_fir_example_f32.c
\"o\"\"*\"arm_fir_f32.c
\"o\"\"*\"arm_fir_fast_q15.c
\"o\"\"*\"arm_fir_fast_q31.c
\"o\"\"*\"arm_fir_init_f32.c
\"o\"\"*\"arm_fir_init_q15.c
\"o\"\"*\"arm_fir_init_q31.c
\"o\"\"*\"arm_fir_init_q7.c
\"o\"\"*\"arm_fir_interpolate_f32.c
\"o\"\"*\"arm_fir_interpolate_init_f32.c
\"o\"\"*\"arm_fir_interpolate_init_q15.c
\"o\"\"*\"arm_fir_interpolate_init_q31.c
\"o\"\"*\"arm_fir_interpolate_q15.c
\"o\"\"*\"arm_fir_interpolate_q31.c
\"o\"\"*\"arm_fir_lattice_f32.c
\"o\"\"*\"arm_fir_lattice_init_f32.c
\"o\"\"*\"arm_fir_lattice_init_q15.c
\"o\"\"*\"arm_fir_lattice_init_q31.c
\"o\"\"*\"arm_fir_lattice_q15.c
\"o\"\"*\"arm_fir_lattice_q31.c
\"o\"\"*\"arm_fir_q15.c
\"o\"\"*\"arm_fir_q31.c
\"o\"\"*\"arm_fir_q7.c
\"o\"\"*\"arm_fir_sparse_f32.c
\"o\"\"*\"arm_fir_sparse_init_f32.c
\"o\"\"*\"arm_fir_sparse_init_q15.c
\"o\"\"*\"arm_fir_sparse_init_q31.c
\"o\"\"*\"arm_fir_sparse_init_q7.c
\"o\"\"*\"arm_fir_sparse_q15.c
\"o\"\"*\"arm_fir_sparse_q31.c
\"o\"\"*\"arm_fir_sparse_q7.c
\"o\"\"*\"arm_float_to_q15.c
\"o\"\"*\"arm_float_to_q31.c
\"o\"\"*\"arm_float_to_q7.c
\"o\"\"*\"arm_graphic_equalizer_data.c
\"o\"\"*\"arm_graphic_equalizer_example_q31.c
\"o\"\"*\"arm_iir_lattice_f32.c
\"o\"\"*\"arm_iir_lattice_init_f32.c
\"o\"\"*\"arm_iir_lattice_init_q15.c
\"o\"\"*\"arm_iir_lattice_init_q31.c
\"o\"\"*\"arm_iir_lattice_q15.c
\"o\"\"*\"arm_iir_lattice_q31.c
\"o\"\"*\"arm_linear_interp_data.c
\"o\"\"*\"arm_linear_interp_example_f32.c
\"o\"\"*\"arm_lms_f32.c
\"o\"\"*\"arm_lms_init_f32.c
\"o\"\"*\"arm_lms_init_q15.c
\"o\"\"*\"arm_lms_init_q31.c
\"o\"\"*\"arm_lms_norm_f32.c
\"o\"\"*\"arm_lms_norm_init_f32.c
\"o\"\"*\"arm_lms_norm_init_q15.c
\"o\"\"*\"arm_lms_norm_init_q31.c
\"o\"\"*\"arm_lms_norm_q15.c
\"o\"\"*\"arm_lms_norm_q31.c
\"o\"\"*\"arm_lms_q15.c
\"o\"\"*\"arm_lms_q31.c
\"o\"\"*\"arm_mat_add_f32.c
\"o\"\"*\"arm_mat_add_q15.c
\"o\"\"*\"arm_mat_add_q31.c
\"o\"\"*\"arm_mat_init_f32.c
\"o\"\"*\"arm_mat_init_q15.c
\"o\"\"*\"arm_mat_init_q31.c
\"o\"\"*\"arm_mat_inverse_f32.c
\"o\"\"*\"arm_mat_mult_f32.c
\"o\"\"*\"arm_mat_mult_fast_q15.c
\"o\"\"*\"arm_mat_mult_fast_q31.c
\"o\"\"*\"arm_mat_mult_q15.c
\"o\"\"*\"arm_mat_mult_q31.c
\"o\"\"*\"arm_mat_scale_f32.c
\"o\"\"*\"arm_mat_scale_q15.c
\"o\"\"*\"arm_mat_scale_q31.c
\"o\"\"*\"arm_mat_sub_f32.c
\"o\"\"*\"arm_mat_sub_q15.c
\"o\"\"*\"arm_mat_sub_q31.c
\"o\"\"*\"arm_mat_trans_f32.c
\"o\"\"*\"arm_mat_trans_q15.c
\"o\"\"*\"arm_mat_trans_q31.c
\"o\"\"*\"arm_math.h
\"o\"\"*\"arm_matrix_example_f32.c
\"o\"\"*\"arm_max_f32.c
\"o\"\"*\"arm_max_q15.c
\"o\"\"*\"arm_max_q31.c
\"o\"\"*\"arm_max_q7.c
\"o\"\"*\"arm_mean_f32.c
\"o\"\"*\"arm_mean_q15.c
\"o\"\"*\"arm_mean_q31.c
\"o\"\"*\"arm_mean_q7.c
\"o\"\"*\"arm_min_f32.c
\"o\"\"*\"arm_min_q15.c
\"o\"\"*\"arm_min_q31.c
\"o\"\"*\"arm_min_q7.c
\"o\"\"*\"arm_mult_f32.c
\"o\"\"*\"arm_mult_q15.c
\"o\"\"*\"arm_mult_q31.c
\"o\"\"*\"arm_mult_q7.c
\"o\"\"*\"arm_negate_f32.c
\"o\"\"*\"arm_negate_q15.c
\"o\"\"*\"arm_negate_q31.c
\"o\"\"*\"arm_negate_q7.c
\"o\"\"*\"arm_offset_f32.c
\"o\"\"*\"arm_offset_q15.c
\"o\"\"*\"arm_offset_q31.c
\"o\"\"*\"arm_offset_q7.c
\"o\"\"*\"arm_pid_init_f32.c
\"o\"\"*\"arm_pid_init_q15.c
\"o\"\"*\"arm_pid_init_q31.c
\"o\"\"*\"arm_pid_reset_f32.c
\"o\"\"*\"arm_pid_reset_q15.c
\"o\"\"*\"arm_pid_reset_q31.c
\"o\"\"*\"arm_power_f32.c
\"o\"\"*\"arm_power_q15.c
\"o\"\"*\"arm_power_q31.c
\"o\"\"*\"arm_power_q7.c
\"o\"\"*\"arm_q15_to_float.c
\"o\"\"*\"arm_q15_to_q31.c
\"o\"\"*\"arm_q15_to_q7.c
\"o\"\"*\"arm_q31_to_float.c
\"o\"\"*\"arm_q31_to_q15.c
\"o\"\"*\"arm_q31_to_q7.c
\"o\"\"*\"arm_q7_to_float.c
\"o\"\"*\"arm_q7_to_q15.c
\"o\"\"*\"arm_q7_to_q31.c
\"o\"\"*\"arm_rfft_f32.c
\"o\"\"*\"arm_rfft_fast_f32.c
\"o\"\"*\"arm_rfft_fast_init_f32.c
\"o\"\"*\"arm_rfft_init_f32.c
\"o\"\"*\"arm_rfft_init_q15.c
\"o\"\"*\"arm_rfft_init_q31.c
\"o\"\"*\"arm_rfft_q15.c
\"o\"\"*\"arm_rfft_q31.c
\"o\"\"*\"arm_rms_f32.c
\"o\"\"*\"arm_rms_q15.c
\"o\"\"*\"arm_rms_q31.c
\"o\"\"*\"arm_scale_f32.c
\"o\"\"*\"arm_scale_q15.c
\"o\"\"*\"arm_scale_q31.c
\"o\"\"*\"arm_scale_q7.c
\"o\"\"*\"arm_shift_q15.c
\"o\"\"*\"arm_shift_q31.c
\"o\"\"*\"arm_shift_q7.c
\"o\"\"*\"arm_signal_converge_data.c
\"o\"\"*\"arm_signal_converge_example_f32.c
\"o\"\"*\"arm_sin_cos_example_f32.c
\"o\"\"*\"arm_sin_cos_f32.c
\"o\"\"*\"arm_sin_cos_q31.c
\"o\"\"*\"arm_sin_f32.c
\"o\"\"*\"arm_sin_q15.c
\"o\"\"*\"arm_sin_q31.c
\"o\"\"*\"arm_sqrt_q15.c
\"o\"\"*\"arm_sqrt_q31.c
\"o\"\"*\"arm_std_f32.c
\"o\"\"*\"arm_std_q15.c
\"o\"\"*\"arm_std_q31.c
\"o\"\"*\"arm_sub_f32.c
\"o\"\"*\"arm_sub_q15.c
\"o\"\"*\"arm_sub_q31.c
\"o\"\"*\"arm_sub_q7.c
\"o\"\"*\"arm_var_f32.c
\"o\"\"*\"arm_var_q15.c
\"o\"\"*\"arm_var_q31.c
\"o\"\"*\"arm_variance_example_f32.c
\"o\"\"*\"math_helper.c
\"o\"\"*\"math_helper.h
\"o\"\"*\"system_ARMCM0.cCMSIS Device System Source File for ARMCM0 Device Series
\"o\"\"*\"system_ARMCM3.cCMSIS Device System Source File for ARMCM3 Device Series
\"\\\"\"*\"system_ARMCM4.cCMSIS Device System Source File for ARMCM4 Device Series
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- a -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x62.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x65.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- e -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x66.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x69.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x6b.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x6c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- l -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x6d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x6e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- n -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x6f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- o -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x70.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- p -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x72.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- r -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x73.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x74.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_0x78.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all struct and union fields with links to the structures/unions they belong to:
\n\n
- x -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_dup.js",
    "content": "var functions_dup =\n[\n    [ \"a\", \"functions.html\", null ],\n    [ \"b\", \"functions_0x62.html\", null ],\n    [ \"e\", \"functions_0x65.html\", null ],\n    [ \"f\", \"functions_0x66.html\", null ],\n    [ \"i\", \"functions_0x69.html\", null ],\n    [ \"k\", \"functions_0x6b.html\", null ],\n    [ \"l\", \"functions_0x6c.html\", null ],\n    [ \"m\", \"functions_0x6d.html\", null ],\n    [ \"n\", \"functions_0x6e.html\", null ],\n    [ \"o\", \"functions_0x6f.html\", null ],\n    [ \"p\", \"functions_0x70.html\", null ],\n    [ \"r\", \"functions_0x72.html\", null ],\n    [ \"s\", \"functions_0x73.html\", null ],\n    [ \"t\", \"functions_0x74.html\", null ],\n    [ \"x\", \"functions_0x78.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars.js",
    "content": "var functions_vars =\n[\n    [ \"a\", \"functions_vars.html\", null ],\n    [ \"b\", \"functions_vars_0x62.html\", null ],\n    [ \"e\", \"functions_vars_0x65.html\", null ],\n    [ \"f\", \"functions_vars_0x66.html\", null ],\n    [ \"i\", \"functions_vars_0x69.html\", null ],\n    [ \"k\", \"functions_vars_0x6b.html\", null ],\n    [ \"l\", \"functions_vars_0x6c.html\", null ],\n    [ \"m\", \"functions_vars_0x6d.html\", null ],\n    [ \"n\", \"functions_vars_0x6e.html\", null ],\n    [ \"o\", \"functions_vars_0x6f.html\", null ],\n    [ \"p\", \"functions_vars_0x70.html\", null ],\n    [ \"r\", \"functions_vars_0x72.html\", null ],\n    [ \"s\", \"functions_vars_0x73.html\", null ],\n    [ \"t\", \"functions_vars_0x74.html\", null ],\n    [ \"x\", \"functions_vars_0x78.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x62.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x65.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x66.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x69.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x6b.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x6c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x6d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x6e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- n -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x6f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x70.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- p -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x72.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x73.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x74.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/functions_vars_0x78.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- _ -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x61.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- a -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x62.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- b -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x63.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- c -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x64.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- d -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x65.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- e -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x66.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- f -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x67.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- g -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x69.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- i -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x6c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- l -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x6d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- m -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x6e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- n -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x6f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- o -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x70.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- p -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x71.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- q -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x72.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- r -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x73.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- s -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x74.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- t -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x75.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- u -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x76.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- v -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x77.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- w -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_0x78.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
\n\n
- x -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_defs.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- _ -
\n\n\n
- a -
\n\n\n
- b -
\n\n\n
- d -
\n\n\n
- i -
\n\n\n
- m -
\n\n\n
- n -
\n\n\n
- p -
\n\n\n
- s -
\n\n\n
- t -
\n\n\n
- u -
\n\n\n
- x -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:59 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_enum.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_eval.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:59 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- a -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x62.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- b -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x63.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- c -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x64.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- d -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x66.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- f -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x67.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x69.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- i -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x6c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- l -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x6d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- m -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x6e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- n -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x6f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- o -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x70.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- p -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x71.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
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\n
\n
\n  
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\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- q -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x72.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
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\n
\n
\n  
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\n    
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\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- r -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x73.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
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\n
\n
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\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n\n
- s -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x74.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
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\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_func_0x76.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_type.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
\n  
\n    
\n      
\n    
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\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n \n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
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\n
\n
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\n  
\n
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\n\n\n\n\n
\n\n
\n\n
\n \n\n
- a -
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x62.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n  
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\n
\n
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\n  
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\n
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\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x63.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
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\n
\n
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x64.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x65.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x66.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x67.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x69.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x6c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x6d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x6e.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x6f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x72.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x73.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x74.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x76.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x77.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/globals_vars_0x78.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_abs.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Absolute Value\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Vector Absolute Value
Basic Math Functions
  
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\nFunctions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Floating-point vector absolute value.  More...
 
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Q15 vector absolute value.  More...
 
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Q31 vector absolute value.  More...
 
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Q7 vector absolute value.  More...
 
\n
Description
\n
Computes the absolute value of a vector on an element-by-element basis.
\n
        \n    pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.        \n
The functions support in-place computation allowing the source and destination pointers to reference the same memory buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_abs_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 
\n  
\n
\n
Returns
none. 
\n
Examples: 
arm_signal_converge_example_f32.c.
\n
\n
References blockSize.
\n\n
Referenced by main().
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void arm_abs_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 
\n\n
References __SIMD32_CONST, and blockSize.
\n\n
\n
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void arm_abs_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 
\n\n
References blockSize.
\n\n
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void arm_abs_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 
\n  
\n
\n
Returns
none.
\n
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 
\n\n
References blockSize.
\n\n
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_abs.js",
    "content": "var group___basic_abs =\n[\n    [ \"arm_abs_f32\", \"group___basic_abs.html#ga421b6275f9d35f50286c0ff3beceff02\", null ],\n    [ \"arm_abs_q15\", \"group___basic_abs.html#ga39f92964c9b649ba252e26ebe7b95594\", null ],\n    [ \"arm_abs_q31\", \"group___basic_abs.html#ga59eafcdcdb52da60d37f20aec6ff4577\", null ],\n    [ \"arm_abs_q7\", \"group___basic_abs.html#gadc30985e33fbf96802a5a7954dece3b1\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_add.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Addition\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
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\nFunctions  
\n  
\n
Vector Addition
Basic Math Functions
  
\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector addition.  More...
 
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector addition.  More...
 
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector addition.  More...
 
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector addition.  More...
 
\n
Description
\n
Element-by-element addition of two vectors.
\n
        \n    pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        \n
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
\n
Function Documentation
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void arm_add_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none. 
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Examples: 
arm_dotproduct_example_f32.c, and arm_sin_cos_example_f32.c.
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References blockSize.
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Referenced by main().
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void arm_add_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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References __SIMD32, and blockSize.
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void arm_add_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 
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References blockSize, and clip_q63_to_q31().
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void arm_add_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 
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References __SIMD32, and blockSize.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_add.js",
    "content": "var group___basic_add =\n[\n    [ \"arm_add_f32\", \"group___basic_add.html#ga6a904a547413b10565dd1d251c6bafbd\", null ],\n    [ \"arm_add_q15\", \"group___basic_add.html#gabb51285a41f511670bbff62fc0e1bf62\", null ],\n    [ \"arm_add_q31\", \"group___basic_add.html#ga24d6c3f7f8b9fae4847c0c3f26a39a3b\", null ],\n    [ \"arm_add_q7\", \"group___basic_add.html#gaed633f415a7840a66861debca2dfb96b\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_mult.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Multiplication\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Vector Multiplication
Basic Math Functions
  
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\nFunctions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector multiplication.  More...
 
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector multiplication.  More...
 
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector multiplication.  More...
 
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector multiplication.  More...
 
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Description
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Element-by-element multiplication of two vectors.
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        \n    pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        \n
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
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Function Documentation
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void arm_mult_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none. 
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Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.
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References blockSize.
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Referenced by arm_dct4_f32(), and main().
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void arm_mult_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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References __SIMD32, and blockSize.
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Referenced by arm_dct4_q15().
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void arm_mult_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 
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References blockSize, and clip_q63_to_q31().
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Referenced by arm_dct4_q31().
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void arm_mult_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 
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References __PACKq7, __SIMD32, and blockSize.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_mult.js",
    "content": "var group___basic_mult =\n[\n    [ \"arm_mult_f32\", \"group___basic_mult.html#gaca3f0b8227da431ab29225b88888aa32\", null ],\n    [ \"arm_mult_q15\", \"group___basic_mult.html#gafb0778d27ed98a2a6f2ecb7d48cc8c75\", null ],\n    [ \"arm_mult_q31\", \"group___basic_mult.html#ga3528c0f54a0607acc603f0490d3ca6c6\", null ],\n    [ \"arm_mult_q7\", \"group___basic_mult.html#ga16677275ed83ff0878da531e875c27ef\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_sub.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Subtraction\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Vector Subtraction
Basic Math Functions
  
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void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
 Floating-point vector subtraction.  More...
 
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
 Q15 vector subtraction.  More...
 
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
 Q31 vector subtraction.  More...
 
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
 Q7 vector subtraction.  More...
 
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Description
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Element-by-element subtraction of two vectors.
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        \n    pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        \n
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
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Function Documentation
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void arm_sub_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none. 
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Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.
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References blockSize.
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Referenced by main().
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void arm_sub_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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References __SIMD32, and blockSize.
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void arm_sub_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 
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References blockSize, and clip_q63_to_q31().
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void arm_sub_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
q7_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 
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References __SIMD32, and blockSize.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___basic_sub.js",
    "content": "var group___basic_sub =\n[\n    [ \"arm_sub_f32\", \"group___basic_sub.html#ga7f975a472de286331134227c08aad826\", null ],\n    [ \"arm_sub_q15\", \"group___basic_sub.html#ga997a8ee93088d15bda23c325d455b588\", null ],\n    [ \"arm_sub_q31\", \"group___basic_sub.html#ga28aa6908d092752144413e21933dc878\", null ],\n    [ \"arm_sub_q7\", \"group___basic_sub.html#gab09941de7dfeb247e5c29b406a435fcc\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___bilinear_interpolate.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Bilinear Interpolation\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Bilinear Interpolation
Interpolation Functions
  
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static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
 Floating-point bilinear interpolation.  More...
 
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
 Q31 bilinear interpolation.  More...
 
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
 Q15 bilinear interpolation.  More...
 
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)
 Q7 bilinear interpolation.  More...
 
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Description
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Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. The underlying function f(x, y) is sampled on a regular grid and the interpolation process determines values between the grid points. Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. Bilinear interpolation is often used in image processing to rescale images. The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
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Algorithm 
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The instance structure used by the bilinear interpolation functions describes a two dimensional data table. For floating-point, the instance structure is defined as: 
\n  typedef struct\n  {\n    uint16_t numRows;\n    uint16_t numCols;\n    float32_t *pData;\n} arm_bilinear_interp_instance_f32;\n
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where numRows specifies the number of rows in the table; numCols specifies the number of columns in the table; and pData points to an array of size numRows*numCols values. The data table pTable is organized in row order and the supplied data values fall on integer indexes. That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
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Let (x, y) specify the desired interpolation point. Then define: 
\n    XF = floor(x)\n    YF = floor(y)\n
 
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The interpolated output point is computed as: 
\n f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\n          + f(XF+1, YF) * (x-XF)*(1-(y-YF))\n          + f(XF, YF+1) * (1-(x-XF))*(y-YF)\n          + f(XF+1, YF+1) * (x-XF)*(y-YF)\n
 Note that the coordinates (x, y) contain integer and fractional components. The integer components specify which portion of the table to use while the fractional components control the interpolation processor.
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if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
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Function Documentation
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static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 * S, 
float32_t X, 
float32_t Y 
)
\n  		\nstatic  
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Parameters
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[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate. 
[in]Yinterpolation coordinate. 
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Returns
out interpolated value. 
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References arm_bilinear_interp_instance_f32::numCols, arm_bilinear_interp_instance_f32::numRows, and arm_bilinear_interp_instance_f32::pData.
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static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 * S, 
q31_t X, 
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Parameters
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[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 
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Returns
out interpolated value. 
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References arm_bilinear_interp_instance_q15::numCols, arm_bilinear_interp_instance_q15::numRows, and arm_bilinear_interp_instance_q15::pData.
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static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 * S, 
q31_t X, 
q31_t Y 
)
\n  		\nstatic  
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Parameters
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[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 
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Returns
out interpolated value. 
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References arm_bilinear_interp_instance_q31::numCols, arm_bilinear_interp_instance_q31::numRows, and arm_bilinear_interp_instance_q31::pData.
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static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 * S, 
q31_t X, 
q31_t Y 
)
\n  		\nstatic  
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Parameters
\n  \n    \n    \n    \n  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 
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Returns
out interpolated value. 
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References arm_bilinear_interp_instance_q7::numCols, arm_bilinear_interp_instance_q7::numRows, and arm_bilinear_interp_instance_q7::pData.
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___bilinear_interpolate.js",
    "content": "var group___bilinear_interpolate =\n[\n    [ \"arm_bilinear_interp_f32\", \"group___bilinear_interpolate.html#gab49a4c0f64854903d996d01ba38f711a\", null ],\n    [ \"arm_bilinear_interp_q15\", \"group___bilinear_interpolate.html#gaa8dffbc2a01bb7accf231384498ec85e\", null ],\n    [ \"arm_bilinear_interp_q31\", \"group___bilinear_interpolate.html#ga202a033c8a2ad3678b136f93153b6d13\", null ],\n    [ \"arm_bilinear_interp_q7\", \"group___bilinear_interpolate.html#gade8db9706a3ae9ad03b2750a239d2ee6\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Biquad Cascade IIR Filters Using Direct Form I Structure\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Biquad Cascade IIR Filters Using Direct Form I Structure
Filtering Functions
  
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\nFunctions
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
 Initialization function for the Q15 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
 Initialization function for the Q31 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 Biquad cascade filter.  More...
 
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 Biquad cascade filter.  More...
 
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Description
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This set of functions implements arbitrary order recursive (IIR) filters. The filters are implemented as a cascade of second order Biquad sections. The functions support Q15, Q31 and floating-point data types. Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
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The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.
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Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
    \n    y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 
\n\"Biquad.gif\"/\n
\nSingle Biquad filter stage
\n Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
    \n    y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    \n
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
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Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 
\n\"BiquadCascade.gif\"/\n
\n8th order filter using a cascade of Biquad stages
\n A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
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The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
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The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed, the coefficients are untouched.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.
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Init Functions 
There is also an associated initialization function for each data type. The initialization function performs following operations:
    \n
  • Sets the values of the internal structure fields.
    • \n
  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numStages, pCoeffs, pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
    \n    arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    \n    arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    \n    arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    \n
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied.
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Fixed-Point Behavior 
Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. Following issues must be considered:
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  • Scaling of coefficients
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  • Filter gain
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  • Overflow and saturation
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Scaling of coefficients:  Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift which allow the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 
\n\"BiquadPostshift.gif\"/\n
\nFixed-point Biquad with shift by postShift bits after accumulator
\n This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
    \n   {1.5, -0.8, 1.2, 1.6, -0.9}    \n
 set the pCoeffs array to: 
    \n   {0.75, -0.4, 0.6, 0.8, -0.45}    \n
 and set postShift=1
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Filter gain:  The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
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Overflow and saturation:  For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. 
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Function Documentation
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void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none. 
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References blockSize, arm_biquad_casd_df1_inst_f32::numStages, arm_biquad_casd_df1_inst_f32::pCoeffs, and arm_biquad_casd_df1_inst_f32::pState.
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void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.
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Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure. 
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References __SIMD32, arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.
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void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function arm_biquad_cascade_df1_init_q31() to initialize filter structure.
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Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure. 
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References arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.
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void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 * S, 
uint8_t numStages, 
float32_t * pCoeffs, 
float32_t * pState 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients array. 
[in]*pStatepoints to the state array. 
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Returns
none
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Coefficient and State Ordering:
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The coefficients are stored in the array pCoeffs in the following order: 
    \n    {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n
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where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.
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The pState is a pointer to state array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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References arm_biquad_casd_df1_inst_f32::numStages, arm_biquad_casd_df1_inst_f32::pCoeffs, and arm_biquad_casd_df1_inst_f32::pState.
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void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 * S, 
uint8_t numStages, 
q15_t * pCoeffs, 
q15_t * pState, 
int8_t postShift 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied to the accumulator result. Varies according to the coefficients format 
\n  
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Returns
none
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Coefficient and State Ordering:
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The coefficients are stored in the array pCoeffs in the following order: 
    \n    {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    \n
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 6*numStages values. The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.
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The state variables are stored in the array pState. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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References arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.
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void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 * S, 
uint8_t numStages, 
q31_t * pCoeffs, 
q31_t * pState, 
int8_t postShift 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format 
\n  
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Returns
none
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Coefficient and State Ordering:
\n
The coefficients are stored in the array pCoeffs in the following order: 
    \n    {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.
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The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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Examples: 
arm_graphic_equalizer_example_q31.c.
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References arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.
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Referenced by main().
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void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. Finally, the result is saturated to 1.15 format.
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Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 
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References __SIMD32, arm_biquad_casd_df1_inst_q15::numStages, arm_biquad_casd_df1_inst_q15::pCoeffs, arm_biquad_casd_df1_inst_q15::postShift, and arm_biquad_casd_df1_inst_q15::pState.
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void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.
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Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 
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Examples: 
arm_graphic_equalizer_example_q31.c.
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References blockSize, arm_biquad_casd_df1_inst_q31::numStages, arm_biquad_casd_df1_inst_q31::pCoeffs, arm_biquad_casd_df1_inst_q31::postShift, and arm_biquad_casd_df1_inst_q31::pState.
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Referenced by main().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1__32x64.html",
    "content": "\n\n\n\n\nCMSIS-DSP: High Precision Q31 Biquad Cascade Filter\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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High Precision Q31 Biquad Cascade Filter
Filtering Functions
  
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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
 
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 
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Description
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This function implements a high precision Biquad cascade filter which operates on Q31 data values. The filter coefficients are in 1.31 format and the state variables are in 1.63 format. The double precision state variables reduce quantization noise in the filter and provide a cleaner output. These filters are particularly useful when implementing filters in which the singularities are close to the unit circle. This is common for low pass or high pass filters with very low cutoff frequencies.
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The function operates on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize Q31 values.
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Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
    \n    y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    \n
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 
\n\"Biquad.gif\"/\n
\nSingle Biquad filter stage
\n Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
    \n    y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    \n
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
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Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 
\n\"BiquadCascade.gif\"/\n
\n8th order filter using a cascade of Biquad stages
\n A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
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The pState points to state variables array . Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. The state variables are arranged in the array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
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The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values of data in 1.63 format. The state variables are updated after each block of data is processed; the coefficients are untouched.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
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Init Function 
There is also an associated initialization function which performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the filter instance structure use 
    \n    arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    \n
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below. 
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Fixed-Point Behavior 
Care must be taken while using Biquad Cascade 32x64 filter function. Following issues must be considered:
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  • Scaling of coefficients
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  • Filter gain
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  • Overflow and saturation
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Filter coefficients are represented as fractional values and restricted to lie in the range [-1 +1). The processing function has an additional scaling parameter postShift which allows the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 
\n\"BiquadPostshift.gif\"/\n
\nFixed-point Biquad with shift by postShift bits after accumulator
\n This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
    \n   {1.5, -0.8, 1.2, 1.6, -0.9}    \n
 set the Coefficient array to: 
    \n   {0.75, -0.4, 0.6, 0.8, -0.45}    \n
 and set postShift=1
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The second thing to keep in mind is the gain through the filter. The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
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The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. This is described in the function specific documentation below. 
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Function Documentation
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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 * S, 
uint8_t numStages, 
q31_t * pCoeffs, 
q63_t * pState, 
uint8_t postShift 
)
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Parameters
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[in,out]*Spoints to an instance of the high precision Q31 Biquad cascade filter structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format. 
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Returns
none
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Coefficient and State Ordering:
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The coefficients are stored in the array pCoeffs in the following order: 
    \n    {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.
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The pState points to state variables array and size of each state variable is 1.63 format. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the state array as: 
    \n    {x[n-1], x[n-2], y[n-1], y[n-2]}    \n
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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Examples: 
arm_graphic_equalizer_example_q31.c.
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References arm_biquad_cas_df1_32x64_ins_q31::numStages, arm_biquad_cas_df1_32x64_ins_q31::pCoeffs, arm_biquad_cas_df1_32x64_ins_q31::postShift, and arm_biquad_cas_df1_32x64_ins_q31::pState.
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Referenced by main().
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void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the high precision Q31 Biquad cascade filter. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.
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Two related functions are provided in the CMSIS DSP library. arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. 
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Examples: 
arm_graphic_equalizer_example_q31.c.
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References blockSize, mult32x64(), arm_biquad_cas_df1_32x64_ins_q31::numStages, arm_biquad_cas_df1_32x64_ins_q31::pCoeffs, arm_biquad_cas_df1_32x64_ins_q31::postShift, and arm_biquad_cas_df1_32x64_ins_q31::pState.
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Referenced by main().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f1__32x64.js",
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f2_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
Filtering Functions
  
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LOW_OPTIMIZATION_ENTER void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point transposed direct form II Biquad cascade filter.  More...
 
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Description
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This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. The filters are implemented as a cascade of second order Biquad sections. These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. Only floating-point data is supported.
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This function operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.
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Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
       \n   y[n] = b0 * x[n] + d1       \n   d1 = b1 * x[n] + a1 * y[n] + d2       \n   d2 = b2 * x[n] + a2 * y[n]       \n
 where d1 and d2 represent the two state values.
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A Biquad filter using a transposed Direct Form II structure is shown below. 
\n\"BiquadDF2Transposed.gif\"/\n
\nSingle transposed Direct Form II Biquad
\n Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools flip the sign of the feedback coefficients: 
       \n   y[n] = b0 * x[n] + d1;       \n   d1 = b1 * x[n] - a1 * y[n] + d2;       \n   d2 = b2 * x[n] - a2 * y[n];       \n
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
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Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
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pState points to the state variable array. Each Biquad stage has 2 state variables d1 and d2. The state variables are arranged in the pState array as: 
       \n    {d11, d12, d21, d22, ...}       \n
 where d1x refers to the state variables for the first Biquad and d2x refers to the state variables for the second Biquad. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched.
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The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. That is why the Direct Form I structure supports Q15 and Q31 data types. The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
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Init Functions 
There is also an associated initialization function. The initialization function performs following operations:
    \n
  • Sets the values of the internal structure fields.
    • \n
  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numStages, pCoeffs, pState. Also set all of the values in pState to zero.
    • \n
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the instance structure use 
       \n    arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       \n
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer. pCoeffs is the address of the coefficient buffer; 
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Function Documentation
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LOW_OPTIMIZATION_ENTER void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the filter data structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 
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none. 
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References blockSize, arm_biquad_cascade_df2T_instance_f32::numStages, arm_biquad_cascade_df2T_instance_f32::pCoeffs, and arm_biquad_cascade_df2T_instance_f32::pState.
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void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 * S, 
uint8_t numStages, 
float32_t * pCoeffs, 
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[in,out]*Spoints to an instance of the filter data structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
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Coefficient and State Ordering: 
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The coefficients are stored in the array pCoeffs in the following order: 
    \n    {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    \n
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where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.
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The pState is a pointer to state array. Each Biquad stage has 2 state variables d1, and d2. The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 
\n\n
References arm_biquad_cascade_df2T_instance_f32::numStages, arm_biquad_cascade_df2T_instance_f32::pCoeffs, and arm_biquad_cascade_df2T_instance_f32::pState.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___biquad_cascade_d_f2_t.js",
    "content": "var group___biquad_cascade_d_f2_t =\n[\n    [ \"arm_biquad_cascade_df2T_f32\", \"group___biquad_cascade_d_f2_t.html#ga114f373fbc16a314e9f293c7c7649c7f\", null ],\n    [ \"arm_biquad_cascade_df2T_init_f32\", \"group___biquad_cascade_d_f2_t.html#ga70eaddf317a4a8bde6bd6a97df67fedd\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___c_f_f_t___c_i_f_f_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex FFT Tables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nVariables  
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Complex FFT Tables
Transform Functions
  
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\nVariables
const uint16_t armBitRevTable [1024]
 
const float32_t twiddleCoef_16 [32]
 
const float32_t twiddleCoef_32 [64]
 
const float32_t twiddleCoef_64 [128]
 
const float32_t twiddleCoef_128 [256]
 
const float32_t twiddleCoef_256 [512]
 
const float32_t twiddleCoef_512 [1024]
 
const float32_t twiddleCoef_1024 [2048]
 
const float32_t twiddleCoef_2048 [4096]
 
const float32_t twiddleCoef_4096 [8192]
 
const q31_t twiddleCoefQ31 [6144]
 
const q15_t ALIGN4 twiddleCoefQ15 [6144]
 
\n
Description
\n
Variable Documentation
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const uint16_t armBitRevTable[1024]
\n
\n
Pseudo code for Generation of Bit reversal Table is 
\n
for(l=1;l <= N/4;l++)    \n{    \n  for(i=0;i<logN2;i++)    \n  {     \n    a[i]=l&(1<<i);    \n  }    \n  for(j=0; j<logN2; j++)    \n  {    \n    if (a[j]!=0)    \n    y[l]+=(1<<((logN2-1)-j));    \n  }    \n  y[l] = y[l] >> 1;    \n } 
 
\n
where N = 4096 logN2 = 12 
\n
N is the maximum FFT Size supported 
\n\n
Referenced by arm_cfft_radix2_init_f32(), arm_cfft_radix2_init_q15(), arm_cfft_radix2_init_q31(), arm_cfft_radix4_init_f32(), arm_cfft_radix4_init_q15(), and arm_cfft_radix4_init_q31().
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const float32_t twiddleCoef_1024[2048]
\n
\n
Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
\n
Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_128[256]
\n
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Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
\n
Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_16[32]
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Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_2048[4096]
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Example code for Floating-point Twiddle factors Generation: 
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for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
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where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_256[512]
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Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_32[64]
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Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_4096[8192]
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Example code for Floating-point Twiddle factors Generation: 
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for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
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where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_512[1024]
\n
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Example code for Floating-point Twiddle factors Generation: 
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for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
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where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const float32_t twiddleCoef_64[128]
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Example code for Floating-point Twiddle factors Generation: 
\n
for(i = 0; i< N/; i++)    \n{    \n      twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
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where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are in interleaved fashion 
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const q15_t ALIGN4 twiddleCoefQ15[6144]
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Example code for Q15 Twiddle factors Generation:: 
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for(i = 0; i< 3N/4; i++)    \n{    \n      twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);    \n      twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
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where N = 4096 and PI = 3.14159265358979 
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Cos and Sin values are interleaved fashion 
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Convert Floating point to Q15(Fixed point 1.15): round(twiddleCoefQ15(i) * pow(2, 15)) 
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Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix4_init_q15().
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const q31_t twiddleCoefQ31[6144]
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Example code for Q31 Twiddle factors Generation:: 
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for(i = 0; i< 3N/4; i++)    \n{    \n   twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    \n   twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    \n} 
 
\n
where N = 4096 and PI = 3.14159265358979 
\n
Cos and Sin values are interleaved fashion 
\n
Convert Floating point to Q31(Fixed point 1.31): round(twiddleCoefQ31(i) * pow(2, 31)) 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix4_init_q31().
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___c_f_f_t___c_i_f_f_t.js",
    "content": "var group___c_f_f_t___c_i_f_f_t =\n[\n    [ \"armBitRevTable\", \"group___c_f_f_t___c_i_f_f_t.html#gae247e83ad50d474107254e25b36ad42b\", null ],\n    [ \"twiddleCoef_1024\", \"group___c_f_f_t___c_i_f_f_t.html#ga27c056eb130a4333d1cc5dd43ec738b1\", null ],\n    [ \"twiddleCoef_128\", \"group___c_f_f_t___c_i_f_f_t.html#ga948433536dafaac1381decfccf4e2d9c\", null ],\n    [ \"twiddleCoef_16\", \"group___c_f_f_t___c_i_f_f_t.html#gae75e243ec61706427314270f222e0c8e\", null ],\n    [ \"twiddleCoef_2048\", \"group___c_f_f_t___c_i_f_f_t.html#ga23e7f30421a7905b21c2015429779633\", null ],\n    [ \"twiddleCoef_256\", \"group___c_f_f_t___c_i_f_f_t.html#gafe813758a03a798e972359a092315be4\", null ],\n    [ \"twiddleCoef_32\", \"group___c_f_f_t___c_i_f_f_t.html#ga78a72c85d88185de98050c930cfc76e3\", null ],\n    [ \"twiddleCoef_4096\", \"group___c_f_f_t___c_i_f_f_t.html#gae0182d1dd3b2f21aad4e38a815a0bd40\", null ],\n    [ \"twiddleCoef_512\", \"group___c_f_f_t___c_i_f_f_t.html#gad8830f0c068ab2cc19f2f87d220fa148\", null ],\n    [ \"twiddleCoef_64\", \"group___c_f_f_t___c_i_f_f_t.html#ga4f3c6d98c7e66393b4ef3ac63746e43d\", null ],\n    [ \"twiddleCoefQ15\", \"group___c_f_f_t___c_i_f_f_t.html#ga39e78f61a5f4bd5cfb577b11099a2c7f\", null ],\n    [ \"twiddleCoefQ31\", \"group___c_f_f_t___c_i_f_f_t.html#ga80f8f038faf4289eebc59dd5fa010993\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___class_marks.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Class Marks Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Class Marks Example
Examples
  
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Description:
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Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance and Matrix functions to calculate statistical values of marks obtained in a class.
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Note
This example also demonstrates the usage of static initialization.
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Variables Description:
\n
    \n
  • testMarks_f32 points to the marks scored by 20 students in 4 subjects 
    • \n
  • max_marks Maximum of all marks 
    • \n
  • min_marks Minimum of all marks 
    • \n
  • mean Mean of all marks 
    • \n
  • var Variance of the marks 
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  • std Standard deviation of the marks 
    • \n
  • numStudents Total number of students in the class
    • \n
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CMSIS DSP Software Library Functions Used:
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\n
 Refer  arm_class_marks_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___cmplx_by_cmplx_mult.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex-by-Complex Multiplication\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Complex-by-Complex Multiplication
Complex Math Functions
  
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\nFunctions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
 Floating-point complex-by-complex multiplication.  More...
 
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
 Q15 complex-by-complex multiplication.  More...
 
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
 Q31 complex-by-complex multiplication.  More...
 
\n
Description
\n
Multiplies a complex vector by another complex vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values.
\n
The underlying algorithm is used:
\n
        \nfor(n=0; n<numSamples; n++) {        \n    pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];        \n    pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];        \n}        \n
There are separate functions for floating-point, Q15, and Q31 data types. 
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Function Documentation
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void arm_cmplx_mult_cmplx_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
float32_t * pDst, 
uint32_t numSamples 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 
\n  
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Returns
none. 
\n
Examples: 
arm_convolution_example_f32.c.
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Referenced by main().
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void arm_cmplx_mult_cmplx_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
q15_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 
\n  
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Returns
none.
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Scaling and Overflow Behavior: 
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The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 
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void arm_cmplx_mult_cmplx_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
q31_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 
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Referenced by arm_dct4_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___cmplx_by_cmplx_mult.js",
    "content": "var group___cmplx_by_cmplx_mult =\n[\n    [ \"arm_cmplx_mult_cmplx_f32\", \"group___cmplx_by_cmplx_mult.html#ga14b47080054a1ba1250a86805be1ff6b\", null ],\n    [ \"arm_cmplx_mult_cmplx_q15\", \"group___cmplx_by_cmplx_mult.html#ga67e96abfc9c3e30efb70a2ec9d0fe7e8\", null ],\n    [ \"arm_cmplx_mult_cmplx_q31\", \"group___cmplx_by_cmplx_mult.html#ga1829e50993a90742de225a0ce4213838\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___cmplx_by_real_mult.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex-by-Real Multiplication\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Complex-by-Real Multiplication
Complex Math Functions
  
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\nFunctions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
 Floating-point complex-by-real multiplication.  More...
 
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
 Q15 complex-by-real multiplication.  More...
 
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
 Q31 complex-by-real multiplication.  More...
 
\n
Description
\n
Multiplies a complex vector by a real vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values while the real array has a total of numSamples real values.
\n
The underlying algorithm is used:
\n
        \nfor(n=0; n<numSamples; n++) {        \n    pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];        \n    pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];        \n}        \n
There are separate functions for floating-point, Q15, and Q31 data types. 
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Function Documentation
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void arm_cmplx_mult_real_f32 (float32_t * pSrcCmplx, 
float32_t * pSrcReal, 
float32_t * pCmplxDst, 
uint32_t numSamples 
)
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Parameters
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[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 
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Returns
none. 
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void arm_cmplx_mult_real_q15 (q15_t * pSrcCmplx, 
q15_t * pSrcReal, 
q15_t * pCmplxDst, 
uint32_t numSamples 
)
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Parameters
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[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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References __SIMD32.
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void arm_cmplx_mult_real_q31 (q31_t * pSrcCmplx, 
q31_t * pSrcReal, 
q31_t * pCmplxDst, 
uint32_t numSamples 
)
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Parameters
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[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 
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References clip_q63_to_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___cmplx_by_real_mult.js",
    "content": "var group___cmplx_by_real_mult =\n[\n    [ \"arm_cmplx_mult_real_f32\", \"group___cmplx_by_real_mult.html#ga9c18616f56cb4d3c0889ce0b339221ca\", null ],\n    [ \"arm_cmplx_mult_real_q15\", \"group___cmplx_by_real_mult.html#ga3bd8889dcb45980e1d3e53344df54e85\", null ],\n    [ \"arm_cmplx_mult_real_q31\", \"group___cmplx_by_real_mult.html#ga715e4bb8e945b8ca51ec5237611697ce\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___complex_f_f_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex FFT Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Complex FFT Functions
Transform Functions
  
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\nFunctions
void arm_cfft_f32 (const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Processing function for the floating-point complex FFT.  More...
 
void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc)
 Radix-2 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc)
 Processing function for the fixed-point CFFT/CIFFT.  More...
 
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
 Processing function for the floating-point Radix-4 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the floating-point CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q15 CFFT/CIFFT.  More...
 
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
 Initialization function for the Q31 CFFT/CIFFT.  More...
 
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
 Processing function for the Q15 CFFT/CIFFT.  More...
 
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
 Processing function for the Q31 CFFT/CIFFT.  More...
 
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Description
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The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster than the DFT, especially for long lengths. The algorithms described in this section operate on complex data. A separate set of functions is devoted to handling of real sequences. 
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There are separate algorithms for handling floating-point, Q15, and Q31 data types. The algorithms available for each data type are described next. 
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The FFT functions operate in-place. That is, the array holding the input data will also be used to hold the corresponding result. The input data is complex and contains 2*fftLen interleaved values as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 
 The FFT result will be contained in the same array and the frequency domain values will have the same interleaving.
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Floating-point
The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 stages are performed along with a single radix-2 or radix-4 stage, as needed. The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses a different twiddle factor table. 
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The function uses the standard FFT definition and output values may grow by a factor of fftLen when computing the forward transform. The inverse transform includes a scale of 1/fftLen as part of the calculation and this matches the textbook definition of the inverse FFT. 
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Preinitialized data structures containing twiddle factors and bit reversal tables are provided and defined in arm_const_structs.h. Include this header in your function and then pass one of the constant structures as an argument to arm_cfft_f32. For example: 
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arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) 
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computes a 64-point inverse complex FFT including bit reversal. The data structures are treated as constant data and not modified during the calculation. The same data structure can be reused for multiple transforms including mixing forward and inverse transforms. 
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Earlier releases of the library provided separate radix-2 and radix-4 algorithms that operated on floating-point data. These functions are still provided but are deprecated. The older functions are slower and less general than the new functions. 
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An example of initialization of the constants for the arm_cfft_f32 function follows: 
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const static arm_cfft_instance_f32 *S; ... switch (length) { case 16: S = & arm_cfft_sR_f32_len16; break; case 32: S = & arm_cfft_sR_f32_len32; break; case 64: S = & arm_cfft_sR_f32_len64; break; case 128: S = & arm_cfft_sR_f32_len128; break; case 256: S = & arm_cfft_sR_f32_len256; break; case 512: S = & arm_cfft_sR_f32_len512; break; case 1024: S = & arm_cfft_sR_f32_len1024; break; case 2048: S = & arm_cfft_sR_f32_len2048; break; case 4096: S = & arm_cfft_sR_f32_len4096; break; } 
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Q15 and Q31
The library provides radix-2 and radix-4 FFT algorithms for fixed-point data. The radix-2 algorithm supports lengths of [16, 32, 64, ..., 4096]. The radix-4 algorithm supports lengths of [16, 64, 256, ..., 4096]. When possible, you should use the radix-4 algorithm since it is faster than the radix-2 of the same length. 
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The forward FFTs include scaling in order to prevent results from overflowing. Intermediate results are scaled down during each butterfly stage. In the radix-2 algorithm, a scale of 0.5 is applied during each butterfly. In the radix-4 algorithm, a scale of 0.25 is applied. The scaling applies to both the forward and the inverse FFTs. Thus the forward FFT contains an additional scale factor of 1/fftLen as compared to the standard textbook definition of the FFT. The inverse FFT also scales down during each butterfly stage and this corresponds to the standard textbook definition. 
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A separate instance structure must be defined for each transform used but twiddle factor and bit reversal tables can be reused. 
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There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Initializes twiddle factor table and bit reversal table pointers. 
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure should be manually initialized as follows: 
   \n*arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   \n*arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   \n*arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    \n*arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    \n*arm_cfft_instance_f32 S = {fftLen, pTwiddle, pBitRevTable, bitRevLength};\n  
 
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where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of forward or inverse transform. When ifftFlag is set the inverse transform is calculated. bitReverseFlag Flag for selection of output order (Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT; 
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The Q15 and Q31 FFT functions use a large bit reversal and twiddle factor table. The tables are defined for the maximum length transform and a subset of the coefficients are used in shorter transforms. 
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Function Documentation
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void arm_cfft_f32 (const arm_cfft_instance_f32 * S, 
float32_t * p1, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Parameters
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[in]*Spoints to an instance of the floating-point CFFT structure. 
[in,out]*p1points to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
none. 
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Examples: 
arm_fft_bin_example_f32.c.
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References arm_bitreversal_32(), arm_cfft_radix8by2_f32(), arm_cfft_radix8by4_f32(), arm_radix8_butterfly_f32(), arm_cfft_instance_f32::bitRevLength, arm_cfft_instance_f32::fftLen, arm_cfft_instance_f32::pBitRevTable, and arm_cfft_instance_f32::pTwiddle.
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Referenced by arm_rfft_fast_f32(), and main().
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void arm_cfft_radix2_f32 (const arm_cfft_radix2_instance_f32 * S, 
float32_t * pSrc 
)
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Deprecated:
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future. 
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Parameters
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[in]*Spoints to an instance of the floating-point Radix-2 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
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Returns
none. 
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References arm_bitreversal_f32(), arm_radix2_butterfly_f32(), arm_radix2_butterfly_inverse_f32(), arm_cfft_radix2_instance_f32::bitReverseFlag, arm_cfft_radix2_instance_f32::bitRevFactor, arm_cfft_radix2_instance_f32::fftLen, arm_cfft_radix2_instance_f32::ifftFlag, arm_cfft_radix2_instance_f32::onebyfftLen, arm_cfft_radix2_instance_f32::pBitRevTable, arm_cfft_radix2_instance_f32::pTwiddle, and arm_cfft_radix2_instance_f32::twidCoefModifier.
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arm_status arm_cfft_radix2_init_f32 (arm_cfft_radix2_instance_f32 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Deprecated:
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future. 
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Parameters
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[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_f32::bitReverseFlag, arm_cfft_radix2_instance_f32::bitRevFactor, arm_cfft_radix2_instance_f32::fftLen, ifftFlag, arm_cfft_radix2_instance_f32::ifftFlag, arm_cfft_radix2_instance_f32::onebyfftLen, arm_cfft_radix2_instance_f32::pBitRevTable, arm_cfft_radix2_instance_f32::pTwiddle, status, arm_cfft_radix2_instance_f32::twidCoefModifier, and twiddleCoef.
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arm_status arm_cfft_radix2_init_q15 (arm_cfft_radix2_instance_q15 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_q15::bitReverseFlag, arm_cfft_radix2_instance_q15::bitRevFactor, arm_cfft_radix2_instance_q15::fftLen, ifftFlag, arm_cfft_radix2_instance_q15::ifftFlag, arm_cfft_radix2_instance_q15::pBitRevTable, arm_cfft_radix2_instance_q15::pTwiddle, status, arm_cfft_radix2_instance_q15::twidCoefModifier, and twiddleCoefQ15.
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arm_status arm_cfft_radix2_init_q31 (arm_cfft_radix2_instance_q31 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Parameters
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[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix2_instance_q31::bitReverseFlag, arm_cfft_radix2_instance_q31::bitRevFactor, arm_cfft_radix2_instance_q31::fftLen, ifftFlag, arm_cfft_radix2_instance_q31::ifftFlag, arm_cfft_radix2_instance_q31::pBitRevTable, arm_cfft_radix2_instance_q31::pTwiddle, status, arm_cfft_radix2_instance_q31::twidCoefModifier, and twiddleCoefQ31.
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void arm_cfft_radix2_q15 (const arm_cfft_radix2_instance_q15 * S, 
q15_t * pSrc 
)
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Parameters
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[in]*Spoints to an instance of the fixed-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
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Returns
none. 
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References arm_bitreversal_q15(), arm_radix2_butterfly_inverse_q15(), arm_radix2_butterfly_q15(), arm_cfft_radix2_instance_q15::bitRevFactor, arm_cfft_radix2_instance_q15::fftLen, arm_cfft_radix2_instance_q15::ifftFlag, arm_cfft_radix2_instance_q15::pBitRevTable, arm_cfft_radix2_instance_q15::pTwiddle, and arm_cfft_radix2_instance_q15::twidCoefModifier.
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void arm_cfft_radix2_q31 (const arm_cfft_radix2_instance_q31 * S, 
q31_t * pSrc 
)
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Parameters
\n  \n    \n    \n  
[in]*Spoints to an instance of the fixed-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
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Returns
none. 
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References arm_bitreversal_q31(), arm_radix2_butterfly_inverse_q31(), arm_radix2_butterfly_q31(), arm_cfft_radix2_instance_q31::bitRevFactor, arm_cfft_radix2_instance_q31::fftLen, arm_cfft_radix2_instance_q31::ifftFlag, arm_cfft_radix2_instance_q31::pBitRevTable, arm_cfft_radix2_instance_q31::pTwiddle, and arm_cfft_radix2_instance_q31::twidCoefModifier.
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void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 * S, 
float32_t * pSrc 
)
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Deprecated:
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future. 
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Parameters
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[in]*Spoints to an instance of the floating-point Radix-4 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
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Returns
none. 
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Examples: 
arm_convolution_example_f32.c.
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References arm_bitreversal_f32(), arm_radix4_butterfly_f32(), arm_radix4_butterfly_inverse_f32(), arm_cfft_radix4_instance_f32::bitReverseFlag, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, arm_cfft_radix4_instance_f32::ifftFlag, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_cfft_radix4_instance_f32::pTwiddle, and arm_cfft_radix4_instance_f32::twidCoefModifier.
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Referenced by main().
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arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Deprecated:
Do not use this function. It has been superceded by arm_cfft_f32 and will be removed in the future. 
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Parameters
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[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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Examples: 
arm_convolution_example_f32.c.
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_f32::bitReverseFlag, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, ifftFlag, arm_cfft_radix4_instance_f32::ifftFlag, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_cfft_radix4_instance_f32::pTwiddle, status, arm_cfft_radix4_instance_f32::twidCoefModifier, and twiddleCoef.
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Referenced by arm_rfft_init_f32(), and main().
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arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_q15::bitReverseFlag, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, ifftFlag, arm_cfft_radix4_instance_q15::ifftFlag, arm_cfft_radix4_instance_q15::pBitRevTable, arm_cfft_radix4_instance_q15::pTwiddle, status, arm_cfft_radix4_instance_q15::twidCoefModifier, and twiddleCoefQ15.
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Referenced by arm_rfft_init_q15().
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arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 * S, 
uint16_t fftLen, 
uint8_t ifftFlag, 
uint8_t bitReverseFlag 
)
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Parameters
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[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevTable, arm_cfft_radix4_instance_q31::bitReverseFlag, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, ifftFlag, arm_cfft_radix4_instance_q31::ifftFlag, arm_cfft_radix4_instance_q31::pBitRevTable, arm_cfft_radix4_instance_q31::pTwiddle, status, arm_cfft_radix4_instance_q31::twidCoefModifier, and twiddleCoefQ31.
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Referenced by arm_rfft_init_q31().
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void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 * S, 
q15_t * pSrc 
)
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Parameters
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[in]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer. Processing occurs in-place. 
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Returns
none.
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Input and output formats: 
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Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 
\n
\n\"CFFTQ15.gif\"/\n
\nInput and Output Formats for Q15 CFFT
\n 
\n\"CIFFTQ15.gif\"/\n
\nInput and Output Formats for Q15 CIFFT
\n 
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References arm_bitreversal_q15(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_cfft_radix4_instance_q15::bitReverseFlag, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, arm_cfft_radix4_instance_q15::ifftFlag, arm_cfft_radix4_instance_q15::pBitRevTable, arm_cfft_radix4_instance_q15::pTwiddle, and arm_cfft_radix4_instance_q15::twidCoefModifier.
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void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 * S, 
q31_t * pSrc 
)
\n
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Parameters
\n  \n    \n    \n  
[in]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 
\n  
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Returns
none.
\n
Input and output formats: 
\n
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 
\n
\n\"CFFTQ31.gif\"/\n
\nInput and Output Formats for Q31 CFFT
\n 
\n\"CIFFTQ31.gif\"/\n
\nInput and Output Formats for Q31 CIFFT
\n 
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References arm_bitreversal_q31(), arm_radix4_butterfly_inverse_q31(), arm_radix4_butterfly_q31(), arm_cfft_radix4_instance_q31::bitReverseFlag, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, arm_cfft_radix4_instance_q31::ifftFlag, arm_cfft_radix4_instance_q31::pBitRevTable, arm_cfft_radix4_instance_q31::pTwiddle, and arm_cfft_radix4_instance_q31::twidCoefModifier.
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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    "content": "\n\n\n\n\nCMSIS-DSP: Convolution\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Convolution
Filtering Functions
  
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\nFunctions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.  More...
 
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.  More...
 
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.  More...
 
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.  More...
 
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.  More...
 
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.  More...
 
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Description
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Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. Convolution is similar to correlation and is frequently used in filtering and data analysis. The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
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Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. Then the convolution
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    \n                  c[n] = a[n] * b[n]    \n
is defined as 
\n\"ConvolutionEquation.gif\"/\n
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Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.
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Conceptually, when two signals a[n] and b[n] are convolved, the signal b[n] slides over a[n]. For each offset n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
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Note that convolution is a commutative operation:
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    \n                  a[n] * b[n] = b[n] * a[n].    \n
This means that switching the A and B arguments to the convolution functions has no effect.
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Fixed-Point Behavior
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Convolution requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used.
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Fast Versions
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Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires the input signals should be scaled down to avoid intermediate overflows.
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Opt Versions
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Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 
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Function Documentation
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void arm_conv_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
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Returns
none. 
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References srcALen, and srcBLen.
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void arm_conv_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 
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Returns
none.
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
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Scaling and Overflow Behavior:
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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
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See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 
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References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.
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void arm_conv_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
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See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 
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References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.
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void arm_conv_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior:
\n
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.
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The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally.
\n
See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 
\n\n
References srcALen, and srcBLen.
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void arm_conv_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 
\n  
\n
\n
Returns
none.
\n
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
\n
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
\n\n
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.
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void arm_conv_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 
\n  
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\n
Returns
none.
\n
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. 
\n\n
References __PACKq7, __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), srcALen, and srcBLen.
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void arm_conv_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
\n
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
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Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. 
\n\n
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.
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void arm_conv_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
\n
See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
\n\n
References srcALen, and srcBLen.
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_conv_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
\n
Refer the function arm_conv_opt_q7() for a faster implementation of this function. 
\n\n
References srcALen, and srcBLen.
\n\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___conv.js",
    "content": "var group___conv =\n[\n    [ \"arm_conv_f32\", \"group___conv.html#ga3f860dc98c6fc4cafc421e4a2aed3c89\", null ],\n    [ \"arm_conv_fast_opt_q15\", \"group___conv.html#gaf16f490d245391ec18a42adc73d6d749\", null ],\n    [ \"arm_conv_fast_q15\", \"group___conv.html#gad75ca978ce906e04abdf86a8d76306d4\", null ],\n    [ \"arm_conv_fast_q31\", \"group___conv.html#ga51112dcdf9b3624eb05182cdc4da9ec0\", null ],\n    [ \"arm_conv_opt_q15\", \"group___conv.html#gac77dbcaef5c754cac27eab96c4753a3c\", null ],\n    [ \"arm_conv_opt_q7\", \"group___conv.html#ga4c7cf073e89d6d57cc4e711f078c3f68\", null ],\n    [ \"arm_conv_q15\", \"group___conv.html#gaccd6a89b0ff7a94df64610598e6e6893\", null ],\n    [ \"arm_conv_q31\", \"group___conv.html#ga946b58da734f1e4e78c91fcaab4b12b6\", null ],\n    [ \"arm_conv_q7\", \"group___conv.html#gae2070cb792a167e78dbad8d06b97cdab\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___convolution_example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Convolution Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Convolution Example
Examples
  
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Description:
\n
Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex Multiplication, and Support Functions.
\n
Algorithm:
\n
The convolution theorem states that convolution in the time domain corresponds to multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of two signals is equal to the product of their individual Fourier transforms. The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). 
\n
Two input signals, a[n] and b[n], with lengths n1 and n2 respectively, are zero padded so that their lengths become N, which is greater than or equal to (n1+n2-1) and is a power of 4 as FFT implementation is radix-4. The convolution of a[n] and b[n] is obtained by taking the FFT of the input signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of the multiplied result. 
\n
This is denoted by the following equations: 
 A[k] = FFT(a[n],N)\nB[k] = FFT(b[n],N)\nconv(a[n], b[n]) = IFFT(A[k] * B[k], N)
 where A[k] and B[k] are the N-point FFTs of the signals a[n] and b[n] respectively. The length of the convolved signal is (n1+n2-1).
\n
Block Diagram:
\n
\n\"Convolution.gif\"/\n
\n
\n
Variables Description:
\n
    \n
  • testInputA_f32 points to the first input sequence 
    • \n
  • srcALen length of the first input sequence 
    • \n
  • testInputB_f32 points to the second input sequence 
    • \n
  • srcBLen length of the second input sequence 
    • \n
  • outLen length of convolution output sequence, (srcALen + srcBLen - 1) 
    • \n
  • AxB points to the output array where the product of individual FFTs of inputs is stored.
    • \n
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\n
CMSIS DSP Software Library Functions Used:
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\n
 Refer  arm_convolution_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___corr.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Correlation\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Correlation
Filtering Functions
  
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\nFunctions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Correlation of floating-point sequences.  More...
 
void arm_correlate_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
void arm_correlate_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch)
 Correlation of Q15 sequences.  More...
 
void arm_correlate_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Correlation of Q7 sequences.  More...
 
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Correlation of Q15 sequences.  More...
 
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Correlation of Q31 sequences.  More...
 
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Correlation of Q7 sequences.  More...
 
\n
Description
\n
Correlation is a mathematical operation that is similar to convolution. As with convolution, correlation uses two signals to produce a third signal. The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. Correlation is commonly used to measure the similarity between two signals. It has applications in pattern recognition, cryptanalysis, and searching. The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. Fast versions of the Q15 and Q31 functions are also provided.
\n
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. The convolution of the two signals is denoted by 
    \n                  c[n] = a[n] * b[n]    \n
 In correlation, one of the signals is flipped in time 
    \n                  c[n] = a[n] * b[-n]    \n
\n
and this is mathematically defined as 
\n\"CorrelateEquation.gif\"/\n
\n 
\n
The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.
\n
Note 
\n
The pDst should be initialized to all zeros before being used.
\n
Fixed-Point Behavior 
\n
Correlation requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used.
\n
Fast Versions
\n
Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires the input signals should be scaled down to avoid intermediate overflows.
\n
Opt Versions
\n
Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 
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Function Documentation
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void arm_correlate_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
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Returns
none. 
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References srcALen, and srcBLen.
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void arm_correlate_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratchpoints to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
\n  
\n
\n
Returns
none.
\n
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior:
\n
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
\n
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 
\n\n
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.
\n\n
\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
\n
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 
\n\n
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.
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void arm_correlate_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.
\n
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally.
\n
See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 
\n\n
References srcALen, and srcBLen.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
q15_t * pScratch 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratchpoints to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
\n  
\n
\n
Returns
none.
\n
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
\n
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
\n\n
References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 
\n  
\n
\n
Returns
none.
\n
Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. 
\n\n
References __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), srcALen, and srcBLen.
\n\n
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\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
\n
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
\n
Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. 
\n\n
References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
\n
See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
\n\n
References srcALen, and srcBLen.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_correlate_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
\n
Refer the function arm_correlate_opt_q7() for a faster implementation of this function. 
\n\n
References srcALen, and srcBLen.
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
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    "content": "\n\n\n\n\nCMSIS-DSP: DCT Type IV Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\n  
\nFunctions |\nVariables  
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\n
DCT Type IV Functions
Transform Functions
  
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\nFunctions
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
 Processing function for the floating-point DCT4/IDCT4.  More...
 
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
 Initialization function for the floating-point DCT4/IDCT4.  More...
 
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
 Initialization function for the Q15 DCT4/IDCT4.  More...
 
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
 Initialization function for the Q31 DCT4/IDCT4.  More...
 
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
 Processing function for the Q15 DCT4/IDCT4.  More...
 
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
 Processing function for the Q31 DCT4/IDCT4.  More...
 
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\nVariables
static const float32_t Weights_128 [256]
 
static const float32_t Weights_512 [1024]
 
static const float32_t Weights_2048 [4096]
 
static const float32_t Weights_8192 [16384]
 
static const float32_t cos_factors_128 [128]
 
static const float32_t cos_factors_512 [512]
 
static const float32_t cos_factors_2048 [2048]
 
static const float32_t cos_factors_8192 [8192]
 
static const q15_t ALIGN4 WeightsQ15_128 [256]
 
static const q15_t ALIGN4 WeightsQ15_512 [1024]
 
static const q15_t ALIGN4 WeightsQ15_2048 [4096]
 
static const q15_t ALIGN4 WeightsQ15_8192 [16384]
 
static const q15_t ALIGN4 cos_factorsQ15_128 [128]
 
static const q15_t ALIGN4 cos_factorsQ15_512 [512]
 
static const q15_t ALIGN4 cos_factorsQ15_2048 [2048]
 
static const q15_t ALIGN4 cos_factorsQ15_8192 [8192]
 
static const q31_t WeightsQ31_128 [256]
 
static const q31_t WeightsQ31_512 [1024]
 
static const q31_t WeightsQ31_2048 [4096]
 
static const q31_t WeightsQ31_8192 [16384]
 
static const q31_t cos_factorsQ31_128 [128]
 
static const q31_t cos_factorsQ31_512 [512]
 
static const q31_t cos_factorsQ31_2048 [2048]
 
static const q31_t cos_factorsQ31_8192 [8192]
 
\n
Description
\n
Representation of signals by minimum number of values is important for storage and transmission. The possibility of large discontinuity between the beginning and end of a period of a signal in DFT can be avoided by extending the signal so that it is even-symmetric. Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the spectrum and is very widely used in signal and image coding applications. The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
\n
DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. Reordering of the input data makes the computation of DCT just a problem of computing the DFT of a real signal with a few additional operations. This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
\n
DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. DCT2 implementation can be described in the following steps:
\n
    \n
  • Re-ordering input
    • \n
  • Calculating Real FFT
    • \n
  • Multiplication of weights and Real FFT output and getting real part from the product.
    • \n
\n
This process is explained by the block diagram below: 
\n
\n\"DCT4.gif\"/\n
\nDiscrete Cosine Transform - type-IV
\n
Algorithm: 
The N-point type-IV DCT is defined as a real, linear transformation by the formula: 
\n\"DCT4Equation.gif\"/\n
\n where k = 0,1,2,.....N-1 
\n
Its inverse is defined as follows: 
\n\"IDCT4Equation.gif\"/\n
\n where n = 0,1,2,.....N-1 
\n
The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). The symmetry of the transform matrix indicates that the fast algorithms for the forward and inverse transform computation are identical. Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
\n
Lengths supported by the transform: 
As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32(). The library provides separate functions for Q15, Q31, and floating-point data types. 
\n
Instance Structure 
The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. A separate instance structure must be defined for each transform. There are separate instance structure declarations for each of the 3 supported data types.
\n
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    \n
  • Sets the values of the internal structure fields.
    • \n
  • Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32(). 
    • \n
\n
\n
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
    \n*arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    \n*arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   \n*arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   \n  
 where N is the length of the DCT4; Nby2 is half of the length of the DCT4; normalize is normalizing factor used and is equal to sqrt(2/N); pTwiddle points to the twiddle factor table; pCosFactor points to the cosFactor table; pRfft points to the real FFT instance; pCfft points to the complex FFT instance; The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() and arm_rfft_f32() respectively for details regarding static initialization.
\n
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the DCT4 transform functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_dct4_f32 (const arm_dct4_instance_f32 * S, 
float32_t * pState, 
float32_t * pInlineBuffer 
)
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Parameters
\n  \n    \n    \n    \n  
[in]*Spoints to an instance of the floating-point DCT4/IDCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 
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Returns
none. 
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References arm_mult_f32(), arm_scale_f32(), arm_dct4_instance_f32::N, arm_dct4_instance_f32::Nby2, arm_dct4_instance_f32::pCosFactor, and arm_dct4_instance_f32::pTwiddle.
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arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 * S, 
arm_rfft_instance_f32 * S_RFFT, 
arm_cfft_radix4_instance_f32 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
float32_t normalize 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of floating-point DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of floating-point RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of floating-point CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 
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\n
Returns
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. 
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Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Floating-point normalizing factors are mentioned in the table below for different DCT sizes: 
\n\"dct4NormalizingF32Table.gif\"/\n
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_f32(), cos_factors_128, cos_factors_2048, cos_factors_512, cos_factors_8192, arm_dct4_instance_f32::N, arm_dct4_instance_f32::Nby2, arm_dct4_instance_f32::normalize, arm_dct4_instance_f32::pCfft, arm_dct4_instance_f32::pCosFactor, arm_dct4_instance_f32::pRfft, arm_dct4_instance_f32::pTwiddle, status, Weights_128, Weights_2048, Weights_512, and Weights_8192.
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arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 * S, 
arm_rfft_instance_q15 * S_RFFT, 
arm_cfft_radix4_instance_q15 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
q15_t normalize 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of Q15 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of Q15 CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 
\n  
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\n
Returns
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 
\n
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: 
\n\"dct4NormalizingQ15Table.gif\"/\n
\n 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_q15(), cos_factorsQ15_128, cos_factorsQ15_2048, cos_factorsQ15_512, cos_factorsQ15_8192, arm_dct4_instance_q15::N, arm_dct4_instance_q15::Nby2, arm_dct4_instance_q15::normalize, arm_dct4_instance_q15::pCfft, arm_dct4_instance_q15::pCosFactor, arm_dct4_instance_q15::pRfft, arm_dct4_instance_q15::pTwiddle, status, WeightsQ15_128, WeightsQ15_2048, WeightsQ15_512, and WeightsQ15_8192.
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arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 * S, 
arm_rfft_instance_q31 * S_RFFT, 
arm_cfft_radix4_instance_q31 * S_CFFT, 
uint16_t N, 
uint16_t Nby2, 
q31_t normalize 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of Q31 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q31 RFFT/RIFFT structure 
[in]*S_CFFTpoints to an instance of Q31 CFFT/CIFFT structure 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 
\n  
\n
\n
Returns
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 
\n
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: 
\n\"dct4NormalizingQ31Table.gif\"/\n
\n 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_init_q31(), cos_factorsQ31_128, cos_factorsQ31_2048, cos_factorsQ31_512, cos_factorsQ31_8192, arm_dct4_instance_q31::N, arm_dct4_instance_q31::Nby2, arm_dct4_instance_q31::normalize, arm_dct4_instance_q31::pCfft, arm_dct4_instance_q31::pCosFactor, arm_dct4_instance_q31::pRfft, arm_dct4_instance_q31::pTwiddle, status, WeightsQ31_128, WeightsQ31_2048, WeightsQ31_512, and WeightsQ31_8192.
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void arm_dct4_q15 (const arm_dct4_instance_q15 * S, 
q15_t * pState, 
q15_t * pInlineBuffer 
)
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Parameters
\n  \n    \n    \n    \n  
[in]*Spoints to an instance of the Q15 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 
\n  
\n
\n
Returns
none.
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Input an output formats: 
Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
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\n\"dct4FormatsQ15Table.gif\"/\n
\n \n
References arm_mult_q15(), arm_shift_q15(), arm_dct4_instance_q15::N, arm_dct4_instance_q15::Nby2, arm_dct4_instance_q15::pCosFactor, and arm_dct4_instance_q15::pTwiddle.
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void arm_dct4_q31 (const arm_dct4_instance_q31 * S, 
q31_t * pState, 
q31_t * pInlineBuffer 
)
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Parameters
\n  \n    \n    \n    \n  
[in]*Spoints to an instance of the Q31 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 
\n  
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Returns
none. 
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Input an output formats: 
Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, as the conversion from DCT2 to DCT4 involves one subtraction. Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
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\n\"dct4FormatsQ31Table.gif\"/\n
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References arm_cmplx_mult_cmplx_q31(), arm_mult_q31(), arm_rfft_q31(), arm_shift_q31(), arm_dct4_instance_q31::N, arm_dct4_instance_q31::Nby2, arm_dct4_instance_q31::normalize, arm_dct4_instance_q31::pCosFactor, arm_dct4_instance_q31::pRfft, and arm_dct4_instance_q31::pTwiddle.
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Variable Documentation
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const float32_t cos_factors_128[128]
\n  		\nstatic  
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\n
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 
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C command to generate the table 
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 for(i = 0; i< N; i++)    \n{    \n   cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n} 
 
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where N is the number of factors to generate and c is pi/(2*N) 
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Referenced by arm_dct4_init_f32().
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const float32_t cos_factors_2048[2048]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const float32_t cos_factors_512[512]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const float32_t cos_factors_8192[8192]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const q15_t ALIGN4 cos_factorsQ15_128[128]
\n  		\nstatic  
\n
\n
cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
 
\n
C command to generate the table 
    \nfor(i = 0; i< N; i++)    \n{    \n  cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n} 
 
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where N is the number of factors to generate and c is pi/(2*N) 
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Then converted to q15 format by multiplying with 2^31 and saturated if required. 
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 cos_factorsQ15_2048[2048]
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 cos_factorsQ15_512[512]
\n  		\nstatic  
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 cos_factorsQ15_8192[8192]
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Referenced by arm_dct4_init_q15().
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const q31_t cos_factorsQ31_128[128]
\n  		\nstatic  
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cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 
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C command to generate the table 
    \nfor(i = 0; i< N; i++)    \n{    \n  cos_factors[i]= 2 * cos((2*i+1)*c/2);    \n} 
 
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where N is the number of factors to generate and c is pi/(2*N) 
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Then converted to q31 format by multiplying with 2^31 and saturated if required. 
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Referenced by arm_dct4_init_q31().
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const q31_t cos_factorsQ31_2048[2048]
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Referenced by arm_dct4_init_q31().
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const q31_t cos_factorsQ31_512[512]
\n  		\nstatic  
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Referenced by arm_dct4_init_q31().
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const q31_t cos_factorsQ31_8192[8192]
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Referenced by arm_dct4_init_q31().
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const float32_t Weights_128[256]
\n  		\nstatic  
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\n
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 
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C command to generate the table 
    \nfor(i = 0; i< N; i++)    \n{    \n   weights[2*i]= cos(i*c);    \n   weights[(2*i)+1]= -sin(i * c);    \n} 
 
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Where N is the Number of weights to be calculated and c is pi/(2*N) 
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In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 
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Referenced by arm_dct4_init_f32().
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const float32_t Weights_2048[4096]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const float32_t Weights_512[1024]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const float32_t Weights_8192[16384]
\n  		\nstatic  
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Referenced by arm_dct4_init_f32().
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const q15_t ALIGN4 WeightsQ15_128[256]
\n  		\nstatic  
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\n
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 
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C command to generate the table 
    \nfor(i = 0; i< N; i++)    \n{    \n  weights[2*i]= cos(i*c);    \n  weights[(2*i)+1]= -sin(i * c);    \n} 
 
\n
where N is the Number of weights to be calculated and c is pi/(2*N) 
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Converted the output to q15 format by multiplying with 2^31 and saturated if required. 
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In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 WeightsQ15_2048[4096]
\n  		\nstatic  
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 WeightsQ15_512[1024]
\n  		\nstatic  
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Referenced by arm_dct4_init_q15().
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const q15_t ALIGN4 WeightsQ15_8192[16384]
\n  		\nstatic  
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Referenced by arm_dct4_init_q15().
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const q31_t WeightsQ31_128[256]
\n  		\nstatic  
\n
\n
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 
\n
C command to generate the table 
    \nfor(i = 0; i< N; i++)    \n{    \n  weights[2*i]= cos(i*c);    \n  weights[(2*i)+1]= -sin(i * c);    \n} 
 
\n
where N is the Number of weights to be calculated and c is pi/(2*N) 
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Convert the output to q31 format by multiplying with 2^31 and saturated if required. 
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In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 
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Referenced by arm_dct4_init_q31().
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const q31_t WeightsQ31_2048[4096]
\n  		\nstatic  
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Referenced by arm_dct4_init_q31().
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const q31_t WeightsQ31_512[1024]
\n  		\nstatic  
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Referenced by arm_dct4_init_q31().
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const q31_t WeightsQ31_8192[16384]
\n  		\nstatic  
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Referenced by arm_dct4_init_q31().
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___d_c_t4___i_d_c_t4.js",
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___dotproduct_example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Dot Product Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Dot Product Example
Examples
  
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Description:
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Demonstrates the use of the Multiply and Add functions to perform the dot product. The dot product of two vectors is obtained by multiplying corresponding elements and summing the products.
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Algorithm:
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The two input vectors A and B with length n, are multiplied element-by-element and then added to obtain dot product. 
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This is denoted by the following equation: 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
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Block Diagram:
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\n\"dotProduct.gif\"/\n
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Variables Description:
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  • srcA_buf_f32 points to first input vector 
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  • srcB_buf_f32 points to second input vector 
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  • testOutput stores dot product of the two input vectors.
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_dotproduct_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Finite Impulse Response (FIR) Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Finite Impulse Response (FIR) Filters
Filtering Functions
  
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\nFunctions
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR filter.  More...
 
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
IAR_ONLY_LOW_OPTIMIZATION_ENTER 
\nvoid 		arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.  More...
 
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR filter.  More...
 
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR filter.  More...
 
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR filter.  More...
 
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
 Initialization function for the Q7 FIR filter.  More...
 
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR filter.  More...
 
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR filter.  More...
 
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Processing function for the Q7 FIR filter.  More...
 
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Description
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This set of functions implements Finite Impulse Response (FIR) filters for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize values.
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Algorithm: 
The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. 
  \n     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  \n  
 
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\n\"FIR.gif\"/\n
\nFinite Impulse Response filter
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pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 
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  \n     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  \n  
 
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pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the following order. 
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  \n     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  \n  
 
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Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
  \n*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  \n*arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  \n  
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where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer.
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_fir_f32 (const arm_fir_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
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Parameters
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[in]*Spoints to an instance of the floating-point FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none. 
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Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.
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References arm_fir_instance_f32::numTaps, arm_fir_instance_f32::pCoeffs, and arm_fir_instance_f32::pState.
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Referenced by main().
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void arm_fir_fast_q15 (const arm_fir_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
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Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q15() to initialize the filter structure. 
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References __SIMD32, _SIMD32_OFFSET, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, and arm_fir_instance_q15::pState.
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IAR_ONLY_LOW_OPTIMIZATION_ENTER void arm_fir_fast_q31 (const arm_fir_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior:
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This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
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Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q31() to initialize the filter structure. 
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References arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.
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void arm_fir_init_f32 (arm_fir_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 
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Returns
none.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32(). 
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Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.
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References arm_fir_instance_f32::numTaps, arm_fir_instance_f32::pCoeffs, and arm_fir_instance_f32::pState.
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Referenced by main().
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arm_status arm_fir_init_q15 (arm_fir_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. Must be even and greater than or equal to 4. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizeis number of samples processed per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if numTaps is not greater than or equal to 4 and even.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 Note that numTaps must be even and greater than or equal to 4. To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. For example, to implement a filter with numTaps=3 and coefficients 
    \n    {0.3, -0.8, 0.3}    \n
 set numTaps=4 and use the coefficients: 
    \n    {0.3, -0.8, 0.3, 0}.    \n
 Similarly, to implement a two point filter 
    \n    {0.3, -0.3}    \n
 set numTaps=4 and use the coefficients: 
    \n    {0.3, -0.3, 0, 0}.    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, arm_fir_instance_q15::pState, and status.
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void arm_fir_init_q31 (arm_fir_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q31 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 
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Returns
none.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31(). 
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References arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.
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void arm_fir_init_q7 (arm_fir_instance_q7 * S, 
uint16_t numTaps, 
q7_t * pCoeffs, 
q7_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q7 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 
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Returns
none
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). 
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References arm_fir_instance_q7::numTaps, arm_fir_instance_q7::pCoeffs, and arm_fir_instance_q7::pState.
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void arm_fir_q15 (const arm_fir_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit
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Scaling and Overflow Behavior: 
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The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.
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Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function. 
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References __SIMD32, _SIMD32_OFFSET, arm_fir_instance_q15::numTaps, arm_fir_instance_q15::pCoeffs, and arm_fir_instance_q15::pState.
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void arm_fir_q31 (const arm_fir_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the Q31 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
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Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 
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References blockSize, arm_fir_instance_q31::numTaps, arm_fir_instance_q31::pCoeffs, and arm_fir_instance_q31::pState.
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void arm_fir_q7 (const arm_fir_instance_q7 * S, 
q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
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[in]*Spoints to an instance of the Q7 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 
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References blockSize, arm_fir_instance_q7::numTaps, arm_fir_instance_q7::pCoeffs, and arm_fir_instance_q7::pState.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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    "content": "\n\n\n\n\nCMSIS-DSP: Finite Impulse Response (FIR) Interpolator\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Finite Impulse Response (FIR) Interpolator
Filtering Functions
  
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\nFunctions
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR interpolator.  More...
 
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR interpolator.  More...
 
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR interpolator.  More...
 
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR interpolator.  More...
 
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Description
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These functions combine an upsampler (zero stuffer) and an FIR filter. They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. Conceptually, the functions are equivalent to the block diagram below: 
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\n\"FIRInterpolator.gif\"/\n
\nComponents included in the FIR Interpolator functions
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 After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. The user of the function is responsible for providing the filter coefficients.
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The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. The upsampler inserts L-1 zeros between each sample. Instead of multiplying by these zero values, the FIR filter is designed to skip them. This leads to an efficient implementation without any wasted effort. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize*L output values.
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The library provides separate functions for Q15, Q31, and floating-point data types.
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Algorithm: 
The functions use a polyphase filter structure: 
    \n   y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    \n   y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    \n   ...    \n   y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    \n
 This approach is more efficient than straightforward upsample-then-filter algorithms. With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. 
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pCoeffs points to a coefficient array of size numTaps. numTaps must be a multiple of the interpolation factor L and this is checked by the initialization functions. Internally, the function divides the FIR filter's impulse response into shorter filters of length phaseLength=numTaps/L. Coefficients are stored in time reversed order. 
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    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to a state array of size blockSize + phaseLength - 1. Samples in the state buffer are stored in the order: 
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    \n   {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    \n
 The state variables are updated after each block of data is processed, the coefficients are untouched.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
    • \n
  • Zeros out the values in the state buffer.
    • \n
  • Checks to make sure that the length of the filter is a multiple of the interpolation factor. To do this manually without calling the init function, assign the follow subfields of the instance structure: L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
    \narm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    \narm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    \narm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    \n
 where L is the interpolation factor; phaseLength=numTaps/L is the length of each of the shorter FIR filters used internally, pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none. 
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References arm_fir_interpolate_instance_f32::L, arm_fir_interpolate_instance_f32::pCoeffs, arm_fir_interpolate_instance_f32::phaseLength, and arm_fir_interpolate_instance_f32::pState.
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arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 * S, 
uint8_t L, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n
 The length of the filter numTaps must be a multiple of the interpolation factor L. 
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pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_f32::L, arm_fir_interpolate_instance_f32::pCoeffs, arm_fir_interpolate_instance_f32::phaseLength, arm_fir_interpolate_instance_f32::pState, and status.
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arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 * S, 
uint8_t L, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n
 The length of the filter numTaps must be a multiple of the interpolation factor L. 
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pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_q15::L, arm_fir_interpolate_instance_q15::pCoeffs, arm_fir_interpolate_instance_q15::phaseLength, arm_fir_interpolate_instance_q15::pState, and status.
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arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 * S, 
uint8_t L, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    \n
 The length of the filter numTaps must be a multiple of the interpolation factor L. 
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pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_interpolate_instance_q31::L, arm_fir_interpolate_instance_q31::pCoeffs, arm_fir_interpolate_instance_q31::phaseLength, arm_fir_interpolate_instance_q31::pState, and status.
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void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 
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References __SIMD32, arm_fir_interpolate_instance_q15::L, arm_fir_interpolate_instance_q15::pCoeffs, arm_fir_interpolate_instance_q15::phaseLength, and arm_fir_interpolate_instance_q15::pState.
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void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). since numTaps/L additions occur per output sample. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
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References arm_fir_interpolate_instance_q31::L, arm_fir_interpolate_instance_q31::pCoeffs, arm_fir_interpolate_instance_q31::phaseLength, and arm_fir_interpolate_instance_q31::pState.
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r___interpolate.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r___lattice.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Finite Impulse Response (FIR) Lattice Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Finite Impulse Response (FIR) Lattice Filters
Filtering Functions
  
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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR lattice filter.  More...
 
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
 Initialization function for the floating-point FIR lattice filter.  More...
 
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
 Initialization function for the Q15 FIR lattice filter.  More...
 
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
 Initialization function for the Q31 FIR lattice filter.  More...
 
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR lattice filter.  More...
 
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR lattice filter.  More...
 
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Description
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This set of functions implements Finite Impulse Response (FIR) lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure is feedforward and the net impulse response is finite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.
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Algorithm: 
\n\"FIRLattice.gif\"/\n
\nFinite Impulse Response Lattice filter
\n The following difference equation is implemented: 
    \n     f0[n] = g0[n] = x[n]    \n     fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    \n     gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    \n     y[n] = fM[n]    \n  
 
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pCoeffs points to tha array of reflection coefficients of size numStages. Reflection Coefficients are stored in the following order. 
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    \n     {k1, k2, ..., kM}    \n  
 where M is number of stages 
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pState points to a state array of size numStages. The state variables (g values) hold previous inputs and are stored in the following order. 
    \n     {g0[n], g1[n], g2[n] ...gM-1[n]}    \n  
 The state variables are updated after each block of data is processed; the coefficients are untouched. 
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
    • \n
  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numStages, pCoeffs, pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
    \n*arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    \n*arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    \n*arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    \n  
 
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where numStages is the number of stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer. 
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References blockSize, arm_fir_lattice_instance_f32::numStages, arm_fir_lattice_instance_f32::pCoeffs, and arm_fir_lattice_instance_f32::pState.
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void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 * S, 
uint16_t numStages, 
float32_t * pCoeffs, 
float32_t * pState 
)
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[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 
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Returns
none. 
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References arm_fir_lattice_instance_f32::numStages, arm_fir_lattice_instance_f32::pCoeffs, and arm_fir_lattice_instance_f32::pState.
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void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 * S, 
uint16_t numStages, 
q15_t * pCoeffs, 
q15_t * pState 
)
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[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 
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Returns
none. 
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References arm_fir_lattice_instance_q15::numStages, arm_fir_lattice_instance_q15::pCoeffs, and arm_fir_lattice_instance_q15::pState.
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void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 * S, 
uint16_t numStages, 
q31_t * pCoeffs, 
q31_t * pState 
)
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[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 
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Returns
none. 
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References arm_fir_lattice_instance_q31::numStages, arm_fir_lattice_instance_q31::pCoeffs, and arm_fir_lattice_instance_q31::pState.
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void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References __SIMD32, blockSize, arm_fir_lattice_instance_q15::numStages, arm_fir_lattice_instance_q15::pCoeffs, and arm_fir_lattice_instance_q15::pState.
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void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
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[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. 
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References arm_fir_lattice_instance_q31::numStages, arm_fir_lattice_instance_q31::pCoeffs, and arm_fir_lattice_instance_q31::pState.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r___lattice.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r___sparse.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Finite Impulse Response (FIR) Sparse Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Finite Impulse Response (FIR) Sparse Filters
Filtering Functions
  
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void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
 Processing function for the floating-point sparse FIR filter.  More...
 
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the floating-point sparse FIR filter.  More...
 
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q15 sparse FIR filter.  More...
 
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q31 sparse FIR filter.  More...
 
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
 Initialization function for the Q7 sparse FIR filter.  More...
 
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q15 sparse FIR filter.  More...
 
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
 Processing function for the Q31 sparse FIR filter.  More...
 
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
 Processing function for the Q7 sparse FIR filter.  More...
 
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Description
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This group of functions implements sparse FIR filters. Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. Sparse filters are used for simulating reflections in communications and audio applications.
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There are separate functions for Q7, Q15, Q31, and floating-point data types. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays respectively containing blockSize values.
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Algorithm: 
The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. This is in addition to the coefficient array b. The implementation essentially skips the multiplications by zero and leads to an efficient realization. 
   \n      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    \n  
 
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\n\"FIRSparse.gif\"/\n
\nSparse FIR filter. b[n] represents the filter coefficients
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pCoeffs points to a coefficient array of size numTaps; pTapDelay points to an array of nonzero indices and is also of size numTaps; pState points to a state array of size maxDelay + blockSize, where maxDelay is the largest offset value that is ever used in the pTapDelay array. Some of the processing functions also require temporary working buffers.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    \n
  • Sets the values of the internal structure fields.
    • \n
  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
    • \n
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
    \n*arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n*arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n*arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n*arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    \n  
 
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the sparse FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
float32_t * pScratchIn, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 
\n  
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Returns
none. 
\n\n
References arm_circularRead_f32(), arm_circularWrite_f32(), blockSize, arm_fir_sparse_instance_f32::maxDelay, arm_fir_sparse_instance_f32::numTaps, arm_fir_sparse_instance_f32::pCoeffs, arm_fir_sparse_instance_f32::pState, arm_fir_sparse_instance_f32::pTapDelay, and arm_fir_sparse_instance_f32::stateIndex.
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void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 
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Returns
none
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Description: 
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pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_f32() function. 
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References arm_fir_sparse_instance_f32::maxDelay, arm_fir_sparse_instance_f32::numTaps, arm_fir_sparse_instance_f32::pCoeffs, arm_fir_sparse_instance_f32::pState, arm_fir_sparse_instance_f32::pTapDelay, and arm_fir_sparse_instance_f32::stateIndex.
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void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 
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Returns
none
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Description: 
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pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q15() function. 
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References arm_fir_sparse_instance_q15::maxDelay, arm_fir_sparse_instance_q15::numTaps, arm_fir_sparse_instance_q15::pCoeffs, arm_fir_sparse_instance_q15::pState, arm_fir_sparse_instance_q15::pTapDelay, and arm_fir_sparse_instance_q15::stateIndex.
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void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 
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Returns
none
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Description: 
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pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q31() function. 
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References arm_fir_sparse_instance_q31::maxDelay, arm_fir_sparse_instance_q31::numTaps, arm_fir_sparse_instance_q31::pCoeffs, arm_fir_sparse_instance_q31::pState, arm_fir_sparse_instance_q31::pTapDelay, and arm_fir_sparse_instance_q31::stateIndex.
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void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 * S, 
uint16_t numTaps, 
q7_t * pCoeffs, 
q7_t * pState, 
int32_t * pTapDelay, 
uint16_t maxDelay, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 
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Returns
none
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Description: 
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pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_q7() function. 
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References arm_fir_sparse_instance_q7::maxDelay, arm_fir_sparse_instance_q7::numTaps, arm_fir_sparse_instance_q7::pCoeffs, arm_fir_sparse_instance_q7::pState, arm_fir_sparse_instance_q7::pTapDelay, and arm_fir_sparse_instance_q7::stateIndex.
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void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
q15_t * pScratchIn, 
q31_t * pScratchOut, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 32-bit accumulator. The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. If the accumulator result overflows it will wrap around rather than saturate. After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 
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References __SIMD32, arm_circularRead_q15(), arm_circularWrite_q15(), blockSize, arm_fir_sparse_instance_q15::maxDelay, arm_fir_sparse_instance_q15::numTaps, arm_fir_sparse_instance_q15::pCoeffs, arm_fir_sparse_instance_q15::pState, arm_fir_sparse_instance_q15::pTapDelay, and arm_fir_sparse_instance_q15::stateIndex.
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void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
q31_t * pScratchIn, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 32-bit accumulator. The 1.31 x 1.31 multiplications are truncated to 2.30 format. This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. If the accumulator result overflows, it wraps around rather than saturate. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 
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References arm_circularRead_f32(), arm_circularWrite_f32(), blockSize, arm_fir_sparse_instance_q31::maxDelay, arm_fir_sparse_instance_q31::numTaps, arm_fir_sparse_instance_q31::pCoeffs, arm_fir_sparse_instance_q31::pState, arm_fir_sparse_instance_q31::pTapDelay, and arm_fir_sparse_instance_q31::stateIndex.
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void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 * S, 
q7_t * pSrc, 
q7_t * pDst, 
q7_t * pScratchIn, 
q31_t * pScratchOut, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 
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References __PACKq7, __SIMD32, arm_circularRead_q7(), arm_circularWrite_q7(), blockSize, arm_fir_sparse_instance_q7::maxDelay, arm_fir_sparse_instance_q7::numTaps, arm_fir_sparse_instance_q7::pCoeffs, arm_fir_sparse_instance_q7::pState, arm_fir_sparse_instance_q7::pTapDelay, and arm_fir_sparse_instance_q7::stateIndex.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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    "content": "\n\n\n\n\nCMSIS-DSP: Finite Impulse Response (FIR) Decimator\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Finite Impulse Response (FIR) Decimator
Filtering Functions
  
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\nFunctions
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point FIR decimator.  More...
 
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point FIR decimator.  More...
 
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 FIR decimator.  More...
 
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 FIR decimator.  More...
 
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 FIR decimator.  More...
 
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 FIR decimator.  More...
 
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Description
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These functions combine an FIR filter together with a decimator. They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. Conceptually, the functions are equivalent to the block diagram below: 
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\n\"FIRDecimator.gif\"/\n
\nComponents included in the FIR Decimator functions
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 When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized cutoff frequency of 1/M in order to prevent aliasing distortion. The user of the function is responsible for providing the filter coefficients.
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The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the samples output by the decimator are computed. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize/M output values. In order to have an integer number of output samples blockSize must always be a multiple of the decimation factor M.
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The library provides separate functions for Q15, Q31 and floating-point data types.
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Algorithm: 
The FIR portion of the algorithm uses the standard form filter: 
    \n     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n  
 where, b[n] are the filter coefficients. 
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The pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 
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    \n     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n  
 
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pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 
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    \n     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n  
 The state variables are updated after each block of data is processed, the coefficients are untouched.
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer.
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  • Checks to make sure that the size of the input is a multiple of the decimation factor. To do this manually without calling the init function, assign the follow subfields of the instance structure: numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
    \n*arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    \n*arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    \n*arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    \n  
 where M is the decimation factor; numTaps is the number of filter coefficients in the filter; pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR decimate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none. 
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References arm_fir_decimate_instance_f32::M, arm_fir_decimate_instance_f32::numTaps, arm_fir_decimate_instance_f32::pCoeffs, and arm_fir_decimate_instance_f32::pState.
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void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 
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Returns
none
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit
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Scaling and Overflow Behavior: 
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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
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Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q15() to initialize the filter structure. 
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References __SIMD32, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, and arm_fir_decimate_instance_q15::pState.
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void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 
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Returns
none
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Scaling and Overflow Behavior:
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This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
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Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q31() to initialize the filter structure. 
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References arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, and arm_fir_decimate_instance_q31::pState.
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arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 * S, 
uint16_t numTaps, 
uint8_t M, 
float32_t * pCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). M is the decimation factor. 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_f32::M, arm_fir_decimate_instance_f32::numTaps, arm_fir_decimate_instance_f32::pCoeffs, arm_fir_decimate_instance_f32::pState, and status.
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arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 * S, 
uint16_t numTaps, 
uint8_t M, 
q15_t * pCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples to the call arm_fir_decimate_q15(). M is the decimation factor. 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, arm_fir_decimate_instance_q15::pState, and status.
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arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 * S, 
uint16_t numTaps, 
uint8_t M, 
q31_t * pCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 
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pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). M is the decimation factor. 
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References ARM_MATH_LENGTH_ERROR, ARM_MATH_SUCCESS, arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, arm_fir_decimate_instance_q31::pState, and status.
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void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of input samples to process per call. 
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Returns
none.
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Scaling and Overflow Behavior: 
\n
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.
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Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
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References __SIMD32, arm_fir_decimate_instance_q15::M, arm_fir_decimate_instance_q15::numTaps, arm_fir_decimate_instance_q15::pCoeffs, and arm_fir_decimate_instance_q15::pState.
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void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 
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Returns
none
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
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Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
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References arm_fir_decimate_instance_q31::M, arm_fir_decimate_instance_q31::numTaps, arm_fir_decimate_instance_q31::pCoeffs, and arm_fir_decimate_instance_q31::pState.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r__decimate.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___f_i_r_l_p_f.html",
    "content": "\n\n\n\n\nCMSIS-DSP: FIR Lowpass Filter Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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FIR Lowpass Filter Example
Examples
  
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Description:
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Removes high frequency signal components from the input using an FIR lowpass filter. The example demonstrates how to configure an FIR filter and then pass data through it in a block-by-block fashion. 
\n\"FIRLPF_signalflow.gif\"/\n
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Algorithm:
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The input signal is a sum of two sine waves: 1 kHz and 15 kHz. This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. 
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The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and a length of 29 points. The MATLAB code to generate the filter coefficients is shown below: 
\n    h = fir1(28, 6/24);\n
 The first argument is the \"order\" of the filter and is always one less than the desired length. The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. The CMSIS FIR filter function requires the coefficients to be in time reversed order. 
\n    fliplr(h)\n
 The resulting filter coefficients and are shown below. Note that the filter is symmetric (a property of linear phase FIR filters) and the point of symmetry is sample 14. Thus the filter will have a delay of 14 samples for all frequencies. 
\n
\n\"FIRLPF_coeffs.gif\"/\n
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The frequency response of the filter is shown next. The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. 
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\n\"FIRLPF_response.gif\"/\n
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The input signal is shown below. The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. The two sine wave components can be clearly seen. 
\n
\n\"FIRLPF_input.gif\"/\n
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The output of the filter is shown below. The 15 kHz component has been eliminated. 
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\n\"FIRLPF_output.gif\"/\n
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Variables Description:
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  • testInput_f32_1kHz_15kHz points to the input data 
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  • refOutput points to the reference output data 
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  • testOutput points to the test output data 
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  • firStateF32 points to state buffer 
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  • firCoeffs32 points to coefficient buffer 
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  • blockSize number of samples processed at a time 
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  • numBlocks number of frames
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_fir_example_f32.c 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___fast.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Real FFT Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Real FFT Functions
Transform Functions
  
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The CMSIS DSP library includes specialized algorithms for computing the FFT of real data sequences. The FFT is defined over complex data but in many applications the input is real. Real FFT algorithms take advantage of the symmetry properties of the FFT and have a speed advantage over complex algorithms of the same length. 
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The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage. 
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The real length N forward FFT of a sequence is computed using the steps shown below. 
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\n\"RFFT.gif\"/\n
\nReal Fast Fourier Transform
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The real sequence is initially treated as if it were complex to perform a CFFT. Later, a processing stage reshapes the data to obtain half of the frequency spectrum in complex format. Except the first complex number that contains the two real numbers X[0] and X[N/2] all the data is complex. In other words, the first complex sample contains two real values packed. 
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The input for the inverse RFFT should keep the same format as the output of the forward RFFT. A first processing stage pre-process the data to later perform an inverse CFFT. 
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\n\"RIFFT.gif\"/\n
\nReal Inverse Fast Fourier Transform
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The algorithms for floating-point, Q15, and Q31 data are slightly different and we describe each algorithm in turn. 
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Floating-point
The main functions are arm_rfft_fast_f32() and arm_rfft_fast_init_f32(). The older functions arm_rfft_f32() and arm_rfft_init_f32() have been deprecated but are still documented. 
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The FFT of a real N-point sequence has even symmetry in the frequency domain. The second half of the data equals the conjugate of the first half flipped in frequency: 
\n*X[0] - real data\n*X[1] - complex data\n*X[2] - complex data\n ... \n*X[fftLen/2-1] - complex data\n*X[fftLen/2] - real data\n*X[fftLen/2+1] - conjugate of X[fftLen/2-1]\n*X[fftLen/2+2] - conjugate of X[fftLen/2-2]\n ... \n*X[fftLen-1] - conjugate of X[1]\n  
 Looking at the data, we see that we can uniquely represent the FFT using only 
\n*N/2+1 samples:\n*X[0] - real data\n*X[1] - complex data\n*X[2] - complex data\n ... \n*X[fftLen/2-1] - complex data\n*X[fftLen/2] - real data\n  
 Looking more closely we see that the first and last samples are real valued. They can be packed together and we can thus represent the FFT of an N-point real sequence by N/2 complex values: 
\n*X[0],X[N/2] - packed real data: X[0] + jX[N/2]\n*X[1] - complex data\n*X[2] - complex data\n ... \n*X[fftLen/2-1] - complex data\n  
 The real FFT functions pack the frequency domain data in this fashion. The forward transform outputs the data in this form and the inverse transform expects input data in this form. The function always performs the needed bitreversal so that the input and output data is always in normal order. The functions support lengths of [32, 64, 128, ..., 4096] samples. 
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The forward and inverse real FFT functions apply the standard FFT scaling; no scaling on the forward transform and 1/fftLen scaling on the inverse transform. 
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Q15 and Q31
The real algorithms are defined in a similar manner and utilize N/2 complex transforms behind the scenes. In the case of fixed-point data, a radix-4 complex transform is performed and this limits the allows sequence lengths to 128, 512, and 2048 samples. 
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TBD. We need to document input and output order of data. 
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The complex transforms used internally include scaling to prevent fixed-point overflows. The overall scaling equals 1/(fftLen/2). 
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A separate instance structure must be defined for each transform used but twiddle factor and bit reversal tables can be reused. 
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There is also an associated initialization function for each data type. The initialization function performs the following operations:
    \n
  • Sets the values of the internal structure fields.
    • \n
  • Initializes twiddle factor table and bit reversal table pointers.
    • \n
  • Initializes the internal complex FFT data structure. 
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure should be manually initialized as follows: 
\n*arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    \n*arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    \n  
 where fftLenReal is the length of the real transform; fftLenBy2 length of the internal complex transform. ifftFlagR Selects forward (=0) or inverse (=1) transform. bitReverseFlagR Selects bit reversed output (=0) or normal order output (=1). twidCoefRModifier stride modifier for the twiddle factor table. The value is based on the FFT length; pTwiddleARealpoints to the A array of twiddle coefficients; pTwiddleBRealpoints to the B array of twiddle coefficients; pCfft points to the CFFT Instance structure. The CFFT structure must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding static initialization of the complex FFT instance structure. 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___fill.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Fill\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Vector Fill
Support Functions
  
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void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
 Fills a constant value into a floating-point vector.  More...
 
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q15 vector.  More...
 
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q31 vector.  More...
 
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
 Fills a constant value into a Q7 vector.  More...
 
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Description
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Fills the destination vector with a constant value.
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    \n        pDst[n] = value;   0 <= n < blockSize.    \n
There are separate functions for floating point, Q31, Q15, and Q7 data types. 
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Function Documentation
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void arm_fill_f32 (float32_t value, 
float32_t * pDst, 
uint32_t blockSize 
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Parameters
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[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 
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Returns
none. 
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Examples: 
arm_convolution_example_f32.c, and arm_variance_example_f32.c.
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References blockSize.
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Referenced by main().
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void arm_fill_q15 (q15_t value, 
q15_t * pDst, 
uint32_t blockSize 
)
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[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 
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Returns
none. 
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References __SIMD32, and blockSize.
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Referenced by arm_conv_fast_opt_q15(), arm_conv_opt_q15(), arm_conv_opt_q7(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_opt_q15(), arm_conv_partial_opt_q7(), arm_correlate_fast_opt_q15(), arm_correlate_opt_q15(), and arm_correlate_opt_q7().
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void arm_fill_q31 (q31_t value, 
q31_t * pDst, 
uint32_t blockSize 
)
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[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 
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Returns
none. 
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References blockSize.
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void arm_fill_q7 (q7_t value, 
q7_t * pDst, 
uint32_t blockSize 
)
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[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 
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Returns
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References __PACKq7, __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___fill.js",
    "content": "var group___fill =\n[\n    [ \"arm_fill_f32\", \"group___fill.html#ga2248e8d3901b4afb7827163132baad94\", null ],\n    [ \"arm_fill_q15\", \"group___fill.html#ga76b21c32a3783a2b3334d930a646e5d8\", null ],\n    [ \"arm_fill_q31\", \"group___fill.html#ga69cc781cf337bd0a31bb85c772a35f7f\", null ],\n    [ \"arm_fill_q7\", \"group___fill.html#ga0465cf326ada039ed792f94b033d9ec5\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___frequency_bin.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Frequency Bin Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Frequency Bin Example
Examples
  
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Description
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Demonstrates the calculation of the maximum energy bin in the frequency domain of the input signal with the use of Complex FFT, Complex Magnitude, and Maximum functions.
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Algorithm:
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The input test signal contains a 10 kHz signal with uniformly distributed white noise. Calculating the FFT of the input signal will give us the maximum energy of the bin corresponding to the input frequency of 10 kHz.
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Block Diagram:
\n\"FFTBin.gif\"/\n
\nBlock Diagram
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The figure below shows the time domain signal of 10 kHz signal with uniformly distributed white noise, and the next figure shows the input in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. 
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\n\"FFTBinInput.gif\"/\n
\nInput signal in Time domain
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\n\"FFTBinOutput.gif\"/\n
\nInput signal in Frequency domain
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Variables Description:
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  • testInput_f32_10khz points to the input data 
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  • testOutput points to the output data 
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  • fftSize length of FFT 
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  • ifftFlag flag for the selection of CFFT/CIFFT 
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  • doBitReverse Flag for selection of normal order or bit reversed order 
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  • refIndex reference index value at which maximum energy of bin ocuurs 
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  • testIndex calculated index value at which maximum energy of bin ocuurs
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_fft_bin_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___g_e_q5_band.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Graphic Audio Equalizer Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Graphic Audio Equalizer Example
Examples
  
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Description:
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This example demonstrates how a 5-band graphic equalizer can be constructed using the Biquad cascade functions. A graphic equalizer is used in audio applications to vary the tonal quality of the audio.
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Block Diagram:
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The design is based on a cascade of 5 filter sections. 
\n\"GEQ_signalflow.gif\"/\n
\n Each filter section is 4th order and consists of a cascade of two Biquads. Each filter has a nominal gain of 0 dB (1.0 in linear units) and boosts or cuts signals within a specific frequency range. The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. Each band has an adjustable boost or cut in the range of +/- 9 dB. For example, the band that extends from 500 to 2000 Hz has the response shown below: 
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\n\"GEQ_bandresponse.gif\"/\n
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With 1 dB steps, each filter has a total of 19 different settings. The filter coefficients for all possible 19 settings were precomputed in MATLAB and stored in a table. With 5 different tables, there are a total of 5 x 19 = 95 different 4th order filters. All 95 responses are shown below: 
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\n\"GEQ_allbandresponse.gif\"/\n
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Each 4th order filter has 10 coefficents for a grand total of 950 different filter coefficients that must be tabulated. The input and output data is in Q31 format. For better noise performance, the two low frequency bands are implemented using the high precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. 
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\n\"GEQ_inputchirp.gif\"/\n
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The array bandGains specifies the gain in dB to apply in each band. For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: 
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\n\"GEQ_outputchirp.gif\"/\n
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Note
The output chirp signal follows the gain or boost of each band. 
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Variables Description:
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  • testInput_f32 points to the input data 
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  • testOutput points to the test output data 
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  • inputQ31 temporary input buffer 
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  • outputQ31 temporary output buffer 
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  • biquadStateBand1Q31 points to state buffer for band1 
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  • biquadStateBand2Q31 points to state buffer for band2 
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  • biquadStateBand3Q31 points to state buffer for band3 
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  • biquadStateBand4Q31 points to state buffer for band4 
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  • biquadStateBand5Q31 points to state buffer for band5 
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  • coeffTable points to coefficient buffer for all bands 
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_graphic_equalizer_example_q31.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___i_i_r___lattice.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Infinite Impulse Response (IIR) Lattice Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Infinite Impulse Response (IIR) Lattice Filters
Filtering Functions
  
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void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Processing function for the floating-point IIR lattice filter.  More...
 
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
 Initialization function for the floating-point IIR lattice filter.  More...
 
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
 Initialization function for the Q15 IIR lattice filter.  More...
 
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
 Initialization function for the Q31 IIR lattice filter.  More...
 
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Processing function for the Q15 IIR lattice filter.  More...
 
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Processing function for the Q31 IIR lattice filter.  More...
 
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Description
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This set of functions implements lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure has feedforward and feedback components and the net impulse response is infinite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.
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Algorithm: 
\n\"IIRLattice.gif\"/\n
\nInfinite Impulse Response Lattice filter
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    \n     fN(n)   =  x(n)    \n     fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    \n     gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    \n     y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    \n  
 
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pkCoeffs points to array of reflection coefficients of size numStages. Reflection coefficients are stored in time-reversed order. 
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    \n     {kN, kN-1, ....k1}    \n  
 pvCoeffs points to the array of ladder coefficients of size (numStages+1). Ladder coefficients are stored in time-reversed order. 
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    \n     {vN, vN-1, ...v0}    \n  
 pState points to a state array of size numStages + blockSize. The state variables shown in the figure above (the g values) are stored in the pState array. The state variables are updated after each block of data is processed; the coefficients are untouched. 
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
    \n*arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n*arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n*arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    \n  
 
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where numStages is the number of stages in the filter; pState points to the state buffer array; pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. 
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the IIR lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References blockSize, arm_iir_lattice_instance_f32::numStages, arm_iir_lattice_instance_f32::pkCoeffs, arm_iir_lattice_instance_f32::pState, and arm_iir_lattice_instance_f32::pvCoeffs.
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void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 * S, 
uint16_t numStages, 
float32_t * pkCoeffs, 
float32_t * pvCoeffs, 
float32_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References arm_iir_lattice_instance_f32::numStages, arm_iir_lattice_instance_f32::pkCoeffs, arm_iir_lattice_instance_f32::pState, and arm_iir_lattice_instance_f32::pvCoeffs.
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void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 * S, 
uint16_t numStages, 
q15_t * pkCoeffs, 
q15_t * pvCoeffs, 
q15_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process per call. 
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Returns
none. 
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References arm_iir_lattice_instance_q15::numStages, arm_iir_lattice_instance_q15::pkCoeffs, arm_iir_lattice_instance_q15::pState, and arm_iir_lattice_instance_q15::pvCoeffs.
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void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 * S, 
uint16_t numStages, 
q31_t * pkCoeffs, 
q31_t * pvCoeffs, 
q31_t * pState, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References arm_iir_lattice_instance_q31::numStages, arm_iir_lattice_instance_q31::pkCoeffs, arm_iir_lattice_instance_q31::pState, and arm_iir_lattice_instance_q31::pvCoeffs.
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void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 
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Returns
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Scaling and Overflow Behavior: 
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The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 
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References __SIMD32, blockSize, arm_iir_lattice_instance_q15::numStages, arm_iir_lattice_instance_q15::pkCoeffs, arm_iir_lattice_instance_q15::pState, and arm_iir_lattice_instance_q15::pvCoeffs.
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void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. 
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References blockSize, clip_q63_to_q31(), arm_iir_lattice_instance_q31::numStages, arm_iir_lattice_instance_q31::pkCoeffs, arm_iir_lattice_instance_q31::pState, and arm_iir_lattice_instance_q31::pvCoeffs.
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  },
  {
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    "content": "\n\n\n\n\nCMSIS-DSP: Least Mean Square (LMS) Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Least Mean Square (LMS) Filters
Filtering Functions
  
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void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point LMS filter.  More...
 
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point LMS filter.  More...
 
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for the Q15 LMS filter.  More...
 
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
 Initialization function for Q31 LMS filter.  More...
 
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 LMS filter.  More...
 
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 LMS filter.  More...
 
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Description
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LMS filters are a class of adaptive filters that are able to \"learn\" an unknown transfer functions. LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. Adaptive filters are often used in communication systems, equalizers, and noise removal. The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
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An LMS filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The LMS filter has two input signals. The \"input\" feeds the FIR filter while the \"reference input\" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This \"error signal\" tends towards zero as the filter adapts. The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. 
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\n\"LMS.gif\"/\n
\nInternal structure of the Least Mean Square filter
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The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.
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The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
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Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
    \n     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n 
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The error signal equals the difference between the reference signal d[n] and the filter output: 
    \n     e[n] = d[n] - y[n].    \n 
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After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: 
    \n     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    \n 
 where mu is the step size and controls the rate of coefficient convergence. 
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In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 
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    \n    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n 
 
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pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 
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    \n    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n 
 
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Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
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Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
    \n    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    \n    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    \n    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    \n 
 where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.
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Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the LMS filter. The following issues must be considered:
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Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.
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Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 
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Function Documentation
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void arm_lms_f32 (const arm_lms_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pRef, 
float32_t * pOut, 
float32_t * pErr, 
uint32_t blockSize 
)
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This function operates on floating-point data types.
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Parameters
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[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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References blockSize, arm_lms_instance_f32::mu, arm_lms_instance_f32::numTaps, arm_lms_instance_f32::pCoeffs, and arm_lms_instance_f32::pState.
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void arm_lms_init_f32 (arm_lms_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
float32_t mu, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). 
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References arm_lms_instance_f32::mu, arm_lms_instance_f32::numTaps, arm_lms_instance_f32::pCoeffs, and arm_lms_instance_f32::pState.
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void arm_lms_init_q15 (arm_lms_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
q15_t mu, 
uint32_t blockSize, 
uint32_t postShift 
)
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Parameters
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[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 
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Returns
none.
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Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q15(). 
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References arm_lms_instance_q15::mu, arm_lms_instance_q15::numTaps, arm_lms_instance_q15::pCoeffs, arm_lms_instance_q15::postShift, and arm_lms_instance_q15::pState.
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void arm_lms_init_q31 (arm_lms_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
q31_t mu, 
uint32_t blockSize, 
uint32_t postShift 
)
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Parameters
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[in]*Spoints to an instance of the Q31 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 
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Returns
none.
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Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q31(). 
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References arm_lms_instance_q31::mu, arm_lms_instance_q31::numTaps, arm_lms_instance_q31::pCoeffs, arm_lms_instance_q31::postShift, and arm_lms_instance_q31::pState.
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void arm_lms_q15 (const arm_lms_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pRef, 
q15_t * pOut, 
q15_t * pErr, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: 
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.
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In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 
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References __SIMD32, blockSize, arm_lms_instance_q15::mu, arm_lms_instance_q15::numTaps, arm_lms_instance_q15::pCoeffs, arm_lms_instance_q15::postShift, and arm_lms_instance_q15::pState.
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void arm_lms_q31 (const arm_lms_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pRef, 
q31_t * pOut, 
q31_t * pErr, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: 
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clips. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.
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In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 
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References blockSize, clip_q63_to_q31(), arm_lms_instance_q31::mu, arm_lms_instance_q31::numTaps, arm_lms_instance_q31::pCoeffs, arm_lms_instance_q31::postShift, and arm_lms_instance_q31::pState.
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    "content": "\n\n\n\n\nCMSIS-DSP: Normalized LMS Filters\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Normalized LMS Filters
Filtering Functions
  
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void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
 Processing function for floating-point normalized LMS filter.  More...
 
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
 Initialization function for floating-point normalized LMS filter.  More...
 
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q15 normalized LMS filter.  More...
 
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
 Initialization function for Q31 normalized LMS filter.  More...
 
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
 Processing function for Q15 normalized LMS filter.  More...
 
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
 Processing function for Q31 normalized LMS filter.  More...
 
\n
Description
\n
This set of functions implements a commonly used adaptive filter. It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization factor which increases the adaptation rate of the filter. The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
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A normalized least mean square (NLMS) filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The NLMS filter has two input signals. The \"input\" feeds the FIR filter while the \"reference input\" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This \"error signal\" tends towards zero as the filter adapts. The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. 
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\n\"LMS.gif\"/\n
\nInternal structure of the NLMS adaptive filter
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The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.
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The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
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Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
    \n     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    \n 
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The error signal equals the difference between the reference signal d[n] and the filter output: 
    \n     e[n] = d[n] - y[n].    \n 
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After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: 
    \n    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    \n 
 The filter coefficients b[k] are then updated on a sample-by-sample basis: 
    \n     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    \n 
 where mu is the step size and controls the rate of coefficient convergence. 
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In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 
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    \n    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n 
 
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pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 
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    \n    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    \n 
 
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Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 
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Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.
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Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
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  • Sets the values of the internal structure fields.
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  • Zeros out the values in the state buffer. To do this manually without calling the init function, assign the follow subfields of the instance structure: numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. For Q7, Q15, and Q31 the following fields must also be initialized; recipTable, postShift
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Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
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Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. The following issues must be considered:
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  • Scaling of coefficients
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  • Overflow and saturation
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Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.
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Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 
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Function Documentation
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void arm_lms_norm_f32 (arm_lms_norm_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pRef, 
float32_t * pOut, 
float32_t * pErr, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the floating-point normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none. 
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Examples: 
arm_signal_converge_example_f32.c.
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References blockSize, arm_lms_norm_instance_f32::energy, arm_lms_norm_instance_f32::mu, arm_lms_norm_instance_f32::numTaps, arm_lms_norm_instance_f32::pCoeffs, arm_lms_norm_instance_f32::pState, and arm_lms_norm_instance_f32::x0.
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Referenced by main().
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void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 * S, 
uint16_t numTaps, 
float32_t * pCoeffs, 
float32_t * pState, 
float32_t mu, 
uint32_t blockSize 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). 
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Examples: 
arm_signal_converge_example_f32.c.
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References arm_lms_norm_instance_f32::energy, arm_lms_norm_instance_f32::mu, arm_lms_norm_instance_f32::numTaps, arm_lms_norm_instance_f32::pCoeffs, arm_lms_norm_instance_f32::pState, and arm_lms_norm_instance_f32::x0.
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Referenced by main().
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void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 * S, 
uint16_t numTaps, 
q15_t * pCoeffs, 
q15_t * pState, 
q15_t mu, 
uint32_t blockSize, 
uint8_t postShift 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 
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Returns
none.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q15(). 
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References armRecipTableQ15, arm_lms_norm_instance_q15::energy, arm_lms_norm_instance_q15::mu, arm_lms_norm_instance_q15::numTaps, arm_lms_norm_instance_q15::pCoeffs, arm_lms_norm_instance_q15::postShift, arm_lms_norm_instance_q15::pState, arm_lms_norm_instance_q15::recipTable, and arm_lms_norm_instance_q15::x0.
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void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 * S, 
uint16_t numTaps, 
q31_t * pCoeffs, 
q31_t * pState, 
q31_t mu, 
uint32_t blockSize, 
uint8_t postShift 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 
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Returns
none.
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Description: 
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pCoeffs points to the array of filter coefficients stored in time reversed order: 
    \n   {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    \n
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). 
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References armRecipTableQ31, arm_lms_norm_instance_q31::energy, arm_lms_norm_instance_q31::mu, arm_lms_norm_instance_q31::numTaps, arm_lms_norm_instance_q31::pCoeffs, arm_lms_norm_instance_q31::postShift, arm_lms_norm_instance_q31::pState, arm_lms_norm_instance_q31::recipTable, and arm_lms_norm_instance_q31::x0.
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void arm_lms_norm_q15 (arm_lms_norm_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pRef, 
q15_t * pOut, 
q15_t * pErr, 
uint32_t blockSize 
)
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Parameters
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[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: 
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The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.
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In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 
\n\n
References __SIMD32, arm_recip_q15(), blockSize, DELTA_Q15, arm_lms_norm_instance_q15::energy, arm_lms_norm_instance_q15::mu, arm_lms_norm_instance_q15::numTaps, arm_lms_norm_instance_q15::pCoeffs, arm_lms_norm_instance_q15::postShift, arm_lms_norm_instance_q15::pState, arm_lms_norm_instance_q15::recipTable, and arm_lms_norm_instance_q15::x0.
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void arm_lms_norm_q31 (arm_lms_norm_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pRef, 
q31_t * pOut, 
q31_t * pErr, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 
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Returns
none.
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Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.
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In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 
\n\n
References arm_recip_q31(), blockSize, clip_q63_to_q31(), DELTA_Q31, arm_lms_norm_instance_q31::energy, arm_lms_norm_instance_q31::mu, arm_lms_norm_instance_q31::numTaps, arm_lms_norm_instance_q31::pCoeffs, arm_lms_norm_instance_q31::postShift, arm_lms_norm_instance_q31::pState, arm_lms_norm_instance_q31::recipTable, and arm_lms_norm_instance_q31::x0.
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    "content": "\n\n\n\n\nCMSIS-DSP: Linear Interpolate Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Linear Interpolate Example
Examples
  
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 CMSIS DSP Software Library – Linear Interpolate Example 
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 Description  This example demonstrates usage of linear interpolate modules and fast math modules. Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses linear interpolation function and results are compared to reference output. Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.
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Block Diagram:
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\n\"linearInterpExampleMethod1.gif\"/\n
\nMethod 1: Sine caluclation using fast math
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\n\"linearInterpExampleMethod2.gif\"/\n
\nMethod 2: Sine caluclation using interpolation function
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Variables Description:
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  • testInputSin_f32 points to the input values for sine calculation 
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  • testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function 
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  • testOutput points to output buffer calculation from cubic interpolation 
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  • testLinIntOutput points to output buffer calculation from linear interpolation 
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  • snr1 Signal to noise ratio for reference and cubic interpolation output 
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  • snr2 Signal to noise ratio for reference and linear interpolation output
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_linear_interp_example_f32.c 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___linear_interpolate.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Linear Interpolation\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Linear Interpolation
Interpolation Functions
  
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static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
 Process function for the floating-point Linear Interpolation Function.  More...
 
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q31 Linear Interpolation Function.  More...
 
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q15 Linear Interpolation Function.  More...
 
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
 Process function for the Q7 Linear Interpolation Function.  More...
 
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Description
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Linear interpolation is a method of curve fitting using linear polynomials. Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
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\n\"LinearInterp.gif\"/\n
\nLinear interpolation
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A Linear Interpolate function calculates an output value(y), for the input(x) using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
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Algorithm:
\n      y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\n      where x0, x1 are nearest values of input x\n            y0, y1 are nearest values to output y\n
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This set of functions implements Linear interpolation process for Q7, Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the Linear Interpolate function data structure. x is the input sample value. The functions returns the output value.
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if x is outside of the table boundary, Linear interpolation returns first value of the table if x is below input range and returns last value of table if x is above range. 
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Function Documentation
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static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 * S, 
float32_t x 
)
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Parameters
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[in,out]*Sis an instance of the floating-point Linear Interpolation structure 
[in]xinput sample to process 
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Returns
y processed output sample. 
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Examples: 
arm_linear_interp_example_f32.c.
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References arm_linear_interp_instance_f32::nValues, arm_linear_interp_instance_f32::pYData, arm_linear_interp_instance_f32::x1, and arm_linear_interp_instance_f32::xSpacing.
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Referenced by main().
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static __INLINE q15_t arm_linear_interp_q15 (q15_t * pYData, 
q31_t x, 
uint32_t nValues 
)
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Parameters
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[in]*pYDatapointer to Q15 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 
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Returns
y processed output sample.
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Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 
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static __INLINE q31_t arm_linear_interp_q31 (q31_t * pYData, 
q31_t x, 
uint32_t nValues 
)
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Parameters
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[in]*pYDatapointer to Q31 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 
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Returns
y processed output sample.
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Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 
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static __INLINE q7_t arm_linear_interp_q7 (q7_t * pYData, 
q31_t x, 
uint32_t nValues 
)
\n  		\nstatic  
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Parameters
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[in]*pYDatapointer to Q7 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 
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Returns
y processed output sample.
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Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___linear_interpolate.js",
    "content": "var group___linear_interpolate =\n[\n    [ \"arm_linear_interp_f32\", \"group___linear_interpolate.html#ga2269263d810cafcd19681957b37d5cf6\", null ],\n    [ \"arm_linear_interp_q15\", \"group___linear_interpolate.html#ga42c9206e5d2d22b8808716dc30622846\", null ],\n    [ \"arm_linear_interp_q31\", \"group___linear_interpolate.html#ga690e63e9a513ca0a741b1b174805d031\", null ],\n    [ \"arm_linear_interp_q7\", \"group___linear_interpolate.html#gacb0d44fe00aca0ba1d036d469a1763fc\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_add.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Addition\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Matrix Addition
Matrix Functions
  
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arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix addition.  More...
 
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix addition.  More...
 
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix addition.  More...
 
\n
Description
\n
Adds two matrices. 
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\n\"MatrixAddition.gif\"/\n
\nAddition of two 3 x 3 matrices
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The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 
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Function Documentation
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arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
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arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
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Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 
\n\n
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_add.js",
    "content": "var group___matrix_add =\n[\n    [ \"arm_mat_add_f32\", \"group___matrix_add.html#ga04bbf64a5f9c9e57dd1efb26a768aba1\", null ],\n    [ \"arm_mat_add_q15\", \"group___matrix_add.html#ga147e90b7c12a162735ab8824127a33ee\", null ],\n    [ \"arm_mat_add_q31\", \"group___matrix_add.html#ga7d9d7d81a0832a17b831aad1e4a5dc16\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Matrix Example
Examples
  
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Description:
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Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse functions to apply least squares fitting to input data. Least squares fitting is the procedure for finding the best-fitting curve that minimizes the sum of the squares of the offsets (least square error) from a given set of data.
\n
Algorithm:
\n
The linear combination of parameters considered is as follows: 
\n
A * X = B, where X is the unknown value and can be estimated from A & B. 
\n
The least squares estimate X is given by the following equation: 
\n
X = Inverse(AT * A) * AT * B
\n
Block Diagram:
\n
\n\"matrixExample.gif\"/\n
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Variables Description:
\n
    \n
  • A_f32 input matrix in the linear combination equation 
    • \n
  • B_f32 output matrix in the linear combination equation 
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  • X_f32 unknown matrix estimated using A_f32 & B_f32 matrices
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_matrix_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_init.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Initialization\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Matrix Initialization
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void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
 Floating-point matrix initialization.  More...
 
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
 Q15 matrix initialization.  More...
 
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
 Q31 matrix initialization.  More...
 
\n
Description
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Initializes the underlying matrix data structure. The functions set the numRows, numCols, and pData fields of the matrix data structure. 
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Function Documentation
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void arm_mat_init_f32 (arm_matrix_instance_f32 * S, 
uint16_t nRows, 
uint16_t nColumns, 
float32_t * pData 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 
\n  
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Returns
none 
\n
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.
\n
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References arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, and arm_matrix_instance_f32::pData.
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Referenced by main().
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void arm_mat_init_q15 (arm_matrix_instance_q15 * S, 
uint16_t nRows, 
uint16_t nColumns, 
q15_t * pData 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 
\n  
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Returns
none 
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References arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, and arm_matrix_instance_q15::pData.
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void arm_mat_init_q31 (arm_matrix_instance_q31 * S, 
uint16_t nRows, 
uint16_t nColumns, 
q31_t * pData 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 
\n  
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Returns
none 
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References arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, and arm_matrix_instance_q31::pData.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_init.js",
    "content": "var group___matrix_init =\n[\n    [ \"arm_mat_init_f32\", \"group___matrix_init.html#ga11e3dc41592a6401c13182fef9416a27\", null ],\n    [ \"arm_mat_init_q15\", \"group___matrix_init.html#ga31a7c2b991803d49719393eb2d53dc26\", null ],\n    [ \"arm_mat_init_q31\", \"group___matrix_init.html#ga48a5e5d37e1f062cc57fcfaf683343cc\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_inv.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Inverse\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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Matrix Inverse
Matrix Functions
  
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arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix inverse.  More...
 
\n
Description
\n
Computes the inverse of a matrix.
\n
The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). The function checks that the input and output matrices are square and of the same size.
\n
Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix inversion of floating-point matrices.
\n
Algorithm 
The Gauss-Jordan method is used to find the inverse. The algorithm performs a sequence of elementary row-operations till it reduces the input matrix to an identity matrix. Applying the same sequence of elementary row-operations to an identity matrix yields the inverse matrix. If the input matrix is singular, then the algorithm terminates and returns error status ARM_MATH_SINGULAR. 
\n\"MatrixInverse.gif\"/\n
\nMatrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method
\n 
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Function Documentation
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arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 * pSrc, 
arm_matrix_instance_f32 * pDst 
)
\n
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Parameters
\n  \n    \n    \n  
[in]*pSrcpoints to input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size of the output matrix does not match the size of the input matrix. If the input matrix is found to be singular (non-invertible), then the function returns ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS. 
\n
Examples: 
arm_matrix_example_f32.c.
\n
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References ARM_MATH_SINGULAR, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
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Referenced by main().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_inv.js",
    "content": "var group___matrix_inv =\n[\n    [ \"arm_mat_inverse_f32\", \"group___matrix_inv.html#ga542be7aabbf7a2297a4b62cf212910e3\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_mult.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Multiplication\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix multiplication.  More...
 
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
 Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState CMSIS_UNUSED)
 Q15 matrix multiplication.  More...
 
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix multiplication.  More...
 
\n
Description
\n
Multiplies two matrices.
\n
\n\"MatrixMultiplication.gif\"/\n
\nMultiplication of two 3 x 3 matrices
\n
Matrix multiplication is only defined if the number of columns of the first matrix equals the number of rows of the second matrix. Multiplying an M x N matrix with an N x P matrix results in an M x P matrix. When matrix size checking is enabled, the functions check: (1) that the inner dimensions of pSrcA and pSrcB are equal; and (2) that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. 
\n
Function Documentation
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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
\n  
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\n
Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
\n
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.
\n
\n
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
\n\n
Referenced by main().
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arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst, 
q15_t * pState 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 
\n  
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
\n
Scaling and Overflow Behavior:
\n
The difference between the function arm_mat_mult_q15() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.15 x 1.15 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.15 result.
\n
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 16 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.
\n
See arm_mat_mult_q15() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 
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References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
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Scaling and Overflow Behavior:
\n
The difference between the function arm_mat_mult_q31() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.
\n
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.
\n
See arm_mat_mult_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst, 
q15_t *pState CMSIS_UNUSED 
)
\n
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Parameters
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[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
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Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. The inputs to the multiplications are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
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Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
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References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. The input is thus scaled down by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are performed internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
\n
See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
\n\n
References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_mult.js",
    "content": "var group___matrix_mult =\n[\n    [ \"arm_mat_mult_f32\", \"group___matrix_mult.html#ga917bf0270310c1d3f0eda1fc7c0026a0\", null ],\n    [ \"arm_mat_mult_fast_q15\", \"group___matrix_mult.html#ga08f37d93a5bfef0c5000dc5e0a411f93\", null ],\n    [ \"arm_mat_mult_fast_q31\", \"group___matrix_mult.html#ga2785e8c1b785348b0c439b56aaf585a3\", null ],\n    [ \"arm_mat_mult_q15\", \"group___matrix_mult.html#ga3657b99a9667945373e520dbac0f4516\", null ],\n    [ \"arm_mat_mult_q31\", \"group___matrix_mult.html#ga2ec612a8c2c4916477fb9bc1ab548a6e\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_scale.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Scale\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Matrix Scale
Matrix Functions
  
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arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
 Floating-point matrix scaling.  More...
 
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
 Q15 matrix scaling.  More...
 
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
 Q31 matrix scaling.  More...
 
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Description
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Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the matrix by the scalar. For example: 
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\n\"MatrixScale.gif\"/\n
\nMatrix Scaling of a 3 x 3 matrix
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The function checks to make sure that the input and output matrices are of the same size.
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In the fixed-point Q15 and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The overall scale factor applied to the fixed-point data is 
\n
        \n    scale = scaleFract * 2^shift.        \n
 
Function Documentation
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arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 * pSrc, 
float32_t scale, 
arm_matrix_instance_f32 * pDst 
)
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Parameters
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[in]*pSrcpoints to input matrix structure 
[in]scalescale factor to be applied 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
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arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 * pSrc, 
q15_t scaleFract, 
int32_t shift, 
arm_matrix_instance_q15 * pDst 
)
\n
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Parameters
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[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
\n
Scaling and Overflow Behavior: 
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The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 
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References _SIMD32_OFFSET, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 * pSrc, 
q31_t scaleFract, 
int32_t shift, 
arm_matrix_instance_q31 * pDst 
)
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Parameters
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[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
\n
Scaling and Overflow Behavior: 
\n
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_scale.js",
    "content": "var group___matrix_scale =\n[\n    [ \"arm_mat_scale_f32\", \"group___matrix_scale.html#ga9cb4e385b18c9a0b9cbc940c1067ca12\", null ],\n    [ \"arm_mat_scale_q15\", \"group___matrix_scale.html#ga7521769e2cf1c3d9c4656138cd2ae2ca\", null ],\n    [ \"arm_mat_scale_q31\", \"group___matrix_scale.html#ga609743821ee81fa8c34c4bcdc1ed9744\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_sub.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Subtraction\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Matrix Subtraction
Matrix Functions
  
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arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
 Floating-point matrix subtraction.  More...
 
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
 Q15 matrix subtraction.  More...
 
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
 Q31 matrix subtraction.  More...
 
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Description
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Subtract two matrices. 
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\n\"MatrixSubtraction.gif\"/\n
\nSubraction of two 3 x 3 matrices
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The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 
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Function Documentation
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arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 * pSrcA, 
const arm_matrix_instance_f32 * pSrcB, 
arm_matrix_instance_f32 * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
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arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 * pSrcA, 
const arm_matrix_instance_q15 * pSrcB, 
arm_matrix_instance_q15 * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
\n\n
References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 * pSrcA, 
const arm_matrix_instance_q31 * pSrcB, 
arm_matrix_instance_q31 * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_sub.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_trans.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Transpose\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Matrix Transpose
Matrix Functions
  
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arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
 Floating-point matrix transpose.  More...
 
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
 Q15 matrix transpose.  More...
 
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
 Q31 matrix transpose.  More...
 
\n
Description
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Tranposes a matrix. Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. 
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\n\"MatrixTranspose.gif\"/\n
\nTranspose of a 3 x 3 matrix
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Function Documentation
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arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 * pSrc, 
arm_matrix_instance_f32 * pDst 
)
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Parameters
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[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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Examples: 
arm_matrix_example_f32.c.
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_f32::numCols, arm_matrix_instance_f32::numRows, arm_matrix_instance_f32::pData, and status.
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Referenced by main().
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arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 * pSrc, 
arm_matrix_instance_q15 * pDst 
)
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Parameters
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[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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References __SIMD32, ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q15::numCols, arm_matrix_instance_q15::numRows, arm_matrix_instance_q15::pData, and status.
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arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 * pSrc, 
arm_matrix_instance_q31 * pDst 
)
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Parameters
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[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 
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Returns
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 
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References ARM_MATH_SIZE_MISMATCH, ARM_MATH_SUCCESS, arm_matrix_instance_q31::numCols, arm_matrix_instance_q31::numRows, arm_matrix_instance_q31::pData, and status.
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___matrix_trans.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___max.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Maximum\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Maximum
Statistics Functions
  
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\nFunctions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Maximum value of a floating-point vector.  More...
 
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Maximum value of a Q15 vector.  More...
 
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Maximum value of a Q31 vector.  More...
 
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Maximum value of a Q7 vector.  More...
 
\n
Description
\n
Computes the maximum value of an array of data. The function returns both the maximum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 
\n
Function Documentation
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_max_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 
\n  
\n
\n
Returns
none. 
\n
Examples: 
arm_class_marks_example_f32.c, and arm_fft_bin_example_f32.c.
\n
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Referenced by main().
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void arm_max_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 
\n  
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Returns
none. 
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_max_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 
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Returns
none. 
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void arm_max_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult, 
uint32_t * pIndex 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 
\n  
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Returns
none. 
\n\n
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___max.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___min.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Minimum\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Minimum
Statistics Functions
  
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\nFunctions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
 Minimum value of a floating-point vector.  More...
 
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
 Minimum value of a Q15 vector.  More...
 
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
 Minimum value of a Q31 vector.  More...
 
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
 Minimum value of a Q7 vector.  More...
 
\n
Description
\n
Computes the minimum value of an array of data. The function returns both the minimum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 
\n
Function Documentation
\n\n
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void arm_min_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 
\n  
\n
\n
Returns
none. 
\n
Examples: 
arm_class_marks_example_f32.c, and arm_signal_converge_example_f32.c.
\n
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Referenced by main().
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void arm_min_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 
\n  
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Returns
none. 
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void arm_min_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 
\n  
\n
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Returns
none. 
\n\n
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void arm_min_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult, 
uint32_t * pIndex 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 
\n  
\n
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Returns
none. 
\n\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___min.js",
    "content": "var group___min =\n[\n    [ \"arm_min_f32\", \"group___min.html#gaf62b1673740fc516ea64daf777b7d74a\", null ],\n    [ \"arm_min_q15\", \"group___min.html#gad065e37535ebb726750ac1545cb3fa6f\", null ],\n    [ \"arm_min_q31\", \"group___min.html#gab20faeceb5ff5d2d9dd628c2ecf41303\", null ],\n    [ \"arm_min_q7\", \"group___min.html#ga3631d38ac8d715fc14f6f1b343f4c4ed\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___p_i_d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: PID Motor Control\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\nFunctions  
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PID Motor Control
Controller Functions
  
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\nFunctions
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
 Initialization function for the floating-point PID Control.  More...
 
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
 Initialization function for the Q15 PID Control.  More...
 
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
 Initialization function for the Q31 PID Control.  More...
 
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
 Reset function for the floating-point PID Control.  More...
 
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
 Reset function for the Q15 PID Control.  More...
 
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
 Reset function for the Q31 PID Control.  More...
 
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
 Process function for the floating-point PID Control.  More...
 
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
 Process function for the Q31 PID Control.  More...
 
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
 Process function for the Q15 PID Control.  More...
 
\n
Description
\n
A Proportional Integral Derivative (PID) controller is a generic feedback control loop mechanism widely used in industrial control systems. A PID controller is the most commonly used type of feedback controller.
\n
This set of functions implements (PID) controllers for Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the PID control data structure. in is the input sample value. The functions return the output value.
\n
Algorithm:
\n   y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\n   A0 = Kp + Ki + Kd\n   A1 = (-Kp ) - (2 * Kd )\n   A2 = Kd  
\n
where Kp is proportional constant, Ki is Integral constant and Kd is Derivative constant
\n
\n\"PID.gif\"/\n
\nProportional Integral Derivative Controller
\n 
\n
The PID controller calculates an \"error\" value as the difference between the measured output and the reference input. The controller attempts to minimize the error by adjusting the process control inputs. The proportional value determines the reaction to the current error, the integral value determines the reaction based on the sum of recent errors, and the derivative value determines the reaction based on the rate at which the error has been changing.
\n
Instance Structure
The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. A separate instance structure must be defined for each PID Controller. There are separate instance structure declarations for each of the 3 supported data types.
\n
Reset Functions
There is also an associated reset function for each data type which clears the state array.
\n
Initialization Functions
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    \n
  • Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
    • \n
  • Zeros out the values in the state buffer.
    • \n
\n
\n
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
\n
Fixed-Point Behavior
Care must be taken when using the fixed-point versions of the PID Controller functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 
\n
Function Documentation
\n\n
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static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 * S, 
float32_t in 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Sis an instance of the floating-point PID Control structure 
[in]ininput sample to process 
\n  
\n
\n
Returns
out processed output sample. 
\n\n
References arm_pid_instance_f32::A0, arm_pid_instance_f32::A1, arm_pid_instance_f32::A2, and arm_pid_instance_f32::state.
\n\n
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void arm_pid_init_f32 (arm_pid_instance_f32 * S, 
int32_t resetStateFlag 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Spoints to an instance of the PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state & 1 = reset the state. 
\n  
\n
\n
Returns
none. 
\n
Description: 
\n
The resetStateFlag specifies whether to set state to zero or not. 
\n The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 
\n\n
References arm_pid_instance_f32::A0, arm_pid_instance_f32::A1, arm_pid_instance_f32::A2, arm_pid_instance_f32::Kd, arm_pid_instance_f32::Ki, arm_pid_instance_f32::Kp, and arm_pid_instance_f32::state.
\n\n
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void arm_pid_init_q15 (arm_pid_instance_q15 * S, 
int32_t resetStateFlag 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Spoints to an instance of the Q15 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 
\n  
\n
\n
Returns
none. 
\n
Description: 
\n
The resetStateFlag specifies whether to set state to zero or not. 
\n The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 
\n\n
References arm_pid_instance_q15::A0, arm_pid_instance_q15::A1, arm_pid_instance_q15::Kd, arm_pid_instance_q15::Ki, arm_pid_instance_q15::Kp, and arm_pid_instance_q15::state.
\n\n
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void arm_pid_init_q31 (arm_pid_instance_q31 * S, 
int32_t resetStateFlag 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Spoints to an instance of the Q31 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 
\n  
\n
\n
Returns
none. 
\n
Description: 
\n
The resetStateFlag specifies whether to set state to zero or not. 
\n The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 
\n\n
References arm_pid_instance_q31::A0, arm_pid_instance_q31::A1, arm_pid_instance_q31::A2, clip_q63_to_q31(), arm_pid_instance_q31::Kd, arm_pid_instance_q31::Ki, arm_pid_instance_q31::Kp, and arm_pid_instance_q31::state.
\n\n
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\n\n  \n  \n  \n  \n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 * S, 
q15_t in 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Spoints to an instance of the Q15 PID Control structure 
[in]ininput sample to process 
\n  
\n
\n
Returns
out processed output sample.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using a 64-bit internal accumulator. Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 
\n\n
References __SIMD32_CONST, arm_pid_instance_q15::A0, arm_pid_instance_q15::A1, and arm_pid_instance_q15::state.
\n\n
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\n\n  \n  \n  \n  \n
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static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 * S, 
q31_t in 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n  
[in,out]*Spoints to an instance of the Q31 PID Control structure 
[in]ininput sample to process 
\n  
\n
\n
Returns
out processed output sample.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
\n\n
References arm_pid_instance_q31::A0, arm_pid_instance_q31::A1, arm_pid_instance_q31::A2, and arm_pid_instance_q31::state.
\n\n
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\n      \n        \n          \n          \n          \n          \n          \n        \n      
void arm_pid_reset_f32 (arm_pid_instance_f32 * S)
\n
\n
Parameters
\n  \n    \n  
[in]*SInstance pointer of PID control data structure. 
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Returns
none. 
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Description: 
The function resets the state buffer to zeros. 
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References arm_pid_instance_f32::state.
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void arm_pid_reset_q15 (arm_pid_instance_q15 * S)
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Parameters
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[in]*SInstance pointer of PID control data structure. 
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Returns
none. 
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Description: 
The function resets the state buffer to zeros. 
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References arm_pid_instance_q15::state.
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void arm_pid_reset_q31 (arm_pid_instance_q31 * S)
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Parameters
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[in]*SInstance pointer of PID control data structure. 
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Returns
none. 
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Description: 
The function resets the state buffer to zeros. 
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References arm_pid_instance_q31::state.
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    \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___partial_conv.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Partial Convolution\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Partial Convolution
Filtering Functions
  
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\nFunctions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of floating-point sequences.  More...
 
arm_status arm_conv_partial_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.  More...
 
arm_status arm_conv_partial_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q15 sequences.  More...
 
arm_status arm_conv_partial_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2)
 Partial convolution of Q7 sequences.  More...
 
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q15 sequences.  More...
 
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q31 sequences.  More...
 
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
 Partial convolution of Q7 sequences.  More...
 
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Description
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Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. Each function has two additional arguments. firstIndex specifies the starting index of the subset of output samples. numPoints is the number of output samples to compute. The function computes the output in the range [firstIndex, ..., firstIndex+numPoints-1]. The output array pDst contains numPoints values.
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The allowable range of output indices is [0 srcALen+srcBLen-2]. If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. Otherwise the functions return ARM_MATH_SUCCESS. 
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Note
Refer arm_conv_f32() for details on fixed point behavior.
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Fast Versions
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Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires the input signals should be scaled down to avoid intermediate overflows.
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Opt Versions
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Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution 
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Function Documentation
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arm_status arm_conv_partial_f32 (float32_t * pSrcA, 
uint32_t srcALen, 
float32_t * pSrcB, 
uint32_t srcBLen, 
float32_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_fast_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit 
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References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_fast_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 
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References __SIMD32, _SIMD32_OFFSET, ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_fast_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_opt_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen). 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, state buffers should be aligned by 32-bit
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Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
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References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_opt_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints, 
q15_t * pScratch1, 
q15_t * pScratch2 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. 
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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Restrictions 
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit 
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References __PACKq7, __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_q15 (q15_t * pSrcA, 
uint32_t srcALen, 
q15_t * pSrcB, 
uint32_t srcBLen, 
q15_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
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Parameters
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[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
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Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
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Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. 
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References __SIMD32, _SIMD32_OFFSET, ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_q31 (q31_t * pSrcA, 
uint32_t srcALen, 
q31_t * pSrcB, 
uint32_t srcBLen, 
q31_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
\n  
\n
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Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
\n
See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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arm_status arm_conv_partial_q7 (q7_t * pSrcA, 
uint32_t srcALen, 
q7_t * pSrcB, 
uint32_t srcBLen, 
q7_t * pDst, 
uint32_t firstIndex, 
uint32_t numPoints 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 
\n  
\n
\n
Returns
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
\n
Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, srcALen, srcBLen, and status.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___partial_conv.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___r_m_s.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Root mean square (RMS)\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Root mean square (RMS)
Statistics Functions
  
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void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Root Mean Square of the elements of a floating-point vector.  More...
 
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Root Mean Square of the elements of a Q15 vector.  More...
 
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Root Mean Square of the elements of a Q31 vector.  More...
 
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Description
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Calculates the Root Mean Sqaure of the elements in the input vector. The underlying algorithm is used:
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    \n        Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    \n
There are separate functions for floating point, Q31, and Q15 data types. 
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Function Documentation
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void arm_rms_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)
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Parameters
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[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 
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Returns
none. 
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References arm_sqrt_f32(), and blockSize.
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void arm_rms_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)
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Parameters
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[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 
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Returns
none.
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Scaling and Overflow Behavior:
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The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 
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References __SIMD32, arm_sqrt_q15(), and blockSize.
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void arm_rms_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)
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[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 
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Returns
none.
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Scaling and Overflow Behavior:
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The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows, it wraps around and distorts the result. In order to avoid overflows completely, the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 
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References arm_sqrt_q31(), and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___r_m_s.js",
    "content": "var group___r_m_s =\n[\n    [ \"arm_rms_f32\", \"group___r_m_s.html#ga0e3ab1b57da32d45388d1fa90d7fd88c\", null ],\n    [ \"arm_rms_q15\", \"group___r_m_s.html#gaf5b836b72dda9e5dfbbd17c7906fd13f\", null ],\n    [ \"arm_rms_q31\", \"group___r_m_s.html#gae33015fda23fc44e7ead5e5ed7e8d314\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___radix8___c_f_f_t___c_i_f_f_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Radix-8 Complex FFT Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Radix-8 Complex FFT Functions
Transform Functions
  
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Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 
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This set of functions implements CFFT/CIFFT for floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output. Complex input is stored in input buffer in an interleaved fashion.
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The functions operate on blocks of input and output data and each call to the function processes 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values. 
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The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 
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Lengths supported by the transform: 
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Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm and the size of the FFT supported are of the lengths [ 64, 512, 4096].
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Algorithm: 
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Complex Fast Fourier Transform: 
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Input real and imaginary data: 
    \nx(n) = xa + j * ya    \nx(n+N/4 ) = xb + j * yb    \nx(n+N/2 ) = xc + j * yc    \nx(n+3N 4) = xd + j * yd    \n
 where N is length of FFT 
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Output real and imaginary data: 
    \nX(4r) = xa'+ j * ya'    \nX(4r+1) = xb'+ j * yb'    \nX(4r+2) = xc'+ j * yc'    \nX(4r+3) = xd'+ j * yd'    \n
 
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Twiddle factors for Radix-8 FFT: 
    \nWn = co1 + j * (- si1)    \nW2n = co2 + j * (- si2)    \nW3n = co3 + j * (- si3)    \n
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\n\"CFFT.gif\"/\n
\nRadix-8 Decimation-in Frequency Complex Fast Fourier Transform
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Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output. 
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 Butterfly CFFT equations: 
    \nxa' = xa + xb + xc + xd    \nya' = ya + yb + yc + yd    \nxc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    \nyc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    \nxb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    \nyb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    \nxd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    \nyd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    \n
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where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT); bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT;
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Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the CFFT/CIFFT function. Refer to the function specific documentation below for usage guidelines. 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group___real_f_f_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: RealFFT\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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RealFFT
Transform Functions
  
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void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
 Processing function for the floating-point RFFT/RIFFT.  More...
 
void arm_rfft_fast_f32 (arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, uint8_t ifftFlag)
 Processing function for the floating-point real FFT.  More...
 
arm_status arm_rfft_fast_init_f32 (arm_rfft_fast_instance_f32 *S, uint16_t fftLen)
 Initialization function for the floating-point real FFT.  More...
 
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the floating-point RFFT/RIFFT.  More...
 
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q15 RFFT/RIFFT.  More...
 
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
 Initialization function for the Q31 RFFT/RIFFT.  More...
 
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
 Processing function for the Q15 RFFT/RIFFT.  More...
 
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
 Processing function for the Q31 RFFT/RIFFT.  More...
 
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static const float32_t realCoefA [8192]
 
static const float32_t realCoefB [8192]
 
static const q15_t ALIGN4 realCoefAQ15 [8192]
 
static const q15_t ALIGN4 realCoefBQ15 [8192]
 
static const q31_t realCoefAQ31 [8192]
 
static const q31_t realCoefBQ31 [8192]
 
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Description
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Function Documentation
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void arm_rfft_f32 (const arm_rfft_instance_f32 * S, 
float32_t * pSrc, 
float32_t * pDst 
)
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Deprecated:
Do not use this function. It has been superceded by arm_rfft_fast_f32 and will be removed in the future. 
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Parameters
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[in]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 
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Returns
none. 
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References arm_bitreversal_f32(), arm_radix4_butterfly_f32(), arm_radix4_butterfly_inverse_f32(), arm_split_rfft_f32(), arm_split_rifft_f32(), arm_rfft_instance_f32::bitReverseFlagR, arm_cfft_radix4_instance_f32::bitRevFactor, arm_cfft_radix4_instance_f32::fftLen, arm_rfft_instance_f32::fftLenBy2, arm_rfft_instance_f32::ifftFlagR, arm_cfft_radix4_instance_f32::onebyfftLen, arm_cfft_radix4_instance_f32::pBitRevTable, arm_rfft_instance_f32::pCfft, arm_cfft_radix4_instance_f32::pTwiddle, arm_rfft_instance_f32::pTwiddleAReal, arm_rfft_instance_f32::pTwiddleBReal, arm_cfft_radix4_instance_f32::twidCoefModifier, and arm_rfft_instance_f32::twidCoefRModifier.
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void arm_rfft_fast_f32 (arm_rfft_fast_instance_f32 * S, 
float32_t * p, 
float32_t * pOut, 
uint8_t ifftFlag 
)
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Parameters
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[in]*Spoints to an arm_rfft_fast_instance_f32 structure. 
[in]*ppoints to the input buffer. 
[in]*pOutpoints to an arm_rfft_fast_instance_f32 structure. 
[in]ifftFlagRFFT if flag is 0, RIFFT if flag is 1 
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Returns
none. 
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References arm_cfft_f32(), arm_cfft_instance_f32::fftLen, arm_rfft_fast_instance_f32::fftLenRFFT, merge_rfft_f32(), arm_rfft_fast_instance_f32::Sint, and stage_rfft_f32().
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arm_status arm_rfft_fast_init_f32 (arm_rfft_fast_instance_f32 * S, 
uint16_t fftLen 
)
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[in,out]*Spoints to an arm_rfft_fast_instance_f32 structure. 
[in]fftLenlength of the Real Sequence. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
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Description: 
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The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise RFFT is calculated 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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The parameter fftLen Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 16, 32, 64, 128, 256, 512, 1024, 2048, 4096. 
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This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 
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References ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH, armBitRevIndexTable128, armBitRevIndexTable16, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH, armBitRevIndexTable256, armBitRevIndexTable32, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH, armBitRevIndexTable512, armBitRevIndexTable64, ARMBITREVINDEXTABLE_128_TABLE_LENGTH, ARMBITREVINDEXTABLE_256_TABLE_LENGTH, ARMBITREVINDEXTABLE_512_TABLE_LENGTH, ARMBITREVINDEXTABLE__16_TABLE_LENGTH, ARMBITREVINDEXTABLE__32_TABLE_LENGTH, ARMBITREVINDEXTABLE__64_TABLE_LENGTH, arm_cfft_instance_f32::bitRevLength, arm_cfft_instance_f32::fftLen, arm_rfft_fast_instance_f32::fftLenRFFT, arm_cfft_instance_f32::pBitRevTable, arm_rfft_fast_instance_f32::Sint, and status.
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arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 * S, 
arm_cfft_radix4_instance_f32 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)
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Parameters
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[in,out]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
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Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
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Description: 
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The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 
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The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 
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The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
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This function also initializes Twiddle factor table. 
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References arm_cfft_radix4_init_f32(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_f32::bitReverseFlagR, arm_rfft_instance_f32::fftLenBy2, arm_rfft_instance_f32::fftLenReal, arm_rfft_instance_f32::ifftFlagR, arm_rfft_instance_f32::pCfft, arm_rfft_instance_f32::pTwiddleAReal, arm_rfft_instance_f32::pTwiddleBReal, realCoefA, realCoefB, status, and arm_rfft_instance_f32::twidCoefRModifier.
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Referenced by arm_dct4_init_f32().
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arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 * S, 
arm_cfft_radix4_instance_q15 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)
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Parameters
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[in,out]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n  
\n
\n
Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
\n
Description: 
\n
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 
\n
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 
\n
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
\n
This function also initializes Twiddle factor table. 
\n\n
References arm_cfft_radix4_init_q15(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_q15::bitReverseFlagR, arm_rfft_instance_q15::fftLenBy2, arm_rfft_instance_q15::fftLenReal, arm_rfft_instance_q15::ifftFlagR, arm_rfft_instance_q15::pCfft, arm_rfft_instance_q15::pTwiddleAReal, arm_rfft_instance_q15::pTwiddleBReal, realCoefAQ15, realCoefBQ15, status, and arm_rfft_instance_q15::twidCoefRModifier.
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Referenced by arm_dct4_init_q15().
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arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 * S, 
arm_cfft_radix4_instance_q31 * S_CFFT, 
uint32_t fftLenReal, 
uint32_t ifftFlagR, 
uint32_t bitReverseFlag 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in,out]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n  
\n
\n
Returns
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
\n
Description: 
\n
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 
\n
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 
\n
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 
\n
This function also initializes Twiddle factor table. 
\n\n
References arm_cfft_radix4_init_q31(), ARM_MATH_ARGUMENT_ERROR, ARM_MATH_SUCCESS, arm_rfft_instance_q31::bitReverseFlagR, arm_rfft_instance_q31::fftLenBy2, arm_rfft_instance_q31::fftLenReal, arm_rfft_instance_q31::ifftFlagR, arm_rfft_instance_q31::pCfft, arm_rfft_instance_q31::pTwiddleAReal, arm_rfft_instance_q31::pTwiddleBReal, realCoefAQ31, realCoefBQ31, status, and arm_rfft_instance_q31::twidCoefRModifier.
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Referenced by arm_dct4_init_q31().
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void arm_rfft_q15 (const arm_rfft_instance_q15 * S, 
q15_t * pSrc, 
q15_t * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 
\n  
\n
\n
Returns
none.
\n
Input an output formats: 
\n
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 
\n
\n\"RFFTQ15.gif\"/\n
\nInput and Output Formats for Q15 RFFT
\n 
\n
\n\"RIFFTQ15.gif\"/\n
\nInput and Output Formats for Q15 RIFFT
\n 
\n\n
References arm_bitreversal_q15(), arm_radix4_butterfly_inverse_q15(), arm_radix4_butterfly_q15(), arm_split_rfft_q15(), arm_split_rifft_q15(), arm_rfft_instance_q15::bitReverseFlagR, arm_cfft_radix4_instance_q15::bitRevFactor, arm_cfft_radix4_instance_q15::fftLen, arm_rfft_instance_q15::fftLenBy2, arm_rfft_instance_q15::ifftFlagR, arm_cfft_radix4_instance_q15::pBitRevTable, arm_rfft_instance_q15::pCfft, arm_cfft_radix4_instance_q15::pTwiddle, arm_rfft_instance_q15::pTwiddleAReal, arm_rfft_instance_q15::pTwiddleBReal, arm_cfft_radix4_instance_q15::twidCoefModifier, and arm_rfft_instance_q15::twidCoefRModifier.
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void arm_rfft_q31 (const arm_rfft_instance_q31 * S, 
q31_t * pSrc, 
q31_t * pDst 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 
\n  
\n
\n
Returns
none.
\n
Input an output formats: 
\n
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 
\n
\n\"RFFTQ31.gif\"/\n
\nInput and Output Formats for Q31 RFFT
\n
\n
\n\"RIFFTQ31.gif\"/\n
\nInput and Output Formats for Q31 RIFFT
\n 
\n\n
References arm_bitreversal_q31(), arm_radix4_butterfly_inverse_q31(), arm_radix4_butterfly_q31(), arm_split_rfft_q31(), arm_split_rifft_q31(), arm_rfft_instance_q31::bitReverseFlagR, arm_cfft_radix4_instance_q31::bitRevFactor, arm_cfft_radix4_instance_q31::fftLen, arm_rfft_instance_q31::fftLenBy2, arm_rfft_instance_q31::ifftFlagR, arm_cfft_radix4_instance_q31::pBitRevTable, arm_rfft_instance_q31::pCfft, arm_cfft_radix4_instance_q31::pTwiddle, arm_rfft_instance_q31::pTwiddleAReal, arm_rfft_instance_q31::pTwiddleBReal, arm_cfft_radix4_instance_q31::twidCoefModifier, and arm_rfft_instance_q31::twidCoefRModifier.
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Referenced by arm_dct4_q31().
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Variable Documentation
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const float32_t realCoefA[8192]
\n  		\nstatic  
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Generation of realCoefA array: 
\n
n = 4096 
for (i = 0; i < n; i++)    \n {    \n   pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n   pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n } 
 
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Referenced by arm_rfft_init_f32().
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const q15_t ALIGN4 realCoefAQ15[8192]
\n  		\nstatic  
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Generation floating point real_CoefA array: 
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n = 4096 
for (i = 0; i < n; i++)    \n {    \n   pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n   pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n } 
 
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Convert to fixed point Q15 format round(pATable[i] * pow(2, 15)) 
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Referenced by arm_rfft_init_q15().
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const q31_t realCoefAQ31[8192]
\n  		\nstatic  
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Generation floating point realCoefAQ31 array: 
\n
n = 4096 
for (i = 0; i < n; i++)    \n{    \n   pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    \n   pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n}
 
\n
Convert to fixed point Q31 format round(pATable[i] * pow(2, 31)) 
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Referenced by arm_rfft_init_q31().
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const float32_t realCoefB[8192]
\n  		\nstatic  
\n
\n
Generation of realCoefB array: 
\n
n = 4096 
for (i = 0; i < n; i++)    \n{    \n   pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n   pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n } 
 
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Referenced by arm_rfft_init_f32().
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const q15_t ALIGN4 realCoefBQ15[8192]
\n  		\nstatic  
\n
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Generation of real_CoefB array: 
\n
n = 4096 
for (i = 0; i < n; i++)    \n {    \n   pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n   pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n } 
 
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Convert to fixed point Q15 format round(pBTable[i] * pow(2, 15)) 
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Referenced by arm_rfft_init_q15().
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const q31_t realCoefBQ31[8192]
\n  		\nstatic  
\n
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Generation of realCoefBQ31 array: 
\n
n = 4096 
for (i = 0; i < n; i++)    \n{    \n   pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    \n   pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    \n} 
 
\n
Convert to fixed point Q31 format round(pBTable[i] * pow(2, 31)) 
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Referenced by arm_rfft_init_q31().
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___real_f_f_t.js",
    "content": "var group___real_f_f_t =\n[\n    [ \"arm_rfft_f32\", \"group___real_f_f_t.html#ga3df1766d230532bc068fc4ed69d0fcdc\", null ],\n    [ \"arm_rfft_fast_f32\", \"group___real_f_f_t.html#ga180d8b764d59cbb85d37a2d5f7cd9799\", null ],\n    [ \"arm_rfft_fast_init_f32\", \"group___real_f_f_t.html#gac5fceb172551e7c11eb4d0e17ef15aa3\", null ],\n    [ \"arm_rfft_init_f32\", \"group___real_f_f_t.html#ga10717ee326bf50832ef1c25b85a23068\", null ],\n    [ \"arm_rfft_init_q15\", \"group___real_f_f_t.html#ga2530ebf44b7f5b559b191ff7265a9120\", null ],\n    [ \"arm_rfft_init_q31\", \"group___real_f_f_t.html#ga8b9c7f99f3c368c82048cd1899acbbd5\", null ],\n    [ \"arm_rfft_q15\", \"group___real_f_f_t.html#ga00e615f5db21736ad5b27fb6146f3fc5\", null ],\n    [ \"arm_rfft_q31\", \"group___real_f_f_t.html#gabaeab5646aeea9844e6d42ca8c73fe3a\", null ],\n    [ \"realCoefA\", \"group___real_f_f_t.html#ga8b1ad947c470596674fa3364e16045c6\", null ],\n    [ \"realCoefAQ15\", \"group___real_f_f_t.html#ga11e84d0ee257a547f749b37dd0078d36\", null ],\n    [ \"realCoefAQ31\", \"group___real_f_f_t.html#gaf1592a6cf0504675205074a43c3728a2\", null ],\n    [ \"realCoefB\", \"group___real_f_f_t.html#gac52f98b52a1f03bfac8b57a67ba07397\", null ],\n    [ \"realCoefBQ15\", \"group___real_f_f_t.html#gac871666f018b70938b2b98017628cb97\", null ],\n    [ \"realCoefBQ31\", \"group___real_f_f_t.html#ga1eb5745728a61c3715755f5d69a4a960\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___s_q_r_t.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Square Root\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Square Root
Fast Math Functions
  
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\nFunctions
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
 Q15 square root function.  More...
 
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
 Q31 square root function.  More...
 
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
 Floating-point square root function.  More...
 
\n
Description
\n
Computes the square root of a number. There are separate functions for Q15, Q31, and floating-point data types. The square root function is computed using the Newton-Raphson algorithm. This is an iterative algorithm of the form: 
\n
\n     x1 = x0 - f(x0)/f'(x0)\n
 where x1 is the current estimate, x0 is the previous estimate, and f'(x0) is the derivative of f() evaluated at x0. For the square root function, the algorithm reduces to: 
\n
\n    x0 = in/2                         [initial guess]\n    x1 = 1/2 * ( x0 + in / x0)        [each iteration]\n
 
Function Documentation
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static __INLINE arm_status arm_sqrt_f32 (float32_t in, 
float32_t * pOut 
)
\n  		\nstatic  
\n
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Parameters
\n  \n    \n    \n  
[in]ininput value. 
[out]*pOutsquare root of input value. 
\n  
\n
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Returns
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 
\n\n
References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.
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Referenced by arm_cmplx_mag_f32(), arm_rms_f32(), and arm_std_f32().
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arm_status arm_sqrt_q15 (q15_t in, 
q15_t * pOut 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]ininput value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. 
[out]*pOutsquare root of input value. 
\n  
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Returns
The function returns ARM_MATH_SUCCESS if the input value is positive and ARM_MATH_ARGUMENT_ERROR if the input is negative. For negative inputs, the function returns *pOut = 0.
\n
Parameters
\n  \n    \n    \n  
[in]ininput value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. 
[out]*pOutsquare root of input value. 
\n  
\n
\n
Returns
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 
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References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.
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Referenced by arm_cmplx_mag_q15(), arm_rms_q15(), and arm_std_q15().
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arm_status arm_sqrt_q31 (q31_t in, 
q31_t * pOut 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]ininput value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
[out]*pOutsquare root of input value. 
\n  
\n
\n
Returns
The function returns ARM_MATH_SUCCESS if the input value is positive and ARM_MATH_ARGUMENT_ERROR if the input is negative. For negative inputs, the function returns *pOut = 0.
\n
Parameters
\n  \n    \n    \n  
[in]ininput value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
[out]*pOutsquare root of input value. 
\n  
\n
\n
Returns
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 
\n\n
References ARM_MATH_ARGUMENT_ERROR, and ARM_MATH_SUCCESS.
\n\n
Referenced by arm_cmplx_mag_q31(), arm_rms_q31(), and arm_std_q31().
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___s_t_d.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Standard deviation\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Standard deviation
Statistics Functions
  
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void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Standard deviation of the elements of a floating-point vector.  More...
 
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Standard deviation of the elements of a Q15 vector.  More...
 
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Standard deviation of the elements of a Q31 vector.  More...
 
\n
Description
\n
Calculates the standard deviation of the elements in the input vector. The underlying algorithm is used:
\n
    \n        Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
        where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
                        sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   \n
There are separate functions for floating point, Q31, and Q15 data types. 
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Function Documentation
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void arm_std_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 
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Returns
none. 
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Examples: 
arm_class_marks_example_f32.c.
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References arm_sqrt_f32(), blockSize, mean, and var.
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void arm_std_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)
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Parameters
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[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 
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Returns
none.
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Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 
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References __SIMD32, arm_sqrt_q15(), blockSize, and mean.
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void arm_std_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)
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Parameters
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[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 
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Returns
none.
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Scaling and Overflow Behavior:
\n
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 
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References arm_sqrt_q31(), blockSize, and mean.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___s_t_d.js",
    "content": "var group___s_t_d =\n[\n    [ \"arm_std_f32\", \"group___s_t_d.html#ga4969b5b5f3d001377bc401a3ee99dfc2\", null ],\n    [ \"arm_std_q15\", \"group___s_t_d.html#gaf9d27afa9928ff28a63cd98ea9218a72\", null ],\n    [ \"arm_std_q31\", \"group___s_t_d.html#ga39495e74f96116178be085c9dc7742f5\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___signal_convergence.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Signal Convergence Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Signal Convergence Example
Examples
  
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Description:
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Demonstrates the ability of an adaptive filter to \"learn\" the transfer function of a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse Response (FIR) Filter, and Basic Math Functions.
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Algorithm:
\n
The figure below illustrates the signal flow in this example. Uniformly distributed white noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the reference input of the adaptive filter (normalized LMS filter). The white noise is input to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and (2) the error signal which is the difference between the adaptive filter and the reference output of the FIR filter. Over time as the adaptive filter learns the transfer function of the FIR filter, the first output approaches the reference output of the FIR filter, and the error signal approaches zero. 
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The adaptive filter converges properly even if the input signal has a large dynamic range (i.e., varies from small to large values). The coefficients of the adaptive filter are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() implements the stopping condition. The function checks if all of the values of the error signal have a magnitude below a threshold DELTA.
\n
Block Diagram:
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\n\"SignalFlow.gif\"/\n
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Variables Description:
\n
    \n
  • testInput_f32 points to the input data 
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  • firStateF32 points to FIR state buffer 
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  • lmsStateF32 points to Normalised Least mean square FIR filter state buffer 
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  • FIRCoeff_f32 points to coefficient buffer 
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  • lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer 
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  • wire1, wir2, wire3 temporary buffers 
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  • errOutput, err_signal temporary error buffers
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_signal_converge_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___sin_cos.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Sine Cosine\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Sine Cosine
Controller Functions
  
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void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
 Floating-point sin_cos function.  More...
 
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
 Q31 sin_cos function.  More...
 
\n\n\n\n\n\n\n\n\n\n
\nVariables
static const float32_t cosTable [360]
 
static const float32_t sinTable [360]
 
static const int32_t sinTableQ31 [360]
 
static const int32_t cosTableQ31 [360]
 
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Description
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Computes the trigonometric sine and cosine values using a combination of table lookup and linear interpolation. There are separate functions for Q31 and floating-point data types. The input to the floating-point version is in degrees while the fixed-point Q31 have a scaled input with the range [-1 0.9999] mapping to [-180 179] degrees.
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The implementation is based on table lookup using 360 values together with linear interpolation. The steps used are:
\n
    \n
  1. Calculation of the nearest integer table index.
    2. \n
  2. Compute the fractional portion (fract) of the input.
    3. \n
  3. Fetch the value corresponding to index from sine table to y0 and also value from index+1 to y1.
    4. \n
  4. Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).
    5. \n
  5. Fetch the value corresponding to index from cosine table to y0 and also value from index+1 to y1.
    6. \n
  6. Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)). 
    7. \n
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Function Documentation
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void arm_sin_cos_f32 (float32_t theta, 
float32_t * pSinVal, 
float32_t * pCosVal 
)
\n
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Parameters
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[in]thetainput value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cos output. 
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Returns
none. 
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References cosTable, and sinTable.
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void arm_sin_cos_q31 (q31_t theta, 
q31_t * pSinVal, 
q31_t * pCosVal 
)
\n
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Parameters
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[in]thetascaled input value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cosine output. 
\n  
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Returns
none.
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The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. 
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References cosTableQ31, INPUT_SPACING, and sinTableQ31.
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Variable Documentation
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const float32_t cosTable[360]
\n  		\nstatic  
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\n
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)    \n{    \n   cosTable[i]= cos((i-180) * PI/180.0);    \n} 
 
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Referenced by arm_sin_cos_f32().
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const int32_t cosTableQ31[360]
\n  		\nstatic  
\n
\n
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)    \n{    \n   cosTable[i]= cos((i-180) * PI/180.0);    \n} 
 
\n
Convert above coefficients to fixed point 1.31 format. 
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Referenced by arm_sin_cos_q31().
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const float32_t sinTable[360]
\n  		\nstatic  
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\n
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)    \n{    \n   sinTable[i]= sin((i-180) * PI/180.0);    \n} 
 
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Referenced by arm_sin_cos_f32().
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const int32_t sinTableQ31[360]
\n  		\nstatic  
\n
\n
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)    \n{    \n   sinTable[i]= sin((i-180) * PI/180.0);    \n} 
 Convert above coefficients to fixed point 1.31 format. 
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Referenced by arm_sin_cos_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___sin_cos.js",
    "content": "var group___sin_cos =\n[\n    [ \"arm_sin_cos_f32\", \"group___sin_cos.html#ga4420d45c37d58c310ef9ae1b5fe58020\", null ],\n    [ \"arm_sin_cos_q31\", \"group___sin_cos.html#gae9e4ddebff9d4eb5d0a093e28e0bc504\", null ],\n    [ \"cosTable\", \"group___sin_cos.html#ga73d46b72b2e2e5c3301adb7a8a7cab5e\", null ],\n    [ \"cosTableQ31\", \"group___sin_cos.html#gab3ca1fd1431d146c6bde7d39dd7e903d\", null ],\n    [ \"sinTable\", \"group___sin_cos.html#ga2e70480fd73eae93d51a6e881bb1f2e4\", null ],\n    [ \"sinTableQ31\", \"group___sin_cos.html#ga77c2ec4c8f210d254ef0fbeea0bdf067\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___sin_cos_example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: SineCosine Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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SineCosine Example
Examples
  
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Description:
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Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector Multiplication, and Vector Addition functions.
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Algorithm:
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Mathematically, the Pythagorean trignometric identity is defined by the following equation: 
sin(x) * sin(x) + cos(x) * cos(x) = 1
 where x is the angle in radians.
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Block Diagram:
\n
\n\"sinCos.gif\"/\n
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Variables Description:
\n
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  • testInput_f32 array of input angle in radians 
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  • testOutput stores sum of the squares of sine and cosine values of input angle
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_sin_cos_example_f32.c 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group___variance_example.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Variance Example\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Variance Example
Examples
  
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Description:
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Demonstrates the use of Basic Math and Support Functions to calculate the variance of an input sequence with N samples. Uniformly distributed white noise is taken as input.
\n
Algorithm:
\n
The variance of a sequence is the mean of the squared deviation of the sequence from its mean. 
\n
This is denoted by the following equation: 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
 where, x[n] is the input sequence, N is the number of input samples, and x' is the mean value of the input sequence, x[n]. 
\n
The mean value x' is defined as: 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
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Block Diagram:
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\n\"Variance.gif\"/\n
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Variables Description:
\n
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  • testInput_f32 points to the input data 
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  • refVarianceOut reference variance value
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CMSIS DSP Software Library Functions Used:
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 Refer  arm_variance_example_f32.c 
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  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__clarke.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Clarke Transform\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Vector Clarke Transform
Controller Functions
  
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static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
 Floating-point Clarke transform.  More...
 
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
 Clarke transform for Q31 version.  More...
 
\n
Description
\n
Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents in the two-phase orthogonal stator axis Ialpha and Ibeta. When Ialpha is superposed with Ia as shown in the figure below 
\n
\n\"clarke.gif\"/\n
\nStator current space vector and its components in (a,b).
\n
 and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta can be calculated using only Ia and Ib.
\n
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 
\n
Algorithm
\n\"clarkeFormula.gif\"/\n
\n where Ia and Ib are the instantaneous stator phases and pIalpha and pIbeta are the two coordinates of time invariant vector. 
\n
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 
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Function Documentation
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static __INLINE void arm_clarke_f32 (float32_t Ia, 
float32_t Ib, 
float32_t * pIalpha, 
float32_t * pIbeta 
)
\n  		\nstatic  
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Parameters
\n  \n    \n    \n    \n    \n  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
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none. 
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static __INLINE void arm_clarke_q31 (q31_t Ia, 
q31_t Ib, 
q31_t * pIalpha, 
q31_t * pIbeta 
)
\n  		\nstatic  
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__clarke.js",
    "content": "var group__clarke =\n[\n    [ \"arm_clarke_f32\", \"group__clarke.html#ga2b4ebec76215e1277c970c269ffdbd76\", null ],\n    [ \"arm_clarke_q31\", \"group__clarke.html#ga7fd106ca8d346a2a472842e0656014c1\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__conj.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex Conjugate\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Complex Conjugate
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\nFunctions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex conjugate.  More...
 
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex conjugate.  More...
 
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex conjugate.  More...
 
\n
Description
\n
Conjugates the elements of a complex data vector.
\n
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values. The underlying algorithm is used:
\n
        \nfor(n=0; n<numSamples; n++) {        \n    pDst[(2*n)+0)] = pSrc[(2*n)+0];     // real part        \n    pDst[(2*n)+1)] = -pSrc[(2*n)+1];    // imag part        \n}        \n
There are separate functions for floating-point, Q15, and Q31 data types. 
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Function Documentation
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void arm_cmplx_conj_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 
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Returns
none. 
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void arm_cmplx_conj_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 
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Returns
none.
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Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 
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References __SIMD32.
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void arm_cmplx_conj_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
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*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__conj.js",
    "content": "var group__cmplx__conj =\n[\n    [ \"arm_cmplx_conj_f32\", \"group__cmplx__conj.html#ga3a102aead6460ad9fcb0626f6b226ffb\", null ],\n    [ \"arm_cmplx_conj_q15\", \"group__cmplx__conj.html#gaf47689ae07962acaecb8ddde556df4a4\", null ],\n    [ \"arm_cmplx_conj_q31\", \"group__cmplx__conj.html#gafecc94879a383c5208ec3ef99485e4b5\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__dot__prod.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex Dot Product\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Complex Dot Product
Complex Math Functions
  
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\nFunctions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
 Floating-point complex dot product.  More...
 
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
 Q15 complex dot product.  More...
 
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
 Q31 complex dot product.  More...
 
\n
Description
\n
Computes the dot product of two complex vectors. The vectors are multiplied element-by-element and then summed.
\n
The pSrcA points to the first complex input vector and pSrcB points to the second complex input vector. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values.
\n
The underlying algorithm is used: 
\n
    \nrealResult=0;    \nimagResult=0;    \nfor(n=0; n<numSamples; n++) {    \n    realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];    \n    imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];    \n}    \n
There are separate functions for floating-point, Q15, and Q31 data types. 
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Function Documentation
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void arm_cmplx_dot_prod_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
uint32_t numSamples, 
float32_t * realResult, 
float32_t * imagResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 
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Returns
none. 
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void arm_cmplx_dot_prod_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
uint32_t numSamples, 
q31_t * realResult, 
q31_t * imagResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 64-bit accumulator. The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. These are accumulated in a 64-bit accumulator with 34.30 precision. As a final step, the accumulators are converted to 8.24 format. The return results realResult and imagResult are in 8.24 format. 
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void arm_cmplx_dot_prod_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
uint32_t numSamples, 
q63_t * realResult, 
q63_t * imagResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 
\n  
\n
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 64-bit accumulator. The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. The return results realResult and imagResult are in 16.48 format. Input down scaling is not required. 
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__dot__prod.js",
    "content": "var group__cmplx__dot__prod =\n[\n    [ \"arm_cmplx_dot_prod_f32\", \"group__cmplx__dot__prod.html#gadcfaf567a25eb641da4043eafb9bb076\", null ],\n    [ \"arm_cmplx_dot_prod_q15\", \"group__cmplx__dot__prod.html#ga2b08b5e8001d2c15204639d00893fc70\", null ],\n    [ \"arm_cmplx_dot_prod_q31\", \"group__cmplx__dot__prod.html#ga5b731a59db062a9ad84562ef68a6c8af\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__mag.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex Magnitude\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Complex Magnitude
Complex Math Functions
  
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void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude.  More...
 
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude.  More...
 
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude.  More...
 
\n
Description
\n
Computes the magnitude of the elements of a complex data vector.
\n
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values. The underlying algorithm is used:
\n
    \nfor(n=0; n<numSamples; n++) {    \n    pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);    \n}    \n
There are separate functions for floating-point, Q15, and Q31 data types. 
\n
Function Documentation
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void arm_cmplx_mag_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to complex input buffer 
[out]*pDstpoints to real output buffer 
[in]numSamplesnumber of complex samples in the input vector 
\n  
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Returns
none. 
\n
Examples: 
arm_fft_bin_example_f32.c.
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References arm_sqrt_f32().
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Referenced by main().
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void arm_cmplx_mag_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 
\n  
\n
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. 
\n\n
References __SIMD32, and arm_sqrt_q15().
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void arm_cmplx_mag_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 
\n  
\n
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. Input down scaling is not required. 
\n\n
References arm_sqrt_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__mag.js",
    "content": "var group__cmplx__mag =\n[\n    [ \"arm_cmplx_mag_f32\", \"group__cmplx__mag.html#gae45024c497392cde2ae358a76d435213\", null ],\n    [ \"arm_cmplx_mag_q15\", \"group__cmplx__mag.html#ga0a4a8f77a6a51d9b3f3b9d729f85b7a4\", null ],\n    [ \"arm_cmplx_mag_q31\", \"group__cmplx__mag.html#ga14f82f9230e9d96d5b9774e2fefcb7be\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__mag__squared.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex Magnitude Squared\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Complex Magnitude Squared
Complex Math Functions
  
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void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
 Floating-point complex magnitude squared.  More...
 
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
 Q15 complex magnitude squared.  More...
 
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
 Q31 complex magnitude squared.  More...
 
\n
Description
\n
Computes the magnitude squared of the elements of a complex data vector.
\n
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values.
\n
The underlying algorithm is used:
\n
        \nfor(n=0; n<numSamples; n++) {        \n    pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;        \n}        \n
There are separate functions for floating-point, Q15, and Q31 data types. 
\n
Function Documentation
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void arm_cmplx_mag_squared_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the complex input vector 
[out]*pDstpoints to the real output vector 
[in]numSamplesnumber of complex samples in the input vector 
\n  
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Returns
none. 
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void arm_cmplx_mag_squared_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 
\n  
\n
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 
\n\n
References __SIMD32.
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void arm_cmplx_mag_squared_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t numSamples 
)
\n
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Parameters
\n  \n    \n    \n    \n  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 
\n  
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Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cmplx__mag__squared.js",
    "content": "var group__cmplx__mag__squared =\n[\n    [ \"arm_cmplx_mag_squared_f32\", \"group__cmplx__mag__squared.html#gaa7faccc0d96b061d8b7d0d7d82045074\", null ],\n    [ \"arm_cmplx_mag_squared_q15\", \"group__cmplx__mag__squared.html#ga45537f576102d960d467eb722b8431f2\", null ],\n    [ \"arm_cmplx_mag_squared_q31\", \"group__cmplx__mag__squared.html#ga384b0538101e8c03fa4fa14271e63b04\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__copy.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Copy\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Vector Copy
Support Functions
  
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void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Copies the elements of a floating-point vector.  More...
 
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Copies the elements of a Q15 vector.  More...
 
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Copies the elements of a Q31 vector.  More...
 
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Copies the elements of a Q7 vector.  More...
 
\n
Description
\n
Copies sample by sample from source vector to destination vector.
\n
    \n        pDst[n] = pSrc[n];   0 <= n < blockSize.    \n
There are separate functions for floating point, Q31, Q15, and Q7 data types. 
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Function Documentation
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void arm_copy_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 
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Returns
none. 
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Examples: 
arm_convolution_example_f32.c, arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.
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References blockSize.
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Referenced by main().
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void arm_copy_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 
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Returns
none. 
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References __SIMD32, and blockSize.
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Referenced by arm_conv_fast_opt_q15(), arm_conv_opt_q15(), arm_conv_partial_fast_opt_q15(), arm_conv_partial_opt_q15(), arm_correlate_fast_opt_q15(), and arm_correlate_opt_q15().
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void arm_copy_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 
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Returns
none. 
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References blockSize.
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void arm_copy_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 
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Returns
none. 
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References __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__copy.js",
    "content": "var group__copy =\n[\n    [ \"arm_copy_f32\", \"group__copy.html#gadd1f737e677e0e6ca31767c7001417b3\", null ],\n    [ \"arm_copy_q15\", \"group__copy.html#ga872ca4cfc18c680b8991ccd569a5fda0\", null ],\n    [ \"arm_copy_q31\", \"group__copy.html#gaddf70be7e3f87e535c324862b501f3f9\", null ],\n    [ \"arm_copy_q7\", \"group__copy.html#ga467579beda492aa92797529d794c88fb\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cos.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Cosine\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Cosine
Fast Math Functions
  
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float32_t arm_cos_f32 (float32_t x)
 Fast approximation to the trigonometric cosine function for floating-point data.  More...
 
q15_t arm_cos_q15 (q15_t x)
 Fast approximation to the trigonometric cosine function for Q15 data.  More...
 
q31_t arm_cos_q31 (q31_t x)
 Fast approximation to the trigonometric cosine function for Q31 data.  More...
 
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\nVariables
static const float32_t cosTable [260]
 
static const q15_t cosTableQ15 [259]
 
static const q31_t cosTableQ31 [259]
 
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Description
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Computes the trigonometric cosine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a value of 2*pi wraps around to 0.
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The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:
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  1. Calculation of the nearest integer table index
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  2. Fetch the four table values a, b, c, and d
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  3. Compute the fractional portion (fract) of the table index.
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  4. Calculation of wa, wb, wc, wd
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  5. The final result equals a*wa + b*wb + c*wc + d*wd
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where 
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    \n   a=Table[index-1];    \n   b=Table[index+0];    \n   c=Table[index+1];    \n   d=Table[index+2];    \n
 and 
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    \n   wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    \n   wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    \n   wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    \n   wd=(1/6)*fract.^3 - (1/6)*fract;    \n
 
Function Documentation
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float32_t arm_cos_f32 (float32_t x)
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Parameters
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[in]xinput value in radians. 
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Returns
cos(x). 
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Examples: 
arm_sin_cos_example_f32.c.
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References cosTable, and TABLE_SIZE.
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Referenced by main().
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q15_t arm_cos_q15 (q15_t x)
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Parameters
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[in]xScaled input value in radians. 
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Returns
cos(x).
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The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). 
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References cosTableQ15, and TABLE_SPACING_Q15.
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q31_t arm_cos_q31 (q31_t x)
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Parameters
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[in]xScaled input value in radians. 
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Returns
cos(x).
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The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). 
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References cosTableQ31, and TABLE_SPACING_Q31.
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Variable Documentation
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const float32_t cosTable[260]
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Example code for Generation of Cos Table: 
\ntableSize = 256;    \nfor(n = -1; n < (tableSize + 2); n++)    \n{    \n      cosTable[n+1]= cos(2*pi*n/tableSize);    \n} 
 where pi value is 3.14159265358979 
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Referenced by arm_cos_f32().
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const q15_t cosTableQ15[259]
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Table values are in Q15 (1.15 fixed-point format) and generation is done in three steps. First, generate cos values in floating point: 
\n tableSize = 256;\n for(n = -1; n < (tableSize + 1); n++)    \n {    \n        cosTable[n+1]= cos(2*pi*n/tableSize);    \n } 
 where pi value is 3.14159265358979 
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Second, convert floating-point to Q15 (fixed-point): (cosTable[i] * pow(2, 15)) 
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Finally, round to the nearest integer value: cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 
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Referenced by arm_cos_q15().
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const q31_t cosTableQ31[259]
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Table values are in Q31 (1.31 fixed-point format) and generation is done in three steps. First, generate cos values in floating point: 
\ntableSize = 256;      \nfor(n = -1; n < (tableSize + 1); n++)    \n{    \n     cosTable[n+1]= cos(2*pi*n/tableSize);    \n} 
 where pi value is 3.14159265358979 
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Second, convert floating-point to Q31 (Fixed point): (cosTable[i] * pow(2, 31)) 
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Finally, round to the nearest integer value: cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 
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Referenced by arm_cos_q31().
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__cos.js",
    "content": "var group__cos =\n[\n    [ \"arm_cos_f32\", \"group__cos.html#gace15287f9c64b9b4084d1c797d4c49d8\", null ],\n    [ \"arm_cos_q15\", \"group__cos.html#gadfd60c24def501638c0d5db20f4c869b\", null ],\n    [ \"arm_cos_q31\", \"group__cos.html#gad80f121949ef885a77d83ab36e002567\", null ],\n    [ \"cosTable\", \"group__cos.html#gac597d7d00485bea7080b318b4473e83f\", null ],\n    [ \"cosTableQ15\", \"group__cos.html#ga012ad965e3493ffcc6dd7f9a12569e58\", null ],\n    [ \"cosTableQ31\", \"group__cos.html#gafe999a5fcf1774a2292220071096b834\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__dot__prod.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Dot Product\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Vector Dot Product
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void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
 Dot product of floating-point vectors.  More...
 
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q15 vectors.  More...
 
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
 Dot product of Q31 vectors.  More...
 
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
 Dot product of Q7 vectors.  More...
 
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Description
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Computes the dot product of two vectors. The vectors are multiplied element-by-element and then summed.
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\n    sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]\n
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
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Function Documentation
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void arm_dot_prod_f32 (float32_t * pSrcA, 
float32_t * pSrcB, 
uint32_t blockSize, 
float32_t * result 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 
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Returns
none. 
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Examples: 
arm_variance_example_f32.c.
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References blockSize.
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Referenced by main().
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void arm_dot_prod_q15 (q15_t * pSrcA, 
q15_t * pSrcB, 
uint32_t blockSize, 
q63_t * result 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 
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Returns
none.
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Scaling and Overflow Behavior: 
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The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these results are added to a 64-bit accumulator in 34.30 format. Nonsaturating additions are used and given that there are 33 guard bits in the accumulator there is no risk of overflow. The return result is in 34.30 format. 
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References __SIMD32, and blockSize.
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void arm_dot_prod_q31 (q31_t * pSrcA, 
q31_t * pSrcB, 
uint32_t blockSize, 
q63_t * result 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 
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Returns
none.
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Scaling and Overflow Behavior: 
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The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these are truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. There are 15 guard bits in the accumulator and there is no risk of overflow as long as the length of the vectors is less than 2^16 elements. The return result is in 16.48 format. 
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References blockSize.
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void arm_dot_prod_q7 (q7_t * pSrcA, 
q7_t * pSrcB, 
uint32_t blockSize, 
q31_t * result 
)
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Parameters
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[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 
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Returns
none.
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Scaling and Overflow Behavior: 
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The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these results are added to an accumulator in 18.14 format. Nonsaturating additions are used and there is no danger of wrap around as long as the vectors are less than 2^18 elements long. The return result is in 18.14 format. 
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References __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__dot__prod.js",
    "content": "var group__dot__prod =\n[\n    [ \"arm_dot_prod_f32\", \"group__dot__prod.html#ga55418d4362f6ba84c327f9b4f089a8c3\", null ],\n    [ \"arm_dot_prod_q15\", \"group__dot__prod.html#ga436d5bed28a4b73b24acbde436a3044b\", null ],\n    [ \"arm_dot_prod_q31\", \"group__dot__prod.html#gab15d8fa060fc85b4d948d091b7deaa11\", null ],\n    [ \"arm_dot_prod_q7\", \"group__dot__prod.html#ga9c3293a50ac7ec8ba928bf8e3aaea6c1\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__float__to__x.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Convert 32-bit floating point value\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Convert 32-bit floating point value
Support Functions
  
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void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q15 vector.  More...
 
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q31 vector.  More...
 
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the floating-point vector to Q7 vector.  More...
 
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Description
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Function Documentation
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void arm_float_to_q15 (float32_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 
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Returns
none.
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Description: 
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The equation used for the conversion process is: 
    \n        pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    \n
 
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Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
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Note
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 
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References blockSize.
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void arm_float_to_q31 (float32_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
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Parameters
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[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 
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Returns
none.
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Description: 
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The equation used for the conversion process is:
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    \n        pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    \n 
 Scaling and Overflow Behavior: 
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The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
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Note
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 
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Examples: 
arm_graphic_equalizer_example_q31.c.
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References blockSize, and clip_q63_to_q31().
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Referenced by main().
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void arm_float_to_q7 (float32_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 
\n  
\n
\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is: 
    \n        pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    \n 
 
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 
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Note
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 
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References blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__float__to__x.js",
    "content": "var group__float__to__x =\n[\n    [ \"arm_float_to_q15\", \"group__float__to__x.html#ga215456e35a18db86882e1d3f0d24e1f2\", null ],\n    [ \"arm_float_to_q31\", \"group__float__to__x.html#ga177704107f94564e9abe4daaa36f4554\", null ],\n    [ \"arm_float_to_q7\", \"group__float__to__x.html#ga44a393818cdee8dce80f2d66add25411\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_cmplx_math.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Complex Math Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Complex Math Functions
  
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 Complex Conjugate
 
 Complex Dot Product
 
 Complex Magnitude
 
 Complex Magnitude Squared
 
 Complex-by-Complex Multiplication
 
 Complex-by-Real Multiplication
 
\n
Description
\n
This set of functions operates on complex data vectors. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). In the API functions, the number of samples in a complex array refers to the number of complex values; the array contains twice this number of real values. 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_cmplx_math.js",
    "content": "var group__group_cmplx_math =\n[\n    [ \"Complex Conjugate\", \"group__cmplx__conj.html\", \"group__cmplx__conj\" ],\n    [ \"Complex Dot Product\", \"group__cmplx__dot__prod.html\", \"group__cmplx__dot__prod\" ],\n    [ \"Complex Magnitude\", \"group__cmplx__mag.html\", \"group__cmplx__mag\" ],\n    [ \"Complex Magnitude Squared\", \"group__cmplx__mag__squared.html\", \"group__cmplx__mag__squared\" ],\n    [ \"Complex-by-Complex Multiplication\", \"group___cmplx_by_cmplx_mult.html\", \"group___cmplx_by_cmplx_mult\" ],\n    [ \"Complex-by-Real Multiplication\", \"group___cmplx_by_real_mult.html\", \"group___cmplx_by_real_mult\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_controller.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Controller Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_controller.js",
    "content": "var group__group_controller =\n[\n    [ \"Sine Cosine\", \"group___sin_cos.html\", \"group___sin_cos\" ],\n    [ \"PID Motor Control\", \"group___p_i_d.html\", \"group___p_i_d\" ],\n    [ \"Vector Clarke Transform\", \"group__clarke.html\", \"group__clarke\" ],\n    [ \"Vector Inverse Clarke Transform\", \"group__inv__clarke.html\", \"group__inv__clarke\" ],\n    [ \"Vector Park Transform\", \"group__park.html\", \"group__park\" ],\n    [ \"Vector Inverse Park transform\", \"group__inv__park.html\", \"group__inv__park\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_examples.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Examples\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_examples.js",
    "content": "var group__group_examples =\n[\n    [ \"Class Marks Example\", \"group___class_marks.html\", null ],\n    [ \"Convolution Example\", \"group___convolution_example.html\", null ],\n    [ \"Dot Product Example\", \"group___dotproduct_example.html\", null ],\n    [ \"Frequency Bin Example\", \"group___frequency_bin.html\", null ],\n    [ \"FIR Lowpass Filter Example\", \"group___f_i_r_l_p_f.html\", null ],\n    [ \"Graphic Audio Equalizer Example\", \"group___g_e_q5_band.html\", null ],\n    [ \"Linear Interpolate Example\", \"group___linear_interp_example.html\", null ],\n    [ \"Matrix Example\", \"group___matrix_example.html\", null ],\n    [ \"Signal Convergence Example\", \"group___signal_convergence.html\", null ],\n    [ \"SineCosine Example\", \"group___sin_cos_example.html\", null ],\n    [ \"Variance Example\", \"group___variance_example.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_fast_math.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Fast Math Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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Fast Math Functions
  
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 Cosine
 
 Sine
 
 Square Root
 
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Description
\n
This set of functions provides a fast approximation to sine, cosine, and square root. As compared to most of the other functions in the CMSIS math library, the fast math functions operate on individual values and not arrays. There are separate functions for Q15, Q31, and floating-point data. 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_fast_math.js",
    "content": "var group__group_fast_math =\n[\n    [ \"Cosine\", \"group__cos.html\", \"group__cos\" ],\n    [ \"Sine\", \"group__sin.html\", \"group__sin\" ],\n    [ \"Square Root\", \"group___s_q_r_t.html\", \"group___s_q_r_t\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_filters.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Filtering Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_filters.js",
    "content": "var group__group_filters =\n[\n    [ \"High Precision Q31 Biquad Cascade Filter\", \"group___biquad_cascade_d_f1__32x64.html\", \"group___biquad_cascade_d_f1__32x64\" ],\n    [ \"Biquad Cascade IIR Filters Using Direct Form I Structure\", \"group___biquad_cascade_d_f1.html\", \"group___biquad_cascade_d_f1\" ],\n    [ \"Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure\", \"group___biquad_cascade_d_f2_t.html\", \"group___biquad_cascade_d_f2_t\" ],\n    [ \"Convolution\", \"group___conv.html\", \"group___conv\" ],\n    [ \"Partial Convolution\", \"group___partial_conv.html\", \"group___partial_conv\" ],\n    [ \"Correlation\", \"group___corr.html\", \"group___corr\" ],\n    [ \"Finite Impulse Response (FIR) Decimator\", \"group___f_i_r__decimate.html\", \"group___f_i_r__decimate\" ],\n    [ \"Finite Impulse Response (FIR) Filters\", \"group___f_i_r.html\", \"group___f_i_r\" ],\n    [ \"Finite Impulse Response (FIR) Lattice Filters\", \"group___f_i_r___lattice.html\", \"group___f_i_r___lattice\" ],\n    [ \"Finite Impulse Response (FIR) Sparse Filters\", \"group___f_i_r___sparse.html\", \"group___f_i_r___sparse\" ],\n    [ \"Infinite Impulse Response (IIR) Lattice Filters\", \"group___i_i_r___lattice.html\", \"group___i_i_r___lattice\" ],\n    [ \"Least Mean Square (LMS) Filters\", \"group___l_m_s.html\", \"group___l_m_s\" ],\n    [ \"Normalized LMS Filters\", \"group___l_m_s___n_o_r_m.html\", \"group___l_m_s___n_o_r_m\" ],\n    [ \"Finite Impulse Response (FIR) Interpolator\", \"group___f_i_r___interpolate.html\", \"group___f_i_r___interpolate\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_interpolation.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Interpolation Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Interpolation Functions
  
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 Linear Interpolation
 
 Bilinear Interpolation
 
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Description
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These functions perform 1- and 2-dimensional interpolation of data. Linear interpolation is used for 1-dimensional data and bilinear interpolation is used for 2-dimensional data. 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_interpolation.js",
    "content": "var group__group_interpolation =\n[\n    [ \"Linear Interpolation\", \"group___linear_interpolate.html\", \"group___linear_interpolate\" ],\n    [ \"Bilinear Interpolation\", \"group___bilinear_interpolate.html\", \"group___bilinear_interpolate\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_math.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Basic Math Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_math.js",
    "content": "var group__group_math =\n[\n    [ \"Vector Absolute Value\", \"group___basic_abs.html\", \"group___basic_abs\" ],\n    [ \"Vector Addition\", \"group___basic_add.html\", \"group___basic_add\" ],\n    [ \"Vector Dot Product\", \"group__dot__prod.html\", \"group__dot__prod\" ],\n    [ \"Vector Multiplication\", \"group___basic_mult.html\", \"group___basic_mult\" ],\n    [ \"Vector Negate\", \"group__negate.html\", \"group__negate\" ],\n    [ \"Vector Offset\", \"group__offset.html\", \"group__offset\" ],\n    [ \"Vector Scale\", \"group__scale.html\", \"group__scale\" ],\n    [ \"Vector Shift\", \"group__shift.html\", \"group__shift\" ],\n    [ \"Vector Subtraction\", \"group___basic_sub.html\", \"group___basic_sub\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_matrix.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Matrix Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Matrix Functions
  
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 Matrix Addition
 
 Matrix Initialization
 
 Matrix Inverse
 
 Matrix Multiplication
 
 Matrix Scale
 
 Matrix Subtraction
 
 Matrix Transpose
 
\n
Description
\n
This set of functions provides basic matrix math operations. The functions operate on matrix data structures. For example, the type definition for the floating-point matrix structure is shown below: 
\n
\n    typedef struct\n    {\n      uint16_t numRows;     // number of rows of the matrix.\n      uint16_t numCols;     // number of columns of the matrix.\n      float32_t *pData;     // points to the data of the matrix.\n    } arm_matrix_instance_f32;\n
 There are similar definitions for Q15 and Q31 data types.
\n
The structure specifies the size of the matrix and then points to an array of data. The array is of size numRows X numCols and the values are arranged in row order. That is, the matrix element (i, j) is stored at: 
\n
\n    pData[i*numCols + j]\n
Init Functions
There is an associated initialization function for each type of matrix data structure. The initialization function sets the values of the internal structure fields. Refer to the function arm_mat_init_f32(), arm_mat_init_q31() and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
\n
Use of the initialization function is optional. However, if initialization function is used then the instance structure cannot be placed into a const data section. To place the instance structure in a const data section, manually initialize the data structure. For example: 
\narm_matrix_instance_f32 S = {nRows, nColumns, pData};\narm_matrix_instance_q31 S = {nRows, nColumns, pData};\narm_matrix_instance_q15 S = {nRows, nColumns, pData};\n
 where nRows specifies the number of rows, nColumns specifies the number of columns, and pData points to the data array.
\n
Size Checking
By default all of the matrix functions perform size checking on the input and output matrices. For example, the matrix addition function verifies that the two input matrices and the output matrix all have the same number of rows and columns. If the size check fails the functions return: 
\n    ARM_MATH_SIZE_MISMATCH\n
 Otherwise the functions return 
\n    ARM_MATH_SUCCESS\n
 There is some overhead associated with this matrix size checking. The matrix size checking is enabled via the #define 
\n    ARM_MATH_MATRIX_CHECK\n
 within the library project settings. By default this macro is defined and size checking is enabled. By changing the project settings and undefining this macro size checking is eliminated and the functions run a bit faster. With size checking disabled the functions always return ARM_MATH_SUCCESS. 
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_matrix.js",
    "content": "var group__group_matrix =\n[\n    [ \"Matrix Addition\", \"group___matrix_add.html\", \"group___matrix_add\" ],\n    [ \"Matrix Initialization\", \"group___matrix_init.html\", \"group___matrix_init\" ],\n    [ \"Matrix Inverse\", \"group___matrix_inv.html\", \"group___matrix_inv\" ],\n    [ \"Matrix Multiplication\", \"group___matrix_mult.html\", \"group___matrix_mult\" ],\n    [ \"Matrix Scale\", \"group___matrix_scale.html\", \"group___matrix_scale\" ],\n    [ \"Matrix Subtraction\", \"group___matrix_sub.html\", \"group___matrix_sub\" ],\n    [ \"Matrix Transpose\", \"group___matrix_trans.html\", \"group___matrix_trans\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_stats.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Statistics Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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Statistics Functions
  
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 Maximum
 
 Mean
 
 Minimum
 
 Power
 
 Root mean square (RMS)
 
 Standard deviation
 
 Variance
 
\n
Description
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_stats.js",
    "content": "var group__group_stats =\n[\n    [ \"Maximum\", \"group___max.html\", \"group___max\" ],\n    [ \"Mean\", \"group__mean.html\", \"group__mean\" ],\n    [ \"Minimum\", \"group___min.html\", \"group___min\" ],\n    [ \"Power\", \"group__power.html\", \"group__power\" ],\n    [ \"Root mean square (RMS)\", \"group___r_m_s.html\", \"group___r_m_s\" ],\n    [ \"Standard deviation\", \"group___s_t_d.html\", \"group___s_t_d\" ],\n    [ \"Variance\", \"group__variance.html\", \"group__variance\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_support.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Support Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_support.js",
    "content": "var group__group_support =\n[\n    [ \"Vector Copy\", \"group__copy.html\", \"group__copy\" ],\n    [ \"Vector Fill\", \"group___fill.html\", \"group___fill\" ],\n    [ \"Convert 32-bit floating point value\", \"group__float__to__x.html\", \"group__float__to__x\" ],\n    [ \"Convert 16-bit Integer value\", \"group__q15__to__x.html\", \"group__q15__to__x\" ],\n    [ \"Convert 32-bit Integer value\", \"group__q31__to__x.html\", \"group__q31__to__x\" ],\n    [ \"Convert 8-bit Integer value\", \"group__q7__to__x.html\", \"group__q7__to__x\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_transforms.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Transform Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Transform Functions
  
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\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nContent
 Complex FFT Functions
 
 Radix-8 Complex FFT Functions
 
 DCT Type IV Functions
 
 Real FFT Functions
 
 Complex FFT Tables
 
 RealFFT
 
\n\n\n\n\n\n\n
\nFunctions
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
 
void arm_split_rfft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
 Core Real FFT process.  More...
 
\n
Description
\n
Function Documentation
\n\n
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void arm_radix4_butterfly_f32 (float32_t * pSrc, 
uint16_t fftLen, 
float32_t * pCoef, 
uint16_t twidCoefModifier 
)
\n
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Referenced by arm_cfft_radix4_f32(), and arm_rfft_f32().
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void arm_split_rfft_f32 (float32_t * pSrc, 
uint32_t fftLen, 
float32_t * pATable, 
float32_t * pBTable, 
float32_t * pDst, 
uint32_t modifier 
)
\n
\n
end of RealFFT group 
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n  
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Returns
none. 
\n\n
Referenced by arm_rfft_f32().
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__group_transforms.js",
    "content": "var group__group_transforms =\n[\n    [ \"Complex FFT Functions\", \"group___complex_f_f_t.html\", \"group___complex_f_f_t\" ],\n    [ \"Radix-8 Complex FFT Functions\", \"group___radix8___c_f_f_t___c_i_f_f_t.html\", null ],\n    [ \"DCT Type IV Functions\", \"group___d_c_t4___i_d_c_t4.html\", \"group___d_c_t4___i_d_c_t4\" ],\n    [ \"Real FFT Functions\", \"group___fast.html\", null ],\n    [ \"Complex FFT Tables\", \"group___c_f_f_t___c_i_f_f_t.html\", \"group___c_f_f_t___c_i_f_f_t\" ],\n    [ \"RealFFT\", \"group___real_f_f_t.html\", \"group___real_f_f_t\" ],\n    [ \"arm_radix4_butterfly_f32\", \"group__group_transforms.html#gae239ddf995d1607115f9e84d5c069b9c\", null ],\n    [ \"arm_split_rfft_f32\", \"group__group_transforms.html#ga6cfdb6bdc66b13732ef2351caf98fdbb\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__inv__clarke.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Inverse Clarke Transform\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Vector Inverse Clarke Transform
Controller Functions
  
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\nFunctions
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
 Floating-point Inverse Clarke transform.  More...
 
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
 Inverse Clarke transform for Q31 version.  More...
 
\n
Description
\n
Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
\n
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 
\n
Algorithm
\n\"clarkeInvFormula.gif\"/\n
\n where pIa and pIb are the instantaneous stator phases and Ialpha and Ibeta are the two coordinates of time invariant vector. 
\n
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 
\n
Function Documentation
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static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, 
float32_t Ibeta, 
float32_t * pIa, 
float32_t * pIb 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 
\n  
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Returns
none. 
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static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, 
q31_t Ibeta, 
q31_t * pIa, 
q31_t * pIb 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the subtraction, hence there is no risk of overflow. 
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__inv__clarke.js",
    "content": "var group__inv__clarke =\n[\n    [ \"arm_inv_clarke_f32\", \"group__inv__clarke.html#ga137f0396d837477b899ecae89f075a50\", null ],\n    [ \"arm_inv_clarke_q31\", \"group__inv__clarke.html#ga2d0c60f114f095a2f27442d98781ba02\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__inv__park.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Inverse Park transform\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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\nFunctions  
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Vector Inverse Park transform
Controller Functions
  
\n
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\nFunctions
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
 Floating-point Inverse Park transform.  More...
 
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
 Inverse Park transform for Q31 version.  More...
 
\n
Description
\n
Inverse Park transform converts the input flux and torque components to two-coordinate vector.
\n
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 
\n
Algorithm
\n\"parkInvFormula.gif\"/\n
\n where pIalpha and pIbeta are the stator vector components, Id and Iq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 
\n
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 
\n
Function Documentation
\n\n
\n
\n\n  \n  \n  \n  \n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
static __INLINE void arm_inv_park_f32 (float32_t Id, 
float32_t Iq, 
float32_t * pIalpha, 
float32_t * pIbeta, 
float32_t sinVal, 
float32_t cosVal 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 
\n  
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Returns
none. 
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
static __INLINE void arm_inv_park_q31 (q31_t Id, 
q31_t Iq, 
q31_t * pIalpha, 
q31_t * pIbeta, 
q31_t sinVal, 
q31_t cosVal 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 
\n\n
\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__inv__park.js",
    "content": "var group__inv__park =\n[\n    [ \"arm_inv_park_f32\", \"group__inv__park.html#gaaf6bef0de21946f774d49df050dd8b05\", null ],\n    [ \"arm_inv_park_q31\", \"group__inv__park.html#ga0b33822b988a15455773d28440c5579a\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__mean.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Mean\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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Mean
Statistics Functions
  
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void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Mean value of a floating-point vector.  More...
 
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
 Mean value of a Q15 vector.  More...
 
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Mean value of a Q31 vector.  More...
 
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
 Mean value of a Q7 vector.  More...
 
\n
Description
\n
Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. The underlying algorithm is used:
\n
    \n        Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    \n
There are separate functions for floating-point, Q31, Q15, and Q7 data types. 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_mean_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 
\n  
\n
\n
Returns
none. 
\n
Examples: 
arm_class_marks_example_f32.c.
\n
\n
References blockSize.
\n\n
Referenced by main().
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_mean_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q15_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.15 format and is accumulated in a 32-bit accumulator in 17.15 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is saturated and truncated to yield a result of 1.15 format. 
\n\n
References __SIMD32, and blockSize.
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_mean_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format and is accumulated in a 64-bit accumulator in 33.31 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.31 format. 
\n\n
References blockSize.
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_mean_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q7_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format and is accumulated in a 32-bit accumulator in 25.7 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.7 format. 
\n\n
References __SIMD32, and blockSize.
\n\n
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__mean.js",
    "content": "var group__mean =\n[\n    [ \"arm_mean_f32\", \"group__mean.html#ga74ce08c49ab61e57bd50c3a0ca1fdb2b\", null ],\n    [ \"arm_mean_q15\", \"group__mean.html#gac882495d5f098819fd3939c1ef7795b3\", null ],\n    [ \"arm_mean_q31\", \"group__mean.html#gacf2526d8c2d75e486e8f0b0e31877ad0\", null ],\n    [ \"arm_mean_q7\", \"group__mean.html#gaebc707ee539020357c25da4c75b52eb7\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__negate.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Negate\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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Vector Negate
Basic Math Functions
  
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void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Negates the elements of a floating-point vector.  More...
 
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Negates the elements of a Q15 vector.  More...
 
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Negates the elements of a Q31 vector.  More...
 
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Negates the elements of a Q7 vector.  More...
 
\n
Description
\n
Negates the elements of a vector.
\n
        \n    pDst[n] = -pSrc[n],   0 <= n < blockSize.        \n
The functions support in-place computation allowing the source and destination pointers to reference the same memory buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
\n
Function Documentation
\n\n
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void arm_negate_f32 (float32_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none. 
\n\n
References blockSize.
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_negate_q15 (q15_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 
\n\n
References _SIMD32_OFFSET, and blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_negate_q31 (q31_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 
\n\n
References blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_negate_q7 (q7_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 
\n\n
References __SIMD32, and blockSize.
\n\n
\n
\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__negate.js",
    "content": "var group__negate =\n[\n    [ \"arm_negate_f32\", \"group__negate.html#ga2e169c4de6cc6e3ba4be9473531e6657\", null ],\n    [ \"arm_negate_q15\", \"group__negate.html#ga0239a833d72cf00290b9723c394e5042\", null ],\n    [ \"arm_negate_q31\", \"group__negate.html#ga2784c6887686a73dc7c364e2e41c776c\", null ],\n    [ \"arm_negate_q7\", \"group__negate.html#gaae78fc079a43bdaa3055f9b32e2a1f4c\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__offset.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Offset\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\nFunctions  
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Vector Offset
Basic Math Functions
  
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\nFunctions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
 Adds a constant offset to a floating-point vector.  More...
 
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q15 vector.  More...
 
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q31 vector.  More...
 
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
 Adds a constant offset to a Q7 vector.  More...
 
\n
Description
\n
Adds a constant offset to each element of a vector.
\n
        \n    pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        \n
The functions support in-place computation allowing the source and destination pointers to reference the same memory buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_offset_f32 (float32_t * pSrc, 
float32_t offset, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none. 
\n\n
References blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_offset_q15 (q15_t * pSrc, 
q15_t offset, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. 
\n\n
References __SIMD32, and blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_offset_q31 (q31_t * pSrc, 
q31_t offset, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. 
\n\n
References blockSize, and clip_q63_to_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_offset_q7 (q7_t * pSrc, 
q7_t offset, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] are saturated. 
\n\n
References __PACKq7, __SIMD32, and blockSize.
\n\n
\n
\n
\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__offset.js",
    "content": "var group__offset =\n[\n    [ \"arm_offset_f32\", \"group__offset.html#ga989dfae15235799d82f62ef9d356abb4\", null ],\n    [ \"arm_offset_q15\", \"group__offset.html#gab4c1d2391b599549e5a06fdfbc2747bf\", null ],\n    [ \"arm_offset_q31\", \"group__offset.html#gac84ec42cbbebc5c197a87d0221819acf\", null ],\n    [ \"arm_offset_q7\", \"group__offset.html#ga00bd9cc17c5bf905e76c91ad50886393\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__park.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Park Transform\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\nFunctions  
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Vector Park Transform
Controller Functions
  
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\n
\n\n\n\n\n\n\n\n\n
\nFunctions
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
 Floating-point Park transform.  More...
 
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
 Park transform for Q31 version.  More...
 
\n
Description
\n
Forward Park transform converts the input two-coordinate vector to flux and torque components. The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents from the stationary to the moving reference frame and control the spatial relationship between the stator vector current and rotor flux vector. If we consider the d axis aligned with the rotor flux, the diagram below shows the current vector and the relationship from the two reference frames: 
\n
\n\"park.gif\"/\n
\nStator current space vector and its component in (a,b) and in the d,q rotating reference frame
\n
 The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 
\n
Algorithm
\n\"parkFormula.gif\"/\n
\n where Ialpha and Ibeta are the stator vector components, pId and pIq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 
\n
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 
\n
Function Documentation
\n\n
\n
\n\n  \n  \n  \n  \n
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static __INLINE void arm_park_f32 (float32_t Ialpha, 
float32_t Ibeta, 
float32_t * pId, 
float32_t * pIq, 
float32_t sinVal, 
float32_t cosVal 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 
\n  
\n
\n
Returns
none.
\n
The function implements the forward Park transform. 
\n\n
\n
\n\n
\n
\n\n  \n  \n  \n  \n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
static __INLINE void arm_park_q31 (q31_t Ialpha, 
q31_t Ibeta, 
q31_t * pId, 
q31_t * pIq, 
q31_t sinVal, 
q31_t cosVal 
)
\n  		\nstatic  
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n    \n  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition and subtraction, hence there is no risk of overflow. 
\n\n
\n
\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__park.js",
    "content": "var group__park =\n[\n    [ \"arm_park_f32\", \"group__park.html#ga08b3a683197de7e143fb00497787683c\", null ],\n    [ \"arm_park_q31\", \"group__park.html#gaf4cc6370c0cfc14ea66774ed3c5bb10f\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__power.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Power\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
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\nFunctions  
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\n
Power
Statistics Functions
  
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\nFunctions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Sum of the squares of the elements of a floating-point vector.  More...
 
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q15 vector.  More...
 
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Sum of the squares of the elements of a Q31 vector.  More...
 
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Sum of the squares of the elements of a Q7 vector.  More...
 
\n
Description
\n
Calculates the sum of the squares of the elements in the input vector. The underlying algorithm is used:
\n
    \n        Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    \n
There are separate functions for floating point, Q31, Q15, and Q7 data types. 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_power_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 
\n  
\n
\n
Returns
none. 
\n\n
References blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_power_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 34.30 format. 
\n\n
References __SIMD32, and blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_power_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format. Intermediate multiplication yields a 2.62 format, and this result is truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. With 15 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 16.48 format. 
\n\n
References blockSize.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_power_q7 (q7_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format. Intermediate multiplication yields a 2.14 format, and this result is added without saturation to an accumulator in 18.14 format. With 17 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 18.14 format. 
\n\n
References __SIMD32, and blockSize.
\n\n
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__power.js",
    "content": "var group__power =\n[\n    [ \"arm_power_f32\", \"group__power.html#ga993c00dd7f661d66bdb6e58426e893aa\", null ],\n    [ \"arm_power_q15\", \"group__power.html#ga7050c04b7515e01a75c38f1abbaf71ba\", null ],\n    [ \"arm_power_q31\", \"group__power.html#ga0b93d31bb5b5ed214c2b94d8a7744cd2\", null ],\n    [ \"arm_power_q7\", \"group__power.html#gaf969c85c5655e3d72d7b99ff188f92c9\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q15__to__x.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Convert 16-bit Integer value\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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Convert 16-bit Integer value
Support Functions
  
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\nFunctions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to floating-point vector.  More...
 
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q31 vector.  More...
 
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q15 vector to Q7 vector.  More...
 
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Description
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Function Documentation
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void arm_q15_to_float (q15_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 
\n  
\n
\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    \n
 \n
References blockSize.
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void arm_q15_to_q31 (q15_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 
\n  
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\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    \n
 \n
References __SIMD32, and blockSize.
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void arm_q15_to_q7 (q15_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 
\n  
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Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    \n
 \n
References __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q15__to__x.js",
    "content": "var group__q15__to__x =\n[\n    [ \"arm_q15_to_float\", \"group__q15__to__x.html#gaf8b0d2324de273fc430b0e61ad4e9eb2\", null ],\n    [ \"arm_q15_to_q31\", \"group__q15__to__x.html#ga7ba2d87366990ad5380439e2b4a4c0a5\", null ],\n    [ \"arm_q15_to_q7\", \"group__q15__to__x.html#ga8fb31855ff8cce09c2ec9308f48ded69\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q31__to__x.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Convert 32-bit Integer value\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Convert 32-bit Integer value
Support Functions
  
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void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to floating-point vector.  More...
 
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q15 vector.  More...
 
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
 Converts the elements of the Q31 vector to Q7 vector.  More...
 
\n
Description
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Function Documentation
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void arm_q31_to_float (q31_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 
\n  
\n
\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    \n
 
Examples: 
arm_graphic_equalizer_example_q31.c.
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References blockSize.
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Referenced by main().
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void arm_q31_to_q15 (q31_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 
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Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    \n
 \n
References __SIMD32, and blockSize.
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void arm_q31_to_q7 (q31_t * pSrc, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 
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Returns
none.
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Description: 
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The equation used for the conversion process is:
\n
    \n        pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     \n
 \n
References __PACKq7, __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q31__to__x.js",
    "content": "var group__q31__to__x =\n[\n    [ \"arm_q31_to_float\", \"group__q31__to__x.html#gacf407b007a37da18e99dabd9023c56b4\", null ],\n    [ \"arm_q31_to_q15\", \"group__q31__to__x.html#ga901dede4661365c9e7c630d3eb31c32c\", null ],\n    [ \"arm_q31_to_q7\", \"group__q31__to__x.html#ga7f297d1a7d776805395095fdb24a8071\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q7__to__x.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Convert 8-bit Integer value\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
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CMSIS-DSP\n    Verison 1.4.1\n   
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Convert 8-bit Integer value
Support Functions
  
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void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to floating-point vector.  More...
 
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q15 vector.  More...
 
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
 Converts the elements of the Q7 vector to Q31 vector.  More...
 
\n
Description
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Function Documentation
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void arm_q7_to_float (q7_t * pSrc, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 
\n  
\n
\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    \n
 \n
References blockSize.
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void arm_q7_to_q15 (q7_t * pSrc, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 
\n  
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Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
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    \n        pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    \n
 \n
References __SIMD32, and blockSize.
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void arm_q7_to_q31 (q7_t * pSrc, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 
\n  
\n
\n
Returns
none.
\n
Description: 
\n
The equation used for the conversion process is:
\n
    \n        pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   \n
 \n
References __SIMD32, and blockSize.
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__q7__to__x.js",
    "content": "var group__q7__to__x =\n[\n    [ \"arm_q7_to_float\", \"group__q7__to__x.html#ga656620f957b65512ed83db03fd455ec5\", null ],\n    [ \"arm_q7_to_q15\", \"group__q7__to__x.html#gabc02597fc3f01033daf43ec0547a2f78\", null ],\n    [ \"arm_q7_to_q31\", \"group__q7__to__x.html#gad8958cd3cb7f521466168b46a25b7908\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__scale.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Scale\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
 Multiplies a floating-point vector by a scalar.  More...
 
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
 Multiplies a Q15 vector by a scalar.  More...
 
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
 Multiplies a Q31 vector by a scalar.  More...
 
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
 Multiplies a Q7 vector by a scalar.  More...
 
\n
Description
\n
Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
\n
        \n    pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        \n
In the fixed-point Q7, Q15, and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The algorithm used with fixed-point data is:
\n
        \n    pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        \n
The overall scale factor applied to the fixed-point data is 
\n
        \n    scale = scaleFract * 2^shift.        \n
The functions support in-place computation allowing the source and destination pointers to reference the same memory buffer. 
\n
Function Documentation
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void arm_scale_f32 (float32_t * pSrc, 
float32_t scale, 
float32_t * pDst, 
uint32_t blockSize 
)
\n
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Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]scalescale factor to be applied 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
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Returns
none. 
\n
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.
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References blockSize.
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Referenced by arm_dct4_f32(), and main().
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void arm_scale_q15 (q15_t * pSrc, 
q15_t scaleFract, 
int8_t shift, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 
\n\n
References __SIMD32, and blockSize.
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void arm_scale_q31 (q31_t * pSrc, 
q31_t scaleFract, 
int8_t shift, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 
\n
Examples: 
arm_graphic_equalizer_example_q31.c.
\n
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References blockSize.
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Referenced by main().
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void arm_scale_q7 (q7_t * pSrc, 
q7_t scaleFract, 
int8_t shift, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The input data *pSrc and scaleFract are in 1.7 format. These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. 
\n\n
References __PACKq7, __SIMD32, and blockSize.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__scale.js",
    "content": "var group__scale =\n[\n    [ \"arm_scale_f32\", \"group__scale.html#ga3487af88b112f682ee90589cd419e123\", null ],\n    [ \"arm_scale_q15\", \"group__scale.html#gafaac0e1927daffeb68a42719b53ea780\", null ],\n    [ \"arm_scale_q31\", \"group__scale.html#ga83e36cd82bf51ce35406a199e477d47c\", null ],\n    [ \"arm_scale_q7\", \"group__scale.html#gabc9fd3d37904c58df56492b351d21fb0\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__shift.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Vector Shift\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q15 vector a specified number of bits.  More...
 
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q31 vector a specified number of bits.  More...
 
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
 Shifts the elements of a Q7 vector a specified number of bits.  More...
 
\n
Description
\n
Shifts the elements of a fixed-point vector by a specified number of bits. There are separate functions for Q7, Q15, and Q31 data types. The underlying algorithm used is:
\n
        \n    pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        \n
If shift is positive then the elements of the vector are shifted to the left. If shift is negative then the elements of the vector are shifted to the right.
\n
The functions support in-place computation allowing the source and destination pointers to reference the same memory buffer. 
\n
Function Documentation
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void arm_shift_q15 (q15_t * pSrc, 
int8_t shiftBits, 
q15_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 
\n\n
References __SIMD32, and blockSize.
\n\n
Referenced by arm_dct4_q15().
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void arm_shift_q31 (q31_t * pSrc, 
int8_t shiftBits, 
q31_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 
\n\n
References blockSize, and clip_q63_to_q31().
\n\n
Referenced by arm_dct4_q31().
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void arm_shift_q7 (q7_t * pSrc, 
int8_t shiftBits, 
q7_t * pDst, 
uint32_t blockSize 
)
\n
\n
Parameters
\n  \n    \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 
\n  
\n
\n
Returns
none.
\n
Conditions for optimum performance 
Input and output buffers should be aligned by 32-bit
\n
Scaling and Overflow Behavior: 
\n
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. 
\n\n
References __PACKq7, __SIMD32, and blockSize.
\n\n
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  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__shift.js",
    "content": "var group__shift =\n[\n    [ \"arm_shift_q15\", \"group__shift.html#gaa1757e53279780107acc92cf100adb61\", null ],\n    [ \"arm_shift_q31\", \"group__shift.html#ga387dd8b7b87377378280978f16cdb13d\", null ],\n    [ \"arm_shift_q7\", \"group__shift.html#ga47295d08a685f7de700a48dafb4db6fb\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__sin.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Sine\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\nFunctions |\nVariables  
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Sine
Fast Math Functions
  
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\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
float32_t arm_sin_f32 (float32_t x)
 Fast approximation to the trigonometric sine function for floating-point data.  More...
 
q15_t arm_sin_q15 (q15_t x)
 Fast approximation to the trigonometric sine function for Q15 data.  More...
 
q31_t arm_sin_q31 (q31_t x)
 Fast approximation to the trigonometric sine function for Q31 data.  More...
 
\n\n\n\n\n\n\n\n
\nVariables
static const float32_t sinTable [259]
 
static const q15_t sinTableQ15 [259]
 
static const q31_t sinTableQ31 [259]
 
\n
Description
\n
Computes the trigonometric sine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a value of 2*pi wraps around to 0.
\n
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:
\n
    \n
  1. Calculation of the nearest integer table index
    2. \n
  2. Fetch the four table values a, b, c, and d
    3. \n
  3. Compute the fractional portion (fract) of the table index.
    4. \n
  4. Calculation of wa, wb, wc, wd
    5. \n
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. \n
\n
where 
\n
    \n   a=Table[index-1];    \n   b=Table[index+0];    \n   c=Table[index+1];    \n   d=Table[index+2];    \n
 and 
\n
    \n   wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    \n   wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    \n   wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    \n   wd=(1/6)*fract.^3 - (1/6)*fract;    \n
 
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
float32_t arm_sin_f32 (float32_t x)
\n
\n
Parameters
\n  \n    \n  
[in]xinput value in radians. 
\n  
\n
\n
Returns
sin(x). 
\n
Examples: 
arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.
\n
\n
References sinTable, and TABLE_SIZE.
\n\n
Referenced by main().
\n\n
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\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
q15_t arm_sin_q15 (q15_t x)
\n
\n
Parameters
\n  \n    \n  
[in]xScaled input value in radians. 
\n  
\n
\n
Returns
sin(x).
\n
The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). 
\n\n
References sinTableQ15, and TABLE_SPACING_Q15.
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
q31_t arm_sin_q31 (q31_t x)
\n
\n
Parameters
\n  \n    \n  
[in]xScaled input value in radians. 
\n  
\n
\n
Returns
sin(x).
\n
The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). 
\n\n
References sinTableQ31, and TABLE_SPACING_Q31.
\n\n
\n
\n
Variable Documentation
\n\n
\n
\n\n  \n  \n  \n  \n
\n      \n        \n          \n        \n      
const float32_t sinTable[259]
\n  		\nstatic  
\n
\n
Example code for the generation of the floating-point sine table: 
\ntableSize = 256;    \nfor(n = -1; n < (tableSize + 1); n++)    \n{    \n     sinTable[n+1]=sin(2*pi*n/tableSize);    \n}
 
\n
where pi value is 3.14159265358979 
\n\n
Referenced by arm_sin_f32().
\n\n
\n
\n\n
\n
\n\n  \n  \n  \n  \n
\n      \n        \n          \n        \n      
const q15_t sinTableQ15[259]
\n  		\nstatic  
\n
\n
Table values are in Q15 (1.15 fixed-point format) and generation is done in three steps. First, generate sin values in floating point: 
\n tableSize = 256;\n for(n = -1; n < (tableSize + 1); n++)    \n {    \n        sinTable[n+1]= sin(2*pi*n/tableSize);    \n } 
 where pi value is 3.14159265358979 
\n
Second, convert floating-point to Q15 (fixed-point): (sinTable[i] * pow(2, 15)) 
\n
Finally, round to the nearest integer value: sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 
\n\n
Referenced by arm_sin_q15().
\n\n
\n
\n\n
\n
\n\n  \n  \n  \n  \n
\n      \n        \n          \n        \n      
const q31_t sinTableQ31[259]
\n  		\nstatic  
\n
\n
Table values are in Q31 (1.31 fixed-point format) and generation is done in three steps. First, generate sin values in floating point: 
\ntableSize = 256;      \nfor(n = -1; n < (tableSize + 1); n++)    \n{    \n     sinTable[n+1]= sin(2*pi*n/tableSize);    \n} 
 where pi value is 3.14159265358979 
\n
Second, convert floating-point to Q31 (Fixed point): (sinTable[i] * pow(2, 31)) 
\n
Finally, round to the nearest integer value: sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 
\n\n
Referenced by arm_sin_q31().
\n\n
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    \n    
  • Generated on Mon Mar 18 2013 13:37:56 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__sin.js",
    "content": "var group__sin =\n[\n    [ \"arm_sin_f32\", \"group__sin.html#gae164899c4a3fc0e946dc5d55555fe541\", null ],\n    [ \"arm_sin_q15\", \"group__sin.html#ga1fc6d6640be6cfa688a8bea0a48397ee\", null ],\n    [ \"arm_sin_q31\", \"group__sin.html#ga57aade7d8892585992cdc6375bd82f9c\", null ],\n    [ \"sinTable\", \"group__sin.html#ga71a0a466c6d42c65526968509b04790c\", null ],\n    [ \"sinTableQ15\", \"group__sin.html#ga0bb9449f52f04f5241f073864a72930a\", null ],\n    [ \"sinTableQ31\", \"group__sin.html#gab1ffde7f3deee5adc75ba8b3d0a53106\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__variance.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Variance\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Variance
Statistics Functions
  
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void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
 Variance of the elements of a floating-point vector.  More...
 
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
 Variance of the elements of a Q15 vector.  More...
 
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
 Variance of the elements of a Q31 vector.  More...
 
\n
Description
\n
Calculates the variance of the elements in the input vector. The underlying algorithm is used:
\n
    \n        Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)
        where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
                        sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   \n
There are separate functions for floating point, Q31, and Q15 data types. 
\n
Function Documentation
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void arm_var_f32 (float32_t * pSrc, 
uint32_t blockSize, 
float32_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 
\n  
\n
\n
Returns
none. 
\n
Examples: 
arm_class_marks_example_f32.c.
\n
\n
References blockSize, and mean.
\n\n
Referenced by main().
\n\n
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void arm_var_q15 (q15_t * pSrc, 
uint32_t blockSize, 
q31_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 
\n\n
References __SIMD32, blockSize, and mean.
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void arm_var_q31 (q31_t * pSrc, 
uint32_t blockSize, 
q63_t * pResult 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 
\n  
\n
\n
Returns
none.
\n
Scaling and Overflow Behavior:
\n
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 
\n\n
References blockSize, and mean.
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/group__variance.js",
    "content": "var group__variance =\n[\n    [ \"arm_var_f32\", \"group__variance.html#ga393f26c5a3bfa05624fb8d32232a6d96\", null ],\n    [ \"arm_var_q15\", \"group__variance.html#ga957b23ddcc2e0883461797ebf8a2cf1f\", null ],\n    [ \"arm_var_q31\", \"group__variance.html#ga353e4c924e707ab9ee7687d28094a668\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/index.html",
    "content": "\n\n\n\n\nCMSIS-DSP: CMSIS DSP Software Library\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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CMSIS DSP Software Library 
  
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Introduction
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This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M processor based devices.
\n
The library is divided into a number of functions each covering a specific category:
\n
    \n
  • Basic math functions
    • \n
  • Fast math functions
    • \n
  • Complex math functions
    • \n
  • Filters
    • \n
  • Matrix functions
    • \n
  • Transforms
    • \n
  • Motor control functions
    • \n
  • Statistical functions
    • \n
  • Support functions
    • \n
  • Interpolation functions
    • \n
\n
The library has separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.
\n
Using the Library
\n
The library installer contains prebuilt versions of the libraries in the Lib folder.
\n
    \n
  • arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
    • \n
  • arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
    • \n
  • arm_cortexM4l_math.lib (Little endian on Cortex-M4)
    • \n
  • arm_cortexM4b_math.lib (Big endian on Cortex-M4)
    • \n
  • arm_cortexM3l_math.lib (Little endian on Cortex-M3)
    • \n
  • arm_cortexM3b_math.lib (Big endian on Cortex-M3)
    • \n
  • arm_cortexM0l_math.lib (Little endian on Cortex-M0)
    • \n
  • arm_cortexM0b_math.lib (Big endian on Cortex-M3)
    • \n
\n
The library functions are declared in the public file arm_math.h which is placed in the Include folder. Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
\n
Examples
\n
The library ships with a number of examples which demonstrate how to use the library functions.
\n
Toolchain Support
\n
The library has been developed and tested with MDK-ARM version 4.60. The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
\n
Building the Library
\n
The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
\n
    \n
  • arm_cortexM0b_math.uvproj
    • \n
  • arm_cortexM0l_math.uvproj
    • \n
  • arm_cortexM3b_math.uvproj
    • \n
  • arm_cortexM3l_math.uvproj
    • \n
  • arm_cortexM4b_math.uvproj
    • \n
  • arm_cortexM4l_math.uvproj
    • \n
  • arm_cortexM4bf_math.uvproj
    • \n
  • arm_cortexM4lf_math.uvproj
    • \n
\n
The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
\n
Pre-processor Macros
\n
Each library project have differant pre-processor macros.
\n
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  • UNALIGNED_SUPPORT_DISABLE:
    • \n
\n
Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
\n
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  • ARM_MATH_BIG_ENDIAN:
    • \n
\n
Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
\n
    \n
  • ARM_MATH_MATRIX_CHECK:
    • \n
\n
Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
\n
    \n
  • ARM_MATH_ROUNDING:
    • \n
\n
Define macro ARM_MATH_ROUNDING for rounding on support functions
\n
    \n
  • ARM_MATH_CMx:
    • \n
\n
Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
\n
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  • __FPU_PRESENT:
    • \n
\n
Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
\n
Copyright Notice
\n
Copyright (C) 2010-2013 ARM Limited. All rights reserved. 
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
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b;a.browser.msie&&/(static|relative)/.test(this.css(\"position\"))||/absolute/.test(this.css(\"position\"))?b=this.parents().filter(function(){return/(relative|absolute|fixed)/.test(a.curCSS(this,\"position\",1))&&/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0):b=this.parents().filter(function(){return/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0);return/fixed/.test(this.css(\"position\"))||!b.length?a(document):b},zIndex:function(c){if(c!==b)return this.css(\"zIndex\",c);if(this.length){var d=a(this[0]),e,f;while(d.length&&d[0]!==document){e=d.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){f=parseInt(d.css(\"zIndex\"),10);if(!isNaN(f)&&f!==0)return f}d=d.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(a){a.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}}),a.each([\"Width\",\"Height\"],function(c,d){function h(b,c,d,f){a.each(e,function(){c-=parseFloat(a.curCSS(b,\"padding\"+this,!0))||0,d&&(c-=parseFloat(a.curCSS(b,\"border\"+this+\"Width\",!0))||0),f&&(c-=parseFloat(a.curCSS(b,\"margin\"+this,!0))||0)});return c}var e=d===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],f=d.toLowerCase(),g={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};a.fn[\"inner\"+d]=function(c){if(c===b)return g[\"inner\"+d].call(this);return this.each(function(){a(this).css(f,h(this,c)+\"px\")})},a.fn[\"outer\"+d]=function(b,c){if(typeof b!=\"number\")return g[\"outer\"+d].call(this,b);return this.each(function(){a(this).css(f,h(this,b,!0,c)+\"px\")})}}),a.extend(a.expr[\":\"],{data:function(b,c,d){return!!a.data(b,d[3])},focusable:function(b){return c(b,!isNaN(a.attr(b,\"tabindex\")))},tabbable:function(b){var d=a.attr(b,\"tabindex\"),e=isNaN(d);return(e||d>=0)&&c(b,!e)}}),a(function(){var b=document.body,c=b.appendChild(c=document.createElement(\"div\"));c.offsetHeight,a.extend(c.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0}),a.support.minHeight=c.offsetHeight===100,a.support.selectstart=\"onselectstart\"in c,b.removeChild(c).style.display=\"none\"}),a.extend(a.ui,{plugin:{add:function(b,c,d){var e=a.ui[b].prototype;for(var f in d)e.plugins[f]=e.plugins[f]||[],e.plugins[f].push([c,d[f]])},call:function(a,b,c){var d=a.plugins[b];if(!!d&&!!a.element[0].parentNode)for(var e=0;e0)return!0;b[d]=1,e=b[d]>0,b[d]=0;return e},isOverAxis:function(a,b,c){return a>b&&a=9)&&!b.button)return this._mouseUp(b);if(this._mouseStarted){this._mouseDrag(b);return b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+\".preventClickEvent\",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery);\n/*\n * jQuery UI Resizable 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Resizables\n *\n * Depends:\n *\tjquery.ui.core.js\n *\tjquery.ui.mouse.js\n *\tjquery.ui.widget.js\n */\n(function(a,b){a.widget(\"ui.resizable\",a.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:!1,animate:!1,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:\"e,s,se\",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass(\"ui-resizable\"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||\"ui-resizable-helper\":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")})),this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css(\"resize\"),this.originalElement.css(\"resize\",\"none\"),this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"})),this.originalElement.css({margin:this.originalElement.css(\"margin\")}),this._proportionallyResize()),this.handles=c.handles||(a(\".ui-resizable-handle\",this.element).length?{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"}:\"e,s,se\");if(this.handles.constructor==String){this.handles==\"all\"&&(this.handles=\"n,e,s,w,se,sw,ne,nw\");var d=this.handles.split(\",\");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),\"se\"==f&&h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\"),this.handles[f]=\".ui-resizable-\"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=[\"padding\",/ne|nw|n/.test(c)?\"Top\":/se|sw|s/.test(c)?\"Bottom\":/^e$/.test(c)?\"Right\":\"Left\"].join(\"\");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(\".ui-resizable-handle\",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:\"se\"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass(\"ui-resizable-autohide\").hover(function(){c.disabled||(a(this).removeClass(\"ui-resizable-autohide\"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass(\"ui-resizable-autohide\"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css(\"position\"),width:c.outerWidth(),height:c.outerHeight(),top:c.css(\"top\"),left:c.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(\".ui-draggable\")||/absolute/.test(f.css(\"position\")))&&f.css({position:\"absolute\",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css(\"left\")),h=c(this.helper.css(\"top\"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio==\"number\"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(\".ui-resizable-\"+this.axis).css(\"cursor\");a(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i),f.addClass(\"ui-resizable-resizing\"),this._propagate(\"start\",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate(\"resize\",b),c.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger(\"resize\",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],\"left\")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a(\"body\").css(\"cursor\",\"auto\"),this.element.removeClass(\"ui-resizable-resizing\"),this._propagate(\"stop\",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:\"absolute\",left:this.elementOffset.left-e+\"px\",top:this.elementOffset.top-e+\"px\",zIndex:++c.zIndex}),this.helper.appendTo(\"body\").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!=\"resize\"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:\"1.8.18\"}),a.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data(\"resizable-alsoresize\",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css(\"left\"),10),top:parseInt(b.css(\"top\"),10)})})};typeof e.alsoResize==\"object\"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data(\"resizable-alsoresize\"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?[\"width\",\"height\"]:[\"width\",\"height\",\"top\",\"left\"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize==\"object\"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData(\"resizable-alsoresize\")}}),a.ui.plugin.add(\"resizable\",\"animate\",{stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d._proportionallyResizeElements,g=f.length&&/textarea/i.test(f[0].nodeName),h=g&&a.ui.hasScroll(f[0],\"left\")?0:d.sizeDiff.height,i=g?0:d.sizeDiff.width,j={width:d.size.width-i,height:d.size.height-h},k=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,l=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;d.element.animate(a.extend(j,l&&k?{top:l,left:k}:{}),{duration:e.animateDuration,easing:e.animateEasing,step:function(){var c={width:parseInt(d.element.css(\"width\"),10),height:parseInt(d.element.css(\"height\"),10),top:parseInt(d.element.css(\"top\"),10),left:parseInt(d.element.css(\"left\"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate(\"resize\",b)}})}}),a.ui.plugin.add(\"resizable\",\"containment\",{start:function(b,d){var e=a(this).data(\"resizable\"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a([\"Top\",\"Right\",\"Left\",\"Bottom\"]).each(function(a,b){k[a]=c(j.css(\"padding\"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,\"left\")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css(\"position\"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css(\"position\"));o&&p\n&&(m-=d.parentData.left),m+d.size.width>=d.parentData.width&&(d.size.width=d.parentData.width-m,j&&(d.size.height=d.size.width/d.aspectRatio)),n+d.size.height>=d.parentData.height&&(d.size.height=d.parentData.height-n,j&&(d.size.width=d.size.height*d.aspectRatio))},stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.position,g=d.containerOffset,h=d.containerPosition,i=d.containerElement,j=a(d.helper),k=j.offset(),l=j.outerWidth()-d.sizeDiff.width,m=j.outerHeight()-d.sizeDiff.height;d._helper&&!e.animate&&/relative/.test(i.css(\"position\"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m}),d._helper&&!e.animate&&/static/.test(i.css(\"position\"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m})}}),a.ui.plugin.add(\"resizable\",\"ghost\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.size;d.ghost=d.originalElement.clone(),d.ghost.css({opacity:.25,display:\"block\",position:\"relative\",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass(\"ui-resizable-ghost\").addClass(typeof e.ghost==\"string\"?e.ghost:\"\"),d.ghost.appendTo(d.helper)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options;d.ghost&&d.ghost.css({position:\"relative\",height:d.size.height,width:d.size.width})},stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options;d.ghost&&d.helper&&d.helper.get(0).removeChild(d.ghost.get(0))}}),a.ui.plugin.add(\"resizable\",\"grid\",{resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.size,g=d.originalSize,h=d.originalPosition,i=d.axis,j=e._aspectRatio||b.shiftKey;e.grid=typeof e.grid==\"number\"?[e.grid,e.grid]:e.grid;var k=Math.round((f.width-g.width)/(e.grid[0]||1))*(e.grid[0]||1),l=Math.round((f.height-g.height)/(e.grid[1]||1))*(e.grid[1]||1);/^(se|s|e)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l):/^(ne)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l):/^(sw)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.left=h.left-k):(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l,d.position.left=h.left-k)}});var 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\n  
\nFunctions |\nVariables  
\n  
\n
license.txt File Reference
  
\n
\n
\n
\n\n\n\n\n\n
\nFunctions
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY OR CONSEQUENTIAL 		DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;LOSS OF USE, DATA, OR PROFITS;OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY OR CONSEQUENTIAL WHETHER 
\nIN STRICT OR 		TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nVariables
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following 		license
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without 		modification
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are 		met
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright 		notice
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED 		WARRANTIES
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED 		INCLUDING
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED 		TO
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY 		DIRECT
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY 		INDIRECT
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY 		INCIDENTAL
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY 		SPECIAL
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY 		EXEMPLARY
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY OR CONSEQUENTIAL WHETHER 
\nIN 		CONTRACT
 
All files contained in the 
\nfolders CMSIS DSP Lib Source 
\nand CMSIS DSP Lib Examples are 
\nguided by the following with 
\nor without are permitted 
\nprovided that the following 
\nconditions are this list of 
\nconditions and the following 
\ndisclaimer Redistributions in 
\nbinary form must reproduce the 
\nabove copyright this list of 
\nconditions and the following 
\ndisclaimer in the 
\ndocumentation and or other 
\nmaterials provided with the 
\ndistribution Neither the name 
\nof ARM nor the names of its 
\ncontributors may be used to 
\nendorse or promote products 
\nderived from this software 
\nwithout specific prior written 
\npermission THIS SOFTWARE IS 
\nPROVIDED BY THE COPYRIGHT 
\nHOLDERS AND CONTRIBUTORS AS IS 
\nAND ANY EXPRESS OR IMPLIED BUT 
\nNOT LIMITED THE IMPLIED 
\nWARRANTIES OF MERCHANTABILITY 
\nAND FITNESS FOR A PARTICULAR 
\nPURPOSE ARE DISCLAIMED IN NO 
\nEVENT SHALL COPYRIGHT HOLDERS 
\nAND CONTRIBUTORS BE LIABLE FOR 
\nANY OR CONSEQUENTIAL WHETHER 
\nIN STRICT 		LIABILITY
 
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY OR CONSEQUENTIAL DAMAGES (INCLUDING , 
BUT NOT LIMITED TO, 
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;LOSS OF USE, 
DATA , 
OR PROFITS;OR BUSINESS INTERRUPTION 
)
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY OR CONSEQUENTIAL WHETHER IN STRICT OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
\n
\n\n
\n
\n
Variable Documentation
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY OR CONSEQUENTIAL WHETHER IN CONTRACT
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY EXEMPLARY
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY INCIDENTAL
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED INCLUDING
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY INDIRECT
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY OR CONSEQUENTIAL WHETHER IN STRICT LIABILITY
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following license
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are met
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without modification
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright notice
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY SPECIAL
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED BUT NOT LIMITED TO
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
All files contained in the folders CMSIS DSP Lib Source and CMSIS DSP Lib Examples are guided by the following with or without are permitted provided that the following conditions are this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES
\n
\n\n
\n
\n\n\n\n
\n  
    \n    
  • license.txt
    • \n    
  • Generated on Mon Mar 18 2013 13:37:55 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/math__helper_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: math_helper.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
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math_helper.c File Reference
  
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\nFunctions
float arm_snr_f32 (float *pRef, float *pTest, uint32_t buffSize)
 Caluclation of SNR.  More...
 
void arm_provide_guard_bits_q15 (q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  More...
 
void arm_float_to_q12_20 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed in q12.20 format.  More...
 
uint32_t arm_compare_fixed_q15 (q15_t *pIn, q15_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  More...
 
uint32_t arm_compare_fixed_q31 (q31_t *pIn, q31_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  More...
 
void arm_provide_guard_bits_q31 (q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  More...
 
void arm_provide_guard_bits_q7 (q7_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  More...
 
uint32_t arm_calc_guard_bits (uint32_t num_adds)
 Caluclates number of guard bits.  More...
 
void arm_apply_guard_bits (float32_t *pIn, uint32_t numSamples, uint32_t guard_bits)
 Converts Q15 to floating-point.  More...
 
uint32_t arm_calc_2pow (uint32_t numShifts)
 Calculates pow(2, numShifts)  More...
 
void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
 Converts float to fixed q14.  More...
 
void arm_float_to_q30 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  More...
 
void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  More...
 
void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q28 format.  More...
 
void arm_clip_f32 (float *pIn, uint32_t numSamples)
 Clip the float values to +/- 1.  More...
 
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Function Documentation
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void arm_apply_guard_bits (float32_t * pIn, 
uint32_t numSamples, 
uint32_t guard_bits 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none 
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References arm_calc_2pow().
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uint32_t arm_calc_2pow (uint32_t numShifts)
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Parameters
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uint32_tnumber of shifts 
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Returns
pow(2, numShifts) 
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Referenced by arm_apply_guard_bits().
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uint32_t arm_calc_guard_bits (uint32_t num_adds)
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Parameters
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uint32_tnumber of additions 
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Returns
none The function Caluclates the number of guard bits depending on the numtaps 
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void arm_clip_f32 (float * pIn, 
uint32_t numSamples 
)
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Parameters
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pIninput buffer 
numSamplesnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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uint32_t arm_compare_fixed_q15 (q15_t * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)
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Parameters
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q15_t*Pointer to Ref buffer 
q15_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 
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Returns
none 
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uint32_t arm_compare_fixed_q31 (q31_t * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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q31_t*Pointer to Ref buffer 
q31_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 
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Returns
none 
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void arm_float_to_q12_20 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point(q12.20) values 
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void arm_float_to_q14 (float * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_float_to_q28 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_float_to_q29 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_float_to_q30 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_provide_guard_bits_q15 (q15_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)
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Parameters
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q15_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 
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Returns
none The function Provides the guard bits for the buffer to avoid overflow 
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References blockSize.
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void arm_provide_guard_bits_q31 (q31_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)
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Parameters
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q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 
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Returns
none The function Provides the guard bits for the buffer to avoid overflow 
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References blockSize.
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void arm_provide_guard_bits_q7 (q7_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)
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Parameters
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q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 
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Returns
none The function Provides the guard bits for the buffer to avoid overflow 
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References blockSize.
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float arm_snr_f32 (float * pRef, 
float * pTest, 
uint32_t buffSize 
)
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Parameters
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float*Pointer to the reference buffer 
float*Pointer to the test buffer 
uint32_ttotal number of samples 
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Returns
float SNR The function Caluclates signal to noise ratio for the reference output and test output 
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Referenced by main().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/math__helper_8h.html",
    "content": "\n\n\n\n\nCMSIS-DSP: math_helper.h File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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math_helper.h File Reference
  
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\nFunctions
float arm_snr_f32 (float *pRef, float *pTest, uint32_t buffSize)
 Caluclation of SNR.  More...
 
void arm_float_to_q12_20 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed in q12.20 format.  More...
 
void arm_provide_guard_bits_q15 (q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  More...
 
void arm_provide_guard_bits_q31 (q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits)
 Provide guard bits for Input buffer.  More...
 
void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
 Converts float to fixed q14.  More...
 
void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  More...
 
void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q28 format.  More...
 
void arm_float_to_q30 (float *pIn, q31_t *pOut, uint32_t numSamples)
 Converts float to fixed q30 format.  More...
 
void arm_clip_f32 (float *pIn, uint32_t numSamples)
 Clip the float values to +/- 1.  More...
 
uint32_t arm_calc_guard_bits (uint32_t num_adds)
 Caluclates number of guard bits.  More...
 
void arm_apply_guard_bits (float32_t *pIn, uint32_t numSamples, uint32_t guard_bits)
 Converts Q15 to floating-point.  More...
 
uint32_t arm_compare_fixed_q15 (q15_t *pIn, q15_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  More...
 
uint32_t arm_compare_fixed_q31 (q31_t *pIn, q31_t *pOut, uint32_t numSamples)
 Compare MATLAB Reference Output and ARM Test output.  More...
 
uint32_t arm_calc_2pow (uint32_t guard_bits)
 Calculates pow(2, numShifts)  More...
 
\n
Function Documentation
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void arm_apply_guard_bits (float32_t * pIn, 
uint32_t numSamples, 
uint32_t guard_bits 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none 
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References arm_calc_2pow().
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uint32_t arm_calc_2pow (uint32_t numShifts)
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Parameters
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uint32_tnumber of shifts 
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Returns
pow(2, numShifts) 
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Referenced by arm_apply_guard_bits().
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uint32_t arm_calc_guard_bits (uint32_t num_adds)
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Parameters
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uint32_tnumber of additions 
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Returns
none The function Caluclates the number of guard bits depending on the numtaps 
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void arm_clip_f32 (float * pIn, 
uint32_t numSamples 
)
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Parameters
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pIninput buffer 
numSamplesnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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uint32_t arm_compare_fixed_q15 (q15_t * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)
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Parameters
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q15_t*Pointer to Ref buffer 
q15_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 
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Returns
none 
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uint32_t arm_compare_fixed_q31 (q31_t * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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q31_t*Pointer to Ref buffer 
q31_t*Pointer to Test buffer 
uint32_tnumber of samples in the buffer 
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Returns
none 
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void arm_float_to_q12_20 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point(q12.20) values 
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void arm_float_to_q14 (float * pIn, 
q15_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_float_to_q28 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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none The function converts floating point values to fixed point values 
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void arm_float_to_q29 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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none The function converts floating point values to fixed point values 
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void arm_float_to_q30 (float * pIn, 
q31_t * pOut, 
uint32_t numSamples 
)
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Parameters
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uint32_tnumber of samples in the buffer 
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Returns
none The function converts floating point values to fixed point values 
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void arm_provide_guard_bits_q15 (q15_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)
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Parameters
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q15_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 
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Returns
none The function Provides the guard bits for the buffer to avoid overflow 
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References blockSize.
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void arm_provide_guard_bits_q31 (q31_t * input_buf, 
uint32_t blockSize, 
uint32_t guard_bits 
)
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Parameters
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q31_t*Pointer to input buffer 
uint32_tblockSize 
uint32_tguard_bits 
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Returns
none The function Provides the guard bits for the buffer to avoid overflow 
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References blockSize.
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float arm_snr_f32 (float * pRef, 
float * pTest, 
uint32_t buffSize 
)
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Parameters
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float*Pointer to the reference buffer 
float*Pointer to the test buffer 
uint32_ttotal number of samples 
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Returns
float SNR The function Caluclates signal to noise ratio for the reference output and test output 
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Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_matrix_example_f32.c.
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Referenced by main().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/modules.html",
    "content": "\n\n\n\n\nCMSIS-DSP: Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Reference
  
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Here is a list of all modules:
\n
[detail level 12]
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\"o\"Basic Math Functions
\"|\"\"o\"Vector Absolute Value
\"|\"\"o\"Vector Addition
\"|\"\"o\"Vector Dot Product
\"|\"\"o\"Vector Multiplication
\"|\"\"o\"Vector Negate
\"|\"\"o\"Vector Offset
\"|\"\"o\"Vector Scale
\"|\"\"o\"Vector Shift
\"|\"\"\\\"Vector Subtraction
\"o\"Fast Math Functions
\"|\"\"o\"Cosine
\"|\"\"o\"Sine
\"|\"\"\\\"Square Root
\"o\"Complex Math Functions
\"|\"\"o\"Complex Conjugate
\"|\"\"o\"Complex Dot Product
\"|\"\"o\"Complex Magnitude
\"|\"\"o\"Complex Magnitude Squared
\"|\"\"o\"Complex-by-Complex Multiplication
\"|\"\"\\\"Complex-by-Real Multiplication
\"o\"Filtering Functions
\"|\"\"o\"High Precision Q31 Biquad Cascade Filter
\"|\"\"o\"Biquad Cascade IIR Filters Using Direct Form I Structure
\"|\"\"o\"Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
\"|\"\"o\"Convolution
\"|\"\"o\"Partial Convolution
\"|\"\"o\"Correlation
\"|\"\"o\"Finite Impulse Response (FIR) Decimator
\"|\"\"o\"Finite Impulse Response (FIR) Filters
\"|\"\"o\"Finite Impulse Response (FIR) Lattice Filters
\"|\"\"o\"Finite Impulse Response (FIR) Sparse Filters
\"|\"\"o\"Infinite Impulse Response (IIR) Lattice Filters
\"|\"\"o\"Least Mean Square (LMS) Filters
\"|\"\"o\"Normalized LMS Filters
\"|\"\"\\\"Finite Impulse Response (FIR) Interpolator
\"o\"Matrix Functions
\"|\"\"o\"Matrix Addition
\"|\"\"o\"Matrix Initialization
\"|\"\"o\"Matrix Inverse
\"|\"\"o\"Matrix Multiplication
\"|\"\"o\"Matrix Scale
\"|\"\"o\"Matrix Subtraction
\"|\"\"\\\"Matrix Transpose
\"o\"Transform Functions
\"|\"\"o\"Complex FFT Functions
\"|\"\"o\"Radix-8 Complex FFT Functions
\"|\"\"o\"DCT Type IV Functions
\"|\"\"o\"Real FFT Functions
\"|\"\"o\"Complex FFT Tables
\"|\"\"\\\"RealFFT
\"o\"Controller Functions
\"|\"\"o\"Sine Cosine
\"|\"\"o\"PID Motor Control
\"|\"\"o\"Vector Clarke Transform
\"|\"\"o\"Vector Inverse Clarke Transform
\"|\"\"o\"Vector Park Transform
\"|\"\"\\\"Vector Inverse Park transform
\"o\"Statistics Functions
\"|\"\"o\"Maximum
\"|\"\"o\"Mean
\"|\"\"o\"Minimum
\"|\"\"o\"Power
\"|\"\"o\"Root mean square (RMS)
\"|\"\"o\"Standard deviation
\"|\"\"\\\"Variance
\"o\"Support Functions
\"|\"\"o\"Vector Copy
\"|\"\"o\"Vector Fill
\"|\"\"o\"Convert 32-bit floating point value
\"|\"\"o\"Convert 16-bit Integer value
\"|\"\"o\"Convert 32-bit Integer value
\"|\"\"\\\"Convert 8-bit Integer value
\"o\"Interpolation Functions
\"|\"\"o\"Linear Interpolation
\"|\"\"\\\"Bilinear Interpolation
\"\\\"Examples
\" \"\"o\"Class Marks Example
\" \"\"o\"Convolution Example
\" \"\"o\"Dot Product Example
\" \"\"o\"Frequency Bin Example
\" \"\"o\"FIR Lowpass Filter Example
\" \"\"o\"Graphic Audio Equalizer Example
\" \"\"o\"Linear Interpolate Example
\" \"\"o\"Matrix Example
\" \"\"o\"Signal Convergence Example
\" \"\"o\"SineCosine Example
\" \"\"\\\"Variance Example
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/modules.js",
    "content": "var modules =\n[\n    [ \"Basic Math Functions\", \"group__group_math.html\", \"group__group_math\" ],\n    [ \"Fast Math Functions\", \"group__group_fast_math.html\", \"group__group_fast_math\" ],\n    [ \"Complex Math Functions\", \"group__group_cmplx_math.html\", \"group__group_cmplx_math\" ],\n    [ \"Filtering Functions\", \"group__group_filters.html\", \"group__group_filters\" ],\n    [ \"Matrix Functions\", \"group__group_matrix.html\", \"group__group_matrix\" ],\n    [ \"Transform Functions\", \"group__group_transforms.html\", \"group__group_transforms\" ],\n    [ \"Controller Functions\", \"group__group_controller.html\", \"group__group_controller\" ],\n    [ \"Statistics Functions\", \"group__group_stats.html\", \"group__group_stats\" ],\n    [ \"Support Functions\", \"group__group_support.html\", \"group__group_support\" ],\n    [ \"Interpolation Functions\", \"group__group_interpolation.html\", \"group__group_interpolation\" ],\n    [ \"Examples\", \"group__group_examples.html\", \"group__group_examples\" ]\n];"
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  {
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\n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null) \n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) { \n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).show();\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+11) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); 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};\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  navTo(o,toroot,window.location.hash,relpath);\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n\n  $(window).load(showRoot);\n}\n\n"
  },
  {
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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Instance structure for the Q15 bilinear interpolation function.  \n
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arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
  
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Instance structure for the high precision Q31 Biquad cascade filter.  \n More...
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\nData Fields
uint8_t numStages
 
q63_t * pState
 
q31_t * pCoeffs
 
uint8_t postShift
 
\n
Description
\n
Examples: 
arm_graphic_equalizer_example_q31.c.
\n
Field Documentation
\n\n
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uint8_t arm_biquad_cas_df1_32x64_ins_q31::numStages
\n
\n
number of 2nd order stages in the filter. Overall order is 2*numStages. 
\n\n
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().
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q31_t* arm_biquad_cas_df1_32x64_ins_q31::pCoeffs
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points to the array of coefficients. The array is of length 5*numStages. 
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Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().
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uint8_t arm_biquad_cas_df1_32x64_ins_q31::postShift
\n
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additional shift, in bits, applied to each output sample. 
\n\n
Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().
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q63_t* arm_biquad_cas_df1_32x64_ins_q31::pState
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points to the array of state coefficients. The array is of length 4*numStages. 
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Referenced by arm_biquad_cas_df1_32x64_init_q31(), and arm_biquad_cas_df1_32x64_q31().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_biquad_cascade_df2T_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_biquad_cascade_df2T_instance_f32 Struct Reference
  
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Instance structure for the floating-point transposed direct form II Biquad cascade filter.  \n
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\nData Fields
uint8_t numStages
 
float32_t * pState
 
float32_t * pCoeffs
 
\n
Field Documentation
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uint8_t arm_biquad_cascade_df2T_instance_f32::numStages
\n
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number of 2nd order stages in the filter. Overall order is 2*numStages. 
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Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().
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float32_t* arm_biquad_cascade_df2T_instance_f32::pCoeffs
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points to the array of coefficients. The array is of length 5*numStages. 
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Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().
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float32_t* arm_biquad_cascade_df2T_instance_f32::pState
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points to the array of state coefficients. The array is of length 2*numStages. 
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Referenced by arm_biquad_cascade_df2T_f32(), and arm_biquad_cascade_df2T_init_f32().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_biquad_casd_df1_inst_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_biquad_casd_df1_inst_f32 Struct Reference
  
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Instance structure for the floating-point Biquad cascade filter.  \n
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\nData Fields
uint32_t numStages
 
float32_t * pState
 
float32_t * pCoeffs
 
\n
Field Documentation
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uint32_t arm_biquad_casd_df1_inst_f32::numStages
\n
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number of 2nd order stages in the filter. Overall order is 2*numStages. 
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Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().
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float32_t* arm_biquad_casd_df1_inst_f32::pCoeffs
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Points to the array of coefficients. The array is of length 5*numStages. 
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Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().
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float32_t* arm_biquad_casd_df1_inst_f32::pState
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Points to the array of state coefficients. The array is of length 4*numStages. 
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Referenced by arm_biquad_cascade_df1_f32(), and arm_biquad_cascade_df1_init_f32().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_biquad_casd_df1_inst_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_biquad_casd_df1_inst_q15 Struct Reference
  
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Instance structure for the Q15 Biquad cascade filter.  \n
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\nData Fields
int8_t numStages
 
q15_t * pState
 
q15_t * pCoeffs
 
int8_t postShift
 
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Field Documentation
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int8_t arm_biquad_casd_df1_inst_q15::numStages
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number of 2nd order stages in the filter. Overall order is 2*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().
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q15_t* arm_biquad_casd_df1_inst_q15::pCoeffs
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Points to the array of coefficients. The array is of length 5*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().
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int8_t arm_biquad_casd_df1_inst_q15::postShift
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Additional shift, in bits, applied to each output sample. 
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Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().
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q15_t* arm_biquad_casd_df1_inst_q15::pState
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Points to the array of state coefficients. The array is of length 4*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q15(), arm_biquad_cascade_df1_init_q15(), and arm_biquad_cascade_df1_q15().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_biquad_casd_df1_inst_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_biquad_casd_df1_inst_q31 Struct Reference
  
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Instance structure for the Q31 Biquad cascade filter.  \n More...
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uint32_t numStages
 
q31_t * pState
 
q31_t * pCoeffs
 
uint8_t postShift
 
\n
Description
\n
Examples: 
arm_graphic_equalizer_example_q31.c.
\n
Field Documentation
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uint32_t arm_biquad_casd_df1_inst_q31::numStages
\n
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number of 2nd order stages in the filter. Overall order is 2*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().
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q31_t* arm_biquad_casd_df1_inst_q31::pCoeffs
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Points to the array of coefficients. The array is of length 5*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().
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uint8_t arm_biquad_casd_df1_inst_q31::postShift
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Additional shift, in bits, applied to each output sample. 
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Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().
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q31_t* arm_biquad_casd_df1_inst_q31::pState
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Points to the array of state coefficients. The array is of length 4*numStages. 
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Referenced by arm_biquad_cascade_df1_fast_q31(), arm_biquad_cascade_df1_init_q31(), and arm_biquad_cascade_df1_q31().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_cfft_instance_f32 Struct Reference
  
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Instance structure for the floating-point CFFT/CIFFT function.  \n
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uint16_t fftLen
 
const float32_t * pTwiddle
 
const uint16_t * pBitRevTable
 
uint16_t bitRevLength
 
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Field Documentation
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uint16_t arm_cfft_instance_f32::bitRevLength
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bit reversal table length. 
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Referenced by arm_cfft_f32(), and arm_rfft_fast_init_f32().
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uint16_t arm_cfft_instance_f32::fftLen
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length of the FFT. 
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Referenced by arm_cfft_f32(), arm_cfft_radix8by2_f32(), arm_cfft_radix8by4_f32(), arm_rfft_fast_f32(), and arm_rfft_fast_init_f32().
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const uint16_t* arm_cfft_instance_f32::pBitRevTable
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points to the bit reversal table. 
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Referenced by arm_cfft_f32(), and arm_rfft_fast_init_f32().
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const float32_t* arm_cfft_instance_f32::pTwiddle
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points to the Twiddle factor table. 
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Referenced by arm_cfft_f32(), arm_cfft_radix8by2_f32(), and arm_cfft_radix8by4_f32().
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  • arm_cfft_instance_f32
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_cfft_radix2_instance_f32 Struct Reference
  
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Instance structure for the floating-point CFFT/CIFFT function.  \n
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uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
float32_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
float32_t onebyfftLen
 
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Field Documentation
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uint8_t arm_cfft_radix2_instance_f32::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_f32::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_f32::fftLen
\n
\n
length of the FFT. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix2_instance_f32::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t arm_cfft_radix2_instance_f32::onebyfftLen
\n
\n
value of 1/fftLen. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t* arm_cfft_radix2_instance_f32::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t* arm_cfft_radix2_instance_f32::pTwiddle
\n
\n
points to the Twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_f32::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_f32(), and arm_cfft_radix2_init_f32().
\n\n
\n
\n
\n
\n\n
\n  \n
\n\n\n"
  },
  {
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
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\nData Fields  
\n  
\n
arm_cfft_radix2_instance_q15 Struct Reference
  
\n
\n
\n\n
Instance structure for the Q15 CFFT/CIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
q15_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix2_instance_q15::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix2_init_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q15::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q15::fftLen
\n
\n
length of the FFT. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix2_instance_q15::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t* arm_cfft_radix2_instance_q15::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q15_t* arm_cfft_radix2_instance_q15::pTwiddle
\n
\n
points to the Sin twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q15::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_init_q15(), and arm_cfft_radix2_q15().
\n\n
\n
\n
\n
\n\n
\n  \n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q15.js",
    "content": "var structarm__cfft__radix2__instance__q15 =\n[\n    [ \"bitReverseFlag\", \"structarm__cfft__radix2__instance__q15.html#af8300c1f60caa21e6b44b9240ab5af19\", null ],\n    [ \"bitRevFactor\", \"structarm__cfft__radix2__instance__q15.html#a8722720c542cabd41df83fe88ef4f4cb\", null ],\n    [ \"fftLen\", \"structarm__cfft__radix2__instance__q15.html#a874085647351dcf3f0de39d2b1d49744\", null ],\n    [ \"ifftFlag\", \"structarm__cfft__radix2__instance__q15.html#ab5c073286bdd2f6e2bf783ced36bf1de\", null ],\n    [ \"pBitRevTable\", \"structarm__cfft__radix2__instance__q15.html#ab88afeff6493be3c8b5e4530efa82d51\", null ],\n    [ \"pTwiddle\", \"structarm__cfft__radix2__instance__q15.html#a3809dd15e7cbf1a054c728cfbbb0cc5a\", null ],\n    [ \"twidCoefModifier\", \"structarm__cfft__radix2__instance__q15.html#a6f2ab87fb4c568656e1f92f687b5c850\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix2_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
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\nData Fields  
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\n
arm_cfft_radix2_instance_q31 Struct Reference
  
\n
\n
\n\n
Instance structure for the Radix-2 Q31 CFFT/CIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
q31_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix2_instance_q31::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix2_init_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q31::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q31::fftLen
\n
\n
length of the FFT. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix2_instance_q31::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t* arm_cfft_radix2_instance_q31::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t* arm_cfft_radix2_instance_q31::pTwiddle
\n
\n
points to the Twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix2_instance_q31::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix2_init_q31(), and arm_cfft_radix2_q31().
\n\n
\n
\n
\n
\n\n
\n  \n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix2__instance__q31.js",
    "content": "var structarm__cfft__radix2__instance__q31 =\n[\n    [ \"bitReverseFlag\", \"structarm__cfft__radix2__instance__q31.html#a6239b8d268285334e88c008c07d68616\", null ],\n    [ \"bitRevFactor\", \"structarm__cfft__radix2__instance__q31.html#a9d17a87263953fe3559a007512c9f3a4\", null ],\n    [ \"fftLen\", \"structarm__cfft__radix2__instance__q31.html#a960199f1373a192366878ef279eab00f\", null ],\n    [ \"ifftFlag\", \"structarm__cfft__radix2__instance__q31.html#a2607378ce64be16698bb8a3b1af8d3c8\", null ],\n    [ \"pBitRevTable\", \"structarm__cfft__radix2__instance__q31.html#ada8e5264f4b22ff4c621817978994674\", null ],\n    [ \"pTwiddle\", \"structarm__cfft__radix2__instance__q31.html#a1d5bbe9a991e133f81652a77a7985d23\", null ],\n    [ \"twidCoefModifier\", \"structarm__cfft__radix2__instance__q31.html#ae63ca9193322cd477970c1d2086407d1\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
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\n  
\n
arm_cfft_radix4_instance_f32 Struct Reference
  
\n
\n
\n\n
Instance structure for the floating-point CFFT/CIFFT function.  \n More...
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
float32_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
float32_t onebyfftLen
 
\n
Description
\n
Examples: 
arm_convolution_example_f32.c.
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix4_instance_f32::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix4_f32(), and arm_cfft_radix4_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_f32::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_f32::fftLen
\n
\n
length of the FFT. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
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\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix4_instance_f32::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix4_f32(), and arm_cfft_radix4_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t arm_cfft_radix4_instance_f32::onebyfftLen
\n
\n
value of 1/fftLen. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t* arm_cfft_radix4_instance_f32::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t* arm_cfft_radix4_instance_f32::pTwiddle
\n
\n
points to the Twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_f32::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_f32(), arm_cfft_radix4_init_f32(), and arm_rfft_f32().
\n\n
\n
\n
\n
\n\n
\n  \n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__f32.js",
    "content": "var structarm__cfft__radix4__instance__f32 =\n[\n    [ \"bitReverseFlag\", \"structarm__cfft__radix4__instance__f32.html#ac10927a1620195a88649ce63dab66120\", null ],\n    [ \"bitRevFactor\", \"structarm__cfft__radix4__instance__f32.html#acc8cb18a8b901b8321ab9d86491e41a3\", null ],\n    [ \"fftLen\", \"structarm__cfft__radix4__instance__f32.html#a7e6a6d290ce158ce9a15a45e364b021a\", null ],\n    [ \"ifftFlag\", \"structarm__cfft__radix4__instance__f32.html#a25d1da64dd6487c291f04d226f9acc66\", null ],\n    [ \"onebyfftLen\", \"structarm__cfft__radix4__instance__f32.html#ab9eed39e40b8d7c16381fbccf84467cd\", null ],\n    [ \"pBitRevTable\", \"structarm__cfft__radix4__instance__f32.html#a8da0d2ca69749fde8cbb95caeac6fe6a\", null ],\n    [ \"pTwiddle\", \"structarm__cfft__radix4__instance__f32.html#a14860c7544911702ca1fa0bf78204ef3\", null ],\n    [ \"twidCoefModifier\", \"structarm__cfft__radix4__instance__f32.html#abe31ea2157dfa233e389cdfd3b9993ee\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
\n\n
\n    \n
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\n
arm_cfft_radix4_instance_q15 Struct Reference
  
\n
\n
\n\n
Instance structure for the Q15 CFFT/CIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
q15_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix4_instance_q15::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), and arm_cfft_radix4_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_q15::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_q15::fftLen
\n
\n
length of the FFT. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
\n\n
\n
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uint8_t arm_cfft_radix4_instance_q15::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), and arm_cfft_radix4_q15().
\n\n
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uint16_t* arm_cfft_radix4_instance_q15::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
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q15_t* arm_cfft_radix4_instance_q15::pTwiddle
\n
\n
points to the twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
\n\n
\n
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\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_q15::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_init_q15(), arm_cfft_radix4_q15(), and arm_rfft_q15().
\n\n
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\n  \n
\n\n\n"
  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_cfft_radix4_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_cfft_radix4_instance_q31 Struct Reference
  
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Instance structure for the Q31 CFFT/CIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t fftLen
 
uint8_t ifftFlag
 
uint8_t bitReverseFlag
 
q31_t * pTwiddle
 
uint16_t * pBitRevTable
 
uint16_t twidCoefModifier
 
uint16_t bitRevFactor
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_cfft_radix4_instance_q31::bitReverseFlag
\n
\n
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), and arm_cfft_radix4_q31().
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uint16_t arm_cfft_radix4_instance_q31::bitRevFactor
\n
\n
bit reversal modifier that supports different size FFTs with the same bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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uint16_t arm_cfft_radix4_instance_q31::fftLen
\n
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length of the FFT. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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uint8_t arm_cfft_radix4_instance_q31::ifftFlag
\n
\n
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), and arm_cfft_radix4_q31().
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\n
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\n
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uint16_t* arm_cfft_radix4_instance_q31::pBitRevTable
\n
\n
points to the bit reversal table. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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\n
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q31_t* arm_cfft_radix4_instance_q31::pTwiddle
\n
\n
points to the twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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\n      \n        \n          \n        \n      
uint16_t arm_cfft_radix4_instance_q31::twidCoefModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_cfft_radix4_init_q31(), arm_cfft_radix4_q31(), and arm_rfft_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__cfft__radix4__instance__q31.js",
    "content": "var structarm__cfft__radix4__instance__q31 =\n[\n    [ \"bitReverseFlag\", \"structarm__cfft__radix4__instance__q31.html#a5a7c4f4c7b3fb655cbb2bc11ef160a2a\", null ],\n    [ \"bitRevFactor\", \"structarm__cfft__radix4__instance__q31.html#a94d2fead4efa4d5eaae142bbe30b0e15\", null ],\n    [ \"fftLen\", \"structarm__cfft__radix4__instance__q31.html#ab413d2a5d3f45fa187d93813bf3bf81b\", null ],\n    [ \"ifftFlag\", \"structarm__cfft__radix4__instance__q31.html#adc0a62ba669ad2282ecbe43d5d96abab\", null ],\n    [ \"pBitRevTable\", \"structarm__cfft__radix4__instance__q31.html#a33a3bc774c97373261699463c05dfe54\", null ],\n    [ \"pTwiddle\", \"structarm__cfft__radix4__instance__q31.html#a561c22dee4cbdcfa0fd5f15106ecc306\", null ],\n    [ \"twidCoefModifier\", \"structarm__cfft__radix4__instance__q31.html#a8cf8187b8232815cf17ee82bf572ecf9\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_dct4_instance_f32 Struct Reference
  
\n
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Instance structure for the floating-point DCT4/IDCT4 function.  \n
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\nData Fields
uint16_t N
 
uint16_t Nby2
 
float32_t normalize
 
float32_t * pTwiddle
 
float32_t * pCosFactor
 
arm_rfft_instance_f32 * pRfft
 
arm_cfft_radix4_instance_f32 * pCfft
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_f32::N
\n
\n
length of the DCT4. 
\n\n
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().
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\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_f32::Nby2
\n
\n
half of the length of the DCT4. 
\n\n
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().
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\n
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float32_t arm_dct4_instance_f32::normalize
\n
\n
normalizing factor. 
\n\n
Referenced by arm_dct4_init_f32().
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arm_cfft_radix4_instance_f32* arm_dct4_instance_f32::pCfft
\n
\n
points to the complex FFT instance. 
\n\n
Referenced by arm_dct4_init_f32().
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float32_t* arm_dct4_instance_f32::pCosFactor
\n
\n
points to the cosFactor table. 
\n\n
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
arm_rfft_instance_f32* arm_dct4_instance_f32::pRfft
\n
\n
points to the real FFT instance. 
\n\n
Referenced by arm_dct4_init_f32().
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\n
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\n      \n        \n          \n        \n      
float32_t* arm_dct4_instance_f32::pTwiddle
\n
\n
points to the twiddle factor table. 
\n\n
Referenced by arm_dct4_f32(), and arm_dct4_init_f32().
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    \n    
  • arm_dct4_instance_f32
    • \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__f32.js",
    "content": "var structarm__dct4__instance__f32 =\n[\n    [ \"N\", \"structarm__dct4__instance__f32.html#a262b29a51c371b46efc89120e31ccf37\", null ],\n    [ \"Nby2\", \"structarm__dct4__instance__f32.html#adb1ef2739ddbe62e5cdadc47455a4147\", null ],\n    [ \"normalize\", \"structarm__dct4__instance__f32.html#a61ce8c967b2e998a9c0041cca73cdef8\", null ],\n    [ \"pCfft\", \"structarm__dct4__instance__f32.html#a018f7860b6e070af533fb7d76c7cdc32\", null ],\n    [ \"pCosFactor\", \"structarm__dct4__instance__f32.html#a6da1187e070801e011ce5e0582efa861\", null ],\n    [ \"pRfft\", \"structarm__dct4__instance__f32.html#a978f37fc19add31af243ab5c63ae502f\", null ],\n    [ \"pTwiddle\", \"structarm__dct4__instance__f32.html#ad13544aafad268588c62e3eb35ae662c\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_dct4_instance_q15 Struct Reference
  
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Instance structure for the Q15 DCT4/IDCT4 function.  \n
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\nData Fields
uint16_t N
 
uint16_t Nby2
 
q15_t normalize
 
q15_t * pTwiddle
 
q15_t * pCosFactor
 
arm_rfft_instance_q15 * pRfft
 
arm_cfft_radix4_instance_q15 * pCfft
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_q15::N
\n
\n
length of the DCT4. 
\n\n
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().
\n\n
\n
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\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_q15::Nby2
\n
\n
half of the length of the DCT4. 
\n\n
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().
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q15_t arm_dct4_instance_q15::normalize
\n
\n
normalizing factor. 
\n\n
Referenced by arm_dct4_init_q15().
\n\n
\n
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\n      \n        \n          \n        \n      
arm_cfft_radix4_instance_q15* arm_dct4_instance_q15::pCfft
\n
\n
points to the complex FFT instance. 
\n\n
Referenced by arm_dct4_init_q15().
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q15_t* arm_dct4_instance_q15::pCosFactor
\n
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points to the cosFactor table. 
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Referenced by arm_dct4_init_q15(), and arm_dct4_q15().
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arm_rfft_instance_q15* arm_dct4_instance_q15::pRfft
\n
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points to the real FFT instance. 
\n\n
Referenced by arm_dct4_init_q15().
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\n
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q15_t* arm_dct4_instance_q15::pTwiddle
\n
\n
points to the twiddle factor table. 
\n\n
Referenced by arm_dct4_init_q15(), and arm_dct4_q15().
\n\n
\n
\n
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\n  
    \n    
  • arm_dct4_instance_q15
    • \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q15.js",
    "content": "var structarm__dct4__instance__q15 =\n[\n    [ \"N\", \"structarm__dct4__instance__q15.html#a53d24009bb9b2e93d0aa07db7f1a6c25\", null ],\n    [ \"Nby2\", \"structarm__dct4__instance__q15.html#af43dcbbc2fc661ffbc525afe3dcbd7da\", null ],\n    [ \"normalize\", \"structarm__dct4__instance__q15.html#a197098140d68e89a08f7a249003a0b86\", null ],\n    [ \"pCfft\", \"structarm__dct4__instance__q15.html#a7284932ee8c36107c33815eb62eadffc\", null ],\n    [ \"pCosFactor\", \"structarm__dct4__instance__q15.html#ac76df681b1bd502fb4874c06f055dded\", null ],\n    [ \"pRfft\", \"structarm__dct4__instance__q15.html#a11cf95c1cd9dd2dd5e4b81b8f88dc208\", null ],\n    [ \"pTwiddle\", \"structarm__dct4__instance__q15.html#abc6c847e9f906781e1d5da40e9aafa76\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_dct4_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
\n  
\n
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arm_dct4_instance_q31 Struct Reference
  
\n
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\n\n
Instance structure for the Q31 DCT4/IDCT4 function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t N
 
uint16_t Nby2
 
q31_t normalize
 
q31_t * pTwiddle
 
q31_t * pCosFactor
 
arm_rfft_instance_q31 * pRfft
 
arm_cfft_radix4_instance_q31 * pCfft
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_q31::N
\n
\n
length of the DCT4. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_dct4_instance_q31::Nby2
\n
\n
half of the length of the DCT4. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
\n\n
\n
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q31_t arm_dct4_instance_q31::normalize
\n
\n
normalizing factor. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
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arm_cfft_radix4_instance_q31* arm_dct4_instance_q31::pCfft
\n
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points to the complex FFT instance. 
\n\n
Referenced by arm_dct4_init_q31().
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q31_t* arm_dct4_instance_q31::pCosFactor
\n
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points to the cosFactor table. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
\n\n
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arm_rfft_instance_q31* arm_dct4_instance_q31::pRfft
\n
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points to the real FFT instance. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
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q31_t* arm_dct4_instance_q31::pTwiddle
\n
\n
points to the twiddle factor table. 
\n\n
Referenced by arm_dct4_init_q31(), and arm_dct4_q31().
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    \n    
  • arm_dct4_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__dct4__instance__q31.js",
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_decimate_instance_f32 Struct Reference
  
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Instance structure for the floating-point FIR decimator.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint8_t M
 
uint16_t numTaps
 
float32_t * pCoeffs
 
float32_t * pState
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_fir_decimate_instance_f32::M
\n
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decimation factor. 
\n\n
Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().
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uint16_t arm_fir_decimate_instance_f32::numTaps
\n
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number of coefficients in the filter. 
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Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().
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float32_t* arm_fir_decimate_instance_f32::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().
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float32_t* arm_fir_decimate_instance_f32::pState
\n
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_fir_decimate_f32(), and arm_fir_decimate_init_f32().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__decimate__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_decimate_instance_q15 Struct Reference
  
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Instance structure for the Q15 FIR decimator.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint8_t M
 
uint16_t numTaps
 
q15_t * pCoeffs
 
q15_t * pState
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_fir_decimate_instance_q15::M
\n
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decimation factor. 
\n\n
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().
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uint16_t arm_fir_decimate_instance_q15::numTaps
\n
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number of coefficients in the filter. 
\n\n
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().
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q15_t* arm_fir_decimate_instance_q15::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().
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q15_t* arm_fir_decimate_instance_q15::pState
\n
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_fir_decimate_fast_q15(), arm_fir_decimate_init_q15(), and arm_fir_decimate_q15().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_decimate_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_decimate_instance_q31 Struct Reference
  
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Instance structure for the Q31 FIR decimator.  \n
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\nData Fields
uint8_t M
 
uint16_t numTaps
 
q31_t * pCoeffs
 
q31_t * pState
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_fir_decimate_instance_q31::M
\n
\n
decimation factor. 
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Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().
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uint16_t arm_fir_decimate_instance_q31::numTaps
\n
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number of coefficients in the filter. 
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Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().
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q31_t* arm_fir_decimate_instance_q31::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().
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q31_t* arm_fir_decimate_instance_q31::pState
\n
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points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_fir_decimate_fast_q31(), arm_fir_decimate_init_q31(), and arm_fir_decimate_q31().
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  },
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_instance_f32 Struct Reference
  
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Instance structure for the floating-point FIR filter.  \n More...
\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numTaps
 
float32_t * pState
 
float32_t * pCoeffs
 
\n
Description
\n
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.
\n
Field Documentation
\n\n
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\n      \n        \n          \n        \n      
uint16_t arm_fir_instance_f32::numTaps
\n
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number of filter coefficients in the filter. 
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Referenced by arm_fir_f32(), and arm_fir_init_f32().
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float32_t* arm_fir_instance_f32::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_f32(), and arm_fir_init_f32().
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float32_t* arm_fir_instance_f32::pState
\n
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points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_fir_f32(), and arm_fir_init_f32().
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  • arm_fir_instance_f32
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  • Generated on Mon Mar 18 2013 13:37:57 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_instance_q15 Struct Reference
  
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Instance structure for the Q15 FIR filter.  \n
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\nData Fields
uint16_t numTaps
 
q15_t * pState
 
q15_t * pCoeffs
 
\n
Field Documentation
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uint16_t arm_fir_instance_q15::numTaps
\n
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number of filter coefficients in the filter. 
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Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().
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q15_t* arm_fir_instance_q15::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().
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q15_t* arm_fir_instance_q15::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_fir_fast_q15(), arm_fir_init_q15(), and arm_fir_q15().
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  • arm_fir_instance_q15
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_instance_q31 Struct Reference
  
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Instance structure for the Q31 FIR filter.  \n
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\nData Fields
uint16_t numTaps
 
q31_t * pState
 
q31_t * pCoeffs
 
\n
Field Documentation
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uint16_t arm_fir_instance_q31::numTaps
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number of filter coefficients in the filter. 
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Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().
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q31_t* arm_fir_instance_q31::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().
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q31_t* arm_fir_instance_q31::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_fir_fast_q31(), arm_fir_init_q31(), and arm_fir_q31().
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  • arm_fir_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__instance__q7.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_instance_q7 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS DSP Software Library
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arm_fir_instance_q7 Struct Reference
  
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Instance structure for the Q7 FIR filter.  \n
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uint16_t numTaps
 
q7_t * pState
 
q7_t * pCoeffs
 
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Field Documentation
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uint16_t arm_fir_instance_q7::numTaps
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number of filter coefficients in the filter. 
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Referenced by arm_fir_init_q7(), and arm_fir_q7().
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q7_t* arm_fir_instance_q7::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_fir_init_q7(), and arm_fir_q7().
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q7_t* arm_fir_instance_q7::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_fir_init_q7(), and arm_fir_q7().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_interpolate_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_interpolate_instance_f32 Struct Reference
  
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Instance structure for the floating-point FIR interpolator.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint8_t L
 
uint16_t phaseLength
 
float32_t * pCoeffs
 
float32_t * pState
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_fir_interpolate_instance_f32::L
\n
\n
upsample factor. 
\n\n
Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().
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float32_t* arm_fir_interpolate_instance_f32::pCoeffs
\n
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points to the coefficient array. The array is of length L*phaseLength. 
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Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().
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uint16_t arm_fir_interpolate_instance_f32::phaseLength
\n
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length of each polyphase filter component. 
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Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().
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\n      \n        \n          \n        \n      
float32_t* arm_fir_interpolate_instance_f32::pState
\n
\n
points to the state variable array. The array is of length phaseLength+numTaps-1. 
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Referenced by arm_fir_interpolate_f32(), and arm_fir_interpolate_init_f32().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__f32.js",
    "content": "var structarm__fir__interpolate__instance__f32 =\n[\n    [ \"L\", \"structarm__fir__interpolate__instance__f32.html#ae6f94dcc0ccd8aa4bc699b20985d9df5\", null ],\n    [ \"pCoeffs\", \"structarm__fir__interpolate__instance__f32.html#a86053b715980a93c9df630d6de5bb63c\", null ],\n    [ \"phaseLength\", \"structarm__fir__interpolate__instance__f32.html#a389e669e13ec56292a70db8e92194b12\", null ],\n    [ \"pState\", \"structarm__fir__interpolate__instance__f32.html#a42a8ba1bda85fa86d7b6c84d3da4c75b\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_interpolate_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_interpolate_instance_q15 Struct Reference
  
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Instance structure for the Q15 FIR interpolator.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint8_t L
 
uint16_t phaseLength
 
q15_t * pCoeffs
 
q15_t * pState
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_fir_interpolate_instance_q15::L
\n
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upsample factor. 
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Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().
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q15_t* arm_fir_interpolate_instance_q15::pCoeffs
\n
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points to the coefficient array. The array is of length L*phaseLength. 
\n\n
Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().
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uint16_t arm_fir_interpolate_instance_q15::phaseLength
\n
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length of each polyphase filter component. 
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Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().
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q15_t* arm_fir_interpolate_instance_q15::pState
\n
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points to the state variable array. The array is of length blockSize+phaseLength-1. 
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Referenced by arm_fir_interpolate_init_q15(), and arm_fir_interpolate_q15().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q15.js",
    "content": "var structarm__fir__interpolate__instance__q15 =\n[\n    [ \"L\", \"structarm__fir__interpolate__instance__q15.html#a5431bdc079e72a973b51d359f7f13603\", null ],\n    [ \"pCoeffs\", \"structarm__fir__interpolate__instance__q15.html#a767d91d61d4c0beeddd4325d28d28e24\", null ],\n    [ \"phaseLength\", \"structarm__fir__interpolate__instance__q15.html#ad5178a02a697a77e0d0e60705d9f0a19\", null ],\n    [ \"pState\", \"structarm__fir__interpolate__instance__q15.html#a26b864363fa47954248f2590e3a82a3c\", null ]\n];"
  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_interpolate_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_interpolate_instance_q31 Struct Reference
  
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Instance structure for the Q31 FIR interpolator.  \n
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\nData Fields
uint8_t L
 
uint16_t phaseLength
 
q31_t * pCoeffs
 
q31_t * pState
 
\n
Field Documentation
\n\n
\n
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uint8_t arm_fir_interpolate_instance_q31::L
\n
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upsample factor. 
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Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().
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q31_t* arm_fir_interpolate_instance_q31::pCoeffs
\n
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points to the coefficient array. The array is of length L*phaseLength. 
\n\n
Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().
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uint16_t arm_fir_interpolate_instance_q31::phaseLength
\n
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length of each polyphase filter component. 
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Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().
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q31_t* arm_fir_interpolate_instance_q31::pState
\n
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points to the state variable array. The array is of length blockSize+phaseLength-1. 
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Referenced by arm_fir_interpolate_init_q31(), and arm_fir_interpolate_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__interpolate__instance__q31.js",
    "content": "var structarm__fir__interpolate__instance__q31 =\n[\n    [ \"L\", \"structarm__fir__interpolate__instance__q31.html#a5cdf0a631cb74e0e9588c388abe5235c\", null ],\n    [ \"pCoeffs\", \"structarm__fir__interpolate__instance__q31.html#afa719433687e1936ec3403d0d32f06e6\", null ],\n    [ \"phaseLength\", \"structarm__fir__interpolate__instance__q31.html#a5d243796584afc7cd6c557f00b7acca5\", null ],\n    [ \"pState\", \"structarm__fir__interpolate__instance__q31.html#addde04514b6e6ac72be3d609f0398b1a\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_lattice_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_lattice_instance_f32 Struct Reference
  
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Instance structure for the floating-point FIR lattice filter.  \n
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\nData Fields
uint16_t numStages
 
float32_t * pState
 
float32_t * pCoeffs
 
\n
Field Documentation
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uint16_t arm_fir_lattice_instance_f32::numStages
\n
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number of filter stages. 
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Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().
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float32_t* arm_fir_lattice_instance_f32::pCoeffs
\n
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points to the coefficient array. The array is of length numStages. 
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Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().
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float32_t* arm_fir_lattice_instance_f32::pState
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points to the state variable array. The array is of length numStages. 
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Referenced by arm_fir_lattice_f32(), and arm_fir_lattice_init_f32().
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__f32.js",
    "content": "var structarm__fir__lattice__instance__f32 =\n[\n    [ \"numStages\", \"structarm__fir__lattice__instance__f32.html#ad369bd9997a250f195254df37408a38f\", null ],\n    [ \"pCoeffs\", \"structarm__fir__lattice__instance__f32.html#a33bf5948c947f9ef80a99717cb0a0a43\", null ],\n    [ \"pState\", \"structarm__fir__lattice__instance__f32.html#ae348884a1ba9b83fadccd5da640cbcaf\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_lattice_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_lattice_instance_q15 Struct Reference
  
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Instance structure for the Q15 FIR lattice filter.  \n
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\nData Fields
uint16_t numStages
 
q15_t * pState
 
q15_t * pCoeffs
 
\n
Field Documentation
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uint16_t arm_fir_lattice_instance_q15::numStages
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number of filter stages. 
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Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().
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q15_t* arm_fir_lattice_instance_q15::pCoeffs
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points to the coefficient array. The array is of length numStages. 
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Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().
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q15_t* arm_fir_lattice_instance_q15::pState
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points to the state variable array. The array is of length numStages. 
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Referenced by arm_fir_lattice_init_q15(), and arm_fir_lattice_q15().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q15.js",
    "content": "var structarm__fir__lattice__instance__q15 =\n[\n    [ \"numStages\", \"structarm__fir__lattice__instance__q15.html#a38b179138d6a6c9cac4f8f79b6fd5357\", null ],\n    [ \"pCoeffs\", \"structarm__fir__lattice__instance__q15.html#a78f872826140069cf67836fff87360bc\", null ],\n    [ \"pState\", \"structarm__fir__lattice__instance__q15.html#a37b90dea2bc3ee7c9951a9fe74db0cbb\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_lattice_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_lattice_instance_q31 Struct Reference
  
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Instance structure for the Q31 FIR lattice filter.  \n
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\nData Fields
uint16_t numStages
 
q31_t * pState
 
q31_t * pCoeffs
 
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Field Documentation
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uint16_t arm_fir_lattice_instance_q31::numStages
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number of filter stages. 
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Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().
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q31_t* arm_fir_lattice_instance_q31::pCoeffs
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points to the coefficient array. The array is of length numStages. 
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Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().
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q31_t* arm_fir_lattice_instance_q31::pState
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points to the state variable array. The array is of length numStages. 
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Referenced by arm_fir_lattice_init_q31(), and arm_fir_lattice_q31().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__lattice__instance__q31.js",
    "content": "var structarm__fir__lattice__instance__q31 =\n[\n    [ \"numStages\", \"structarm__fir__lattice__instance__q31.html#a9f3773bbb76bc5a8a5ee9d37786bf478\", null ],\n    [ \"pCoeffs\", \"structarm__fir__lattice__instance__q31.html#a66c3364bf5863cd45e05f1652c3dc522\", null ],\n    [ \"pState\", \"structarm__fir__lattice__instance__q31.html#a08fe9494ab7cd336b791e9657adadcf6\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_fir_sparse_instance_f32 Struct Reference
  
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Instance structure for the floating-point sparse FIR filter.  \n
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uint16_t numTaps
 
uint16_t stateIndex
 
float32_t * pState
 
float32_t * pCoeffs
 
uint16_t maxDelay
 
int32_t * pTapDelay
 
\n
Field Documentation
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uint16_t arm_fir_sparse_instance_f32::maxDelay
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maximum offset specified by the pTapDelay array. 
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
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uint16_t arm_fir_sparse_instance_f32::numTaps
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number of coefficients in the filter. 
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
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float32_t* arm_fir_sparse_instance_f32::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
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float32_t* arm_fir_sparse_instance_f32::pState
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points to the state buffer array. The array is of length maxDelay+blockSize-1. 
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Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
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int32_t* arm_fir_sparse_instance_f32::pTapDelay
\n
\n
points to the array of delay values. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_fir_sparse_instance_f32::stateIndex
\n
\n
state buffer index. Points to the oldest sample in the state buffer. 
\n\n
Referenced by arm_fir_sparse_f32(), and arm_fir_sparse_init_f32().
\n\n
\n
\n
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\n  \n
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  },
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
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\n  
\n
arm_fir_sparse_instance_q15 Struct Reference
  
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\n
\n\n
Instance structure for the Q15 sparse FIR filter.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numTaps
 
uint16_t stateIndex
 
q15_t * pState
 
q15_t * pCoeffs
 
uint16_t maxDelay
 
int32_t * pTapDelay
 
\n
Field Documentation
\n\n
\n
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uint16_t arm_fir_sparse_instance_q15::maxDelay
\n
\n
maximum offset specified by the pTapDelay array. 
\n\n
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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uint16_t arm_fir_sparse_instance_q15::numTaps
\n
\n
number of coefficients in the filter. 
\n\n
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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q15_t* arm_fir_sparse_instance_q15::pCoeffs
\n
\n
points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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q15_t* arm_fir_sparse_instance_q15::pState
\n
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points to the state buffer array. The array is of length maxDelay+blockSize-1. 
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Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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int32_t* arm_fir_sparse_instance_q15::pTapDelay
\n
\n
points to the array of delay values. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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\n
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uint16_t arm_fir_sparse_instance_q15::stateIndex
\n
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state buffer index. Points to the oldest sample in the state buffer. 
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Referenced by arm_fir_sparse_init_q15(), and arm_fir_sparse_q15().
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q15.js",
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_fir_sparse_instance_q31 Struct Reference
  
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\n\n
Instance structure for the Q31 sparse FIR filter.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numTaps
 
uint16_t stateIndex
 
q31_t * pState
 
q31_t * pCoeffs
 
uint16_t maxDelay
 
int32_t * pTapDelay
 
\n
Field Documentation
\n\n
\n
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uint16_t arm_fir_sparse_instance_q31::maxDelay
\n
\n
maximum offset specified by the pTapDelay array. 
\n\n
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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uint16_t arm_fir_sparse_instance_q31::numTaps
\n
\n
number of coefficients in the filter. 
\n\n
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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q31_t* arm_fir_sparse_instance_q31::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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q31_t* arm_fir_sparse_instance_q31::pState
\n
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points to the state buffer array. The array is of length maxDelay+blockSize-1. 
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Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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int32_t* arm_fir_sparse_instance_q31::pTapDelay
\n
\n
points to the array of delay values. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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uint16_t arm_fir_sparse_instance_q31::stateIndex
\n
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state buffer index. Points to the oldest sample in the state buffer. 
\n\n
Referenced by arm_fir_sparse_init_q31(), and arm_fir_sparse_q31().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__fir__sparse__instance__q7.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_fir_sparse_instance_q7 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_fir_sparse_instance_q7 Struct Reference
  
\n
\n
\n\n
Instance structure for the Q7 sparse FIR filter.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numTaps
 
uint16_t stateIndex
 
q7_t * pState
 
q7_t * pCoeffs
 
uint16_t maxDelay
 
int32_t * pTapDelay
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_fir_sparse_instance_q7::maxDelay
\n
\n
maximum offset specified by the pTapDelay array. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
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uint16_t arm_fir_sparse_instance_q7::numTaps
\n
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number of coefficients in the filter. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
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q7_t* arm_fir_sparse_instance_q7::pCoeffs
\n
\n
points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
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q7_t* arm_fir_sparse_instance_q7::pState
\n
\n
points to the state buffer array. The array is of length maxDelay+blockSize-1. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
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\n      \n        \n          \n        \n      
int32_t* arm_fir_sparse_instance_q7::pTapDelay
\n
\n
points to the array of delay values. The array is of length numTaps. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint16_t arm_fir_sparse_instance_q7::stateIndex
\n
\n
state buffer index. Points to the oldest sample in the state buffer. 
\n\n
Referenced by arm_fir_sparse_init_q7(), and arm_fir_sparse_q7().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_iir_lattice_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_iir_lattice_instance_f32 Struct Reference
  
\n
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\n\n
Instance structure for the floating-point IIR lattice filter.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numStages
 
float32_t * pState
 
float32_t * pkCoeffs
 
float32_t * pvCoeffs
 
\n
Field Documentation
\n\n
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uint16_t arm_iir_lattice_instance_f32::numStages
\n
\n
number of stages in the filter. 
\n\n
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().
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\n
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float32_t* arm_iir_lattice_instance_f32::pkCoeffs
\n
\n
points to the reflection coefficient array. The array is of length numStages. 
\n\n
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().
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float32_t* arm_iir_lattice_instance_f32::pState
\n
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points to the state variable array. The array is of length numStages+blockSize. 
\n\n
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().
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float32_t* arm_iir_lattice_instance_f32::pvCoeffs
\n
\n
points to the ladder coefficient array. The array is of length numStages+1. 
\n\n
Referenced by arm_iir_lattice_f32(), and arm_iir_lattice_init_f32().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_iir_lattice_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_iir_lattice_instance_q15 Struct Reference
  
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Instance structure for the Q15 IIR lattice filter.  \n
\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint16_t numStages
 
q15_t * pState
 
q15_t * pkCoeffs
 
q15_t * pvCoeffs
 
\n
Field Documentation
\n\n
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uint16_t arm_iir_lattice_instance_q15::numStages
\n
\n
number of stages in the filter. 
\n\n
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().
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\n
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q15_t* arm_iir_lattice_instance_q15::pkCoeffs
\n
\n
points to the reflection coefficient array. The array is of length numStages. 
\n\n
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().
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\n
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q15_t* arm_iir_lattice_instance_q15::pState
\n
\n
points to the state variable array. The array is of length numStages+blockSize. 
\n\n
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().
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q15_t* arm_iir_lattice_instance_q15::pvCoeffs
\n
\n
points to the ladder coefficient array. The array is of length numStages+1. 
\n\n
Referenced by arm_iir_lattice_init_q15(), and arm_iir_lattice_q15().
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q15.js",
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__iir__lattice__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_iir_lattice_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_iir_lattice_instance_q31 Struct Reference
  
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Instance structure for the Q31 IIR lattice filter.  \n
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\nData Fields
uint16_t numStages
 
q31_t * pState
 
q31_t * pkCoeffs
 
q31_t * pvCoeffs
 
\n
Field Documentation
\n\n
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\n      \n        \n          \n        \n      
uint16_t arm_iir_lattice_instance_q31::numStages
\n
\n
number of stages in the filter. 
\n\n
Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().
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q31_t* arm_iir_lattice_instance_q31::pkCoeffs
\n
\n
points to the reflection coefficient array. The array is of length numStages. 
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Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().
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q31_t* arm_iir_lattice_instance_q31::pState
\n
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points to the state variable array. The array is of length numStages+blockSize. 
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Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().
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q31_t* arm_iir_lattice_instance_q31::pvCoeffs
\n
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points to the ladder coefficient array. The array is of length numStages+1. 
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Referenced by arm_iir_lattice_init_q31(), and arm_iir_lattice_q31().
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_linear_interp_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_linear_interp_instance_f32 Struct Reference
  
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Instance structure for the floating-point Linear Interpolate function.  \n More...
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uint32_t nValues
 
float32_t x1
 
float32_t xSpacing
 
float32_t * pYData
 
\n
Description
\n
Examples: 
arm_linear_interp_example_f32.c.
\n
Field Documentation
\n\n
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\n      \n        \n          \n        \n      
uint32_t arm_linear_interp_instance_f32::nValues
\n
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nValues 
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Referenced by arm_linear_interp_f32().
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float32_t* arm_linear_interp_instance_f32::pYData
\n
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pointer to the table of Y values 
\n\n
Referenced by arm_linear_interp_f32().
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float32_t arm_linear_interp_instance_f32::x1
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x1 
\n\n
Referenced by arm_linear_interp_f32().
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float32_t arm_linear_interp_instance_f32::xSpacing
\n
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xSpacing 
\n\n
Referenced by arm_linear_interp_f32().
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\n  \n
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__linear__interp__instance__f32.js",
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_instance_f32 Struct Reference
  
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Instance structure for the floating-point LMS filter.  \n
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\nData Fields
uint16_t numTaps
 
float32_t * pState
 
float32_t * pCoeffs
 
float32_t mu
 
\n
Field Documentation
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float32_t arm_lms_instance_f32::mu
\n
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step size that controls filter coefficient updates. 
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Referenced by arm_lms_f32(), and arm_lms_init_f32().
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uint16_t arm_lms_instance_f32::numTaps
\n
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number of coefficients in the filter. 
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Referenced by arm_lms_f32(), and arm_lms_init_f32().
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float32_t* arm_lms_instance_f32::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_lms_f32(), and arm_lms_init_f32().
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float32_t* arm_lms_instance_f32::pState
\n
\n
points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_lms_f32(), and arm_lms_init_f32().
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    \n    
  • arm_lms_instance_f32
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__instance__f32.js",
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_instance_q15 Struct Reference
  
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Instance structure for the Q15 LMS filter.  \n
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\nData Fields
uint16_t numTaps
 
q15_t * pState
 
q15_t * pCoeffs
 
q15_t mu
 
uint32_t postShift
 
\n
Field Documentation
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q15_t arm_lms_instance_q15::mu
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step size that controls filter coefficient updates. 
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Referenced by arm_lms_init_q15(), and arm_lms_q15().
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uint16_t arm_lms_instance_q15::numTaps
\n
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number of coefficients in the filter. 
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Referenced by arm_lms_init_q15(), and arm_lms_q15().
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q15_t* arm_lms_instance_q15::pCoeffs
\n
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points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_lms_init_q15(), and arm_lms_q15().
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uint32_t arm_lms_instance_q15::postShift
\n
\n
bit shift applied to coefficients. 
\n\n
Referenced by arm_lms_init_q15(), and arm_lms_q15().
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q15_t* arm_lms_instance_q15::pState
\n
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_lms_init_q15(), and arm_lms_q15().
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  • arm_lms_instance_q15
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__instance__q15.js",
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_instance_q31 Struct Reference
  
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Instance structure for the Q31 LMS filter.  \n
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\nData Fields
uint16_t numTaps
 
q31_t * pState
 
q31_t * pCoeffs
 
q31_t mu
 
uint32_t postShift
 
\n
Field Documentation
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\n      \n        \n          \n        \n      
q31_t arm_lms_instance_q31::mu
\n
\n
step size that controls filter coefficient updates. 
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Referenced by arm_lms_init_q31(), and arm_lms_q31().
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uint16_t arm_lms_instance_q31::numTaps
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number of coefficients in the filter. 
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Referenced by arm_lms_init_q31(), and arm_lms_q31().
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q31_t* arm_lms_instance_q31::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_lms_init_q31(), and arm_lms_q31().
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uint32_t arm_lms_instance_q31::postShift
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bit shift applied to coefficients. 
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Referenced by arm_lms_init_q31(), and arm_lms_q31().
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q31_t* arm_lms_instance_q31::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_lms_init_q31(), and arm_lms_q31().
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  • arm_lms_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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  },
  {
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    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_norm_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_norm_instance_f32 Struct Reference
  
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Instance structure for the floating-point normalized LMS filter.  \n More...
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\nData Fields
uint16_t numTaps
 
float32_t * pState
 
float32_t * pCoeffs
 
float32_t mu
 
float32_t energy
 
float32_t x0
 
\n
Description
\n
Examples: 
arm_signal_converge_example_f32.c.
\n
Field Documentation
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float32_t arm_lms_norm_instance_f32::energy
\n
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saves previous frame energy. 
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Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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float32_t arm_lms_norm_instance_f32::mu
\n
\n
step size that control filter coefficient updates. 
\n\n
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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uint16_t arm_lms_norm_instance_f32::numTaps
\n
\n
number of coefficients in the filter. 
\n\n
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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float32_t* arm_lms_norm_instance_f32::pCoeffs
\n
\n
points to the coefficient array. The array is of length numTaps. 
\n\n
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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float32_t* arm_lms_norm_instance_f32::pState
\n
\n
points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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float32_t arm_lms_norm_instance_f32::x0
\n
\n
saves previous input sample. 
\n\n
Referenced by arm_lms_norm_f32(), and arm_lms_norm_init_f32().
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  • arm_lms_norm_instance_f32
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
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  {
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_norm_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_norm_instance_q15 Struct Reference
  
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Instance structure for the Q15 normalized LMS filter.  \n
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\nData Fields
uint16_t numTaps
 
q15_t * pState
 
q15_t * pCoeffs
 
q15_t mu
 
uint8_t postShift
 
q15_t * recipTable
 
q15_t energy
 
q15_t x0
 
\n
Field Documentation
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q15_t arm_lms_norm_instance_q15::energy
\n
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saves previous frame energy. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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q15_t arm_lms_norm_instance_q15::mu
\n
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step size that controls filter coefficient updates. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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uint16_t arm_lms_norm_instance_q15::numTaps
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Number of coefficients in the filter. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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q15_t* arm_lms_norm_instance_q15::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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uint8_t arm_lms_norm_instance_q15::postShift
\n
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bit shift applied to coefficients. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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q15_t* arm_lms_norm_instance_q15::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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q15_t* arm_lms_norm_instance_q15::recipTable
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Points to the reciprocal initial value table. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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q15_t arm_lms_norm_instance_q15::x0
\n
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saves previous input sample. 
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Referenced by arm_lms_norm_init_q15(), and arm_lms_norm_q15().
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  • arm_lms_norm_instance_q15
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q15.js",
    "content": "var structarm__lms__norm__instance__q15 =\n[\n    [ \"energy\", \"structarm__lms__norm__instance__q15.html#a1c81ded399919d8181026bc1c8602e7b\", null ],\n    [ \"mu\", \"structarm__lms__norm__instance__q15.html#a7ce00f21d11cfda6d963240641deea8c\", null ],\n    [ \"numTaps\", \"structarm__lms__norm__instance__q15.html#a9ee7a45f4f315d7996a969e25fdc7146\", null ],\n    [ \"pCoeffs\", \"structarm__lms__norm__instance__q15.html#ae7bca648c75a2ffa02d87852bb78bc8a\", null ],\n    [ \"postShift\", \"structarm__lms__norm__instance__q15.html#aa0d435fbcf7dedb7179d4467e9b79e9f\", null ],\n    [ \"pState\", \"structarm__lms__norm__instance__q15.html#aa4de490b3bdbd03561b76ee07901c8e3\", null ],\n    [ \"recipTable\", \"structarm__lms__norm__instance__q15.html#a9aabb0e4c79f3db807e7a441fa36f5f8\", null ],\n    [ \"x0\", \"structarm__lms__norm__instance__q15.html#a3fc1d6f97d2c6d5324871de6895cb7e9\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_lms_norm_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_lms_norm_instance_q31 Struct Reference
  
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Instance structure for the Q31 normalized LMS filter.  \n
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\nData Fields
uint16_t numTaps
 
q31_t * pState
 
q31_t * pCoeffs
 
q31_t mu
 
uint8_t postShift
 
q31_t * recipTable
 
q31_t energy
 
q31_t x0
 
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Field Documentation
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q31_t arm_lms_norm_instance_q31::energy
\n
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saves previous frame energy. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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q31_t arm_lms_norm_instance_q31::mu
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step size that controls filter coefficient updates. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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uint16_t arm_lms_norm_instance_q31::numTaps
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number of coefficients in the filter. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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q31_t* arm_lms_norm_instance_q31::pCoeffs
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points to the coefficient array. The array is of length numTaps. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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uint8_t arm_lms_norm_instance_q31::postShift
\n
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bit shift applied to coefficients. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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q31_t* arm_lms_norm_instance_q31::pState
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points to the state variable array. The array is of length numTaps+blockSize-1. 
\n\n
Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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q31_t* arm_lms_norm_instance_q31::recipTable
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points to the reciprocal initial value table. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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q31_t arm_lms_norm_instance_q31::x0
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saves previous input sample. 
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Referenced by arm_lms_norm_init_q31(), and arm_lms_norm_q31().
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  • arm_lms_norm_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__lms__norm__instance__q31.js",
    "content": "var structarm__lms__norm__instance__q31 =\n[\n    [ \"energy\", \"structarm__lms__norm__instance__q31.html#a3c0ae42869afec8555dc8e3a7ef9b386\", null ],\n    [ \"mu\", \"structarm__lms__norm__instance__q31.html#ad3dd2a2406e02fdaa7782ba6c3940a64\", null ],\n    [ \"numTaps\", \"structarm__lms__norm__instance__q31.html#a28e4c085af69c9c3e2e95dacf8004c3e\", null ],\n    [ \"pCoeffs\", \"structarm__lms__norm__instance__q31.html#a57a64c1ff102d033c1bd05043f1d9955\", null ],\n    [ \"postShift\", \"structarm__lms__norm__instance__q31.html#a28d7b9e437817f83397e081967e90f3c\", null ],\n    [ \"pState\", \"structarm__lms__norm__instance__q31.html#a6b25c96cf048b77078d62f4252a01ec4\", null ],\n    [ \"recipTable\", \"structarm__lms__norm__instance__q31.html#a85836d0907077b9ac660f7bbbaa9d694\", null ],\n    [ \"x0\", \"structarm__lms__norm__instance__q31.html#a47c4466d644e0d8ba407995adfa9b917\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_matrix_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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arm_matrix_instance_f32 Struct Reference
  
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Instance structure for the floating-point matrix structure.  \n More...
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uint16_t numRows
 
uint16_t numCols
 
float32_t * pData
 
\n
Description
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Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.
\n
Field Documentation
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uint16_t arm_matrix_instance_f32::numCols
\n
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number of columns of the matrix. 
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Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().
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uint16_t arm_matrix_instance_f32::numRows
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number of rows of the matrix. 
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Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().
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float32_t* arm_matrix_instance_f32::pData
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points to the data of the matrix. 
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Referenced by arm_mat_add_f32(), arm_mat_init_f32(), arm_mat_inverse_f32(), arm_mat_mult_f32(), arm_mat_scale_f32(), arm_mat_sub_f32(), and arm_mat_trans_f32().
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  • arm_matrix_instance_f32
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__f32.js",
    "content": "var structarm__matrix__instance__f32 =\n[\n    [ \"numCols\", \"structarm__matrix__instance__f32.html#acdd1fb73734df68b89565c54f1dd8ae2\", null ],\n    [ \"numRows\", \"structarm__matrix__instance__f32.html#a23f4e34d70a82c9cad7612add5640b7b\", null ],\n    [ \"pData\", \"structarm__matrix__instance__f32.html#af3917c032600a9dfd5ed4a96f074910a\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_matrix_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_matrix_instance_q15 Struct Reference
  
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Instance structure for the Q15 matrix structure.  \n
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uint16_t numRows
 
uint16_t numCols
 
q15_t * pData
 
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Field Documentation
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uint16_t arm_matrix_instance_q15::numCols
\n
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number of columns of the matrix. 
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Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().
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uint16_t arm_matrix_instance_q15::numRows
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number of rows of the matrix. 
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Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().
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q15_t* arm_matrix_instance_q15::pData
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points to the data of the matrix. 
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Referenced by arm_mat_add_q15(), arm_mat_init_q15(), arm_mat_mult_fast_q15(), arm_mat_mult_q15(), arm_mat_scale_q15(), arm_mat_sub_q15(), and arm_mat_trans_q15().
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  • arm_matrix_instance_q15
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q15.js",
    "content": "var structarm__matrix__instance__q15 =\n[\n    [ \"numCols\", \"structarm__matrix__instance__q15.html#acbbce67ba058d8e1c867c71d57288c97\", null ],\n    [ \"numRows\", \"structarm__matrix__instance__q15.html#a9bac6ed54be287c4d4f01a1a28be65f5\", null ],\n    [ \"pData\", \"structarm__matrix__instance__q15.html#a6da33a5553e634787d0f515cf8d724af\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_matrix_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_matrix_instance_q31 Struct Reference
  
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Instance structure for the Q31 matrix structure.  \n
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uint16_t numRows
 
uint16_t numCols
 
q31_t * pData
 
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Field Documentation
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uint16_t arm_matrix_instance_q31::numCols
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number of columns of the matrix. 
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Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().
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uint16_t arm_matrix_instance_q31::numRows
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number of rows of the matrix. 
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Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().
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q31_t* arm_matrix_instance_q31::pData
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points to the data of the matrix. 
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Referenced by arm_mat_add_q31(), arm_mat_init_q31(), arm_mat_mult_fast_q31(), arm_mat_mult_q31(), arm_mat_scale_q31(), arm_mat_sub_q31(), and arm_mat_trans_q31().
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  • arm_matrix_instance_q31
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  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__matrix__instance__q31.js",
    "content": "var structarm__matrix__instance__q31 =\n[\n    [ \"numCols\", \"structarm__matrix__instance__q31.html#abd161da7614eda927157f18b698074b1\", null ],\n    [ \"numRows\", \"structarm__matrix__instance__q31.html#a63bacac158a821c8cfc06088d251598c\", null ],\n    [ \"pData\", \"structarm__matrix__instance__q31.html#a09a64267c0579fef086efc9059741e56\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_pid_instance_f32 Struct Reference
  
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Instance structure for the floating-point PID Control.  \n
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float32_t A0
 
float32_t A1
 
float32_t A2
 
float32_t state [3]
 
float32_t Kp
 
float32_t Ki
 
float32_t Kd
 
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Field Documentation
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float32_t arm_pid_instance_f32::A0
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The derived gain, A0 = Kp + Ki + Kd . 
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Referenced by arm_pid_f32(), and arm_pid_init_f32().
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float32_t arm_pid_instance_f32::A1
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The derived gain, A1 = -Kp - 2Kd. 
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Referenced by arm_pid_f32(), and arm_pid_init_f32().
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float32_t arm_pid_instance_f32::A2
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The derived gain, A2 = Kd . 
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Referenced by arm_pid_f32(), and arm_pid_init_f32().
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float32_t arm_pid_instance_f32::Kd
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The derivative gain. 
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Referenced by arm_pid_init_f32().
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float32_t arm_pid_instance_f32::Ki
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The integral gain. 
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Referenced by arm_pid_init_f32().
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float32_t arm_pid_instance_f32::Kp
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The proportional gain. 
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Referenced by arm_pid_init_f32().
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float32_t arm_pid_instance_f32::state[3]
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The state array of length 3. 
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Referenced by arm_pid_f32(), arm_pid_init_f32(), and arm_pid_reset_f32().
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    \n    
  • arm_pid_instance_f32
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__f32.js",
    "content": "var structarm__pid__instance__f32 =\n[\n    [ \"A0\", \"structarm__pid__instance__f32.html#ad7b0bed64915d0a25a3409fa2dc45556\", null ],\n    [ \"A1\", \"structarm__pid__instance__f32.html#a7def89571c50f7137a213326a396e560\", null ],\n    [ \"A2\", \"structarm__pid__instance__f32.html#a155acf642ba2f521869f19d694cd7fa0\", null ],\n    [ \"Kd\", \"structarm__pid__instance__f32.html#ad5b68fbf84d16188ae4747ff91f6f088\", null ],\n    [ \"Ki\", \"structarm__pid__instance__f32.html#ac0feffde05fe391eeab3bf78e953830a\", null ],\n    [ \"Kp\", \"structarm__pid__instance__f32.html#aa9b9aa9e413c6cec376a9dddc9f01ebe\", null ],\n    [ \"state\", \"structarm__pid__instance__f32.html#afd394e1e52fb1d526aa472c83b8f2464\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
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\n
arm_pid_instance_q15 Struct Reference
  
\n
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\n\n
Instance structure for the Q15 PID Control.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
q15_t A0
 
q31_t A1
 
q15_t state [3]
 
q15_t Kp
 
q15_t Ki
 
q15_t Kd
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
q15_t arm_pid_instance_q15::A0
\n
\n
The derived gain, A0 = Kp + Ki + Kd . 
\n\n
Referenced by arm_pid_init_q15(), and arm_pid_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q15::A1
\n
\n
The derived gain A1 = -Kp - 2Kd | Kd. 
\n\n
Referenced by arm_pid_init_q15(), and arm_pid_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q15_t arm_pid_instance_q15::Kd
\n
\n
The derivative gain. 
\n\n
Referenced by arm_pid_init_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q15_t arm_pid_instance_q15::Ki
\n
\n
The integral gain. 
\n\n
Referenced by arm_pid_init_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q15_t arm_pid_instance_q15::Kp
\n
\n
The proportional gain. 
\n\n
Referenced by arm_pid_init_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q15_t arm_pid_instance_q15::state[3]
\n
\n
The state array of length 3. 
\n\n
Referenced by arm_pid_init_q15(), arm_pid_q15(), and arm_pid_reset_q15().
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • arm_pid_instance_q15
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__q15.js",
    "content": "var structarm__pid__instance__q15 =\n[\n    [ \"A0\", \"structarm__pid__instance__q15.html#ad77f3a2823c7f96de42c92a3fbf3246b\", null ],\n    [ \"A1\", \"structarm__pid__instance__q15.html#a1b8412c517071962a9acfdc6778906ec\", null ],\n    [ \"Kd\", \"structarm__pid__instance__q15.html#af5d4b53091f19eff7536636b7cc43111\", null ],\n    [ \"Ki\", \"structarm__pid__instance__q15.html#a0dcc19d5c8f7bc401acea9e8318cd777\", null ],\n    [ \"Kp\", \"structarm__pid__instance__q15.html#ad228aae24a1b6d855c93a8b9bbc1c4f1\", null ],\n    [ \"state\", \"structarm__pid__instance__q15.html#a4a3f0a878b5b6b055e3478a2f244cd30\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_pid_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n  
\n
arm_pid_instance_q31 Struct Reference
  
\n
\n
\n\n
Instance structure for the Q31 PID Control.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
q31_t A0
 
q31_t A1
 
q31_t A2
 
q31_t state [3]
 
q31_t Kp
 
q31_t Ki
 
q31_t Kd
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::A0
\n
\n
The derived gain, A0 = Kp + Ki + Kd . 
\n\n
Referenced by arm_pid_init_q31(), and arm_pid_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::A1
\n
\n
The derived gain, A1 = -Kp - 2Kd. 
\n\n
Referenced by arm_pid_init_q31(), and arm_pid_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::A2
\n
\n
The derived gain, A2 = Kd . 
\n\n
Referenced by arm_pid_init_q31(), and arm_pid_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::Kd
\n
\n
The derivative gain. 
\n\n
Referenced by arm_pid_init_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::Ki
\n
\n
The integral gain. 
\n\n
Referenced by arm_pid_init_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::Kp
\n
\n
The proportional gain. 
\n\n
Referenced by arm_pid_init_q31().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
q31_t arm_pid_instance_q31::state[3]
\n
\n
The state array of length 3. 
\n\n
Referenced by arm_pid_init_q31(), arm_pid_q31(), and arm_pid_reset_q31().
\n\n
\n
\n
\n
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\n  
    \n    
  • arm_pid_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__pid__instance__q31.js",
    "content": "var structarm__pid__instance__q31 =\n[\n    [ \"A0\", \"structarm__pid__instance__q31.html#aa5332635ce9c7078cdb4c1ecf442eadd\", null ],\n    [ \"A1\", \"structarm__pid__instance__q31.html#a2f7492bd6fb92fae5e2de7fbbec39b0e\", null ],\n    [ \"A2\", \"structarm__pid__instance__q31.html#a3e34537c53af4f9ad7bfffa4dff27c82\", null ],\n    [ \"Kd\", \"structarm__pid__instance__q31.html#aab4ff371d14441df501f1169f71cbd17\", null ],\n    [ \"Ki\", \"structarm__pid__instance__q31.html#aa861d69fd398f29aa0b4b455a823ed72\", null ],\n    [ \"Kp\", \"structarm__pid__instance__q31.html#ac2410bf7f856d58dc1d773d4983cac8e\", null ],\n    [ \"state\", \"structarm__pid__instance__q31.html#a228e4a64da6014844a0a671a1fa391d4\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__fast__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_fast_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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\n
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arm_rfft_fast_instance_f32 Struct Reference
  
\n
\n
\n\n
Instance structure for the floating-point RFFT/RIFFT function.  \n
\n\n\n\n\n\n\n\n\n
\nData Fields
arm_cfft_instance_f32 Sint
 
uint16_t fftLenRFFT
 
float32_t * pTwiddleRFFT
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_rfft_fast_instance_f32::fftLenRFFT
\n
\n
length of the real sequence 
\n\n
Referenced by arm_rfft_fast_f32(), and arm_rfft_fast_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t* arm_rfft_fast_instance_f32::pTwiddleRFFT
\n
\n
Twiddle factors real stage 
\n\n
Referenced by merge_rfft_f32(), and stage_rfft_f32().
\n\n
\n
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\n
\n      \n        \n          \n        \n      
arm_cfft_instance_f32 arm_rfft_fast_instance_f32::Sint
\n
\n
Internal CFFT structure. 
\n\n
Referenced by arm_rfft_fast_f32(), arm_rfft_fast_init_f32(), merge_rfft_f32(), and stage_rfft_f32().
\n\n
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\n  \n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__fast__instance__f32.js",
    "content": "var structarm__rfft__fast__instance__f32 =\n[\n    [ \"fftLenRFFT\", \"structarm__rfft__fast__instance__f32.html#aef06ab665041ec36f5b25d464f0cab14\", null ],\n    [ \"pTwiddleRFFT\", \"structarm__rfft__fast__instance__f32.html#a9f30b04f163fabc1b24421d3c323d5fc\", null ],\n    [ \"Sint\", \"structarm__rfft__fast__instance__f32.html#a37419ababdfb3151b1891ae6bcd21012\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__f32.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_instance_f32 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_rfft_instance_f32 Struct Reference
  
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Instance structure for the floating-point RFFT/RIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t fftLenReal
 
uint16_t fftLenBy2
 
uint8_t ifftFlagR
 
uint8_t bitReverseFlagR
 
uint32_t twidCoefRModifier
 
float32_t * pTwiddleAReal
 
float32_t * pTwiddleBReal
 
arm_cfft_radix4_instance_f32 * pCfft
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_rfft_instance_f32::bitReverseFlagR
\n
\n
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint16_t arm_rfft_instance_f32::fftLenBy2
\n
\n
length of the complex FFT. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t arm_rfft_instance_f32::fftLenReal
\n
\n
length of the real FFT. 
\n\n
Referenced by arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_rfft_instance_f32::ifftFlagR
\n
\n
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
arm_cfft_radix4_instance_f32* arm_rfft_instance_f32::pCfft
\n
\n
points to the complex FFT instance. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
float32_t* arm_rfft_instance_f32::pTwiddleAReal
\n
\n
points to the real twiddle factor table. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
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\n
\n      \n        \n          \n        \n      
float32_t* arm_rfft_instance_f32::pTwiddleBReal
\n
\n
points to the imag twiddle factor table. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t arm_rfft_instance_f32::twidCoefRModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_rfft_f32(), and arm_rfft_init_f32().
\n\n
\n
\n
\n
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\n  
    \n    
  • arm_rfft_instance_f32
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__f32.js",
    "content": "var structarm__rfft__instance__f32 =\n[\n    [ \"bitReverseFlagR\", \"structarm__rfft__instance__f32.html#ac342f3248157cbbd2f04a3c8ec9fc9eb\", null ],\n    [ \"fftLenBy2\", \"structarm__rfft__instance__f32.html#a075076e07ebb8521d8e3b49a31db6c57\", null ],\n    [ \"fftLenReal\", \"structarm__rfft__instance__f32.html#a4219d4669699e4efdcb150ed7a0d9a57\", null ],\n    [ \"ifftFlagR\", \"structarm__rfft__instance__f32.html#a5ee6d10a934ab4b666e0bb286c3d633f\", null ],\n    [ \"pCfft\", \"structarm__rfft__instance__f32.html#a9f47ba9f50c81e4445ae3827b981bc05\", null ],\n    [ \"pTwiddleAReal\", \"structarm__rfft__instance__f32.html#a534cc7e6e9b3e3dd022fad611c762142\", null ],\n    [ \"pTwiddleBReal\", \"structarm__rfft__instance__f32.html#a23543ecfd027fea2477fe1eea23c3c4d\", null ],\n    [ \"twidCoefRModifier\", \"structarm__rfft__instance__f32.html#aede85350fb5ae6baa1b3e8bfa15b18d6\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q15.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_instance_q15 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-DSP\n    Verison 1.4.1\n   
\n   
CMSIS DSP Software Library
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arm_rfft_instance_q15 Struct Reference
  
\n
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Instance structure for the Q15 RFFT/RIFFT function.  \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t fftLenReal
 
uint32_t fftLenBy2
 
uint8_t ifftFlagR
 
uint8_t bitReverseFlagR
 
uint32_t twidCoefRModifier
 
q15_t * pTwiddleAReal
 
q15_t * pTwiddleBReal
 
arm_cfft_radix4_instance_q15 * pCfft
 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint8_t arm_rfft_instance_q15::bitReverseFlagR
\n
\n
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t arm_rfft_instance_q15::fftLenBy2
\n
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length of the complex FFT. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
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\n
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\n
\n      \n        \n          \n        \n      
uint32_t arm_rfft_instance_q15::fftLenReal
\n
\n
length of the real FFT. 
\n\n
Referenced by arm_rfft_init_q15().
\n\n
\n
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\n
\n      \n        \n          \n        \n      
uint8_t arm_rfft_instance_q15::ifftFlagR
\n
\n
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
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\n      \n        \n          \n        \n      
arm_cfft_radix4_instance_q15* arm_rfft_instance_q15::pCfft
\n
\n
points to the complex FFT instance. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
\n
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\n
\n      \n        \n          \n        \n      
q15_t* arm_rfft_instance_q15::pTwiddleAReal
\n
\n
points to the real twiddle factor table. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
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\n
\n      \n        \n          \n        \n      
q15_t* arm_rfft_instance_q15::pTwiddleBReal
\n
\n
points to the imag twiddle factor table. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t arm_rfft_instance_q15::twidCoefRModifier
\n
\n
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
\n\n
Referenced by arm_rfft_init_q15(), and arm_rfft_q15().
\n\n
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    \n    
  • arm_rfft_instance_q15
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q15.js",
    "content": "var structarm__rfft__instance__q15 =\n[\n    [ \"bitReverseFlagR\", \"structarm__rfft__instance__q15.html#a4c65cd40e0098ec2f5c0dc31488b9bc6\", null ],\n    [ \"fftLenBy2\", \"structarm__rfft__instance__q15.html#afef95bc722f5929d5e63ecba14fa3ca1\", null ],\n    [ \"fftLenReal\", \"structarm__rfft__instance__q15.html#aac5cf9e825917cbb14f439e56bb86ab3\", null ],\n    [ \"ifftFlagR\", \"structarm__rfft__instance__q15.html#a8051ffe268c147e431e1bea7bb4c4258\", null ],\n    [ \"pCfft\", \"structarm__rfft__instance__q15.html#acd8f28f777f3417280212ce799ebef46\", null ],\n    [ \"pTwiddleAReal\", \"structarm__rfft__instance__q15.html#affbf2de522ac029432d98e8373c0ec53\", null ],\n    [ \"pTwiddleBReal\", \"structarm__rfft__instance__q15.html#a937d815022adc557b435ba8c6cd58b0d\", null ],\n    [ \"twidCoefRModifier\", \"structarm__rfft__instance__q15.html#afd444d05858c5f419980e94e8240d5c3\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q31.html",
    "content": "\n\n\n\n\nCMSIS-DSP: arm_rfft_instance_q31 Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-DSP\n    Verison 1.4.1\n   
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CMSIS DSP Software Library
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arm_rfft_instance_q31 Struct Reference
  
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Instance structure for the Q31 RFFT/RIFFT function.  \n
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\nData Fields
uint32_t fftLenReal
 
uint32_t fftLenBy2
 
uint8_t ifftFlagR
 
uint8_t bitReverseFlagR
 
uint32_t twidCoefRModifier
 
q31_t * pTwiddleAReal
 
q31_t * pTwiddleBReal
 
arm_cfft_radix4_instance_q31 * pCfft
 
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Field Documentation
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uint8_t arm_rfft_instance_q31::bitReverseFlagR
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flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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uint32_t arm_rfft_instance_q31::fftLenBy2
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length of the complex FFT. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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uint32_t arm_rfft_instance_q31::fftLenReal
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length of the real FFT. 
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Referenced by arm_rfft_init_q31().
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uint8_t arm_rfft_instance_q31::ifftFlagR
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flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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arm_cfft_radix4_instance_q31* arm_rfft_instance_q31::pCfft
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points to the complex FFT instance. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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q31_t* arm_rfft_instance_q31::pTwiddleAReal
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points to the real twiddle factor table. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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q31_t* arm_rfft_instance_q31::pTwiddleBReal
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points to the imag twiddle factor table. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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uint32_t arm_rfft_instance_q31::twidCoefRModifier
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twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
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Referenced by arm_rfft_init_q31(), and arm_rfft_q31().
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    \n    
  • arm_rfft_instance_q31
    • \n    
  • Generated on Mon Mar 18 2013 13:37:58 for CMSIS-DSP by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/structarm__rfft__instance__q31.js",
    "content": "var structarm__rfft__instance__q31 =\n[\n    [ \"bitReverseFlagR\", \"structarm__rfft__instance__q31.html#a3cb90cdc928a88b0203917dcb3dc1b71\", null ],\n    [ \"fftLenBy2\", \"structarm__rfft__instance__q31.html#a7d1a948bb8a23bf5419bb6f9ef43dd76\", null ],\n    [ \"fftLenReal\", \"structarm__rfft__instance__q31.html#af777b0cadd5abaf064323692c2e6693b\", null ],\n    [ \"ifftFlagR\", \"structarm__rfft__instance__q31.html#af5c2615e6cde15524df38fa57ea32d94\", null ],\n    [ \"pCfft\", \"structarm__rfft__instance__q31.html#ac6bf12707e1985818d161616adf27977\", null ],\n    [ \"pTwiddleAReal\", \"structarm__rfft__instance__q31.html#a2a0c944e66bab92fcbe19d1c29153250\", null ],\n    [ \"pTwiddleBReal\", \"structarm__rfft__instance__q31.html#ae5070be4c2e0327e618f5e1f4c5b9d80\", null ],\n    [ \"twidCoefRModifier\", \"structarm__rfft__instance__q31.html#a6fc90252b579f7c29e01bd279334fc43\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/DSP/html/system___a_r_m_c_m0_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: system_ARMCM0.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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system_ARMCM0.c File Reference
  
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CMSIS Device System Source File for ARMCM0 Device Series.  \nMore...
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#define __HSI
 
#define __XTAL
 
#define __SYSTEM_CLOCK
 
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void SystemCoreClockUpdate (void)
 
void SystemInit (void)
 Setup the microcontroller system. Initialize the System.  More...
 
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uint32_t SystemCoreClock
 
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Description
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Version
V1.08 
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Date
23. November 2012
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Note
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Macro Definition Documentation
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#define __HSI
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#define __SYSTEM_CLOCK
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Referenced by SystemCoreClockUpdate(), and SystemInit().
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#define __XTAL
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Function Documentation
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void SystemCoreClockUpdate (void )
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References __SYSTEM_CLOCK, and SystemCoreClock.
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void SystemInit (void )
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Initialize the system
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Parameters
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none
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Returns
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References __SYSTEM_CLOCK, and SystemCoreClock.
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Variable Documentation
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uint32_t SystemCoreClock
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System Clock Frequency (Core Clock) 
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Referenced by SystemCoreClockUpdate(), and SystemInit().
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    "path": "Libraries/CMSIS/Documentation/DSP/html/system___a_r_m_c_m3_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: system_ARMCM3.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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system_ARMCM3.c File Reference
  
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CMSIS Device System Source File for ARMCM3 Device Series.  \nMore...
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#define __HSI
 
#define __XTAL
 
#define __SYSTEM_CLOCK
 
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\nFunctions
void SystemCoreClockUpdate (void)
 
void SystemInit (void)
 Setup the microcontroller system. Initialize the System.  More...
 
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uint32_t SystemCoreClock
 
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Description
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Version
V1.08 
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Date
23. November 2012
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Note
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Macro Definition Documentation
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#define __HSI
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#define __SYSTEM_CLOCK
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Referenced by SystemCoreClockUpdate(), and SystemInit().
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#define __XTAL
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Function Documentation
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void SystemCoreClockUpdate (void )
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References __SYSTEM_CLOCK, and SystemCoreClock.
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void SystemInit (void )
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Initialize the system
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Parameters
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none
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Returns
none 
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References __SYSTEM_CLOCK, and SystemCoreClock.
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Variable Documentation
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uint32_t SystemCoreClock
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System Clock Frequency (Core Clock) 
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  },
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    "path": "Libraries/CMSIS/Documentation/DSP/html/system___a_r_m_c_m4_8c.html",
    "content": "\n\n\n\n\nCMSIS-DSP: system_ARMCM4.c File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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system_ARMCM4.c File Reference
  
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CMSIS Device System Source File for ARMCM4 Device Series.  \nMore...
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#define __HSI
 
#define __XTAL
 
#define __SYSTEM_CLOCK
 
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void SystemCoreClockUpdate (void)
 
void SystemInit (void)
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uint32_t SystemCoreClock
 
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Description
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Version
V1.08 
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Date
23. November 2012
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Note
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Macro Definition Documentation
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#define __HSI
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#define __SYSTEM_CLOCK
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Referenced by SystemCoreClockUpdate(), and SystemInit().
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#define __XTAL
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Function Documentation
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void SystemCoreClockUpdate (void )
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References __SYSTEM_CLOCK, and SystemCoreClock.
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void SystemInit (void )
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Initialize the system
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Parameters
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none
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Returns
none 
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References __SYSTEM_CLOCK, and SystemCoreClock.
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Variable Documentation
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uint32_t SystemCoreClock
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System Clock Frequency (Core Clock) 
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{\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: 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line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #354E81;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/General/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l\n\n\n\n\nCMSIS: Introduction\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS\n    Version 3.20\n   
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Cortex Microcontroller Software Interface Standard
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Introduction 
  
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The Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series. The CMSIS enables consistent and simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.
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The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.
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The CMSIS components are:
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  • CMSIS-CORE: API for the Cortex-M processor core and peripherals. It provides at standardized interface for Cortex-M0, Cortex-M3, Cortex-M4, SC000, and SC300. Included are also SIMD intrinsic functions for Cortex-M4 SIMD instructions.
    • \n
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  • CMSIS-DSP: DSP Library Collection with over 60 Functions for various data types: fix-point (fractional q7, q15, q31) and single precision floating-point (32-bit). The library is available for Cortex-M0, Cortex-M3, and Cortex-M4. The Cortex-M4 implementation is optimized for the SIMD instruction set.
    • \n
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  • CMSIS-RTOS API: Common API for Real-Time operating systems. It provides a standardized programming interface that is portable to many RTOS and enables therefore software templates, middleware, libraries, and other components that can work acrosss supported the RTOS systems.
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  • CMSIS-SVD: System View Description for Peripherals. Describes the peripherals of a device in an XML file and can be used to create peripheral awareness in debuggers or header files with peripheral register and interrupt definitions.
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  • CMSIS-DAP: Debug Access Port. Standardized firmware for a Debug Unit that connects to the CoreSight Debug Access Port. CMSIS-DAP is distributed as separate package and well suited for integration on evaluation boards.
    • \n
\n
\n\"CMSIS_V3_small.png\"/\n
\nCMSIS Structure
\n 
\nMotivation
\n
CMSIS has been created to help the industry in standardization. It is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard. In detail the benefits of the CMSIS are:
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    \n
  • Consistent software interfaces improve the software portability and re-usability. Generic software libraries can interface with device libraries from various silicon vendors.
    • \n
  • Reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through an easy to use and standardized software interface.
    • \n
  • Provides a compiler independent layer that allows using different compilers. CMSIS is supported by all mainstream compilers (ARMCC, IAR, and GNU).
    • \n
  • Enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output and RTOS kernel awareness.
    • \n
\n
\nCoding Rules
\n
The CMSIS uses the following essential coding rules and conventions:
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  • Compliant with ANSI C and C++.
    • \n
  • Uses ANSI C standard data types defined in <stdint.h>.
    • \n
  • Variables and parameters have a complete data type.
    • \n
  • Expressions for #define constants are enclosed in parenthesis.
    • \n
  • Conforms to MISRA 2004. MIRSA rule violations are documented.
    • \n
\n
In addition, the CMSIS recommends the following conventions for identifiers:
\n
    \n
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • \n
  • CamelCase names to identify function names and interrupt functions.
    • \n
  • Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).
    • \n
\n
The CMSIS is documented within the source files with: 
\n
    \n
  • Comments that use the C or C++ style. 
    • \n
  • Doxygen compliant function comments that provide:
      \n
    • brief function overview.
      • \n
    • detailed description of the function.
      • \n
    • detailed parameter explanation.
      • \n
    • detailed information about return values.
      • \n
    \n
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Doxygen comment example: 
\n
/** \n * @brief  Enable Interrupt in NVIC Interrupt Controller\n * @param  IRQn  interrupt number that specifies the interrupt\n * @return none.\n * Enable the specified interrupt in the NVIC Interrupt Controller.\n * Other settings of the interrupt such as priority are not affected.\n */\n
\nLicence
\n
The CMSIS is provided free of charge by ARM and can be used for all Cortex-M based devices.
\n
The software portions that are deployed in the application program are under a BSD license which allows usage of CMSIS in any commercial or open source projects.
\n
View the LICENCE AGREEMENT for CMSIS in detail. 
\n
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\n  
    \n    
  • Generated on Mon Mar 18 2013 13:37:59 for CMSIS by ARM Ltd. All rights reserved.\n\t\n\t
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d=c.toLowerCase();f.fn[\"inner\"+c]=function(){var a=this[0];return a?a.style?parseFloat(f.css(a,d,\"padding\")):this[d]():null},f.fn[\"outer\"+c]=function(a){var b=this[0];return b?b.style?parseFloat(f.css(b,d,a?\"margin\":\"border\")):this[d]():null},f.fn[d]=function(a){var e=this[0];if(!e)return a==null?null:this;if(f.isFunction(a))return this.each(function(b){var c=f(this);c[d](a.call(this,b,c[d]()))});if(f.isWindow(e)){var g=e.document.documentElement[\"client\"+c],h=e.document.body;return e.document.compatMode===\"CSS1Compat\"&&g||h&&h[\"client\"+c]||g}if(e.nodeType===9)return Math.max(e.documentElement[\"client\"+c],e.body[\"scroll\"+c],e.documentElement[\"scroll\"+c],e.body[\"offset\"+c],e.documentElement[\"offset\"+c]);if(a===b){var i=f.css(e,d),j=parseFloat(i);return f.isNumeric(j)?j:i}return this.css(d,typeof a==\"string\"?a:a+\"px\")}}),a.jQuery=a.$=f,typeof define==\"function\"&&define.amd&&define.amd.jQuery&&define(\"jquery\",[],function(){return f})})(window);\n/*!\n * jQuery UI 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI\n */\n(function(a,b){function d(b){return!a(b).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}function c(b,c){var e=b.nodeName.toLowerCase();if(\"area\"===e){var f=b.parentNode,g=f.name,h;if(!b.href||!g||f.nodeName.toLowerCase()!==\"map\")return!1;h=a(\"img[usemap=#\"+g+\"]\")[0];return!!h&&d(h)}return(/input|select|textarea|button|object/.test(e)?!b.disabled:\"a\"==e?b.href||c:c)&&d(b)}a.ui=a.ui||{};a.ui.version||(a.extend(a.ui,{version:\"1.8.18\",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}}),a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(b,c){return typeof b==\"number\"?this.each(function(){var d=this;setTimeout(function(){a(d).focus(),c&&c.call(d)},b)}):this._focus.apply(this,arguments)},scrollParent:function(){var b;a.browser.msie&&/(static|relative)/.test(this.css(\"position\"))||/absolute/.test(this.css(\"position\"))?b=this.parents().filter(function(){return/(relative|absolute|fixed)/.test(a.curCSS(this,\"position\",1))&&/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0):b=this.parents().filter(function(){return/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0);return/fixed/.test(this.css(\"position\"))||!b.length?a(document):b},zIndex:function(c){if(c!==b)return this.css(\"zIndex\",c);if(this.length){var d=a(this[0]),e,f;while(d.length&&d[0]!==document){e=d.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){f=parseInt(d.css(\"zIndex\"),10);if(!isNaN(f)&&f!==0)return f}d=d.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(a){a.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}}),a.each([\"Width\",\"Height\"],function(c,d){function h(b,c,d,f){a.each(e,function(){c-=parseFloat(a.curCSS(b,\"padding\"+this,!0))||0,d&&(c-=parseFloat(a.curCSS(b,\"border\"+this+\"Width\",!0))||0),f&&(c-=parseFloat(a.curCSS(b,\"margin\"+this,!0))||0)});return c}var e=d===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],f=d.toLowerCase(),g={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};a.fn[\"inner\"+d]=function(c){if(c===b)return g[\"inner\"+d].call(this);return this.each(function(){a(this).css(f,h(this,c)+\"px\")})},a.fn[\"outer\"+d]=function(b,c){if(typeof b!=\"number\")return g[\"outer\"+d].call(this,b);return this.each(function(){a(this).css(f,h(this,b,!0,c)+\"px\")})}}),a.extend(a.expr[\":\"],{data:function(b,c,d){return!!a.data(b,d[3])},focusable:function(b){return c(b,!isNaN(a.attr(b,\"tabindex\")))},tabbable:function(b){var d=a.attr(b,\"tabindex\"),e=isNaN(d);return(e||d>=0)&&c(b,!e)}}),a(function(){var b=document.body,c=b.appendChild(c=document.createElement(\"div\"));c.offsetHeight,a.extend(c.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0}),a.support.minHeight=c.offsetHeight===100,a.support.selectstart=\"onselectstart\"in c,b.removeChild(c).style.display=\"none\"}),a.extend(a.ui,{plugin:{add:function(b,c,d){var e=a.ui[b].prototype;for(var f in d)e.plugins[f]=e.plugins[f]||[],e.plugins[f].push([c,d[f]])},call:function(a,b,c){var d=a.plugins[b];if(!!d&&!!a.element[0].parentNode)for(var e=0;e0)return!0;b[d]=1,e=b[d]>0,b[d]=0;return e},isOverAxis:function(a,b,c){return a>b&&a=9)&&!b.button)return this._mouseUp(b);if(this._mouseStarted){this._mouseDrag(b);return b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+\".preventClickEvent\",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery);\n/*\n * jQuery UI Resizable 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Resizables\n *\n * Depends:\n *\tjquery.ui.core.js\n *\tjquery.ui.mouse.js\n *\tjquery.ui.widget.js\n */\n(function(a,b){a.widget(\"ui.resizable\",a.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:!1,animate:!1,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:\"e,s,se\",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass(\"ui-resizable\"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||\"ui-resizable-helper\":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")})),this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css(\"resize\"),this.originalElement.css(\"resize\",\"none\"),this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"})),this.originalElement.css({margin:this.originalElement.css(\"margin\")}),this._proportionallyResize()),this.handles=c.handles||(a(\".ui-resizable-handle\",this.element).length?{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"}:\"e,s,se\");if(this.handles.constructor==String){this.handles==\"all\"&&(this.handles=\"n,e,s,w,se,sw,ne,nw\");var d=this.handles.split(\",\");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),\"se\"==f&&h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\"),this.handles[f]=\".ui-resizable-\"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=[\"padding\",/ne|nw|n/.test(c)?\"Top\":/se|sw|s/.test(c)?\"Bottom\":/^e$/.test(c)?\"Right\":\"Left\"].join(\"\");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(\".ui-resizable-handle\",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:\"se\"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass(\"ui-resizable-autohide\").hover(function(){c.disabled||(a(this).removeClass(\"ui-resizable-autohide\"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass(\"ui-resizable-autohide\"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css(\"position\"),width:c.outerWidth(),height:c.outerHeight(),top:c.css(\"top\"),left:c.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(\".ui-draggable\")||/absolute/.test(f.css(\"position\")))&&f.css({position:\"absolute\",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css(\"left\")),h=c(this.helper.css(\"top\"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio==\"number\"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(\".ui-resizable-\"+this.axis).css(\"cursor\");a(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i),f.addClass(\"ui-resizable-resizing\"),this._propagate(\"start\",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate(\"resize\",b),c.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger(\"resize\",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],\"left\")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a(\"body\").css(\"cursor\",\"auto\"),this.element.removeClass(\"ui-resizable-resizing\"),this._propagate(\"stop\",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:\"absolute\",left:this.elementOffset.left-e+\"px\",top:this.elementOffset.top-e+\"px\",zIndex:++c.zIndex}),this.helper.appendTo(\"body\").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!=\"resize\"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:\"1.8.18\"}),a.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data(\"resizable-alsoresize\",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css(\"left\"),10),top:parseInt(b.css(\"top\"),10)})})};typeof e.alsoResize==\"object\"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data(\"resizable-alsoresize\"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?[\"width\",\"height\"]:[\"width\",\"height\",\"top\",\"left\"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof 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c={width:parseInt(d.element.css(\"width\"),10),height:parseInt(d.element.css(\"height\"),10),top:parseInt(d.element.css(\"top\"),10),left:parseInt(d.element.css(\"left\"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate(\"resize\",b)}})}}),a.ui.plugin.add(\"resizable\",\"containment\",{start:function(b,d){var e=a(this).data(\"resizable\"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var 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\n  
\n
Function Overview 
  
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\n
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The following list provides a brief overview of all CMSIS-RTOS functions. Functions marked with $ are optional. A CMSIS RTOS implementation may not provided functions, but this is clearly indicated with osFeatureXXXX defines.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/_using_o_s.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Using a CMSIS RTOS Implementation\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n
\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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Using a CMSIS RTOS Implementation 
  
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A CMSIS RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based application the RTOS library (and typically a configuration file) needs to be added. The available functionality of the RTOS library is defined in the file cmsis_os.h that is specific for each RTOS implementation.
\n
\n\"CMSIS_RTOS_Files.png\"/\n
\nCMSIS-RTOS File Structure
\n
 Depending on the CMSIS-RTOS implementation, execution may start with the main function as the first thread. This has the benefit that an application programmer may use other middleware libraries that create threads internally, but the remaining part of the user application just uses the main thread. Therefore, the usage of the RTOS can be invisible to the application programmer, but libraries can use CMSIS-RTOS features.
\n
Once the files are added to a project, the user can start using the CMSIS-RTOS functions. A code example is provided below:
\n
Example 
\n
#include "cmsis_os.h"                            // CMSIS RTOS header file
\n
\n
void job1 (void const *argument)  {              // thread function 'job1'
\n
  while (1)  {
\n
      :                                          // execute some code
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    osDelay (10);                                // delay execution for 10 milliseconds
\n
  }
\n
}
\n
// define job1 as thread function
\n
osThreadDef(job1, osPriorityAboveNormal, 1, 0);  // define job1 as thread function
\n
\n
\n
void job2 (void const *argument)  {              // thread function 'job2'
\n
  osThreadCreate(osThread(job1),NULL);           // create job1 thread
\n
  while (1)   {
\n
    :                                            // execute some code
\n
  }
\n
}
\n
\n
osThreadDef(job2, osPriorityNormal, 1, 0);       // define job2 as thread function
\n
\n
void job3 (void const *argument)  {              // thread function 'job3'
\n
  while (1)   {
\n
      :                                          // execute some code
\n
        osDelay (20);                                // delay execution for 20 milliseconds
\n
  }
\n
}
\n
\n
osThreadDef(job3, osPriorityNormal, 1, 0);       // define job3 as thread function
\n
\n
int main (void) {                                // program execution starts here
\n
  osKernelInitialize ();                         // initialize RTOS kernel
\n
    :                                            // setup and initialize peripherals
\n
  osThreadCreate (osThread(job2));
\n
  osThreadCreate (osThread(job3));
\n
  osKernelStart ();                              // start kernel with job2 execution
\n
}
\n
 
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  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/annotated.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Data Structures\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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Data Structures
  
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Here are the data structures with brief descriptions:
\n\n\n\n\n\n\n\n\n\n\n
\"o\"\"C\"os_mailQ
\"o\"\"C\"osEventEvent structure contains detailed information about an event
\"o\"\"C\"osMailQDef_tDefinition structure for mail queue
\"o\"\"C\"osMessageQDef_tDefinition structure for message queue
\"o\"\"C\"osMutexDef_tMutex Definition structure contains setup information for a mutex
\"o\"\"C\"osPoolDef_tDefinition structure for memory block allocation
\"o\"\"C\"osSemaphoreDef_tSemaphore Definition structure contains setup information for a semaphore
\"o\"\"C\"osThreadDef_tThread Definition structure contains startup information of a thread
\"\\\"\"C\"osTimerDef_tTimer Definition structure contains timer parameters
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  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/annotated.js",
    "content": "var annotated =\n[\n    [ \"os_mailQ\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#structos__mail_q\", null ],\n    [ \"osEvent\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#structos_event\", \"group___c_m_s_i_s___r_t_o_s___definitions\" ],\n    [ \"osMailQDef_t\", \"structos_mail_q_def__t.html\", \"structos_mail_q_def__t\" ],\n    [ \"osMessageQDef_t\", \"structos_message_q_def__t.html\", \"structos_message_q_def__t\" ],\n    [ \"osMutexDef_t\", \"structos_mutex_def__t.html\", \"structos_mutex_def__t\" ],\n    [ \"osPoolDef_t\", \"structos_pool_def__t.html\", \"structos_pool_def__t\" ],\n    [ \"osSemaphoreDef_t\", \"structos_semaphore_def__t.html\", \"structos_semaphore_def__t\" ],\n    [ \"osThreadDef_t\", \"structos_thread_def__t.html\", \"structos_thread_def__t\" ],\n    [ \"osTimerDef_t\", \"structos_timer_def__t.html\", \"structos_timer_def__t\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/classes.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Data Structure Index\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #2D4068;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n\theight: 28px;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\n\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: 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line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #354E81;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8h.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: cmsis_os.h File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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\nData Structures |\nMacros |\nTypedefs |\nEnumerations |\nFunctions  
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cmsis_os.h File Reference
  
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\nData Structures
struct  osThreadDef_t
 Thread Definition structure contains startup information of a thread.  More...
 
struct  osTimerDef_t
 Timer Definition structure contains timer parameters.  More...
 
struct  osMutexDef_t
 Mutex Definition structure contains setup information for a mutex.  More...
 
struct  osSemaphoreDef_t
 Semaphore Definition structure contains setup information for a semaphore.  More...
 
struct  osPoolDef_t
 Definition structure for memory block allocation.  More...
 
struct  osMessageQDef_t
 Definition structure for message queue.  More...
 
struct  osMailQDef_t
 Definition structure for mail queue.  More...
 
struct  osEvent
 Event structure contains detailed information about an event.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nMacros
#define osCMSIS   0x10002
 API version (main [31:16] .sub [15:0])  More...
 
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0])  More...
 
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string.  More...
 
#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available  More...
 
#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available.  More...
 
#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available.  More...
 
#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available.  More...
 
#define osFeature_Signals   8
 maximum number of Signal Flags available per thread  More...
 
#define osFeature_Semaphore   30
 maximum count for osSemaphoreCreate function  More...
 
#define osFeature_Wait   1
 osWait function: 1=available, 0=not available  More...
 
#define osFeature_SysTick   1
 osKernelSysTick functions: 1=available, 0=not available  More...
 
#define osWaitForever   0xFFFFFFFF
 Timeout value.  More...
 
#define osKernelSysTickFrequency   100000000
 The RTOS kernel system timer frequency in Hz.  More...
 
#define osKernelSysTickMicroSec(microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
 Convert a microseconds value to a RTOS kernel system timer value.  More...
 
#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements.  More...
 
#define osThread(name)   &os_thread_def_##name
 Access a Thread definition.  More...
 
#define osTimerDef(name, function)
 Define a Timer object.  More...
 
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition.  More...
 
#define osMutexDef(name)   const osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex.  More...
 
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex definition.  More...
 
#define osSemaphoreDef(name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object.  More...
 
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition.  More...
 
#define osPoolDef(name, no, type)
 Define a Memory Pool.  More...
 
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition.  More...
 
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition.  More...
 
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition.  More...
 
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition.  More...
 
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nTypedefs
typedef void(* os_pthread )(void const *argument)
 Entry point of a thread.  More...
 
typedef void(* os_ptimer )(void const *argument)
 Entry point of a timer call back function.  More...
 
typedef struct os_thread_cb * osThreadId
 Thread ID identifies the thread (pointer to a thread control block).  More...
 
typedef struct os_timer_cb * osTimerId
 Timer ID identifies the timer (pointer to a timer control block).  More...
 
typedef struct os_mutex_cb * osMutexId
 Mutex ID identifies the mutex (pointer to a mutex control block).  More...
 
typedef struct os_semaphore_cb * osSemaphoreId
 Semaphore ID identifies the semaphore (pointer to a semaphore control block).  More...
 
typedef struct os_pool_cb * osPoolId
 Pool ID identifies the memory pool (pointer to a memory pool control block).  More...
 
typedef struct os_messageQ_cb * osMessageQId
 Message ID identifies the message queue (pointer to a message queue control block).  More...
 
typedef struct os_mailQ_cb * osMailQId
 Mail ID identifies the mail queue (pointer to a mail queue control block).  More...
 
\n\n\n\n\n\n\n\n\n\n\n
\nEnumerations
enum  osPriority { 
\n  osPriorityIdle = -3, \n
\n  osPriorityLow = -2, \n
\n  osPriorityBelowNormal = -1, \n
\n  osPriorityNormal = 0, \n
\n  osPriorityAboveNormal = +1, \n
\n  osPriorityHigh = +2, \n
\n  osPriorityRealtime = +3, \n
\n  osPriorityError = 0x84\n
\n }
 Priority used for thread control.  More...
 
enum  osStatus { 
\n  osOK = 0, \n
\n  osEventSignal = 0x08, \n
\n  osEventMessage = 0x10, \n
\n  osEventMail = 0x20, \n
\n  osEventTimeout = 0x40, \n
\n  osErrorParameter = 0x80, \n
\n  osErrorResource = 0x81, \n
\n  osErrorTimeoutResource = 0xC1, \n
\n  osErrorISR = 0x82, \n
\n  osErrorISRRecursive = 0x83, \n
\n  osErrorPriority = 0x84, \n
\n  osErrorNoMemory = 0x85, \n
\n  osErrorValue = 0x86, \n
\n  osErrorOS = 0xFF, \n
\n  os_status_reserved = 0x7FFFFFFF\n
\n }
 Status code values returned by CMSIS-RTOS functions.  More...
 
enum  os_timer_type { 
\n  osTimerOnce = 0, \n
\n  osTimerPeriodic = 1\n
\n }
 Timer type value for the timer definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osStatus osKernelInitialize (void)
 Initialize the RTOS Kernel for creating objects.  More...
 
osStatus osKernelStart (void)
 Start the RTOS Kernel.  More...
 
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started.  More...
 
uint32_t osKernelSysTick (void)
 Get the RTOS kernel system timer counter.  More...
 
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY.  More...
 
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread.  More...
 
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads.  More...
 
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY.  More...
 
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread.  More...
 
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread.  More...
 
osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay).  More...
 
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout.  More...
 
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer.  More...
 
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer.  More...
 
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer.  More...
 
osStatus osTimerDelete (osTimerId timer_id)
 Delete a timer that was created by osTimerCreate.  More...
 
int32_t osSignalSet (osThreadId thread_id, int32_t signals)
 Set the specified Signal Flags of an active thread.  More...
 
int32_t osSignalClear (osThreadId thread_id, int32_t signals)
 Clear the specified Signal Flags of an active thread.  More...
 
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread.  More...
 
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object.  More...
 
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available.  More...
 
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait.  More...
 
osStatus osMutexDelete (osMutexId mutex_id)
 Delete a Mutex that was created by osMutexCreate.  More...
 
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources.  More...
 
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available.  More...
 
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token.  More...
 
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
 Delete a Semaphore that was created by osSemaphoreCreate.  More...
 
osPoolId osPoolCreate (const osPoolDef_t *pool_def)
 Create and Initialize a memory pool.  More...
 
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool.  More...
 
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero.  More...
 
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool.  More...
 
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue.  More...
 
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue.  More...
 
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue.  More...
 
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue.  More...
 
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail.  More...
 
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero.  More...
 
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue.  More...
 
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue.  More...
 
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail.  More...
 
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osWaitForever   0xFFFFFFFF
\n
\n
Note
MUST REMAIN UNCHANGED: osWaitForever shall be consistent in every CMSIS-RTOS. wait forever timeout value 
\n\n
\n
\n
Typedef Documentation
\n\n
\n
\n      \n        \n          \n        \n      
typedef void(* os_pthread)(void const *argument)
\n
\n
Note
MUST REMAIN UNCHANGED: os_pthread shall be consistent in every CMSIS-RTOS. 
\n\n
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\n\n
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typedef void(* os_ptimer)(void const *argument)
\n
\n
Note
MUST REMAIN UNCHANGED: os_ptimer shall be consistent in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_mailQ_cb* osMailQId
\n
\n
Note
CAN BE CHANGED: os_mailQ_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_messageQ_cb* osMessageQId
\n
\n
Note
CAN BE CHANGED: os_messageQ_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_mutex_cb* osMutexId
\n
\n
Note
CAN BE CHANGED: os_mutex_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_pool_cb* osPoolId
\n
\n
Note
CAN BE CHANGED: os_pool_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_semaphore_cb* osSemaphoreId
\n
\n
Note
CAN BE CHANGED: os_semaphore_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_thread_cb* osThreadId
\n
\n
Note
CAN BE CHANGED: os_thread_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
typedef struct os_timer_cb* osTimerId
\n
\n
Note
CAN BE CHANGED: os_timer_cb is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Enumeration Type Documentation
\n\n
\n
\n      \n        \n          \n        \n      
enum os_timer_type
\n
\n
Note
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. 
\n\n\n\n
Enumerator
osTimerOnce \n
one-shot timer 
\n
osTimerPeriodic \n
repeating timer 
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
enum osPriority
\n
\n
Note
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS. 
\n\n\n\n\n\n\n\n\n\n
Enumerator
osPriorityIdle \n
priority: idle (lowest) 
\n
osPriorityLow \n
priority: low 
\n
osPriorityBelowNormal \n
priority: below normal 
\n
osPriorityNormal \n
priority: normal (default) 
\n
osPriorityAboveNormal \n
priority: above normal 
\n
osPriorityHigh \n
priority: high 
\n
osPriorityRealtime \n
priority: realtime (highest) 
\n
osPriorityError \n
system cannot determine priority or thread has illegal priority 
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
enum osStatus
\n
\n
Note
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS. 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Enumerator
osOK \n
function completed; no error or event occurred. 
\n
osEventSignal \n
function completed; signal event occurred. 
\n
osEventMessage \n
function completed; message event occurred. 
\n
osEventMail \n
function completed; mail event occurred. 
\n
osEventTimeout \n
function completed; timeout occurred. 
\n
osErrorParameter \n
parameter error: a mandatory parameter was missing or specified an incorrect object. 
\n
osErrorResource \n
resource not available: a specified resource was not available. 
\n
osErrorTimeoutResource \n
resource not available within given time: a specified resource was not available within the timeout period. 
\n
osErrorISR \n
not allowed in ISR context: the function cannot be called from interrupt service routines. 
\n
osErrorISRRecursive \n
function called multiple times from ISR with same object. 
\n
osErrorPriority \n
system cannot determine priority or thread has illegal priority. 
\n
osErrorNoMemory \n
system is out of memory: it was impossible to allocate or reserve memory for the operation. 
\n
osErrorValue \n
value of a parameter is out of range. 
\n
osErrorOS \n
unspecified RTOS error: run-time error but no other error message fits. 
\n
os_status_reserved \n
prevent from enum down-size compiler optimization. 
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • RTOS
  • Template
  • cmsis_os.h
    • \n    
  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/cmsis__os_8txt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: cmsis_os.txt File Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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cmsis_os.txt File Reference
  
\n
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\nEnumerations
enum  osPriority { 
\n  osPriorityIdle = -3, \n
\n  osPriorityLow = -2, \n
\n  osPriorityBelowNormal = -1, \n
\n  osPriorityNormal = 0, \n
\n  osPriorityAboveNormal = +1, \n
\n  osPriorityHigh = +2, \n
\n  osPriorityRealtime = +3, \n
\n  osPriorityError = 0x84\n
\n }
 
enum  os_timer_type { 
\n  osTimerOnce = 0, \n
\n  osTimerPeriodic = 1\n
\n }
 
enum  osStatus { 
\n  osOK = 0, \n
\n  osEventSignal = 0x08, \n
\n  osEventMessage = 0x10, \n
\n  osEventMail = 0x20, \n
\n  osEventTimeout = 0x40, \n
\n  osErrorParameter = 0x80, \n
\n  osErrorResource = 0x81, \n
\n  osErrorTimeoutResource = 0xC1, \n
\n  osErrorISR = 0x82, \n
\n  osErrorISRRecursive = 0x83, \n
\n  osErrorPriority = 0x84, \n
\n  osErrorNoMemory = 0x85, \n
\n  osErrorValue = 0x86, \n
\n  osErrorOS = 0xFF, \n
\n  os_status_reserved = 0x7FFFFFFF\n
\n }
 
\n
\n
\n\n
\n  
    \n    
  • cmsis_os.txt
    • \n    
  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/cmsis_os_h.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Header File Template: cmsis_os.h\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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Header File Template: cmsis_os.h 
  
\n
\n
\n
The file cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). Each RTOS that is compliant with CMSIS-RTOS shall provide a specific cmsis_os.h header file that represents its implementation.
\n
The file cmsis_os.h contains:
\n
    \n
  • CMSIS-RTOS API function definitions
    • \n
  • struct definitions for parameters and return types
    • \n
  • status and priority values used by CMSIS-RTOS API functions
    • \n
  • macros for defining threads and other kernel objects
    • \n
\n
Name conventions and header file modifications
\n
All definitions are prefixed with os to give an unique name space for CMSIS-RTOS functions. Definitions that are prefixed os_ are not used in the application code but local to this header file. All definitions and functions that belong to a module are grouped and have a common prefix, i.e. osThread.
\n
Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. These definitions can be specific to the underlying RTOS kernel.
\n
Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
\n
Function calls from interrupt service routines
\n
The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
\n\n
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called from an ISR context the status code osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
\n
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code osErrorISRRecursive.
\n
Define and reference object definitions
\n
With #define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file that is used throughout a project as shown below:
\n
Header File 
\n
#include <cmsis_os.h>                                         // CMSIS RTOS header file
\n
\n
// Thread definition
\n
extern void thread_sample (void const *argument);             // function prototype
\n
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
\n
\n
// Pool definition
\n
osPoolDef(MyPool, 10, long);
\n
This header file defines all objects when included in a C/C++ source file. When #define osObjectsExternal is present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be used throughout the whole project.
\n
Example 
\n
#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
\n
#define osObjectExternal   // Objects will be defined as external symbols
\n
#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
\n
 
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  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/dir_67baed4ff719a838d401a6dc7774cf41.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: RTOS Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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RTOS Directory Reference
  
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\n\n\n\n\n
\nDirectories
directory  Template
 
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  • RTOS
    • \n    
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    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/dir_9afdeffb8e409a4e0df5c5bf9ab1a7d2.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Template Directory Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Template Directory Reference
  
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\nFiles
file  cmsis_os.h
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l\n\n\n\n\nCMSIS-RTOS: File List\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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File List
  
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Here is a list of all files with brief descriptions:
\n\n\n
\"\\\"\"*\"cmsis_os.h
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  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/functions.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Data Fields\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/functions_vars.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Data Fields - Variables\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals_defs.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals_enum.html",
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CMSIS-RTOS\n    Version 1.02\n   
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    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals_eval.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals_func.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/globals_type.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Globals\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: CMSIS-RTOS API\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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CMSIS-RTOS API
  
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This section describes the CMSIS-RTOS API.  \nMore...
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\nContent
 Kernel Information and Control
 Provide version/system information and start the RTOS Kernel. 
 
 Thread Management
 Define, create, and control thread functions. 
 
 Generic Wait Functions
 Wait for a time period or unspecified events. 
 
 Timer Management
 Create and control timer and timer callback functions. 
 
 Signal Management
 Control or wait for signal flags. 
 
 Mutex Management
 Synchronize thread execution with a Mutex. 
 
 Semaphore Management
 Control access to shared resources. 
 
 Memory Pool Management
 Define and manage fixed-size memory pools. 
 
 Message Queue Management
 Control, send, receive, or wait for messages. 
 
 Mail Queue Management
 Control, send, receive, or wait for mail. 
 
 Generic Data Types and Definitions
 Data Type Definitions used by the CMSIS-RTOS API functions. 
 
 Status and Error Codes
 Status and Error Codes returned by CMSIS-RTOS API functions. 
 
\n
Description
\n
The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel. It provides the following functional modules: 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s.js",
    "content": "var group___c_m_s_i_s___r_t_o_s =\n[\n    [ \"Kernel Information and Control\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl\" ],\n    [ \"Thread Management\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt\" ],\n    [ \"Generic Wait Functions\", \"group___c_m_s_i_s___r_t_o_s___wait.html\", \"group___c_m_s_i_s___r_t_o_s___wait\" ],\n    [ \"Timer Management\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt\" ],\n    [ \"Signal Management\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt\" ],\n    [ \"Mutex Management\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt\" ],\n    [ \"Semaphore Management\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt\" ],\n    [ \"Memory Pool Management\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt\" ],\n    [ \"Message Queue Management\", \"group___c_m_s_i_s___r_t_o_s___message.html\", \"group___c_m_s_i_s___r_t_o_s___message\" ],\n    [ \"Mail Queue Management\", \"group___c_m_s_i_s___r_t_o_s___mail.html\", \"group___c_m_s_i_s___r_t_o_s___mail\" ],\n    [ \"Generic Data Types and Definitions\", \"group___c_m_s_i_s___r_t_o_s___definitions.html\", \"group___c_m_s_i_s___r_t_o_s___definitions\" ],\n    [ \"Status and Error Codes\", \"group___c_m_s_i_s___r_t_o_s___status.html\", \"group___c_m_s_i_s___r_t_o_s___status\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Generic Data Types and Definitions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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Generic Data Types and Definitions
CMSIS-RTOS API
  
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Data Type Definitions used by the CMSIS-RTOS API functions.  \nMore...
\n\n\n\n\n\n\n\n
\nData Structures
struct  osEvent
 Event structure contains detailed information about an event.  More...
 
struct  os_mailQ
 
\n
Description
\n
The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions. 
\n
Data Structure Documentation
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\n      \n        \n          \n        \n      
struct osEvent
\n
\n
Note
MUST REMAIN UNCHANGED: os_event shall be consistent in every CMSIS-RTOS. However the struct may be extended at the end.
\n
The osEvent structure describes the events returned by CMSIS-RTOS functions. 
\n
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Data Fields
osStatus status
 status code: event or error information  More...
 
union {
   uint32_t   v
 message as 32-bit value  More...
 
   void *   p
 message or mail as void pointer  More...
 
   int32_t   signals
 signal flags  More...
 
} value
 event value  More...
 
union {
   osMailQId   mail_id
 mail id obtained by osMailCreate  More...
 
   osMessageQId   message_id
 message id obtained by osMessageCreate  More...
 
} def
 event definition  More...
 
\n
Field Documentation
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union { ... }   def
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osMailQId mail_id
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osMessageQId message_id
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int32_t signals
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osStatus status
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struct os_mailQ
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The osEvent structure describes the events returned by CMSIS-RTOS functions. 
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___definitions.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___definitions =\n[\n    [ \"def\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#a596b6d55c3321db19239256bbe403df6\", null ],\n    [ \"mail_id\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#ac86175a4b1706bee596f3018322df26e\", null ],\n    [ \"message_id\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#af394cbe21dde7377974e63af38cd87b0\", null ],\n    [ \"p\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#a117104b82864d3b23ec174af6d392709\", null ],\n    [ \"signals\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#ad0dda1bf7e74f1576261d493fba232b6\", null ],\n    [ \"status\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#ad477a289f1f03ac45407b64268d707d3\", null ],\n    [ \"v\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc\", null ],\n    [ \"value\", \"group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Kernel Information and Control\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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\n  
\nMacros |\nFunctions  
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Kernel Information and Control
CMSIS-RTOS API
  
\n
\n
\n\n
Provide version/system information and start the RTOS Kernel.  \nMore...
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\nMacros
#define osFeature_MainThread   1
 main thread 1=main can be thread, 0=not available  More...
 
#define osFeature_SysTick   1
 osKernelSysTick functions: 1=available, 0=not available  More...
 
#define osCMSIS   0x10002
 API version (main [31:16] .sub [15:0])  More...
 
#define osCMSIS_KERNEL   0x10000
 RTOS identification and version (main [31:16] .sub [15:0])  More...
 
#define osKernelSystemId   "KERNEL V1.00"
 RTOS identification string.  More...
 
#define osKernelSysTickFrequency   100000000
 The RTOS kernel system timer frequency in Hz.  More...
 
#define osKernelSysTickMicroSec(microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
 Convert a microseconds value to a RTOS kernel system timer value.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osStatus osKernelInitialize (void)
 Initialize the RTOS Kernel for creating objects.  More...
 
osStatus osKernelStart (void)
 Start the RTOS Kernel.  More...
 
int32_t osKernelRunning (void)
 Check if the RTOS kernel is already started.  More...
 
uint32_t osKernelSysTick (void)
 Get the RTOS kernel system timer counter.  More...
 
\n
Description
\n
The Kernel Information and Control function group allow to:
\n
    \n
  • obtain information about the system and the underlying kernel.
    • \n
  • obtain version information about the CMSIS RTOS API.
    • \n
  • initialize of the RTOS kernel for creating objects.
    • \n
  • start the RTOS kernel and thread switching.
    • \n
  • check the execution status of the RTOS kernel.
    • \n
\n
The function main is a special thread function that may be started at system initialization. In this case it has the initial priority osPriorityNormal.
\n
Example 
\n
void system_error (void)  {
\n
                                                 // fatal error: set system to a safe state
\n
  while (1);
\n
}
\n
                                                                                
\n
\n
int main (void) {                                // program execution starts here
\n
  if (osKernelInitialize () != osOK)  {          // initialize RTOS kernel
\n
    system_error ();                             // invoke system error function
\n
  }
\n
\n
  system_initialize ();                          // setup and initialize peripherals
\n
  osThreadCreate (osThread(job1));               // create threads              
\n
  osThreadCreate (osThread(job2));              
\n
  if (osKernelStart () != osOK)  {               // start kernel with job2 execution
\n
    system_error ();                             // invoke system error function
\n
  }
\n
}
\n
 
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osCMSIS   0x10002
\n
\n
Version information of the CMSIS RTOS API whereby major version is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.
\n
Note
MUST REMAIN UNCHANGED: osCMSIS identifies the CMSIS-RTOS API version. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
#define osCMSIS_KERNEL   0x10000
\n
\n
Identifies the underlying RTOS kernel and version number. The actual name of that define depends on the RTOS Kernel used in the implementation. For example, osCMSIS_FreeRTOS identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major version is in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.
\n
Note
CAN BE CHANGED: osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_MainThread   1
\n
\n
A CMSIS-RTOS implementation may support to start thread execution with the function 'main'.
\n\n
Note
MUST REMAIN UNCHANGED: osFeature_xxx shall be consistent in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_SysTick   1
\n
\n
A CMSIS-RTOS implementation may provide access to the RTOS kernel system timer.
\n\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
#define osKernelSystemId   "KERNEL V1.00"
\n
\n
Defines a string that identifies the underlying RTOS Kernel and provides version information. The length of that string is limited to 21 bytes. A valid identification string is for example, \"FreeRTOS V1.00\".
\n
Note
MUST REMAIN UNCHANGED: osKernelSystemId shall be consistent in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
#define osKernelSysTickFrequency   100000000
\n
\n
Specifies the frequency of the Kernel SysTick timer in Hz. The value is typically use to scale a time value and is for example used in osKernelSysTickMicroSec.
\n
See Also
osKernelSysTick
\n
Note
Reflects the system timer setting and is typically defined in a configuration file. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osKernelSysTickMicroSec( microsec)   (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
\n
\n
Allows to scale a microsecond value to the frequency of the Kernel SysTick timer. This macro is typically used to check for short timeouts in polling loops.
\n
See Also
osKernelSysTick
\n
Parameters
\n  \n    \n  
microsectime value in microseconds. 
\n  
\n
\n
Returns
time value normalized to the osKernelSysTickFrequency 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osKernelInitialize (void )
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osKernelInitialize shall be consistent in every CMSIS-RTOS.
\n
Initialize of the RTOS Kernel to allow peripheral setup and creation of other RTOS objects with the functions:
\n\n
The RTOS kernel does not start thread switching until the function osKernelStart is called.
\n
Note
In case that the RTOS Kernel starts thread execution with the function main the function osKernelInitialize stops thread switching. This allows to setup the system to a defined state before thread switching is resumed with osKernelStart.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
int main (void)  {
\n
  if (!osKernelRunning ())  {                    // if kernel is not running, initialize the kernel
\n
    if (osKernelInitialize () != osOK)  {        // check osStatus for other possible valid values
\n
      // exit with an error message
\n
    }
\n
  }
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
int32_t osKernelRunning (void )
\n
\n
Note
MUST REMAIN UNCHANGED: osKernelRunning shall be consistent in every CMSIS-RTOS. 
\n
Returns
0 RTOS is not started, 1 RTOS is started.
\n
Identifies if the RTOS kernel is started. For systems with the option to start the main function as a thread this allows to identify that the RTOS kernel is already running.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
int main (void) {                                // program execution starts here
\n
  if (osKernelRunning ())  {                    
\n
    :                                            // main is already a thread function
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osKernelStart (void )
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osKernelStart shall be consistent in every CMSIS-RTOS.
\n
Start the RTOS Kernel and begin thread switching.
\n
Note
When the CMSIS-RTOS starts thread execution with the function main this function resumes thread switching. The main thread will continue executing after osKernelStart.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the RTOS kernel has been successfully started.
    • \n
  • osErrorISR: osKernelStart cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
int main (void)  {
\n
  if (osKernelInitialize () != osOK)  {          // check osStatus for other possible valid values
\n
    // exit with an error message
\n
  }
\n
 
\n
  if (!osKernelRunning ())  {                    // is the kernel running ?
\n
    if (osKernelStart () != osOK)  {             // start the kernel
\n
                                                     // kernel could not be started
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
uint32_t osKernelSysTick (void )
\n
\n
Note
MUST REMAIN UNCHANGED: osKernelSysTick shall be consistent in every CMSIS-RTOS. 
\n
Returns
RTOS kernel system timer as 32-bit value
\n
Get the value of the Kernel SysTick timer for time comparison. The value is a rolling 32-bit counter that is typically composed of the kernel system interrupt timer value and an counter that counts these interrupts.
\n
This function allows the implementation of timeout checks. These are for example required when checking for a busy status in a device or peripheral initialization routine.
\n
Example 
\n
#include "cmsis_os.h"
\n
\n
void SetupDevice (void)  {
\n
  uint32_t tick;
\n
  
\n
  tick = osKernelSysTick();                      // get start value of the Kernel system tick
\n
  Device.Setup ();                               // initialize a device or peripheral
\n
  do {                                           // poll device busy status for 100 microseconds
\n
    if (!Device.Busy) break;                     // check if device is correctly initialized
\n
  } while ((osKernelSysTick() - tick) < osKernelTickMicroSec(100));  
\n
  if (Device.Busy)  {              
\n
    ;                                            // in case device still busy, signal error
\n
  }
\n
                                                 // start interacting with device
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___kernel_ctrl.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___kernel_ctrl =\n[\n    [ \"osCMSIS\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga702196bacccbb978620c736b209387f1\", null ],\n    [ \"osCMSIS_KERNEL\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gab78dce646fabec479c5f34bc5175b7de\", null ],\n    [ \"osFeature_MainThread\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga22f7d235bc9f783933bd5a981fd79696\", null ],\n    [ \"osFeature_SysTick\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gae554ec16c23c5b7d65affade2a351891\", null ],\n    [ \"osKernelSystemId\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga47cf03658f01cdffca688e9096b58289\", null ],\n    [ \"osKernelSysTickFrequency\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga9e0954d52722673e2031233a2ab99960\", null ],\n    [ \"osKernelSysTickMicroSec\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gae12c190af42d7310d8006d64f4ed5a88\", null ],\n    [ \"osKernelInitialize\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga53d078a801022e202e8115c083ece68e\", null ],\n    [ \"osKernelRunning\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#ga3b571de44cd3094c643247a7397f86b5\", null ],\n    [ \"osKernelStart\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gaab668ffd2ea76bb0a77ab0ab385eaef2\", null ],\n    [ \"osKernelSysTick\", \"group___c_m_s_i_s___r_t_o_s___kernel_ctrl.html#gad0262e4688e95d1e9038afd9bcc16001\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Mail Queue Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
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\n  
\nMacros |\nFunctions  
\n  
\n
Mail Queue Management
CMSIS-RTOS API
  
\n
\n
\n\n
Control, send, receive, or wait for mail.  \nMore...
\n\n\n\n\n\n\n\n\n\n\n\n
\nMacros
#define osFeature_MailQ   1
 Mail Queues: 1=available, 0=not available.  More...
 
#define osMailQDef(name, queue_sz, type)
 Create a Mail Queue Definition.  More...
 
#define osMailQ(name)   &os_mailQ_def_##name
 Access a Mail Queue Definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize mail queue.  More...
 
void * osMailAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail.  More...
 
void * osMailCAlloc (osMailQId queue_id, uint32_t millisec)
 Allocate a memory block from a mail and set memory block to zero.  More...
 
osStatus osMailPut (osMailQId queue_id, void *mail)
 Put a mail to a queue.  More...
 
osEvent osMailGet (osMailQId queue_id, uint32_t millisec)
 Get a mail from a queue.  More...
 
osStatus osMailFree (osMailQId queue_id, void *mail)
 Free a memory block from a mail.  More...
 
\n
Description
\n
The Mail Queue Management function group allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine.
\n
\n\"MailQueue.png\"/\n
\nCMSIS-RTOS Mail Queue
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_MailQ   1
\n
\n
A CMSIS-RTOS implementation may support mail queues.
\n\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osMailQ( name)   &os_mailQ_def_##name
\n
\n
Access to the mail queue definition for the function osMailCreate.
\n
Parameters
\n  \n    \n  
namename of the queue 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMailQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
#define osMailQDef( name, 
 queue_sz, 
 type 
)
\n
\n
Define the attributes of a mail queue that can by the function osMailCreate using osMailQ.
\n
Parameters
\n  \n    \n    \n    \n  
namename of the queue 
queue_szmaximum number of messages in queue 
typedata type of a single message element 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMailQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void * osMailAlloc (osMailQId queue_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 
\n  
\n
\n
Returns
pointer to memory block that can be filled with mail or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osMailAlloc shall be consistent in every CMSIS-RTOS.
\n
Allocate a memory block from the mail queue that is filled with the mail information.
\n
The argument queue_id specifies a mail queue identifier that is obtain with osMailCreate.
\n
The argument millisec specifies how long the system waits for a mail slot to become available. While the system waits the tread calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail slot can be allocated.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Note
The parameter millisec must be 0 for using this function in an ISR.
\n
A NULL pointer is returned when no memory slot can be obtained or queue specifies an illegal parameter. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
void * osMailCAlloc (osMailQId queue_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 
\n  
\n
\n
Returns
pointer to memory block that can be filled with mail or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osMailCAlloc shall be consistent in every CMSIS-RTOS.
\n
Allocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared.
\n
The argument queue_id specifies a mail queue identifier that is obtain with osMailCreate.
\n
The argument millisec specifies how long the system waits for a mail slot to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail slot can be allocated.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Note
The parameter millisec must be 0 for using this function in an ISR.
\n
A NULL pointer is returned when no memory block can be obtained or queue specifies an illegal parameter. 
\n\n
\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osMailQId osMailCreate (const osMailQDef_t * queue_def, 
osThreadId thread_id 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_defreference to the mail queue definition obtain with osMailQ 
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL. 
\n  
\n
\n
Returns
mail queue ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osMailCreate shall be consistent in every CMSIS-RTOS.
\n
Initialize and create a mail queue.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
osThreadId tid_thread1;                          // ID for thread 1
\n
osThreadId tid_thread2;                          // ID for thread 2
\n
 
\n
typedef struct {                                 // Mail object structure
\n
  float    voltage;                              // AD result of measured voltage
\n
  float    current;                              // AD result of measured current
\n
  int      counter;                              // A counter value
\n
} T_MEAS;
\n
 
\n
osMailQDef(mail, 16, T_MEAS);                    // Define mail queue
\n
osMailQId  mail;
\n
 
\n
void send_thread (void const *argument);         // forward reference
\n
void recv_thread (void const *argument);
\n
 
\n
osThreadDef(send_thread, osPriorityNormal, 1, 0);     // thread definitions
\n
osThreadDef(recv_thread, osPriorityNormal, 1, 2000);
\n
 
\n
/*
\n
    Thread 1: Send thread
\n
 */
\n
void send_thread (void const *argument) {
\n
  T_MEAS *mptr;
\n
 
\n
  mptr = osMailAlloc(mail, osWaitForever);       // Allocate memory
\n
  mptr->voltage = 223.72;                        // Set the mail content
\n
  mptr->current = 17.54;
\n
  mptr->counter = 120786;
\n
  osMailPut(mail, mptr);                         // Send Mail
\n
  osDelay(100);
\n
   
\n
  mptr = osMailAlloc(mail, osWaitForever);       // Allocate memory
\n
  mptr->voltage = 227.23;                        // Prepare 2nd mail
\n
  mptr->current = 12.41;
\n
  mptr->counter = 170823;
\n
  osMailPut(mail, mptr);                         // Send Mail
\n
  osThreadYield();                               // Cooperative multitasking
\n
                                                 // We are done here, exit this thread
\n
}
\n
 
\n
/*
\n
    Thread 2: Receive thread
\n
 */
\n
void recv_thread (void const *argument) {
\n
  T_MEAS  *rptr;
\n
  osEvent  evt;
\n
   
\n
  for (;;) {
\n
    evt = osMailGet(mail, osWaitForever);        // wait for mail
\n
    if (evt.status == osEventMail) {
\n
      rptr = evt.value.p;
\n
      printf ("\\nVoltage: %.2f V\\n", rptr->voltage);
\n
      printf ("Current: %.2f A\\n", rptr->current);
\n
      printf ("Number of cycles: %d\\n", rptr->counter);
\n
      osMailFree(mail, rptr);                    // free memory allocated for mail
\n
    }
\n
  }
\n
}
\n
 
\n
void StartApplication (void) {
\n
  mail = osMailCreate(osMailQ(mail), NULL);      // create mail queue
\n
 
\n
  tid_thread1 = osThreadCreate(osThread(send_thread), NULL);
\n
  tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osStatus osMailFree (osMailQId queue_id, 
void * mail 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]mailpointer to the memory block that was obtained with osMailGet. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMailFree shall be consistent in every CMSIS-RTOS.
\n
Free the memory block specified by mail and return it to the mail queue.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the mail block is released.
    • \n
  • osErrorValue: mail block does not belong to the mail queue pool.
    • \n
  • osErrorParameter: the value to the parameter queue_id is incorrect. 
    • \n
\n\n
\n
\n\n
\n
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osEvent osMailGet (osMailQId queue_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]millisectimeout value or 0 in case of no time-out 
\n  
\n
\n
Returns
event that contains mail information or error code. 
\n
Note
MUST REMAIN UNCHANGED: osMailGet shall be consistent in every CMSIS-RTOS.
\n
Suspend the execution of the current RUNNING thread until a mail arrives. When a mail is already in the queue, the function returns instantly with the mail information.
\n
The argument millisec specifies how long the system waits for a mail to arrive. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a mail arrives.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Note
The parameter millisec must be 0 for using this function in an ISR.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: no mail is available in the queue and no timeout was specified
    • \n
  • osEventTimeout: no mail has arrived during the given timeout period.
    • \n
  • osEventMail: mail received, value.p contains the pointer to mail content.
    • \n
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • \n
\n\n
\n
\n\n
\n
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osStatus osMailPut (osMailQId queue_id, 
void * mail 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmail queue ID obtained with osMailCreate. 
[in]mailmemory block previously allocated with osMailAlloc or osMailCAlloc. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMailPut shall be consistent in every CMSIS-RTOS.
\n
Put the memory block specified with mail into the mail queue specified by queue.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the message is put into the queue.
    • \n
  • osErrorValue: mail was previously not allocated as memory slot.
    • \n
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • \n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mail.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___mail =\n[\n    [ \"osFeature_MailQ\", \"group___c_m_s_i_s___r_t_o_s___mail.html#gaceb2e0071ce160d153047f2eac1aca8e\", null ],\n    [ \"osMailQ\", \"group___c_m_s_i_s___r_t_o_s___mail.html#gad2deeb66d51ade54e63d8f87ff2ec9d2\", null ],\n    [ \"osMailQDef\", \"group___c_m_s_i_s___r_t_o_s___mail.html#ga58d712b16c0c6668059f509386d1e55b\", null ],\n    [ \"osMailAlloc\", \"group___c_m_s_i_s___r_t_o_s___mail.html#gadf5ce811bd6a56e617e902a1db6c2194\", null ],\n    [ \"osMailCAlloc\", \"group___c_m_s_i_s___r_t_o_s___mail.html#ga8fde74f6fe5b9e88f75cc5eb8f2124fd\", null ],\n    [ \"osMailCreate\", \"group___c_m_s_i_s___r_t_o_s___mail.html#gaa177e7fe5820dd70d8c9e46ded131174\", null ],\n    [ \"osMailFree\", \"group___c_m_s_i_s___r_t_o_s___mail.html#ga27c1060cf21393f96b4fd1ed1c0167cc\", null ],\n    [ \"osMailGet\", \"group___c_m_s_i_s___r_t_o_s___mail.html#gac6ad7e6e7d6c4a80e60da22c57a42ccd\", null ],\n    [ \"osMailPut\", \"group___c_m_s_i_s___r_t_o_s___mail.html#ga485ef6f81854ebda8ffbce4832181e02\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Message Queue Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
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\n\n
\n\n
\n  
\nMacros |\nFunctions  
\n  
\n
Message Queue Management
CMSIS-RTOS API
  
\n
\n
\n\n
Control, send, receive, or wait for messages.  \nMore...
\n\n\n\n\n\n\n\n\n\n\n\n
\nMacros
#define osFeature_MessageQ   1
 Message Queues: 1=available, 0=not available.  More...
 
#define osMessageQDef(name, queue_sz, type)
 Create a Message Queue Definition.  More...
 
#define osMessageQ(name)   &os_messageQ_def_##name
 Access a Message Queue Definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
 Create and Initialize a Message Queue.  More...
 
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
 Put a Message to a Queue.  More...
 
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
 Get a Message or Wait for a Message from a Queue.  More...
 
\n
Description
\n
Message Queue Management functions allow to control, send, receive, or wait for messages. A message can be an integer or pointer value that is send to a thread or interrupt service routine.
\n
\n\"MessageQueue.png\"/\n
\nCMSIS-RTOS Message Queue
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_MessageQ   1
\n
\n
A CMSIS-RTOS implementation may support message queues.
\n\n\n
\n
\n\n
\n
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#define osMessageQ( name)   &os_messageQ_def_##name
\n
\n
Access to the message queue definition for the function osMessageCreate.
\n
Parameters
\n  \n    \n  
namename of the queue 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMessageQ shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
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#define osMessageQDef( name, 
 queue_sz, 
 type 
)
\n
\n
Define the attributes of a message queue created by the function osMessageCreate using osMessageQ.
\n
Parameters
\n  \n    \n    \n    \n  
namename of the queue. 
queue_szmaximum number of messages in the queue. 
typedata type of a single message element (for debugger). 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMessageQDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osMessageQId osMessageCreate (const osMessageQDef_t * queue_def, 
osThreadId thread_id 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_defqueue definition referenced with osMessageQ. 
[in]thread_idthread ID (obtained by osThreadCreate or osThreadGetId) or NULL. 
\n  
\n
\n
Returns
message queue ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osMessageCreate shall be consistent in every CMSIS-RTOS.
\n
Create and initialize a message queue.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
osThreadId tid_thread1;                          // ID for thread 1
\n
osThreadId tid_thread2;                          // for thread 2
\n
 
\n
typedef struct {                                 // Message object structure
\n
  float    voltage;                              // AD result of measured voltage
\n
  float    current;                              // AD result of measured current
\n
  int      counter;                              // A counter value
\n
} T_MEAS;
\n
 
\n
osPoolDef(mpool, 16, T_MEAS);                    // Define memory pool
\n
osPoolId  mpool;
\n
osMessageQDef(MsgBox, 16, T_MEAS);               // Define message queue
\n
osMessageQId  MsgBox;
\n
 
\n
void send_thread (void const *argument);         // forward reference
\n
void recv_thread (void const *argument);         // forward reference
\n
                                                 // Thread definitions
\n
osThreadDef(send_thread, osPriorityNormal, 1, 0);
\n
osThreadDef(recv_thread, osPriorityNormal, 1, 2000);
\n
 
\n
/*
\n
    Thread 1: Send thread
\n
 */
\n
void send_thread (void const *argument) {
\n
  T_MEAS    *mptr;
\n
 
\n
  mptr = osPoolAlloc(mpool);                     // Allocate memory for the message
\n
  mptr->voltage = 223.72;                        // Set the message content
\n
  mptr->current = 17.54;
\n
  mptr->counter = 120786;
\n
  osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever);  // Send Message
\n
  osDelay(100);
\n
 
\n
  mptr = osPoolAlloc(mpool);                     // Allocate memory for the message
\n
  mptr->voltage = 227.23;                        // Prepare a 2nd message
\n
  mptr->current = 12.41;
\n
  mptr->counter = 170823;
\n
  osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever);  // Send Message
\n
  osThreadYield();                               // Cooperative multitasking
\n
                                                 // We are done here, exit this thread
\n
}
\n
 
\n
/*
\n
    Thread 2: Receive thread
\n
 */
\n
void recv_thread (void const *argument) {
\n
  T_MEAS  *rptr;
\n
  osEvent  evt;
\n
   
\n
  for (;;) {
\n
    evt = osMessageGet(MsgBox, osWaitForever);  // wait for message
\n
    if (evt.status == osEventMessage) {
\n
      rptr = evt.value.p;
\n
      printf ("\\nVoltage: %.2f V\\n", rptr->voltage);
\n
      printf ("Current: %.2f A\\n", rptr->current);
\n
      printf ("Number of cycles: %d\\n", rptr->counter);
\n
      osPoolFree(mpool, rptr);                  // free memory allocated for message
\n
    }
\n
  }
\n
}
\n
 
\n
void StartApplication (void) {
\n
  mpool = osPoolCreate(osPool(mpool));                 // create memory pool
\n
  MsgBox = osMessageCreate(osMessageQ(MsgBox), NULL);  // create msg queue
\n
   
\n
  tid_thread1 = osThreadCreate(osThread(send_thread), NULL);
\n
  tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osEvent osMessageGet (osMessageQId queue_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]queue_idmessage queue ID obtained with osMessageCreate. 
[in]millisectimeout value or 0 in case of no time-out. 
\n  
\n
\n
Returns
event information that includes status code. 
\n
Note
MUST REMAIN UNCHANGED: osMessageGet shall be consistent in every CMSIS-RTOS.
\n
Suspend the execution of the current RUNNING thread until a message arrives. When a message is already in the queue, the function returns instantly with the message information.
\n
The argument millisec specifies how long the system waits for a message to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout value can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a message arrives.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Note
The parameter millisec must be 0 for using this function in an ISR.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: no message is available in the queue and no timeout was specified.
    • \n
  • osEventTimeout: no message has arrived during the given timeout period.
    • \n
  • osEventMessage: message received, value.p contains the pointer to message.
    • \n
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • \n
\n\n
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osStatus osMessagePut (osMessageQId queue_id, 
uint32_t info, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]queue_idmessage queue ID obtained with osMessageCreate. 
[in]infomessage information. 
[in]millisectimeout value or 0 in case of no time-out. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMessagePut shall be consistent in every CMSIS-RTOS.
\n
Put the message info in a message queue specified by queue_id.
\n
When the message queue is full, the system retries for a specified time with millisec. While the system retries the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a message queue slot becomes available.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Note
The parameter millisec must be 0 for using this function in an ISR.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the message is put into the queue.
    • \n
  • osErrorResource: no memory in the queue was available.
    • \n
  • osErrorTimeoutResource: no memory in the queue was available during the given time limit.
    • \n
  • osErrorParameter: a parameter is invalid or outside of a permitted range. 
    • \n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___message.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___message =\n[\n    [ \"osFeature_MessageQ\", \"group___c_m_s_i_s___r_t_o_s___message.html#ga479a6561f859e3d4818e25708593d203\", null ],\n    [ \"osMessageQ\", \"group___c_m_s_i_s___r_t_o_s___message.html#ga2d446a0b4bb90bf05d6f92eedeaabc97\", null ],\n    [ \"osMessageQDef\", \"group___c_m_s_i_s___r_t_o_s___message.html#gac9a6a6276c12609793e7701afcc82326\", null ],\n    [ \"osMessageCreate\", \"group___c_m_s_i_s___r_t_o_s___message.html#gaf3b9345cf426304d46565152bc26fb78\", null ],\n    [ \"osMessageGet\", \"group___c_m_s_i_s___r_t_o_s___message.html#ga6c6892b8f2296cca6becd57ca2d7e1ae\", null ],\n    [ \"osMessagePut\", \"group___c_m_s_i_s___r_t_o_s___message.html#gac0dcf462fc92de8ffaba6cc004514a6d\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Mutex Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
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\nMacros |\nFunctions  
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Mutex Management
CMSIS-RTOS API
  
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\n
\n\n
Synchronize thread execution with a Mutex.  \nMore...
\n\n\n\n\n\n\n\n\n
\nMacros
#define osMutexDef(name)   const osMutexDef_t os_mutex_def_##name = { 0 }
 Define a Mutex.  More...
 
#define osMutex(name)   &os_mutex_def_##name
 Access a Mutex definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
 Create and Initialize a Mutex object.  More...
 
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
 Wait until a Mutex becomes available.  More...
 
osStatus osMutexRelease (osMutexId mutex_id)
 Release a Mutex that was obtained by osMutexWait.  More...
 
osStatus osMutexDelete (osMutexId mutex_id)
 Delete a Mutex that was created by osMutexCreate.  More...
 
\n
Description
\n
The Mutex Management function group is used to synchronize the execution of threads. This is for example used to protect access to a shared resource, for example a shared memory image.
\n
Note
Mutex Management functions cannot be called from interrupt service routines (ISR).
\n
\n\"Mutex.png\"/\n
\nCMSIS-RTOS Mutex
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osMutex( name)   &os_mutex_def_##name
\n
\n
Access to mutex object for the functions osMutexCreate.
\n
Parameters
\n  \n    \n  
namename of the mutex object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMutex shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osMutexDef( name)   const osMutexDef_t os_mutex_def_##name = { 0 }
\n
\n
Define a mutex object that is referenced by osMutex.
\n
Parameters
\n  \n    \n  
namename of the mutex object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osMutexDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osMutexId osMutexCreate (const osMutexDef_t * mutex_def)
\n
\n
Parameters
\n  \n    \n  
[in]mutex_defmutex definition referenced with osMutex. 
\n  
\n
\n
Returns
mutex ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osMutexCreate shall be consistent in every CMSIS-RTOS.
\n
Create and initialize a Mutex object.
\n
Example 
\n
#include "cmsis_os.h"
\n
  
\n
osMutexDef (MutexIsr);                                     // Mutex name definition
\n
  
\n
void CreateMutex (void)  {
\n
osMutexId mutex_id;   
\n
 
\n
  mutex_id = osMutexCreate  (osMutex (MutexIsr));
\n
  if (mutex_id != NULL)  {
\n
    // Mutex object created
\n
  }   
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osMutexDelete (osMutexId mutex_id)
\n
\n
Parameters
\n  \n    \n  
[in]mutex_idmutex ID obtained by osMutexCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMutexDelete shall be consistent in every CMSIS-RTOS.
\n
Delete a Mutex object. The function releases internal memory obtained for Mutex handling. After this call the mutex_id is no longer valid and cannot be used. The Mutex may be created again using the function osMutexCreate.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the mutex object has been deleted.
    • \n
  • osErrorISR: osMutexDelete cannot be called from interrupt service routines.
    • \n
  • osErrorResource: all tokens have already been released.
    • \n
  • osErrorParameter: the parameter mutex_id is incorrect.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
  
\n
osMutexDef (MutexIsr);                                     // Mutex name definition 
\n
osMutexId mutex_id;                                                                                // Mutex id populated by the function CreateMutex()
\n
osMutexId CreateMutex (void);                              // function prototype that creates the Mutex
\n
 
\n
void DeleteMutex (osMutexId mutex_id)  {
\n
osStatus status;
\n
  
\n
  if (mutex_id != NULL)  {
\n
    status = osMutexDelete(mutex_id);
\n
    if (status != osOK)  {
\n
          // handle failure code
\n
        }
\n
  }
\n
}
\n
 \n
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\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osMutexRelease (osMutexId mutex_id)
\n
\n
Parameters
\n  \n    \n  
[in]mutex_idmutex ID obtained by osMutexCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMutexRelease shall be consistent in every CMSIS-RTOS.
\n
Release a Mutex that was obtained with osMutexWait. Other threads that currently wait for the same mutex will be now put into the state READY.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the mutex has been correctly released.
    • \n
  • osErrorResource: the mutex was not obtained before.
    • \n
  • osErrorParameter: the parameter mutex_id is incorrect.
    • \n
  • osErrorISR: osMutexRelease cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
  
\n
osMutexDef (MutexIsr);                                     // Mutex name definition 
\n
osMutexId mutex_id;                                                                                // Mutex id populated by the function CreateMutex()
\n
osMutexId CreateMutex (void);                              // function prototype that creates the Mutex
\n
 
\n
void ReleaseMutex (osMutexId mutex_id)  {
\n
osStatus status;
\n
  
\n
  if (mutex_id != NULL)  {
\n
    status = osMutexRelease(mutex_id);
\n
    if (status != osOK)  {
\n
          // handle failure code
\n
        }
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osStatus osMutexWait (osMutexId mutex_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]mutex_idmutex ID obtained by osMutexCreate. 
[in]millisectimeout value or 0 in case of no time-out. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osMutexWait shall be consistent in every CMSIS-RTOS.
\n
Wait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object.
\n
The argument millisec specifies how long the system waits for a mutex. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until the mutex becomes available.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the mutex has been obtain.
    • \n
  • osErrorTimeoutResource: the mutex could not be obtained in the given time.
    • \n
  • osErrorResource: the mutex could not be obtained when no timeout was specified.
    • \n
  • osErrorParameter: the parameter mutex_id is incorrect.
    • \n
  • osErrorISR: osMutexWait cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
  
\n
osMutexDef (MutexIsr);
\n
  
\n
void WaitMutex (void)  {
\n
osMutexId mutex_id;   
\n
osStatus status;
\n
 
\n
  mutex_id = osMutexCreate  (osMutex (MutexIsr));
\n
  if (mutex_id != NULL)  {
\n
    status  = osMutexWait    (mutex_id, 0);
\n
    if (status != osOK)  {
\n
          // handle failure code
\n
        }
\n
  }
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___mutex_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___mutex_mgmt =\n[\n    [ \"osMutex\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga1122a86faa64b4a0880c76cf68d0c934\", null ],\n    [ \"osMutexDef\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga9b522438489d7c402c95332b58bc94f3\", null ],\n    [ \"osMutexCreate\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5c9de56e717016e39e788064e9a291cc\", null ],\n    [ \"osMutexDelete\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#gac27e24135185d51d18f3dabc20910219\", null ],\n    [ \"osMutexRelease\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga006e4744d741e8e132c3d5bbc295afe1\", null ],\n    [ \"osMutexWait\", \"group___c_m_s_i_s___r_t_o_s___mutex_mgmt.html#ga5e1752b73f573ee015dbd9ef1edaba13\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Memory Pool Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nMacros |\nFunctions  
\n  
\n
Memory Pool Management
CMSIS-RTOS API
  
\n
\n
\n\n
Define and manage fixed-size memory pools.  \nMore...
\n\n\n\n\n\n\n\n\n\n\n\n
\nMacros
#define osFeature_Pool   1
 Memory Pools: 1=available, 0=not available.  More...
 
#define osPoolDef(name, no, type)
 Define a Memory Pool.  More...
 
#define osPool(name)   &os_pool_def_##name
 Access a Memory Pool definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osPoolId osPoolCreate (const osPoolDef_t *pool_def)
 Create and Initialize a memory pool.  More...
 
void * osPoolAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool.  More...
 
void * osPoolCAlloc (osPoolId pool_id)
 Allocate a memory block from a memory pool and set memory block to zero.  More...
 
osStatus osPoolFree (osPoolId pool_id, void *block)
 Return an allocated memory block back to a specific memory pool.  More...
 
\n
Description
\n
The Memory Pool Management function group is used to define and manage fixed-sized memory pools. 
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_Pool   1
\n
\n
A CMSIS-RTOS implementation may support fixed-size memory pools.
\n\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osPool( name)   &os_pool_def_##name
\n
\n
Access a memory pool for the functions osPoolCreate.
\n
Parameters
\n  \n    \n  
namename of the memory pool 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osPool shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
#define osPoolDef( name, 
 no, 
 type 
)
\n
\n
Define a memory pool that is referenced by osPool.
\n
Parameters
\n  \n    \n    \n    \n  
namename of the memory pool. 
nomaximum number of blocks (objects) in the memory pool. 
typedata type of a single block (object). 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osPoolDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void * osPoolAlloc (osPoolId pool_id)
\n
\n
Parameters
\n  \n    \n  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 
\n  
\n
\n
Returns
address of the allocated memory block or NULL in case of no memory available. 
\n
Note
MUST REMAIN UNCHANGED: osPoolAlloc shall be consistent in every CMSIS-RTOS.
\n
Allocate a memory block from the memory pool.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
typedef struct {
\n
  uint8_t Buf[32];
\n
  uint8_t Idx;
\n
} MEM_BLOCK;
\n
 
\n
osPoolDef (MemPool, 8, MEM_BLOCK);
\n
 
\n
void AlocMemoryPoolBlock (void)  {
\n
  osPoolId   MemPool_Id;
\n
  MEM_BLOCK *addr;
\n
 
\n
  MemPool_Id = osPoolCreate (osPool (MemPool));
\n
  if (MemPool_Id != NULL)  {
\n
    :
\n
    // allocate a memory block
\n
    addr = (MEM_BLOCK *)osPoolAlloc (MemPool_Id);
\n
    
\n
    if (addr != NULL) {
\n
      // memory block was allocated
\n
      :
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
void * osPoolCAlloc (osPoolId pool_id)
\n
\n
Parameters
\n  \n    \n  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 
\n  
\n
\n
Returns
address of the allocated memory block or NULL in case of no memory available. 
\n
Note
MUST REMAIN UNCHANGED: osPoolCAlloc shall be consistent in every CMSIS-RTOS.
\n
Allocate a memory block from the memory pool. The block is initialized to zero.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
typedef struct {
\n
  uint8_t Buf[32];
\n
  uint8_t Idx;
\n
} MEM_BLOCK;
\n
 
\n
osPoolDef (MemPool, 8, MEM_BLOCK);
\n
 
\n
void CAlocMemoryPoolBlock (void)  {
\n
  osPoolId   MemPool_Id;
\n
  MEM_BLOCK *addr;
\n
 
\n
  MemPool_Id = osPoolCreate (osPool (MemPool));
\n
  if (MemPool_Id != NULL)  {
\n
    :
\n
    // allocate a memory block
\n
    addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);
\n
    
\n
    if (addr != NULL) {
\n
      // memory block was allocated
\n
      :
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osPoolId osPoolCreate (const osPoolDef_t * pool_def)
\n
\n
Parameters
\n  \n    \n  
[in]pool_defmemory pool definition referenced with osPool. 
\n  
\n
\n
Returns
memory pool ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osPoolCreate shall be consistent in every CMSIS-RTOS.
\n
Create and initialize a memory pool.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
typedef struct {
\n
  uint8_t Buf[32];
\n
  uint8_t Idx;
\n
} MEM_BLOCK;
\n
 
\n
osPoolDef (MemPool, 8, MEM_BLOCK);
\n
  
\n
void CreateMemoryPool (void)  {
\n
osPoolId MemPool_Id;
\n
 
\n
  MemPool_Id = osPoolCreate (osPool (MemPool));
\n
  if (MemPool_Id != NULL)  {
\n
    // memory pool created
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osStatus osPoolFree (osPoolId pool_id, 
void * block 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]pool_idmemory pool ID obtain referenced with osPoolCreate. 
[in]blockaddress of the allocated memory block that is returned to the memory pool. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osPoolFree shall be consistent in every CMSIS-RTOS.
\n
Return a memory block to a memory pool.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the memory block is released.
    • \n
  • osErrorValue: block does not belong to the memory pool.
    • \n
  • osErrorParameter: a parameter is invalid or outside of a permitted range.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
typedef struct {
\n
  uint8_t Buf[32];
\n
  uint8_t Idx;
\n
} MEM_BLOCK;
\n
 
\n
osPoolDef (MemPool, 8, MEM_BLOCK);
\n
  
\n
void CAlocMemoryPoolBlock (void)  {
\n
  osPoolId   MemPool_Id;
\n
  MEM_BLOCK *addr;
\n
  osStatus   status;
\n
  
\n
  MemPool_Id = osPoolCreate (osPool (MemPool));
\n
  if (MemPool_Id != NULL)  {
\n
    addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);
\n
    if (addr != NULL) {
\n
      :
\n
      // return a memory block back to pool
\n
      status = osPoolFree (MemPool_Id, addr);
\n
      if (status==osOK)  {
\n
        // handle status code
\n
      }
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___pool_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___pool_mgmt =\n[\n    [ \"osFeature_Pool\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gadd84b683001de327894851b428587caa\", null ],\n    [ \"osPool\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga5f0b204a82327533d420210125c90697\", null ],\n    [ \"osPoolDef\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga87b471d4fe2d5dbd0040708edd52771b\", null ],\n    [ \"osPoolAlloc\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#gaa0b2994f1a866c19e0d11e6e0d44f543\", null ],\n    [ \"osPoolCAlloc\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga9f129fcad4730fbd1048ad4fa262f36a\", null ],\n    [ \"osPoolCreate\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga34af5c4f4ab38f4138ea7f1f9ece3a1a\", null ],\n    [ \"osPoolFree\", \"group___c_m_s_i_s___r_t_o_s___pool_mgmt.html#ga4a861e9c469c9d0daf5721bf174f8e54\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Semaphore Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
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\n    \n
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\n    \n  
\n
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\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nMacros |\nFunctions  
\n  
\n
Semaphore Management
CMSIS-RTOS API
  
\n
\n
\n\n
Control access to shared resources.  \nMore...
\n\n\n\n\n\n\n\n\n\n\n\n
\nMacros
#define osFeature_Semaphore   30
 maximum count for osSemaphoreCreate function  More...
 
#define osSemaphoreDef(name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 Define a Semaphore object.  More...
 
#define osSemaphore(name)   &os_semaphore_def_##name
 Access a Semaphore definition.  More...
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
 Create and Initialize a Semaphore object used for managing resources.  More...
 
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
 Wait until a Semaphore token becomes available.  More...
 
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
 Release a Semaphore token.  More...
 
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
 Delete a Semaphore that was created by osSemaphoreCreate.  More...
 
\n
Description
\n
The Semaphore Management function group is used to manage and protect access to shared resources. For example, with a Semaphore the access to a group of identical peripherals can be managed. The number of available resources is specified as parameter of the osSemaphoreCreate function.
\n
Each time a Semaphore token is obtained with osSemaphoreWait the semaphore count is decremented. When the semaphore count is 0, no Semaphore token can be obtained. Semaphores are released with osSemaphoreRelease; this function increments the semaphore count.
\n
\n\"Semaphore.png\"/\n
\nCMSIS-RTOS Semaphore
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_Semaphore   30
\n
\n
A CMSIS-RTOS implementation may support semaphores. The value osFeature_Semaphore indicates the maximum index count for a semaphore. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osSemaphore( name)   &os_semaphore_def_##name
\n
\n
Access to semaphore object for the functions osSemaphoreCreate.
\n
Parameters
\n  \n    \n  
namename of the semaphore object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osSemaphore shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osSemaphoreDef( name)   const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
\n
\n
Define a semaphore object that is referenced by osSemaphore.
\n
Parameters
\n  \n    \n  
namename of the semaphore object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osSemaphoreDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t * semaphore_def, 
int32_t count 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]semaphore_defsemaphore definition referenced with osSemaphore. 
[in]countnumber of available resources. 
\n  
\n
\n
Returns
semaphore ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
\n
Create and initialize a Semaphore object that is used to manage access to shared resources. The parameter count specifies the number of available resources. The count value 1 creates a binary semaphore.
\n
Example 
\n
#include "cmsis_os.h"
\n
   
\n
osThreadId tid_thread1;                          // ID for thread 1
\n
osThreadId tid_thread2;                          // ID for thread 2
\n
  
\n
osSemaphoreId semaphore;                         // Semaphore ID
\n
osSemaphoreDef(semaphore);                       // Semaphore definition
\n
   
\n
/*
\n
     Thread 1 - High Priority - Active every 3ms
\n
 */
\n
void thread1 (void const *argument) {
\n
  int32_t value;
\n
\n
  while (1) {
\n
    osDelay(3);                                  // Pass control to other tasks for 3ms
\n
    val = osSemaphoreWait (semaphore, 1);        // Wait 1ms for the free semaphore
\n
    if (val > 0) {
\n
                                                 // If there was no time-out the semaphore was acquired
\n
      :                                          // OK, the interface is free now, use it.
\n
      osSemaphoreRelease (semaphore);            // Return a token back to a semaphore
\n
    }
\n
  }
\n
}
\n
  
\n
/*
\n
     Thread 2 - Normal Priority - looks for a free semaphore and uses
\n
                                  the resource whenever it is available
\n
 */
\n
void thread2 (void const *argument) {
\n
  while (1) {
\n
    osSemaphoreWait (semaphore, osWaitForever);  // Wait indefinitely for a free semaphore
\n
                                                 // OK, the interface is free now, use it.
\n
    :
\n
    osSemaphoreRelease (semaphore);              // Return a token back to a semaphore.
\n
  }
\n
}
\n
  
\n
/* Thread definitions */
\n
osThreadDef(thread1, osPriorityHigh,   1, 0);
\n
osThreadDef(thread2, osPriorityNormal, 1, 0);
\n
   
\n
void StartApplication (void) {
\n
  semaphore = osSemaphoreCreate(osSemaphore(semaphore), 1);
\n
\n
  tid_thread1 = osThreadCreate(osThread(thread1), NULL);
\n
  tid_thread2 = osThreadCreate(osThread(thread2), NULL);
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)
\n
\n
Parameters
\n  \n    \n  
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
\n
Delete a Semaphore object. The function releases internal memory obtained for Semaphore handling. After this call the semaphore_id is no longer valid and cannot be used. The Semaphore may be created again using the function osSemaphoreCreate.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the semaphore object has been deleted.
    • \n
  • osErrorISR: osSemaphoreDelete cannot be called from interrupt service routines.
    • \n
  • osErrorResource: the semaphore object could not be deleted.
    • \n
  • osErrorParameter: the parameter semaphore_id is incorrect. 
    • \n
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
\n
\n
Parameters
\n  \n    \n  
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
\n
Release a Semaphore token. This increments the count of available semaphore tokens.
\n
Note
osSemaphoreRelease can be called also from interrupt service routines.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the semaphore has been released.
    • \n
  • osErrorResource: all tokens have already been released.
    • \n
  • osErrorParameter: the parameter semaphore_id is incorrect. 
    • \n
\n\n
\n
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int32_t osSemaphoreWait (osSemaphoreId semaphore_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]semaphore_idsemaphore object referenced with osSemaphoreCreate. 
[in]millisectimeout value or 0 in case of no time-out. 
\n  
\n
\n
Returns
number of available tokens, or -1 in case of incorrect parameters. 
\n
Note
MUST REMAIN UNCHANGED: osSemaphoreWait shall be consistent in every CMSIS-RTOS.
\n
Wait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter millisec.
\n
The argument millisec specifies how long the system waits for a Semaphore token to become available. While the system waits the thread that is calling this function is put into the state WAITING. The millisec timeout can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until the Semaphore token becomes available.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
The return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available. 
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___semaphore_mgmt =\n[\n    [ \"osFeature_Semaphore\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga7da4c7bfb340779c9fc7b321f5ab3e3a\", null ],\n    [ \"osSemaphore\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga03761ee8d2c3cd4544e18364ab301dac\", null ],\n    [ \"osSemaphoreDef\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga9e66fe361749071e5ab87826c43c2f1b\", null ],\n    [ \"osSemaphoreCreate\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#ga97381e8e55cd47cec390bf57c96d6edb\", null ],\n    [ \"osSemaphoreDelete\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gabae2801ac2c096f6e8c69a264908f595\", null ],\n    [ \"osSemaphoreRelease\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gab108914997c49e14d8ff1ae0d1988ca0\", null ],\n    [ \"osSemaphoreWait\", \"group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html#gacc15b0fc8ce1167fe43da33042e62098\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Signal Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
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\n    \n
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\n  
\nMacros |\nFunctions  
\n  
\n
Signal Management
CMSIS-RTOS API
  
\n
\n
\n\n
Control or wait for signal flags.  \nMore...
\n\n\n\n\n\n
\nMacros
#define osFeature_Signals   8
 maximum number of Signal Flags available per thread  More...
 
\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
int32_t osSignalSet (osThreadId thread_id, int32_t signals)
 Set the specified Signal Flags of an active thread.  More...
 
int32_t osSignalClear (osThreadId thread_id, int32_t signals)
 Clear the specified Signal Flags of an active thread.  More...
 
osEvent osSignalWait (int32_t signals, uint32_t millisec)
 Wait for one or more Signal Flags to become signaled for the current RUNNING thread.  More...
 
\n
Description
\n
The Signal Management function group allows to control or wait signal flags. Each thread has assigned signal flags. 
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_Signals   8
\n
\n
The CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available per thread. The maximum value is 31 signal flags per thread. 
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
int32_t osSignalClear (osThreadId thread_id, 
int32_t signals 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]signalsspecifies the signal flags of the thread that shall be cleared. 
\n  
\n
\n
Returns
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. 
\n
Note
MUST REMAIN UNCHANGED: osSignalClear shall be consistent in every CMSIS-RTOS.
\n
Clear the signal flags of an active thread. This function may be used also within interrupt service routines.
\n
Example 
\n
void Thread_2 (void const *arg);
\n
\n
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
\n
 
\n
static void EX_Signal_1 (void)  {
\n
  int32_t  signals;
\n
  osThreadId thread_id;
\n
  
\n
  thread_id = osThreadCreate (osThread(Thread_2), NULL);
\n
  if (thread_id == NULL)  {
\n
    // Failed to create a thread.
\n
  }
\n
  else  {
\n
f    :
\n
    signals = osSignalClear (thread_id, 0x01);
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
int32_t osSignalSet (osThreadId thread_id, 
int32_t signals 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]signalsspecifies the signal flags of the thread that should be set. 
\n  
\n
\n
Returns
previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. 
\n
Note
MUST REMAIN UNCHANGED: osSignalSet shall be consistent in every CMSIS-RTOS.
\n
Set the signal flags of an active thread. This function may be used also within interrupt service routines.
\n
Example 
\n
void Thread_2 (void const *arg);
\n
 
\n
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
\n
 
\n
static void EX_Signal_1 (void)  {
\n
  int32_t signals;
\n
  uint32_t exec;
\n
  osThreadId thread_id;
\n
  
\n
  thread_id = osThreadCreate (osThread(Thread_2), NULL);
\n
  if (thread_id == NULL)  {
\n
    // Failed to create a thread.
\n
  }
\n
  else  {
\n
    signals = osSignalSet (thread_id, 0x00000005);         // Send signals to the created thread
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osEvent osSignalWait (int32_t signals, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]signalswait until all specified signal flags set or 0 for any single signal flag. 
[in]millisectimeout value or 0 in case of no time-out. 
\n  
\n
\n
Returns
event flag information or error code. 
\n
Note
MUST REMAIN UNCHANGED: osSignalWait shall be consistent in every CMSIS-RTOS.
\n
Suspend the execution of the current RUNNING thread until all specified signal flags with the parameter signals are set. When this signal flags are already set, the function returns instantly. Otherwise the thread is put into the state WAITING. Signal flags that are reported as event are automatically cleared.
\n
The argument millisec specifies how long the system waits for the specified signal flags. While the system waits the tread calling this function is put into the state WAITING. The timeout value can have the following values:
\n
    \n
  • when millisec is 0, the function returns instantly.
    • \n
  • when millisec is set to osWaitForever the function will wait for an infinite time until a specified signal is set.
    • \n
  • all other values specify a time in millisecond for a timeout.
    • \n
\n
Status and Error Codes
\n
\n
    \n
  • osOK: no signal received when the timeout value millisec was 0.
    • \n
  • osEventTimeout: signal not occurred within timeout
    • \n
  • osEventSignal: signal occurred, value.signals contains the signal flags; these signal flags are cleared.
    • \n
  • osErrorValue: the value signals is outside of the permitted range.
    • \n
  • osErrorISR: osSignalWait cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
void Thread_2 (void const *arg);
\n
  
\n
osThreadDef (Thread_2, osPriorityHigh, 1, 0);
\n
   
\n
static void EX_Signal_1 (void)  {
\n
  osThreadId thread_id;
\n
  osEvent evt;
\n
    
\n
  thread_id = osThreadCreate (osThread(Thread_2), NULL);
\n
  if (thread_id == NULL)  {
\n
    // Failed to create a thread.
\n
  }
\n
  else  {
\n
    :
\n
    // wait for a signal
\n
    evt = osSignalWait (0x01, 100);
\n
    if (evt.status == osEventSignal)  {
\n
          // handle event status
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___signal_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___signal_mgmt =\n[\n    [ \"osFeature_Signals\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga01edde265710d883b6e237d34a6ef4a6\", null ],\n    [ \"osSignalClear\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga87283a6ebc31ce9ed42baf3ea7e4eab6\", null ],\n    [ \"osSignalSet\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga3de2730654589d6c3559c4b9e2825553\", null ],\n    [ \"osSignalWait\", \"group___c_m_s_i_s___r_t_o_s___signal_mgmt.html#ga38860acda96df47da6923348d96fc4c9\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Status and Error Codes\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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\nEnumerations  
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\n
Status and Error Codes
CMSIS-RTOS API
  
\n
\n
\n\n
Status and Error Codes returned by CMSIS-RTOS API functions.  \nMore...
\n\n\n\n\n
\nEnumerations
enum  osStatus { 
\n  osOK = 0, \n
\n  osEventSignal = 0x08, \n
\n  osEventMessage = 0x10, \n
\n  osEventMail = 0x20, \n
\n  osEventTimeout = 0x40, \n
\n  osErrorParameter = 0x80, \n
\n  osErrorResource = 0x81, \n
\n  osErrorTimeoutResource = 0xC1, \n
\n  osErrorISR = 0x82, \n
\n  osErrorISRRecursive = 0x83, \n
\n  osErrorPriority = 0x84, \n
\n  osErrorNoMemory = 0x85, \n
\n  osErrorValue = 0x86, \n
\n  osErrorOS = 0xFF, \n
\n  os_status_reserved = 0x7FFFFFFF\n
\n }
 
\n
Description
\n
The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return. 
\n
Enumeration Type Documentation
\n\n
\n
\n      \n        \n          \n        \n      
enum osStatus
\n
\n
Note
MUST REMAIN UNCHANGED: osStatus shall be consistent in every CMSIS-RTOS.
\n
The osStatus enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions. 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Enumerator
osOK \n
function completed; no error or event occurred. 
\n
osEventSignal \n
function completed; signal event occurred. 
\n
osEventMessage \n
function completed; message event occurred. 
\n
osEventMail \n
function completed; mail event occurred. 
\n
osEventTimeout \n
function completed; timeout occurred. 
\n
osErrorParameter \n
parameter error: a mandatory parameter was missing or specified an incorrect object. 
\n
osErrorResource \n
resource not available: a specified resource was not available. 
\n
osErrorTimeoutResource \n
resource not available within given time: a specified resource was not available within the timeout period. 
\n
osErrorISR \n
not allowed in ISR context: the function cannot be called from interrupt service routines. 
\n
osErrorISRRecursive \n
function called multiple times from ISR with same object. 
\n
osErrorPriority \n
system cannot determine priority or thread has illegal priority. 
\n
osErrorNoMemory \n
system is out of memory: it was impossible to allocate or reserve memory for the operation. 
\n
osErrorValue \n
value of a parameter is out of range. 
\n
osErrorOS \n
unspecified RTOS error: run-time error but no other error message fits. 
\n
os_status_reserved \n
prevent from enum down-size compiler optimization. 
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___status.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___status =\n[\n    [ \"osStatus\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99e\", [\n      [ \"osOK\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea9e1c9e2550bb4de8969a935acffc968f\", null ],\n      [ \"osEventSignal\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5df7e9643aa8a2f5f3a6f6ec59758518\", null ],\n      [ \"osEventMessage\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ead604f3673359dd4ac643b16dc5a2c342\", null ],\n      [ \"osEventMail\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea15b12e42b42b53f35fb8a2724ad02926\", null ],\n      [ \"osEventTimeout\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea78f477732375c0e1fca814e369618177\", null ],\n      [ \"osErrorParameter\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac24adca6a5d072c9f01c32178ba0d109\", null ],\n      [ \"osErrorResource\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea8fc5801e8b0482bdf22ad63a77f0155d\", null ],\n      [ \"osErrorTimeoutResource\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea314d24a49003f09459035db0dd7c9467\", null ],\n      [ \"osErrorISR\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea21635bdc492d3094fe83027fa4a30e2f\", null ],\n      [ \"osErrorISRRecursive\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf6552310a817452aedfcd453f2805d65\", null ],\n      [ \"osErrorPriority\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eab7dda0ef504817659334cbfd650ae56f\", null ],\n      [ \"osErrorNoMemory\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eaf1fac0240218e51eb30a13da2f8aae81\", null ],\n      [ \"osErrorValue\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea4672c8a0c0f6bb1d7981da4602e8e9ee\", null ],\n      [ \"osErrorOS\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99ea5fde24ff588ec5ab9cb8314bade26fbc\", null ],\n      [ \"os_status_reserved\", \"group___c_m_s_i_s___r_t_o_s___status.html#gae2e091fefc4c767117727bd5aba4d99eac7a77f5fe18a15a357790c36a4aca1b1\", null ]\n    ] ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Thread Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
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\n\n\n\n\n
\n\n
\n\n
\n  
\nMacros |\nEnumerations |\nFunctions  
\n  
\n
Thread Management
CMSIS-RTOS API
  
\n
\n
\n\n
Define, create, and control thread functions.  \nMore...
\n\n\n\n\n\n\n\n\n
\nMacros
#define osThreadDef(name, priority, instances, stacksz)
 Create a Thread Definition with function, priority, and stack requirements.  More...
 
#define osThread(name)   &os_thread_def_##name
 Access a Thread definition.  More...
 
\n\n\n\n
\nEnumerations
enum  osPriority { 
\n  osPriorityIdle = -3, \n
\n  osPriorityLow = -2, \n
\n  osPriorityBelowNormal = -1, \n
\n  osPriorityNormal = 0, \n
\n  osPriorityAboveNormal = +1, \n
\n  osPriorityHigh = +2, \n
\n  osPriorityRealtime = +3, \n
\n  osPriorityError = 0x84\n
\n }
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
 Create a thread and add it to Active Threads and set it to state READY.  More...
 
osThreadId osThreadGetId (void)
 Return the thread ID of the current running thread.  More...
 
osStatus osThreadTerminate (osThreadId thread_id)
 Terminate execution of a thread and remove it from Active Threads.  More...
 
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)
 Change priority of an active thread.  More...
 
osPriority osThreadGetPriority (osThreadId thread_id)
 Get current priority of an active thread.  More...
 
osStatus osThreadYield (void)
 Pass control to next thread that is in state READY.  More...
 
\n
Description
\n
The Thread Management function group allow defining, creating, and controlling thread functions in the system. The function main is a special thread function that is started at system initialization and has the initial priority osPriorityNormal.
\n
Threads can be in the following states:
\n
    \n
  • RUNNING: The thread that is currently running is in the RUNNING state. Only one thread at a time can be in this state.
    • \n
  • READY: Threads which are ready to run are in the READY state. Once the RUNNING thread has terminated or is WAITING the next READY thread with the highest priority becomes the RUNNING thread.
    • \n
  • WAITING: Threads that are waiting for an event to occur are in the WAITING state.
    • \n
  • INACTIVE: Threads that are not created or terminated are in the INACTIVE state. These threads typically consume no system resources.
    • \n
\n
\n\"ThreadStatus.png\"/\n
\nThread State and State Transitions
\n
 The CMSIS-RTOS assumes that threads are scheduled as shown in the figure Thread State and State Transitions. The thread states change as described below:
\n
    \n
  • A thread is created using the function osThreadCreate. This puts the thread into the READY or RUNNING state (depending on the thread priority).
    • \n
  • CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the RUNNING thread provided it does not wait for any event. The initial priority of a thread is defined with the osThreadDef but may be changed during execution using the function osThreadSetPriority.
    • \n
  • The RUNNING thread transfers into the WAITING state when it is waiting for an event.
    • \n
  • Active threads can be terminated any time using the function osThreadTerminate. Threads can terminate also by just returning from the thread function. Threads that are terminated are in the INACTIVE state and typically do not consume any dynamic memory resources. 
    • \n
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osThread( name)   &os_thread_def_##name
\n
\n
Access to the thread definition for the function osThreadCreate.
\n
Parameters
\n  \n    \n  
namename of the thread definition object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osThread shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
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\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
#define osThreadDef( name, 
 priority, 
 instances, 
 stacksz 
)
\n
\n
Define the attributes of a thread functions that can be created by the function osThreadCreate using osThread.
\n
Parameters
\n  \n    \n    \n    \n    \n  
namename of the thread function. 
priorityinitial priority of the thread function. 
instancesnumber of possible thread instances. 
stackszstack size (in bytes) requirements for the thread function. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameters to osThreadDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Enumeration Type Documentation
\n\n
\n
\n      \n        \n          \n        \n      
enum osPriority
\n
\n
Note
MUST REMAIN UNCHANGED: osPriority shall be consistent in every CMSIS-RTOS.
\n
The osPriority value specifies the priority for a thread. The default thread priority should be osPriorityNormal. If a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately to execute the new task.
\n
To prevent from a priority inversion, a CMSIS-RTOS complained OS may optionally implement a priority inheritance method. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread with a lower priority. 
\n\n\n\n\n\n\n\n\n\n
Enumerator
osPriorityIdle \n
priority: idle (lowest) 
\n
osPriorityLow \n
priority: low 
\n
osPriorityBelowNormal \n
priority: below normal 
\n
osPriorityNormal \n
priority: normal (default) 
\n
osPriorityAboveNormal \n
priority: above normal 
\n
osPriorityHigh \n
priority: high 
\n
osPriorityRealtime \n
priority: realtime (highest) 
\n
osPriorityError \n
system cannot determine priority or thread has illegal priority 
\n
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osThreadId osThreadCreate (const osThreadDef_t * thread_def, 
void * argument 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]thread_defthread definition referenced with osThread. 
[in]argumentpointer that is passed to the thread function as start argument. 
\n  
\n
\n
Returns
thread ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osThreadCreate shall be consistent in every CMSIS-RTOS.
\n
Start a thread function by adding it to the Active Threads list and set it to state READY. The thread function receives the argument pointer as function argument when the function is started. When the priority of the created thread function is higher than the current RUNNING thread, the created thread function starts instantly and becomes the new RUNNING thread.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg);                           // function prototype for Thread_1
\n
osThreadDef (Thread_1, osPriorityNormal, 1, 0);            // define Thread_1
\n
 
\n
void ThreadCreate_example (void) {
\n
  osThreadId id;
\n
  
\n
  id = osThreadCreate (osThread (Thread_1), NULL);         // create the thread
\n
  if (id == NULL) {                                        // handle thread creation
\n
    // Failed to create a thread
\n
  }
\n
  :
\n
  osThreadTerminate (id);                                  // stop the thread
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osThreadId osThreadGetId (void )
\n
\n
Returns
thread ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osThreadGetId shall be consistent in every CMSIS-RTOS.
\n
Get the thread ID of the current running thread.
\n
Example 
\n
void ThreadGetId_example (void)  {
\n
  osThreadId id;                                           // id for the currently running thread
\n
   
\n
  id = osThreadGetId ();
\n
  if (id == NULL) {
\n
    // Failed to get the id; not in a thread
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osPriority osThreadGetPriority (osThreadId thread_id)
\n
\n
Parameters
\n  \n    \n  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
\n  
\n
\n
Returns
current priority value of the thread function. 
\n
Note
MUST REMAIN UNCHANGED: osThreadGetPriority shall be consistent in every CMSIS-RTOS.
\n
Get the priority of an active thread. In case of a failure the value osPriorityError is returned.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg)  {                         // Thread function
\n
  osThreadId id;                                           // id for the currently running thread
\n
  osPriority priority;                                     // thread priority
\n
   
\n
  id = osThreadGetId ();                                   // Obtain ID of current running thread
\n
   
\n
  if (id != NULL)  {
\n
    priority = osThreadGetPriority (id);
\n
  }
\n
  else  {
\n
    // Failed to get the id
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osStatus osThreadSetPriority (osThreadId thread_id, 
osPriority priority 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
[in]prioritynew priority value for the thread function. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osThreadSetPriority shall be consistent in every CMSIS-RTOS.
\n
Change the priority of an active thread.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the priority of the specified thread has been successfully changed.
    • \n
  • osErrorParameter: thread_id is incorrect.
    • \n
  • osErrorValue: incorrect priority value.
    • \n
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • \n
  • osErrorISR: osThreadSetPriority cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg)  {                         // Thread function
\n
  osThreadId id;                                           // id for the currently running thread
\n
  osPriority pr;                                           // thread priority
\n
  osStatus   status;                                       // status of the executed function
\n
   
\n
  :  
\n
  id = osThreadGetId ();                                   // Obtain ID of current running thread
\n
   
\n
  if (id != NULL) {
\n
    status = osThreadSetPriority (id, osPriorityBelowNormal);
\n
    if (status == osOK)  {
\n
      // Thread priority changed to BelowNormal
\n
    }
\n
    else {
\n
      // Failed to set the priority
\n
    }
\n
  }
\n
  else  {
\n
    // Failed to get the id
\n
  }
\n
  :  
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osThreadTerminate (osThreadId thread_id)
\n
\n
Parameters
\n  \n    \n  
[in]thread_idthread ID obtained by osThreadCreate or osThreadGetId. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osThreadTerminate shall be consistent in every CMSIS-RTOS.
\n
Remove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.
\n
Note
In case that osThreadTerminate terminates the currently running task, the function never returns and other threads that are in the READY state are started.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the specified thread has been successfully terminated.
    • \n
  • osErrorParameter: thread_id is incorrect.
    • \n
  • osErrorResource: thread_id refers to a thread that is not an active thread.
    • \n
  • osErrorISR: osThreadTerminate cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg);                           // function prototype for Thread_1
\n
osThreadDef (Thread_1, osPriorityNormal, 1, 0);            // define Thread_1
\n
\n
void ThreadTerminate_example (void) {
\n
  osStatus status;
\n
  osThreadId id;
\n
 
\n
  id = osThreadCreate (osThread (Thread_1), NULL);         // create the thread
\n
  :  
\n
  status = osThreadTerminate (id);                         // stop the thread
\n
  if (status == osOK) {
\n
    // Thread was terminated successfully
\n
  }
\n
  else {
\n
    // Failed to terminate a thread
\n
  }
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osThreadYield (void )
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osThreadYield shall be consistent in every CMSIS-RTOS.
\n
Pass control to the next thread that is in state READY. If there is no other thread in the state READY, the current thread continues execution and no thread switching occurs.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the function has been correctly executed.
    • \n
  • osErrorISR: osThreadYield cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg)  {                         // Thread function
\n
  osStatus   status;                                       // status of the executed function
\n
  :
\n
  while (1)  {
\n
    status = osThreadYield();                              // 
\n
    if (status != osOK)  {
\n
      // thread switch not occurred, not in a thread function
\n
    }
\n
  }
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___thread_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___thread_mgmt =\n[\n    [ \"osThread\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf0c7c6b5e09f8be198312144b5c9e453\", null ],\n    [ \"osThreadDef\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaee93d929beb350f16e5cc7fa602e229f\", null ],\n    [ \"osPriority\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849a\", [\n      [ \"osPriorityIdle\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa549e79a43ff4f8b2b31afb613f5caa81\", null ],\n      [ \"osPriorityLow\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa61cb822239ac8f66dfbdc7291598a3d4\", null ],\n      [ \"osPriorityBelowNormal\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa193b650117c209b4a203954542bcc3e6\", null ],\n      [ \"osPriorityNormal\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa45a2895ad30c79fb97de18cac7cc19f1\", null ],\n      [ \"osPriorityAboveNormal\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa17b36cd9cd38652c2bc6d4803990674b\", null ],\n      [ \"osPriorityHigh\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa914433934143a9ba767e59577c56e6c2\", null ],\n      [ \"osPriorityRealtime\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aa1485dec3702434a1ec3cb74c7a17a4af\", null ],\n      [ \"osPriorityError\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga7f2b42f1983b9107775ec2a1c69a849aae35f5e2f9c64ad346822521b643bdea4\", null ]\n    ] ],\n    [ \"osThreadCreate\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gac59b5713cb083702dce759c73fd90dff\", null ],\n    [ \"osThreadGetId\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gab1df2a28925862ef8f9cf4e1c995c5a7\", null ],\n    [ \"osThreadGetPriority\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga4299d838978bc2aae5e4350754e6a4e9\", null ],\n    [ \"osThreadSetPriority\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#ga0dfb90ccf1f6e4b54b9251b12d1cbc8b\", null ],\n    [ \"osThreadTerminate\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaea135bb90eb853eff39e0800b91bbeab\", null ],\n    [ \"osThreadYield\", \"group___c_m_s_i_s___r_t_o_s___thread_mgmt.html#gaf13a667493c5d629a90c13e113b99233\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Timer Management\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
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\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nMacros |\nEnumerations |\nFunctions  
\n  
\n
Timer Management
CMSIS-RTOS API
  
\n
\n
\n\n
Create and control timer and timer callback functions.  \nMore...
\n\n\n\n\n\n\n\n\n
\nMacros
#define osTimerDef(name, function)
 Define a Timer object.  More...
 
#define osTimer(name)   &os_timer_def_##name
 Access a Timer definition.  More...
 
\n\n\n\n
\nEnumerations
enum  os_timer_type { 
\n  osTimerOnce = 0, \n
\n  osTimerPeriodic = 1\n
\n }
 
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nFunctions
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)
 Create a timer.  More...
 
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec)
 Start or restart a timer.  More...
 
osStatus osTimerStop (osTimerId timer_id)
 Stop the timer.  More...
 
osStatus osTimerDelete (osTimerId timer_id)
 Delete a timer that was created by osTimerCreate.  More...
 
\n
Description
\n
The Timer Management function group allow creating and controlling of timers and callback functions in the system. A callback function is called when a time period expires whereby both one-shot and periodic timers are possible. A timer can be started, restarted, or stopped.
\n
Timers are handled in the thread osTimerThread. Callback functions run under control of this thread and may use other CMSIS-RTOS API calls.
\n
The figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the callback function.
\n
\n\"Timer.png\"/\n
\nBehavior of a Periodic Timer
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
#define osTimer( name)   &os_timer_def_##name
\n
\n
Access to the timer definition for the function osTimerCreate.
\n
Parameters
\n  \n    \n  
namename of the timer object. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osTimer shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
#define osTimerDef( name, 
 function 
)
\n
\n
Define the attributes of a timer.
\n
Parameters
\n  \n    \n    \n  
namename of the timer object. 
functionname of the timer call back function. 
\n  
\n
\n
Note
CAN BE CHANGED: The parameter to osTimerDef shall be consistent but the macro body is implementation specific in every CMSIS-RTOS. 
\n\n
\n
\n
Enumeration Type Documentation
\n\n
\n
\n      \n        \n          \n        \n      
enum os_timer_type
\n
\n
Note
MUST REMAIN UNCHANGED: os_timer_type shall be consistent in every CMSIS-RTOS. The os_timer_type specifies the a repeating (periodic) or one-shot timer for the function osTimerCreate. 
\n\n\n\n
Enumerator
osTimerOnce \n
one-shot timer 
\n
osTimerPeriodic \n
repeating timer 
\n
\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osTimerId osTimerCreate (const osTimerDef_t * timer_def, 
os_timer_type type, 
void * argument 
)
\n
\n
Parameters
\n  \n    \n    \n    \n  
[in]timer_deftimer object referenced with osTimer. 
[in]typeosTimerOnce for one-shot or osTimerPeriodic for periodic behavior. 
[in]argumentargument to the timer call back function. 
\n  
\n
\n
Returns
timer ID for reference by other functions or NULL in case of error. 
\n
Note
MUST REMAIN UNCHANGED: osTimerCreate shall be consistent in every CMSIS-RTOS.
\n
Create a one-shot or periodic timer and associate it with a callback function argument. The timer is in stopped until it is started with osTimerStart.
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Timer1_Callback  (void const *arg);                   // prototypes for timer callback function
\n
void Timer2_Callback  (void const *arg);                   
\n
 
\n
osTimerDef (Timer1, Timer1_Callback);                      // define timers
\n
osTimerDef (Timer2, Timer2_Callback);                                      
\n
 
\n
uint32_t  exec1;                                           // argument for the timer call back function
\n
uint32_t  exec2;                                           // argument for the timer call back function
\n
\n
void TimerCreate_example (void)  {                                                         
\n
  osTimerId id1;                                           // timer id
\n
  osTimerId id2;                                           // timer id
\n
 
\n
  // Create one-shoot timer
\n
  exec1 = 1;
\n
  id1 = osTimerCreate (osTimer(Timer1), osTimerOnce, &exec1);
\n
  if (id1 != NULL)  {
\n
    // One-shoot timer created
\n
  }
\n
 
\n
  // Create periodic timer
\n
  exec2 = 2;
\n
  id2 = osTimerCreate (osTimer(Timer2), osTimerPeriodic, &exec2);
\n
  if (id2 != NULL)  {
\n
    // Periodic timer created
\n
  }
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osTimerDelete (osTimerId timer_id)
\n
\n
Parameters
\n  \n    \n  
[in]timer_idtimer ID obtained by osTimerCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osTimerDelete shall be consistent in every CMSIS-RTOS.
\n
Delete the timer object.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the specified timer has been deleted.
    • \n
  • osErrorISR: osTimerDelete cannot be called from interrupt service routines.
    • \n
  • osErrorParameter: timer_id is incorrect.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
\n
void Timer_Callback  (void const *arg);                    // prototype for timer callback function
\n
osTimerDef (Timer, Timer_Callback);                        // define timer
\n
 
\n
void TimerDelete_example (void)  {                                                         
\n
  osTimerId id;                                            // timer id
\n
  osStatus status;                                         // function return status  
\n
 
\n
  // Create periodic timer
\n
  exec = 1;
\n
  id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);
\n
  osTimerStart (id, 1000UL);                               // start timer
\n
  :
\n
  status = osTimerDelete (id);                             // stop and delete timer
\n
  if (status != osOK)  {
\n
    // Timer could not be deleted
\n
  } 
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n          \n        \n        \n          \n          \n          \n        \n      
osStatus osTimerStart (osTimerId timer_id, 
uint32_t millisec 
)
\n
\n
Parameters
\n  \n    \n    \n  
[in]timer_idtimer ID obtained by osTimerCreate. 
[in]millisectime delay value of the timer. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osTimerStart shall be consistent in every CMSIS-RTOS.
\n
Start or restart the timer.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the specified timer has been started or restarted.
    • \n
  • osErrorISR: osTimerStart cannot be called from interrupt service routines.
    • \n
  • osErrorParameter: timer_id is incorrect.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Time_Callback  (void const *arg)  {                   // timer callback function
\n
                                                           // arg contains &exec
\n
                                                           // called every second after osTimerStart
\n
} 
\n
\n
osTimerDef (Timer, Timer_Callback);                        // define timer
\n
uint32_t  exec;                                            // argument for the timer call back function
\n
 
\n
void TimerStart_example (void)  {                                                          
\n
  osTimerId id;                                            // timer id
\n
  uint32_t  timerDelay;                                    // timer value
\n
  osStatus  status;                                        // function return status
\n
 
\n
  // Create periodic timer
\n
  exec = 1;
\n
  id = osTimerCreate (osTimer(Timer), osTimerPeriodic, &exec);
\n
  if (id)  {
\n
    timerDelay = 1000;  
\n
    status = osTimerStart (id, timerDelay);                // start timer
\n
    if (status != osOK)  {
\n
      // Timer could not be started
\n
    } 
\n
  }
\n
  :
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osTimerStop (osTimerId timer_id)
\n
\n
Parameters
\n  \n    \n  
[in]timer_idtimer ID obtained by osTimerCreate. 
\n  
\n
\n
Returns
status code that indicates the execution status of the function. 
\n
Note
MUST REMAIN UNCHANGED: osTimerStop shall be consistent in every CMSIS-RTOS.
\n
Stop the timer.
\n
Status and Error Codes
\n
\n
    \n
  • osOK: the specified timer has been stopped.
    • \n
  • osErrorISR: osTimerStop cannot be called from interrupt service routines.
    • \n
  • osErrorParameter: timer_id is incorrect.
    • \n
  • osErrorResource: the timer is not started.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Timer_Callback  (void const *arg);                    // prototype for timer callback function
\n
osTimerDef (Timer, Timer_Callback);                        // define timer
\n
 
\n
void TimerStop_example (void)  {                                                           
\n
  osTimerId id;                                            // timer id
\n
  osStatus status;                                         // function return status
\n
 
\n
  // Create periodic timer
\n
  exec = 1;
\n
  id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);
\n
  osTimerStart (id, 1000);                                 // start timer
\n
  :
\n
  status = osTimerStop (id);                               // stop timer
\n
  if (status != osOK)  {
\n
    // Timer could not be stopped
\n
  } 
\n
  :
\n
  osTimerStart (id, 1000);                                 // start timer again
\n
  :
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___timer_mgmt.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___timer_mgmt =\n[\n    [ \"osTimer\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1b8d670eaf964b2910fa06885e650678\", null ],\n    [ \"osTimerDef\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga1c720627e08d1cc1afcad44e799ed492\", null ],\n    [ \"os_timer_type\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9\", [\n      [ \"osTimerOnce\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ad21712f8df5f97069c82dc9eec37b951\", null ],\n      [ \"osTimerPeriodic\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gadac860eb9e1b4b0619271e6595ed83d9ab9c91f9699162edb09bb7c90c11c8788\", null ]\n    ] ],\n    [ \"osTimerCreate\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#gaedd312bfdca04e0b8162b666e09a1ae6\", null ],\n    [ \"osTimerDelete\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga746b8043d906849bd65e3900fcb483cf\", null ],\n    [ \"osTimerStart\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga27a797a401b068e2644d1125f22a07ca\", null ],\n    [ \"osTimerStop\", \"group___c_m_s_i_s___r_t_o_s___timer_mgmt.html#ga58f36b121a812936435cacc6e1e0e091\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Generic Wait Functions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
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\n    \n  
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\n\n
\n  
\nMacros |\nFunctions  
\n  
\n
Generic Wait Functions
CMSIS-RTOS API
  
\n
\n
\n\n
Wait for a time period or unspecified events.  \nMore...
\n\n\n\n\n\n
\nMacros
#define osFeature_Wait   1
 osWait function: 1=available, 0=not available  More...
 
\n\n\n\n\n\n\n\n
\nFunctions
osStatus osDelay (uint32_t millisec)
 Wait for Timeout (Time Delay).  More...
 
osEvent osWait (uint32_t millisec)
 Wait for Signal, Message, Mail, or Timeout.  More...
 
\n
Description
\n
The Generic Wait function group provides means for a time delay and allow to wait for unspecified events. 
\n
Macro Definition Documentation
\n\n
\n
\n      \n        \n          \n        \n      
#define osFeature_Wait   1
\n
\n
A CMSIS-RTOS implementation may support the generic wait function osWait.
\n\n\n
\n
\n
Function Documentation
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osStatus osDelay (uint32_t millisec)
\n
\n
Parameters
\n  \n    \n  
[in]millisectime delay value 
\n  
\n
\n
Returns
status code that indicates the execution status of the function.
\n
Wait for a specified time period in millisec.
\n
Status and Error Codes
\n
\n
    \n
  • osEventTimeout: the time delay is executed.
    • \n
  • osErrorISR: osDelay cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
 
\n
void Thread_1 (void const *arg)  {               // Thread function
\n
  osStatus status;                               // capture the return status
\n
  uint32_t delayTime;                            // delay time in milliseconds
\n
 
\n
  delayTime = 1000;                              // delay 1 second
\n
  :
\n
  status = osDelay (delayTime);                  // suspend thread execution
\n
    // handle erroe code
\n
  :  
\n
}
\n
 \n
\n
\n\n
\n
\n      \n        \n          \n          \n          \n          \n          \n        \n      
osEvent osWait (uint32_t millisec)
\n
\n
Parameters
\n  \n    \n  
[in]millisectimeout value or 0 in case of no time-out 
\n  
\n
\n
Returns
event that contains signal, message, or mail information or error code. 
\n
Note
MUST REMAIN UNCHANGED: osWait shall be consistent in every CMSIS-RTOS.
\n
Wait for any event of the type Signal, Message, Mail for a specified time period in millisec. While the system waits the thread that is calling this function is put into the state WAITING. When millisec is set to osWaitForever the function will wait for an infinite time until a event occurs.
\n
Note
this function is optionally and may not be provided by all CMSIS-RTOS implementations.
\n
Status and Error Codes
\n
\n
    \n
  • osEventSignal: a signal event occurred and is returned.
    • \n
  • osEventMessage: a message event occurred and is returned.
    • \n
  • osEventMail: a mail event occurred and is returned.
    • \n
  • osEventTimeout: the time delay is executed.
    • \n
  • osErrorISR: osDelay cannot be called from interrupt service routines.
    • \n
\n
Example 
\n
#include "cmsis_os.h"
\n
\n
void Thread_1 (void const *arg)  {               // Thread function
\n
  osEvent  Event;                                // capture the event
\n
  uint32_t waitTime;                             // wait time in milliseconds
\n
 
\n
  :
\n
  waitTime = osWaitForever;                      // special "wait" value
\n
  Event = osWait (waitTime);                     // wait forever and until an event occurred
\n
  switch (Event.status)  {
\n
    case osEventSignal:                          // Signal arrived
\n
            :                                        // Event.value.signals contains the signal flags
\n
          break;
\n
\n
        case osEventMessage:                         // Message arrived
\n
            :                                        // Event.value.p contains the message pointer
\n
            :                                        // Event.def.message_id contains the message Id
\n
          break;
\n
\n
        case osEventMail:                            // Mail arrived
\n
            :                                        // Event.value.p contains the mail pointer
\n
            :                                        // Event.def.mail_id contains the mail Id
\n
          break;
\n
\n
        case osEventTimeout:                         // Timeout occurred
\n
          break;
\n
\n
        default:                                     // Error occurred
\n
          break;
\n
  }
\n
  :
\n
}
\n
 \n
\n
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:00 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/group___c_m_s_i_s___r_t_o_s___wait.js",
    "content": "var group___c_m_s_i_s___r_t_o_s___wait =\n[\n    [ \"osFeature_Wait\", \"group___c_m_s_i_s___r_t_o_s___wait.html#ga6c97d38879ae86491628f6e647639bad\", null ],\n    [ \"osDelay\", \"group___c_m_s_i_s___r_t_o_s___wait.html#ga02e19d5e723bfb06ba9324d625162255\", null ],\n    [ \"osWait\", \"group___c_m_s_i_s___r_t_o_s___wait.html#ga8470c8aaedfde524a44e22e5b2328285\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/index.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: Overview\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\n
Overview 
  
\n
\n
\n
The CMSIS-RTOS API is a generic RTOS interface for Cortex-M processor-based devices. CMSIS-RTOS provides a standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users and the software industry.
\n
    \n
  • CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
    • \n
  • The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.
    • \n
  • Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.
    • \n
  • Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS implementations.
    • \n
\n
Note
The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS vendors.
\n
\n\"API_Structure.png\"/\n
\nCMSIS-RTOS API Structure
\n
 A typical CMSIS-RTOS API implementation interfaces to an existing Real-Time Kernel. The CMSIS-RTOS API provides the following attributes and functionalities:
\n
    \n
  • Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and flexible which reduces the number of functions exposed to the user.
    • \n
\n\n
    \n
  • Interrupt Service Routines (ISR) can call many CMSIS-RTOS functions. When a CMSIS-RTOS function cannot be called from ISR context, it rejects the invocation.
    • \n
\n
    \n
  • Three different thread event types support communication between multiple threads and/or ISR:
      \n
    • Signals: are flags that may be used to signal specific conditions to a thread. Signals can be modified in an ISR or set from other threads.
      • \n
    • Message: is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type and queue size is defined in a descriptor.
      • \n
    • Mail: is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory allocation is provided. The mail type and queue size is defined in a descriptor.
      • \n
    \n
    • \n
\n\n
    \n
  • CPU time can be schedule with the following functionalities:
      \n
    • A timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified, the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.
      • \n
    • The osDelay function puts a thread into the state WAITING for a specified period of time.
      • \n
    • The generic osWait function waits for events that are assigned to a thread.
      • \n
    • The osThreadYield provides co-operative thread switching and passes execution to another thread of the same priority.
      • \n
    \n
    • \n
\n
The CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M Memory Protection Unit (MPU).
\n
In some RTOS implementations threads may execute on different processors and Mail and Message queues can therefore reside in shard memory resources.
\n
The CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and accessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects towards the Cortex-M processors. Optional features may be for Example
\n
    \n
  • Generic Wait function; i.e. with support of time intervals.
    • \n
  • Support of the Cortex-M Memory Protection Unit (MPU).
    • \n
  • Zero-copy mail queue.
    • \n
  • Support of multi-processor systems.
    • \n
  • Support of a DMA controller.
    • \n
  • Deterministic context switching.
    • \n
  • Round-robin context switching.
    • \n
  • Deadlock avoidance, for example with priority inversion.
    • \n
  • Zero interrupt latency by using the Cortex-M3/M4 instructions LDEX and STEX.
    • \n
\n
\n
Revision History of CMSIS-RTOS API
\n\n\n\n\n\n\n\n\n\n\n\n
Version Description  
V1.02 Added: New control functions for short timeouts in microsecond resolution osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec.
\n Removed: osSignalGet.   
V1.01 Added capabilities for C++, kernel initialization and object deletion.
\n Prepared for C++ class interface. In this context to const attribute has been moved from osXxxxDef_t typedefs to the osXxxxDef macros.
\n Added: osTimerDelete, osMutexDelete, osSemaphoreDelete.
\n Added: osKernelInitialize that prepares the Kernel for object creation.
\n   
V0.03 V1.00 First official Release.
\n Added: osKernelStart; starting 'main' as a thread is now an optional feature.
\n Semaphores have now the standard behavior.
\n osTimerCreate does no longer start the timer. Added: osTimerStart (replaces osTimerRestart).
\n Changed: osThreadPass is renamed to osThreadYield.   
V0.02 Preview Release.  
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
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b;a.browser.msie&&/(static|relative)/.test(this.css(\"position\"))||/absolute/.test(this.css(\"position\"))?b=this.parents().filter(function(){return/(relative|absolute|fixed)/.test(a.curCSS(this,\"position\",1))&&/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0):b=this.parents().filter(function(){return/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0);return/fixed/.test(this.css(\"position\"))||!b.length?a(document):b},zIndex:function(c){if(c!==b)return this.css(\"zIndex\",c);if(this.length){var d=a(this[0]),e,f;while(d.length&&d[0]!==document){e=d.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){f=parseInt(d.css(\"zIndex\"),10);if(!isNaN(f)&&f!==0)return f}d=d.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(a){a.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}}),a.each([\"Width\",\"Height\"],function(c,d){function h(b,c,d,f){a.each(e,function(){c-=parseFloat(a.curCSS(b,\"padding\"+this,!0))||0,d&&(c-=parseFloat(a.curCSS(b,\"border\"+this+\"Width\",!0))||0),f&&(c-=parseFloat(a.curCSS(b,\"margin\"+this,!0))||0)});return c}var e=d===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],f=d.toLowerCase(),g={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};a.fn[\"inner\"+d]=function(c){if(c===b)return g[\"inner\"+d].call(this);return this.each(function(){a(this).css(f,h(this,c)+\"px\")})},a.fn[\"outer\"+d]=function(b,c){if(typeof b!=\"number\")return g[\"outer\"+d].call(this,b);return this.each(function(){a(this).css(f,h(this,b,!0,c)+\"px\")})}}),a.extend(a.expr[\":\"],{data:function(b,c,d){return!!a.data(b,d[3])},focusable:function(b){return c(b,!isNaN(a.attr(b,\"tabindex\")))},tabbable:function(b){var d=a.attr(b,\"tabindex\"),e=isNaN(d);return(e||d>=0)&&c(b,!e)}}),a(function(){var b=document.body,c=b.appendChild(c=document.createElement(\"div\"));c.offsetHeight,a.extend(c.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0}),a.support.minHeight=c.offsetHeight===100,a.support.selectstart=\"onselectstart\"in c,b.removeChild(c).style.display=\"none\"}),a.extend(a.ui,{plugin:{add:function(b,c,d){var e=a.ui[b].prototype;for(var f in d)e.plugins[f]=e.plugins[f]||[],e.plugins[f].push([c,d[f]])},call:function(a,b,c){var d=a.plugins[b];if(!!d&&!!a.element[0].parentNode)for(var e=0;e0)return!0;b[d]=1,e=b[d]>0,b[d]=0;return e},isOverAxis:function(a,b,c){return a>b&&a=9)&&!b.button)return this._mouseUp(b);if(this._mouseStarted){this._mouseDrag(b);return b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+\".preventClickEvent\",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery);\n/*\n * jQuery UI Resizable 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Resizables\n *\n * Depends:\n *\tjquery.ui.core.js\n *\tjquery.ui.mouse.js\n *\tjquery.ui.widget.js\n */\n(function(a,b){a.widget(\"ui.resizable\",a.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:!1,animate:!1,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:\"e,s,se\",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass(\"ui-resizable\"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||\"ui-resizable-helper\":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")})),this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css(\"resize\"),this.originalElement.css(\"resize\",\"none\"),this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"})),this.originalElement.css({margin:this.originalElement.css(\"margin\")}),this._proportionallyResize()),this.handles=c.handles||(a(\".ui-resizable-handle\",this.element).length?{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"}:\"e,s,se\");if(this.handles.constructor==String){this.handles==\"all\"&&(this.handles=\"n,e,s,w,se,sw,ne,nw\");var d=this.handles.split(\",\");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),\"se\"==f&&h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\"),this.handles[f]=\".ui-resizable-\"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=[\"padding\",/ne|nw|n/.test(c)?\"Top\":/se|sw|s/.test(c)?\"Bottom\":/^e$/.test(c)?\"Right\":\"Left\"].join(\"\");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(\".ui-resizable-handle\",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:\"se\"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass(\"ui-resizable-autohide\").hover(function(){c.disabled||(a(this).removeClass(\"ui-resizable-autohide\"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass(\"ui-resizable-autohide\"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css(\"position\"),width:c.outerWidth(),height:c.outerHeight(),top:c.css(\"top\"),left:c.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(\".ui-draggable\")||/absolute/.test(f.css(\"position\")))&&f.css({position:\"absolute\",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css(\"left\")),h=c(this.helper.css(\"top\"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio==\"number\"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(\".ui-resizable-\"+this.axis).css(\"cursor\");a(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i),f.addClass(\"ui-resizable-resizing\"),this._propagate(\"start\",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate(\"resize\",b),c.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger(\"resize\",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],\"left\")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a(\"body\").css(\"cursor\",\"auto\"),this.element.removeClass(\"ui-resizable-resizing\"),this._propagate(\"stop\",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:\"absolute\",left:this.elementOffset.left-e+\"px\",top:this.elementOffset.top-e+\"px\",zIndex:++c.zIndex}),this.helper.appendTo(\"body\").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!=\"resize\"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:\"1.8.18\"}),a.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data(\"resizable-alsoresize\",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css(\"left\"),10),top:parseInt(b.css(\"top\"),10)})})};typeof e.alsoResize==\"object\"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data(\"resizable-alsoresize\"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?[\"width\",\"height\"]:[\"width\",\"height\",\"top\",\"left\"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize==\"object\"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData(\"resizable-alsoresize\")}}),a.ui.plugin.add(\"resizable\",\"animate\",{stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d._proportionallyResizeElements,g=f.length&&/textarea/i.test(f[0].nodeName),h=g&&a.ui.hasScroll(f[0],\"left\")?0:d.sizeDiff.height,i=g?0:d.sizeDiff.width,j={width:d.size.width-i,height:d.size.height-h},k=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,l=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;d.element.animate(a.extend(j,l&&k?{top:l,left:k}:{}),{duration:e.animateDuration,easing:e.animateEasing,step:function(){var c={width:parseInt(d.element.css(\"width\"),10),height:parseInt(d.element.css(\"height\"),10),top:parseInt(d.element.css(\"top\"),10),left:parseInt(d.element.css(\"left\"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate(\"resize\",b)}})}}),a.ui.plugin.add(\"resizable\",\"containment\",{start:function(b,d){var e=a(this).data(\"resizable\"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a([\"Top\",\"Right\",\"Left\",\"Bottom\"]).each(function(a,b){k[a]=c(j.css(\"padding\"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,\"left\")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css(\"position\"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css(\"position\"));o&&p\n&&(m-=d.parentData.left),m+d.size.width>=d.parentData.width&&(d.size.width=d.parentData.width-m,j&&(d.size.height=d.size.width/d.aspectRatio)),n+d.size.height>=d.parentData.height&&(d.size.height=d.parentData.height-n,j&&(d.size.width=d.size.height*d.aspectRatio))},stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.position,g=d.containerOffset,h=d.containerPosition,i=d.containerElement,j=a(d.helper),k=j.offset(),l=j.outerWidth()-d.sizeDiff.width,m=j.outerHeight()-d.sizeDiff.height;d._helper&&!e.animate&&/relative/.test(i.css(\"position\"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m}),d._helper&&!e.animate&&/static/.test(i.css(\"position\"))&&a(this).css({left:k.left-h.left-g.left,width:l,height:m})}}),a.ui.plugin.add(\"resizable\",\"ghost\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.size;d.ghost=d.originalElement.clone(),d.ghost.css({opacity:.25,display:\"block\",position:\"relative\",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass(\"ui-resizable-ghost\").addClass(typeof e.ghost==\"string\"?e.ghost:\"\"),d.ghost.appendTo(d.helper)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options;d.ghost&&d.ghost.css({position:\"relative\",height:d.size.height,width:d.size.width})},stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options;d.ghost&&d.helper&&d.helper.get(0).removeChild(d.ghost.get(0))}}),a.ui.plugin.add(\"resizable\",\"grid\",{resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.size,g=d.originalSize,h=d.originalPosition,i=d.axis,j=e._aspectRatio||b.shiftKey;e.grid=typeof e.grid==\"number\"?[e.grid,e.grid]:e.grid;var k=Math.round((f.width-g.width)/(e.grid[0]||1))*(e.grid[0]||1),l=Math.round((f.height-g.height)/(e.grid[1]||1))*(e.grid[1]||1);/^(se|s|e)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l):/^(ne)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l):/^(sw)$/.test(i)?(d.size.width=g.width+k,d.size.height=g.height+l,d.position.left=h.left-k):(d.size.width=g.width+k,d.size.height=g.height+l,d.position.top=h.top-l,d.position.left=h.left-k)}});var c=function(a){return parseInt(a,10)||0},d=function(a){return!isNaN(parseInt(a,10))}})(jQuery);\n/*\n * jQuery hashchange event - v1.3 - 7/21/2010\n * http://benalman.com/projects/jquery-hashchange-plugin/\n * \n * Copyright (c) 2010 \"Cowboy\" Ben Alman\n * Dual licensed under the MIT and GPL licenses.\n * http://benalman.com/about/license/\n */\n(function($,e,b){var c=\"hashchange\",h=document,f,g=$.event.special,i=h.documentMode,d=\"on\"+c in e&&(i===b||i>7);function a(j){j=j||location.href;return\"#\"+j.replace(/^[^#]*#?(.*)$/,\"$1\")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,\"\")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$('\n\n\n
\n  
\n
Reference
  
\n
\n
\n
Here is a list of all modules:
\n
[detail level 12]
\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\"\\\"CMSIS-RTOS APIThis section describes the CMSIS-RTOS API
\" \"\"o\"Kernel Information and ControlProvide version/system information and start the RTOS Kernel
\" \"\"o\"Thread ManagementDefine, create, and control thread functions
\" \"\"o\"Generic Wait FunctionsWait for a time period or unspecified events
\" \"\"o\"Timer ManagementCreate and control timer and timer callback functions
\" \"\"o\"Signal ManagementControl or wait for signal flags
\" \"\"o\"Mutex ManagementSynchronize thread execution with a Mutex
\" \"\"o\"Semaphore ManagementControl access to shared resources
\" \"\"o\"Memory Pool ManagementDefine and manage fixed-size memory pools
\" \"\"o\"Message Queue ManagementControl, send, receive, or wait for messages
\" \"\"o\"Mail Queue ManagementControl, send, receive, or wait for mail
\" \"\"o\"Generic Data Types and DefinitionsData Type Definitions used by the CMSIS-RTOS API functions
\" \"\"\\\"Status and Error CodesStatus and Error Codes returned by CMSIS-RTOS API functions
\n\n\n\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/modules.js",
    "content": "var modules =\n[\n    [ \"CMSIS-RTOS API\", \"group___c_m_s_i_s___r_t_o_s.html\", \"group___c_m_s_i_s___r_t_o_s\" ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n  font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 250px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#nav-sync {\n  position:absolute;\n  top:5px;\n  right:24px;\n  z-index:0;\n}\n\n#nav-sync img {\n  opacity:0.3;\n}\n\n#nav-sync img:hover {\n  opacity:0.9;\n}\n\n@media print\n{\n  #nav-tree { display: none; }\n  div.ui-resizable-handle { display: none; position: relative; }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/navtree.js",
    "content": "var NAVTREE =\n[\n  [ \"CMSIS-RTOS\", \"index.html\", [\n    [ \"Overview\", \"index.html\", null ],\n    [ \"Using a CMSIS RTOS Implementation\", \"_using_o_s.html\", null ],\n    [ \"Function Overview\", \"_function_overview.html\", null ],\n    [ \"Header File Template: cmsis_os.h\", \"cmsis_os_h.html\", null ],\n    [ \"Reference\", \"modules.html\", \"modules\" ],\n    [ \"Data Structures\", \"annotated.html\", \"annotated\" ],\n    [ \"Data Structure Index\", \"classes.html\", null ],\n    [ \"Data Fields\", \"functions.html\", [\n      [ \"All\", \"functions.html\", null ],\n      [ \"Variables\", \"functions_vars.html\", null ]\n    ] ]\n  ] ]\n];\n\nvar NAVTREEINDEX =\n[\n\"_function_overview.html\"\n];\n\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar navTreeSubIndices = new Array();\n\nfunction getData(varName)\n{\n  var i = varName.lastIndexOf('/');\n  var n = i>=0 ? varName.substring(i+1) : varName;\n  return eval(n.replace(/\\-/g,'_'));\n}\n\nfunction stripPath(uri)\n{\n  return uri.substring(uri.lastIndexOf('/')+1);\n}\n\nfunction stripPath2(uri)\n{\n  var i = uri.lastIndexOf('/');\n  var s = uri.substring(i+1);\n  var m = uri.substring(0,i+1).match(/\\/d\\w\\/d\\w\\w\\/$/);\n  return m ? uri.substring(i-6) : s;\n}\n\nfunction localStorageSupported()\n{\n  try {\n    return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem;\n  }\n  catch(e) {\n    return false;\n  }\n}\n\n\nfunction storeLink(link)\n{\n  if (!$(\"#nav-sync\").hasClass('sync') && localStorageSupported()) {\n      window.localStorage.setItem('navpath',link);\n  }\n}\n\nfunction deleteLink()\n{\n  if (localStorageSupported()) {\n    window.localStorage.setItem('navpath','');\n  } \n}\n\nfunction cachedLink()\n{\n  if (localStorageSupported()) {\n    return window.localStorage.getItem('navpath');\n  } else {\n    return '';\n  }\n}\n\nfunction getScript(scriptName,func,show)\n{\n  var head = document.getElementsByTagName(\"head\")[0]; \n  var script = document.createElement('script');\n  script.id = scriptName;\n  script.type = 'text/javascript';\n  script.onload = func; \n  script.src = scriptName+'.js'; \n  if ($.browser.msie && $.browser.version<=8) { \n    // script.onload does not work with older versions of IE\n    script.onreadystatechange = function() {\n      if (script.readyState=='complete' || script.readyState=='loaded') { \n        func(); if (show) showRoot(); \n      }\n    }\n  }\n  head.appendChild(script); \n}\n\nfunction createIndent(o,domNode,node,level)\n{\n  var level=-1;\n  var n = node;\n  while (n.parentNode) { level++; n=n.parentNode; }\n  var imgNode = document.createElement(\"img\");\n  imgNode.style.paddingLeft=(16*level).toString()+'px';\n  imgNode.width  = 16;\n  imgNode.height = 22;\n  imgNode.border = 0;\n  if (node.childrenData) {\n    node.plus_img = imgNode;\n    node.expandToggle = document.createElement(\"a\");\n    node.expandToggle.href = \"javascript:void(0)\";\n    node.expandToggle.onclick = function() {\n      if (node.expanded) {\n        $(node.getChildrenUL()).slideUp(\"fast\");\n        node.plus_img.src = node.relpath+\"ftv2pnode.png\";\n        node.expanded = false;\n      } else {\n        expandNode(o, node, false, false);\n      }\n    }\n    node.expandToggle.appendChild(imgNode);\n    domNode.appendChild(node.expandToggle);\n    imgNode.src = node.relpath+\"ftv2pnode.png\";\n  } else {\n    imgNode.src = node.relpath+\"ftv2node.png\";\n    domNode.appendChild(imgNode);\n  } \n}\n\nvar animationInProgress = false;\n\nfunction gotoAnchor(anchor,aname,updateLocation)\n{\n  var pos, docContent = $('#doc-content');\n  if (anchor.parent().attr('class')=='memItemLeft' ||\n      anchor.parent().attr('class')=='fieldtype' ||\n      anchor.parent().is(':header')) \n  {\n    pos = anchor.parent().position().top;\n  } else if (anchor.position()) {\n    pos = anchor.position().top;\n  }\n  if (pos) {\n    var dist = Math.abs(Math.min(\n               pos-docContent.offset().top,\n               docContent[0].scrollHeight-\n               docContent.height()-docContent.scrollTop()));\n    animationInProgress=true;\n    docContent.animate({\n      scrollTop: pos + docContent.scrollTop() - docContent.offset().top\n    },Math.max(50,Math.min(500,dist)),function(){\n      if (updateLocation) window.location.href=aname;\n      animationInProgress=false;\n    });\n  }\n}\n\nfunction newNode(o, po, text, link, childrenData, lastNode)\n{\n  var node = new Object();\n  node.children = Array();\n  node.childrenData = childrenData;\n  node.depth = po.depth + 1;\n  node.relpath = po.relpath;\n  node.isLast = lastNode;\n\n  node.li = document.createElement(\"li\");\n  po.getChildrenUL().appendChild(node.li);\n  node.parentNode = po;\n\n  node.itemDiv = document.createElement(\"div\");\n  node.itemDiv.className = \"item\";\n\n  node.labelSpan = document.createElement(\"span\");\n  node.labelSpan.className = \"label\";\n\n  createIndent(o,node.itemDiv,node,0);\n  node.itemDiv.appendChild(node.labelSpan);\n  node.li.appendChild(node.itemDiv);\n\n  var a = document.createElement(\"a\");\n  node.labelSpan.appendChild(a);\n  node.label = document.createTextNode(text);\n  node.expanded = false;\n  a.appendChild(node.label);\n  if (link) {\n    var url;\n    if (link.substring(0,1)=='^') {\n      url = link.substring(1);\n      link = url;\n    } else {\n      url = node.relpath+link;\n    }\n    a.className = stripPath(link.replace('#',':'));\n    if (link.indexOf('#')!=-1) {\n      var aname = '#'+link.split('#')[1];\n      var srcPage = stripPath($(location).attr('pathname'));\n      var targetPage = stripPath(link.split('#')[0]);\n      a.href = srcPage!=targetPage ? url : \"javascript:void(0)\"; \n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null) \n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) { \n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).show();\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+11) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); // line number\n    hash=''; // strip line number anchors\n    //root=root.replace(/_source\\./,'.'); // source link to doc link\n  }\n  var url=root+hash;\n  var i=-1;\n  while (NAVTREEINDEX[i+1]<=url) i++;\n  if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index\n  if (navTreeSubIndices[i]) {\n    gotoNode(o,i,root,hash,relpath)\n  } else {\n    getScript(relpath+'navtreeindex'+i,function(){\n      navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);\n      if (navTreeSubIndices[i]) {\n        gotoNode(o,i,root,hash,relpath);\n      }\n    },true);\n  }\n}\n\nfunction showSyncOff(n,relpath)\n{\n    n.html('');\n}\n\nfunction showSyncOn(n,relpath)\n{\n    n.html('');\n}\n\nfunction toggleSyncButton(relpath)\n{\n  var navSync = $('#nav-sync');\n  if (navSync.hasClass('sync')) {\n    navSync.removeClass('sync');\n    showSyncOff(navSync,relpath);\n    storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));\n  } else {\n    navSync.addClass('sync');\n    showSyncOn(navSync,relpath);\n    deleteLink();\n  }\n}\n\nfunction initNavTree(toroot,relpath)\n{\n  var o = new Object();\n  o.toroot = toroot;\n  o.node = new Object();\n  o.node.li = document.getElementById(\"nav-tree-contents\");\n  o.node.childrenData = NAVTREE;\n  o.node.children = new Array();\n  o.node.childrenUL = document.createElement(\"ul\");\n  o.node.getChildrenUL = function() { return o.node.childrenUL; };\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  navTo(o,toroot,window.location.hash,relpath);\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n\n  $(window).load(showRoot);\n}\n\n"
  },
  {
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    "content": "\n\n\n\n\nCMSIS-RTOS: Usage and Description\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
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CMSIS-RTOS\n    Version 1.02\n   
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CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
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    "content": "var searchData=\n[\n  ['v',['v',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a9e0a00edabf3b8a5dafff624fff7bbfc',1,'osEvent']]],\n  ['value',['value',['../group___c_m_s_i_s___r_t_o_s___definitions.html#a0b9f8fd3645f01d8cb09cae82add2d7f',1,'osEvent']]]\n];\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osMailQDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
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\n    \n
\n\n\n  
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\n  
\nData Fields  
\n  
\n
osMailQDef_t Struct Reference
  
\n
\n
\n\n
Definition structure for mail queue.  \n More...
\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t queue_sz
 number of elements in the queue  More...
 
uint32_t item_sz
 size of an item  More...
 
void * pool
 memory array for mail  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_mailQ_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t item_sz
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
void* pool
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t queue_sz
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osMailQDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_mail_q_def__t.js",
    "content": "var structos_mail_q_def__t =\n[\n    [ \"item_sz\", \"structos_mail_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f\", null ],\n    [ \"pool\", \"structos_mail_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c\", null ],\n    [ \"queue_sz\", \"structos_mail_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osMessageQDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
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\n  
\nData Fields  
\n  
\n
osMessageQDef_t Struct Reference
  
\n
\n
\n\n
Definition structure for message queue.  \n More...
\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t queue_sz
 number of elements in the queue  More...
 
uint32_t item_sz
 size of an item  More...
 
void * pool
 memory array for messages  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_messageQ_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t item_sz
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
void* pool
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t queue_sz
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osMessageQDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_message_q_def__t.js",
    "content": "var structos_message_q_def__t =\n[\n    [ \"item_sz\", \"structos_message_q_def__t.html#a4c2a0c691de3365c00ecd22d8102811f\", null ],\n    [ \"pool\", \"structos_message_q_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c\", null ],\n    [ \"queue_sz\", \"structos_message_q_def__t.html#a8a83a3a8c0aa8057b13807d2a54077e0\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osMutexDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
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\n  \n
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\n\n
\n\n
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\nData Fields  
\n  
\n
osMutexDef_t Struct Reference
  
\n
\n
\n\n
Mutex Definition structure contains setup information for a mutex.  \n More...
\n\n\n\n\n\n
\nData Fields
uint32_t dummy
 dummy value.  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_mutex_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t dummy
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osMutexDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_mutex_def__t.js",
    "content": "var structos_mutex_def__t =\n[\n    [ \"dummy\", \"structos_mutex_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osPoolDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
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\n  \n
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\n  
\nData Fields  
\n  
\n
osPoolDef_t Struct Reference
  
\n
\n
\n\n
Definition structure for memory block allocation.  \n More...
\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
uint32_t pool_sz
 number of items (elements) in the pool  More...
 
uint32_t item_sz
 size of an item  More...
 
void * pool
 pointer to memory for pool  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_pool_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t item_sz
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
void* pool
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t pool_sz
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osPoolDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_pool_def__t.js",
    "content": "var structos_pool_def__t =\n[\n    [ \"item_sz\", \"structos_pool_def__t.html#a4c2a0c691de3365c00ecd22d8102811f\", null ],\n    [ \"pool\", \"structos_pool_def__t.html#a269c3935f8bc66db70bccdd02cb05e3c\", null ],\n    [ \"pool_sz\", \"structos_pool_def__t.html#ac112e786b2a234e0e45cb5bdbee53763\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osSemaphoreDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
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\n\n
\n  
\nData Fields  
\n  
\n
osSemaphoreDef_t Struct Reference
  
\n
\n
\n\n
Semaphore Definition structure contains setup information for a semaphore.  \n More...
\n\n\n\n\n\n
\nData Fields
uint32_t dummy
 dummy value.  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_semaphore_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t dummy
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osSemaphoreDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_semaphore_def__t.js",
    "content": "var structos_semaphore_def__t =\n[\n    [ \"dummy\", \"structos_semaphore_def__t.html#a44b7a3baf02bac7ad707e8f2f5eca1ca\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osThreadDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
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\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
osThreadDef_t Struct Reference
  
\n
\n
\n\n
Thread Definition structure contains startup information of a thread.  \n More...
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\nData Fields
os_pthread pthread
 start address of thread function  More...
 
osPriority tpriority
 initial thread priority  More...
 
uint32_t instances
 maximum number of instances of that thread function  More...
 
uint32_t stacksize
 stack size requirements in bytes; 0 is default stack size  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_thread_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t instances
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
os_pthread pthread
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
uint32_t stacksize
\n
\n\n
\n
\n\n
\n
\n      \n        \n          \n        \n      
osPriority tpriority
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osThreadDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_thread_def__t.js",
    "content": "var structos_thread_def__t =\n[\n    [ \"instances\", \"structos_thread_def__t.html#aa4c4115851a098c0b87358ab6c025603\", null ],\n    [ \"pthread\", \"structos_thread_def__t.html#ad3c9624ee214329fb34e71f544a6933e\", null ],\n    [ \"stacksize\", \"structos_thread_def__t.html#a950b7f81ad4711959517296e63bc79d1\", null ],\n    [ \"tpriority\", \"structos_thread_def__t.html#a15da8f23c6fe684b70a73646ada685e7\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.html",
    "content": "\n\n\n\n\nCMSIS-RTOS: osTimerDef_t Struct Reference\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-RTOS\n    Version 1.02\n   
\n   
CMSIS-RTOS API: Generic RTOS interface for Cortex-M processor-based devices.
\n  
\n
\n\n
\n    \n
\n\n\n  
\n    \n  
\n  \n
\n
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\n
\n\n
\n\n\n\n\n
\n\n
\n\n
\n  
\nData Fields  
\n  
\n
osTimerDef_t Struct Reference
  
\n
\n
\n\n
Timer Definition structure contains timer parameters.  \n More...
\n\n\n\n\n\n
\nData Fields
os_ptimer ptimer
 start address of a timer function  More...
 
\n
Description
\n
Note
CAN BE CHANGED: os_timer_def is implementation specific in every CMSIS-RTOS. 
\n
Field Documentation
\n\n
\n
\n      \n        \n          \n        \n      
os_ptimer ptimer
\n
\n\n
\n
\n
\n
\n\n
\n  
    \n    
  • osTimerDef_t
    • \n    
  • Generated on Mon Mar 18 2013 13:38:01 for CMSIS-RTOS by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/structos_timer_def__t.js",
    "content": "var structos_timer_def__t =\n[\n    [ \"ptimer\", \"structos_timer_def__t.html#a15773df83aba93f8e61f3737af5fae47\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/RTOS/html/tabs.css",
    "content": ".tabs, .tabs1, .tabs2, .tabs3 {\n    background-image: url('tab_b.png');\n    width: 100%;\n    z-index: 101;\n    font-size: 10px;\n}\n\n.tabs1 {\n    background-image: url('tab_topnav.png');\n    font-size: 12px;\n}\n\n.tabs2 {\n    font-size: 10px;\n}\n.tabs3 {\n    font-size: 9px;\n}\n\n.tablist {\n    margin: 0;\n    padding: 0;\n    display: table;\n    line-height: 24px;\n}\n\n.tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_b.png');\n    list-style: none;\n}\n\n.tabs1 .tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_topnav.png');\n    list-style: none;\n}\n\n.tablist a {\n    display: block;\n    padding: 0 20px;\n    font-weight: bold;\n    background-image:url('tab_s.png');\n    background-repeat:no-repeat;\n    background-position:right;\n    color: #283A5D;\n    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n    text-decoration: none;\n    outline: none;\n}\n\n.tabs3 .tablist a {\n    padding: 0 10px;\n}\n\n.tablist a:hover {\n    background-image: url('tab_h.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n    text-decoration: none;\n}\n\n.tablist li.current a {\n    background-image: url('tab_a.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/CMSIS-SVD_Schema_1_0.xsd",
    "content": "\n\n\n\n  \n  \n    \n      \n    \n  \n\n  \n    \n      \n    \n  \n\n  \n    \n      \n    \n  \n\n  \n    \n      \n    \n  \n\n  \n    \n      \n      \n      \n      \n      \n    \n  \n\n  \n    \n      \n      \n      \n      \n      \n      \n      \n      \n      \n    \n  \n\n  \n    \n      \n      \n      \n      \n    \n  \n\n  \n    \n      \n      \n      \n    \n  \n\n  \n    \n      \n    \n  \n\n  \n    \n      \n      \n      \n        \n          \n            \n            \n          \n        \n      \n    \n  \n\n  \n    \n      \n      \n      \n        \n          \n            \n            \n            \n          \n        \n      \n    \n  \n\n  \n    \n      \n      \n    \n  \n\n  \n    \n      \n      \n      \n      \n    \n  \n\n  \n    \n      \n      \n    \n  \n\n  \n    \n      \n         \n     \n  \n\n  \n    \n      \n      \n      \n    \n  \n\n  \n    \n      \n        \n        \n        \n        \n        \n        \n        \n          \n            \n              \n                \n                  \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                    \n                      \n                        \n                          \n                            \n                              \n                                \n                                 \n                                \n                                \n                                \n                                \n                                \n                                \n                                \n                                \n                                \n                                  \n                                    \n                                      \n                                      \n                                        \n                                          \n                                          \n                                          \n                                            \n                                            \n                                            \n                                          \n                                          \n                                          \n                                          \n                                          \n                                          \n                                            \n                                              \n                                                \n                                                \n                                                \n                                                  \n                                                    \n                                                      \n                                                      \n                                                      \n                                                        \n                                                        \n                                                      \n                                                    \n                                                  \n                                                \n                                              \n                                              \n                                            \n                                          \n                                        \n                                        \n                                      \n                                    \n                                    \n                                  \n                                \n                              \n                              \n                            \n                          \n                        \n                      \n                    \n                  \n                  \n                \n              \n            \n          \n        \n        \n          \n            \n              \n              \n            \n          \n        \n      \n      \n    \n  \n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #2D4068;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n\theight: 28px;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\n\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #354E81;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l\n\n\n\n\nCMSIS-SVD: Cluster Level (New)\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
\n  
\n
\n\n
\n    \n
\n\n  \n
\n
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\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n
\n  
\n
Cluster Level (New)
SVD Extension in Version 1.1
  
\n
\n
\n
Cluster adds a new and optional sub-level to the CMSIS SVD registers level. A cluster describes a sequence of registers within a peripheral. A cluster has an base offset relative to the base address of the peripheral. All registers within a cluster specify their address offset relative to the cluster base address. Register and cluster sections can occur in an arbitrary order. This feature, targeted at the generation of device header files, is useful to create a C data structure within the peripheral structure type, rather than describing all registers of a peripheral in a flat structure.
\n
\n
\n<registers> 
    <cluster derivedFrom=identifierType>\n    \n        <!-- dimElementGroup --> \n        <dim>scaledNonNegativeInteger</dim>\n        <dimIncrement>scaledNonNegativeInteger</dimIncrement>\n        <dimIndex>dimIndexType</dimIndex>\n        <!-- end of dimElementGroup --> \n    \n        <name>identifierType</name>\n        <description>xs:string</description>\n    \n        <headerStructName>identifierType</headerStructName>\n        <alternateCluster>identifierType</alternateCluster>\n    \n        <addressOffset>scaledNonNegativeInteger</addressOffset>
        <register>\n            ...\n        </register>\n    </cluster>\n    ...\n    <register>\n        ...\n    </register>\n    <cluster>\n        ...\n    </cluster>\n     \n<registers> \n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of the cluster from which to inherit the data. Elements being specified underneath will override the inherited values. 
\nRemarks: When deriving a cluster, it is mandatory to specify at least the name, the description, and the addressOffset. 		registerType 0..1  
Element Name Description Type Occurrence  
See dimElementGroup for details.  
dimIncrement The value defines the number of elements in an array of clusters.  scaledNonNegativeInteger  1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring clusters of the cluster array in the address map. scaledNonNegativeInteger  1..1   
dimIndex Specifies the substrings that replaces the [%s] placeholder within the cluster name. By default, the index is a decimal value starting with 0 for the first cluster element.  dimIndexType  0..1   
name String that identifies the cluster. Register names are required to be unique within the scope of a peripheral. Specify [%s] for generating an array in the device header file. identifierType  1..1   
description String describing the details of the register. xs:string  0..1   
alternateCluster  This tag needs to specify the name of the original description of the register sequence if this cluster provides an alternative description. Otherwise the SVDConv will issue errors. identifierType 0..1   
headerStructName  This tag specifies the struct type name in the device header file. If not specified, then the name of the cluster will be used. identifierType 0..1   
addressOffset Value defining the cluster address relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1   
\n
\nExample:
\n
<cluster>
\n
    <dim>4</dim>
\n
        <dimIncrement>8</dimIncrement>
\n
        <dimIndex>0-3</dimIndex>
\n
    <name>TX[%s]</name>
\n
    <description>Grouping of Transfer data and address</description>
\n
    <addressOffset>0x40</addressOffset>
\n
    <register>
\n
            <name>TX_DATA</name>
\n
        ...
\n
            <addressOffset>0x0</addressOffset>
\n
        ...
\n
    </register>
\n
    <register>
\n
            <name>TX_ADDR</name>
\n
        ...
\n
            <addressOffset>0x4</addressOffset>
\n
        ...
\n
    </register>
\n
</cluster>
\n
The example above describes an array of type TX with 4 elements. TX is a cluster of two consecutive registers with 4 elements. The device header file looks like this:
\n
typedef struct {
\n
    ...
\n
    struct {
\n
       __IO uint32_t  TX_DATA;
\n
       __IO uint32_t  TX_ADDR;
\n
    } TX[4];
\n
    ...
\n
} ..._Type;
\n
 
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:02 for CMSIS-SVD by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: CPU Section (New)\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
\n  
\n
\n\n
\n    \n
\n\n  \n
\n
\n  
\n    
\n      
\n    
\n  
\n  
\n  
\n
\n\n
\n
\n  
\n
CPU Section (New)
SVD Extension in Version 1.1
  
\n
\n
\n
The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.
\n
\n<cpu>\n    <name>cpuNameType<name>\n    <revision>revisionType<revision>\n    <endian>endianType<endian>\n    <mpuPresent>xs:boolean<mpuPresent>\n    <fpuPresent>xs:boolean<fpuPresent>\n    <vtorPresent>xs:boolean<vtorPresent>\n    <nvicPrioBits>scaledNonNegativeInteger<nvicPrioBits>\n    <vendorSystickConfig>xs:boolean<vendorSystickConfig>\n</cpu>\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
name The predefined tokens are:
    \n
  • CM0: ARM Cortex-M0
    • \n
  • CM0PLUS: ARM Cortex-M0+
    • \n
  • CM3: ARM Cortex-M3
    • \n
  • CM4: ARM Cortex-M4
    • \n
  • SC000: ARM Secure Core SC000
    • \n
  • SC300: ARM Secure Core SC300
    • \n
  • other: other processor architectures  
    • \n
\n		cpuNameType  1..1   
revisionType  Defines the HW revision of the processor. The defined version format is rNpM (N,M = [0 - 9]).  revisionType 1..1   
endian  Defines the endianess of the processor being one of:
    \n
  • little: little endian memory (least significant byte gets allocated at the lowest address).
    • \n
  • big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
    • \n
  • selectable: little and big endian are configurable for the device and become active after the next reset.
    • \n
  • other: the endianess is neither little nor big endian.  
    • \n
\n		endianType  1..1   
mpuPresent  Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0. boolean  1..1   
fpuPresent  Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0. boolean  1..1   
vtorPresent  This is an optional flag used for the Cortex-M0+ based devices only. It indicates whether the Vector Table Offset Register (VTOR) is implemented in the Cortex-M0+ device or not. This tag is either set to true or false, 1 or 0. If it is not specified VTOR is assumed to be present. boolean  1..1   
nvicPrioBits  Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. scaledNonNegativeInteger  1..1   
vendorSystickConfig Indicates whether the processor implements a vendor-specific System Tick Timer. If false, then the ARM defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0. boolean  1..1   
\n
\nExample:
\n
...
\n
<cpu>
\n
    <name>CM4</name> 
\n
    <revision>r0p0</revision>
\n
    <endian>little</endian>
\n
    <mpuPresent>true</mpuPresent>
\n
    <fpuPresent>true</fpuPresent>
\n
    <nvicPrioBits>4</nvicPrioBits>
\n
    <vendorSystickConfig>false</vendorSystickConfig> 
\n
</cpu>  
\n
...
\n
This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. 
\n
\n
\n\n
\n  
    \n    
  • Generated on Mon Mar 18 2013 13:38:02 for CMSIS-SVD by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__device_section_extensions__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Extensions to the Device Section\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
\n  
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\n
Extensions to the Device Section
SVD Extension in Version 1.1
  
\n
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\n
A number of elements have been added to the device section. These elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.
\n
\n<device schemaVersion=\"xs:decimal\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD_Schema_1_1.xsd\">\n    <vendor>stringType</vendor>\n    <vendorID>stringType</vendorID>\n    <name>identifierType</name>\n    <series>stringType</series>\n    <version>xs:string</version>\n    <description>xs:string</description>\n    <licenseText>xs:string</licenseText>\n    <cpu>cpuType</cpu>\n    <headerSystemFilename>identifierType</headerSystemFilename>\n    <headerDefinitionsPrefix>identifierType</headerDefinitionsPrefix>\n\n    ...\n</device>\n\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
vendor This specifies the vendor of the device using the full name. stringType  0..1   
vendorID This specifies the vendor of the device using the vendor abbreviation that does not contain any spaces or special characters. This information shall be used for defining the directory. stringType  0..1   
series This element specifies the name of the device series. stringType  0..1   
licenseText The content of this tag will be copied into the header section of the generated device header file and shall contain the legal disclaimer. New lines can be inserted by using \"\\n\". This section is mandatory if the SVD file shall be used for generating the device header file. stringType  0..1    
headerSystemFilename This tag specifies the file name (without extension) of the device-specific system include file (system_<device>.h; See CMSIS-Core description). This tag is used by the header file generator for customizing the include statement referencing the CMSIS system file within the CMSIS device header file. By default, the filename is \"<kbd>system_<i>device:name</i>.h\". In cases where a device series shares a single system header file, the name of the series shall be used instead of the individual device name. identifierType  0..1   
headerDefinitionsPrefix The element specifies the string being prepended to all type definition names generated in the CMSIS-Core device header file. This is used if the silicon vendor's software requires vendor-specific types in order to avoid name clashes with other definied types. identifierType  0..1   
\n
\nExample:
\n
...
\n
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
\n
    <vendor>Advanced RISC Machines</vendor>
\n
    <vendorID>ARM</vendorID>
\n
    ...
\n
    <series>ARMCM3</series>
\n
    ...
\n
    <licenseText>
\n
    ARM Limited (ARM) is supplying this software for use with Cortex-M \\n
\n
    processor based microcontrollers.  This file can be freely distributed \\n
\n
    within development tools that are supporting such ARM based processors. \\n
\n
    \\n
\n
    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED \\n
\n
    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \\n
\n
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \\n
\n
    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \\n
\n
    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\n
    </licenseText>
\n
    ...
\n
    <headerSystemFilename>system_ARMCM4</headeSystemFilename>
\n
    <headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix>
\n
    ...
\n
</device>       
\n
...
\n
This example describes a device from the vendor Advanced RISC Machines using ARM as short name. The device belongs to the device family identified by ARMCM4. The legal disclaimer in the header files generated from this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the generated device header file is named system_ARMCM4.h and all type definitions will be prepended with ARM_. 
\n
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    \n    
  • Generated on Mon Mar 18 2013 13:38:02 for CMSIS-SVD by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__dim_element_group__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: dimElementGroup\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
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dimElementGroup
Element Groups
  
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\n
The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index-specific substring defined in <dimIndex>. The <dimIncrement> specifies the address offset between two registers. The elements below can be used to generate an array of registers.
\n\n\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
dim The value defines the number of elements in an array of registers. scaledNonNegativeInteger 1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger 1..1   
dimIndex Specifies the substrings that replaces the %s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register. dimIndexType 0..1   
\n
\nExamples:
\n
...
\n
<register>
\n
    <dim>6</dim> 
\n
    <dimIncrement>4</dimIncrement> 
\n
    <dimIndex>A,B,C,D,E,Z</dimIndex> 
\n
    <name>GPIO_%s_CTRL</name> 
\n
...
\n
</register>
\n
The code above generates: => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL
\n
...
\n
<register>
\n
    <dim>4</dim> 
\n
    <dimIncrement>4</dimIncrement> 
\n
    <dimIndex>3-6</dimIndex> 
\n
    <name>IRQ%s</name> 
\n
...
\n
</register>
\n
The example above generates: => IRQ3, IRQ4, IRQ5, IRQ6 
\n
\n
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    \n    
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    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Element Groups\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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Element Groups
  
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\nContent
 dimElementGroup
 
 registerPropertiesGroup
 
\n
Description
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  • Generated on Mon Mar 18 2013 13:38:02 for CMSIS-SVD by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
\n
\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__elem__type__gr.js",
    "content": "var group__elem__type__gr =\n[\n    [ \"dimElementGroup\", \"group__dim_element_group__gr.html\", null ],\n    [ \"registerPropertiesGroup\", \"group__register_properties_group__gr.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__peripheral_section_extensions__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Extensions to the Peripheral Section\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
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Extensions to the Peripheral Section
SVD Extension in Version 1.1
  
\n
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\n
The following elements have been added to the peripheral section. All new elements are optional but are highly recommended to enable the generation of consistent and CMSIS-compliant device header files from SVD descriptions.
\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
alternatePeripheral All address blocks in the memory space of a device are assigned to a unique peripheral by default. If there are multiple peripherals describing the same address blocks, this needs to be specified explicitly. A peripheral redefining an address block needs to specify the name of the peripheral that is listed first in the description. If no alternate peripheral is specified, then the SVDConv utility will generate errors. identifierType  0..1   
headerStructName The header file generator uses the name of a peripheral as the base name for the C structure type. If this element is specfied, then this string is used instead of the peripheral name. This is particularly useful when multiple peripherals get derived from a peripheral description and a generic type name shall be used. identifierType  0..1   
\n
\nExample:
\n
<peripheral>
\n
  <name>Timer1</name>
\n
  <version>1.0</version>
\n
  <description>Timer 1 is a standard timer ... </description>
\n
  <baseAddress>0x40002000</baseAddress>
\n
  ...
\n
</peripheral>
\n
<peripheral>
\n
  <name>Timer1_Alt</name>
\n
  <version>1.0</version>
\n
  <description>Alternate Timer 1 is a special timer execution mode ... </description>
\n
  <baseAddress>0x40002000</baseAddress>
\n
  <alternatePeripheral>Timer1</alternatePeripheral>
\n
  ...
\n
</peripheral>
\n
Two timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals. 
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__register_properties_group__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: registerPropertiesGroup\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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registerPropertiesGroup
Element Groups
  
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Register properties can be set on device, peripheral, and register level. Element values defined on a lower level overwrite element values defined on a more general level. For example, the register-level.<size> will overwrite peripheral-level.<size>. Elements that have not been defined on a more general level, must be defined at register level at the latest.
\n\n\n\n\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
size Defines the default bit-width of any register contained in the device (implicit inheritance). This element can be redefined on any lower level of the description using the size element there.  scaledNonNegativeInteger  0..1   
access  Defines the default access rights for all registers. Access rights can be redefined on any lower level of the description using the access element there. 
\n 
\n The predefined tokens are:
    \n
  • read-only: read access is permitted. Write operations have an undefined result.
    • \n
  • write-only: write access is permitted. Read operations have an undefined result.
    • \n
  • read-write: both read and write accesses are permitted. Writes affect the state of the register and reads return a value related to the register.
    • \n
  • writeOnce: only the first write after reset has an effect on the register. Read operations deliver undefined results.
    • \n
  • read-writeOnce: Read operations deliver a result related to the register content. Only the first write access to this register after a reset will have an effect on the register content.  
    • \n
\n		accessType 0..1   
resetValue  Defines the default value for all registers at RESET. The default register value can be redefined on any lower level using the resetValue element there. The actual reset value is calculated from the resetValue and the resetMask. The mask is used to specify bits with an undefined reset value. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. These bit positions are set to one. Bit positions with an undefined reset value are set to zero. scaledNonNegativeInteger 0..1   
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    • \n  
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__register_section_extensions__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Extensions to the Register Section\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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Extensions to the Register Section
SVD Extension in Version 1.1
  
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The following elements have been added to the register section. All new elements are optional.
\n\n\n\n\n\n\n\n
Element Name Description Type Occurrence  
alternateRegister This tag can reference a register that has been defined above to current location in the description and that describes the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is intentional. The register name needs to be unique within the scope of the current peripheral. A register description is defined either for a unique address location or could be a redefinition of an already described address. In the latter case, the register can be either marked alternateRegister and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through the tag alternateGroup (specified in version 1.0). identifierType  0..1   
dataType It can be useful to assign a specific native C datatype to a register. This helps avoiding type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then dataType can be set to \"uint32_t *\". The following simple data types are predefined:
    \n
  • uint8_t: unsigned byte
    • \n
  • uint16_t: unsigned half word
    • \n
  • uint32_t: unsigned word
    • \n
  • uint64_t: unsigned double word
    • \n
  • int8_t: signed byte
    • \n
  • int16_t: signed half word
    • \n
  • int32_t: signed world
    • \n
  • int64_t: signed double word
    • \n
  • uint8_t *: pointer to unsigned byte
    • \n
  • uint16_t *: pointer to unsigned half word
    • \n
  • uint32_t *: pointer to unsigned word
    • \n
  • uint64_t *: pointer to unsigned double word
    • \n
  • int8_t *: pointer to signed byte
    • \n
  • int16_t *: pointer to signed half word
    • \n
  • int32_t *: pointer to signed world
    • \n
  • int64_t *: pointer to signed double word 
    • \n
\n		dataTypeType  0..1   
\n
\nExample:
\n
...
\n
<register>
\n
    <name>TIM_MODEA</name>
\n
    <description>In mode A this register acts as a reload value</description>
\n
    <addressOffset>0xC</addressOffset>
\n
</register>
\n
<register>
\n
    <name>TIM_MODEB</name>
\n
    <description>In mode B this register acts as the compare value</description>
\n
    <alternateRegister>TIM_MODEA</alternateRegister>
\n
    <addressOffset>0xC</addressOffset>
\n
</register>     
\n
<register>
\n
    <name>DMA_DATA</name>
\n
    <description>This register contains the address of the data being transferred</description>
\n
    <dataType>uint32_t *</dataType>
\n
    <addressOffset>0xf0</addressOffset>
\n
</register>     
\n
...
\n
This example describes two registers, TIM_MODEA and TIM_MODEB. Both have the same address offset. Based on the configured operation model being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. The code generated for the device header file is:
\n
typedef struct {
\n
  union {
\n
    __IO   uint32_t TIM_MODEA;
\n
    __IO   uint32_t TIM_MODEB;
\n
        };
\n
  __IO uint32_t * DMA_DATA; 
\n
  ...
\n
} <peripheral:name>_Type;
\n
 
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  • Generated on Mon Mar 18 2013 13:38:02 for CMSIS-SVD by ARM Ltd. All rights reserved.\n\t\n\t
    • \n  
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\n\n\n"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__schema__1__1__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: CMSIS-SVD Schema File Ver. 1.1 (draft)\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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CMSIS-SVD Schema File Ver. 1.1 (draft)
  
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<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!-- \n  date: 04.07.2012\n\n  Copyright (C) 2011 - 2012 ARM Limited. All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used \n     to endorse or promote products derived from this software without \n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n\n  This is CMSIS-SVD version 1.1\n  For backward compatibility all additional tags have been made optional.\n  Extensions may be mandatory for successful device header file generation\n  Other changes are related to some restructuring of the schema.\n  \n  Note that the memory section has been removed since this would limit the\n  reuse of descriptions for a series of devices.\n -->\n\n<xs:schema xmlns:xs=\"http://www.w3.org/2001/XMLSchema\" elementFormDefault=\"qualified\" attributeFormDefault=\"qualified\" version=\"1.1\">\n  <!-- stringType requires a none empty string of a least one character length -->\n  <xs:simpleType name=\"stringType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:minLength value=\"1\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->\n  <xs:simpleType name=\"cpuNameType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"CM0\"/>\n      <xs:enumeration value=\"CM0PLUS\"/>\n      <xs:enumeration value=\"CM0+\"/>\n      <xs:enumeration value=\"SC000\"/>\n      <xs:enumeration value=\"CM3\"/>\n      <xs:enumeration value=\"SC300\"/>\n      <xs:enumeration value=\"CM4\"/>\n      <xs:enumeration value=\"other\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->\n  <xs:simpleType name=\"revisionType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"r[0-9]p[0-9]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->\n  <xs:simpleType name=\"endianType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"little\"/>\n      <xs:enumeration value=\"big\"/>\n      <xs:enumeration value=\"selectable\"/>\n      <xs:enumeration value=\"other\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->\n  <xs:simpleType name=\"dataTypeType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"uint8_t\"/>\n      <xs:enumeration value=\"uint16_t\"/>\n      <xs:enumeration value=\"uint32_t\"/>\n      <xs:enumeration value=\"uint64_t\"/>\n      <xs:enumeration value=\"int8_t\"/>\n      <xs:enumeration value=\"int16_t\"/>\n      <xs:enumeration value=\"int32_t\"/>\n      <xs:enumeration value=\"int64_t\"/>\n      <xs:enumeration value=\"uint8_t *\"/>\n      <xs:enumeration value=\"uint16_t *\"/>\n      <xs:enumeration value=\"uint32_t *\"/>\n      <xs:enumeration value=\"uint64_t *\"/>\n      <xs:enumeration value=\"int8_t *\"/>\n      <xs:enumeration value=\"int16_t *\"/>\n      <xs:enumeration value=\"int32_t *\"/>\n      <xs:enumeration value=\"int64_t *\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- nvicPrioBitsType specifies the integer value range for the number of bits used in NVIC to encode priority levels -->\n  <xs:simpleType name=\"nvicPrioBitsType\">\n    <xs:restriction base=\"xs:integer\">\n      <xs:minInclusive value=\"2\"/>\n      <xs:maxInclusive value=\"8\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers within the description. -->\n  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->\n  <xs:simpleType name=\"identifierType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\\[%s\\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- enumerationNameType specifies the subset and sequence of characters used for specifying names of enumeratedValues. -->\n  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->\n  <xs:simpleType name=\"enumerationNameType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[_A-Za-z0-9]*\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->\n  <xs:simpleType name=\"dimIndexType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[0-9]+\\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\\s*[_0-9a-zA-Z]+)+\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimar format -->\n  <xs:simpleType name=\"scaledNonNegativeInteger\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->\n  <xs:simpleType name=\"enumeratedValueDataType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(0x|0X|#)?[0-9a-fxA-FX]+\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- accessType specfies the pre-defined tokens for the available accesses -->\n  <xs:simpleType name=\"accessType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read-only\"/>\n      <xs:enumeration value=\"write-only\"/>\n      <xs:enumeration value=\"read-write\"/>\n      <xs:enumeration value=\"writeOnce\"/>\n      <xs:enumeration value=\"read-writeOnce\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->\n  <xs:simpleType name=\"modifiedWriteValuesType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"oneToClear\"/>\n      <xs:enumeration value=\"oneToSet\"/>\n      <xs:enumeration value=\"oneToToggle\"/>\n      <xs:enumeration value=\"zeroToClear\"/>\n      <xs:enumeration value=\"zeroToSet\"/>\n      <xs:enumeration value=\"zeroToToggle\"/>\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- readAction type specifies the pre-defined tokens for read side effects -->\n  <xs:simpleType name=\"readActionType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n      <xs:enumeration value=\"modifyExternal\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->\n  <xs:simpleType name=\"enumUsageType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read\"/>\n      <xs:enumeration value=\"write\"/>\n      <xs:enumeration value=\"read-write\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->\n  <xs:simpleType name=\"bitRangeType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:pattern value=\"\\[([0-4])?[0-9]:([0-4])?[0-9]\\]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->\n  <xs:complexType name=\"writeConstraintType\">\n    <xs:choice>\n      <xs:element name=\"writeAsRead\" type=\"xs:boolean\"/>\n      <xs:element name=\"useEnumeratedValues\" type=\"xs:boolean\"/>\n      <xs:element name=\"range\">\n        <xs:complexType>\n          <xs:sequence>\n            <xs:element name=\"minimum\" type=\"scaledNonNegativeInteger\"/>\n            <xs:element name=\"maximum\" type=\"scaledNonNegativeInteger\"/>\n          </xs:sequence>\n        </xs:complexType>\n      </xs:element>\n    </xs:choice>\n  </xs:complexType>\n  <!-- addressBlockType specifies the elements to describe an address block -->\n  <xs:complexType name=\"addressBlockType\">\n    <xs:sequence>\n      <xs:element name=\"offset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"usage\">\n        <xs:simpleType>\n          <xs:restriction base=\"xs:token\">\n            <xs:enumeration value=\"registers\"/>\n            <xs:enumeration value=\"buffer\"/>\n            <xs:enumeration value=\"reserved\"/>\n          </xs:restriction>\n        </xs:simpleType>\n      </xs:element>\n    </xs:sequence>\n  </xs:complexType>\n  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->\n  <xs:complexType name=\"interruptType\">\n    <xs:sequence>\n      <xs:element name=\"name\" type=\"stringType\"/>\n      <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n      <xs:element name=\"value\" type=\"xs:integer\"/>\n    </xs:sequence>\n  </xs:complexType>\n  <!-- register properties group specifies register size, access permission and reset value \n       this is used in multiple locations. Settings are inherited downstream. -->  \n  <xs:group name=\"registerPropertiesGroup\">\n    <xs:sequence>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n      <xs:element name=\"resetValue\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"resetMask\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register \n       by specifying the least significant and the most significant bit position -->\n  <xs:group name=\"bitRangeLsbMsbStyle\">\n    <xs:sequence>\n      <xs:element name=\"lsb\"  type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"msb\"  type=\"scaledNonNegativeInteger\"/>\n    </xs:sequence>\n  </xs:group>\n  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register\n       by specifying the least significant bit position and the bitWidth of the field -->\n  <xs:group name=\"bitRangeOffsetWidthStyle\">\n    <xs:sequence>\n      <xs:element name=\"bitOffset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"bitWidth\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>   \n    </xs:sequence> \n  </xs:group>\n  <!-- dimElementGroup specifies the number of array elements (dim), the address offset\n       between to consecutive array elements and an a comma seperated list of strings \n       being used for identifying each element in the array -->\n  <xs:group name=\"dimElementGroup\">\n    <xs:sequence>\n      <xs:element name=\"dim\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIncrement\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIndex\" type=\"dimIndexType\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <xs:complexType name=\"cpuType\">\n    <xs:sequence>\n      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->\n      <xs:element name=\"name\" type=\"cpuNameType\"/>\n      <!-- V1.1: ARM defined revision of the cpu -->\n      <xs:element name=\"revision\" type=\"revisionType\"/>\n      <!-- V1.1: Endian specifies the endianess of the processor/device -->\n      <xs:element name=\"endian\" type=\"endianType\"/>\n      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->\n      <xs:element name=\"mpuPresent\" type=\"xs:boolean\"/>\n      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->\n      <xs:element name=\"fpuPresent\" type=\"xs:boolean\"/>\n      <!-- V1.1: vtorPresent is used for Cortex-M0+ based devices only. It indicates whether the Vector Table Offset\n                 Register is implemented in the device or not -->\t\t\t\t   \n      <xs:element name=\"vtorPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller\n                 for defining the priority level = # priority levels -->\n      <xs:element name=\"nvicPrioBits\" type=\"scaledNonNegativeInteger\"/>\n      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device \n                   instead of the ARM specified SysTickTimer -->\n      <xs:element name=\"vendorSystickConfig\" type=\"xs:boolean\"/>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"enumeratedValuesType\">\n    <xs:sequence>\n      <!-- name specfies a reference to this enumeratedValues section for reuse purposes\n           this name does not appear in the System Viewer nor the Header File. -->\n      <xs:element name=\"name\" type=\"enumerationNameType\" minOccurs=\"0\"/>\n      <!-- usage specifies whether this enumeration is to be used for read or write or \n                                                       (read and write) accesses -->\n      <xs:element name=\"usage\" type=\"enumUsageType\" minOccurs=\"0\"/>\n      <!-- enumeratedValue derivedFrom=<identifierType> -->\n      <xs:element name=\"enumeratedValue\" minOccurs=\"1\" maxOccurs=\"unbounded\">\n        <xs:complexType>\n          <xs:sequence>\n            <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->\n            <xs:element name=\"name\" type=\"enumerationNameType\"/>\n            <!-- description contains the details about the semantics/behavior specified by this value -->\n            <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n            <xs:choice>\n              <xs:element name=\"value\" type=\"enumeratedValueDataType\"/>\n              <!-- isDefault specifies the name and description for all values that are not\n                   specifically described individually -->\n              <xs:element name=\"isDefault\" type=\"xs:boolean\"/>\n            </xs:choice>\n          </xs:sequence>\n        </xs:complexType>\n      </xs:element>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"enumerationNameType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <xs:complexType name=\"fieldType\">\n    <xs:sequence>\n      <!-- name specifies a field's name. The System Viewer and the device header file will\n           use the name of the field as identifier -->\n      <xs:element name=\"name\" type=\"identifierType\"/>\n      <!-- description contains reference manual level information about the function and \n           options of a field -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- alternative specifications of the bit position of the field within the register -->\n      <xs:choice minOccurs=\"1\" maxOccurs=\"1\">\n        <!-- bit field described by lsb followed by msb tag -->\n        <xs:group ref=\"bitRangeLsbMsbStyle\"/>\n        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->\n        <xs:group ref=\"bitRangeOffsetWidthStyle\"/>\n        <!-- bit field described by [<msb>:<lsb>] -->\n        <xs:element name=\"bitRange\" type=\"bitRangeType\"/>\n      </xs:choice>\n      <!-- access describes the predefined permissions for the field. -->\n      <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n      <!-- predefined description of write side effects -->\n      <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n      <!-- writeContstraint specifies the subrange of allowed values -->\n      <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n      <!-- readAction specifies the read side effects. -->\n      <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n      <!-- enumeratedValues derivedFrom=<identifierType> -->\n      <xs:element name=\"enumeratedValues\" type=\"enumeratedValuesType\" minOccurs=\"0\" maxOccurs=\"2\">\n      </xs:element>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"identifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <xs:complexType name=\"fieldsType\">\n    <xs:sequence>\n      <!-- field derivedFrom=<identifierType> -->\n      <xs:element name=\"field\" type=\"fieldType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"registerType\">\n    <xs:sequence>\n      <xs:group    ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <!-- name specifies the name of the register. The register name is used by System Viewer and\n                                     device header file generator to represent a register -->\n      <xs:element name=\"name\" type=\"identifierType\"/>\n      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.\n                                     The use of this tag is discouraged because it does not allow consistency between\n                                     the System View and the device header file. -->\n      <xs:element name=\"displayName\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- description contains a reference manual level description about the register and it's purpose -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <xs:choice>\n        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.\n                                       This is useful if a register has a different description per mode but a single name -->\n        <xs:element name=\"alternateGroup\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is\n                                       already fully described. In this case the register name must be unique within the peripheral -->\n        <xs:element name=\"alternateRegister\" type=\"identifierType\" minOccurs=\"0\"/>\n      </xs:choice>\n      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->\n      <xs:element name=\"addressOffset\" type=\"scaledNonNegativeInteger\"/>\n      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n                                     reset value. These default values are inherited to all fields contained in this register -->\n      <xs:group    ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->\n      <xs:element name=\"dataType\" type=\"dataTypeType\" minOccurs=\"0\"/>\n      <!-- modifiedWriteValues specifies the write side effects -->\n      <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n      <!-- writeConstraint specifies the subset of allowed write values -->\n      <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n      <!-- readAcction specifies the read side effects -->\n      <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n      <!-- fields section contains all fields that belong to this register -->\n      <xs:element name=\"fields\" type=\"fieldsType\" minOccurs=\"0\" maxOccurs=\"1\"/>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"identifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->\n  <xs:complexType name=\"clusterType\">\n    <xs:sequence>\n      <xs:group   ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <xs:element name=\"name\" type=\"identifierType\"/>\n      <xs:element name=\"description\" type=\"xs:string\"/>\n      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is\n                 already fully described. In this case the cluster name must be unique within the peripheral -->\n      <xs:element name=\"alternateCluster\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef\n                 used in the device header generation instead of the cluster name -->\n      <xs:element name=\"headerStructName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <xs:element name=\"addressOffset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"register\" type=\"registerType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"identifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <!-- the registers section can have an arbitrary list of cluster and register sections -->\n  <xs:complexType name=\"registersType\">\n    <xs:choice minOccurs=\"1\" maxOccurs=\"unbounded\">\n      <xs:element name=\"cluster\" type=\"clusterType\"/>\n      <xs:element name=\"register\" type=\"registerType\"/>\n    </xs:choice>\n  </xs:complexType>\n\n  <xs:complexType name=\"peripheralType\">\n    <xs:sequence>\n      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->\n      <xs:element name=\"name\" type=\"xs:Name\"/>\n      <!-- version specifies the version of the peripheral descriptions -->\n      <xs:element name=\"version\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- description provides a high level functional description of the peripheral -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is\n           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->\n      <xs:element name=\"alternatePeripheral\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->\n      <xs:element name=\"groupName\" type=\"xs:Name\" minOccurs=\"0\"/>\n      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. \n                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->\n      <xs:element name=\"prependToName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header \n                         file will sho the registers in a C-Struct of the peripheral without the postfix -->\n      <xs:element name=\"appendToName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef\n                         used in the device header generation instead of the peripheral name -->\n      <xs:element name=\"headerStructName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- disableCondition contains a logical expression based on constants and register or bit-field values \n                         if the condition is evaluated to true, the peripheral display will be disabled -->\n      <xs:element name=\"disableCondition\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory\n                         to specify a baseAddress. -->\n      <xs:element name=\"baseAddress\" type=\"scaledNonNegativeInteger\"/>\n      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n                         reset value. These default values are inherited to all registers contained in this peripheral -->\n      <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. \n                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify\n                         at least one address block -->\n      <xs:element name=\"addressBlock\" type=\"addressBlockType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->\n      <xs:element name=\"interrupt\" type=\"interruptType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does\n                        not have its own registers section, hence this section is optional. A unique peripheral without a \n                        registers section is not allowed -->\n      <xs:element name=\"registers\" type=\"registersType\" minOccurs=\"0\" maxOccurs=\"1\">\n      </xs:element>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"identifierType\" use=\"optional\"/>\n  </xs:complexType>\n  \n  <!-- ==================================================== -->\n  <!-- The top level element of a description is the device -->\n  <!-- ==================================================== -->\n  <xs:element name=\"device\" nillable=\"true\">\n    <xs:complexType>\n      <xs:sequence>\n        <!-- V1.1: Vendor Name -->\n        <xs:element name=\"vendor\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->\n        <xs:element name=\"vendorID\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- name specifies the device name being described -->\n        <xs:element name=\"name\" type=\"identifierType\"/>\n        <!-- V1.1: series specifies the device series or family name -->\n        <xs:element name=\"series\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- version specifies the version of the device description -->\n        <xs:element name=\"version\" type=\"stringType\"/>\n        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->\n        <xs:element name=\"description\" type=\"stringType\"/>\n        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->\n        <xs:element name=\"licenseText\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- V1.1: cpu specifies the details of the processor included in the device -->\n        <xs:element name=\"cpu\" type=\"cpuType\" minOccurs=\"0\"/>\n        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.\n             This tag is used by the header file generator for customizing the include statement referencing the\n             CMSIS system file within the CMSIS device header file. By default the filename is \"system_<device.name>\"\n             In cases a device series shares a single system header file, the name of the series shall be used \n             instead of the individual device name. -->\n        <xs:element name=\"headerSystemFilename\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in\n             generated device header file -->\n        <xs:element name=\"headerDefinitionsPrefix\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->\n        <xs:element name=\"addressUnitBits\" type=\"scaledNonNegativeInteger\"/>\n        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.\n             This sets the maximum size of a single register that can be defined for an address space -->\n        <xs:element name=\"width\" type=\"scaledNonNegativeInteger\"/>\n        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n             reset value -->\n        <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n\n        <!-- peripherals is containing all peripherals -->\n        <xs:element name=\"peripherals\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:element name=\"peripheral\" type=\"peripheralType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n\n        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->\n        <xs:element name=\"vendorExtensions\" minOccurs=\"0\" maxOccurs=\"1\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:any namespace=\"##any\" processContents=\"lax\" minOccurs=\"0\" maxOccurs=\"unbounded\">\n              </xs:any>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n      </xs:sequence>\n      <xs:attribute name=\"schemaVersion\" type=\"xs:decimal\" use=\"required\" fixed=\"1.1\"/>\n    </xs:complexType>\n  </xs:element>\n</xs:schema>\n
 
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    "path": "Libraries/CMSIS/Documentation/SVD/html/group__schema__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: CMSIS-SVD Schema File Ver. 1.0\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-SVD Schema File Ver. 1.0
  
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<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!-- \n  date: 07.12.2011\n  \n  Copyright (C) 2011 - 2012 ARM Limited. All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used \n     to endorse or promote products derived from this software without \n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<xs:schema xmlns:xs=\"http://www.w3.org/2001/XMLSchema\" elementFormDefault=\"qualified\" attributeFormDefault=\"qualified\" version=\"1.0\">\n  \n  <xs:simpleType name=\"registerNameType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"((%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\\[%s\\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"dimIndexType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[0-9]+\\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\\s*[_0-9a-zA-Z]+)+\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"scaledNonNegativeInteger\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"enumeratedValueDataType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(0x|0X|#)?[0-9a-fxA-FX]+\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"accessType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read-only\"/>\n      <xs:enumeration value=\"write-only\"/>\n      <xs:enumeration value=\"read-write\"/>\n      <xs:enumeration value=\"writeOnce\"/>\n      <xs:enumeration value=\"read-writeOnce\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"modifiedWriteValuesType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"oneToClear\"/>\n      <xs:enumeration value=\"oneToSet\"/>\n      <xs:enumeration value=\"oneToToggle\"/>\n      <xs:enumeration value=\"zeroToClear\"/>\n      <xs:enumeration value=\"zeroToSet\"/>\n      <xs:enumeration value=\"zeroToToggle\"/>\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"readActionType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n      <xs:enumeration value=\"modifyExternal\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"enumUsageType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read\"/>\n      <xs:enumeration value=\"write\"/>\n      <xs:enumeration value=\"read-write\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"bitRangeType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:pattern value=\"\\[([0-3])?[0-9]:([0-3])?[0-9]\\]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:complexType name=\"writeConstraintType\">\n    <xs:choice>\n      <xs:element name=\"writeAsRead\" type=\"xs:boolean\"/>\n      <xs:element name=\"useEnumeratedValues\" type=\"xs:boolean\"/>\n      <xs:element name=\"range\">\n        <xs:complexType>\n          <xs:sequence>\n            <xs:element name=\"minimum\" type=\"scaledNonNegativeInteger\"/>\n            <xs:element name=\"maximum\" type=\"scaledNonNegativeInteger\"/>\n          </xs:sequence>\n        </xs:complexType>\n      </xs:element>\n    </xs:choice>\n  </xs:complexType>\n\n  <xs:complexType name=\"addressBlockType\">\n    <xs:sequence>\n      <xs:element name=\"offset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"usage\">\n        <xs:simpleType>\n          <xs:restriction base=\"xs:token\">\n            <xs:enumeration value=\"registers\"/>\n            <xs:enumeration value=\"buffer\"/>\n            <xs:enumeration value=\"reserved\"/>\n          </xs:restriction>\n        </xs:simpleType>\n      </xs:element>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"interruptType\">\n    <xs:sequence>\n      <xs:element name=\"name\" type=\"xs:string\"/>\n      <xs:element name=\"value\" type=\"xs:integer\"/>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:group name=\"registerPropertiesGroup\">\n    <xs:sequence>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n      <xs:element name=\"resetValue\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"resetMask\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <xs:group name=\"bitRangeLsbMsbStyle\">\n    <xs:sequence>\n      <xs:element name=\"lsb\"  type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"msb\"  type=\"scaledNonNegativeInteger\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <xs:group name=\"bitRangeOffsetWidthStyle\">\n    <xs:sequence>\n      <xs:element name=\"bitOffset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"bitWidth\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>   \n    </xs:sequence> \n  </xs:group>\n\n  <xs:group name=\"dimElementGroup\">\n    <xs:sequence>\n      <xs:element name=\"dim\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIncrement\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIndex\" type=\"dimIndexType\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <xs:element name=\"device\" nillable=\"true\">\n    <xs:complexType>\n      <xs:sequence>\n        <xs:element name=\"name\" type=\"xs:string\"/>\n        <xs:element name=\"version\" type=\"xs:string\"/>\n        <xs:element name=\"description\" type=\"xs:string\"/>\n        <xs:element name=\"addressUnitBits\" type=\"scaledNonNegativeInteger\"/>\n        <xs:element name=\"width\" type=\"scaledNonNegativeInteger\"/>\n        <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n        <xs:element name=\"peripherals\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:element name=\"peripheral\" minOccurs=\"1\" maxOccurs=\"unbounded\">\n                <xs:complexType>\n                  <xs:sequence>\n                    <xs:element name=\"name\" type=\"xs:Name\"/>\n                    <xs:element name=\"version\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"groupName\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"prependToName\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"appendToName\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"disableCondition\" type=\"xs:string\" minOccurs=\"0\"/>\n                    <xs:element name=\"baseAddress\" type=\"scaledNonNegativeInteger\"/>\n                    <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n                    <xs:element name=\"addressBlock\" type=\"addressBlockType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n                    <xs:element name=\"interrupt\" type=\"interruptType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n                    <xs:element name=\"registers\" minOccurs=\"0\" maxOccurs=\"1\">\n                      <xs:complexType>\n                        <xs:sequence>\n                          <xs:element name=\"register\" minOccurs=\"1\" maxOccurs=\"unbounded\">\n                            <xs:complexType>\n                              <xs:sequence>\n                                <xs:group ref=\"dimElementGroup\" minOccurs=\"0\"/>\n                                <xs:element name=\"name\" type=\"registerNameType\"/> <!-- was xs:Name -->\n                                <xs:element name=\"displayName\" type=\"xs:string\" minOccurs=\"0\"/>\n                                <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n                                <xs:element name=\"alternateGroup\" type=\"xs:Name\" minOccurs=\"0\"/>\n                                <xs:element name=\"addressOffset\" type=\"scaledNonNegativeInteger\"/>\n                                <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n                                <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n                                <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n                                <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n                                <xs:element name=\"fields\" minOccurs=\"0\" maxOccurs=\"1\">\n                                  <xs:complexType>\n                                    <xs:sequence>\n                                      <xs:element name=\"field\" minOccurs=\"1\" maxOccurs=\"unbounded\">\n                                      <xs:complexType>\n                                        <xs:sequence>\n                                          <xs:element name=\"name\" type=\"xs:string\"/>\n                                          <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n                                          <xs:choice>\n                                            <xs:group ref=\"bitRangeLsbMsbStyle\" minOccurs=\"0\"/>\n                                            <xs:group ref=\"bitRangeOffsetWidthStyle\" minOccurs=\"0\"/>\n                                            <xs:element name=\"bitRange\" type=\"bitRangeType\" minOccurs=\"0\"/>\n                                          </xs:choice>\n                                          <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n                                          <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n                                          <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n                                          <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n                                          <xs:element name=\"enumeratedValues\" minOccurs=\"0\" maxOccurs=\"2\">\n                                            <xs:complexType>\n                                              <xs:sequence>\n                                                <xs:element name=\"name\" type=\"xs:Name\" minOccurs=\"0\"/>\n                                                <xs:element name=\"usage\" type=\"enumUsageType\" minOccurs=\"0\"/>\n                                                <xs:element name=\"enumeratedValue\" minOccurs=\"1\" maxOccurs=\"unbounded\">\n                                                  <xs:complexType>\n                                                    <xs:sequence>\n                                                      <xs:element name=\"name\" type=\"xs:string\"/>\n                                                      <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n                                                      <xs:choice>\n                                                        <xs:element name=\"value\" type=\"enumeratedValueDataType\"/>\n                                                        <xs:element name=\"isDefault\" type=\"xs:boolean\"/>\n                                                      </xs:choice>\n                                                    </xs:sequence>\n                                                  </xs:complexType>\n                                                </xs:element>\n                                              </xs:sequence>\n                                              <xs:attribute name=\"derivedFrom\" type=\"xs:Name\" use=\"optional\"/>\n                                            </xs:complexType>\n                                          </xs:element>\n                                        </xs:sequence>\n                                        <xs:attribute name=\"derivedFrom\" type=\"xs:Name\" use=\"optional\"/>\n                                      </xs:complexType>\n                                    </xs:element>\n                                    </xs:sequence>\n                                  </xs:complexType>\n                                </xs:element>\n                              </xs:sequence>\n                              <xs:attribute name=\"derivedFrom\" type=\"xs:Name\" use=\"optional\"/>\n                            </xs:complexType>\n                          </xs:element>\n                        </xs:sequence>\n                      </xs:complexType>\n                    </xs:element>\n                  </xs:sequence>\n                  <xs:attribute name=\"derivedFrom\" type=\"xs:Name\" use=\"optional\"/>\n                </xs:complexType>\n              </xs:element>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n        <xs:element name=\"vendorExtensions\" minOccurs=\"0\" maxOccurs=\"1\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:any namespace=\"##any\" processContents=\"lax\" minOccurs=\"0\" maxOccurs=\"unbounded\">\n              </xs:any>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n      </xs:sequence>\n      <xs:attribute name=\"schemaVersion\" type=\"xs:decimal\" use=\"required\" fixed=\"1.0\"/>\n    </xs:complexType>\n  </xs:element>\n</xs:schema>\n
 
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    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: SVD Extension in Version 1.1\n\n\n\n\n\n\n\n\n\n\n\n
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SVD Extension in Version 1.1
  
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\nContent
 Extensions to the Device Section
 
 CPU Section (New)
 
 Extensions to the Peripheral Section
 
 Cluster Level (New)
 
 Extensions to the Register Section
 
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Description
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From a schema perspective, CMSIS-SVD Version 1.1 is fully backward compatible to version 1.0. Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. It is expected that over time all CMSIS-SVD descriptions will comply with version 1.1. Version 1.1 has not been finalized yet and is therefore currently marked draft. 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd___format__1__1__gr.js",
    "content": "var group__svd___format__1__1__gr =\n[\n    [ \"Extensions to the Device Section\", \"group__device_section_extensions__gr.html\", null ],\n    [ \"CPU Section (New)\", \"group__cpu_section__gr.html\", null ],\n    [ \"Extensions to the Peripheral Section\", \"group__peripheral_section_extensions__gr.html\", null ],\n    [ \"Cluster Level (New)\", \"group__cluster_level__gr.html\", null ],\n    [ \"Extensions to the Register Section\", \"group__register_section_extensions__gr.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: SVD File Schema Levels\n\n\n\n\n\n\n\n\n\n\n\n
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SVD File Schema Levels
  
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\nContent
 Device Level
 
 Peripherals Level
 
 Registers Level
 
 Fields Level
 
 Enumerated Values Level
 
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Description
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This section specifies the SVD file format Version 1.0. Each subsection defines one level of hierarchy and lists all mandatory and optional language elements as well as their type. A brief example description snippet demonstrates the usage of the elements. 
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Note
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  • The sequence of elements in CMSIS-SVD is mandatory.
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  • Optional elements are highlighted in green.
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  • Mandatory elements are highlighted in blue. Optional sections can contain mandatory elements, which must be specified when the optional section is used. In this case the mandatory elements are also highlighted in blue.
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\nNames
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All name tags must comply with the ANSI C identifier naming restrictions (identifierType). In particular they must not contain any spaces or special characters. This is necessary to support the generation of device header files thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS compliant target software.
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\nConstants
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Number constants shall be entered in hexadecimal, decimal, or binary format. 
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  • The Hexadecimal format is indicated by a leading \"0x\". 
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\nComments
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Comments have the standard XML format. 
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\nEmpty Tags
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  • Single tags are not supported (for example, <name>).
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Remarks
The CMSIS-SVD Schema File Ver. 1.0 and schema_1_1_gr are provided alongside this document. 
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    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd___format__gr.js",
    "content": "var group__svd___format__gr =\n[\n    [ \"Device Level\", \"group__svd__xml__device__gr.html\", null ],\n    [ \"Peripherals Level\", \"group__svd__xml__peripherals__gr.html\", null ],\n    [ \"Registers Level\", \"group__svd__xml__registers__gr.html\", null ],\n    [ \"Fields Level\", \"group__svd__xml__fields__gr.html\", null ],\n    [ \"Enumerated Values Level\", \"group__svd__xml__enum__gr.html\", null ]\n];"
  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__device__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Device Level\n\n\n\n\n\n\n\n\n\n\n\n
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CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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Device Level
SVD File Schema Levels
  
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<p>The element <b>device</b> provides the outermost frame of the description. \n- Only one device section is allowed per file. All other elements like peripherals, registers, \nfields, enumerated values, and vendor extensions are described within this scope. \n- A device contains one or more peripherals. \n- Optional elements like size, access, resetValue, and resetMask defined on this level are used \nas default values throughout the device description, unless they get redefined at a lower level.\n    </p> \n
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\n<device schemaVersion=\"xs:decimal\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD_Schema_1_0.xsd\">
    <name>identifierType</name>\n    <version>xs:string</version>\n    <description>xs:string</description>\n    <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>\n    <width>scaledNonNegativeInteger</width>\n\n    <!-- registerPropertiesGroup -->\n    <size>scaledNonNegativeInteger</size>\n    <access>accessType</access>\n    <resetValue>scaledNonNegativeInteger</resetValue>\n    <resetMask>scaledNonNegativeInteger</resetMask>\n    <!-- end of registerPropertiesGroup -->\n\n    <peripherals>\n        ...\n    </peripherals>\n\n    <vendorExtensions>\n        ...\n    </vendorExtensions>
</device>\n\n
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Attribute Name Description Type Occurrence  
xmlns:xs Specifies the underlying XML schema to which the CMSIS-SVD schema is compliant. Has to be set to: \"http://www.w3.org/2001/XMLSchema-instance\". xs:decimal 1..1  
xmlns:xs Specifies the file path and file name of the CMSIS-SVD Schema. For example, CMSIS-SVD_Schema_1_0.xsd. xs:string 1..1  
schemaVersion Specifies the CMSIS-SVD schema version the description is compliant to (for example, 1.0).  xs:decimal 1..1  
Element Name Description Type Occurrence  
name The name string is used to identify the device or device series. Device names are required to be unique. xs:string  1..1   
version  The string defines the version of the file. Silicon vendors maintain the description throughout the life-cycle of the device and ensure that all updated and released copies have a unique version string. Higher numbers indicate a more recent version.   xs:string  1..1  
description  String for describing main features of a device (for example CPU, clock frequency, peripheral overview). xs:string  1..1   
addressUnitBits  Defines the number of data bits uniquely selected by each address. The value for Cortex-M based devices is 8 (byte-addressable).  scaledNonNegativeInteger  1..1   
width  Defines the number of data bit-width of the maximum single data transfer supported by the bus infrastructure. This information is relevant for debuggers when accessing registers, because it might be required to issue multiple accesses for accessing a resource of a bigger size. The expected value for Cortex-M based devices is 32. scaledNonNegativeInteger  1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1   
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
peripherals  Next level of description. see Peripherals Level for details.   1..1   
vendorExtensions  The content and format of this section of the description is unspecified. Silicon vendors may choose to provide additional information. By default, this section is ignored for constructing the CMSIS files. It is up to the silicon vendor to specify a schema for this section.  xs:anyType (restriction)  0..1   
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\nExample:
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<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
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  <name>ARM_Cortex_M3</name>
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  <version>0.1</version>
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  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
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  <addressUnitBits>8</addressUnitBits>
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  <width>32</width>
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  <size>32</size>
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  <access>read-write</access>
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  <resetValue>0</resetValue>
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  <resetMask>0xffffffff</resetMask>
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  <peripherals>
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    ...
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  </peripherals>
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</device>
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The device description above is at version 0.1 and uniquely identifies the device by the name \"ARM_Cortex_M3\". The peripherals are memory mapped in a byte-addressable address space with a bus width of 32 bits. The default size of the registers contained in the peripherals is set to 32 bits. Unless redefined for specific peripherals, all registers or fields are read-write accessible. A reset value of 0, valid for all 32 bits as specified by the reset mask, is set for all registers unless redefined at a lower level. 
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    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__enum__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Enumerated Values Level\n\n\n\n\n\n\n\n\n\n\n\n
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Enumerated Values Level
SVD File Schema Levels
  
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Enumerated Values
 The concept of enumerated values creates a map between unsigned integers and an identifier string. In addition, a description string can be associated with each entry in the map.
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\n        0 <-> disabled -> \"the clock source clk0 is turned off\"\n        1 <-> enabled  -> \"the clock source clk1 is running\"\n        
 This information is used for generating an enum in the device header file. The debugger may use this information to display the identifier string as well as the description. Just like symbolic constants making source code more readable, the system view in the debugger becomes more instructive. The detailed description can provide reference manual level details within the debugger.
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\n\n<enumeratedValues derivedFrom=\"xs:Name\">\n\n    <name>enumerationNameType</name>\n    <usage>usageType</usage>\n\n    <enumeratedValue>\n        ...\n    </enumeratedValue>\n\n    ...\n    <enumeratedValue>\n        ...\n    </enumeratedValue>\n\n</enumeratedValues>\n\n
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Attribute Name Description Type Occurrence  
derivedFrom Makes a copy from a previously defined enumeratedValues section. No modifications are allowed. An enumeratedValues entry is referenced by its name. If the name is not unique throughout the description, it needs to be further qualified by specifying the associated field, register, and peripheral as required. For example: 
\n        field:                           clk.dis_en_enum\n        register + field:                ctrl.clk.dis_en_enum\n        peripheral + register + field:   timer0.ctrl.clk.dis_en_enum\n
  		xs:Name 0..1  
Element Name Description Type Occurrence  
name Identifier for the whole enumeration section. xs:Name 0..1  
usage Possible values are read, write, or read-write. This allows specifying two different enumerated values depending whether it is to be used for a read or a write access. If not specified, the default value read-write is used. enumUsageType 0..1  
enumeratedValue Describes a single entry in the enumeration. The number of required items depends on the bit width of the associated field. See section below for details.   1..*  
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Enumerated Value
 
An enumeratedValue defines a map between an unsigned integer and a human readable string.
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\n\n<enumeratedValue>
    <name>identifierType</name>\n    <description>xs:string</description>
    <choice>\n        <value>scaledNonNegativeInteger</value>\n        <isDefault>xs:boolean</isDefault>\n    </choice>
</enumeratedValue>\n\n
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Element Name Description Type Occurrence  
name String describing the semantics of the value. Can be displayed instead of the value. identifierType 0..1  
description Extended string describing the value. xs:string 0..1  
choice of 1..1  
value Defines the constant of the bit-field that the name corresponds to. scaledNonNegativeInteger 0..1  
isDefault Defines the name and description for all other values that are not listed explicitly. xs:boolean 0..1  
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\nExample:
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<enumeratedValues>
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    <name>TimerIntSelect</name>
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    <usage>read-write</usage>
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    <enumeratedValue>
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        <name>disabled</name>
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        <description>The clock source clk0 is turned off.</description>
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        <value>0</value>
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    </enumeratedValue>
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    <enumeratedValue>
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        <name>reserved</name>
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        <description>Reserved values. Do not use.</description>
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        <isDefault>true</isDefault>
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    </enumeratedValue>
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</enumeratedValues>
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<enumeratedValues>
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    <name>TimerIntSelect</name>
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    <usage>read-write</usage>
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    <enumeratedValue>
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        <name>disabled</name>
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        <description>Timer does not generate interrupts.</description>
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        <value>0</value>
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    </enumeratedValue>
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    <enumeratedValue>
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        <name>enabled</name>
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        <description>Timer generates interrupts.</description>
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        <isDefault>true</isDefault>
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    </enumeratedValue>
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Fields Level
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All fields of a register are enclosed between the <fields> opening and closing tags
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A bit-field has a name that is unique within the register. The position and size within the register is either described by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or the lsb and the bit-width of the field. A field may define an enumeratedValue in order to make the display more intuitive to read. 
\n
\n 
\n<fields>
    <field derivedFrom=\"identifierType\">
        <name>xs:Name</name>\n        <description>xs:string</description>
        <choice>\n             <!-- bitRangeLsbMsbStyle --> \n            <bitOffset>scaledNonNegativeInteger<bitOffset>\n            <bitWidth>scaledNonNegativeInteger</bitWidth>\n            or\n             <!-- bitRangeOffsetWidthStyle --> \n            <lsb>scaledNonNegativeInteger</lsb> \n            <msb>scaledNonNegativeInteger</msb>\n            or\n             <!-- bitRangePattern --> \n            <bitRange>pattern</bitRange>\n        </choice>\n        \n        <access>accessType</access>\n        <modifiedWriteValues>writeValueType</modifiedWriteValues>\n        <writeConstraint>writeConstraintType</writeConstraint>\n        <readAction>readActionType</readAction>
        <enumeratedValues>\n            ...\n        </enumeratedValues>
    </field>\n    ...\n    <field>\n       ...\n    </field>\n    \n<fields>\n\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Attribute Name Description Type Occurrence  
derivedFrom The field is cloned from a previously defined field with a unique name. xs:Name 0..1  
Element Name Description Type Occurrence  
name Name string used to identify the field. Field names must be unique within a register. xs:string  1..1   
description String describing the details of the register.  xs:string  0..1   
Choice of Three options exist to describe the field's bit-range. The options are to be used mutually exclusive: 1..1  
1. bitRangeLsbMsbStyle   
bitOffset Value defining the position of the least significant bit of the field within the register it belongs to. scaledNonNegativeInteger 1..1   
bitWidth  Value defining the bit-width of the bitfield within the register it belongs to.  scaledNonNegativeInteger 0..1   
2. bitRangeOffsetWidthStyle  
lsb  Value defining the bit position of the least significant bit within the register it belongs to. scaledNonNegativeInteger 1..1   
msb  Value defining the bit position of the most significant bit within the register it belongs to.  scaledNonNegativeInteger 1..1  
3. bitRangePattern  
bitRange  A string in the format: \"[<msb>:<lsb>]\" bitRangeType  0..1   
access Predefined strings can be used to define the allowed access types for this field: read-only, write-only, read-write,  writeOnce, and read-writeOnce. Can be omitted if it matches the access permission set for the parent register.  accessType 0..1   
modifiedWriteValues Describe the manipulation of data written to a field. If not specified, the value written to the field is the value stored in the field. The other options are bitwise operations: 
    \n
  • oneToClear: write data bit of one shall clear (set to zero) the corresponding bit in the field. 
    • \n
  • oneToSet: write data bit of one shall set (set to one) the corresponding bit in the field. 
    • \n
  • oneToToggle: write data bit of one shall toggle (invert) the corresponding bit in the field. 
    • \n
  • zeroToClear: write data bit of zero shall clear (set to zero) the corresponding bit in the field. 
    • \n
  • zeroToSet: write data bit of zero shall set (set to one) the corresponding bit in the field. 
    • \n
  • zeroToToggle: write data bit of zero shall toggle (invert) the corresponding bit in the field. 
    • \n
  • clear: after a write operation all bits in the field are cleared (set to zero). 
    • \n
  • set: after a write operation all bits in the field are set (set to one). 
    • \n
  • modify: after a write operation all bit in the field may be modified (default).  
    • \n
\n		modifiedWriteValuesType 0..1   
writeConstraint Three options exist to set write-constraints: 0..1  
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1  
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1  
3. range Consists of the following two elements:   0..1  
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1  
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1  
readAction If set, it specifies the side effect following a read operation. If not set, the field is not modified after a read. The defined side effects are: 
    \n
  • clear: The field is cleared (set to zero) following a read operation. 
    • \n
  • set: The field is set (set to ones) following a read operation. 
    • \n
  • modify: The field is modified in some way after a read operation. 
    • \n
  • modifyExternal: One or more dependent resources other than the current field are immediately affected by a read operation (it is recommended that the field description specifies these dependencies). Debuggers are not expected to read this field location unless explicitly instructed by the user. 
    • \n
\n		readActionType 0..1 register  
enumeratedValues Next lower level of description. See section Enumerated Values Level for details.   0..2  
\n
\nExample:
\n
...
\n
<field>
\n
  <name>TimerCtrl0_IntSel</name>
\n
  <description>Select interrupt line that is triggered by timer overflow.</description>
\n
  <bitOffset>1</bitOffset>
\n
  <bitWidth>3</bitWidth>
\n
  <access>read-write</access>
\n
  <resetValue>0x0</resetValue>
\n
  <modifiedWriteValues>oneToSet</modifiedWriteValues>
\n
  <writeConstraint>
\n
    <range>
\n
      <minimum>0</minimum>
\n
      <maximum>5</maximum>
\n
    </range>
\n
  </writeConstraint>
\n
  <readAction>clear</readAction>
\n
 
\n
  <enumeratedValues>
\n
    ...
\n
  </enumeratedValues>
\n
</field>
\n
...
\n
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__peripherals__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Peripherals Level\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
\n   
CMSIS System View Description
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Peripherals Level
SVD File Schema Levels
  
\n
\n
\n
All peripherals of a device are enclosed within the tag <peripherals>. At least one peripheral has to be defined. Each peripheral is enclosed in the tag <peripheral>.
\n
    \n
  • Each peripheral describes all registers belonging to that peripheral.
    • \n
  • The address range allocated by a peripheral is defined through one or more address blocks.
    • \n
  • An address block and register addresses are specified relative to the base address of a peripheral. The address block information can be used for constructing a memory map for the device peripherals.
    • \n
\n
Remarks
The memory map does not contain any information about RAM, ROM, or FLASH memory.
\n
\n
\n <peripherals> 
    <peripheral derivedFrom=identifierType>
        <name>identifierType</name>\n        <version>xs:string</version>\n        <description>xs:string</description>\n    \n        <groupName>identifierType</groupName>\n        <prependToName>identifierType</prependToName>\n        <appendToName>identifierType</appendToName>\n        <disableCondition>xs:string</disableCondition>\n    \n        <baseAddress>scaledNonNegativeInteger</baseAddress>\n    \n         <!-- registerPropertiesGroup -->\n        <size>scaledNonNegativeInteger</size>\n        <access>accessType</access>\n        <resetValue>scaledNonNegativeInteger</resetValue>\n        <resetMask>scaledNonNegativeInteger</resetMask>\n         <!-- end of registerPropertiesGroup -->\n    \n        <addressBlock>\n            <offset>scaledNonNegativeInteger</offset>\n            <size>scaledNonNegativeInteger</size>\n            <usage>usageType</usage>\n        </addressBlock>\n        ...\n        <addressBlock>\n            <offset>scaledNonNegativeInteger</offset>\n            <size>scaledNonNegativeInteger</size>\n            <usage>usageType</usage>\n        </addressBlock>\n    \n        <interrupt>\n            <name>identifierType</name>\n            <value>scaledNonNegativeInteger</value>\n        </interrupt>
        <registers>\n            ...\n        </registers>
    </peripheral>\n    ...\n    <peripheral>\n       ...\n    </peripheral>\n    \n</peripherals>\n\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of a peripheral from which this peripheral will be derived. Values are inherit. Elements specified underneath will override inherited values.  xs:Name  0..1  
Element Name Description Type Occurrence  
name  The name string is used to identify the peripheral. Peripheral names are required to be unique for a device. The name needs to be an ANSI C identifier to allow header file generation.  xs:Name  1..1   
version  The string specifies the version of this peripheral description.  xs:string  0..1   
description  The string provides an overview of the purpose and functionality of the peripheral. xs:string  0..1   
groupName  xs:string  0..1   
prependToName  All register names of this peripheral have their names prefixed with this string. xs:string  0..1   
appendToName  All register names of this peripheral have their names suffixed with this string. xs:string  0..1   
disableCondition  Is a C-language compliant logical expression returning a TRUE or FALSE result. If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed. 
\n 
\n Only constants and references to other registers contained in the description are allowed: <peripheral>-><register>-><field>, for example, (System->ClockControl->apbEnable == 0). The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |]. 
Attention
Use this feature only in cases where accesses from the debugger to registers of un-clocked peripherals result in severe debugging failures. SVD is intended to provide static information and does not include any run-time computation or functions. Such capabilities can be added by the tools, and is beyond the scope of this description language. 
\n		xs:string  0..1   
baseAddress  Lowest address reserved or used by the peripheral. scaledNonNegativeInteger  1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1  
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
addressBlock Specifies an address range uniquely mapped to this peripheral. A peripheral must have at least one address block, but may allocate multiple distinct address ranges. If a peripheral is derived form another peripheral, the addressBlock is not mandatory.  addressBlockType 1..*  
offset Specifies the start address of an address block relative to the peripheral baseAddress.  scaledNonNegativeInteger  1..1  
size Specifies the number of addressUnitBits being covered by this address block. The end address of an address block results from the sum of baseAddress, offset, and (size - 1).  scaledNonNegativeInteger  1..1  
usage The following predefined values can be used: registers,  buffer, or reserved.  scaledNonNegativeInteger  1..1  
interrupt  A peripheral can have multiple associated interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers. interruptType  0..*   
name  The string represents the interrupt name. XS:string  1..1   
value  Is the enumeration index value associated to the interrupt. xs:integer  1..1   
registers  See Registers Level for details.    0..1   
\n
\nExample:
\n
...
\n
<peripheral>
\n
  <name>Timer0</name>
\n
  <version>1.0.32</version>
\n
  <description>Timer 0 is a simple 16 bit timer counting down ... </description>
\n
  <baseAddress>0x40000000</baseAddress>
\n
  <addressBlock>
\n
    <offset>0x0</offset>
\n
    <size>0x400</size>
\n
    <usage>registers</usage>
\n
  </addressBlock>
\n
  <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
\n
  <registers>
\n
    ...
\n
  </registers>
\n
</peripheral>
\n
\n
<peripheral derivedFrom="Timer0">
\n
  <name>Timer1</name>
\n
  <baseAddress>0x40000400</baseAddress>
\n
</peripheral>
\n
...
\n
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/group__svd__xml__registers__gr.html",
    "content": "\n\n\n\n\nCMSIS-SVD: Registers Level\n\n\n\n\n\n\n\n\n\n\n\n
\n
\n\n \n \n  \n  \n \n \n
\"Logo\"\n   
CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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Registers Level
SVD File Schema Levels
  
\n
\n
\n
All registers of a peripheral are enclosed between the <registers> opening and closing tags.
\n
The description of registers is the most essential part of the SVD description. The register's name, detailed description, and the address-offset relative to the peripheral base address are the mandatory elements. If the size, access, reset value, and reset mask have not been specified on the device or peripheral level, or if the default values need to be redefined locally, these fields become mandatory.
\n
A register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics. In schema-terms the fields section is optional, however, from a specification perspective, fields are mandatory when they are described in the device documentation.
\n
The SVD specification supports the array-of-registers concept. The single register description gets duplicated automatically into an array. The size of the array is specified by the <dim> element. The register names can be composed by the register name and an index specific substring define in <dimIndex>. The <dimIncrement> specifies the address offset between two registers.
\n
\n
\n<registers> 
    <register derivedFrom=identifierType>\n    \n        <!-- dimElementGroup --> \n        <dim>scaledNonNegativeInteger</dim>\n        <dimIncrement>scaledNonNegativeInteger</dimIncrement>\n        <dimIndex>xs:string</dimIndex>\n        <!-- end of dimElementGroup --> \n   \n        <name>identifierType</name>\n    \n        <displayName>xs:string</displayName>\n    \n        <description>xs:string</description>\n    \n        <alternateGroup>xs:Name</alternateGroup>\n    \n        <addressOffset>scaledNonNegativeInteger</addressOffset>\n    \n        <!-- registerPropertiesGroup --> \n        <size>scaledNonNegativeInteger</size>\n        <access>accessType</access>\n        <resetValue>scaledNonNegativeInteger</resetValue>\n        <resetMask>scaledNonNegativeInteger</resetMask>\n        <!-- end of registerPropertiesGroup --> \n    \n        <modifiedWriteValues>writeValueType</modifiedWriteValues>\n        <writeConstraint>writeConstraintType</writeConstraint>\n        <readAction>readActionType</readAction>
        <fields>\n            ...\n        </fields>\n    \n    </register>\n    ...\n    <register>\n        ...\n    </register>\n    \n<registers> \n
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Attribute Name Description Type Occurrence  
derivedFrom Specifies the name of the register from which to inherit the data. Elements being specified underneath will override the inherited values. 
\nRemarks: When deriving a register, it is mandatory to specify at least the name, the description, and the addressOffset. 		xs:Name 0..1  
Element Name Description Type Occurrence  
See dimElementGroup for details.  
dimIncrement The value defines the number of elements in an array of registers.  scaledNonNegativeInteger  1..1   
dimIncrement If dim is specified, this element becomes mandatory. The element specifies the address increment in between two neighboring registers of the register array in the address map. scaledNonNegativeInteger  1..1   
dimIndex Specifies the substrings that replaces the %s placeholder within the register name. By default, the index is a decimal value starting with 0 for the first register.  dimIndexType  0..1   
name Name string used to identify the register. Register names are required to be unique within the scope of a peripheral.  registerNameType  1..1   
displayName When specified, the string is being used by a graphical frontend to visualize the register. Otherwise the name element is displayed. The displayName may contain special characters and white spaces. The place holder s can be used and is replaced by the dimIndex substring.  xs:string  0..1   
description String describing the details of the register. xs:string  0..1   
alternateGroup  Specifies a group name associated with all alternate register that have the same name. At the same time, it indicates that there is a register definition allocating the same absolute address in the address space. xs:Name  0..1   
addressOffset Value defining the address of the register relative to the baseAddress defined by the peripheral of the register. scaledNonNegativeInteger 1..1   
See registerPropertiesGroup for details.  
size Defines the default bit-width of any register contained in the device (implicit inheritance).  scaledNonNegativeInteger 0..1  
access Defines the default access rights for all registers. accessType 0..1   
resetValue  Defines the default value for all registers at RESET. scaledNonNegativeInteger  0..1   
resetMask Identifies which register bits have a defined reset value. scaledNonNegativeInteger 0..1  
modifiedWriteValues Element to describe the manipulation of data written to a register. If not specified, the value written to the field is the value stored in the field. The other options define bitwise operations: 
    \n
  • oneToClear: write data bits of one shall clear (set to zero) the corresponding bit in the register. 
    • \n
  • oneToSet: write data bits of one shall set (set to one) the corresponding bit in the register. 
    • \n
  • oneToToggle: write data bits of one shall toggle (invert) the corresponding bit in the register. 
    • \n
  • zeroToClear: write data bits of zero shall clear (set to zero) the corresponding bit in the register. 
    • \n
  • zeroToSet: write data bits of zero shall set (set to one) the corresponding bit in the register. 
    • \n
  • zeroToToggle: write data bits of zero shall toggle (invert) the corresponding bit in the register. 
    • \n
  • clear: after a write operation all bits in the field are cleared (set to zero). 
    • \n
  • set: after a write operation all bits in the field are set (set to one). 
    • \n
  • modify: after a write operation all bit in the field may be modified (default).  
    • \n
\n		modifiedWriteValuesType 0..1   
writeConstraint Three options exist to set write-constraints: 0..1  
1. writeAsRead If TRUE, only the last read value can be written. xs:boolean 0..1  
2. useEnumeratedValues If TRUE, only the values listed in the enumeratedValues list are considered valid write values. xs:boolean 0..1  
3. range Consists of the following two elements:   0..1  
minimum Specifies the smallest number to be written to the field. scaledNonNegativeInteger 1..1  
maximum Specifies the largest number to be written to the field. scaledNonNegativeInteger 1..1  
readAction  If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are: 
    \n
  • clear: The register is cleared (set to zero) following a read operation. 
    • \n
  • set: The register is set (set to ones) following a read operation. 
    • \n
  • modify: The register is modified in some way after a read operation. 
    • \n
  • modifyExternal: One or more dependent resources other than the current register are immediately affected by a read operation (it is recommended that the register description specifies these dependencies). Debuggers are not expected to read this register location unless explicitly instructed by the user. 
    • \n
\n		readActionType 
0..1  
\n
\n
fields  Next lower level of description (see Fields Level for details). Not all registers are further divided into fields, therefore, this level is optional. In case a register is subdivided into bit fields, it should be reflected in the description. The device header file can only contain bit access macros and bit-field structures if this information is contained in the description.   0..1   
\n
\nExample:
\n
...
\n
<register>
\n
  <name>TimerCtrl0</name>
\n
  <description>Timer Control Register</description>
\n
  <addressOffset>0x0</addressOffset>
\n
  <access>read-write</access>
\n
  <resetValue>0x00008001</resetValue>
\n
  <resetMask>0x0000ffff</resetMask>
\n
  <size>32</size>
\n
  <fields>
\n
    ...
\n
  </fields>
\n
</register>
\n
\n
<register derivedFrom="TimerCtrl0">
\n
  <name>TimerCtrl1</name>
\n
  <description>Derived Timer</description>
\n
  <addressOffset>0x4</addressOffset>
\n
</register>
\n
...
\n
 
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  },
  {
    "path": "Libraries/CMSIS/Documentation/SVD/html/index.html",
    "content": "\n\n\n\n\nCMSIS-SVD: System View Description\n\n\n\n\n\n\n\n\n\n\n\n
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\n\n \n \n  \n  \n \n \n
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CMSIS-SVD\n    Version 1.10\n   
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CMSIS System View Description
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System View Description 
  
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This chapter contains the introduction and specification of the CMSIS System View Description format (CMSIS-SVD). The introduction section outlines the objectives and benefits CMSIS-SVD.
\n
Introduction
\n
CMSIS-SVD formalizes the description of the programmer's view for the system contained in ARM Cortex-M processor-based microcontrollers, in particular the memory mapped registers of the peripherals. The detail contained in system view descriptions is comparable to what is found in device reference manuals published by silicon vendors. The information ranges from a high level functional description of a peripheral all the way down to the definition and purpose of an individual bit field in a memory mapped register. CMSIS-SVD files are developed and maintained by the silicon vendors. Silicon vendors manage their descriptions in a central, web-based Device Database and the CMSIS-SVD files are downloadable via a public web interface once they have been released by the silicon vendor. Tool vendors use these descriptions for providing device-specific debug views of peripherals in their debugger. Last but not least CMSIS compliant device header files are generated from CMSIS-SVD files.
\n
CMSIS-SVD Benefits
\n
    \n
  • The benefits for the Software Developer:
      \n
    • Consistency between device header file and what is being displayed by the debugger.
      • \n
    • Detailed information about peripherals, registers, fields, and bit values from within the debugger, without the need to reference device documentation.
      • \n
    • Public access via a web interface to new and updated descriptions as they become available from silicon vendors.
      • \n
    • Improved software development efficiency.
      • \n
    \n
    • \n
\n
    \n
  • The benefits for the Silicon Vendor:
      \n
    • A tool vendor independent file format enables early device support by a wide range of toolchains with limited effort.
      • \n
    • The XML-based format helps ease the integration into in-house design flows.
      • \n
    • Automated generation of CMSIS compliant device header files.
      • \n
    • Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance via the web-based Device Database.
      • \n
    \n
    • \n
\n
    \n
  • The benefits for the Tool Vendor:
      \n
    • Unified file format across silicon vendors helps the efficiency of supporting a wide range of new devices in a timely manner.
      • \n
    • Silicon vendors provide early review access to individuals ahead of the publishing date.
      • \n
    • Updated descriptions are available over the web simplifying the maintenance of device support.
      • \n
    \n
    • \n
\n
The Web Infrastructure
\n
\n\"CMSIS_SVD_WEB_DATABASE.png\"/\n
\nCMSIS-SVD Management Processes
\n
 The diagram illustrates the management process steps for uploading, validating, reviewing, publishing, and downloading CMSIS-SVD files.
\n
    \n
  • Managing Files: A CMSIS-SVD file is uploaded by a silicon vendor via the web interface (Device Database). The system performs a check against the CMSIS-SVD Schema and runs the SVDConv consistency checker. Only if both checks have been successful the file will be stored in the SVD Storage. Files can be added, replaced and deleted.
    • \n
\n
    \n
  • Managing Devices: The silicon vendor creates an entry for each of his devices in the database by defining a name and associating it with a CMSIS-SVD file from the SVD Storage. The publishing date set forth for a device is used by the system to determine when this device becomes visible in the public device database. Prior to the publishing date, the silicon vendor can grant review access to individuals for an individual device. Reviewers get notified by e-mail about a device being made available for review.
    • \n
\n
    \n
  • Public Download: Public access to the silicon vendor specific CMSIS-SVD download pages is provided from cmsis.arm.com or www.arm.com/cmsis. Select the CMSIS-SVD tab and select the Silicon Vendor of interest from the list. For the public download of the CMSIS-SVD files of published devices it is mandatory to:
      \n
    • Be logged in on the ARM web site.
      • \n
    • Have accepted a silicon vendor specific End Users License Agreement (EULA).
      • \n
    \n
    • \n
\n
More information about the web infrastructure can be found in the CMSIS-SVD Web Interface User Guide
\n
Language Outline
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Language Specification
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    • \n  
\n
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b;a.browser.msie&&/(static|relative)/.test(this.css(\"position\"))||/absolute/.test(this.css(\"position\"))?b=this.parents().filter(function(){return/(relative|absolute|fixed)/.test(a.curCSS(this,\"position\",1))&&/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0):b=this.parents().filter(function(){return/(auto|scroll)/.test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0);return/fixed/.test(this.css(\"position\"))||!b.length?a(document):b},zIndex:function(c){if(c!==b)return this.css(\"zIndex\",c);if(this.length){var d=a(this[0]),e,f;while(d.length&&d[0]!==document){e=d.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){f=parseInt(d.css(\"zIndex\"),10);if(!isNaN(f)&&f!==0)return f}d=d.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(a){a.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}}),a.each([\"Width\",\"Height\"],function(c,d){function h(b,c,d,f){a.each(e,function(){c-=parseFloat(a.curCSS(b,\"padding\"+this,!0))||0,d&&(c-=parseFloat(a.curCSS(b,\"border\"+this+\"Width\",!0))||0),f&&(c-=parseFloat(a.curCSS(b,\"margin\"+this,!0))||0)});return c}var e=d===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],f=d.toLowerCase(),g={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};a.fn[\"inner\"+d]=function(c){if(c===b)return g[\"inner\"+d].call(this);return this.each(function(){a(this).css(f,h(this,c)+\"px\")})},a.fn[\"outer\"+d]=function(b,c){if(typeof b!=\"number\")return g[\"outer\"+d].call(this,b);return this.each(function(){a(this).css(f,h(this,b,!0,c)+\"px\")})}}),a.extend(a.expr[\":\"],{data:function(b,c,d){return!!a.data(b,d[3])},focusable:function(b){return c(b,!isNaN(a.attr(b,\"tabindex\")))},tabbable:function(b){var d=a.attr(b,\"tabindex\"),e=isNaN(d);return(e||d>=0)&&c(b,!e)}}),a(function(){var b=document.body,c=b.appendChild(c=document.createElement(\"div\"));c.offsetHeight,a.extend(c.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0}),a.support.minHeight=c.offsetHeight===100,a.support.selectstart=\"onselectstart\"in c,b.removeChild(c).style.display=\"none\"}),a.extend(a.ui,{plugin:{add:function(b,c,d){var e=a.ui[b].prototype;for(var f in d)e.plugins[f]=e.plugins[f]||[],e.plugins[f].push([c,d[f]])},call:function(a,b,c){var d=a.plugins[b];if(!!d&&!!a.element[0].parentNode)for(var e=0;e0)return!0;b[d]=1,e=b[d]>0,b[d]=0;return e},isOverAxis:function(a,b,c){return a>b&&a=9)&&!b.button)return this._mouseUp(b);if(this._mouseStarted){this._mouseDrag(b);return b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+\".preventClickEvent\",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery);\n/*\n * jQuery UI Resizable 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Resizables\n *\n * Depends:\n *\tjquery.ui.core.js\n *\tjquery.ui.mouse.js\n *\tjquery.ui.widget.js\n */\n(function(a,b){a.widget(\"ui.resizable\",a.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:!1,animate:!1,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:\"e,s,se\",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass(\"ui-resizable\"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||\"ui-resizable-helper\":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")})),this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\")),this.elementIsWrapper=!0,this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")}),this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0}),this.originalResizeStyle=this.originalElement.css(\"resize\"),this.originalElement.css(\"resize\",\"none\"),this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"})),this.originalElement.css({margin:this.originalElement.css(\"margin\")}),this._proportionallyResize()),this.handles=c.handles||(a(\".ui-resizable-handle\",this.element).length?{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"}:\"e,s,se\");if(this.handles.constructor==String){this.handles==\"all\"&&(this.handles=\"n,e,s,w,se,sw,ne,nw\");var d=this.handles.split(\",\");this.handles={};for(var e=0;e
');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),\"se\"==f&&h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\"),this.handles[f]=\".ui-resizable-\"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=[\"padding\",/ne|nw|n/.test(c)?\"Top\":/se|sw|s/.test(c)?\"Bottom\":/^e$/.test(c)?\"Right\":\"Left\"].join(\"\");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(\".ui-resizable-handle\",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:\"se\"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass(\"ui-resizable-autohide\").hover(function(){c.disabled||(a(this).removeClass(\"ui-resizable-autohide\"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass(\"ui-resizable-autohide\"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css(\"position\"),width:c.outerWidth(),height:c.outerHeight(),top:c.css(\"top\"),left:c.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in this.handles)a(this.handles[d])[0]==b.target&&(c=!0);return!this.options.disabled&&c},_mouseStart:function(b){var d=this.options,e=this.element.position(),f=this.element;this.resizing=!0,this.documentScroll={top:a(document).scrollTop(),left:a(document).scrollLeft()},(f.is(\".ui-draggable\")||/absolute/.test(f.css(\"position\")))&&f.css({position:\"absolute\",top:e.top,left:e.left}),this._renderProxy();var g=c(this.helper.css(\"left\")),h=c(this.helper.css(\"top\"));d.containment&&(g+=a(d.containment).scrollLeft()||0,h+=a(d.containment).scrollTop()||0),this.offset=this.helper.offset(),this.position={left:g,top:h},this.size=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalSize=this._helper?{width:f.outerWidth(),height:f.outerHeight()}:{width:f.width(),height:f.height()},this.originalPosition={left:g,top:h},this.sizeDiff={width:f.outerWidth()-f.width(),height:f.outerHeight()-f.height()},this.originalMousePosition={left:b.pageX,top:b.pageY},this.aspectRatio=typeof d.aspectRatio==\"number\"?d.aspectRatio:this.originalSize.width/this.originalSize.height||1;var i=a(\".ui-resizable-\"+this.axis).css(\"cursor\");a(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i),f.addClass(\"ui-resizable-resizing\"),this._propagate(\"start\",b);return!0},_mouseDrag:function(b){var c=this.helper,d=this.options,e={},f=this,g=this.originalMousePosition,h=this.axis,i=b.pageX-g.left||0,j=b.pageY-g.top||0,k=this._change[h];if(!k)return!1;var l=k.apply(this,[b,i,j]),m=a.browser.msie&&a.browser.version<7,n=this.sizeDiff;this._updateVirtualBoundaries(b.shiftKey);if(this._aspectRatio||b.shiftKey)l=this._updateRatio(l,b);l=this._respectSize(l,b),this._propagate(\"resize\",b),c.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"}),!this._helper&&this._proportionallyResizeElements.length&&this._proportionallyResize(),this._updateCache(l),this._trigger(\"resize\",b,this.ui());return!1},_mouseStop:function(b){this.resizing=!1;var c=this.options,d=this;if(this._helper){var e=this._proportionallyResizeElements,f=e.length&&/textarea/i.test(e[0].nodeName),g=f&&a.ui.hasScroll(e[0],\"left\")?0:d.sizeDiff.height,h=f?0:d.sizeDiff.width,i={width:d.helper.width()-h,height:d.helper.height()-g},j=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,k=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;c.animate||this.element.css(a.extend(i,{top:k,left:j})),d.helper.height(d.size.height),d.helper.width(d.size.width),this._helper&&!c.animate&&this._proportionallyResize()}a(\"body\").css(\"cursor\",\"auto\"),this.element.removeClass(\"ui-resizable-resizing\"),this._propagate(\"stop\",b),this._helper&&this.helper.remove();return!1},_updateVirtualBoundaries:function(a){var b=this.options,c,e,f,g,h;h={minWidth:d(b.minWidth)?b.minWidth:0,maxWidth:d(b.maxWidth)?b.maxWidth:Infinity,minHeight:d(b.minHeight)?b.minHeight:0,maxHeight:d(b.maxHeight)?b.maxHeight:Infinity};if(this._aspectRatio||a)c=h.minHeight*this.aspectRatio,f=h.minWidth/this.aspectRatio,e=h.maxHeight*this.aspectRatio,g=h.maxWidth/this.aspectRatio,c>h.minWidth&&(h.minWidth=c),f>h.minHeight&&(h.minHeight=f),ea.width,k=d(a.height)&&e.minHeight&&e.minHeight>a.height;j&&(a.width=e.minWidth),k&&(a.height=e.minHeight),h&&(a.width=e.maxWidth),i&&(a.height=e.maxHeight);var l=this.originalPosition.left+this.originalSize.width,m=this.position.top+this.size.height,n=/sw|nw|w/.test(g),o=/nw|ne|n/.test(g);j&&n&&(a.left=l-e.minWidth),h&&n&&(a.left=l-e.maxWidth),k&&o&&(a.top=m-e.minHeight),i&&o&&(a.top=m-e.maxHeight);var p=!a.width&&!a.height;p&&!a.left&&a.top?a.top=null:p&&!a.top&&a.left&&(a.left=null);return a},_proportionallyResize:function(){var b=this.options;if(!!this._proportionallyResizeElements.length){var c=this.helper||this.element;for(var d=0;d');var d=a.browser.msie&&a.browser.version<7,e=d?1:0,f=d?2:-1;this.helper.addClass(this._helper).css({width:this.element.outerWidth()+f,height:this.element.outerHeight()+f,position:\"absolute\",left:this.elementOffset.left-e+\"px\",top:this.elementOffset.top-e+\"px\",zIndex:++c.zIndex}),this.helper.appendTo(\"body\").disableSelection()}else this.helper=this.element},_change:{e:function(a,b,c){return{width:this.originalSize.width+b}},w:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{left:f.left+b,width:e.width-b}},n:function(a,b,c){var d=this.options,e=this.originalSize,f=this.originalPosition;return{top:f.top+c,height:e.height-c}},s:function(a,b,c){return{height:this.originalSize.height+c}},se:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},sw:function(b,c,d){return a.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[b,c,d]))},ne:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[b,c,d]))},nw:function(b,c,d){return a.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[b,c,d]))}},_propagate:function(b,c){a.ui.plugin.call(this,b,[c,this.ui()]),b!=\"resize\"&&this._trigger(b,c,this.ui())},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}}),a.extend(a.ui.resizable,{version:\"1.8.18\"}),a.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=function(b){a(b).each(function(){var b=a(this);b.data(\"resizable-alsoresize\",{width:parseInt(b.width(),10),height:parseInt(b.height(),10),left:parseInt(b.css(\"left\"),10),top:parseInt(b.css(\"top\"),10)})})};typeof e.alsoResize==\"object\"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data(\"resizable-alsoresize\"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?[\"width\",\"height\"]:[\"width\",\"height\",\"top\",\"left\"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize==\"object\"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData(\"resizable-alsoresize\")}}),a.ui.plugin.add(\"resizable\",\"animate\",{stop:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d._proportionallyResizeElements,g=f.length&&/textarea/i.test(f[0].nodeName),h=g&&a.ui.hasScroll(f[0],\"left\")?0:d.sizeDiff.height,i=g?0:d.sizeDiff.width,j={width:d.size.width-i,height:d.size.height-h},k=parseInt(d.element.css(\"left\"),10)+(d.position.left-d.originalPosition.left)||null,l=parseInt(d.element.css(\"top\"),10)+(d.position.top-d.originalPosition.top)||null;d.element.animate(a.extend(j,l&&k?{top:l,left:k}:{}),{duration:e.animateDuration,easing:e.animateEasing,step:function(){var c={width:parseInt(d.element.css(\"width\"),10),height:parseInt(d.element.css(\"height\"),10),top:parseInt(d.element.css(\"top\"),10),left:parseInt(d.element.css(\"left\"),10)};f&&f.length&&a(f[0]).css({width:c.width,height:c.height}),d._updateCache(c),d._propagate(\"resize\",b)}})}}),a.ui.plugin.add(\"resizable\",\"containment\",{start:function(b,d){var e=a(this).data(\"resizable\"),f=e.options,g=e.element,h=f.containment,i=h instanceof a?h.get(0):/parent/.test(h)?g.parent().get(0):h;if(!!i){e.containerElement=a(i);if(/document/.test(h)||h==document)e.containerOffset={left:0,top:0},e.containerPosition={left:0,top:0},e.parentData={element:a(document),left:0,top:0,width:a(document).width(),height:a(document).height()||document.body.parentNode.scrollHeight};else{var j=a(i),k=[];a([\"Top\",\"Right\",\"Left\",\"Bottom\"]).each(function(a,b){k[a]=c(j.css(\"padding\"+b))}),e.containerOffset=j.offset(),e.containerPosition=j.position(),e.containerSize={height:j.innerHeight()-k[3],width:j.innerWidth()-k[1]};var l=e.containerOffset,m=e.containerSize.height,n=e.containerSize.width,o=a.ui.hasScroll(i,\"left\")?i.scrollWidth:n,p=a.ui.hasScroll(i)?i.scrollHeight:m;e.parentData={element:i,left:l.left,top:l.top,width:o,height:p}}}},resize:function(b,c){var d=a(this).data(\"resizable\"),e=d.options,f=d.containerSize,g=d.containerOffset,h=d.size,i=d.position,j=d._aspectRatio||b.shiftKey,k={top:0,left:0},l=d.containerElement;l[0]!=document&&/static/.test(l.css(\"position\"))&&(k=g),i.left<(d._helper?g.left:0)&&(d.size.width=d.size.width+(d._helper?d.position.left-g.left:d.position.left-k.left),j&&(d.size.height=d.size.width/e.aspectRatio),d.position.left=e.helper?g.left:0),i.top<(d._helper?g.top:0)&&(d.size.height=d.size.height+(d._helper?d.position.top-g.top:d.position.top),j&&(d.size.width=d.size.height*e.aspectRatio),d.position.top=d._helper?g.top:0),d.offset.left=d.parentData.left+d.position.left,d.offset.top=d.parentData.top+d.position.top;var m=Math.abs((d._helper?d.offset.left-k.left:d.offset.left-k.left)+d.sizeDiff.width),n=Math.abs((d._helper?d.offset.top-k.top:d.offset.top-g.top)+d.sizeDiff.height),o=d.containerElement.get(0)==d.element.parent().get(0),p=/relative|absolute/.test(d.containerElement.css(\"position\"));o&&p\n&&(m-=d.parentData.left),m+d.size.width>=d.parentData.width&&(d.size.width=d.parentData.width-m,j&&(d.size.height=d.size.width/d.aspectRatio)),n+d.size.height>=d.parentData.height&&(d.size.height=d.parentData.height-n,j&&(d.size.width=d.size.height*d.aspectRatio))},stop:function(b,c){var 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