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Repository: FEX-Emu/FEX
Branch: main
Commit: 5c4c468d1326
Files: 3243
Total size: 18.8 MB
Directory structure:
gitextract_1dff4jwg/
├── .clang-format
├── .clang-format-ignore
├── .git-blame-ignore-revs
├── .github/
│ ├── ISSUE_TEMPLATE/
│ │ └── potential-game-bug.md
│ └── workflows/
│ ├── ccpp.yml
│ ├── glibc_fault.yml
│ ├── hostrunner.yml
│ ├── instcountci.yml
│ ├── mingw_build.yml
│ ├── pr-code-format.yml
│ ├── setup-env/
│ │ └── action.yml
│ ├── steamrt4.yml
│ ├── test/
│ │ └── action.yml
│ ├── vixl_simulator.yml
│ ├── wine_build/
│ │ └── action.yml
│ └── wine_dll_artifacts.yml
├── .gitignore
├── .gitlab-ci.yml
├── .gitmodules
├── CMakeLists.txt
├── CMakeSettings.json
├── CODE_OF_CONDUCT.md
├── CodeEmitter/
│ ├── CMakeLists.txt
│ └── CodeEmitter/
│ ├── ALUOps.inl
│ ├── ASIMDOps.inl
│ ├── BranchOps.inl
│ ├── Buffer.h
│ ├── Emitter.h
│ ├── LoadstoreOps.inl
│ ├── Registers.h
│ ├── SVEOps.inl
│ ├── ScalarOps.inl
│ ├── SystemOps.inl
│ └── VixlUtils.inl
├── Data/
│ ├── AppConfig/
│ │ ├── CMakeLists.txt
│ │ ├── client.json
│ │ └── steamwebhelper.json
│ ├── CI/
│ │ ├── FEXLinuxTestsThunks.json
│ │ ├── GLThunks.json
│ │ └── VulkanThunks.json
│ ├── CMake/
│ │ ├── FindZycore.cmake
│ │ ├── FindZydis.cmake
│ │ ├── Findxxhash.cmake
│ │ ├── LinkerGC.cmake
│ │ ├── cmake_uninstall.cmake.in
│ │ ├── toolchain_aarch64.cmake
│ │ ├── toolchain_mingw.cmake
│ │ ├── toolchain_x86_32.cmake
│ │ ├── toolchain_x86_64.cmake
│ │ └── version_to_variables.cmake
│ ├── Dockerfile
│ ├── ThunksDB.json
│ ├── binfmts/
│ │ ├── CMakeLists.txt
│ │ ├── FEX-x86.conf.in
│ │ ├── FEX-x86.in
│ │ ├── FEX-x86_64.conf.in
│ │ └── FEX-x86_64.in
│ └── nix/
│ ├── FEXLinuxTests/
│ │ └── shell.nix
│ ├── LibraryForwarding/
│ │ └── shell.nix
│ ├── WineOnArm/
│ │ └── shell.nix
│ ├── cmake_configure_woa32.sh
│ ├── cmake_configure_woa64.sh
│ ├── cmake_enable_flt.sh
│ └── cmake_enable_libfwd.sh
├── External/
│ ├── .clang-format
│ ├── SoftFloat-3e/
│ │ ├── CMakeLists.txt
│ │ ├── include/
│ │ │ └── SoftFloat-3e/
│ │ │ ├── opts-GCC.h
│ │ │ ├── platform.h
│ │ │ ├── primitiveTypes.h
│ │ │ ├── softfloat.h
│ │ │ └── softfloat_types.h
│ │ └── src/
│ │ ├── extF80_add.c
│ │ ├── extF80_div.c
│ │ ├── extF80_eq.c
│ │ ├── extF80_le.c
│ │ ├── extF80_lt.c
│ │ ├── extF80_mul.c
│ │ ├── extF80_rem.c
│ │ ├── extF80_roundToInt.c
│ │ ├── extF80_sqrt.c
│ │ ├── extF80_sub.c
│ │ ├── extF80_to_f128.c
│ │ ├── extF80_to_f32.c
│ │ ├── extF80_to_f64.c
│ │ ├── extF80_to_i32.c
│ │ ├── extF80_to_i64.c
│ │ ├── extF80_to_ui64.c
│ │ ├── f128_add.c
│ │ ├── f128_div.c
│ │ ├── f128_eq.c
│ │ ├── f128_eq_signaling.c
│ │ ├── f128_isSignalingNaN.c
│ │ ├── f128_le.c
│ │ ├── f128_le_quiet.c
│ │ ├── f128_lt.c
│ │ ├── f128_lt_quiet.c
│ │ ├── f128_mul.c
│ │ ├── f128_mulAdd.c
│ │ ├── f128_rem.c
│ │ ├── f128_sqrt.c
│ │ ├── f128_sub.c
│ │ ├── f128_to_extF80.c
│ │ ├── f128_to_f16.c
│ │ ├── f128_to_f32.c
│ │ ├── f128_to_f64.c
│ │ ├── f128_to_i32.c
│ │ ├── f128_to_i64.c
│ │ ├── f128_to_ui32.c
│ │ ├── f128_to_ui64.c
│ │ ├── f32_to_extF80.c
│ │ ├── f32_to_f128.c
│ │ ├── f64_to_extF80.c
│ │ ├── i32_to_extF80.c
│ │ ├── i32_to_f128.c
│ │ ├── internals.h
│ │ ├── primitives.h
│ │ ├── s_add128.c
│ │ ├── s_addMagsExtF80.c
│ │ ├── s_addMagsF128.c
│ │ ├── s_approxRecip32_1.c
│ │ ├── s_approxRecipSqrt32_1.c
│ │ ├── s_approxRecipSqrt_1Ks.c
│ │ ├── s_approxRecip_1Ks.c
│ │ ├── s_commonNaNToExtF80UI.c
│ │ ├── s_commonNaNToF128UI.c
│ │ ├── s_commonNaNToF32UI.c
│ │ ├── s_commonNaNToF64UI.c
│ │ ├── s_countLeadingZeros32.c
│ │ ├── s_countLeadingZeros64.c
│ │ ├── s_countLeadingZeros8.c
│ │ ├── s_extF80UIToCommonNaN.c
│ │ ├── s_f128UIToCommonNaN.c
│ │ ├── s_f32UIToCommonNaN.c
│ │ ├── s_f64UIToCommonNaN.c
│ │ ├── s_le128.c
│ │ ├── s_lt128.c
│ │ ├── s_mul64ByShifted32To128.c
│ │ ├── s_mul64To128.c
│ │ ├── s_normRoundPackToExtF80.c
│ │ ├── s_normRoundPackToF128.c
│ │ ├── s_normSubnormalExtF80Sig.c
│ │ ├── s_normSubnormalF128Sig.c
│ │ ├── s_normSubnormalF128SigM.c
│ │ ├── s_normSubnormalF32Sig.c
│ │ ├── s_normSubnormalF64Sig.c
│ │ ├── s_propagateNaNExtF80UI.c
│ │ ├── s_propagateNaNF128UI.c
│ │ ├── s_roundPackToExtF80.c
│ │ ├── s_roundPackToF128.c
│ │ ├── s_roundPackToF32.c
│ │ ├── s_roundPackToF64.c
│ │ ├── s_roundToI32.c
│ │ ├── s_roundToI64.c
│ │ ├── s_roundToUI64.c
│ │ ├── s_shiftRightJam128.c
│ │ ├── s_shiftRightJam128Extra.c
│ │ ├── s_shiftRightJam32.c
│ │ ├── s_shiftRightJam64.c
│ │ ├── s_shiftRightJam64Extra.c
│ │ ├── s_shortShiftLeft128.c
│ │ ├── s_shortShiftRight128.c
│ │ ├── s_shortShiftRightJam64.c
│ │ ├── s_shortShiftRightJam64Extra.c
│ │ ├── s_sub128.c
│ │ ├── s_subMagsExtF80.c
│ │ ├── s_subMagsF128.c
│ │ ├── softfloat_raiseFlags.c
│ │ ├── specialize.h
│ │ └── ui64_to_extF80.c
│ ├── cephes/
│ │ ├── CMakeLists.txt
│ │ ├── LICENSE
│ │ ├── include/
│ │ │ └── cephes_128bit.h
│ │ └── src/
│ │ └── 128bit/
│ │ ├── Impl.cpp
│ │ ├── atanll.c
│ │ ├── constll.c
│ │ ├── exp2ll.c
│ │ ├── floorll.c
│ │ ├── log2ll.c
│ │ ├── mconf.h
│ │ ├── mtherr.c
│ │ ├── polevll.c
│ │ ├── sinll.c
│ │ └── tanll.c
│ ├── code-format-helper/
│ │ ├── code-format-helper.py
│ │ ├── requirements_formatting.txt
│ │ └── requirements_formatting.txt.in
│ └── tiny-json/
│ ├── CMakeLists.txt
│ ├── LICENSE
│ ├── tiny-json.c
│ └── tiny-json.h
├── FEXCore/
│ ├── CMakeLists.txt
│ ├── LICENSE
│ ├── Readme.md
│ ├── Scripts/
│ │ ├── config_generator.py
│ │ ├── json_ir_doc_generator.py
│ │ └── json_ir_generator.py
│ ├── Source/
│ │ ├── CMakeLists.txt
│ │ ├── Common/
│ │ │ ├── BitSet.h
│ │ │ ├── JitSymbols.cpp
│ │ │ ├── JitSymbols.h
│ │ │ ├── SoftFloat.h
│ │ │ ├── StringConv.h
│ │ │ └── VectorRegType.h
│ │ ├── Interface/
│ │ │ ├── Config/
│ │ │ │ ├── Config.cpp
│ │ │ │ └── Config.json.in
│ │ │ ├── Context/
│ │ │ │ ├── Context.cpp
│ │ │ │ └── Context.h
│ │ │ ├── Core/
│ │ │ │ ├── Addressing.cpp
│ │ │ │ ├── Addressing.h
│ │ │ │ ├── ArchHelpers/
│ │ │ │ │ ├── Arm64Emitter.cpp
│ │ │ │ │ └── Arm64Emitter.h
│ │ │ │ ├── CPUBackend.cpp
│ │ │ │ ├── CPUBackend.h
│ │ │ │ ├── CPUID.cpp
│ │ │ │ ├── CPUID.h
│ │ │ │ ├── CodeCache.cpp
│ │ │ │ ├── Core.cpp
│ │ │ │ ├── Dispatcher/
│ │ │ │ │ ├── Dispatcher.cpp
│ │ │ │ │ └── Dispatcher.h
│ │ │ │ ├── Frontend.cpp
│ │ │ │ ├── Frontend.h
│ │ │ │ ├── Interpreter/
│ │ │ │ │ ├── Fallbacks/
│ │ │ │ │ │ ├── F80Fallbacks.h
│ │ │ │ │ │ ├── FallbackOpHandler.h
│ │ │ │ │ │ ├── InterpreterFallbacks.cpp
│ │ │ │ │ │ ├── StringCompareFallbacks.cpp
│ │ │ │ │ │ └── VectorFallbacks.h
│ │ │ │ │ └── InterpreterOps.h
│ │ │ │ ├── JIT/
│ │ │ │ │ ├── ALUOps.cpp
│ │ │ │ │ ├── Arm64Relocations.cpp
│ │ │ │ │ ├── AtomicOps.cpp
│ │ │ │ │ ├── BranchOps.cpp
│ │ │ │ │ ├── ConversionOps.cpp
│ │ │ │ │ ├── DebugData.h
│ │ │ │ │ ├── EncryptionOps.cpp
│ │ │ │ │ ├── JIT.cpp
│ │ │ │ │ ├── JITClass.h
│ │ │ │ │ ├── MemoryOps.cpp
│ │ │ │ │ ├── MiscOps.cpp
│ │ │ │ │ ├── MoveOps.cpp
│ │ │ │ │ ├── Relocations.h
│ │ │ │ │ └── VectorOps.cpp
│ │ │ │ ├── LookupCache.cpp
│ │ │ │ ├── LookupCache.h
│ │ │ │ ├── OpcodeDispatcher/
│ │ │ │ │ ├── AVX_128.cpp
│ │ │ │ │ ├── BaseTables.h
│ │ │ │ │ ├── Crypto.cpp
│ │ │ │ │ ├── DDDTables.h
│ │ │ │ │ ├── Flags.cpp
│ │ │ │ │ ├── H0F38Tables.h
│ │ │ │ │ ├── H0F3ATables.h
│ │ │ │ │ ├── PrimaryGroupTables.h
│ │ │ │ │ ├── SecondaryGroupTables.h
│ │ │ │ │ ├── SecondaryModRMTables.h
│ │ │ │ │ ├── SecondaryTables.h
│ │ │ │ │ ├── VEXTables.h
│ │ │ │ │ ├── Vector.cpp
│ │ │ │ │ ├── X87.cpp
│ │ │ │ │ └── X87F64.cpp
│ │ │ │ ├── OpcodeDispatcher.cpp
│ │ │ │ ├── OpcodeDispatcher.h
│ │ │ │ ├── VSyscall/
│ │ │ │ │ └── VSyscall.inc
│ │ │ │ └── X86Tables/
│ │ │ │ ├── BaseTables.cpp
│ │ │ │ ├── DDDTables.cpp
│ │ │ │ ├── H0F38Tables.cpp
│ │ │ │ ├── H0F3ATables.cpp
│ │ │ │ ├── PrimaryGroupTables.cpp
│ │ │ │ ├── SecondaryGroupTables.cpp
│ │ │ │ ├── SecondaryModRMTables.cpp
│ │ │ │ ├── SecondaryTables.cpp
│ │ │ │ ├── VEXTables.cpp
│ │ │ │ ├── X86Tables.h
│ │ │ │ └── X87Tables.cpp
│ │ │ ├── GDBJIT/
│ │ │ │ ├── GDBJIT.cpp
│ │ │ │ └── GDBJIT.h
│ │ │ └── IR/
│ │ │ ├── IR.h
│ │ │ ├── IR.json
│ │ │ ├── IRDumper.cpp
│ │ │ ├── IREmitter.cpp
│ │ │ ├── IREmitter.h
│ │ │ ├── IntrusiveIRList.h
│ │ │ ├── PassManager.cpp
│ │ │ ├── PassManager.h
│ │ │ ├── Passes/
│ │ │ │ ├── IRDumperPass.cpp
│ │ │ │ ├── IRValidation.cpp
│ │ │ │ ├── IRValidation.h
│ │ │ │ ├── RedundantFlagCalculationElimination.cpp
│ │ │ │ ├── RegisterAllocationPass.cpp
│ │ │ │ ├── RegisterAllocationPass.h
│ │ │ │ └── x87StackOptimizationPass.cpp
│ │ │ ├── Passes.h
│ │ │ └── RegisterAllocationData.h
│ │ └── Utils/
│ │ ├── Allocator/
│ │ │ ├── 64BitAllocator.cpp
│ │ │ ├── FlexBitSet.h
│ │ │ ├── HostAllocator.h
│ │ │ └── IntrusiveArenaAllocator.h
│ │ ├── Allocator.cpp
│ │ ├── Allocator.h
│ │ ├── AllocatorHooks.cpp
│ │ ├── AllocatorOverride.cpp
│ │ ├── ArchHelpers/
│ │ │ ├── Arm64.cpp
│ │ │ └── Arm64_stubs.cpp
│ │ ├── BucketList.h
│ │ ├── Config.h
│ │ ├── FileLoading.cpp
│ │ ├── ForcedAssert.cpp
│ │ ├── LogManager.cpp
│ │ ├── LongJump.cpp
│ │ ├── MemberFunctionToPointer.h
│ │ ├── Profiler.cpp
│ │ ├── SpinWaitLock.cpp
│ │ ├── SpinWaitLock.h
│ │ ├── Telemetry.cpp
│ │ ├── Threads.cpp
│ │ ├── WritePriorityMutex.h
│ │ └── variable_length_integer.h
│ ├── docs/
│ │ ├── CPUBackends.md
│ │ ├── CustomCPUBackend.md
│ │ ├── Frontend.md
│ │ ├── IR.md
│ │ ├── MemoryModelEmulation.md
│ │ └── OpDispatcher.md
│ ├── include/
│ │ ├── FEXCore/
│ │ │ ├── Config/
│ │ │ │ └── Config.h
│ │ │ ├── Core/
│ │ │ │ ├── CPUID.h
│ │ │ │ ├── CodeCache.h
│ │ │ │ ├── Context.h
│ │ │ │ ├── CoreState.h
│ │ │ │ ├── HostFeatures.h
│ │ │ │ ├── SignalDelegator.h
│ │ │ │ ├── Thunks.h
│ │ │ │ └── X86Enums.h
│ │ │ ├── Debug/
│ │ │ │ ├── GDBReaderInterface.h
│ │ │ │ └── InternalThreadState.h
│ │ │ ├── HLE/
│ │ │ │ ├── SourcecodeResolver.h
│ │ │ │ └── SyscallHandler.h
│ │ │ ├── IR/
│ │ │ │ └── IR.h
│ │ │ ├── Utils/
│ │ │ │ ├── Allocator.h
│ │ │ │ ├── AllocatorHooks.h
│ │ │ │ ├── ArchHelpers/
│ │ │ │ │ └── Arm64.h
│ │ │ │ ├── CompilerDefs.h
│ │ │ │ ├── EnumOperators.h
│ │ │ │ ├── EnumUtils.h
│ │ │ │ ├── Event.h
│ │ │ │ ├── FPState.h
│ │ │ │ ├── File.h
│ │ │ │ ├── FileLoading.h
│ │ │ │ ├── InterruptableConditionVariable.h
│ │ │ │ ├── IntervalList.h
│ │ │ │ ├── LogManager.h
│ │ │ │ ├── LongJump.h
│ │ │ │ ├── MathUtils.h
│ │ │ │ ├── PrctlUtils.h
│ │ │ │ ├── Profiler.h
│ │ │ │ ├── SHMStats.h
│ │ │ │ ├── SignalScopeGuards.h
│ │ │ │ ├── StringUtils.h
│ │ │ │ ├── Telemetry.h
│ │ │ │ ├── ThreadPoolAllocator.h
│ │ │ │ ├── Threads.h
│ │ │ │ └── TypeDefines.h
│ │ │ └── fextl/
│ │ │ ├── allocator.h
│ │ │ ├── deque.h
│ │ │ ├── fmt.h
│ │ │ ├── forward_list.h
│ │ │ ├── functional.h
│ │ │ ├── list.h
│ │ │ ├── map.h
│ │ │ ├── memory.h
│ │ │ ├── memory_resource.h
│ │ │ ├── queue.h
│ │ │ ├── robin_map.h
│ │ │ ├── robin_set.h
│ │ │ ├── set.h
│ │ │ ├── sstream.h
│ │ │ ├── stack.h
│ │ │ ├── string.h
│ │ │ ├── unordered_map.h
│ │ │ ├── unordered_set.h
│ │ │ └── vector.h
│ │ └── git_version.h.in
│ └── unittests/
│ ├── APITests/
│ │ ├── Allocator.cpp
│ │ ├── CMakeLists.txt
│ │ ├── FileLoading.cpp
│ │ ├── FlexBitSet.cpp
│ │ ├── FutexSpinTest.cpp
│ │ ├── ILog2.cpp
│ │ └── vl_integer.cpp
│ ├── CMakeLists.txt
│ └── Emitter/
│ ├── ALU_Tests.cpp
│ ├── ASIMD_Tests.cpp
│ ├── Branch_Tests.cpp
│ ├── CMakeLists.txt
│ ├── Loadstore_Tests.cpp
│ ├── SVE_Tests.cpp
│ ├── Scalar_Tests.cpp
│ ├── System_Tests.cpp
│ └── TestDisassembler.h
├── FEXHeaderUtils/
│ ├── CMakeLists.txt
│ └── FEXHeaderUtils/
│ ├── BitUtils.h
│ ├── Filesystem.h
│ ├── RingBuffer.h
│ ├── StringArgumentParser.h
│ ├── SymlinkChecks.h
│ └── Syscalls.h
├── LICENSE
├── Readme.md
├── Scripts/
│ ├── CI_FetchRootFS.py
│ ├── CheckBinfmtNotInstall.sh
│ ├── ClassifyCPU.py
│ ├── DefinitionExtract.py
│ ├── FEXUpdateAOTIRCache.sh
│ ├── GenerateSyscallNumbers.py
│ ├── InstallFEX.py
│ ├── InstructionCountParser.py
│ ├── NeedDisabledSVE.py
│ ├── StructPackVerifier.py
│ ├── Threaded_Lockstep_Runner.py
│ ├── UpdateInstructionCountJson.py
│ ├── aarch64_fit_native.py
│ ├── changelog_generator.py
│ ├── doc_outline_generator.py
│ ├── generate_changelog.sh
│ ├── generate_doc_outline.sh
│ ├── generate_release.sh
│ ├── guest_test_runner.py
│ ├── json_asm_config_parse.py
│ ├── json_config_parse.py
│ ├── json_ir_config_parse.py
│ ├── reformat.sh
│ ├── testharness_runner.py
│ └── update_instcountci.sh
├── Source/
│ ├── CMakeLists.txt
│ ├── Common/
│ │ ├── ArgumentLoader.cpp
│ │ ├── ArgumentLoader.h
│ │ ├── Async.h
│ │ ├── AsyncNet.h
│ │ ├── CMakeLists.txt
│ │ ├── CPUInfo.cpp
│ │ ├── CPUInfo.h
│ │ ├── Config.cpp
│ │ ├── Config.h
│ │ ├── FDUtils.h
│ │ ├── FEXServerClient.cpp
│ │ ├── FEXServerClient.h
│ │ ├── FileFormatCheck.cpp
│ │ ├── FileFormatCheck.h
│ │ ├── FileMappingBaseAddress.h
│ │ ├── HostFeatures.cpp
│ │ ├── HostFeatures.h
│ │ ├── JSONPool.cpp
│ │ ├── JSONPool.h
│ │ ├── Linux/
│ │ │ ├── SBRKAllocations.cpp
│ │ │ └── SBRKAllocations.h
│ │ ├── SHMStats.cpp
│ │ ├── SHMStats.h
│ │ ├── VolatileMetadata.cpp
│ │ ├── VolatileMetadata.h
│ │ └── X86Features.h
│ ├── Steam/
│ │ ├── CMakeLists.txt
│ │ ├── CompatTool.cpp
│ │ ├── ConfigTemplate.json
│ │ ├── ServerManager.cpp
│ │ ├── VERSIONS.txt.in
│ │ ├── emulator.json
│ │ └── toolmanifest.vdf
│ ├── Tools/
│ │ ├── CMakeLists.txt
│ │ ├── CodeSizeValidation/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── CommonTools/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── CodeLoader.h
│ │ │ ├── DummyHandlers.cpp
│ │ │ ├── DummyHandlers.h
│ │ │ ├── HarnessHelpers.h
│ │ │ ├── Linux/
│ │ │ │ └── Utils/
│ │ │ │ ├── ELFContainer.cpp
│ │ │ │ ├── ELFContainer.h
│ │ │ │ └── ELFParser.h
│ │ │ └── PortabilityInfo.h
│ │ ├── FEXBash/
│ │ │ ├── CMakeLists.txt
│ │ │ └── FEXBash.cpp
│ │ ├── FEXConfig/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Main.cpp
│ │ │ ├── Main.h
│ │ │ ├── main.qml
│ │ │ ├── qml5.qrc
│ │ │ ├── qml6.qrc
│ │ │ ├── qt5/
│ │ │ │ ├── FileDialog.qml
│ │ │ │ ├── FolderDialog.qml
│ │ │ │ └── MessageDialog.qml
│ │ │ └── qt6/
│ │ │ ├── FileDialog.qml
│ │ │ ├── FolderDialog.qml
│ │ │ └── MessageDialog.qml
│ │ ├── FEXGDBReader/
│ │ │ ├── CMakeLists.txt
│ │ │ └── FEXGDBReader.cpp
│ │ ├── FEXGetConfig/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── FEXInterpreter/
│ │ │ ├── AOT/
│ │ │ │ ├── AOTGenerator.cpp
│ │ │ │ └── AOTGenerator.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── ELFCodeLoader.h
│ │ │ └── FEXInterpreter.cpp
│ │ ├── FEXOfflineCompiler/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── FEXRootFSFetcher/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Main.cpp
│ │ │ ├── XXFileHash.cpp
│ │ │ └── XXFileHash.h
│ │ ├── FEXServer/
│ │ │ ├── ArgumentLoader.cpp
│ │ │ ├── ArgumentLoader.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Logger.cpp
│ │ │ ├── Logger.h
│ │ │ ├── Main.cpp
│ │ │ ├── PipeScanner.cpp
│ │ │ ├── PipeScanner.h
│ │ │ ├── ProcessPipe.cpp
│ │ │ ├── ProcessPipe.h
│ │ │ ├── SquashFS.cpp
│ │ │ └── SquashFS.h
│ │ ├── LinuxEmulation/
│ │ │ ├── ArchHelpers/
│ │ │ │ ├── MContext.cpp
│ │ │ │ ├── MContext.h
│ │ │ │ ├── UContext.h
│ │ │ │ └── WinContext.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── GdbServer/
│ │ │ │ ├── Info.cpp
│ │ │ │ └── Info.h
│ │ │ ├── LinuxSyscalls/
│ │ │ │ ├── Arm64/
│ │ │ │ │ └── SyscallsEnum.h
│ │ │ │ ├── EmulatedFiles/
│ │ │ │ │ ├── EmulatedFiles.cpp
│ │ │ │ │ └── EmulatedFiles.h
│ │ │ │ ├── FaultSafeUserMemAccess.cpp
│ │ │ │ ├── FileManagement.cpp
│ │ │ │ ├── FileManagement.h
│ │ │ │ ├── GdbServer.cpp
│ │ │ │ ├── GdbServer.h
│ │ │ │ ├── LinuxAllocator.cpp
│ │ │ │ ├── LinuxAllocator.h
│ │ │ │ ├── Seccomp/
│ │ │ │ │ ├── BPFEmitter.cpp
│ │ │ │ │ ├── BPFEmitter.h
│ │ │ │ │ ├── Dumper.cpp
│ │ │ │ │ ├── SeccompEmulator.cpp
│ │ │ │ │ └── SeccompEmulator.h
│ │ │ │ ├── SignalDelegator/
│ │ │ │ │ └── GuestFramesManagement.cpp
│ │ │ │ ├── SignalDelegator.cpp
│ │ │ │ ├── SignalDelegator.h
│ │ │ │ ├── Syscalls/
│ │ │ │ │ ├── EPoll.cpp
│ │ │ │ │ ├── FD.cpp
│ │ │ │ │ ├── FS.cpp
│ │ │ │ │ ├── IO.cpp
│ │ │ │ │ ├── Info.cpp
│ │ │ │ │ ├── Memory.cpp
│ │ │ │ │ ├── NotImplemented.cpp
│ │ │ │ │ ├── Passthrough.cpp
│ │ │ │ │ ├── Signals.cpp
│ │ │ │ │ ├── Stubs.cpp
│ │ │ │ │ ├── Thread.cpp
│ │ │ │ │ ├── Thread.h
│ │ │ │ │ └── Timer.cpp
│ │ │ │ ├── Syscalls.cpp
│ │ │ │ ├── Syscalls.h
│ │ │ │ ├── SyscallsSMCTracking.cpp
│ │ │ │ ├── SyscallsVMATracking.cpp
│ │ │ │ ├── SyscallsVMATracking.h
│ │ │ │ ├── ThreadManager.cpp
│ │ │ │ ├── ThreadManager.h
│ │ │ │ ├── Types.h
│ │ │ │ ├── Utils/
│ │ │ │ │ ├── Threads.cpp
│ │ │ │ │ └── Threads.h
│ │ │ │ ├── x32/
│ │ │ │ │ ├── EPoll.cpp
│ │ │ │ │ ├── FD.cpp
│ │ │ │ │ ├── FS.cpp
│ │ │ │ │ ├── IO.cpp
│ │ │ │ │ ├── Info.cpp
│ │ │ │ │ ├── Ioctl/
│ │ │ │ │ │ ├── HelperDefines.h
│ │ │ │ │ │ ├── amdgpu_drm.inl
│ │ │ │ │ │ ├── asahi_drm.inl
│ │ │ │ │ │ ├── asound.h
│ │ │ │ │ │ ├── asound.inl
│ │ │ │ │ │ ├── drm.h
│ │ │ │ │ │ ├── drm.inl
│ │ │ │ │ │ ├── ext_fs.h
│ │ │ │ │ │ ├── ext_fs.inl
│ │ │ │ │ │ ├── f2fs.h
│ │ │ │ │ │ ├── f2fs.inl
│ │ │ │ │ │ ├── i915_drm.inl
│ │ │ │ │ │ ├── input.h
│ │ │ │ │ │ ├── input.inl
│ │ │ │ │ │ ├── joystick.h
│ │ │ │ │ │ ├── joystick.inl
│ │ │ │ │ │ ├── lima_drm.inl
│ │ │ │ │ │ ├── msdos_fs.h
│ │ │ │ │ │ ├── msdos_fs.inl
│ │ │ │ │ │ ├── msm_drm.inl
│ │ │ │ │ │ ├── nouveau_drm.inl
│ │ │ │ │ │ ├── nova_drm.inl
│ │ │ │ │ │ ├── panfrost_drm.inl
│ │ │ │ │ │ ├── panthor_drm.inl
│ │ │ │ │ │ ├── pvr_drm.inl
│ │ │ │ │ │ ├── radeon_drm.inl
│ │ │ │ │ │ ├── sockios.h
│ │ │ │ │ │ ├── sockios.inl
│ │ │ │ │ │ ├── streams.h
│ │ │ │ │ │ ├── streams.inl
│ │ │ │ │ │ ├── usbdev.h
│ │ │ │ │ │ ├── usbdev.inl
│ │ │ │ │ │ ├── v3d_drm.inl
│ │ │ │ │ │ ├── v4l2.h
│ │ │ │ │ │ ├── v4l2.inl
│ │ │ │ │ │ ├── vc4_drm.inl
│ │ │ │ │ │ ├── virtio_drm.inl
│ │ │ │ │ │ ├── wireless.h
│ │ │ │ │ │ ├── wireless.inl
│ │ │ │ │ │ └── xe_drm.inl
│ │ │ │ │ ├── IoctlEmulation.cpp
│ │ │ │ │ ├── IoctlEmulation.h
│ │ │ │ │ ├── Ioctls.inl
│ │ │ │ │ ├── Memory.cpp
│ │ │ │ │ ├── Msg.cpp
│ │ │ │ │ ├── NotImplemented.cpp
│ │ │ │ │ ├── Sched.cpp
│ │ │ │ │ ├── Semaphore.cpp
│ │ │ │ │ ├── Signals.cpp
│ │ │ │ │ ├── Socket.cpp
│ │ │ │ │ ├── Stubs.cpp
│ │ │ │ │ ├── Syscalls.cpp
│ │ │ │ │ ├── Syscalls.h
│ │ │ │ │ ├── SyscallsEnum.h
│ │ │ │ │ ├── SyscallsNames.inl
│ │ │ │ │ ├── Thread.cpp
│ │ │ │ │ ├── Thread.h
│ │ │ │ │ ├── Time.cpp
│ │ │ │ │ ├── Timer.cpp
│ │ │ │ │ └── Types.h
│ │ │ │ └── x64/
│ │ │ │ ├── EPoll.cpp
│ │ │ │ ├── FD.cpp
│ │ │ │ ├── Info.cpp
│ │ │ │ ├── Ioctl/
│ │ │ │ │ ├── HelperDefines.h
│ │ │ │ │ ├── amdgpu_drm.inl
│ │ │ │ │ ├── asound.h
│ │ │ │ │ ├── asound.inl
│ │ │ │ │ ├── drm.h
│ │ │ │ │ ├── drm.inl
│ │ │ │ │ ├── ext_fs.h
│ │ │ │ │ ├── ext_fs.inl
│ │ │ │ │ ├── f2fs.h
│ │ │ │ │ ├── f2fs.inl
│ │ │ │ │ ├── input.h
│ │ │ │ │ ├── input.inl
│ │ │ │ │ ├── joystick.h
│ │ │ │ │ ├── joystick.inl
│ │ │ │ │ ├── msdos_fs.h
│ │ │ │ │ ├── msdos_fs.inl
│ │ │ │ │ ├── msm_drm.inl
│ │ │ │ │ ├── sockios.h
│ │ │ │ │ ├── sockios.inl
│ │ │ │ │ ├── wireless.h
│ │ │ │ │ └── wireless.inl
│ │ │ │ ├── Memory.cpp
│ │ │ │ ├── NotImplemented.cpp
│ │ │ │ ├── Semaphore.cpp
│ │ │ │ ├── Signals.cpp
│ │ │ │ ├── Syscalls.cpp
│ │ │ │ ├── Syscalls.h
│ │ │ │ ├── SyscallsEnum.h
│ │ │ │ ├── SyscallsNames.inl
│ │ │ │ ├── Thread.cpp
│ │ │ │ ├── Thread.h
│ │ │ │ ├── Time.cpp
│ │ │ │ └── Types.h
│ │ │ ├── Thunks.cpp
│ │ │ ├── Thunks.h
│ │ │ ├── VDSO_Emulation.cpp
│ │ │ └── VDSO_Emulation.h
│ │ ├── TestHarnessRunner/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── TestHarnessRunner/
│ │ │ │ ├── HostRunner.cpp
│ │ │ │ └── HostRunner.h
│ │ │ └── TestHarnessRunner.cpp
│ │ └── pidof/
│ │ ├── CMakeLists.txt
│ │ └── pidof.cpp
│ └── Windows/
│ ├── ARM64EC/
│ │ ├── BTInterface.h
│ │ ├── CMakeLists.txt
│ │ ├── Module.S
│ │ ├── Module.cpp
│ │ └── libarm64ecfex.def
│ ├── CMakeLists.txt
│ ├── Common/
│ │ ├── CMakeLists.txt
│ │ ├── CPUFeatures.cpp
│ │ ├── CPUFeatures.h
│ │ ├── CRT/
│ │ │ ├── Alloc.cpp
│ │ │ ├── CMakeLists.txt
│ │ │ ├── CRT.cpp
│ │ │ ├── CRT.h
│ │ │ ├── IO.cpp
│ │ │ ├── Math.cpp
│ │ │ ├── Misc.cpp
│ │ │ ├── Musl/
│ │ │ │ ├── CMakeLists.txt
│ │ │ │ ├── __math_divzero.c
│ │ │ │ ├── __math_invalid.c
│ │ │ │ ├── __math_oflow.c
│ │ │ │ ├── __math_uflow.c
│ │ │ │ ├── __math_xflow.c
│ │ │ │ ├── exp2.c
│ │ │ │ ├── exp_data.c
│ │ │ │ ├── exp_data.h
│ │ │ │ ├── fmod.c
│ │ │ │ ├── isnan.c
│ │ │ │ ├── libm.h
│ │ │ │ ├── log2.c
│ │ │ │ ├── log2_data.c
│ │ │ │ ├── log2_data.h
│ │ │ │ ├── remainder.c
│ │ │ │ ├── remquo.c
│ │ │ │ ├── strtoimax.c
│ │ │ │ ├── strtoll.c
│ │ │ │ ├── strtoull.c
│ │ │ │ └── strtoumax.c
│ │ │ └── String.cpp
│ │ ├── CallRetStack.h
│ │ ├── Exception.h
│ │ ├── Handle.h
│ │ ├── ImageTracker.cpp
│ │ ├── ImageTracker.h
│ │ ├── InvalidationTracker.cpp
│ │ ├── InvalidationTracker.h
│ │ ├── JITGuardPage.h
│ │ ├── LoadConfig.S
│ │ ├── Logging.cpp
│ │ ├── Logging.h
│ │ ├── Module.h
│ │ ├── OvercommitTracker.h
│ │ ├── PortabilityInfo.h
│ │ ├── Priv.h
│ │ ├── SHMStats.cpp
│ │ ├── SHMStats.h
│ │ ├── TSOHandlerConfig.h
│ │ └── WinAPI/
│ │ ├── Alloc.cpp
│ │ ├── CMakeLists.txt
│ │ ├── IO.cpp
│ │ ├── Misc.cpp
│ │ └── Sync.cpp
│ ├── Defs/
│ │ ├── ntdll.def
│ │ └── wow64.def
│ ├── WOW64/
│ │ ├── BTInterface.h
│ │ ├── CMakeLists.txt
│ │ ├── Module.cpp
│ │ └── libwow64fex.def
│ └── include/
│ ├── wine/
│ │ ├── debug.h
│ │ └── unixlib.h
│ ├── winnt.h
│ └── winternl.h
├── ThunkLibs/
│ ├── Generator/
│ │ ├── CMakeLists.txt
│ │ ├── analysis.cpp
│ │ ├── analysis.h
│ │ ├── data_layout.cpp
│ │ ├── data_layout.h
│ │ ├── diagnostics.h
│ │ ├── gen.cpp
│ │ ├── interface.h
│ │ └── main.cpp
│ ├── GuestLibs/
│ │ └── CMakeLists.txt
│ ├── HostLibs/
│ │ └── CMakeLists.txt
│ ├── README.md
│ ├── include/
│ │ └── common/
│ │ ├── GeneratorInterface.h
│ │ ├── Guest.h
│ │ ├── Host.h
│ │ ├── PackedArguments.h
│ │ └── X11Manager.h
│ ├── libEGL/
│ │ ├── libEGL_Guest.cpp
│ │ ├── libEGL_Host.cpp
│ │ └── libEGL_interface.cpp
│ ├── libGL/
│ │ ├── glcorearb.h
│ │ ├── libGL_Guest.cpp
│ │ ├── libGL_Host.cpp
│ │ └── libGL_interface.cpp
│ ├── libSDL2/
│ │ ├── libSDL2_Guest.cpp
│ │ └── libSDL2_Host.cpp
│ ├── libVDSO/
│ │ ├── Types.h
│ │ ├── libVDSO_Guest.cpp
│ │ ├── libVDSO_Guest.lds
│ │ ├── libVDSO_Guest_32.lds
│ │ └── libVDSO_interface.cpp
│ ├── libX11/
│ │ └── libX11_NativeGuest.cpp
│ ├── libasound/
│ │ ├── libasound_Guest.cpp
│ │ ├── libasound_Host.cpp
│ │ └── libasound_interface.cpp
│ ├── libdrm/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libdrm_interface.cpp
│ ├── libfex_malloc/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── Types.h
│ ├── libfex_malloc_loader/
│ │ └── Guest.cpp
│ ├── libfex_malloc_symbols/
│ │ └── Host.cpp
│ ├── libfex_thunk_test/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ ├── api.h
│ │ ├── lib.cpp
│ │ └── libfex_thunk_test_interface.cpp
│ ├── libvulkan/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libvulkan_interface.cpp
│ ├── libwayland-client/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libwayland-client_interface.cpp
│ └── libxshmfence/
│ ├── Guest.cpp
│ ├── Host.cpp
│ └── libxshmfence_interface.cpp
├── docs/
│ ├── CPUID.md
│ ├── DeferredSignals.md
│ ├── ProgrammingConcerns.md
│ ├── Readme_CN.md
│ ├── ReleaseProcess.md
│ ├── SourceOutline.md
│ └── allocator_usage.md
└── unittests/
├── 32Bit_ASM/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Disabled_Tests_Simulator
│ ├── Disabled_Tests_host
│ ├── FEX_bugs/
│ │ ├── GOT_calculation.asm
│ │ ├── IMUL_garbagedata.asm
│ │ ├── InlineSyscall.asm
│ │ ├── InvertedCarrySet.asm
│ │ ├── LoopAddressSizeCheck.asm
│ │ ├── SignExtendBug.asm
│ │ ├── SubAddrBug.asm
│ │ ├── TelemetryFlags.asm
│ │ ├── VEXW_Bug.asm
│ │ ├── adc.asm
│ │ ├── rep_lods_bug.asm
│ │ └── x87_unordered_cmp_fix_32.asm
│ ├── Known_Failures
│ ├── Primary/
│ │ ├── Loops.asm
│ │ ├── Pop_Segments.asm
│ │ ├── Primary_00.asm
│ │ ├── Primary_00_2.asm
│ │ ├── Primary_00_3.asm
│ │ ├── Primary_27.asm
│ │ ├── Primary_2F.asm
│ │ ├── Primary_37.asm
│ │ ├── Primary_3F.asm
│ │ ├── Primary_60.asm
│ │ ├── Primary_60_2.asm
│ │ ├── Primary_61.asm
│ │ ├── Primary_61_2.asm
│ │ ├── Primary_8C.asm
│ │ ├── Primary_8C_2.asm
│ │ ├── Primary_8D.asm
│ │ ├── Primary_A0.asm
│ │ ├── Primary_A2.asm
│ │ ├── Primary_A6.asm
│ │ ├── Primary_A6_REP.asm
│ │ ├── Primary_A6_REPNE.asm
│ │ ├── Primary_A6_REPNE_Equal.asm
│ │ ├── Primary_A6_REP_Equal.asm
│ │ ├── Primary_A6_REP_Smaller.asm
│ │ ├── Primary_A6_REP_down.asm
│ │ ├── Primary_A6_REP_down_Equal.asm
│ │ ├── Primary_A6_down.asm
│ │ ├── Primary_A7_dword.asm
│ │ ├── Primary_A7_dword_down.asm
│ │ ├── Primary_A7_word.asm
│ │ ├── Primary_A7_word_down.asm
│ │ ├── Primary_AE.asm
│ │ ├── Primary_AE_REP.asm
│ │ ├── Primary_AE_REPNE.asm
│ │ ├── Primary_AE_REPNE_down.asm
│ │ ├── Primary_AE_REP_down.asm
│ │ ├── Primary_AF_REP_dword.asm
│ │ ├── Primary_AF_REP_word.asm
│ │ ├── Primary_C9.asm
│ │ ├── Primary_CE.asm
│ │ ├── Primary_CF.asm
│ │ ├── Primary_D4.asm
│ │ ├── Primary_D5.asm
│ │ ├── Primary_D6.asm
│ │ ├── Primary_E3.asm
│ │ ├── Primary_E8.asm
│ │ ├── Primary_E8_2.asm
│ │ ├── Primary_E9.asm
│ │ ├── Primary_E9_2.asm
│ │ └── Push_Segments.asm
│ ├── PrimaryGroup/
│ │ ├── 3_F6_05.asm
│ │ ├── 5_FF_02.asm
│ │ ├── 5_FF_02_2.asm
│ │ └── 5_FF_02_3.asm
│ ├── Secondary/
│ │ ├── 07_XX_00.asm
│ │ ├── 07_XX_04.asm
│ │ └── 15_XX_0.asm
│ ├── SecondaryModRM/
│ │ ├── Reg_7_1.asm
│ │ └── Reg_7_4_2.asm
│ ├── TwoByte/
│ │ ├── 0F_82.asm
│ │ └── 0F_82_2.asm
│ ├── VEX/
│ │ ├── vgather_qpd_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_4xdisp_overflow.asm
│ │ └── vpgather_qq_256bit_8xdisp_overflow.asm
│ ├── X87/
│ │ ├── D8_00.asm
│ │ ├── D8_01.asm
│ │ ├── D8_04.asm
│ │ ├── D8_05.asm
│ │ ├── D8_06.asm
│ │ ├── D8_07.asm
│ │ ├── D8_C0.asm
│ │ ├── D8_C8.asm
│ │ ├── D8_E0.asm
│ │ ├── D8_E8.asm
│ │ ├── D8_F0.asm
│ │ ├── D8_F0_2.asm
│ │ ├── D8_F8.asm
│ │ ├── D9_00.asm
│ │ ├── D9_02.asm
│ │ ├── D9_03.asm
│ │ ├── D9_05.asm
│ │ ├── D9_06.asm
│ │ ├── D9_06_2.asm
│ │ ├── D9_07.asm
│ │ ├── D9_C0.asm
│ │ ├── D9_C8.asm
│ │ ├── D9_D0.asm
│ │ ├── D9_E0.asm
│ │ ├── D9_E1.asm
│ │ ├── D9_E8.asm
│ │ ├── D9_E9.asm
│ │ ├── D9_EA.asm
│ │ ├── D9_EB.asm
│ │ ├── D9_EC.asm
│ │ ├── D9_ED.asm
│ │ ├── D9_EE.asm
│ │ ├── D9_F0.asm
│ │ ├── D9_F1.asm
│ │ ├── D9_F2.asm
│ │ ├── D9_F3.asm
│ │ ├── D9_F4.asm
│ │ ├── D9_F5.asm
│ │ ├── D9_F6.asm
│ │ ├── D9_F7.asm
│ │ ├── D9_F8.asm
│ │ ├── D9_F9.asm
│ │ ├── D9_FA.asm
│ │ ├── D9_FB.asm
│ │ ├── D9_FC.asm
│ │ ├── D9_FD.asm
│ │ ├── D9_FE.asm
│ │ ├── D9_FF.asm
│ │ ├── DA_00.asm
│ │ ├── DA_01.asm
│ │ ├── DA_04.asm
│ │ ├── DA_05.asm
│ │ ├── DA_06.asm
│ │ ├── DA_07.asm
│ │ ├── DA_C0.asm
│ │ ├── DA_C8.asm
│ │ ├── DA_D0.asm
│ │ ├── DA_D8.asm
│ │ ├── DB_00.asm
│ │ ├── DB_01.asm
│ │ ├── DB_02.asm
│ │ ├── DB_03.asm
│ │ ├── DB_05.asm
│ │ ├── DB_07.asm
│ │ ├── DB_C0.asm
│ │ ├── DB_C8.asm
│ │ ├── DB_D0.asm
│ │ ├── DB_D8.asm
│ │ ├── DB_E2.asm
│ │ ├── DB_E3.asm
│ │ ├── DB_E3_2.asm
│ │ ├── DC_00.asm
│ │ ├── DC_01.asm
│ │ ├── DC_04.asm
│ │ ├── DC_05.asm
│ │ ├── DC_06.asm
│ │ ├── DC_07.asm
│ │ ├── DC_C0.asm
│ │ ├── DC_C8.asm
│ │ ├── DC_E0.asm
│ │ ├── DC_E8.asm
│ │ ├── DC_F0.asm
│ │ ├── DC_F8.asm
│ │ ├── DD_00.asm
│ │ ├── DD_01.asm
│ │ ├── DD_02.asm
│ │ ├── DD_03.asm
│ │ ├── DD_04.asm
│ │ ├── DD_04_2.asm
│ │ ├── DD_07.asm
│ │ ├── DD_C0.asm
│ │ ├── DD_D0.asm
│ │ ├── DD_D8.asm
│ │ ├── DE_00.asm
│ │ ├── DE_01.asm
│ │ ├── DE_04.asm
│ │ ├── DE_05.asm
│ │ ├── DE_06.asm
│ │ ├── DE_07.asm
│ │ ├── DE_C0.asm
│ │ ├── DE_C8.asm
│ │ ├── DE_E0.asm
│ │ ├── DE_E8.asm
│ │ ├── DE_F0.asm
│ │ ├── DE_F8.asm
│ │ ├── DF_00.asm
│ │ ├── DF_01.asm
│ │ ├── DF_02.asm
│ │ ├── DF_03.asm
│ │ ├── DF_05.asm
│ │ ├── DF_07.asm
│ │ ├── DF_C0.asm
│ │ ├── DF_E0.asm
│ │ ├── FST_AddrModes.asm
│ │ ├── RoundingNeg.asm
│ │ ├── RoundingPos.asm
│ │ ├── invalid_div_zero.asm
│ │ ├── invalid_fcos_infinity.asm
│ │ ├── invalid_fist_nan.asm
│ │ ├── invalid_fist_overflow.asm
│ │ ├── invalid_fist_overflow_16bit.asm
│ │ ├── invalid_fist_overflow_32bit.asm
│ │ ├── invalid_fist_overflow_64bit.asm
│ │ ├── invalid_fprem_infinity.asm
│ │ ├── invalid_fptan_infinity.asm
│ │ ├── invalid_fsin_infinity.asm
│ │ ├── invalid_fsincos_infinity.asm
│ │ ├── invalid_infinity_fsub_memory.asm
│ │ ├── invalid_infinity_fsubr_infinity.asm
│ │ ├── invalid_infinity_mul_zero.asm
│ │ ├── invalid_infinity_ops.asm
│ │ ├── invalid_infinity_sub_infinity.asm
│ │ ├── invalid_neg_infinity_sub_neg_infinity.asm
│ │ ├── invalid_reduced_precision.asm
│ │ ├── invalid_simple_test.asm
│ │ ├── invalid_sqrt_negative.asm
│ │ ├── valid_fist_16bit.asm
│ │ └── valid_operation.asm
│ ├── arpl.asm
│ └── arpl_2.asm
├── APITests/
│ ├── Allocator.cpp
│ ├── ArgumentParser.cpp
│ ├── CMakeLists.txt
│ ├── ExtendedVolatileMetadata.cpp
│ ├── FileMappingBaseAddress.cpp
│ ├── Filesystem.cpp
│ ├── InterruptableConditionVariable.cpp
│ ├── StringUtils.cpp
│ └── fextl_function.cpp
├── ASM/
│ ├── 3DNow/
│ │ ├── 0C.asm
│ │ ├── 0D.asm
│ │ ├── 0E.asm
│ │ ├── 1C.asm
│ │ ├── 1D.asm
│ │ ├── 86.asm
│ │ ├── 87.asm
│ │ ├── 8A.asm
│ │ ├── 8E.asm
│ │ ├── 90.asm
│ │ ├── 94.asm
│ │ ├── 96.asm
│ │ ├── 97.asm
│ │ ├── 9A.asm
│ │ ├── 9E.asm
│ │ ├── A0.asm
│ │ ├── A4.asm
│ │ ├── A6.asm
│ │ ├── A7.asm
│ │ ├── AA.asm
│ │ ├── AE.asm
│ │ ├── B0.asm
│ │ ├── B4.asm
│ │ ├── B6.asm
│ │ ├── B7.asm
│ │ ├── BB.asm
│ │ └── BF.asm
│ ├── Atomics/
│ │ ├── adc_atomic16.asm
│ │ ├── adc_atomic32.asm
│ │ ├── adc_atomic64.asm
│ │ ├── neg_atomic16.asm
│ │ ├── neg_atomic32.asm
│ │ ├── neg_atomic64.asm
│ │ ├── not_atomic16.asm
│ │ ├── not_atomic32.asm
│ │ ├── not_atomic64.asm
│ │ ├── sbb_atomic16.asm
│ │ ├── sbb_atomic32.asm
│ │ └── sbb_atomic64.asm
│ ├── CALL.asm
│ ├── CMakeLists.txt
│ ├── ConstProp/
│ │ └── ConstPooling.asm
│ ├── DAZTest.asm
│ ├── Disabled_Tests
│ ├── Disabled_Tests_ARMv8.0
│ ├── Disabled_Tests_ARMv8.2
│ ├── Disabled_Tests_ARMv8.4
│ ├── Disabled_Tests_Simulator
│ ├── Disabled_Tests_host
│ ├── Disabled_Tests_x64
│ ├── Displacement_Encoding.asm
│ ├── FEX_bugs/
│ │ ├── 32bit_syscall.asm
│ │ ├── 3DNow_ModRMSIBDecode.asm
│ │ ├── BEXTR_flags.asm
│ │ ├── BLSI_flags.asm
│ │ ├── BLSMSK_flags.asm
│ │ ├── BLSR_flags.asm
│ │ ├── BT_flags.asm
│ │ ├── BZHI_Sign.asm
│ │ ├── BitConditionCheck.asm
│ │ ├── Blake3.asm
│ │ ├── BranchConditionCheck.asm
│ │ ├── CodeBufferOverflow.asm
│ │ ├── Divide32.asm
│ │ ├── H0F3AREXBug.asm
│ │ ├── IMUL_garbagedata_negative.asm
│ │ ├── InitialPFFlag.asm
│ │ ├── LargeRotatesForSmallSizes.asm
│ │ ├── LargeRotatesForSmallSizes_More.asm
│ │ ├── LoadAtBoundary_LowerPrecision.asm
│ │ ├── LongSignedDivide.asm
│ │ ├── LoopAddressSizeCheck.asm
│ │ ├── MinMaxNaN.asm
│ │ ├── MoveMerging.asm
│ │ ├── NegativeCallAddressSizeOverride.asm
│ │ ├── OptSizeConfusion.asm
│ │ ├── PSRLDQBuf.asm
│ │ ├── Push.asm
│ │ ├── REX/
│ │ │ ├── 0F_38.asm
│ │ │ ├── 0F_3A.asm
│ │ │ ├── DDDNow.asm
│ │ │ ├── Primary.asm
│ │ │ ├── Primary_2.asm
│ │ │ └── TwoByte.asm
│ │ ├── RegCacheMMX.asm
│ │ ├── SBCSmall.asm
│ │ ├── SHRD_OF.asm
│ │ ├── SIBScaleTranspose.asm
│ │ ├── SegmentAddressOverride.asm
│ │ ├── SelfPop.asm
│ │ ├── ShiftConstantBug.asm
│ │ ├── ShiftPF.asm
│ │ ├── ShiftZeroFlagsUpdate.asm
│ │ ├── SmallShiftFlags.asm
│ │ ├── Test_CmpSelect_Merge.asm
│ │ ├── Test_CmpSelect_Merge_Float.asm
│ │ ├── Test_CmpSelect_Merge_Float_branch.asm
│ │ ├── Test_CmpSelect_Merge_branch.asm
│ │ ├── Test_JP.asm
│ │ ├── Test_PF_Zero_Shift.asm
│ │ ├── TrickyRA.asm
│ │ ├── UnalignedLoadStoreSIGBUS.asm
│ │ ├── VectorLoadCrash.asm
│ │ ├── VectorShift_zero.asm
│ │ ├── VectorShift_zero_256.asm
│ │ ├── VectorShift_zero_avx_128.asm
│ │ ├── X87MMXNZCV.asm
│ │ ├── XeSS_quadratic.asm
│ │ ├── adcx_size.asm
│ │ ├── add_sub_carry.asm
│ │ ├── add_sub_carry_2.asm
│ │ ├── cmpxchg.asm
│ │ ├── fnsave_fnrstor_size.asm
│ │ ├── fxrstor_bug.asm
│ │ ├── fxsave_bug.asm
│ │ ├── issue5084_crossblock_const.asm
│ │ ├── mmx_x87_register_conflating.asm
│ │ ├── mov_address_size_override.asm
│ │ ├── non_fatal_syscall.asm
│ │ ├── nzcv_implicit_clobber.asm
│ │ ├── nzcv_rmw.asm
│ │ ├── nzcv_spill_enderlilies.asm
│ │ ├── overlapping_memcpy_bug.asm
│ │ ├── pcmpestri_garbage_rcx.asm
│ │ ├── repeat_on_incdec.asm
│ │ ├── repeat_stringops_crash.asm
│ │ ├── rex_b_mmx.asm
│ │ ├── rotate_zero_extend_with_zero.asm
│ │ ├── sbbNZCVBug.asm
│ │ ├── smallvectorload_regreg.asm
│ │ ├── tls_vector_element.asm
│ │ ├── vcvtdq2ps_incorrect_size.asm
│ │ ├── vgather_xmm4.asm
│ │ ├── vmov_size_test.asm
│ │ ├── vroundscalar_sve256.asm
│ │ ├── x87DecrementStackBug.asm
│ │ ├── x87IncrementStackBug.asm
│ │ ├── x87_fprem.asm
│ │ ├── x87_integer_indefinite.asm
│ │ ├── x87_unordered_cmp_fix.asm
│ │ ├── xor_flags.asm
│ │ └── zero-ah.asm
│ ├── Flags/
│ │ └── Shift.asm
│ ├── GameTests/
│ │ └── EnderLiliesFlash.asm
│ ├── H0F38/
│ │ ├── 0_F0.asm
│ │ ├── 0_F1.asm
│ │ ├── 66_00.asm
│ │ ├── 66_00_2.asm
│ │ ├── 66_01.asm
│ │ ├── 66_02.asm
│ │ ├── 66_03.asm
│ │ ├── 66_04.asm
│ │ ├── 66_05.asm
│ │ ├── 66_06.asm
│ │ ├── 66_07.asm
│ │ ├── 66_08.asm
│ │ ├── 66_09.asm
│ │ ├── 66_0A.asm
│ │ ├── 66_0B.asm
│ │ ├── 66_10.asm
│ │ ├── 66_14.asm
│ │ ├── 66_15.asm
│ │ ├── 66_17.asm
│ │ ├── 66_17_2.asm
│ │ ├── 66_1C.asm
│ │ ├── 66_1D.asm
│ │ ├── 66_1E.asm
│ │ ├── 66_20.asm
│ │ ├── 66_21.asm
│ │ ├── 66_22.asm
│ │ ├── 66_23.asm
│ │ ├── 66_24.asm
│ │ ├── 66_25.asm
│ │ ├── 66_28.asm
│ │ ├── 66_29.asm
│ │ ├── 66_2A.asm
│ │ ├── 66_2B.asm
│ │ ├── 66_30.asm
│ │ ├── 66_31.asm
│ │ ├── 66_32.asm
│ │ ├── 66_33.asm
│ │ ├── 66_34.asm
│ │ ├── 66_35.asm
│ │ ├── 66_37.asm
│ │ ├── 66_38.asm
│ │ ├── 66_39.asm
│ │ ├── 66_3A.asm
│ │ ├── 66_3B.asm
│ │ ├── 66_3C.asm
│ │ ├── 66_3D.asm
│ │ ├── 66_3E.asm
│ │ ├── 66_3F.asm
│ │ ├── 66_40.asm
│ │ ├── 66_41.asm
│ │ ├── 66_DB.asm
│ │ ├── 66_DC.asm
│ │ ├── 66_DD.asm
│ │ ├── 66_DE.asm
│ │ ├── 66_DF.asm
│ │ ├── 66_F0.asm
│ │ ├── 66_F0_2.asm
│ │ ├── 66_F1.asm
│ │ ├── 66_F1_2.asm
│ │ ├── 66_F1_3.asm
│ │ ├── F2_F0.asm
│ │ ├── F2_F1.asm
│ │ ├── XX_00.asm
│ │ ├── XX_00_2.asm
│ │ ├── XX_01.asm
│ │ ├── XX_02.asm
│ │ ├── XX_03.asm
│ │ ├── XX_04.asm
│ │ ├── XX_05.asm
│ │ ├── XX_06.asm
│ │ ├── XX_07.asm
│ │ ├── XX_08.asm
│ │ ├── XX_09.asm
│ │ ├── XX_0A.asm
│ │ ├── XX_0B.asm
│ │ ├── XX_1C.asm
│ │ ├── XX_1D.asm
│ │ ├── XX_1E.asm
│ │ ├── adcx.asm
│ │ ├── adox.asm
│ │ ├── sha1msg1.asm
│ │ ├── sha1msg2.asm
│ │ ├── sha1nexte.asm
│ │ ├── sha256msg1.asm
│ │ ├── sha256msg2.asm
│ │ └── sha256rnds2.asm
│ ├── H0F3A/
│ │ ├── 0_66_0F.asm
│ │ ├── 0_66_21.asm
│ │ ├── 0_66_DF.asm
│ │ ├── 0_XX_0F.asm
│ │ ├── 66_08.asm
│ │ ├── 66_09.asm
│ │ ├── 66_0A.asm
│ │ ├── 66_0B.asm
│ │ ├── 66_0C.asm
│ │ ├── 66_0D.asm
│ │ ├── 66_0E.asm
│ │ ├── 66_14.asm
│ │ ├── 66_14_2.asm
│ │ ├── 66_15.asm
│ │ ├── 66_16.asm
│ │ ├── 66_16_1.asm
│ │ ├── 66_17.asm
│ │ ├── 66_20.asm
│ │ ├── 66_20_1.asm
│ │ ├── 66_22.asm
│ │ ├── 66_22_1.asm
│ │ ├── 66_22_2.asm
│ │ ├── 66_40.asm
│ │ ├── 66_40_2.asm
│ │ ├── 66_41.asm
│ │ ├── 66_41_2.asm
│ │ ├── 66_42.asm
│ │ ├── pclmulqdq.asm
│ │ ├── pcmpestri_equal_any.asm
│ │ ├── pcmpestri_equal_each.asm
│ │ ├── pcmpestri_equal_ordered.asm
│ │ ├── pcmpestri_ranges.asm
│ │ ├── pcmpestrm_equal_any.asm
│ │ ├── pcmpestrm_equal_each.asm
│ │ ├── pcmpestrm_equal_ordered.asm
│ │ ├── pcmpestrm_ranges.asm
│ │ ├── pcmpistri_equal_any.asm
│ │ ├── pcmpistri_equal_each.asm
│ │ ├── pcmpistri_equal_ordered.asm
│ │ ├── pcmpistri_ranges.asm
│ │ ├── pcmpistrm_equal_any.asm
│ │ ├── pcmpistrm_equal_each.asm
│ │ ├── pcmpistrm_equal_ordered.asm
│ │ ├── pcmpistrm_ranges.asm
│ │ └── sha1rnds4.asm
│ ├── Includes/
│ │ ├── checkprecision.mac
│ │ ├── modrm_oob_macros.mac
│ │ ├── x87cw.mac
│ │ └── xsave_macros.mac
│ ├── JMP.asm
│ ├── Known_Failures
│ ├── Known_Failures_host
│ ├── Known_Failures_jit
│ ├── MOVHPD.asm
│ ├── MemoryData.asm
│ ├── Multiblock/
│ │ └── ReachableInvalidCode.asm
│ ├── OpSize/
│ │ ├── 15_BYTE.asm
│ │ ├── 66_10.asm
│ │ ├── 66_11.asm
│ │ ├── 66_12.asm
│ │ ├── 66_13.asm
│ │ ├── 66_14.asm
│ │ ├── 66_15.asm
│ │ ├── 66_16.asm
│ │ ├── 66_17.asm
│ │ ├── 66_28.asm
│ │ ├── 66_29.asm
│ │ ├── 66_2A.asm
│ │ ├── 66_2B.asm
│ │ ├── 66_2C.asm
│ │ ├── 66_2D.asm
│ │ ├── 66_2E.asm
│ │ ├── 66_2F.asm
│ │ ├── 66_50.asm
│ │ ├── 66_51.asm
│ │ ├── 66_54.asm
│ │ ├── 66_55.asm
│ │ ├── 66_56.asm
│ │ ├── 66_57.asm
│ │ ├── 66_58.asm
│ │ ├── 66_59.asm
│ │ ├── 66_5A.asm
│ │ ├── 66_5A_1.asm
│ │ ├── 66_5B.asm
│ │ ├── 66_5B_1.asm
│ │ ├── 66_5C.asm
│ │ ├── 66_5D.asm
│ │ ├── 66_5E.asm
│ │ ├── 66_5F.asm
│ │ ├── 66_60.asm
│ │ ├── 66_61.asm
│ │ ├── 66_62.asm
│ │ ├── 66_63.asm
│ │ ├── 66_64.asm
│ │ ├── 66_65.asm
│ │ ├── 66_66.asm
│ │ ├── 66_67.asm
│ │ ├── 66_68.asm
│ │ ├── 66_69.asm
│ │ ├── 66_6A.asm
│ │ ├── 66_6B.asm
│ │ ├── 66_6C.asm
│ │ ├── 66_6D.asm
│ │ ├── 66_6E.asm
│ │ ├── 66_6F.asm
│ │ ├── 66_70.asm
│ │ ├── 66_74.asm
│ │ ├── 66_75.asm
│ │ ├── 66_76.asm
│ │ ├── 66_7C.asm
│ │ ├── 66_7D.asm
│ │ ├── 66_7E.asm
│ │ ├── 66_7F.asm
│ │ ├── 66_C2.asm
│ │ ├── 66_C4.asm
│ │ ├── 66_C4_2.asm
│ │ ├── 66_C5.asm
│ │ ├── 66_C5_2.asm
│ │ ├── 66_C6.asm
│ │ ├── 66_D0.asm
│ │ ├── 66_D1.asm
│ │ ├── 66_D2.asm
│ │ ├── 66_D3.asm
│ │ ├── 66_D4.asm
│ │ ├── 66_D5.asm
│ │ ├── 66_D6.asm
│ │ ├── 66_D7.asm
│ │ ├── 66_D8.asm
│ │ ├── 66_D9.asm
│ │ ├── 66_DA.asm
│ │ ├── 66_DB.asm
│ │ ├── 66_DC.asm
│ │ ├── 66_DD.asm
│ │ ├── 66_DE.asm
│ │ ├── 66_DF.asm
│ │ ├── 66_E0.asm
│ │ ├── 66_E1.asm
│ │ ├── 66_E2.asm
│ │ ├── 66_E3.asm
│ │ ├── 66_E4.asm
│ │ ├── 66_E5.asm
│ │ ├── 66_E6.asm
│ │ ├── 66_E6_1.asm
│ │ ├── 66_E7.asm
│ │ ├── 66_E8.asm
│ │ ├── 66_E9.asm
│ │ ├── 66_EA.asm
│ │ ├── 66_EB.asm
│ │ ├── 66_EC.asm
│ │ ├── 66_ED.asm
│ │ ├── 66_EE.asm
│ │ ├── 66_EF.asm
│ │ ├── 66_F1.asm
│ │ ├── 66_F2.asm
│ │ ├── 66_F3.asm
│ │ ├── 66_F4.asm
│ │ ├── 66_F5.asm
│ │ ├── 66_F6.asm
│ │ ├── 66_F7.asm
│ │ ├── 66_F8.asm
│ │ ├── 66_F9.asm
│ │ ├── 66_FA.asm
│ │ ├── 66_FB.asm
│ │ ├── 66_FC.asm
│ │ ├── 66_FD.asm
│ │ └── 66_FE.asm
│ ├── Primary/
│ │ ├── Pause.asm
│ │ ├── Primary_00.asm
│ │ ├── Primary_01_Atomic16.asm
│ │ ├── Primary_01_Atomic32.asm
│ │ ├── Primary_01_Atomic64.asm
│ │ ├── Primary_08.asm
│ │ ├── Primary_09_Atomic16.asm
│ │ ├── Primary_09_Atomic32.asm
│ │ ├── Primary_09_Atomic64.asm
│ │ ├── Primary_10.asm
│ │ ├── Primary_10_2.asm
│ │ ├── Primary_10_3.asm
│ │ ├── Primary_10_4.asm
│ │ ├── Primary_18.asm
│ │ ├── Primary_18_2.asm
│ │ ├── Primary_18_3.asm
│ │ ├── Primary_18_4.asm
│ │ ├── Primary_20.asm
│ │ ├── Primary_23_Atomic16.asm
│ │ ├── Primary_23_Atomic32.asm
│ │ ├── Primary_23_Atomic64.asm
│ │ ├── Primary_28.asm
│ │ ├── Primary_29_Atomic16.asm
│ │ ├── Primary_29_Atomic32.asm
│ │ ├── Primary_29_Atomic64.asm
│ │ ├── Primary_30.asm
│ │ ├── Primary_31_Atomic16.asm
│ │ ├── Primary_31_Atomic32.asm
│ │ ├── Primary_31_Atomic64.asm
│ │ ├── Primary_38.asm
│ │ ├── Primary_39.asm
│ │ ├── Primary_3A.asm
│ │ ├── Primary_3B.asm
│ │ ├── Primary_3C.asm
│ │ ├── Primary_3D.asm
│ │ ├── Primary_50.asm
│ │ ├── Primary_50_2.asm
│ │ ├── Primary_63.asm
│ │ ├── Primary_63_2.asm
│ │ ├── Primary_68.asm
│ │ ├── Primary_69.asm
│ │ ├── Primary_6A.asm
│ │ ├── Primary_6A_2.asm
│ │ ├── Primary_6B.asm
│ │ ├── Primary_84.asm
│ │ ├── Primary_84_2.asm
│ │ ├── Primary_85.asm
│ │ ├── Primary_86.asm
│ │ ├── Primary_87.asm
│ │ ├── Primary_87_2.asm
│ │ ├── Primary_87_3.asm
│ │ ├── Primary_87_Atomic16.asm
│ │ ├── Primary_87_Atomic32.asm
│ │ ├── Primary_87_Atomic64.asm
│ │ ├── Primary_8C.asm
│ │ ├── Primary_8C_2.asm
│ │ ├── Primary_8D.asm
│ │ ├── Primary_8D_2.asm
│ │ ├── Primary_90.asm
│ │ ├── Primary_90_2.asm
│ │ ├── Primary_90_3.asm
│ │ ├── Primary_90_4.asm
│ │ ├── Primary_98.asm
│ │ ├── Primary_98_2.asm
│ │ ├── Primary_99.asm
│ │ ├── Primary_99_2.asm
│ │ ├── Primary_9B.asm
│ │ ├── Primary_9C.asm
│ │ ├── Primary_9D.asm
│ │ ├── Primary_9E.asm
│ │ ├── Primary_A0.asm
│ │ ├── Primary_A2.asm
│ │ ├── Primary_A4.asm
│ │ ├── Primary_A4_REP.asm
│ │ ├── Primary_A4_REPNE.asm
│ │ ├── Primary_A4_REPNE_Down.asm
│ │ ├── Primary_A4_REPNE_many.asm
│ │ ├── Primary_A4_REP_Down.asm
│ │ ├── Primary_A4_REP_Down_Overlapping.asm
│ │ ├── Primary_A4_REP_Overlapping.asm
│ │ ├── Primary_A4_REP_many.asm
│ │ ├── Primary_A5.asm
│ │ ├── Primary_A5_REP.asm
│ │ ├── Primary_A5_REPNE.asm
│ │ ├── Primary_A5_REPNE_Down.asm
│ │ ├── Primary_A5_REP_Down.asm
│ │ ├── Primary_A5_dword.asm
│ │ ├── Primary_A5_dword_REP.asm
│ │ ├── Primary_A5_dword_REPNE.asm
│ │ ├── Primary_A5_dword_REPNE_Down.asm
│ │ ├── Primary_A5_dword_REP_Down.asm
│ │ ├── Primary_A5_qword.asm
│ │ ├── Primary_A5_qword_REP.asm
│ │ ├── Primary_A5_qword_REPNE.asm
│ │ ├── Primary_A5_qword_REPNE_Down.asm
│ │ ├── Primary_A5_qword_REP_Down.asm
│ │ ├── Primary_A6.asm
│ │ ├── Primary_A6_REP.asm
│ │ ├── Primary_A6_REPNE.asm
│ │ ├── Primary_A6_REPNE_Equal.asm
│ │ ├── Primary_A6_REP_Equal.asm
│ │ ├── Primary_A6_REP_Smaller.asm
│ │ ├── Primary_A6_REP_addrmod.asm
│ │ ├── Primary_A6_REP_down.asm
│ │ ├── Primary_A6_REP_down_Equal.asm
│ │ ├── Primary_A6_addrmod.asm
│ │ ├── Primary_A6_down.asm
│ │ ├── Primary_A7_dword.asm
│ │ ├── Primary_A7_dword_down.asm
│ │ ├── Primary_A7_qword.asm
│ │ ├── Primary_A7_qword_down.asm
│ │ ├── Primary_A7_word.asm
│ │ ├── Primary_A7_word_down.asm
│ │ ├── Primary_A8.asm
│ │ ├── Primary_A9.asm
│ │ ├── Primary_AA.asm
│ │ ├── Primary_AA_REP.asm
│ │ ├── Primary_AA_REPNE.asm
│ │ ├── Primary_AA_REPNE_down.asm
│ │ ├── Primary_AA_REP_down.asm
│ │ ├── Primary_AB_dword.asm
│ │ ├── Primary_AB_dword_REP.asm
│ │ ├── Primary_AB_dword_REPNE.asm
│ │ ├── Primary_AB_dword_REPNE_down.asm
│ │ ├── Primary_AB_dword_REP_down.asm
│ │ ├── Primary_AB_qword.asm
│ │ ├── Primary_AB_qword_REP.asm
│ │ ├── Primary_AB_qword_REPNE.asm
│ │ ├── Primary_AB_qword_REPNE_down.asm
│ │ ├── Primary_AB_qword_REP_down.asm
│ │ ├── Primary_AB_word.asm
│ │ ├── Primary_AB_word_REP.asm
│ │ ├── Primary_AB_word_REPNE.asm
│ │ ├── Primary_AB_word_REPNE_down.asm
│ │ ├── Primary_AB_word_REP_down.asm
│ │ ├── Primary_AC.asm
│ │ ├── Primary_AC_REP.asm
│ │ ├── Primary_AC_REPNE.asm
│ │ ├── Primary_AC_REPNE_down.asm
│ │ ├── Primary_AC_REP_down.asm
│ │ ├── Primary_AD_REPNE_dword.asm
│ │ ├── Primary_AD_REPNE_dword_down.asm
│ │ ├── Primary_AD_REPNE_qword.asm
│ │ ├── Primary_AD_REPNE_qword_down.asm
│ │ ├── Primary_AD_REPNE_word.asm
│ │ ├── Primary_AD_REPNE_word_down.asm
│ │ ├── Primary_AD_REP_dword.asm
│ │ ├── Primary_AD_REP_dword_down.asm
│ │ ├── Primary_AD_REP_qword.asm
│ │ ├── Primary_AD_REP_qword_down.asm
│ │ ├── Primary_AD_REP_word.asm
│ │ ├── Primary_AD_REP_word_down.asm
│ │ ├── Primary_AD_dword.asm
│ │ ├── Primary_AD_qword.asm
│ │ ├── Primary_AD_word.asm
│ │ ├── Primary_AE.asm
│ │ ├── Primary_AE_REP.asm
│ │ ├── Primary_AE_REPNE.asm
│ │ ├── Primary_AE_REPNE_down.asm
│ │ ├── Primary_AE_REP_down.asm
│ │ ├── Primary_AE_addrmod.asm
│ │ ├── Primary_AF_REP_dword.asm
│ │ ├── Primary_AF_REP_qword.asm
│ │ ├── Primary_AF_REP_word.asm
│ │ ├── Primary_B0.asm
│ │ ├── Primary_B8.asm
│ │ ├── Primary_B8_2.asm
│ │ ├── Primary_B8_3.asm
│ │ ├── Primary_C2.asm
│ │ ├── Primary_C3.asm
│ │ ├── Primary_C8.asm
│ │ ├── Primary_C8_2.asm
│ │ ├── Primary_C8_o16.asm
│ │ ├── Primary_C9.asm
│ │ ├── Primary_C9_o16.asm
│ │ ├── Primary_CF.asm
│ │ ├── Primary_D7.asm
│ │ ├── Primary_E0.asm
│ │ ├── Primary_E1.asm
│ │ ├── Primary_E2.asm
│ │ ├── Primary_E3.asm
│ │ ├── Primary_E8.asm
│ │ ├── Primary_E9.asm
│ │ ├── Primary_EB.asm
│ │ ├── Primary_F5.asm
│ │ ├── Primary_F8.asm
│ │ ├── Primary_F9.asm
│ │ ├── Primary_FC.asm
│ │ ├── Primary_FD.asm
│ │ ├── Primary_FF_0_Atomic16.asm
│ │ ├── Primary_FF_0_Atomic32.asm
│ │ ├── Primary_FF_0_Atomic64.asm
│ │ ├── Primary_FF_1_Atomic16.asm
│ │ ├── Primary_FF_1_Atomic32.asm
│ │ ├── Primary_FF_1_Atomic64.asm
│ │ ├── ROL_Flags.asm
│ │ ├── ROL_OF.asm
│ │ ├── ROR_Flags.asm
│ │ ├── ROR_OF.asm
│ │ ├── SHL.asm
│ │ └── SHR.asm
│ ├── PrimaryGroup/
│ │ ├── 1_80_00.asm
│ │ ├── 1_80_01.asm
│ │ ├── 1_80_02.asm
│ │ ├── 1_80_02_2.asm
│ │ ├── 1_80_03.asm
│ │ ├── 1_80_03_2.asm
│ │ ├── 1_80_04.asm
│ │ ├── 1_80_05.asm
│ │ ├── 1_80_06.asm
│ │ ├── 1_80_07.asm
│ │ ├── 1_81_00.asm
│ │ ├── 1_81_01.asm
│ │ ├── 1_81_02.asm
│ │ ├── 1_81_02_2.asm
│ │ ├── 1_81_03.asm
│ │ ├── 1_81_03_2.asm
│ │ ├── 1_81_04.asm
│ │ ├── 1_81_05.asm
│ │ ├── 1_81_06.asm
│ │ ├── 1_81_07.asm
│ │ ├── 1_83_00.asm
│ │ ├── 1_83_01.asm
│ │ ├── 1_83_02.asm
│ │ ├── 1_83_02_2.asm
│ │ ├── 1_83_03.asm
│ │ ├── 1_83_03_2.asm
│ │ ├── 1_83_04.asm
│ │ ├── 1_83_05.asm
│ │ ├── 1_83_06.asm
│ │ ├── 1_83_07.asm
│ │ ├── 2_C0_00.asm
│ │ ├── 2_C0_01.asm
│ │ ├── 2_C0_02.asm
│ │ ├── 2_C0_02_2.asm
│ │ ├── 2_C0_02_3.asm
│ │ ├── 2_C0_02_4.asm
│ │ ├── 2_C0_03.asm
│ │ ├── 2_C0_03_2.asm
│ │ ├── 2_C0_03_3.asm
│ │ ├── 2_C0_03_4.asm
│ │ ├── 2_C0_04.asm
│ │ ├── 2_C0_05.asm
│ │ ├── 2_C0_07.asm
│ │ ├── 2_C0_07_2.asm
│ │ ├── 2_C1_00.asm
│ │ ├── 2_C1_01.asm
│ │ ├── 2_C1_04.asm
│ │ ├── 2_C1_05.asm
│ │ ├── 2_C1_05_2.asm
│ │ ├── 2_C1_07.asm
│ │ ├── 2_D0_00.asm
│ │ ├── 2_D0_01.asm
│ │ ├── 2_D0_02.asm
│ │ ├── 2_D0_02_2.asm
│ │ ├── 2_D0_03.asm
│ │ ├── 2_D0_03_2.asm
│ │ ├── 2_D0_04.asm
│ │ ├── 2_D0_05.asm
│ │ ├── 2_D0_07.asm
│ │ ├── 2_D1_00.asm
│ │ ├── 2_D1_01.asm
│ │ ├── 2_D1_02.asm
│ │ ├── 2_D1_02_2.asm
│ │ ├── 2_D1_02_3.asm
│ │ ├── 2_D1_02_4.asm
│ │ ├── 2_D1_02_5.asm
│ │ ├── 2_D1_02_6.asm
│ │ ├── 2_D1_03.asm
│ │ ├── 2_D1_03_2.asm
│ │ ├── 2_D1_03_3.asm
│ │ ├── 2_D1_03_4.asm
│ │ ├── 2_D1_03_5.asm
│ │ ├── 2_D1_03_6.asm
│ │ ├── 2_D1_04.asm
│ │ ├── 2_D1_05.asm
│ │ ├── 2_D1_07.asm
│ │ ├── 2_D1_07_2.asm
│ │ ├── 2_D2_02.asm
│ │ ├── 2_D2_02_2.asm
│ │ ├── 2_D2_02_3.asm
│ │ ├── 2_D2_03.asm
│ │ ├── 2_D2_03_2.asm
│ │ ├── 2_D2_03_3.asm
│ │ ├── 2_D3_00.asm
│ │ ├── 2_D3_00_2.asm
│ │ ├── 2_D3_00_3.asm
│ │ ├── 2_D3_01.asm
│ │ ├── 2_D3_01_2.asm
│ │ ├── 2_D3_01_3.asm
│ │ ├── 2_D3_02.asm
│ │ ├── 2_D3_02_2.asm
│ │ ├── 2_D3_02_3.asm
│ │ ├── 2_D3_02_4.asm
│ │ ├── 2_D3_02_5.asm
│ │ ├── 2_D3_03.asm
│ │ ├── 2_D3_03_2.asm
│ │ ├── 2_D3_03_3.asm
│ │ ├── 2_D3_03_4.asm
│ │ ├── 2_D3_03_5.asm
│ │ ├── 2_D3_03_6.asm
│ │ ├── 2_D3_03_7.asm
│ │ ├── 2_D3_03_8.asm
│ │ ├── 2_D3_04.asm
│ │ ├── 2_D3_05.asm
│ │ ├── 2_D3_07.asm
│ │ ├── 2_D3_07_2.asm
│ │ ├── 3_F6_00.asm
│ │ ├── 3_F6_02.asm
│ │ ├── 3_F6_02_2.asm
│ │ ├── 3_F6_03.asm
│ │ ├── 3_F6_03_2.asm
│ │ ├── 3_F6_04.asm
│ │ ├── 3_F6_05.asm
│ │ ├── 3_F6_05_2.asm
│ │ ├── 3_F6_05_3.asm
│ │ ├── 3_F6_05_4.asm
│ │ ├── 3_F6_05_5.asm
│ │ ├── 3_F6_06.asm
│ │ ├── 3_F6_07.asm
│ │ ├── 3_F6_07_2.asm
│ │ ├── 3_F7_00.asm
│ │ ├── 3_F7_00_2.asm
│ │ ├── 3_F7_02.asm
│ │ ├── 3_F7_02_2.asm
│ │ ├── 3_F7_02_3.asm
│ │ ├── 3_F7_03.asm
│ │ ├── 3_F7_03_2.asm
│ │ ├── 3_F7_04.asm
│ │ ├── 3_F7_05.asm
│ │ ├── 3_F7_05_2.asm
│ │ ├── 3_F7_06.asm
│ │ ├── 3_F7_06_2.asm
│ │ ├── 3_F7_07.asm
│ │ ├── 3_F7_07_2.asm
│ │ ├── 4_FE_00.asm
│ │ ├── 4_FE_01.asm
│ │ ├── 5_FF_00.asm
│ │ ├── 5_FF_00_2.asm
│ │ ├── 5_FF_00_3.asm
│ │ ├── 5_FF_01.asm
│ │ ├── 5_FF_01_2.asm
│ │ ├── 5_FF_01_3.asm
│ │ ├── 5_FF_02.asm
│ │ ├── 5_FF_04.asm
│ │ ├── 5_FF_05.asm
│ │ ├── 5_FF_05_03_o32.asm
│ │ ├── 5_FF_05_03_o32_imm.asm
│ │ ├── 5_FF_05_03_o64.asm
│ │ ├── 5_FF_05_03_o64_imm.asm
│ │ ├── 5_FF_06.asm
│ │ ├── 6_C6_00.asm
│ │ └── 6_C7_00.asm
│ ├── REP/
│ │ ├── F3_10.asm
│ │ ├── F3_10_1.asm
│ │ ├── F3_11.asm
│ │ ├── F3_11_1.asm
│ │ ├── F3_12.asm
│ │ ├── F3_16.asm
│ │ ├── F3_2A.asm
│ │ ├── F3_2A_1.asm
│ │ ├── F3_2A_2.asm
│ │ ├── F3_2B.asm
│ │ ├── F3_2C.asm
│ │ ├── F3_2D.asm
│ │ ├── F3_51.asm
│ │ ├── F3_52.asm
│ │ ├── F3_52_2.asm
│ │ ├── F3_53.asm
│ │ ├── F3_58.asm
│ │ ├── F3_59.asm
│ │ ├── F3_5A.asm
│ │ ├── F3_5A_1.asm
│ │ ├── F3_5B.asm
│ │ ├── F3_5B_1.asm
│ │ ├── F3_5C.asm
│ │ ├── F3_5D.asm
│ │ ├── F3_5E.asm
│ │ ├── F3_5F.asm
│ │ ├── F3_6F.asm
│ │ ├── F3_70.asm
│ │ ├── F3_7E.asm
│ │ ├── F3_7F.asm
│ │ ├── F3_B8.asm
│ │ ├── F3_BC.asm
│ │ ├── F3_BD.asm
│ │ ├── F3_BD_2.asm
│ │ ├── F3_BD_3.asm
│ │ ├── F3_BD_4.asm
│ │ ├── F3_C2.asm
│ │ ├── F3_D6.asm
│ │ ├── F3_E6.asm
│ │ └── F3_E6_1.asm
│ ├── REPNE/
│ │ ├── F2_10.asm
│ │ ├── F2_11.asm
│ │ ├── F2_12.asm
│ │ ├── F2_2A.asm
│ │ ├── F2_2A_1.asm
│ │ ├── F2_2B.asm
│ │ ├── F2_2C.asm
│ │ ├── F2_2D.asm
│ │ ├── F2_2D_1.asm
│ │ ├── F2_51.asm
│ │ ├── F2_58.asm
│ │ ├── F2_59.asm
│ │ ├── F2_5A.asm
│ │ ├── F2_5A_1.asm
│ │ ├── F2_5C.asm
│ │ ├── F2_5D.asm
│ │ ├── F2_5E.asm
│ │ ├── F2_5F.asm
│ │ ├── F2_70.asm
│ │ ├── F2_7C.asm
│ │ ├── F2_7D.asm
│ │ ├── F2_C2.asm
│ │ ├── F2_D0.asm
│ │ ├── F2_D6.asm
│ │ ├── F2_E6.asm
│ │ ├── F2_E6_1.asm
│ │ └── F2_F0.asm
│ ├── SSE4a/
│ │ ├── extrq_imm.asm
│ │ ├── extrq_variable.asm
│ │ ├── insertq_imm.asm
│ │ └── insertq_variable.asm
│ ├── STOS.asm
│ ├── STOSQ.asm
│ ├── STOSQ2.asm
│ ├── STOSQ2_REPNE.asm
│ ├── STOSQ_REPNE.asm
│ ├── STOS_REPNE.asm
│ ├── Secondary/
│ │ ├── 07_XX_00.asm
│ │ ├── 07_XX_04.asm
│ │ ├── 08_66_04.asm
│ │ ├── 08_66_04_2.asm
│ │ ├── 08_F2_04.asm
│ │ ├── 08_F2_04_2.asm
│ │ ├── 08_F2_07.asm
│ │ ├── 08_F3_04.asm
│ │ ├── 08_F3_04_2.asm
│ │ ├── 08_XX_04.asm
│ │ ├── 08_XX_04_2.asm
│ │ ├── 08_XX_04_3.asm
│ │ ├── 08_XX_05.asm
│ │ ├── 08_XX_05_2.asm
│ │ ├── 08_XX_05_3.asm
│ │ ├── 08_XX_05_3_Atomic.asm
│ │ ├── 08_XX_05_Atomic.asm
│ │ ├── 08_XX_06.asm
│ │ ├── 08_XX_06_2.asm
│ │ ├── 08_XX_06_3.asm
│ │ ├── 08_XX_06_3_Atomic.asm
│ │ ├── 08_XX_06_Atomic.asm
│ │ ├── 08_XX_07.asm
│ │ ├── 08_XX_07_2.asm
│ │ ├── 08_XX_07_3.asm
│ │ ├── 08_XX_07_3_Atomic.asm
│ │ ├── 08_XX_07_Atomic.asm
│ │ ├── 09_F3_07.asm
│ │ ├── 09_XX_01.asm
│ │ ├── 09_XX_01_10.asm
│ │ ├── 09_XX_01_11.asm
│ │ ├── 09_XX_01_12.asm
│ │ ├── 09_XX_01_13.asm
│ │ ├── 09_XX_01_14.asm
│ │ ├── 09_XX_01_15.asm
│ │ ├── 09_XX_01_16.asm
│ │ ├── 09_XX_01_17.asm
│ │ ├── 09_XX_01_18.asm
│ │ ├── 09_XX_01_19.asm
│ │ ├── 09_XX_01_2.asm
│ │ ├── 09_XX_01_3.asm
│ │ ├── 09_XX_01_4.asm
│ │ ├── 09_XX_01_5.asm
│ │ ├── 09_XX_01_6.asm
│ │ ├── 09_XX_01_7.asm
│ │ ├── 09_XX_01_8.asm
│ │ ├── 09_XX_01_9.asm
│ │ ├── 09_XX_06.asm
│ │ ├── 09_XX_07.asm
│ │ ├── 12_66_02.asm
│ │ ├── 12_66_04.asm
│ │ ├── 12_66_06.asm
│ │ ├── 13_66_02.asm
│ │ ├── 13_66_04.asm
│ │ ├── 13_66_06.asm
│ │ ├── 14_66_02.asm
│ │ ├── 14_66_06.asm
│ │ ├── 14_66_07.asm
│ │ ├── 14_XX_02.asm
│ │ ├── 15_F3_00.asm
│ │ ├── 15_F3_01.asm
│ │ ├── 15_F3_02.asm
│ │ ├── 15_F3_02_2.asm
│ │ ├── 15_F3_03.asm
│ │ ├── 15_F3_03_2.asm
│ │ ├── 15_XX_0.asm
│ │ ├── 15_XX_5.asm
│ │ ├── 15_XX_6.asm
│ │ ├── 15_XX_7.asm
│ │ ├── 15_XX_7_2.asm
│ │ ├── CLFLUSHOPT.asm
│ │ ├── CLWB.asm
│ │ ├── Prefetch.asm
│ │ ├── shufps_optimization.asm
│ │ ├── shufps_optimization_2.asm
│ │ └── xsave/
│ │ ├── xsave.asm
│ │ ├── xsave_avx.asm
│ │ ├── xsave_avx_x87.asm
│ │ ├── xsave_sse.asm
│ │ └── xsave_x87.asm
│ ├── SecondaryModRM/
│ │ ├── Reg_2_0.asm
│ │ ├── Reg_7_1.asm
│ │ ├── Reg_7_4.asm
│ │ └── Reg_7_4_2.asm
│ ├── SelfModifyingCode/
│ │ ├── Delinking.asm
│ │ ├── DifferentBlock.asm
│ │ └── SameBlock.asm
│ ├── TwoByte/
│ │ ├── 0F_02.asm
│ │ ├── 0F_0E.asm
│ │ ├── 0F_10.asm
│ │ ├── 0F_10_2.asm
│ │ ├── 0F_11.asm
│ │ ├── 0F_12.asm
│ │ ├── 0F_13.asm
│ │ ├── 0F_13_2.asm
│ │ ├── 0F_14.asm
│ │ ├── 0F_15.asm
│ │ ├── 0F_16.asm
│ │ ├── 0F_17.asm
│ │ ├── 0F_19.asm
│ │ ├── 0F_28.asm
│ │ ├── 0F_29.asm
│ │ ├── 0F_2A.asm
│ │ ├── 0F_2B.asm
│ │ ├── 0F_2C.asm
│ │ ├── 0F_2D.asm
│ │ ├── 0F_2E.asm
│ │ ├── 0F_2F.asm
│ │ ├── 0F_31.asm
│ │ ├── 0F_40.asm
│ │ ├── 0F_41.asm
│ │ ├── 0F_42.asm
│ │ ├── 0F_43.asm
│ │ ├── 0F_44.asm
│ │ ├── 0F_45.asm
│ │ ├── 0F_46.asm
│ │ ├── 0F_47.asm
│ │ ├── 0F_48.asm
│ │ ├── 0F_49.asm
│ │ ├── 0F_4A.asm
│ │ ├── 0F_4B.asm
│ │ ├── 0F_4C.asm
│ │ ├── 0F_4D.asm
│ │ ├── 0F_4E.asm
│ │ ├── 0F_4F.asm
│ │ ├── 0F_50.asm
│ │ ├── 0F_51.asm
│ │ ├── 0F_52.asm
│ │ ├── 0F_53.asm
│ │ ├── 0F_54.asm
│ │ ├── 0F_55.asm
│ │ ├── 0F_56.asm
│ │ ├── 0F_57.asm
│ │ ├── 0F_58.asm
│ │ ├── 0F_59.asm
│ │ ├── 0F_5A.asm
│ │ ├── 0F_5A_1.asm
│ │ ├── 0F_5B.asm
│ │ ├── 0F_5B_1.asm
│ │ ├── 0F_5C.asm
│ │ ├── 0F_5D.asm
│ │ ├── 0F_5E.asm
│ │ ├── 0F_5F.asm
│ │ ├── 0F_60.asm
│ │ ├── 0F_61.asm
│ │ ├── 0F_62.asm
│ │ ├── 0F_63.asm
│ │ ├── 0F_64.asm
│ │ ├── 0F_65.asm
│ │ ├── 0F_66.asm
│ │ ├── 0F_67.asm
│ │ ├── 0F_68.asm
│ │ ├── 0F_69.asm
│ │ ├── 0F_6A.asm
│ │ ├── 0F_6B.asm
│ │ ├── 0F_6E.asm
│ │ ├── 0F_6E_2.asm
│ │ ├── 0F_6F.asm
│ │ ├── 0F_70.asm
│ │ ├── 0F_74.asm
│ │ ├── 0F_75.asm
│ │ ├── 0F_76.asm
│ │ ├── 0F_77.asm
│ │ ├── 0F_7E.asm
│ │ ├── 0F_7F.asm
│ │ ├── 0F_80.asm
│ │ ├── 0F_81.asm
│ │ ├── 0F_82.asm
│ │ ├── 0F_83.asm
│ │ ├── 0F_84.asm
│ │ ├── 0F_85.asm
│ │ ├── 0F_86.asm
│ │ ├── 0F_87.asm
│ │ ├── 0F_88.asm
│ │ ├── 0F_89.asm
│ │ ├── 0F_8A.asm
│ │ ├── 0F_8B.asm
│ │ ├── 0F_8B_16.asm
│ │ ├── 0F_8B_32.asm
│ │ ├── 0F_8B_64.asm
│ │ ├── 0F_8C.asm
│ │ ├── 0F_8D.asm
│ │ ├── 0F_8E.asm
│ │ ├── 0F_8F.asm
│ │ ├── 0F_90.asm
│ │ ├── 0F_91.asm
│ │ ├── 0F_92.asm
│ │ ├── 0F_93.asm
│ │ ├── 0F_94.asm
│ │ ├── 0F_95.asm
│ │ ├── 0F_96.asm
│ │ ├── 0F_97.asm
│ │ ├── 0F_98.asm
│ │ ├── 0F_99.asm
│ │ ├── 0F_9A.asm
│ │ ├── 0F_9B.asm
│ │ ├── 0F_9C.asm
│ │ ├── 0F_9D.asm
│ │ ├── 0F_9E.asm
│ │ ├── 0F_9F.asm
│ │ ├── 0F_A2.asm
│ │ ├── 0F_A3.asm
│ │ ├── 0F_A3_2.asm
│ │ ├── 0F_A4.asm
│ │ ├── 0F_A4_2.asm
│ │ ├── 0F_A5.asm
│ │ ├── 0F_A5_2.asm
│ │ ├── 0F_A5_3.asm
│ │ ├── 0F_A5_4.asm
│ │ ├── 0F_A5_5.asm
│ │ ├── 0F_A5_6.asm
│ │ ├── 0F_A5_7.asm
│ │ ├── 0F_AB.asm
│ │ ├── 0F_AB_2.asm
│ │ ├── 0F_AB_2_Atomic.asm
│ │ ├── 0F_AB_Atomic.asm
│ │ ├── 0F_AC.asm
│ │ ├── 0F_AC_2.asm
│ │ ├── 0F_AD.asm
│ │ ├── 0F_AD_2.asm
│ │ ├── 0F_AD_3.asm
│ │ ├── 0F_AD_4.asm
│ │ ├── 0F_AD_5.asm
│ │ ├── 0F_AD_6.asm
│ │ ├── 0F_AD_7.asm
│ │ ├── 0F_AF.asm
│ │ ├── 0F_AF_2.asm
│ │ ├── 0F_B0.asm
│ │ ├── 0F_B0_10.asm
│ │ ├── 0F_B0_11.asm
│ │ ├── 0F_B0_2.asm
│ │ ├── 0F_B0_3.asm
│ │ ├── 0F_B0_4.asm
│ │ ├── 0F_B0_5.asm
│ │ ├── 0F_B0_6.asm
│ │ ├── 0F_B0_7.asm
│ │ ├── 0F_B0_8.asm
│ │ ├── 0F_B0_9.asm
│ │ ├── 0F_B3.asm
│ │ ├── 0F_B3_2.asm
│ │ ├── 0F_B3_2_Atomic.asm
│ │ ├── 0F_B3_Atomic.asm
│ │ ├── 0F_B6.asm
│ │ ├── 0F_B7.asm
│ │ ├── 0F_BB.asm
│ │ ├── 0F_BB_2.asm
│ │ ├── 0F_BB_2_Atomic.asm
│ │ ├── 0F_BB_Atomic.asm
│ │ ├── 0F_BC.asm
│ │ ├── 0F_BD.asm
│ │ ├── 0F_BE.asm
│ │ ├── 0F_BF.asm
│ │ ├── 0F_C0.asm
│ │ ├── 0F_C0_2.asm
│ │ ├── 0F_C0_Atomic16.asm
│ │ ├── 0F_C0_Atomic32.asm
│ │ ├── 0F_C0_Atomic64.asm
│ │ ├── 0F_C2.asm
│ │ ├── 0F_C3.asm
│ │ ├── 0F_C4.asm
│ │ ├── 0F_C4_2.asm
│ │ ├── 0F_C5.asm
│ │ ├── 0F_C5_2.asm
│ │ ├── 0F_C6.asm
│ │ ├── 0F_D1.asm
│ │ ├── 0F_D2.asm
│ │ ├── 0F_D3.asm
│ │ ├── 0F_D4.asm
│ │ ├── 0F_D5.asm
│ │ ├── 0F_D7.asm
│ │ ├── 0F_D8.asm
│ │ ├── 0F_D9.asm
│ │ ├── 0F_DA.asm
│ │ ├── 0F_DB.asm
│ │ ├── 0F_DC.asm
│ │ ├── 0F_DD.asm
│ │ ├── 0F_DE.asm
│ │ ├── 0F_DF.asm
│ │ ├── 0F_E0.asm
│ │ ├── 0F_E1.asm
│ │ ├── 0F_E2.asm
│ │ ├── 0F_E3.asm
│ │ ├── 0F_E4.asm
│ │ ├── 0F_E5.asm
│ │ ├── 0F_E7.asm
│ │ ├── 0F_E8.asm
│ │ ├── 0F_E9.asm
│ │ ├── 0F_EA.asm
│ │ ├── 0F_EB.asm
│ │ ├── 0F_EC.asm
│ │ ├── 0F_ED.asm
│ │ ├── 0F_EE.asm
│ │ ├── 0F_EF.asm
│ │ ├── 0F_F1.asm
│ │ ├── 0F_F2.asm
│ │ ├── 0F_F3.asm
│ │ ├── 0F_F4.asm
│ │ ├── 0F_F5.asm
│ │ ├── 0F_F6.asm
│ │ ├── 0F_F6_2.asm
│ │ ├── 0F_F7.asm
│ │ ├── 0F_F8.asm
│ │ ├── 0F_F9.asm
│ │ ├── 0F_FA.asm
│ │ ├── 0F_FB.asm
│ │ ├── 0F_FC.asm
│ │ ├── 0F_FD.asm
│ │ └── 0F_FE.asm
│ ├── VEX/
│ │ ├── andn.asm
│ │ ├── bextr.asm
│ │ ├── blsi.asm
│ │ ├── blsmsk.asm
│ │ ├── blsr.asm
│ │ ├── bzhi.asm
│ │ ├── fma_fmadd_pd.asm
│ │ ├── fma_fmadd_ps.asm
│ │ ├── fma_fmadd_sd.asm
│ │ ├── fma_fmadd_ss.asm
│ │ ├── fma_fmaddsub_pd.asm
│ │ ├── fma_fmaddsub_ps.asm
│ │ ├── fma_fmsub_pd.asm
│ │ ├── fma_fmsub_ps.asm
│ │ ├── fma_fmsub_sd.asm
│ │ ├── fma_fmsub_ss.asm
│ │ ├── fma_fmsubadd_pd.asm
│ │ ├── fma_fmsubadd_ps.asm
│ │ ├── fma_fnmadd_pd.asm
│ │ ├── fma_fnmadd_ps.asm
│ │ ├── fma_fnmadd_sd.asm
│ │ ├── fma_fnmadd_ss.asm
│ │ ├── fma_fnmsub_pd.asm
│ │ ├── fma_fnmsub_ps.asm
│ │ ├── fma_fnmsub_sd.asm
│ │ ├── fma_fnmsub_ss.asm
│ │ ├── full_vpermq_imm.asm
│ │ ├── mulx.asm
│ │ ├── pdep.asm
│ │ ├── pext.asm
│ │ ├── rorx.asm
│ │ ├── sarx.asm
│ │ ├── shlx.asm
│ │ ├── shrx.asm
│ │ ├── vaddpd.asm
│ │ ├── vaddps.asm
│ │ ├── vaddsd.asm
│ │ ├── vaddss.asm
│ │ ├── vaddsubpd.asm
│ │ ├── vaddsubps.asm
│ │ ├── vaesdec.asm
│ │ ├── vaesdec256.asm
│ │ ├── vaesdeclast.asm
│ │ ├── vaesdeclast256.asm
│ │ ├── vaesenc.asm
│ │ ├── vaesenc256.asm
│ │ ├── vaesenclast.asm
│ │ ├── vaesenclast256.asm
│ │ ├── vaesimc.asm
│ │ ├── vaeskeygenassist.asm
│ │ ├── vandnpd.asm
│ │ ├── vandnps.asm
│ │ ├── vandpd.asm
│ │ ├── vandps.asm
│ │ ├── vblendpd.asm
│ │ ├── vblendps.asm
│ │ ├── vblendvpd.asm
│ │ ├── vblendvps.asm
│ │ ├── vbroadcastf128.asm
│ │ ├── vbroadcasti128.asm
│ │ ├── vbroadcastsd.asm
│ │ ├── vbroadcastss.asm
│ │ ├── vcmppd.asm
│ │ ├── vcmppd_256.asm
│ │ ├── vcmppd_full.asm
│ │ ├── vcmpps.asm
│ │ ├── vcmpps_256.asm
│ │ ├── vcmpps_full.asm
│ │ ├── vcmpsd.asm
│ │ ├── vcmpsd_full.asm
│ │ ├── vcmpss.asm
│ │ ├── vcmpss_full.asm
│ │ ├── vcomisd.asm
│ │ ├── vcomiss.asm
│ │ ├── vcvtdq2pd.asm
│ │ ├── vcvtdq2ps.asm
│ │ ├── vcvtpd2dq.asm
│ │ ├── vcvtpd2dq_inexact.asm
│ │ ├── vcvtpd2ps.asm
│ │ ├── vcvtph2ps.asm
│ │ ├── vcvtps2dq.asm
│ │ ├── vcvtps2dq_inexact.asm
│ │ ├── vcvtps2pd.asm
│ │ ├── vcvtps2ph_rd.asm
│ │ ├── vcvtps2ph_rd_mxcsr.asm
│ │ ├── vcvtps2ph_rtne.asm
│ │ ├── vcvtps2ph_rtne_mxcsr.asm
│ │ ├── vcvtps2ph_ru.asm
│ │ ├── vcvtps2ph_ru_mxcsr.asm
│ │ ├── vcvtps2ph_trunc.asm
│ │ ├── vcvtps2ph_trunc_mxcsr.asm
│ │ ├── vcvtsd2si.asm
│ │ ├── vcvtsd2ss.asm
│ │ ├── vcvtsi2sd.asm
│ │ ├── vcvtsi2ss.asm
│ │ ├── vcvtss2sd.asm
│ │ ├── vcvtss2si.asm
│ │ ├── vcvttpd2dq.asm
│ │ ├── vcvttps2dq.asm
│ │ ├── vcvttsd2si.asm
│ │ ├── vcvttss2si.asm
│ │ ├── vdivpd.asm
│ │ ├── vdivps.asm
│ │ ├── vdivsd.asm
│ │ ├── vdivss.asm
│ │ ├── vdppd.asm
│ │ ├── vdpps_128.asm
│ │ ├── vdpps_256.asm
│ │ ├── vextractf128.asm
│ │ ├── vextracti128.asm
│ │ ├── vextractps.asm
│ │ ├── vgather_dpd_128bit_1xdisp.asm
│ │ ├── vgather_dpd_128bit_2xdisp.asm
│ │ ├── vgather_dpd_128bit_4xdisp.asm
│ │ ├── vgather_dpd_128bit_8xdisp.asm
│ │ ├── vgather_dpd_256bit_1xdisp.asm
│ │ ├── vgather_dpd_256bit_2xdisp.asm
│ │ ├── vgather_dpd_256bit_4xdisp.asm
│ │ ├── vgather_dpd_256bit_8xdisp.asm
│ │ ├── vgather_dps_128bit_1xdisp.asm
│ │ ├── vgather_dps_128bit_2xdisp.asm
│ │ ├── vgather_dps_128bit_4xdisp.asm
│ │ ├── vgather_dps_128bit_8xdisp.asm
│ │ ├── vgather_dps_256bit_1xdisp.asm
│ │ ├── vgather_dps_256bit_2xdisp.asm
│ │ ├── vgather_dps_256bit_4xdisp.asm
│ │ ├── vgather_dps_256bit_8xdisp.asm
│ │ ├── vgather_qpd_128bit_1xdisp.asm
│ │ ├── vgather_qpd_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_2xdisp.asm
│ │ ├── vgather_qpd_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_4xdisp.asm
│ │ ├── vgather_qpd_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_8xdisp.asm
│ │ ├── vgather_qpd_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_1xdisp.asm
│ │ ├── vgather_qpd_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_2xdisp.asm
│ │ ├── vgather_qpd_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_4xdisp.asm
│ │ ├── vgather_qpd_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_8xdisp.asm
│ │ ├── vgather_qpd_256bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_1xdisp.asm
│ │ ├── vgather_qps_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_2xdisp.asm
│ │ ├── vgather_qps_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_4xdisp.asm
│ │ ├── vgather_qps_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_8xdisp.asm
│ │ ├── vgather_qps_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_1xdisp.asm
│ │ ├── vgather_qps_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_2xdisp.asm
│ │ ├── vgather_qps_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_4xdisp.asm
│ │ ├── vgather_qps_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_8xdisp.asm
│ │ ├── vgather_qps_256bit_8xdisp_overflow.asm
│ │ ├── vhaddpd.asm
│ │ ├── vhaddps.asm
│ │ ├── vhsubpd.asm
│ │ ├── vhsubps.asm
│ │ ├── vinsertf128.asm
│ │ ├── vinserti128.asm
│ │ ├── vinsertps.asm
│ │ ├── vlddqu.asm
│ │ ├── vldmxcsr.asm
│ │ ├── vmaskmovdqu.asm
│ │ ├── vmaskmovpd_load.asm
│ │ ├── vmaskmovpd_store.asm
│ │ ├── vmaskmovps_load.asm
│ │ ├── vmaskmovps_store.asm
│ │ ├── vmaxpd.asm
│ │ ├── vmaxps.asm
│ │ ├── vmaxsd.asm
│ │ ├── vmaxss.asm
│ │ ├── vminpd.asm
│ │ ├── vminps.asm
│ │ ├── vminsd.asm
│ │ ├── vminss.asm
│ │ ├── vmovapd.asm
│ │ ├── vmovapd_mem.asm
│ │ ├── vmovaps.asm
│ │ ├── vmovaps_mem.asm
│ │ ├── vmovddup.asm
│ │ ├── vmovdqa.asm
│ │ ├── vmovdqu.asm
│ │ ├── vmovhlps.asm
│ │ ├── vmovhpd.asm
│ │ ├── vmovhps.asm
│ │ ├── vmovlhps.asm
│ │ ├── vmovlpd.asm
│ │ ├── vmovlps.asm
│ │ ├── vmovmskpd.asm
│ │ ├── vmovmskps.asm
│ │ ├── vmovntdq.asm
│ │ ├── vmovntdqa.asm
│ │ ├── vmovntpd.asm
│ │ ├── vmovntps.asm
│ │ ├── vmovq.asm
│ │ ├── vmovq_vmovd_reg.asm
│ │ ├── vmovsd_from_mem.asm
│ │ ├── vmovsd_to_mem.asm
│ │ ├── vmovsd_vectors.asm
│ │ ├── vmovshdup.asm
│ │ ├── vmovsldup.asm
│ │ ├── vmovss_from_mem.asm
│ │ ├── vmovss_to_mem.asm
│ │ ├── vmovss_vectors.asm
│ │ ├── vmovupd.asm
│ │ ├── vmovupd_mem.asm
│ │ ├── vmovups.asm
│ │ ├── vmovups_mem.asm
│ │ ├── vmpsadbw_128.asm
│ │ ├── vmpsadbw_256.asm
│ │ ├── vmulpd.asm
│ │ ├── vmulps.asm
│ │ ├── vmulsd.asm
│ │ ├── vmulss.asm
│ │ ├── vorpd.asm
│ │ ├── vorps.asm
│ │ ├── vpabsb.asm
│ │ ├── vpabsd.asm
│ │ ├── vpabsw.asm
│ │ ├── vpackssdw.asm
│ │ ├── vpacksswb.asm
│ │ ├── vpackusdw.asm
│ │ ├── vpackuswb.asm
│ │ ├── vpaddb.asm
│ │ ├── vpaddd.asm
│ │ ├── vpaddq.asm
│ │ ├── vpaddsb.asm
│ │ ├── vpaddsw.asm
│ │ ├── vpaddusb.asm
│ │ ├── vpaddusw.asm
│ │ ├── vpaddw.asm
│ │ ├── vpalignr.asm
│ │ ├── vpand.asm
│ │ ├── vpandn.asm
│ │ ├── vpavgb.asm
│ │ ├── vpavgb_aliasing.asm
│ │ ├── vpavgw.asm
│ │ ├── vpavgw_aliasing.asm
│ │ ├── vpblendd.asm
│ │ ├── vpblendvb.asm
│ │ ├── vpblendw.asm
│ │ ├── vpbroadcastb.asm
│ │ ├── vpbroadcastd.asm
│ │ ├── vpbroadcastq.asm
│ │ ├── vpbroadcastw.asm
│ │ ├── vpclmulqdq.asm
│ │ ├── vpclmulqdq_256.asm
│ │ ├── vpcmpeqb.asm
│ │ ├── vpcmpeqd.asm
│ │ ├── vpcmpeqq.asm
│ │ ├── vpcmpeqw.asm
│ │ ├── vpcmpestri_equal_any.asm
│ │ ├── vpcmpestri_equal_each.asm
│ │ ├── vpcmpestri_equal_ordered.asm
│ │ ├── vpcmpestri_ranges.asm
│ │ ├── vpcmpestrm_equal_any.asm
│ │ ├── vpcmpestrm_equal_each.asm
│ │ ├── vpcmpestrm_equal_ordered.asm
│ │ ├── vpcmpestrm_ranges.asm
│ │ ├── vpcmpgtb.asm
│ │ ├── vpcmpgtd.asm
│ │ ├── vpcmpgtq.asm
│ │ ├── vpcmpgtw.asm
│ │ ├── vpcmpistri_equal_any.asm
│ │ ├── vpcmpistri_equal_each.asm
│ │ ├── vpcmpistri_equal_ordered.asm
│ │ ├── vpcmpistri_ranges.asm
│ │ ├── vpcmpistrm_equal_any.asm
│ │ ├── vpcmpistrm_equal_each.asm
│ │ ├── vpcmpistrm_equal_ordered.asm
│ │ ├── vpcmpistrm_ranges.asm
│ │ ├── vperm2f128.asm
│ │ ├── vperm2i128.asm
│ │ ├── vpermd.asm
│ │ ├── vpermilpd_imm.asm
│ │ ├── vpermilpd_reg.asm
│ │ ├── vpermilps_imm.asm
│ │ ├── vpermilps_reg.asm
│ │ ├── vpermpd.asm
│ │ ├── vpermps.asm
│ │ ├── vpermq.asm
│ │ ├── vpextrb.asm
│ │ ├── vpextrd.asm
│ │ ├── vpextrq.asm
│ │ ├── vpextrw.asm
│ │ ├── vpgather_dd_128bit_1xdisp.asm
│ │ ├── vpgather_dd_128bit_2xdisp.asm
│ │ ├── vpgather_dd_128bit_4xdisp.asm
│ │ ├── vpgather_dd_128bit_8xdisp.asm
│ │ ├── vpgather_dd_256bit_1xdisp.asm
│ │ ├── vpgather_dd_256bit_2xdisp.asm
│ │ ├── vpgather_dd_256bit_4xdisp.asm
│ │ ├── vpgather_dd_256bit_8xdisp.asm
│ │ ├── vpgather_dq_128bit_1xdisp.asm
│ │ ├── vpgather_dq_128bit_2xdisp.asm
│ │ ├── vpgather_dq_128bit_4xdisp.asm
│ │ ├── vpgather_dq_128bit_8xdisp.asm
│ │ ├── vpgather_dq_256bit_1xdisp.asm
│ │ ├── vpgather_dq_256bit_2xdisp.asm
│ │ ├── vpgather_dq_256bit_4xdisp.asm
│ │ ├── vpgather_dq_256bit_8xdisp.asm
│ │ ├── vpgather_qd_128bit_1xdisp.asm
│ │ ├── vpgather_qd_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_2xdisp.asm
│ │ ├── vpgather_qd_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_4xdisp.asm
│ │ ├── vpgather_qd_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_8xdisp.asm
│ │ ├── vpgather_qd_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_1xdisp.asm
│ │ ├── vpgather_qd_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_2xdisp.asm
│ │ ├── vpgather_qd_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_4xdisp.asm
│ │ ├── vpgather_qd_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_8xdisp.asm
│ │ ├── vpgather_qd_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_1xdisp.asm
│ │ ├── vpgather_qq_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_2xdisp.asm
│ │ ├── vpgather_qq_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_4xdisp.asm
│ │ ├── vpgather_qq_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_8xdisp.asm
│ │ ├── vpgather_qq_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_1xdisp.asm
│ │ ├── vpgather_qq_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_2xdisp.asm
│ │ ├── vpgather_qq_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_4xdisp.asm
│ │ ├── vpgather_qq_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_8xdisp.asm
│ │ ├── vpgather_qq_256bit_8xdisp_overflow.asm
│ │ ├── vphaddd.asm
│ │ ├── vphaddsw.asm
│ │ ├── vphaddsw_256.asm
│ │ ├── vphaddw.asm
│ │ ├── vphminposuw.asm
│ │ ├── vphsubd.asm
│ │ ├── vphsubsw.asm
│ │ ├── vphsubsw_256.asm
│ │ ├── vphsubw.asm
│ │ ├── vpinsrb.asm
│ │ ├── vpinsrd.asm
│ │ ├── vpinsrq.asm
│ │ ├── vpinsrw.asm
│ │ ├── vpmaddubsw.asm
│ │ ├── vpmaddubsw_256.asm
│ │ ├── vpmaddwd.asm
│ │ ├── vpmaskmovd_load.asm
│ │ ├── vpmaskmovd_store.asm
│ │ ├── vpmaskmovq_load.asm
│ │ ├── vpmaskmovq_store.asm
│ │ ├── vpmaxsb.asm
│ │ ├── vpmaxsd.asm
│ │ ├── vpmaxsw.asm
│ │ ├── vpmaxub.asm
│ │ ├── vpmaxud.asm
│ │ ├── vpmaxuw.asm
│ │ ├── vpminsb.asm
│ │ ├── vpminsd.asm
│ │ ├── vpminsw.asm
│ │ ├── vpminub.asm
│ │ ├── vpminud.asm
│ │ ├── vpminuw.asm
│ │ ├── vpmovmskb.asm
│ │ ├── vpmovsxbd.asm
│ │ ├── vpmovsxbq.asm
│ │ ├── vpmovsxbw.asm
│ │ ├── vpmovsxdq.asm
│ │ ├── vpmovsxwd.asm
│ │ ├── vpmovsxwq.asm
│ │ ├── vpmovzxbd.asm
│ │ ├── vpmovzxbq.asm
│ │ ├── vpmovzxbw.asm
│ │ ├── vpmovzxdq.asm
│ │ ├── vpmovzxwd.asm
│ │ ├── vpmovzxwq.asm
│ │ ├── vpmuldq.asm
│ │ ├── vpmuldq_256.asm
│ │ ├── vpmulhrsw.asm
│ │ ├── vpmulhuw.asm
│ │ ├── vpmulhw.asm
│ │ ├── vpmulld.asm
│ │ ├── vpmullw.asm
│ │ ├── vpmuludq.asm
│ │ ├── vpor.asm
│ │ ├── vpsadbw.asm
│ │ ├── vpsadbw_256.asm
│ │ ├── vpshufb.asm
│ │ ├── vpshufd.asm
│ │ ├── vpshufhw.asm
│ │ ├── vpshuflw.asm
│ │ ├── vpsignb.asm
│ │ ├── vpsignd.asm
│ │ ├── vpsignw.asm
│ │ ├── vpslld.asm
│ │ ├── vpslld_imm.asm
│ │ ├── vpslldq.asm
│ │ ├── vpsllq.asm
│ │ ├── vpsllq_imm.asm
│ │ ├── vpsllvd.asm
│ │ ├── vpsllvq.asm
│ │ ├── vpsllw.asm
│ │ ├── vpsllw_imm.asm
│ │ ├── vpsrad.asm
│ │ ├── vpsrad_imm.asm
│ │ ├── vpsravd.asm
│ │ ├── vpsraw.asm
│ │ ├── vpsraw_imm.asm
│ │ ├── vpsrld.asm
│ │ ├── vpsrld_imm.asm
│ │ ├── vpsrldq.asm
│ │ ├── vpsrlq.asm
│ │ ├── vpsrlq_imm.asm
│ │ ├── vpsrlvd.asm
│ │ ├── vpsrlvq.asm
│ │ ├── vpsrlw.asm
│ │ ├── vpsrlw_imm.asm
│ │ ├── vpsubb.asm
│ │ ├── vpsubd.asm
│ │ ├── vpsubq.asm
│ │ ├── vpsubsb.asm
│ │ ├── vpsubsw.asm
│ │ ├── vpsubusb.asm
│ │ ├── vpsubusw.asm
│ │ ├── vpsubw.asm
│ │ ├── vptest.asm
│ │ ├── vpunpckhbw.asm
│ │ ├── vpunpckhdq.asm
│ │ ├── vpunpckhqdq.asm
│ │ ├── vpunpckhwd.asm
│ │ ├── vpunpcklbw.asm
│ │ ├── vpunpckldq.asm
│ │ ├── vpunpcklqdq.asm
│ │ ├── vpunpcklwd.asm
│ │ ├── vpxor.asm
│ │ ├── vrcpps.asm
│ │ ├── vrcpss.asm
│ │ ├── vroundpd.asm
│ │ ├── vroundps.asm
│ │ ├── vroundsd.asm
│ │ ├── vroundss.asm
│ │ ├── vrsqrtps.asm
│ │ ├── vrsqrtss.asm
│ │ ├── vshufpd.asm
│ │ ├── vshufps.asm
│ │ ├── vsqrtpd.asm
│ │ ├── vsqrtps.asm
│ │ ├── vsqrtsd.asm
│ │ ├── vsqrtss.asm
│ │ ├── vsubpd.asm
│ │ ├── vsubps.asm
│ │ ├── vsubsd.asm
│ │ ├── vsubss.asm
│ │ ├── vtestpd.asm
│ │ ├── vtestps.asm
│ │ ├── vucomisd.asm
│ │ ├── vucomiss.asm
│ │ ├── vunpckhpd.asm
│ │ ├── vunpckhps.asm
│ │ ├── vunpcklpd.asm
│ │ ├── vunpcklps.asm
│ │ ├── vxorpd.asm
│ │ ├── vxorps.asm
│ │ ├── vzeroall.asm
│ │ └── vzeroupper.asm
│ ├── X87/
│ │ ├── D8_00.asm
│ │ ├── D8_01.asm
│ │ ├── D8_04.asm
│ │ ├── D8_05.asm
│ │ ├── D8_06.asm
│ │ ├── D8_07.asm
│ │ ├── D8_C0.asm
│ │ ├── D8_C8.asm
│ │ ├── D8_D0.asm
│ │ ├── D8_D9.asm
│ │ ├── D8_E0.asm
│ │ ├── D8_E8.asm
│ │ ├── D8_F0.asm
│ │ ├── D8_F0_2.asm
│ │ ├── D8_F8.asm
│ │ ├── D9_00.asm
│ │ ├── D9_02.asm
│ │ ├── D9_03.asm
│ │ ├── D9_05.asm
│ │ ├── D9_06.asm
│ │ ├── D9_06_2.asm
│ │ ├── D9_07.asm
│ │ ├── D9_C0.asm
│ │ ├── D9_C8.asm
│ │ ├── D9_D0.asm
│ │ ├── D9_E0.asm
│ │ ├── D9_E1.asm
│ │ ├── D9_E4.asm
│ │ ├── D9_E8.asm
│ │ ├── D9_E9.asm
│ │ ├── D9_EA.asm
│ │ ├── D9_EB.asm
│ │ ├── D9_EC.asm
│ │ ├── D9_ED.asm
│ │ ├── D9_EE.asm
│ │ ├── D9_F0.asm
│ │ ├── D9_F1.asm
│ │ ├── D9_F2.asm
│ │ ├── D9_F3.asm
│ │ ├── D9_F4.asm
│ │ ├── D9_F4_02.asm
│ │ ├── D9_F5.asm
│ │ ├── D9_F5_2.asm
│ │ ├── D9_F5_3.asm
│ │ ├── D9_F6.asm
│ │ ├── D9_F7.asm
│ │ ├── D9_F8.asm
│ │ ├── D9_F9.asm
│ │ ├── D9_FA.asm
│ │ ├── D9_FB.asm
│ │ ├── D9_FC.asm
│ │ ├── D9_FD.asm
│ │ ├── D9_FD_2.asm
│ │ ├── D9_FE.asm
│ │ ├── D9_FF.asm
│ │ ├── DA_00.asm
│ │ ├── DA_01.asm
│ │ ├── DA_02.asm
│ │ ├── DA_04.asm
│ │ ├── DA_05.asm
│ │ ├── DA_06.asm
│ │ ├── DA_07.asm
│ │ ├── DA_C0.asm
│ │ ├── DA_C8.asm
│ │ ├── DA_D0.asm
│ │ ├── DA_D8.asm
│ │ ├── DA_D9.asm
│ │ ├── DA_E9.asm
│ │ ├── DB_00.asm
│ │ ├── DB_01.asm
│ │ ├── DB_02.asm
│ │ ├── DB_03.asm
│ │ ├── DB_05.asm
│ │ ├── DB_07.asm
│ │ ├── DB_07_2.asm
│ │ ├── DB_C0.asm
│ │ ├── DB_C8.asm
│ │ ├── DB_D0.asm
│ │ ├── DB_D8.asm
│ │ ├── DB_E2.asm
│ │ ├── DB_E3.asm
│ │ ├── DB_E3_2.asm
│ │ ├── DB_E8.asm
│ │ ├── DB_F0.asm
│ │ ├── DC_00.asm
│ │ ├── DC_01.asm
│ │ ├── DC_04.asm
│ │ ├── DC_05.asm
│ │ ├── DC_06.asm
│ │ ├── DC_07.asm
│ │ ├── DC_C0.asm
│ │ ├── DC_C8.asm
│ │ ├── DC_D0.asm
│ │ ├── DC_D9.asm
│ │ ├── DC_E0.asm
│ │ ├── DC_E8.asm
│ │ ├── DC_F0.asm
│ │ ├── DC_F8.asm
│ │ ├── DD_00.asm
│ │ ├── DD_01.asm
│ │ ├── DD_02.asm
│ │ ├── DD_03.asm
│ │ ├── DD_04.asm
│ │ ├── DD_04_2.asm
│ │ ├── DD_07.asm
│ │ ├── DD_C0.asm
│ │ ├── DD_C8.asm
│ │ ├── DD_D0.asm
│ │ ├── DD_D0_2.asm
│ │ ├── DD_D8.asm
│ │ ├── DD_E9.asm
│ │ ├── DE_00.asm
│ │ ├── DE_01.asm
│ │ ├── DE_02.asm
│ │ ├── DE_04.asm
│ │ ├── DE_05.asm
│ │ ├── DE_06.asm
│ │ ├── DE_07.asm
│ │ ├── DE_C0.asm
│ │ ├── DE_C8.asm
│ │ ├── DE_D0.asm
│ │ ├── DE_E0.asm
│ │ ├── DE_E8.asm
│ │ ├── DE_F0.asm
│ │ ├── DE_F8.asm
│ │ ├── DF_00.asm
│ │ ├── DF_01.asm
│ │ ├── DF_02.asm
│ │ ├── DF_03.asm
│ │ ├── DF_04.asm
│ │ ├── DF_05.asm
│ │ ├── DF_07.asm
│ │ ├── DF_C0.asm
│ │ ├── DF_C8.asm
│ │ ├── DF_D0.asm
│ │ ├── DF_D8.asm
│ │ ├── DF_E0.asm
│ │ ├── DF_E8.asm
│ │ ├── DF_F0.asm
│ │ ├── FISTTP_16bit.asm
│ │ ├── FISTTP_16bit_neg.asm
│ │ ├── FISTTP_32bit.asm
│ │ ├── FISTTP_32bit_neg.asm
│ │ ├── FISTTP_64bit.asm
│ │ ├── FISTTP_64bit_neg.asm
│ │ ├── FPREM1_Flags.asm
│ │ ├── FPREM_Flags.asm
│ │ ├── FST_AddrModes.asm
│ │ ├── FScale-Zero.asm
│ │ ├── FScaleFXtract.asm
│ │ ├── FXAM_Push.asm
│ │ ├── FXAM_Push_2.asm
│ │ ├── FXAM_Push_Simple.asm
│ │ ├── FXAM_Push_Simple_2.asm
│ │ ├── FXAM_Simple.asm
│ │ ├── LoadAtBoundary.asm
│ │ ├── Memcopy.asm
│ │ ├── MemcopyWithCPUID.asm
│ │ ├── Rounding.asm
│ │ ├── StoreAtBoundary.asm
│ │ ├── X87MMXInteraction.asm
│ │ ├── invalid_div_zero.asm
│ │ ├── invalid_fcos_infinity.asm
│ │ ├── invalid_fist_nan.asm
│ │ ├── invalid_fist_overflow.asm
│ │ ├── invalid_fist_overflow_16bit.asm
│ │ ├── invalid_fist_overflow_32bit.asm
│ │ ├── invalid_fist_overflow_64bit.asm
│ │ ├── invalid_fprem_infinity.asm
│ │ ├── invalid_fptan_infinity.asm
│ │ ├── invalid_fsin_infinity.asm
│ │ ├── invalid_fsin_neg_infinity.asm
│ │ ├── invalid_fsincos_infinity.asm
│ │ ├── invalid_infinity_fsubr_infinity.asm
│ │ ├── invalid_infinity_mul_zero.asm
│ │ ├── invalid_infinity_ops.asm
│ │ ├── invalid_infinity_sub_infinity.asm
│ │ ├── invalid_neg_infinity_sub_neg_infinity.asm
│ │ ├── invalid_reduced_precision.asm
│ │ ├── invalid_simple_test.asm
│ │ ├── invalid_sqrt_negative.asm
│ │ ├── precision_test_fabs.asm
│ │ ├── precision_test_fadd.asm
│ │ ├── precision_test_fcos.asm
│ │ ├── precision_test_fdiv.asm
│ │ ├── precision_test_fdivr.asm
│ │ ├── precision_test_fmul.asm
│ │ ├── precision_test_fprem.asm
│ │ ├── precision_test_fprem1.asm
│ │ ├── precision_test_fscale.asm
│ │ ├── precision_test_fsin.asm
│ │ ├── precision_test_fsqrt.asm
│ │ ├── precision_test_fsub.asm
│ │ ├── precision_test_fsubr.asm
│ │ ├── precision_test_ftan.asm
│ │ ├── precision_test_fyl2x.asm
│ │ ├── precision_test_fyl2xp1.asm
│ │ ├── precision_test_neg_fabs.asm
│ │ ├── precision_test_neg_fadd.asm
│ │ ├── precision_test_neg_fcos.asm
│ │ ├── precision_test_neg_fdiv.asm
│ │ ├── precision_test_neg_fdivr.asm
│ │ ├── precision_test_neg_fmul.asm
│ │ ├── precision_test_neg_fprem.asm
│ │ ├── precision_test_neg_fprem1.asm
│ │ ├── precision_test_neg_fscale.asm
│ │ ├── precision_test_neg_fsin.asm
│ │ ├── precision_test_neg_fsub.asm
│ │ ├── precision_test_neg_fsubr.asm
│ │ ├── precision_test_neg_ftan.asm
│ │ ├── precision_test_neg_fyl2x.asm
│ │ ├── precision_test_neg_fyl2xp1.asm
│ │ ├── valid_fist_16bit.asm
│ │ └── valid_operation.asm
│ ├── X87_F64/
│ │ ├── D8_00_F64.asm
│ │ ├── D8_01_F64.asm
│ │ ├── D8_04_F64.asm
│ │ ├── D8_05_F64.asm
│ │ ├── D8_06_F64.asm
│ │ ├── D8_07_F64.asm
│ │ ├── D8_C0_F64.asm
│ │ ├── D8_C8_F64.asm
│ │ ├── D8_D9_F64.asm
│ │ ├── D8_E0_F64.asm
│ │ ├── D8_E8_F64.asm
│ │ ├── D8_F0_2_F64.asm
│ │ ├── D8_F0_F64.asm
│ │ ├── D8_F8_F64.asm
│ │ ├── D9_00_F64.asm
│ │ ├── D9_02_F64.asm
│ │ ├── D9_03_F64.asm
│ │ ├── D9_05_F64.asm
│ │ ├── D9_06_2_F64.asm
│ │ ├── D9_06_F64.asm
│ │ ├── D9_07_F64.asm
│ │ ├── D9_C0_F64.asm
│ │ ├── D9_C8_F64.asm
│ │ ├── D9_D0_F64.asm
│ │ ├── D9_E0_F64.asm
│ │ ├── D9_E1_F64.asm
│ │ ├── D9_E4_F64.asm
│ │ ├── D9_E8_F64.asm
│ │ ├── D9_E9_F64.asm
│ │ ├── D9_EA_F64.asm
│ │ ├── D9_EB_F64.asm
│ │ ├── D9_EC_F64.asm
│ │ ├── D9_ED_F64.asm
│ │ ├── D9_EE_F64.asm
│ │ ├── D9_F0_F64.asm
│ │ ├── D9_F1_F64.asm
│ │ ├── D9_F2_F64.asm
│ │ ├── D9_F3_F64.asm
│ │ ├── D9_F4_02_F64.asm
│ │ ├── D9_F4_F64.asm
│ │ ├── D9_F5_F64.asm
│ │ ├── D9_F6_F64.asm
│ │ ├── D9_F7_F64.asm
│ │ ├── D9_F8_F64.asm
│ │ ├── D9_F9_F64.asm
│ │ ├── D9_FA_F64.asm
│ │ ├── D9_FB_F64.asm
│ │ ├── D9_FC_F64.asm
│ │ ├── D9_FD_2_F64.asm
│ │ ├── D9_FD_F64.asm
│ │ ├── D9_FE_F64.asm
│ │ ├── D9_FF_F64.asm
│ │ ├── DA_01_F64.asm
│ │ ├── DA_02_F64.asm
│ │ ├── DA_04_F64.asm
│ │ ├── DA_05_F64.asm
│ │ ├── DA_06_F64.asm
│ │ ├── DA_07_F64.asm
│ │ ├── DA_C0_F64.asm
│ │ ├── DA_C8_F64.asm
│ │ ├── DA_D0_F64.asm
│ │ ├── DA_D8_F64.asm
│ │ ├── DA_D9_F64.asm
│ │ ├── DA_E9_F64.asm
│ │ ├── DB_00_F64.asm
│ │ ├── DB_01_F64.asm
│ │ ├── DB_02_F64.asm
│ │ ├── DB_03_F64.asm
│ │ ├── DB_05_F64.asm
│ │ ├── DB_07_F64.asm
│ │ ├── DB_C0_F64.asm
│ │ ├── DB_C8_F64.asm
│ │ ├── DB_D0_F64.asm
│ │ ├── DB_D8_F64.asm
│ │ ├── DB_E3.asm
│ │ ├── DC_00_F64.asm
│ │ ├── DC_01_F64.asm
│ │ ├── DC_04_F64.asm
│ │ ├── DC_05_F64.asm
│ │ ├── DC_06_F64.asm
│ │ ├── DC_07_F64.asm
│ │ ├── DC_C0_F64.asm
│ │ ├── DC_C8_F64.asm
│ │ ├── DC_E0_F64.asm
│ │ ├── DC_E8_F64.asm
│ │ ├── DC_F0_F64.asm
│ │ ├── DC_F8_F64.asm
│ │ ├── DD_00_F64.asm
│ │ ├── DD_01_F64.asm
│ │ ├── DD_02_F64.asm
│ │ ├── DD_03_F64.asm
│ │ ├── DD_04_2_F64.asm
│ │ ├── DD_04_F64.asm
│ │ ├── DD_07_F64.asm
│ │ ├── DD_C0_F64.asm
│ │ ├── DD_D0_2_F64.asm
│ │ ├── DD_D0_F64.asm
│ │ ├── DD_D8_F64.asm
│ │ ├── DD_E9_F64.asm
│ │ ├── DE_00_F64.asm
│ │ ├── DE_01_F64.asm
│ │ ├── DE_02_F64.asm
│ │ ├── DE_04_F64.asm
│ │ ├── DE_05_F64.asm
│ │ ├── DE_06_F64.asm
│ │ ├── DE_07_F64.asm
│ │ ├── DE_C0_F64.asm
│ │ ├── DE_C8_F64.asm
│ │ ├── DE_E0_F64.asm
│ │ ├── DE_E8_F64.asm
│ │ ├── DE_F0_F64.asm
│ │ ├── DE_F8_F64.asm
│ │ ├── DF_00_F64.asm
│ │ ├── DF_01_F64.asm
│ │ ├── DF_02_F64.asm
│ │ ├── DF_03_F64.asm
│ │ ├── DF_04_F64.asm
│ │ ├── DF_05_F64.asm
│ │ ├── DF_07_F64.asm
│ │ ├── DF_E0_F64.asm
│ │ ├── FCOM_F64.asm
│ │ ├── FILD_NEG_F64.asm
│ │ ├── FIST_F64.asm
│ │ ├── FLDCW_F64.asm
│ │ ├── FLD_F64.asm
│ │ ├── FPREM1_Flags_F64.asm
│ │ ├── FPREM_Flags_F64.asm
│ │ ├── FScale-Zero_F64.asm
│ │ ├── FScaleFXtract_F64.asm
│ │ ├── FXAM_Push_2_F64.asm
│ │ ├── FXAM_Push_F64.asm
│ │ ├── Rounding_F64.asm
│ │ ├── fptan_neg_zero_F64.asm
│ │ ├── fptan_pos_zero_F64.asm
│ │ ├── fsin_neg_zero_F64.asm
│ │ ├── fsin_pos_zero_F64.asm
│ │ └── fsincos_neg_zero_F64.asm
│ ├── fadd.asm
│ ├── fld.asm
│ ├── full_pshufd_imm.asm
│ ├── full_vpblendw_imm.asm
│ ├── jump.asm
│ ├── lea.asm
│ ├── modrm_oob/
│ │ ├── DDD.asm
│ │ ├── H0F38.asm
│ │ ├── H0F3A.asm
│ │ ├── Primary.asm
│ │ ├── PrimaryGroup.asm
│ │ ├── Secondary.asm
│ │ ├── SecondaryGroup.asm
│ │ ├── SecondaryModRM.asm
│ │ ├── SecondaryOpSize.asm
│ │ ├── SecondaryREP.asm
│ │ ├── SecondaryREPNE.asm
│ │ ├── VEX.asm
│ │ ├── VEXGroup.asm
│ │ ├── X87.asm
│ │ └── X87_Reduced.asm
│ ├── mov.asm
│ ├── movups.asm
│ ├── movzx.asm
│ ├── pslldq.asm
│ └── x87_stack.asm
├── CMakeLists.txt
├── Example.asm
├── FEXLinuxTests/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Disabled_Tests_Host
│ ├── Expected_Output
│ ├── Flake_Tests
│ ├── Known_Failures
│ └── tests/
│ ├── CMakeLists.txt
│ ├── cpu/
│ │ └── cpu_count.cpp
│ ├── fd/
│ │ └── test_close_range.cpp
│ ├── fs/
│ │ └── self_symlink.cpp
│ ├── include/
│ │ ├── fpstate.h
│ │ └── simple_x86.h
│ ├── signal/
│ │ ├── Syscall_state.32.cpp
│ │ ├── Syscall_state.64.cpp
│ │ ├── SystemInstructions.64.cpp
│ │ ├── eflags_signal.cpp
│ │ ├── into.32.cpp
│ │ ├── invalid_hlt.cpp
│ │ ├── invalid_int.cpp
│ │ ├── invalid_int1.cpp
│ │ ├── invalid_int3.cpp
│ │ ├── invalid_ud2.cpp
│ │ ├── invalid_util.h
│ │ ├── invalid_vex.32.cpp
│ │ ├── noexec_protect.64.cpp
│ │ ├── pthread_cancel.cpp
│ │ ├── sigill_flags.cpp
│ │ ├── sigill_xstate_magic.cpp
│ │ ├── signal_df_reset.64.cpp
│ │ ├── signal_flags.cpp
│ │ ├── signal_order.cpp
│ │ ├── sigtest_defer.cpp
│ │ ├── sigtest_no_defer.cpp
│ │ ├── sigtest_samask.cpp
│ │ ├── sigtest_siginfo.32.cpp
│ │ ├── sigtest_siginfo.64.cpp
│ │ ├── sigtest_sigmask.cpp
│ │ ├── synchronous-signal-block.cpp
│ │ ├── timer-sigev-thread.cpp
│ │ ├── trap_flag.cpp
│ │ └── x87_state.64.cpp
│ ├── smc/
│ │ ├── smc-1-dynamic.cpp
│ │ ├── smc-2.cpp
│ │ ├── smc-common.h
│ │ ├── smc-exec-stack.cpp
│ │ ├── smc-missing-gnustack.cpp
│ │ ├── smc-mt-1.cpp
│ │ ├── smc-mt-2.cpp
│ │ ├── smc-shared-1.cpp
│ │ ├── smc-shared-2.cpp
│ │ └── smc-unexec-stack.cpp
│ ├── syscalls/
│ │ ├── execveat_memfd.cpp
│ │ ├── futimesat.cpp
│ │ ├── personality.cpp
│ │ ├── syscall_exit.cpp
│ │ ├── syscall_sigaltstack.cpp
│ │ └── syscalls_efault.cpp
│ ├── thunks/
│ │ └── thunk_testlib.cpp
│ └── vdso/
│ └── vdso_test.cpp
├── InstructionCountCI/
│ ├── AFP/
│ │ ├── H0F3A.json
│ │ ├── SVE256/
│ │ │ ├── Secondary.json
│ │ │ ├── Secondary_REP.json
│ │ │ └── Secondary_REPNE.json
│ │ ├── Secondary.json
│ │ ├── Secondary_REP.json
│ │ ├── Secondary_REPNE.json
│ │ ├── VEX_map1.json
│ │ └── VEX_map3.json
│ ├── AVX128/
│ │ ├── FMA4.json
│ │ ├── VEX_map1.json
│ │ ├── VEX_map1_FCMA.json
│ │ ├── VEX_map1_SVE128.json
│ │ ├── VEX_map1_flagm.json
│ │ ├── VEX_map2.json
│ │ ├── VEX_map2_AFP.json
│ │ ├── VEX_map2_SVE128.json
│ │ ├── VEX_map2_flagm.json
│ │ ├── VEX_map3.json
│ │ ├── VEX_map3_SVE128.json
│ │ └── VEX_map_group.json
│ ├── Atomics.json
│ ├── CMakeLists.txt
│ ├── Crypto/
│ │ ├── H0F38.json
│ │ └── H0F3A.json
│ ├── DDD.json
│ ├── FEXOpt/
│ │ ├── AddressingLimitations.json
│ │ ├── AddressingLimitations_32Bit.json
│ │ ├── MultiInst.json
│ │ ├── MultiInst_32bit.json
│ │ ├── MultiInst_AFP.json
│ │ ├── MultiInst_TSO.json
│ │ ├── MultiInst_TSO_32bit.json
│ │ └── libnss.json
│ ├── FlagM/
│ │ ├── Atomics.json
│ │ ├── FlagOpts.json
│ │ ├── H0F38.json
│ │ ├── HotBlocks.json
│ │ ├── HotBlocks_32Bit.json
│ │ ├── HotBlocks_AFP.json
│ │ ├── HotBlocks_TSO_32Bit.json
│ │ ├── Primary.json
│ │ ├── PrimaryGroup.json
│ │ ├── Primary_32Bit.json
│ │ ├── Secondary.json
│ │ ├── SecondaryGroup.json
│ │ ├── SecondaryModRM.json
│ │ ├── Secondary_OpSize.json
│ │ ├── Secondary_REP.json
│ │ ├── Secondary_REP_CSSC.json
│ │ ├── VEX_map1.json
│ │ ├── VEX_map2.json
│ │ ├── VEX_map_group.json
│ │ ├── x87-Crysis2Max-fmodel.json
│ │ ├── x87-HalfLife.json
│ │ ├── x87-Oblivion.json
│ │ ├── x87-Psychonauts.json
│ │ ├── x87.json
│ │ ├── x87_f64-Crysis2Max-fmodel.json
│ │ ├── x87_f64-HalfLife.json
│ │ ├── x87_f64-Oblivion.json
│ │ ├── x87_f64-Psychonauts.json
│ │ └── x87_f64.json
│ ├── H0F38.json
│ ├── H0F3A.json
│ ├── H0F3A_SVE128.json
│ ├── MOPS/
│ │ └── Primary.json
│ ├── Primary.json
│ ├── PrimaryGroup.json
│ ├── Primary_32Bit.json
│ ├── RPRES/
│ │ ├── DDD.json
│ │ ├── Secondary.json
│ │ ├── Secondary_REP_AFP.json
│ │ └── VEX_map1_AFP.json
│ ├── Repeat.json
│ ├── SSE42_Strings.json
│ ├── Secondary.json
│ ├── SecondaryGroup.json
│ ├── SecondaryModRM.json
│ ├── Secondary_32Bit.json
│ ├── Secondary_OpSize.json
│ ├── Secondary_OpSize_FCMA.json
│ ├── Secondary_OpSize_SVE128.json
│ ├── Secondary_OpSize_SVE256.json
│ ├── Secondary_REP.json
│ ├── Secondary_REPNE.json
│ ├── Secondary_REPNE_FCMA.json
│ ├── Secondary_REPNE_SVE128.json
│ ├── Secondary_REP_FRINTTS.json
│ ├── Secondary_SVE128.json
│ ├── VEX_map1.json
│ ├── VEX_map1_FCMA.json
│ ├── VEX_map1_FRINTTS.json
│ ├── VEX_map2.json
│ ├── VEX_map2_svebitperm.json
│ ├── VEX_map3.json
│ ├── VEX_map_group.json
│ ├── X87ldst-SVE.json
│ ├── x87.json
│ ├── x87_32Bit.json
│ ├── x87_f64.json
│ └── x87_f64_32Bit.json
├── POSIX/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ ├── Flake_Tests
│ └── Known_Failures
├── Readme.md
├── ThunkFunctionalTests/
│ └── CMakeLists.txt
├── ThunkLibs/
│ ├── CMakeLists.txt
│ ├── abi.cpp
│ ├── common.h
│ └── generator.cpp
├── Utilities/
│ ├── CMakeLists.txt
│ └── DeleteOldSHMRegions.cpp
├── gcc-target-tests-32/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ └── Known_Failures
├── gcc-target-tests-64/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ └── Known_Failures
└── gvisor-tests/
├── CMakeLists.txt
├── Disabled_Tests
├── Expected_Output
├── Flake_Tests
└── Known_Failures
================================================
FILE CONTENTS
================================================
================================================
FILE: .clang-format
================================================
Language: Cpp
BasedOnStyle: WebKit
AccessModifierOffset: -2
AlignAfterOpenBracket: Align
AlignArrayOfStructures: None
AlignConsecutiveAssignments: None
AlignConsecutiveBitFields: Consecutive
AlignConsecutiveDeclarations: None
AlignConsecutiveMacros: None
AlignEscapedNewlines: Left
AlignOperands: Align
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortCaseLabelsOnASingleLine: true
AllowShortEnumsOnASingleLine: true
AllowShortFunctionsOnASingleLine: Empty
AllowShortIfStatementsOnASingleLine: WithoutElse
AllowShortLambdasOnASingleLine: Inline
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: true
AttributeMacros:
- JEMALLOC_NOTHROW
- FEX_ALIGNED
- FEX_ANNOTATE
- FEX_DEFAULT_VISIBILITY
- FEX_NAKED
- FEX_PACKED
- FEXCORE_PRESERVE_ALL_ATTR
- GLIBC_ALIAS_FUNCTION
BinPackArguments: true
BinPackParameters: true
BitFieldColonSpacing: Both
BreakAfterAttributes: Leave
BreakBeforeBraces: Attach
BreakBeforeBinaryOperators: None
BreakBeforeInlineASMColon: OnlyMultiline # clang 16 required
BreakBeforeTernaryOperators: false
BreakConstructorInitializers: BeforeComma
BreakInheritanceList: BeforeColon
ColumnLimit: 140
CompactNamespaces: false
ConstructorInitializerIndentWidth: 2
ContinuationIndentWidth: 2
Cpp11BracedListStyle: true
DerivePointerAlignment: false
EmptyLineAfterAccessModifier: Leave
EmptyLineBeforeAccessModifier: Leave
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
IncludeBlocks: Preserve
IndentAccessModifiers: false
IndentCaseBlocks: false
IndentCaseLabels: false
IndentExternBlock: AfterExternBlock
IndentGotoLabels: false
IndentPPDirectives: None
IndentRequires: false
IndentWidth: 2
InsertBraces: true
KeepEmptyLinesAtTheStartOfBlocks: true
LambdaBodyIndentation: Signature
LineEnding: LF # clang 16 required
MaxEmptyLinesToKeep: 2
NamespaceIndentation: Inner
QualifierAlignment: Left
PackConstructorInitializers: Never
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 2
PenaltyBreakOpenParenthesis: 2
PenaltyBreakString: 10
PenaltyBreakTemplateDeclaration: 8
PenaltyExcessCharacter: 2
PenaltyReturnTypeOnItsOwnLine: 16
PointerAlignment: Left
RemoveBracesLLVM: false
ReferenceAlignment: Left
ReflowComments: true
RequiresClausePosition: WithPreceding
SeparateDefinitionBlocks: Leave
SortIncludes: Never
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: false
SpaceAroundPointerQualifiers: Default
SpaceBeforeAssignmentOperators: true
SpaceBeforeCaseColon: false
SpaceBeforeCpp11BracedList: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: Custom
SpaceBeforeParensOptions:
AfterControlStatements: true
AfterFunctionDeclarationName: false
AfterFunctionDefinitionName: false
AfterOverloadedOperator: false
AfterRequiresInClause: true
BeforeNonEmptyParentheses: false
SpaceBeforeRangeBasedForLoopColon: true
SpaceBeforeSquareBrackets: false
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: Leave
SpacesInCStyleCastParentheses: false
SpacesInConditionalStatement: false
SpacesInParentheses: false
Standard: c++20
UseTab: Never
================================================
FILE: .clang-format-ignore
================================================
# This file is used to ignore files and directories from clang-format
Source/Common/cpp-optparse/*
# Files with human-indented tables for readability - don't mess with these
FEXCore/Source/Interface/Core/X86Tables/*.cpp
# Inline headers with list-like content that can't be processed individually
Source/Tools/LinuxEmulation/LinuxSyscalls/x*/SyscallsNames.inl
Source/Tools/LinuxEmulation/LinuxSyscalls/x*/Ioctl/*.inl
# Include files in unittests
unittests/*ASM/Includes/*.inc
================================================
FILE: .git-blame-ignore-revs
================================================
# Since version 2.23 (released in August 2019), git-blame has a feature
# to ignore or bypass certain commits.
#
# This file contains a list of commits that are not likely what you
# are looking for in a blame, such as mass reformatting or renaming.
# You can set this file as a default ignore file for blame by running
# the following command.
#
# $ git config blame.ignoreRevsFile .git-blame-ignore-revs
# Whole tree reformat PR#3571
2b4ec88daebd35fefb5bf5c73d7fc2b4155771ed
# Second reformat to find fixed point PR#3577
905aa935f5ce344a48ef4d5edab3c31efa8d793e
# Reformat of CodeEmitter inl files
8760c593ece92d7e9fa94c40da0368fd367c9cad
# Whole-tree reformat with clang-format-19
5267cde60e7642852d18f20ae8568643bb5293d5
# Minor reformat with clang-format-19
9fdd96af61c969cb5732471223f00eda64b7a069
# Reformat of X86Tables.h
ba2b0ef809f66f1a6d334f000798fa2ceafab26f
================================================
FILE: .github/ISSUE_TEMPLATE/potential-game-bug.md
================================================
---
name: Potential Game Bug
about: A bug in FEX-Emu that causes a problem in a game
title: "[Game]: [Short Problem Description]"
labels: Game related
assignees: ''
---
**What Game**
The game name.
A link to the storefront where to get the game. GOG, Steam, Itch.io, etc
**Describe the bug**
A clear and concise description of what the bug is.
**To Reproduce**
Steps to reproduce the behavior:
1. Go to '...'
2. Click on '....'
3. Scroll down to '....'
4. See error
**Expected behavior**
A clear and concise description of what you expected to happen.
**Screenshots and Video**
If applicable, add screenshots and video to help explain your problem.
**System information:**
- OS: [eg: Ubuntu 21.10]
- CPU/SoC: [eg: Snapdragon 888, Intel Core i8-12900k]
- Video driver version: [eg: OpenGL ES 3.2 Mesa 22.0.0-devel (git-9ff086052a)]
- RootFS used: [eg: Ubuntu 21.10 Official Rootfs]
- FEX version: (FEXGetConfig --version) [eg: FEX-2112-155-gc691d709]
- Thunks Enabled: [Yes/No]
**Additional context**
- Is this an x86 or x86-64 game: [x86/x86-64/Both]
- Does this reproduce on AArch64 with Radeon/Intel/Nvidia: [Yes/No/Untested]
- Is this a Vulkan game: [Yes/No/Unknown]
- If Yes, What is your Vulkan driver:
Add any other context about the problem here.
================================================
FILE: .github/workflows/ccpp.yml
================================================
name: Build + Test
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
CC: clang
CXX: clang++
FEX_PORTABLE: 1
jobs:
build_plus_test:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner info
run: |
echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
echo "runner_name=$(hostname)" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True \
-DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True \
-DCMAKE_INSTALL_PREFIX="$PWD"/build/install
# These steps make a lot of noise but rarely fail.
# Put them in a separate step to make normal build logs easier to parse
- name: Noisy Build Targets
run: cmake --build build --target asm_files 32bit_asm_files JemallocLibs Catch2 vixl cephes_128bit
- name: Build
id: build
run: cmake --build build
- name: Install
run: cmake --build build --target install
# GCC tests
- name: GCC64 Target Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: gcc_target_tests_64
- name: GCC32 Target Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: gcc_target_tests_32
# API tests
- name: API Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: api_tests
- name: FEXCore API Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: fexcore_apitests
# ARM emission tests
- name: ARM Emitter Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: emitter_tests
# Linux tests
- name: FEX Linux Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: fex_linux_tests_all
env:
FEX_PORTABLE: 0
# Thunking
- name: Thunkgen tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: thunkgen_tests
- name: Test GL No-Thunks
if: ${{ steps.build.outcome == 'success' && matrix.arch[1] == 'x64' }}
uses: ./.github/workflows/test
with:
target: thunk_functional_tests_nothunks
env:
DISPLAY: ':0'
- name: Test GL Thunks
if: ${{ steps.build.outcome == 'success' && matrix.arch[1] == 'x64' }}
uses: ./.github/workflows/test
with:
target: thunk_functional_tests_thunks
env:
DISPLAY: ':0'
# ASM tests
- name: ASM Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: asm_tests
# POSIX tests
- name: POSIX Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: posix_tests
# GVisor tests
- name: GVisor Tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: gvisor_tests
# Struct verifier tests
- name: Struct verifier tests
if: steps.build.outcome == 'success'
uses: ./.github/workflows/test
with:
target: struct_verifier
- name: Remove old SHM regions
if: ${{ always() }}
run: cmake --build build --target remove_old_shm_regions
- name: Upload results
if: ${{ always() }}
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
name: Results-${{ env.runner_name }}-${{ env.runner_label }}
path: results/*.log
retention-days: 3
================================================
FILE: .github/workflows/glibc_fault.yml
================================================
name: GLIBC fault test
# This workflow file is the same as the `Build + Test` with some key differences
# - Runs on any x86 and ARM64 runner
# - Disables the glibc jemalloc compile option
# - Enables the glibc allocator fault option
# - Disables gvisor tests to reduce stress on CI machines (tmp/shm tests overwhelm them)
# - Disables thunk tests since they are incompatible with glibc fault allocator
# - Disables ARMEmitter tests (We don't want to fault test vixl's disassembler)
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
CC: clang
CXX: clang++
FEX_PORTABLE: 1
jobs:
glibc_fault_test:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, ARM64]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner info
run: |
echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
echo "runner_name=$(hostname)" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False \
-DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True \
-DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False \
-DCMAKE_INSTALL_PREFIX="$PWD"/build/install
# These steps make a lot of noise but rarely fail.
# Put them in a separate step to make normal build logs easier to parse
- name: Noisy Build Targets
run: cmake --build build --target asm_files 32bit_asm_files JemallocLibs Catch2 vixl cephes_128bit
- name: Build
run: cmake --build build
- name: Install
run: cmake --build build --target install
# GCC tests
- name: GCC64 Target Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: gcc_target_tests_64
- name: GCC32 Target Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: gcc_target_tests_32
# API Tests
- name: API Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: api_tests
- name: FEXCore API Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: fexcore_apitests
# Linux tests
- name: FEX Linux Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: fex_linux_tests_all
# ASM Tests
- name: ASM Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: asm_tests
# POSIX Tests
- name: POSIX Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: posix_tests
- name: Remove old SHM regions
if: ${{ always() }}
run: cmake --build build --target remove_old_shm_regions
- name: Upload results
if: ${{ always() }}
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
name: Results-${{ env.runner_name }}-${{ env.runner_label }}
path: results/*.log
retention-days: 3
================================================
FILE: .github/workflows/hostrunner.yml
================================================
name: Hostrunner tests
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
CC: clang
CXX: clang++
FEX_PORTABLE: 1
jobs:
hostrunner_tests:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, x64]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner info
run: |
echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
echo "runner_name=$(hostname)" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False \
-DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
# These steps make a lot of noise but rarely fail.
# Put them in a separate step to make normal build logs easier to parse
- name: Noisy Build Targets
run: cmake --build build --target asm_files 32bit_asm_files JemallocLibs Catch2 vixl cephes_128bit
- name: Build
run: cmake --build build
# ASM tests
- name: ASM Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: asm_tests
- name: Upload results
if: ${{ always() }}
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
name: Results-${{ env.runner_name }}-${{ env.runner_label }}
path: results/*.log
retention-days: 3
================================================
FILE: .github/workflows/instcountci.yml
================================================
name: Instruction Count CI run
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
CC: clang
CXX: clang++
jobs:
instcountci_tests:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, x64], [self-hosted, ARM64]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner info
run: |
echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
echo "runner_name=$(hostname)" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Set VIXL_SIM_ENABLED
run: |
case '${{ matrix.arch[1] }}' in
x64) _sim=True ;;
ARM64) _sim=False ;;
esac
echo "VIXL_SIM_ENABLED=$_sim" >> $GITHUB_ENV
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=$VIXL_SIM_ENABLED \
-DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
- name: Build
env:
FEX_DISABLETELEMETRY: 1
run: cmake --build build --target CodeSizeValidation instcountci_test_files
- name: Instruction Count Tests
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: instcountci_tests
- name: Update local repo instcount
if: ${{ always() }}
run: cmake --build build --target instcountci_update_tests
- name: Check InstCountCI diff
if: ${{ always() }}
run: git --no-pager diff --exit-code HEAD
- name: Upload results
if: ${{ always() }}
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
name: Results-${{ env.runner_name }}-${{ env.runner_label }}
path: results/*.log
retention-days: 3
================================================
FILE: .github/workflows/mingw_build.yml
================================================
name: Mingw build
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
BUILD_TYPE: Debug
jobs:
mingw_build:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, ARM64, mingw], [self-hosted, ARM64EC, mingw, ARM64]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner label
run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
- name: Add MingGW to PATH
run: echo "$HOME/llvm-mingw/build/bin/" >> $GITHUB_PATH
- name: Set CC
run: |
case '${{ matrix.arch[1] }}' in
x64) _cpu=x86_64 ;;
ARM64) _cpu=aarch64 ;;
ARM64EC) _cpu=arm64ec ;;
esac
echo "MINGW_TRIPLE=${_cpu}-w64-mingw32" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/Data/CMake/toolchain_mingw.cmake \
-DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTING=False \
-DCMAKE_INSTALL_PREFIX="$PWD"/build/install
- name: Build
run: cmake --build build
================================================
FILE: .github/workflows/pr-code-format.yml
================================================
# Inspired by LLVM's pr-code-format.yml at
# https://github.com/llvm/llvm-project/blob/main/.github/workflows/pr-code-format.yml
name: Check code formatting
on:
pull_request:
branches:
- main
jobs:
code_formatter:
runs-on: [self-hosted, X64]
if: github.repository == 'FEX-Emu/FEX'
steps:
- name: Checkout
uses: actions/checkout@v4
with:
ref: ${{ github.event.pull_request.head.sha }}
- name: Checkout through merge base
uses: rmacklin/fetch-through-merge-base@v0
timeout-minutes: 3
with:
base_ref: ${{ github.event.pull_request.base.ref }}
head_ref: ${{ github.event.pull_request.head.sha }}
deepen_length: 500
- name: Get changed files
run: |
BASE=$(git merge-base main HEAD)
FILES=$(git diff --name-only "$BASE" | tr '\n' ',' | sed 's/,$//')
echo "CHANGED_FILES=$FILES" >> $GITHUB_ENV
echo "Changed files:"
echo "$FILES"
- name: Check git-clang-format-19 exists
run: which git-clang-format-19
- name: Setup Python env
uses: actions/setup-python@v4
with:
python-version: 3.11
cache: pip
cache-dependency-path: ./External/code-format-helper/requirements_formatting.txt
- name: Install python dependencies
run: pip install -r ./External/code-format-helper/requirements_formatting.txt
- name: Run code formatter
env:
CLANG_FORMAT_PATH: git-clang-format-19
GITHUB_PR_NUMBER: ${{ github.event.pull_request.number }}
START_REV: ${{ github.event.pull_request.base.sha }}
END_REV: ${{ github.event.pull_request.head.sha }}
run: |
python ./External/code-format-helper/code-format-helper.py \
--repo "FEX-Emu/FEX" \
--issue-number "$GITHUB_PR_NUMBER" \
--start-rev "$START_REV" \
--end-rev "$END_REV" \
--changed-files "$CHANGED_FILES"
================================================
FILE: .github/workflows/setup-env/action.yml
================================================
name: Setup Build Environment
description: Setup RootFS and build environment
inputs:
setup-rootfs:
description: 'Whether or not to set up the rootfs'
default: true
runs:
using: composite
steps:
- name: Set rootfs paths
if: ${{ inputs.setup-rootfs == 'true' }}
shell: bash
run: |
echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
- name: Update RootFS cache
if: ${{ inputs.setup-rootfs == 'true' }}
shell: bash
run: python3 Scripts/CI_FetchRootFS.py
- name: Checkout Submodules
shell: bash
run: |
git submodule sync --recursive
git submodule update --init --depth 1
- name: Clean Build Environment
shell: bash
run: rm -Rf build
================================================
FILE: .github/workflows/steamrt4.yml
================================================
name: steamrt4 build
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
DEBIAN_FRONTEND: noninteractive
BUILD_TYPE: Release
CC: clang
CXX: clang++
jobs:
steamrt4_build:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, ARM64, distrobox]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner label
run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
with:
setup-rootfs: false
# Setup everything required.
- name : distrobox setup
run: |
distrobox create -Y -i registry.gitlab.steamos.cloud/steamrt/steamrt4/sdk/arm64:4.0.20251117.183306 steamrt4 || true
distrobox upgrade steamrt4
distrobox enter --name steamrt4 -- sudo apt-get install -y \
git cmake ninja-build ccache \
lld clang \
libclang-dev llvm-dev \
libstdc++-14-dev-i386-cross libgcc-14-dev-i386-cross \
libstdc++-14-dev-amd64-cross libgcc-14-dev-amd64-cross
- name: Configure CMake
run: |
distrobox enter --name steamrt4 -- cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE \
-G Ninja -DBUILD_STEAM_SUPPORT=True -DENABLE_LTO=True -DENABLE_ASSERTIONS=False -DBUILD_THUNKS=True \
-DBUILD_FEXCONFIG=False -DBUILD_TESTING=False -DENABLE_CLANG_THUNKS=True -DUSE_LINKER=lld \
-DCMAKE_INSTALL_PREFIX=/usr
- name: Build
run: distrobox enter --name steamrt4 -- cmake --build build
- name: install
run: DESTDIR="$PWD"/install distrobox enter --name steamrt4 -- cmake --build build -t install
- name: Upload libraries
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
overwrite: true
name: steamrt4_steampipe_depot
path: ${{ github.workspace }}/install/*
retention-days: 60
compression-level: 9
================================================
FILE: .github/workflows/test/action.yml
================================================
name: Run Test and Store Logs
description: Run a test and store the log.
inputs:
target:
description: 'The test target to run'
required: true
runs:
using: composite
steps:
- name: Run Tests
shell: bash
run: cmake --build build --target ${{ inputs.target }}
- name: Move and Truncate Results
if: ${{ always() }}
shell: bash
run: |
mkdir -p results
mv build/Testing/Temporary/LastTest.log results/${{ inputs.target }}.log || true
truncate --size="<20M" results/${{ inputs.target }}.log || true
================================================
FILE: .github/workflows/vixl_simulator.yml
================================================
name: Vixl Simulator run
on:
push:
branches:
- main
pull_request:
branches:
- main
env:
# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
BUILD_TYPE: Release
CC: clang
CXX: clang++
FEX_PORTABLE: 1
jobs:
vixl_simulator:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
# Only the x86-64 runner is fast enough to run this
arch: [[self-hosted, x64], [self-hosted, ARMv8.4]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Set runner info
run: |
echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
echo "runner_name=$(hostname)" >> $GITHUB_ENV
- name: Setup Build Environment
uses: ./.github/workflows/setup-env
- name: Configure CMake
run: |
cmake -S . -B build -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_LTO=False \
-DENABLE_VIXL_DISASSEMBLER=True -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
# These steps make a lot of noise but rarely fail.
# Put them in a separate step to make normal build logs easier to parse
- name: Noisy Build Targets
run: cmake --build build --target asm_files 32bit_asm_files JemallocLibs Catch2 vixl cephes_128bit
- name: Build
run: cmake --build build
- name: ASM Tests - SVE256
if: ${{ always() }}
uses: ./.github/workflows/test
with:
target: asm_tests
- name: ASM Tests - SVE128
if: ${{ always() }}
uses: ./.github/workflows/test
env:
FEX_FORCESVEWIDTH: "128"
with:
target: asm_tests
- name: ASM Tests - ASIMD
if: ${{ always() }}
uses: ./.github/workflows/test
env:
FEX_HOSTFEATURES: "disablesve"
with:
target: asm_tests
- name: Upload results
if: ${{ always() }}
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
name: Results-${{ env.runner_name }}-${{ env.runner_label }}
path: results/*.log
retention-days: 3
================================================
FILE: .github/workflows/wine_build/action.yml
================================================
name: Wine DLL Build
description: Build a wow64 or arm64ec Wine DLL
inputs:
target:
description: 'The target (arm64ec or wow64)'
required: true
runs:
using: composite
steps:
- name: Clean Build Environment
shell: bash
run: rm -Rf build_${{ inputs.target }}
- name: Configure CMake
shell: bash
run: |
case "${{ inputs.target }}" in
wow64) _cc=aarch64 ;;
arm64ec) _cc=arm64ec ;;
esac
cmake -S . -B build_${{ inputs.target }} -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=Data/CMake/toolchain_mingw.cmake \
-DMINGW_TRIPLE=${_cc}-w64-mingw32 -DCMAKE_INSTALL_LIBDIR=/usr/lib/wine/aarch64-windows -G Ninja \
-DENABLE_LTO=False -DENABLE_ASSERTIONS=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False \
-DBUILD_TESTING=False -DCMAKE_INSTALL_PREFIX=/usr -DTUNE_ARCH=generic -DTUNE_CPU=none
- name: Build
shell: bash
run: cmake --build build_${{ inputs.target }}
- name: Install
shell: bash
run: DESTDIR="$PWD"/install cmake --build build_${{ inputs.target }} -t install
================================================
FILE: .github/workflows/wine_dll_artifacts.yml
================================================
name: Wine DLL artifacts
on:
push:
branches:
- main
env:
BUILD_TYPE: Release
jobs:
wine_dll_artifacts:
runs-on: ${{ matrix.arch }}
strategy:
matrix:
arch: [[self-hosted, ARM64, mingw]]
fail-fast: false
steps:
- uses: actions/checkout@v6
with:
fetch-depth: '0'
fetch-tags: 'true'
- name: Add MingGW to PATH
run: echo "$HOME/llvm-mingw/build/bin/" >> $GITHUB_PATH
- name: Checkout Submodules
# Need to update submodules
run: |
git submodule sync --recursive
git submodule update --init --depth 1
- name: Clean install directory
run: rm -Rf install
- name: Build (wow64)
uses: ./.github/workflows/wine_build
with:
target: wow64
- name: Build (arm64ec)
uses: ./.github/workflows/wine_build
with:
target: arm64ec
- name: Upload libraries
uses: actions/upload-artifact@v6
timeout-minutes: 1
with:
overwrite: true
name: wine_dll_artifacts
path: ${{ github.workspace }}/install/usr/lib/wine/aarch64-windows/lib*.dll
retention-days: 60
compression-level: 9
================================================
FILE: .gitignore
================================================
# Existing
compile_commands.json
vim_rc
Config.json
[Bb]uild*
[Bb]in/
out/
.vscode/
.vs/
*.pyc
.cache
.idea/
CMakeLists.txt.user
================================================
FILE: .gitlab-ci.yml
================================================
spec:
inputs:
PROMOTE_BRANCH:
description: "Branch to promote the build to. Empty means no promotion."
default: "bleeding-edge"
---
workflow:
rules:
- when: always
variables:
PROMOTE_BRANCH: $[[ inputs.PROMOTE_BRANCH ]]
variables:
DEBIAN_FRONTEND: noninteractive
GIT_SUBMODULE_STRATEGY: recursive
GIT_DEPTH: 0
CC: clang
CXX: clang++
build:
stage: build
image: registry.gitlab.steamos.cloud/steamrt/steamrt4/sdk/arm64:4.0.20251117.183306
tags:
- docker
- linux
- arm64
- aarch64
script:
- apt-get -y update
- apt-get install -y
git cmake ninja-build ccache
lld clang
libclang-dev llvm-dev
libstdc++-14-dev-i386-cross libgcc-14-dev-i386-cross
libstdc++-14-dev-amd64-cross libgcc-14-dev-amd64-cross
- cmake -E make_directory build/
- cmake -DCMAKE_BUILD_TYPE=Release -G Ninja -DBUILD_STEAM_SUPPORT=True -DENABLE_LTO=True -DENABLE_ASSERTIONS=False -DBUILD_THUNKS=True -DBUILD_FEXCONFIG=False -DBUILD_TESTING=False -DENABLE_CLANG_THUNKS=True -DUSE_LINKER=lld -DCMAKE_INSTALL_PREFIX=/usr -DTUNE_ARCH=armv8.2-a -DTUNE_CPU=none . -B build/
- cmake --build build/ --config Release
- DESTDIR=$(pwd)/install/ cmake --build build/ --config Release -t install
artifacts:
name: "steamrt artifacts"
untracked: false
paths:
- install/
promote:
stage: deploy
variables:
GIT_STRATEGY: none
image: registry.gitlab.steamos.cloud/steamrt/steamrt4/sdk/arm64:4.0.20251117.183306
tags:
- docker
- linux
- arm64
- aarch64
rules:
- if: '$PROMOTE_BRANCH'
before_script:
- apt-get -y update
- apt-get install -y tmux curl
script:
# comment out to debug: SSH in via GCP, go down the container and attach to the session (with `tmux attach -t debug`)
# - tmux new-session -d -s debug
# - while tmux has-session -t debug 2>/dev/null; do sleep 1; done
# ref controls which fex-depot code runs the pipeline, while VERSION_PARAM controls which fex branch's artifacts that pipeline downloads.
- >
curl --fail --location --request POST --form token=${FEX_DEPOT_TRIGGER_TOKEN} --form ref=master --form "variables[PROMOTE_BRANCH]=${PROMOTE_BRANCH}" --form "variables[VERSION_PARAM]=${CI_COMMIT_REF_NAME}" "${CI_API_V4_URL}/projects/fex%2Ffex-depot/trigger/pipeline"
================================================
FILE: .gitmodules
================================================
[submodule "External/vixl"]
shallow = true
path = External/vixl
url = https://github.com/FEX-Emu/vixl.git
[submodule "External/cpp-optparse"]
path = Source/Common/cpp-optparse
url = https://github.com/Sonicadvance1/cpp-optparse
[submodule "External/fex-posixtest-bins"]
shallow = true
path = External/fex-posixtest-bins
url = https://github.com/FEX-Emu/fex-posixtest-bins.git
[submodule "External/fex-gvisor-tests-bins"]
shallow = true
path = External/fex-gvisor-tests-bins
url = https://github.com/FEX-Emu/fex-gvisor-tests-bins.git
[submodule "External/fex-gcc-target-tests-bins"]
shallow = true
path = External/fex-gcc-target-tests-bins
url = https://github.com/FEX-Emu/fex-gcc-target-tests-bins.git
[submodule "External/fmt"]
path = External/fmt
url = https://github.com/fmtlib/fmt.git
[submodule "External/drm-headers"]
path = External/drm-headers
url = https://github.com/FEX-Emu/drm-headers.git
[submodule "External/xxhash"]
path = External/xxhash
url = https://github.com/Cyan4973/xxHash.git
[submodule "External/Catch2"]
path = External/Catch2
url = https://github.com/catchorg/Catch2.git
[submodule "External/Vulkan-Headers"]
shallow = true
path = External/Vulkan-Headers
url = https://github.com/KhronosGroup/Vulkan-Headers.git
[submodule "External/jemalloc_glibc"]
path = External/jemalloc_glibc
url = https://github.com/FEX-Emu/jemalloc.git
[submodule "External/tracy"]
path = External/tracy
url = https://github.com/wolfpld/tracy
[submodule "External/range-v3"]
path = External/range-v3
url = https://github.com/ericniebler/range-v3.git
[submodule "External/zydis"]
shallow = true
path = External/zydis
url = https://github.com/zyantific/zydis.git
[submodule "External/unordered_dense"]
path = External/unordered_dense
url = https://github.com/martinus/unordered_dense.git
[submodule "External/rpmalloc"]
path = External/rpmalloc
url = https://github.com/FEX-Emu/rpmalloc.git
================================================
FILE: CMakeLists.txt
================================================
cmake_minimum_required(VERSION 3.14)
project(FEX C CXX ASM)
include(CheckIncludeFiles)
check_include_files("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests (requires x86 compiler)" FALSE)
option(BUILD_THUNKS "Build thunks" FALSE)
option(BUILD_FEXCONFIG "Build FEXConfig" TRUE)
option(ENABLE_CLANG_THUNKS "Build thunks with clang" TRUE)
option(ENABLE_IWYU "Enable the Include What You Use sanitizer" FALSE)
option(ENABLE_LTO "Enable LTO with compilation" TRUE)
option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
set(USE_LINKER "" CACHE STRING "Path to a custom linker program")
option(ENABLE_UBSAN "Enable the Clang Undefined Behavior Sanitizer" FALSE)
option(ENABLE_ASAN "Enable the Clang Address Sanitizer" FALSE)
option(ENABLE_TSAN "Enable the Clang Thread Sanitizer" FALSE)
option(ENABLE_COVERAGE "Enable Code Coverage" FALSE)
option(ENABLE_ASSERTIONS "Enable debug assertions" FALSE)
option(ENABLE_GDB_SYMBOLS "Enable GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
option(ENABLE_STRICT_WERROR "Enable stricter -Werror" FALSE)
option(ENABLE_WERROR "Enable -Werror" FALSE)
option(ENABLE_FEX_ALLOCATOR "Enable allocator for FEX" TRUE)
option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enable jemalloc glibc allocator" TRUE)
option(ENABLE_OFFLINE_TELEMETRY "Enable FEX offline telemetry" TRUE)
option(ENABLE_COMPILE_TIME_TRACE "Enable time trace compile option" FALSE)
option(ENABLE_LIBCXX "Use LLVM's libc++ instead of the GNU libstdc++" FALSE)
option(ENABLE_CCACHE "Enable ccache for build caching" TRUE)
option(ENABLE_VIXL_SIMULATOR "Use the VIXL simulator for emulation (only useful for CI testing)" FALSE)
option(ENABLE_VIXL_DISASSEMBLER "Enable debug disassembler output with VIXL" FALSE)
option(ENABLE_ZYDIS "Enable x86/x86-64 guest disassembler output with Zydis" FALSE)
option(USE_LEGACY_BINFMTMISC "Use legacy method of setting up binfmt_misc" FALSE)
option(ENABLE_FEXCORE_PROFILER "Enable FEXCore's timeline profiling capabilities" FALSE)
set(FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend to use for FEXCore's profiler")
set_property(CACHE FEXCORE_PROFILER_BACKEND PROPERTY STRINGS gpuvis tracy)
option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
option(USE_PDB_DEBUGINFO "Build debug info in PDB format" FALSE)
option(BUILD_STEAM_SUPPORT "Enable Steam integration" FALSE)
set(X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
set(X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
set(X86_DEV_ROOTFS "/" CACHE FILEPATH "Path to the sysroot used for cross-compiling for i686 and x86_64")
set(DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
set(HOSTLIBS_DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
if (NOT DATA_DIRECTORY)
set(DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu")
endif()
include(GNUInstallDirs)
if (NOT HOSTLIBS_DATA_DIRECTORY)
set(HOSTLIBS_DATA_DIRECTORY "${CMAKE_INSTALL_FULL_LIBDIR}/fex-emu")
endif()
## Platform Checks ##
# Only 64-bit Linux and Windows are supported
# NB: SIZEOF_VOID_P is in bytes, not bits
# On 32-bit systems this is set to 4
if (NOT CMAKE_SIZEOF_VOID_P EQUAL 8)
message(FATAL_ERROR "Unsupported pointer size ${CMAKE_SIZEOF_VOID_P}."
" FEX only supports 64-bit (8-byte pointer) systems."
" If you believe this is in error, file an issue.")
elseif (NOT (WIN32 OR CMAKE_SYSTEM_NAME STREQUAL "Linux"))
message(FATAL_ERROR "Unsupported system type ${CMAKE_SYSTEM_NAME}."
" FEX only supports Linux and Windows."
" If you believe this is in error, file an issue.")
endif()
## Compiler Checks ##
# GCC and MSVC are unsupported
if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
message(FATAL_ERROR "FEX doesn't support GCC! Use Clang instead.")
elseif (MSVC)
message(FATAL_ERROR "FEX doesn't support MSVC! Use Clang on MinGW instead.")
elseif (MINGW)
message(STATUS "Building for MinGW")
set(ENABLE_FEX_ALLOCATOR TRUE)
set(ENABLE_JEMALLOC_GLIBC_ALLOC FALSE)
else ()
message(STATUS "Clang version ${CMAKE_CXX_COMPILER_VERSION}")
set(CLANG_MINIMUM_VERSION 13.0)
if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS ${CLANG_MINIMUM_VERSION})
message(FATAL_ERROR "Clang version too old for FEX. Need at least ${CLANG_MINIMUM_VERSION} but has ${CMAKE_CXX_COMPILER_VERSION}")
endif()
endif()
## Architecture Handling ##
string(TOLOWER ${CMAKE_SYSTEM_PROCESSOR} processor)
if (processor MATCHES "x86|amd64")
option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
if (NOT ENABLE_X86_HOST_DEBUG)
message(FATAL_ERROR
" FEX doesn't support compiling for x86-64 hosts!"
" This is /only/ a supported configuration for FEX CI and nothing else!")
else()
message(STATUS "x86_64 debug build")
endif()
set(ARCHITECTURE_x86_64 1)
add_compile_definitions(ARCHITECTURE_x86_64=1)
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
elseif (processor MATCHES "^aarch64|^arm64|^armv8\.*")
set(ARCHITECTURE_arm64 1)
add_compile_definitions(ARCHITECTURE_arm64=1)
# arm64ec needs to define both arm64 and arm64ec
if (processor MATCHES "^arm64ec")
set(ARCHITECTURE_arm64ec 1)
add_compile_definitions(ARCHITECTURE_arm64ec=1)
endif()
endif()
if (NOT (ARCHITECTURE_arm64 OR ARCHITECTURE_arm64ec OR ARCHITECTURE_x86_64))
message(FATAL_ERROR "Unsupported processor type ${processor}."
" If you believe this is in error, file an issue.")
endif()
if (BUILD_STEAM_SUPPORT)
add_compile_definitions(FEX_STEAM_SUPPORT=1)
endif()
if (ENABLE_FEXCORE_PROFILER)
add_compile_definitions(ENABLE_FEXCORE_PROFILER=1)
string(TOUPPER "${FEXCORE_PROFILER_BACKEND}" FEXCORE_PROFILER_BACKEND)
if (FEXCORE_PROFILER_BACKEND STREQUAL "GPUVIS")
add_compile_definitions(FEXCORE_PROFILER_BACKEND=1)
elseif (FEXCORE_PROFILER_BACKEND STREQUAL "TRACY")
add_compile_definitions(FEXCORE_PROFILER_BACKEND=2)
add_compile_definitions(TRACY_ENABLE=1)
# Required so that Tracy will only start in the selected guest application
add_compile_definitions(TRACY_MANUAL_LIFETIME=1)
add_compile_definitions(TRACY_DELAYED_INIT=1)
# This interferes with FEX's signal handling
add_compile_definitions(TRACY_NO_CRASH_HANDLER=1)
# Tracy can gather call stack samples in regular intervals, but this
# isn't useful for us since it would usually sample opaque JIT code
add_compile_definitions(TRACY_NO_SAMPLING=1)
# This pulls in libbacktrace which allocators in global constructors (before FEX can set up its allocator hooks)
add_compile_definitions(TRACY_NO_CALLSTACK=1)
if (MINGW)
message(FATAL_ERROR "Tracy profiler not supported on MinGW")
endif()
else()
message(FATAL_ERROR "Unknown FEXCore profiler backend ${FEXCORE_PROFILER_BACKEND}")
endif()
endif()
if (ENABLE_JEMALLOC_GLIBC_ALLOC AND ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
message(FATAL_ERROR "Can't have both glibc fault allocator and jemalloc glibc allocator enabled at the same time")
endif()
if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
add_compile_definitions(GLIBC_ALLOCATOR_FAULT=1)
endif()
# uninstall target
if(NOT TARGET uninstall)
configure_file(
"${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/cmake_uninstall.cmake.in"
"${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/cmake_uninstall.cmake"
IMMEDIATE @ONLY)
add_custom_target(uninstall
COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/cmake_uninstall.cmake)
endif()
# These options are meant for package management
set(TUNE_CPU "native" CACHE STRING "Override the CPU the build is tuned for")
set(TUNE_ARCH "generic" CACHE STRING "Override the Arch the build is tuned for")
set(OVERRIDE_VERSION "detect" CACHE STRING "Override the FEX version")
set(OVERRIDE_HASH "detect" CACHE STRING "Override the FEX git hash")
get_property(IS_MULTI_CONFIG GLOBAL PROPERTY GENERATOR_IS_MULTI_CONFIG)
if (NOT IS_MULTI_CONFIG AND NOT CMAKE_BUILD_TYPE)
set(CMAKE_BUILD_TYPE Release
CACHE STRING "Choose the type of build." FORCE)
message(STATUS "No build type set, defaulting to a Release build")
endif()
string(TOUPPER "${CMAKE_BUILD_TYPE}" CMAKE_BUILD_TYPE)
if (CMAKE_BUILD_TYPE MATCHES "DEBUG")
set(ENABLE_ASSERTIONS TRUE)
endif()
if (ENABLE_ASSERTIONS)
message(STATUS "Assertions enabled")
add_compile_definitions(ASSERTIONS_ENABLED=1)
endif()
if (ENABLE_GDB_SYMBOLS)
message(STATUS "GDBSymbols support enabled")
add_compile_definitions(GDB_SYMBOLS_ENABLED=1)
endif()
set(CMAKE_CXX_STANDARD 20)
set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
set(CMAKE_INCLUDE_CURRENT_DIR ON)
set(CMAKE_POSITION_INDEPENDENT_CODE ON)
cmake_policy(SET CMP0083 NEW) # Follow new PIE policy
include(CheckPIESupported)
check_pie_supported()
set(CMAKE_INTERPROCEDURAL_OPTIMIZATION ${ENABLE_LTO})
include(CheckCXXSourceCompiles)
set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
check_cxx_source_compiles(
"
__attribute__((preserve_all))
int Testy(int a, int b, int c, int d, int e, int f) {
return a + b + c + d + e + f;
}
int main() {
return Testy(0, 1, 2, 3, 4, 5);
}"
HAS_CLANG_PRESERVE_ALL)
unset(CMAKE_REQUIRED_FLAGS)
if (HAS_CLANG_PRESERVE_ALL)
if (MINGW)
message(STATUS "Ignoring broken clang::preserve_all support")
set(HAS_CLANG_PRESERVE_ALL FALSE)
else()
message(STATUS "Has clang::preserve_all")
endif()
endif()
if (ARCHITECTURE_arm64 AND HAS_CLANG_PRESERVE_ALL)
add_compile_definitions("FEX_PRESERVE_ALL_ATTR=__attribute__((preserve_all))" "FEX_HAS_PRESERVE_ALL_ATTR=1")
else()
add_compile_definitions("FEX_PRESERVE_ALL_ATTR=" "FEX_HAS_PRESERVE_ALL_ATTR=0")
endif()
check_cxx_source_compiles(
"
#define _GNU_SOURCE
#include <errno.h>
int main() {
return program_invocation_name == nullptr;
}"
HAS_PROGRAM_INVOCATION_NAME)
add_compile_definitions("HAS_PROGRAM_INVOCATION_NAME=${HAS_PROGRAM_INVOCATION_NAME}")
if (ENABLE_VIXL_SIMULATOR)
# We can run the simulator on both x86-64 or AArch64 hosts
add_compile_definitions(VIXL_SIMULATOR=1 VIXL_INCLUDE_SIMULATOR_AARCH64=1)
endif()
if (ENABLE_CCACHE)
find_program(CCACHE_PROGRAM ccache)
if(CCACHE_PROGRAM)
message(STATUS "CCache enabled")
set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${CCACHE_PROGRAM}")
endif()
endif()
if (ENABLE_XRAY)
add_compile_options(-fxray-instrument)
link_libraries(-fxray-instrument)
endif()
if (ENABLE_COMPILE_TIME_TRACE)
add_compile_options(-ftime-trace)
link_libraries(-ftime-trace)
endif()
set(PTHREAD_LIB pthread)
if (USE_LINKER)
message(STATUS "Overriding linker to: ${USE_LINKER}")
add_link_options("-fuse-ld=${USE_LINKER}")
endif()
if (ENABLE_LIBCXX)
message(WARNING "This is an unsupported configuration and should only be used for testing")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -stdlib=libc++")
set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -stdlib=libc++ -lc++abi")
endif()
if (NOT ENABLE_OFFLINE_TELEMETRY)
# Disable FEX offline telemetry entirely if asked
add_compile_definitions(FEX_DISABLE_TELEMETRY=1)
endif()
if (ENABLE_UBSAN)
# See https://github.com/FEX-Emu/FEX/pull/4494#issuecomment-2800608944
# and related discussion for the use of -fno-sanitize=alignment -fno-sanitize=function
# with UBSAN.
# alignment: we don't follow a strict alignment policy, for example IR uses packed structs
# that are regularly access unaligned.
# function: syscalls cast function pointers to void (*)(unsigned long...), causing warnings
# related to this access.
add_compile_definitions(ENABLE_UBSAN=1)
add_compile_options(-fno-omit-frame-pointer -fsanitize=undefined -fno-sanitize=alignment -fno-sanitize=function -fno-sanitize-recover=undefined)
link_libraries(-fno-omit-frame-pointer -fsanitize=undefined -fno-sanitize=alignment -fno-sanitize=function -fno-sanitize-recover=undefined)
endif()
if (ENABLE_ASAN)
add_compile_definitions(ENABLE_ASAN=1)
add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
endif()
if (ENABLE_TSAN)
add_compile_options(-fno-omit-frame-pointer -fsanitize=thread)
link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
endif()
if (ENABLE_COVERAGE)
add_compile_options(-fprofile-instr-generate -fcoverage-mapping)
link_libraries(-fprofile-instr-generate -fcoverage-mapping)
endif()
if (ENABLE_JEMALLOC_GLIBC_ALLOC)
# The glibc jemalloc subproject which hooks the glibc allocator.
# Required for thunks to work.
# All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
add_subdirectory(External/jemalloc_glibc/)
elseif (NOT MINGW)
message(STATUS
" jemalloc glibc allocator disabled!\n"
" This is not a recommended configuration!\n"
" This will very explicitly break thunk execution!\n"
" Use at your own risk!")
endif()
if (ENABLE_FEX_ALLOCATOR)
# The rpmalloc subproject that all FEXCore fextl objects allocate through.
add_subdirectory(External/rpmalloc/)
elseif (NOT MINGW)
message (STATUS
" FEX allocator is disabled!\n"
" This is not a recommended configuration!\n"
" This will very explicitly break 32-bit application execution!\n"
" Use at your own risk!")
endif()
if (USE_PDB_DEBUGINFO)
add_compile_options(-g -gcodeview)
add_link_options(-g -Wl,--pdb=)
endif()
set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
set(CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
set(CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
## Modules ##
list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/Data/CMake/)
include(LinkerGC)
## Externals ##
find_package(unordered_dense QUIET CONFIG)
if (NOT unordered_dense_FOUND)
add_subdirectory(External/unordered_dense)
endif()
include(CTest)
if (BUILD_TESTING OR ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
add_subdirectory(External/vixl/)
endif()
if (ENABLE_ZYDIS)
find_package(Zycore 1.5 MODULE QUIET)
find_package(Zydis 4.0 MODULE QUIET)
if (TARGET Zydis::Zydis AND TARGET Zycore::Zycore)
message(STATUS "Using system Zydis")
else()
set(ZYDIS_BUILD_TOOLS OFF CACHE BOOL "" FORCE)
set(ZYDIS_BUILD_EXAMPLES OFF CACHE BOOL "" FORCE)
message(STATUS "Using bundled Zydis")
add_subdirectory(External/zydis/)
endif()
endif()
if (ENABLE_FEXCORE_PROFILER AND FEXCORE_PROFILER_BACKEND STREQUAL "TRACY")
add_subdirectory(External/tracy)
endif()
find_package(Python 3.9 REQUIRED COMPONENTS Interpreter)
set(BUILD_SHARED_LIBS OFF)
if (NOT CMAKE_CROSSCOMPILING)
find_package(xxhash MODULE QUIET)
endif()
if (NOT TARGET xxHash::xxhash)
set(XXHASH_BUNDLED_MODE TRUE)
set(XXHASH_BUILD_XXHSUM FALSE)
add_subdirectory(External/xxhash/cmake_unofficial/)
endif()
add_compile_options(-Wno-trigraphs)
add_compile_definitions(GLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
if (BUILD_TESTING)
find_package(Catch2 3 QUIET)
if (NOT Catch2_FOUND)
add_subdirectory(External/Catch2/)
# Pull in catch_discover_tests definition
list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/External/Catch2/contrib/")
endif()
include(Catch)
else ()
# Override any previously generated test list to avoid running stale test binaries
file(GENERATE OUTPUT CTestTestfile.cmake CONTENT "# No tests since BUILD_TESTING is disabled")
endif()
find_package(fmt QUIET)
if (NOT fmt_FOUND)
# Disable fmt install
set(FMT_INSTALL OFF)
add_subdirectory(External/fmt/)
endif()
find_package(range-v3 QUIET)
if (NOT range-v3_FOUND)
add_subdirectory(External/range-v3/)
target_compile_definitions(range-v3 INTERFACE RANGES_DISABLE_DEPRECATED_WARNINGS)
endif()
add_subdirectory(External/tiny-json/)
include_directories(Source/)
include_directories("${CMAKE_BINARY_DIR}/Source/")
include(CheckCXXCompilerFlag)
# Add in diagnostic colours if the option is available.
# Ninja code generator will kill colours if this isn't here
check_cxx_compiler_flag(-fdiagnostics-color=always GCC_COLOR)
check_cxx_compiler_flag(-fcolor-diagnostics CLANG_COLOR)
check_cxx_compiler_flag(-Wno-deprecated-enum-enum-conversion ENUM_ENUM_WARNING)
if (GCC_COLOR)
add_compile_options(-fdiagnostics-color=always)
endif()
if (CLANG_COLOR)
add_compile_options(-fcolor-diagnostics)
endif()
if(ENUM_ENUM_WARNING)
add_compile_options(-Wno-deprecated-enum-enum-conversion)
endif()
# GCC enables -Wchanges-meaning by default and treats some cases as an error
if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
add_compile_options(-Wno-error=changes-meaning)
endif()
if(ENABLE_WERROR OR ENABLE_STRICT_WERROR)
add_compile_options(-Werror)
if (NOT ENABLE_STRICT_WERROR)
# Disable some Werror that can add frustration when developing
add_compile_options(-Wno-error=unused-variable)
endif()
endif()
set(FEX_TUNE_COMPILE_FLAGS)
if (NOT TUNE_ARCH STREQUAL "generic")
check_cxx_compiler_flag("-march=${TUNE_ARCH}" COMPILER_SUPPORTS_ARCH_TYPE)
if(COMPILER_SUPPORTS_ARCH_TYPE)
list(APPEND FEX_TUNE_COMPILE_FLAGS "-march=${TUNE_ARCH}")
else()
message(FATAL_ERROR "Trying to compile arch type '${TUNE_ARCH}' but the compiler doesn't support this")
endif()
endif()
if (TUNE_CPU STREQUAL "native")
if(ARCHITECTURE_arm64)
if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
# Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
# Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
if(COMPILER_SUPPORTS_CPU_TYPE)
list(APPEND FEX_TUNE_COMPILE_FLAGS "-mcpu=native")
endif()
else()
execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
OUTPUT_VARIABLE AARCH64_CPU)
string(STRIP ${AARCH64_CPU} AARCH64_CPU)
execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/NeedDisabledSVE.py"
RESULT_VARIABLE NEEDS_SVE_DISABLED)
if (NEEDS_SVE_DISABLED)
message(STATUS "Platform has bugged SVE. Disabling")
set(AARCH64_CPU "cortex-a78")
endif()
check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
if(COMPILER_SUPPORTS_CPU_TYPE)
list(APPEND FEX_TUNE_COMPILE_FLAGS "-mcpu=${AARCH64_CPU}")
endif()
endif()
else()
check_cxx_compiler_flag("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
if(COMPILER_SUPPORTS_MARCH_NATIVE)
list(APPEND FEX_TUNE_COMPILE_FLAGS "-march=native")
endif()
endif()
elseif (NOT TUNE_CPU STREQUAL "none")
check_cxx_compiler_flag("-mcpu=${TUNE_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
if(COMPILER_SUPPORTS_CPU_TYPE)
list(APPEND FEX_TUNE_COMPILE_FLAGS "-mcpu=${TUNE_CPU}")
else()
message(FATAL_ERROR "Trying to compile cpu type '${TUNE_CPU}' but the compiler doesn't support this")
endif()
endif()
set(GIT_DESCRIBE_STRING "FEX-Unknown")
if (OVERRIDE_VERSION STREQUAL "detect")
find_package(Git)
if (GIT_FOUND)
execute_process(
COMMAND ${GIT_EXECUTABLE} describe --abbrev=7
WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
OUTPUT_VARIABLE GIT_DESCRIBE_STRING
ERROR_QUIET
OUTPUT_STRIP_TRAILING_WHITESPACE)
endif()
else()
set(GIT_DESCRIBE_STRING "${OVERRIDE_VERSION}")
endif()
set(GIT_HASH "Unknown")
if (OVERRIDE_HASH STREQUAL "detect")
find_package(Git)
if (GIT_FOUND)
execute_process(
COMMAND ${GIT_EXECUTABLE} rev-parse HEAD
WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
OUTPUT_VARIABLE GIT_HASH
ERROR_QUIET
OUTPUT_STRIP_TRAILING_WHITESPACE)
endif()
else()
set(GIT_HASH "${OVERRIDE_HASH}")
endif()
message(STATUS "FEX version: ${GIT_DESCRIBE_STRING}")
message(STATUS "FEX commit: ${GIT_HASH}")
# Prepends 0x to every two-character sequence in the hash,
# OR the final character of the hash, to plumb it for C++ usage. e.g.:
# -DOVERRIDE_HASH=123456aa => 0x12, 0x34, 0x56, 0xaa,
# -DOVERRIDE_HASH=12345678a => 0x12, 0x34, 0x56, 0x78, 0xa,
string(REGEX
REPLACE "(..|.$)" "0x\\1, "
GIT_HASH_ARRAY "${GIT_HASH}")
if (ENABLE_IWYU)
find_program(IWYU_EXE
NAMES iwyu include-what-you-use)
if (IWYU_EXE)
message(STATUS "IWYU enabled")
set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
endif()
endif()
add_compile_options(-Wall)
if (BUILD_TESTING)
message(STATUS "Unit tests are enabled")
set(TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
if (TEST_JOB_COUNT)
message(STATUS "Running tests with ${TEST_JOB_COUNT} jobs")
elseif(CMAKE_VERSION VERSION_LESS "3.29")
execute_process(COMMAND "nproc" OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE TEST_JOB_COUNT)
endif()
set(TEST_JOB_FLAG "-j${TEST_JOB_COUNT}")
endif()
add_subdirectory(External/SoftFloat-3e/)
add_subdirectory(External/cephes/)
add_subdirectory(FEXHeaderUtils/)
add_subdirectory(CodeEmitter/)
add_subdirectory(FEXCore/)
if (ARCHITECTURE_arm64 AND NOT MINGW AND NOT BUILD_STEAM_SUPPORT)
# Binfmt_misc files must be installed prior to Source/ installs
add_subdirectory(Data/binfmts/)
endif()
add_subdirectory(Source/)
if (NOT BUILD_STEAM_SUPPORT)
add_subdirectory(Data/AppConfig/)
endif()
# Install the ThunksDB file
file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/Data/*.json)
# Any application configuration json file gets installed
foreach(CONFIG_SRC ${CONFIG_SOURCES})
install(FILES ${CONFIG_SRC}
DESTINATION ${DATA_DIRECTORY}/
COMPONENT Runtime)
endforeach()
if (BUILD_TESTING)
add_subdirectory(unittests/)
endif()
if (BUILD_THUNKS)
set(FEX_PROJECT_SOURCE_DIR ${PROJECT_SOURCE_DIR})
add_subdirectory(ThunkLibs/Generator)
# Thunk targets for both host libraries and IDE integration
add_subdirectory(ThunkLibs/HostLibs)
# Thunk targets for IDE integration of guest code, only
add_subdirectory(ThunkLibs/GuestLibs)
# Thunk targets for guest libraries
include(ExternalProject)
ExternalProject_Add(guest-libs
PREFIX guest-libs
SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
BINARY_DIR "Guest"
CMAKE_ARGS
"-DBITNESS=64"
"-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
"-DBUILD_FEX_LINUX_TESTS=${BUILD_FEX_LINUX_TESTS}"
"-DENABLE_CLANG_THUNKS=${ENABLE_CLANG_THUNKS}"
"-DCMAKE_TOOLCHAIN_FILE:FILEPATH=${X86_64_TOOLCHAIN_FILE}"
"-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
"-DFEX_PROJECT_SOURCE_DIR=${FEX_PROJECT_SOURCE_DIR}"
"-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
"-DX86_DEV_ROOTFS=${X86_DEV_ROOTFS}"
INSTALL_COMMAND ""
BUILD_ALWAYS ON
DEPENDS thunkgen)
ExternalProject_Add(guest-libs-32
PREFIX guest-libs-32
SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
BINARY_DIR "Guest_32"
CMAKE_ARGS
"-DBITNESS=32"
"-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
"-DBUILD_FEX_LINUX_TESTS=${BUILD_FEX_LINUX_TESTS}"
"-DENABLE_CLANG_THUNKS=${ENABLE_CLANG_THUNKS}"
"-DCMAKE_TOOLCHAIN_FILE:FILEPATH=${X86_32_TOOLCHAIN_FILE}"
"-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
"-DFEX_PROJECT_SOURCE_DIR=${FEX_PROJECT_SOURCE_DIR}"
"-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
"-DX86_DEV_ROOTFS=${X86_DEV_ROOTFS}"
INSTALL_COMMAND ""
BUILD_ALWAYS ON
DEPENDS thunkgen)
install(
CODE "message(\"-- Installing: guest-libs\")"
CODE "
execute_process(COMMAND ${CMAKE_COMMAND} --build . --target install
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest)"
DEPENDS guest-libs
COMPONENT Runtime)
install(
CODE "message(\"-- Installing: guest-libs-32\")"
CODE "
execute_process(COMMAND ${CMAKE_COMMAND} --build . --target install
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32)"
DEPENDS guest-libs-32
COMPONENT Runtime)
add_custom_target(uninstall_guest-libs
COMMAND ${CMAKE_COMMAND} "--build" "." "--target" "uninstall"
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest)
add_custom_target(uninstall_guest-libs-32
COMMAND ${CMAKE_COMMAND} "--build" "." "--target" "uninstall"
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32)
add_dependencies(uninstall uninstall_guest-libs)
add_dependencies(uninstall uninstall_guest-libs-32)
endif()
if (NOT MINGW AND BUILD_STEAM_SUPPORT)
add_subdirectory(Source/Steam/)
endif()
================================================
FILE: CMakeSettings.json
================================================
{
"environments": [
{
"BuildPath": "${projectDir}\\out\\build\\${name}",
"InstallPath": "${projectDir}\\out\\install\\${name}",
"clangcl": "clang-cl.exe",
"cc": "clang",
"cxx": "clang++"
}
],
"configurations": [
{
"name": "WSL-Clang-Debug",
"generator": "Ninja",
"configurationType": "Debug",
"buildRoot": "${env.BuildPath}",
"installRoot": "${env.InstallPath}",
"cmakeExecutable": "/usr/bin/cmake",
"cmakeCommandArgs": "",
"buildCommandArgs": "-v",
"ctestCommandArgs": "",
"wslPath": "${defaultWSLPath}",
"inheritEnvironments": [ "linux_clang_x64" ],
"addressSanitizerRuntimeFlags": "detect_leaks=0",
"variables": [
{
"name": "WSL",
"value": "TRUE",
"type": "BOOL"
}
]
},
{
"name": "WSL-Clang-Release",
"generator": "Ninja",
"configurationType": "RelWithDebInfo",
"buildRoot": "${env.BuildPath}",
"installRoot": "${env.InstallPath}",
"cmakeExecutable": "/usr/bin/cmake",
"cmakeCommandArgs": "",
"buildCommandArgs": "-v",
"ctestCommandArgs": "",
"wslPath": "${defaultWSLPath}",
"inheritEnvironments": [ "linux_clang_x64" ],
"addressSanitizerRuntimeFlags": "detect_leaks=0",
"variables": [
{
"name": "WSL",
"value": "TRUE",
"type": "BOOL"
}
]
},
{
"name": "x86-Clang-Cross-Debug",
"generator": "Ninja",
"configurationType": "Debug",
"buildRoot": "${env.BuildPath}",
"installRoot": "${env.InstallPath}",
"cmakeCommandArgs": "",
"buildCommandArgs": "-v",
"ctestCommandArgs": "",
"inheritEnvironments": [ "clang_cl_x86" ],
"variables": [
{
"name": "CMAKE_C_COMPILER",
"value": "${env.cc}",
"type": "STRING"
},
{
"name": "CMAKE_CXX_COMPILER",
"value": "${env.cxx}",
"type": "STRING"
},
{
"name": "CMAKE_SYSROOT",
"value": "${env.fexsysroot}",
"type": "STRING"
}
]
},
{
"name": "x64-Clang-Cross-Release",
"generator": "Ninja",
"configurationType": "RelWithDebInfo",
"buildRoot": "${env.BuildPath}",
"installRoot": "${env.InstallPath}",
"cmakeCommandArgs": "",
"buildCommandArgs": "-v",
"ctestCommandArgs": "",
"inheritEnvironments": [ "clang_cl_x86" ],
"variables": [
{
"name": "CMAKE_C_COMPILER",
"value": "${env.cc}",
"type": "STRING"
},
{
"name": "CMAKE_CXX_COMPILER",
"value": "${env.cxx}",
"type": "STRING"
},
{
"name": "CMAKE_SYSROOT",
"value": "${env.fexsysroot}",
"type": "STRING"
}
]
},
{
"name": "Linux-Clang-Remote-Debug",
"generator": "Ninja",
"configurationType": "Debug",
"cmakeExecutable": "/usr/bin/cmake",
"remoteCopySourcesExclusionList": [ ".vs", ".vscode", ".git", ".github", "build", "out", "bin" ],
"cmakeCommandArgs": "",
"buildCommandArgs": "-v",
"ctestCommandArgs": "",
"inheritEnvironments": [ "linux_clang_x64" ],
"remoteMachineName": "${env.fexremote}",
"remoteCMakeListsRoot": "$HOME/projects/.vs/${projectDirName}/src",
"remoteBuildRoot": "$HOME/projects/.vs/${projectDirName}/build/${name}",
"remoteInstallRoot": "$HOME/projects/.vs/${projectDirName}/install/${name}",
"remoteCopySources": true,
"rsyncCommandArgs": "-t --delete --delete-excluded",
"remoteCopyBuildOutput": false,
"remoteCopySourcesMethod": "rsync",
"addressSanitizerRuntimeFlags": "detect_leaks=0",
"variables": []
}
]
}
================================================
FILE: CODE_OF_CONDUCT.md
================================================
# Contributor Covenant Code of Conduct
## Our Pledge
In the interest of fostering an open and welcoming environment, we as
contributors and maintainers pledge to making participation in our project and
our community a harassment-free experience for everyone, regardless of age, body
size, disability, ethnicity, sex characteristics, gender identity and expression,
level of experience, education, socio-economic status, nationality, personal
appearance, race, religion, or sexual identity and orientation.
## Our Standards
Examples of behavior that contributes to creating a positive environment
include:
* Using welcoming and inclusive language
* Being respectful of differing viewpoints and experiences
* Gracefully accepting constructive criticism
* Focusing on what is best for the community
* Showing empathy towards other community members
Examples of unacceptable behavior by participants include:
* The use of sexualized language or imagery and unwelcome sexual attention or
advances
* Trolling, insulting/derogatory comments, and personal or political attacks
* Public or private harassment
* Publishing others' private information, such as a physical or electronic
address, without explicit permission
* Other conduct which could reasonably be considered inappropriate in a
professional setting
## Our Responsibilities
Project maintainers are responsible for clarifying the standards of acceptable
behavior and are expected to take appropriate and fair corrective action in
response to any instances of unacceptable behavior.
Project maintainers have the right and responsibility to remove, edit, or
reject comments, commits, code, wiki edits, issues, and other contributions
that are not aligned to this Code of Conduct, or to ban temporarily or
permanently any contributor for other behaviors that they deem inappropriate,
threatening, offensive, or harmful.
## Scope
This Code of Conduct applies both within project spaces and in public spaces
when an individual is representing the project or its community. Examples of
representing a project or community include using an official project e-mail
address, posting via an official social media account, or acting as an appointed
representative at an online or offline event. Representation of a project may be
further defined and clarified by project maintainers.
## Enforcement
Instances of abusive, harassing, or otherwise unacceptable behavior may be
reported by contacting the project team at team@fex-emu.com. All
complaints will be reviewed and investigated and will result in a response that
is deemed necessary and appropriate to the circumstances. The project team is
obligated to maintain confidentiality with regard to the reporter of an incident.
Further details of specific enforcement policies may be posted separately.
Project maintainers who do not follow or enforce the Code of Conduct in good
faith may face temporary or permanent repercussions as determined by other
members of the project's leadership.
## Attribution
This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
[homepage]: https://www.contributor-covenant.org
For answers to common questions about this code of conduct, see
https://www.contributor-covenant.org/faq
================================================
FILE: CodeEmitter/CMakeLists.txt
================================================
add_library(CodeEmitter INTERFACE)
target_include_directories(CodeEmitter INTERFACE .)
================================================
FILE: CodeEmitter/CodeEmitter/ALUOps.inl
================================================
// SPDX-License-Identifier: MIT
/* ALU instruction emitters.
*
* Almost all of these operations have `ARMEmitter::Size` as their first argument.
* This allows both 32-bit and 64-bit selection of how that instruction is going to operate.
*
* Some emitter operations explicitly use `XRegister` or `WRegister`.
* This is usually due to the instruction only supporting one operating size.
* Although in some cases is a minor convenience without any performance implications.
*
* FEX-Emu ALU operations usually have a 32-bit or 64-bit operating size encoded in the IR operation,
* This allows FEX to use a single helper function which decodes to both handlers.
*/
#pragma once
#ifndef INCLUDED_BY_EMITTER
#include <CodeEmitter/Emitter.h>
namespace ARMEmitter {
struct EmitterOps : Emitter {
#endif
private:
static bool IsADRRange(int64_t Imm) {
return Imm >= -1048576 && Imm <= 1048575;
}
static bool IsADRPRange(int64_t Imm) {
return Imm >= -4294967296 && Imm <= 4294963200;
}
static bool IsADRPAligned(int64_t Imm) {
return (Imm & 0xFFF) == 0;
}
public:
// PC relative
void adr(ARMEmitter::Register rd, uint32_t Imm) {
constexpr uint32_t Op = 0b0001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, Imm);
}
[[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, const BackwardLabel* Label) {
int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
if (IsADRRange(Imm)) {
constexpr uint32_t Op = 0b0001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, Imm);
return BranchEncodeSucceeded::Success;
}
// Can't encode.
return BranchEncodeSucceeded::Failure;
}
[[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, ForwardLabel* Label) {
AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::ADR});
constexpr uint32_t Op = 0b0001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, 0);
// Forward label doesn't know if it can encode until Bind.
return BranchEncodeSucceeded::Success;
}
[[nodiscard]] BranchEncodeSucceeded adr(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
if (Label->Backward.Location) {
return adr(rd, &Label->Backward);
} else {
return adr(rd, &Label->Forward);
}
}
void adrp(ARMEmitter::Register rd, uint32_t Imm) {
constexpr uint32_t Op = 0b1001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, Imm);
}
[[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, const BackwardLabel* Label) {
int64_t Imm = reinterpret_cast<int64_t>(Label->Location) - (GetCursorAddress<int64_t>() & ~0xFFFLL);
if (IsADRPRange(Imm) && IsADRPAligned(Imm)) {
constexpr uint32_t Op = 0b1001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, Imm);
return BranchEncodeSucceeded::Success;
}
// Can't encode.
return BranchEncodeSucceeded::Failure;
}
[[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, ForwardLabel* Label) {
AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::ADRP});
constexpr uint32_t Op = 0b1001'0000 << 24;
DataProcessing_PCRel_Imm(Op, rd, 0);
// Forward label doesn't know if it can encode until Bind.
return BranchEncodeSucceeded::Success;
}
[[nodiscard]] BranchEncodeSucceeded adrp(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
if (Label->Backward.Location) {
return adrp(rd, &Label->Backward);
} else {
return adrp(rd, &Label->Forward);
}
}
[[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, const BackwardLabel* Label) {
const auto SLocation = reinterpret_cast<int64_t>(Label->Location);
const auto ULocation = std::bit_cast<uint64_t>(SLocation);
const int64_t Imm = SLocation - (GetCursorAddress<int64_t>());
const auto UImm = std::bit_cast<uint64_t>(Imm);
if (IsADRRange(Imm)) {
// If the range is in ADR range then we can just use ADR.
return adr(rd, Label);
}
if (IsADRPRange(Imm)) {
const int64_t ADRPImm = (SLocation & ~0xFFFLL) - (GetCursorAddress<int64_t>() & ~0xFFFLL);
// If the range is in the ADRP range then we can use ADRP.
const bool NeedsOffset = !IsADRPAligned(ULocation);
const uint64_t AlignedOffset = ULocation & 0xFFFULL;
// First emit ADRP
adrp(rd, ADRPImm >> 12);
if (NeedsOffset) {
// Now even an add
add(ARMEmitter::Size::i64Bit, rd, rd, AlignedOffset);
}
return BranchEncodeSucceeded::Success;
}
// Stinky path, we need to load the address as a sequence of movz+movk+movk
movz(ARMEmitter::Size::i64Bit, rd, (UImm >> 32) & 0xFFFF, 32);
movk(ARMEmitter::Size::i64Bit, rd, (UImm >> 16) & 0xFFFF, 16);
movk(ARMEmitter::Size::i64Bit, rd, UImm & 0xFFFF);
return BranchEncodeSucceeded::Success;
}
[[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, ForwardLabel* Label) {
AddLocationToLabel(Label, ForwardLabel::Reference {.Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::InstType::LONG_ADDRESS_GEN});
// Emit a register index and two nops. These will be backpatched.
dc32(rd.Idx());
nop();
nop();
// Forward label doesn't know if it can encode until Bind.
return BranchEncodeSucceeded::Success;
}
[[nodiscard]] BranchEncodeSucceeded LongAddressGen(ARMEmitter::Register rd, BiDirectionalLabel* Label) {
if (Label->Backward.Location) {
return LongAddressGen(rd, &Label->Backward);
} else {
return LongAddressGen(rd, &Label->Forward);
}
}
// Add/subtract immediate
void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
constexpr uint32_t Op = 0b0001'0001'0 << 23;
DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
}
void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
constexpr uint32_t Op = 0b0011'0001'0 << 23;
DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
}
void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
adds(s, ARMEmitter::Reg::zr, rn, Imm, LSL12);
}
void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
constexpr uint32_t Op = 0b0101'0001'0 << 23;
DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
}
void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
constexpr uint32_t Op = 0b0111'0001'0 << 23;
DataProcessing_AddSub_Imm(Op, s, ARMEmitter::Reg::rsp, rn, Imm, LSL12);
}
void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
constexpr uint32_t Op = 0b0111'0001'0 << 23;
DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
}
// Min/max immediate
void smax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, int64_t Imm) {
LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__);
MinMaxImmediate(0b0000, s, rd, rn, Imm);
}
void umax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__);
MinMaxImmediate(0b0001, s, rd, rn, Imm);
}
void smin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, int64_t Imm) {
LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__);
MinMaxImmediate(0b0010, s, rd, rn, Imm);
}
void umin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__);
MinMaxImmediate(0b0011, s, rd, rn, Imm);
}
// Logical immediate
void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
uint32_t n, immr, imms;
const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
and_(s, rd, rn, n, immr, imms);
}
void bic(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
and_(s, rd, rn, ~Imm);
}
void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
uint32_t n, immr, imms;
const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
ands(s, rd, rn, n, immr, imms);
}
void bics(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
ands(s, rd, rn, ~Imm);
}
void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
uint32_t n, immr, imms;
const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
orr(s, rd, rn, n, immr, imms);
}
void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
uint32_t n, immr, imms;
const auto IsImm = IsImmLogical(Imm, RegSizeInBits(s), &n, &imms, &immr);
LOGMAN_THROW_A_FMT(IsImm, "Couldn't encode immediate to logical op");
eor(s, rd, rn, n, immr, imms);
}
void tst(ARMEmitter::Size s, Register rn, uint64_t imm) {
ands(s, Reg::zr, rn, imm);
}
// Move wide immediate
void movn(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
constexpr uint32_t Op = 0b001'0010'100 << 21;
DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
}
void mov(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm) {
movz(s, rd, Imm, 0);
}
void mov(ARMEmitter::XRegister rd, uint32_t Imm) {
movz(ARMEmitter::Size::i64Bit, rd.R(), Imm, 0);
}
void mov(ARMEmitter::WRegister rd, uint32_t Imm) {
movz(ARMEmitter::Size::i32Bit, rd.R(), Imm, 0);
}
void movz(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
constexpr uint32_t Op = 0b101'0010'100 << 21;
DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
}
void movk(ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
LOGMAN_THROW_A_FMT((Offset % 16) == 0, "Offset must be 16bit aligned");
constexpr uint32_t Op = 0b111'0010'100 << 21;
DataProcessing_MoveWide(Op, s, rd, Imm, Offset >> 4);
}
void movn(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movn(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
}
void movz(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movz(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
}
void movk(ARMEmitter::XRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movk(ARMEmitter::Size::i64Bit, rd.R(), Imm, Offset);
}
void movn(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movn(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
}
void movz(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movz(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
}
void movk(ARMEmitter::WRegister rd, uint32_t Imm, uint32_t Offset = 0) {
movk(ARMEmitter::Size::i32Bit, rd.R(), Imm, Offset);
}
// Bitfield
void sxtb(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
sbfm(s, rd, rn, 0, 7);
}
void sxth(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
sbfm(s, rd, rn, 0, 15);
}
void sxtw(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn) {
sbfm(ARMEmitter::Size::i64Bit, rd, rn.X(), 0, 31);
}
void sbfx(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
LOGMAN_THROW_A_FMT(width > 0, "sbfx needs width > 0");
LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to sbfx a region larger than the register");
sbfm(s, rd, rn, lsb, lsb + width - 1);
}
void sbfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
xbfiz_helper(true, s, rd, rn, lsb, width);
}
void asr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) {
const auto RegSize_m1 = RegSizeInBits(s) - 1;
shift &= RegSize_m1;
sbfm(s, rd, rn, shift, RegSize_m1);
}
void uxtb(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
ubfm(s, rd, rn, 0, 7);
}
void uxth(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
ubfm(s, rd, rn, 0, 15);
}
void uxtw(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
ubfm(s, rd, rn, 0, 31);
}
void ubfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b0101'0011'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
}
void ubfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
xbfiz_helper(false, s, rd, rn, lsb, width);
}
void lsl(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) {
const auto RegSize_m1 = RegSizeInBits(s) - 1;
shift &= RegSize_m1;
ubfm(s, rd, rn, (RegSizeInBits(s) - shift) & RegSize_m1, RegSize_m1 - shift);
}
void lsr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t shift) {
const auto RegSize_m1 = RegSizeInBits(s) - 1;
shift &= RegSize_m1;
ubfm(s, rd, rn, shift, RegSize_m1);
}
void ubfx(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
LOGMAN_THROW_A_FMT(width > 0, "ubfx needs width > 0");
LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to ubfx a region larger than the register");
ubfm(s, rd, rn, lsb, lsb + width - 1);
}
void bfi(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
const auto RegSize = RegSizeInBits(s);
LOGMAN_THROW_A_FMT(width > 0, "bfc/bfi needs width > 0");
LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfc/bfi a region larger than the register");
bfm(s, rd, rn, (RegSize - lsb) & (RegSize - 1), width - 1);
}
void bfc(ARMEmitter::Size s, Register rd, uint32_t lsb, uint32_t width) {
bfi(s, rd, Reg::zr, lsb, width);
}
void bfxil(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
const auto reg_size_bits = RegSizeInBits(s);
const auto lsb_p_width = lsb + width;
LOGMAN_THROW_A_FMT(width >= 1, "bfxil needs width >= 1");
LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "bfxil lsb + width ({}) must be <= {}. lsb={}, width={}", lsb_p_width, reg_size_bits,
lsb, width);
bfm(s, rd, rn, lsb, lsb_p_width - 1);
}
// Extract
void extr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, uint32_t Imm) {
constexpr uint32_t Op = 0b001'0011'100 << 21;
LOGMAN_THROW_A_FMT(Imm < RegSizeInBits(s), "Tried to extr a region larger than the register");
DataProcessing_Extract(Op, s, rd, rn, rm, Imm);
}
void ror(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm) {
Imm &= RegSizeInBits(s) - 1;
extr(s, rd, rn, rn, Imm);
}
// Data processing - 2 source
void udiv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0000'10U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void sdiv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0000'11U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void lslv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0010'00U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void lsrv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0010'01U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void asrv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0010'10U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void rorv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0010'11U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void crc32b(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0100'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void crc32h(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0100'01U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void crc32w(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0100'10U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void crc32cb(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0101'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void crc32ch(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0101'01U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void crc32cw(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0101'10U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
}
void smax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0110'00U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void umax(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0110'01U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void smin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0110'10U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void umin(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0110'11U << 10);
DataProcessing_2Source(Op, s, rd, rn, rm);
}
void subp(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0000'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void irg(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0001'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void gmi(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0001'01U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void pacga(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0011'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void crc32x(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0100'11U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void crc32cx(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b001'1010'110U << 21) | (0b0101'11U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
void subps(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = (0b011'1010'110U << 21) | (0b0000'00U << 10);
DataProcessing_2Source(Op, ARMEmitter::Size::i64Bit, rd, rn, rm);
}
// Data processing - 1 source
void rbit(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'00U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void rev16(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'01U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void rev(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'10U << 10);
DataProcessing_1Source(Op, ARMEmitter::Size::i32Bit, rd, rn);
}
void rev32(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'10U << 10);
DataProcessing_1Source(Op, ARMEmitter::Size::i64Bit, rd, rn);
}
void clz(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0001'00U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void cls(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0001'01U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void rev(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'11U << 10);
DataProcessing_1Source(Op, ARMEmitter::Size::i64Bit, rd, rn);
}
void rev(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0000'10U << 10) | (s == ARMEmitter::Size::i64Bit ? (1U << 10) : 0);
DataProcessing_1Source(Op, s, rd, rn);
}
void ctz(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0001'10U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void cnt(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0001'11U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
void abs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
constexpr uint32_t Op = (0b101'1010'110U << 21) | (0b0'0000U << 16) | (0b0010'00U << 10);
DataProcessing_1Source(Op, s, rd, rn);
}
// TODO: PAUTH
// Logical - shifted register
void mov(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn) {
orr(s, rd, ARMEmitter::Reg::zr, rn, ARMEmitter::ShiftType::LSL, 0);
}
void mov(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn) {
orr(ARMEmitter::Size::i64Bit, rd.R(), ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0);
}
void mov(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn) {
orr(ARMEmitter::Size::i32Bit, rd.R(), ARMEmitter::Reg::zr, rn.R(), ARMEmitter::ShiftType::LSL, 0);
}
void mvn(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL,
uint32_t amt = 0) {
orn(s, rd, ARMEmitter::Reg::zr, rn, Shift, amt);
}
void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b000'1010'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b110'1010'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void bic(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b000'1010'001U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void bics(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b110'1010'001U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b010'1010'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void tst(ARMEmitter::Size s, Register rn, Register rm, ShiftType shift = ShiftType::LSL, uint32_t amt = 0) {
ands(s, Reg::zr, rn, rm, shift, amt);
}
void orn(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b010'1010'001U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b100'1010'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void eon(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
constexpr uint32_t Op = 0b100'1010'001U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
// AddSub - shifted register
void add(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
add(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void adds(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
adds(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void cmn(ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
adds(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::zr, rn.R(), rm.R(), Shift, amt);
}
void sub(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
sub(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void neg(ARMEmitter::XRegister rd, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
sub(rd, ARMEmitter::XReg::zr, rm, Shift, amt);
}
void cmp(ARMEmitter::XRegister rn, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt);
}
void subs(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void negs(ARMEmitter::XRegister rd, ARMEmitter::XRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(rd, ARMEmitter::XReg::zr, rm, Shift, amt);
}
void add(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
add(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void adds(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
adds(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void cmn(ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
adds(ARMEmitter::Size::i32Bit, ARMEmitter::WReg::zr, rn.R(), rm.R(), Shift, amt);
}
void sub(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
sub(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void neg(ARMEmitter::WRegister rd, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
sub(rd, ARMEmitter::WReg::zr, rm, Shift, amt);
}
void cmp(ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::rsp, rn.R(), rm.R(), Shift, amt);
}
void subs(ARMEmitter::WRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
}
void negs(ARMEmitter::WRegister rd, ARMEmitter::WRegister rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
subs(rd, ARMEmitter::WReg::zr, rm, Shift, amt);
}
void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
LOGMAN_THROW_A_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
constexpr uint32_t Op = 0b000'1011'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
LOGMAN_THROW_A_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
constexpr uint32_t Op = 0b010'1011'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL,
uint32_t amt = 0) {
adds(s, ARMEmitter::Reg::zr, rn, rm, Shift, amt);
}
void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
LOGMAN_THROW_A_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
constexpr uint32_t Op = 0b100'1011'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void neg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL,
uint32_t amt = 0) {
sub(s, rd, ARMEmitter::Reg::zr, rm, Shift, amt);
}
void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL,
uint32_t amt = 0) {
subs(s, ARMEmitter::Reg::zr, rn, rm, Shift, amt);
}
void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
LOGMAN_THROW_A_FMT(Shift != ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
constexpr uint32_t Op = 0b110'1011'000U << 21;
DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
}
void negs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rm, ARMEmitter::ShiftType Shift = ARMEmitter::ShiftType::LSL,
uint32_t amt = 0) {
subs(s, rd, ARMEmitter::Reg::zr, rm, Shift, amt);
}
// AddSub - extended register
void add(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option,
uint32_t Shift = 0) {
LOGMAN_THROW_A_FMT(Shift <= 4, "Shift amount is too large");
constexpr uint32_t Op = 0b000'1011'001U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
}
void adds(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option,
uint32_t Shift = 0) {
constexpr uint32_t Op = 0b010'1011'001U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
}
void cmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
adds(s, ARMEmitter::Reg::zr, rn, rm, Option, Shift);
}
void sub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option,
uint32_t Shift = 0) {
constexpr uint32_t Op = 0b100'1011'001U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
}
void subs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option,
uint32_t Shift = 0) {
constexpr uint32_t Op = 0b110'1011'001U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
}
void cmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
constexpr uint32_t Op = 0b110'1011'001U << 21;
DataProcessing_Extended_Reg(Op, s, ARMEmitter::Reg::zr, rn, rm, Option, Shift);
}
// AddSub - with carry
void adc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = 0b0001'1010'000U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0);
}
void adcs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = 0b0011'1010'000U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0);
}
void sbc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = 0b0101'1010'000U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0);
}
void sbcs(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
constexpr uint32_t Op = 0b0111'1010'000U << 21;
DataProcessing_Extended_Reg(Op, s, rd, rn, rm, ARMEmitter::ExtendedType::UXTB, 0);
}
void ngc(ARMEmitter::Size s, Register rd, Register rm) {
sbc(s, rd, Reg::zr, rm);
}
void ngcs(ARMEmitter::Size s, Register rd, Register rm) {
sbcs(s, rd, Reg::zr, rm);
}
// Rotate right into flags
void rmif(XRegister rn, uint32_t shift, uint32_t mask) {
LOGMAN_THROW_A_FMT(shift <= 63, "Shift must be within 0-63. Shift: {}", shift);
LOGMAN_THROW_A_FMT(mask <= 15, "Mask must be within 0-15. Mask: {}", mask);
uint32_t Op = 0b1011'1010'0000'0000'0000'0100'0000'0000;
Op |= rn.Idx() << 5;
Op |= shift << 15;
Op |= mask;
dc32(Op);
}
// Evaluate into flags
void setf8(WRegister rn) {
constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101;
EvaluateIntoFlags(Op, 0, rn);
}
void setf16(WRegister rn) {
constexpr uint32_t Op = 0b0011'1010'0000'0000'0000'1000'0000'1101;
EvaluateIntoFlags(Op, 1, rn);
}
void cfinv() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0001'1111;
dc32(Op);
}
void axflag() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0101'1111;
dc32(Op);
}
void xaflag() {
constexpr uint32_t Op = 0b1101'0101'0000'0000'0100'0000'0011'1111;
dc32(Op);
}
// Conditional compare - register
void ccmn(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0011'1010'010 << 21;
ConditionalCompare(Op, 0, 0b00, 0, s, rn, rm, flags, Cond);
}
void ccmp(ARMEmitter::Size s, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0011'1010'010 << 21;
ConditionalCompare(Op, 1, 0b00, 0, s, rn, rm, flags, Cond);
}
// Conditional compare - immediate
void ccmn(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) {
LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large");
constexpr uint32_t Op = 0b0011'1010'010 << 21;
ConditionalCompare(Op, 0, 0b10, 0, s, rn, rm, flags, Cond);
}
void ccmp(ARMEmitter::Size s, ARMEmitter::Register rn, uint32_t rm, ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) {
LOGMAN_THROW_A_FMT((rm & ~0b1'1111) == 0, "Comparison imm too large");
constexpr uint32_t Op = 0b0011'1010'010 << 21;
ConditionalCompare(Op, 1, 0b10, 0, s, rn, rm, flags, Cond);
}
// Conditional select
void csel(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0001'1010'100 << 21;
ConditionalCompare(Op, 0, 0b00, s, rd, rn, rm, Cond);
}
void cset(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0001'1010'100 << 21;
ConditionalCompare(Op, 0, 0b01, s, rd, ARMEmitter::Reg::zr, ARMEmitter::Reg::zr,
static_cast<ARMEmitter::Condition>(FEXCore::ToUnderlying(Cond) ^ FEXCore::ToUnderlying(ARMEmitter::Condition::CC_NE)));
}
void csinc(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0001'1010'100 << 21;
ConditionalCompare(Op, 0, 0b01, s, rd, rn, rm, Cond);
}
void csinv(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0001'1010'100 << 21;
ConditionalCompare(Op, 1, 0b00, s, rd, rn, rm, Cond);
}
void csneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Condition Cond) {
constexpr uint32_t Op = 0b0001'1010'100 << 21;
ConditionalCompare(Op, 1, 0b01, s, rd, rn, rm, Cond);
}
void cneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Condition Cond) {
csneg(s, rd, rn, rn, InvertCondition(Cond));
}
void cinc(ARMEmitter::Size s, Register rd, Register rn, Condition cond) {
csinc(s, rd, rn, rn, InvertCondition(cond));
}
void cinv(ARMEmitter::Size s, Register rd, Register rn, Condition cond) {
csinv(s, rd, rn, rn, InvertCondition(cond));
}
void csetm(ARMEmitter::Size s, Register rd, Condition cond) {
csinv(s, rd, Reg::zr, Reg::zr, InvertCondition(cond));
}
// Data processing - 3 source
void madd(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Register ra) {
constexpr uint32_t Op = 0b001'1011'000U << 21;
DataProcessing_3Source(Op, 0, s, rd, rn, rm, ra);
}
void mul(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
madd(s, rd, rn, rm, XReg::zr);
}
void msub(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm, ARMEmitter::Register ra) {
constexpr uint32_t Op = 0b001'1011'000U << 21;
DataProcessing_3Source(Op, 1, s, rd, rn, rm, ra);
}
void mneg(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
msub(s, rd, rn, rm, XReg::zr);
}
void smaddl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) {
constexpr uint32_t Op = 0b001'1011'001U << 21;
DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
}
void smull(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
smaddl(rd, rn, rm, XReg::zr);
}
void smsubl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) {
constexpr uint32_t Op = 0b001'1011'001U << 21;
DataProcessing_3Source(Op, 1, ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
}
void smnegl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
smsubl(rd, rn, rm, XReg::zr);
}
void smulh(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = 0b001'1011'010U << 21;
DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ARMEmitter::Reg::zr);
}
void umaddl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) {
constexpr uint32_t Op = 0b001'1011'101U << 21;
DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
}
void umull(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
umaddl(rd, rn, rm, XReg::zr);
}
void umsubl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm, ARMEmitter::XRegister ra) {
constexpr uint32_t Op = 0b001'1011'101U << 21;
DataProcessing_3Source(Op, 1, ARMEmitter::Size::i64Bit, rd, rn, rm, ra);
}
void umnegl(ARMEmitter::XRegister rd, ARMEmitter::WRegister rn, ARMEmitter::WRegister rm) {
umsubl(rd, rn, rm, XReg::zr);
}
void umulh(ARMEmitter::XRegister rd, ARMEmitter::XRegister rn, ARMEmitter::XRegister rm) {
constexpr uint32_t Op = 0b001'1011'110U << 21;
DataProcessing_3Source(Op, 0, ARMEmitter::Size::i64Bit, rd, rn, rm, ARMEmitter::Reg::zr);
}
private:
void and_(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b001'0010'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
}
void ands(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b111'0010'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
}
void orr(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b011'0010'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
}
void eor(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b101'0010'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
}
void sbfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b0001'0011'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
}
void bfm(ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t immr, uint32_t imms) {
constexpr uint32_t Op = 0b0011'0011'00 << 22;
DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
}
// 4.1.64 - Data processing - Immediate
void DataProcessing_PCRel_Imm(uint32_t Op, ARMEmitter::Register rd, uint32_t Imm) {
// Ensure the immediate is masked.
Imm &= 0b1'1111'1111'1111'1111'1111U;
uint32_t Instr = Op;
Instr |= (Imm & 0b11) << 29;
Instr |= (Imm >> 2) << 5;
Instr |= Encode_rd(rd);
dc32(Instr);
}
void DataProcessing_AddSub_Imm(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t Imm, bool LSL12) {
bool TooLarge = (Imm & ~0b1111'1111'1111U) != 0;
if (TooLarge && !LSL12 && ((Imm >> 12) & ~0b1111'1111'1111U) == 0) {
// We can convert an immediate
TooLarge = false;
LSL12 = true;
Imm >>= 12;
}
LOGMAN_THROW_A_FMT(TooLarge == false, "Imm amount too large: 0x{:x}", Imm);
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= LSL12 << 22;
Instr |= Imm << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Min/max immediate
void MinMaxImmediate(uint32_t opc, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint64_t Imm) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = 0b1'0001'11U << 22;
Instr |= SF;
Instr |= opc << 18;
Instr |= (Imm & 0xFF) << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Move Wide
void DataProcessing_MoveWide(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= Imm << 5;
Instr |= Offset << 21;
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Logical immediate
void DataProcessing_Logical_Imm(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, uint32_t n,
uint32_t immr, uint32_t imms) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= n << 22;
Instr |= immr << 16;
Instr |= imms << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
void xbfiz_helper(bool is_signed, ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
const auto lsb_p_width = lsb + width;
const auto reg_size_bits = RegSizeInBits(s);
LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "lsb + width ({}) must be <= {}. lsb={}, width={}", lsb_p_width, reg_size_bits, lsb, width);
LOGMAN_THROW_A_FMT(width >= 1, "xbfiz width must be >= 1");
const auto immr = (reg_size_bits - lsb) & (reg_size_bits - 1);
const auto imms = width - 1;
if (is_signed) {
sbfm(s, rd, rn, immr, imms);
} else {
ubfm(s, rd, rn, immr, imms);
}
}
void DataProcessing_Extract(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm,
uint32_t Imm) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
// Current ARMv8 spec hardcodes SF == N for this class of instructions.
// Anythign else is undefined behaviour.
const uint32_t N = s == ARMEmitter::Size::i64Bit ? (1U << 22) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= N;
Instr |= Encode_rm(rm);
Instr |= Imm << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Data-processing - 2 source
void DataProcessing_2Source(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, ARMEmitter::Register rm) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= Encode_rm(rm);
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Data processing - 1 source
template<typename T>
void DataProcessing_1Source(uint32_t Op, ARMEmitter::Size s, T rd, T rn) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// AddSub - shifted register
void DataProcessing_Shifted_Reg(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn,
ARMEmitter::Register rm, ARMEmitter::ShiftType Shift, uint32_t amt) {
LOGMAN_THROW_A_FMT((amt & ~0b11'1111U) == 0, "Shift amount too large");
if (s == ARMEmitter::Size::i32Bit) {
LOGMAN_THROW_A_FMT(amt < 32, "Shift amount for 32-bit must be below 32");
}
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= FEXCore::ToUnderlying(Shift) << 22;
Instr |= Encode_rm(rm);
Instr |= static_cast<uint32_t>(amt) << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// AddSub - extended register
void DataProcessing_Extended_Reg(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn,
ARMEmitter::Register rm, ARMEmitter::ExtendedType Option, uint32_t Shift) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= Encode_rm(rm);
Instr |= FEXCore::ToUnderlying(Option) << 13;
Instr |= static_cast<uint32_t>(Shift) << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Conditional compare - register
template<typename T>
void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, uint32_t o3, ARMEmitter::Size s, ARMEmitter::Register rn, T rm,
ARMEmitter::StatusFlags flags, ARMEmitter::Condition Cond) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= o1 << 30;
Instr |= Encode_rm(rm);
Instr |= FEXCore::ToUnderlying(Cond) << 12;
Instr |= o2 << 10;
Instr |= Encode_rn(rn);
Instr |= o3 << 4;
Instr |= FEXCore::ToUnderlying(flags);
dc32(Instr);
}
template<typename T>
void ConditionalCompare(uint32_t Op, uint32_t o1, uint32_t o2, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn, T rm,
ARMEmitter::Condition Cond) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= o1 << 30;
Instr |= Encode_rm(rm);
Instr |= FEXCore::ToUnderlying(Cond) << 12;
Instr |= o2 << 10;
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
// Data-processing - 3 source
void DataProcessing_3Source(uint32_t Op, uint32_t Op0, ARMEmitter::Size s, ARMEmitter::Register rd, ARMEmitter::Register rn,
ARMEmitter::Register rm, ARMEmitter::Register ra) {
const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
uint32_t Instr = Op;
Instr |= SF;
Instr |= Encode_rm(rm);
Instr |= Op0 << 15;
Instr |= Encode_ra(ra);
Instr |= Encode_rn(rn);
Instr |= Encode_rd(rd);
dc32(Instr);
}
void EvaluateIntoFlags(uint32_t op, uint32_t size, WRegister rn) {
uint32_t Instr = op;
Instr |= size << 14;
Instr |= rn.Idx() << 5;
dc32(Instr);
}
#ifndef INCLUDED_BY_EMITTER
}; // struct LoadstoreEmitterOps
} // namespace ARMEmitter
#endif
================================================
FILE: CodeEmitter/CodeEmitter/ASIMDOps.inl
================================================
// SPDX-License-Identifier: MIT
/* ASIMD instruction emitters.
*
* This contains emitters for vector operations explicitly.
* Most instructions have a `SubRegSize` as their first argument to select element size while operating.
* Additionally most emitters accept templated vector register arguments of both `QRegister` and `DRegister` types.
* Based on the combination of those two arguments, it will emit an instruction operating on a 64-bit or 128-bit wide register
* with the selected element size.
*
* Some vector operations are unsized and only operate at the one width. In these cases the instruction only
* operates at one size, the width depends on the instruction.
* The arguments for these instructions are usually `VRegister` but might be one of the other sized types as well.
*
* Only two instructions support the `i128Bit` ElementSize.
*/
#pragma once
#ifndef INCLUDED_BY_EMITTER
#include <CodeEmitter/Emitter.h>
namespace ARMEmitter {
struct EmitterOps : Emitter {
#endif
public:
// Data Processing -- Scalar Floating-Point and Advanced SIMD
// Cryptographic AES
void aese(VRegister rd, VRegister rn) {
CryptoAES(0b00100, rd, rn);
}
void aesd(VRegister rd, VRegister rn) {
CryptoAES(0b00101, rd, rn);
}
void aesmc(VRegister rd, VRegister rn) {
CryptoAES(0b00110, rd, rn);
}
void aesimc(VRegister rd, VRegister rn) {
CryptoAES(0b00111, rd, rn);
}
// Cryptographic three-register SHA
void sha1c(VRegister rd, SRegister rn, VRegister rm) {
Crypto3RegSHA(0b000, rd, rn.V(), rm);
}
void sha1p(VRegister rd, SRegister rn, VRegister rm) {
Crypto3RegSHA(0b001, rd, rn.V(), rm);
}
void sha1m(VRegister rd, SRegister rn, VRegister rm) {
Crypto3RegSHA(0b010, rd, rn.V(), rm);
}
void sha1su0(VRegister rd, VRegister rn, VRegister rm) {
Crypto3RegSHA(0b011, rd, rn, rm);
}
void sha256h(VRegister rd, VRegister rn, VRegister rm) {
Crypto3RegSHA(0b100, rd, rn, rm);
}
void sha256h2(VRegister rd, VRegister rn, VRegister rm) {
Crypto3RegSHA(0b101, rd, rn, rm);
}
void sha256su1(VRegister rd, VRegister rn, VRegister rm) {
Crypto3RegSHA(0b110, rd, rn, rm);
}
// Cryptographic two-register SHA
void sha1h(SRegister rd, SRegister rn) {
Crypto2RegSHA(0b00000, rd.V(), rn.V());
}
void sha1su1(VRegister rd, VRegister rn) {
Crypto2RegSHA(0b00001, rd, rn);
}
void sha256su0(VRegister rd, VRegister rn) {
Crypto2RegSHA(0b00010, rd, rn);
}
// Advanced SIMD table lookup
void tbl(QRegister rd, QRegister rn, QRegister rm) {
ASIMDTable(1, 0b00, 0b00, 0b0, rd.V(), rn.V(), rm.V());
}
void tbl(DRegister rd, QRegister rn, DRegister rm) {
ASIMDTable(0, 0b00, 0b00, 0b0, rd.V(), rn.V(), rm.V());
}
void tbx(QRegister rd, QRegister rn, QRegister rm) {
ASIMDTable(1, 0b00, 0b00, 0b1, rd.V(), rn.V(), rm.V());
}
void tbx(DRegister rd, QRegister rn, DRegister rm) {
ASIMDTable(0, 0b00, 0b00, 0b1, rd.V(), rn.V(), rm.V());
}
void tbl(QRegister rd, QRegister rn, QRegister rn2, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2), "rn and rn2 must be sequential");
ASIMDTable(1, 0b00, 0b01, 0b0, rd.V(), rn.V(), rm.V());
}
void tbl(DRegister rd, QRegister rn, QRegister rn2, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2), "rn and rn2 must be sequential");
ASIMDTable(0, 0b00, 0b01, 0b0, rd.V(), rn.V(), rm.V());
}
void tbx(QRegister rd, QRegister rn, QRegister rn2, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2), "rn and rn2 must be sequential");
ASIMDTable(1, 0b00, 0b01, 0b1, rd.V(), rn.V(), rm.V());
}
void tbx(DRegister rd, QRegister rn, QRegister rn2, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2), "rn and rn2 must be sequential");
ASIMDTable(0, 0b00, 0b01, 0b1, rd.V(), rn.V(), rm.V());
}
void tbl(QRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3), "rn, rn2, and rn3 must be sequential");
ASIMDTable(1, 0b00, 0b10, 0b0, rd.V(), rn.V(), rm.V());
}
void tbl(DRegister rd, QRegister rn, QRegister rn2, QRegister rn3, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3), "rn, rn2, and rn3 must be sequential");
ASIMDTable(0, 0b00, 0b10, 0b0, rd.V(), rn.V(), rm.V());
}
void tbx(QRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3), "rn, rn2, and rn3 must be sequential");
ASIMDTable(1, 0b00, 0b10, 0b1, rd.V(), rn.V(), rm.V());
}
void tbx(DRegister rd, QRegister rn, QRegister rn2, QRegister rn3, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3), "rn, rn2, and rn3 must be sequential");
ASIMDTable(0, 0b00, 0b10, 0b1, rd.V(), rn.V(), rm.V());
}
void tbl(QRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rn4, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3, rn4), "rn, rn2, rn3, and rn4 must be sequential");
ASIMDTable(1, 0b00, 0b11, 0b0, rd.V(), rn.V(), rm.V());
}
void tbl(DRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rn4, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3, rn4), "rn, rn2, rn3, and rn4 must be sequential");
ASIMDTable(0, 0b00, 0b11, 0b0, rd.V(), rn.V(), rm.V());
}
void tbx(QRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rn4, QRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3, rn4), "rn, rn2, rn3, and rn4 must be sequential");
ASIMDTable(1, 0b00, 0b11, 0b1, rd.V(), rn.V(), rm.V());
}
void tbx(DRegister rd, QRegister rn, QRegister rn2, QRegister rn3, QRegister rn4, DRegister rm) {
LOGMAN_THROW_A_FMT(AreVectorsSequential(rn, rn2, rn3, rn4), "rn, rn2, rn3, and rn4 must be sequential");
ASIMDTable(0, 0b00, 0b11, 0b1, rd.V(), rn.V(), rm.V());
}
// Advanced SIMD permute
void uzp1(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b001, rd.V(), rn.V(), rm.V());
}
void uzp1(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b001, rd.V(), rn.V(), rm.V());
}
void trn1(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b010, rd.V(), rn.V(), rm.V());
}
void trn1(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b010, rd.V(), rn.V(), rm.V());
}
void zip1(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b011, rd.V(), rn.V(), rm.V());
}
void zip1(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b011, rd.V(), rn.V(), rm.V());
}
void uzp2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b101, rd.V(), rn.V(), rm.V());
}
void uzp2(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b101, rd.V(), rn.V(), rm.V());
}
void trn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b110, rd.V(), rn.V(), rm.V());
}
void trn2(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b110, rd.V(), rn.V(), rm.V());
}
void zip2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
ASIMDPermute(1, size, 0b111, rd.V(), rn.V(), rm.V());
}
void zip2(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid 64-bit size on 64-bit permute");
ASIMDPermute(0, size, 0b111, rd.V(), rn.V(), rm.V());
}
// Advanced SIMD extract
void ext(QRegister rd, QRegister rn, QRegister rm, uint32_t Index) {
LOGMAN_THROW_A_FMT(Index < 16, "Index can't be more than 15");
ASIMDExtract(1, 0b00, Index, rd.V(), rn.V(), rm.V());
}
void ext(DRegister rd, DRegister rn, DRegister rm, uint32_t Index) {
LOGMAN_THROW_A_FMT(Index < 8, "Index can't be more than 7");
ASIMDExtract(0, 0b00, Index, rd.V(), rn.V(), rm.V());
}
// Advanced SIMD copy
template<IsQOrDRegister T>
void dup(SubRegSize size, T rd, T rn, uint32_t Index) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit dup");
}
constexpr uint32_t Q = std::is_same_v<QRegister, T> ? 1 : 0;
const uint32_t SizeImm = FEXCore::ToUnderlying(size);
const uint32_t IndexShift = SizeImm + 1;
const uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] const uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
ASIMDScalarCopy(Q, 0, imm5, 0b0000, rd.V(), rn.V());
}
template<IsQOrDRegister T>
void dup(SubRegSize size, T rd, Register rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit dup");
}
constexpr uint32_t Q = std::is_same_v<QRegister, T> ? 1 : 0;
// Upper bits of imm5 are ignored for GPR dup
const uint32_t imm5 = 1U << FEXCore::ToUnderlying(size);
ASIMDScalarCopy(Q, 0, imm5, 0b0001, rd, ToVReg(rn));
}
template<SubRegSize size>
requires (size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit)
void smov(XRegister rd, VRegister rn, uint32_t Index) {
static_assert(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit, "Unsupported smov size");
constexpr uint32_t SizeImm = FEXCore::ToUnderlying(size);
constexpr uint32_t IndexShift = SizeImm + 1;
constexpr uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] constexpr uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
ASIMDScalarCopy(1, 0, imm5, 0b0101, ToVReg(rd), rn);
}
template<SubRegSize size>
requires (size == SubRegSize::i8Bit || size == SubRegSize::i16Bit)
void smov(WRegister rd, VRegister rn, uint32_t Index) {
static_assert(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit, "Unsupported smov size");
constexpr uint32_t SizeImm = FEXCore::ToUnderlying(size);
constexpr uint32_t IndexShift = SizeImm + 1;
constexpr uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] constexpr uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
ASIMDScalarCopy(0, 0, imm5, 0b0101, ToVReg(rd), rn);
}
template<SubRegSize size>
void umov(Register rd, VRegister rn, uint32_t Index) {
static_assert(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
"Unsupported umov size");
constexpr uint32_t Q = size == SubRegSize::i64Bit ? 1 : 0;
constexpr uint32_t SizeImm = FEXCore::ToUnderlying(size);
constexpr uint32_t IndexShift = SizeImm + 1;
constexpr uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] constexpr uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
ASIMDScalarCopy(Q, 0, imm5, 0b0111, ToVReg(rd), rn);
}
void ins(SubRegSize size, VRegister rd, uint32_t Index, Register rn) {
const uint32_t SizeImm = FEXCore::ToUnderlying(size);
const uint32_t IndexShift = SizeImm + 1;
const uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] const uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
ASIMDScalarCopy(1, 0, imm5, 0b0011, rd, ToVReg(rn));
}
void ins(SubRegSize size, VRegister rd, uint32_t Index, VRegister rn, uint32_t Index2) {
const uint32_t SizeImm = FEXCore::ToUnderlying(size);
const uint32_t IndexShift = SizeImm + 1;
const uint32_t ElementSize = 1U << SizeImm;
[[maybe_unused]] const uint32_t MaxIndex = 128U / (ElementSize * 8);
LOGMAN_THROW_A_FMT(Index < MaxIndex, "Index too large. Index={}, Max Index: {}", Index, MaxIndex);
LOGMAN_THROW_A_FMT(Index2 < MaxIndex, "Index2 too large. Index2={}, Max Index: {}", Index2, MaxIndex);
const uint32_t imm5 = (Index << IndexShift) | ElementSize;
const uint32_t imm4 = Index2 << SizeImm;
ASIMDScalarCopy(1, 0b10, imm5, imm4, rd, rn);
}
// Advanced SIMD three-register extension
template<IsQOrDRegister T>
void sdot(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMDThreeRegisterExt(0, 0b0010, size, rm, rn, rd);
}
template<IsQOrDRegister T>
void usdot(T rd, T rn, T rm) {
ASIMDThreeRegisterExt(0, 0b0011, ARMEmitter::SubRegSize::i32Bit, rm, rn, rd);
}
template<IsQOrDRegister T>
void sqrdmlah(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMDThreeRegisterExt(1, 0b0000, size, rm, rn, rd);
}
template<IsQOrDRegister T>
void sqrdmlsh(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMDThreeRegisterExt(1, 0b0001, size, rm, rn, rd);
}
template<IsQOrDRegister T>
void udot(ARMEmitter::SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMDThreeRegisterExt(1, 0b0010, size, rm, rn, rd);
}
template<IsQOrDRegister T>
void fcmla(ARMEmitter::SubRegSize size, T rd, T rn, T rm, ARMEmitter::Rotation Rot) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported");
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMDThreeRegisterExt(1, 0b1000 | FEXCore::ToUnderlying(Rot), size, rm, rn, rd);
}
template<IsQOrDRegister T>
void fcadd(ARMEmitter::SubRegSize size, T rd, T rn, T rm, ARMEmitter::Rotation Rot) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i8Bit, "8-bit subregsize not supported");
if constexpr (std::is_same_v<ARMEmitter::DRegister, T>) {
LOGMAN_THROW_A_FMT(size != ARMEmitter::SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(Rot == ARMEmitter::Rotation::ROTATE_90 || Rot == ARMEmitter::Rotation::ROTATE_270, "Invalid rotation");
const uint32_t ConvertedRotation = Rot == ARMEmitter::Rotation::ROTATE_90 ? 0b00 : 0b10;
ASIMDThreeRegisterExt(1, 0b1100 | ConvertedRotation, size, rm, rn, rd);
}
template<IsQOrDRegister T>
void bfdot(T rd, T rn, T rm) {
ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i16Bit, rm, rn, rd);
}
void bfmlalb(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i64Bit, rm.D(), rn.D(), rd.D());
}
void bfmlalt(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(1, 0b1111, ARMEmitter::SubRegSize::i64Bit, rm.Q(), rn.Q(), rd.Q());
}
void smmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(0, 0b0100, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q());
}
void usmmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(0, 0b0101, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q());
}
void bfmmla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(1, 0b1101, ARMEmitter::SubRegSize::i16Bit, rm.Q(), rn.Q(), rd.Q());
}
void ummla(ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, ARMEmitter::VRegister rm) {
ASIMDThreeRegisterExt(1, 0b0100, ARMEmitter::SubRegSize::i32Bit, rm.Q(), rn.Q(), rd.Q());
}
// Advanced SIMD two-register miscellaneous
template<IsQOrDRegister T>
void rev64(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD2RegMisc(0, size, 0b00000, rd, rn);
}
template<IsQOrDRegister T>
void rev16(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit, "Only 8-bit subregsize supported");
ASIMD2RegMisc(0, size, 0b00001, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
template<IsQOrDRegister T>
void saddlp(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(0, ConvertedSize, 0b00010, rd, rn);
}
template<IsQOrDRegister T>
void suqadd(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b00011, rd, rn);
}
template<IsQOrDRegister T>
void cls(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD2RegMisc(0, size, 0b00100, rd, rn);
}
template<IsQOrDRegister T>
void cnt(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit, "Only 8-bit subregsize supported");
ASIMD2RegMisc(0, size, 0b00101, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
template<IsQOrDRegister T>
void sadalp(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(0, ConvertedSize, 0b00110, rd, rn);
}
template<IsQOrDRegister T>
void sqabs(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b00111, rd, rn);
}
// Comparison against zero
template<IsQOrDRegister T>
void cmgt(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b01000, rd, rn);
}
// Comparison against zero
template<IsQOrDRegister T>
void cmeq(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b01001, rd, rn);
}
// Comparison against zero
template<IsQOrDRegister T>
void cmlt(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b01010, rd, rn);
}
template<IsQOrDRegister T>
void abs(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(0, size, 0b01011, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
void xtn(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(0, size, 0b10010, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void xtn2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(0, size, 0b10010, rd.Q(), rn.Q());
}
///< size is the destination size.
///< source size is the next size up.
void sqxtn(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(0, size, 0b10100, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void sqxtn2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(0, size, 0b10100, rd.Q(), rn.Q());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtn(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i32Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b10110, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtn2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i16Bit, "Only 16-bit & 32-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i32Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b10110, rd.Q(), rn.Q());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtl(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b10111, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtl2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b10111, rd.Q(), rn.Q());
}
template<IsQOrDRegister T>
void frintn(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11000, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11000, rd, rn);
}
}
template<IsQOrDRegister T>
void frintm(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11001, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11001, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtns(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11010, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11010, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtms(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11011, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11011, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtas(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11100, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11100, rd, rn);
}
}
template<IsQOrDRegister T>
void scvtf(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 0, 0b11101, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11101, rd, rn);
}
}
template<IsQOrDRegister T>
void frint32z(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11110, rd, rn);
}
template<IsQOrDRegister T>
void frint64z(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(0, ConvertedSize, 0b11111, rd, rn);
}
template<IsQOrDRegister T>
void fcmgt(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b01100, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b01100, rd, rn);
}
}
template<IsQOrDRegister T>
void fcmeq(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b01101, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b01101, rd, rn);
}
}
template<IsQOrDRegister T>
void fcmlt(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b01110, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b01110, rd, rn);
}
}
template<IsQOrDRegister T>
void fabs(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b01111, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b01111, rd, rn);
}
}
template<IsQOrDRegister T>
void frintp(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b11000, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b11000, rd, rn);
}
}
template<IsQOrDRegister T>
void frintz(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b11001, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b11001, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtps(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b11010, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b11010, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtzs(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b11011, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b11011, rd, rn);
}
}
template<IsQOrDRegister T>
void urecpe(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit, "Only 32-bit subregsize supported");
ASIMD2RegMisc(0, size, 0b11100, rd, rn);
}
template<IsQOrDRegister T>
void frecpe(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(0, 1, 0b11101, rn, rd);
} else {
ASIMD2RegMisc(0, size, 0b11101, rd, rn);
}
}
template<IsQOrDRegister T>
void rev32(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit, "Only 8-bit & 16-bit subregsize supported");
ASIMD2RegMisc(1, size, 0b00000, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
template<IsQOrDRegister T>
void uaddlp(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(1, ConvertedSize, 0b00010, rd, rn);
}
template<IsQOrDRegister T>
void usqadd(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(1, size, 0b00011, rd, rn);
}
template<IsQOrDRegister T>
void clz(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD2RegMisc(1, size, 0b00100, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
template<IsQOrDRegister T>
void uadalp(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(1, ConvertedSize, 0b00110, rd, rn);
}
template<IsQOrDRegister T>
void sqneg(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(1, size, 0b00111, rd, rn);
}
// Comparison against zero
template<IsQOrDRegister T>
void cmge(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(1, size, 0b01000, rd, rn);
}
// Comparison against zero
template<IsQOrDRegister T>
void cmle(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(1, size, 0b01001, rd, rn);
}
template<IsQOrDRegister T>
void neg(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
ASIMD2RegMisc(1, size, 0b01011, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
void sqxtun(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(1, size, 0b10010, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void sqxtun2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit destination subregsize not supported");
ASIMD2RegMisc(1, size, 0b10010, rd.Q(), rn.Q());
}
///< size is the destination size.
///< source size is the next size up.
void shll(SubRegSize size, DRegister rd, DRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(1, ConvertedSize, 0b10011, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
void shll2(SubRegSize size, QRegister rd, QRegister rn) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD2RegMisc(1, ConvertedSize, 0b10011, rd, rn);
}
///< size is the destination size.
///< source size is the next size up.
void uqxtn(SubRegSize size, VRegister rd, VRegister rn) {
ASIMD2RegMisc(1, size, 0b10100, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void uqxtn2(SubRegSize size, VRegister rd, VRegister rn) {
ASIMD2RegMisc(1, size, 0b10100, rd.Q(), rn.Q());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtxn(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit, "Only 32-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i32Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b10110, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void fcvtxn2(SubRegSize size, VRegister rd, VRegister rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit, "Only 32-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i32Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b10110, rd.Q(), rn.Q());
}
template<IsQOrDRegister T>
void frinta(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11000, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11000, rd, rn);
}
}
template<IsQOrDRegister T>
void frintx(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11001, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11001, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtnu(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11010, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11010, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtmu(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11011, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11011, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtau(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11100, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11100, rd, rn);
}
}
template<IsQOrDRegister T>
void ucvtf(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 0, 0b11101, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11101, rd, rn);
}
}
template<IsQOrDRegister T>
void frint32x(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11110, rd, rn);
}
template<IsQOrDRegister T>
void frint64x(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i64Bit || size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD2RegMisc(1, ConvertedSize, 0b11111, rd, rn);
}
template<IsQOrDRegister T>
void not_(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit, "Only 8-bit subregsize supported");
ASIMD2RegMisc(1, SubRegSize::i8Bit, 0b00101, rd, rn);
}
template<IsQOrDRegister T>
void mvn(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit, "Only 8-bit subregsize supported");
ASIMD2RegMisc(1, SubRegSize::i8Bit, 0b00101, rd, rn);
}
template<IsQOrDRegister T>
void rbit(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit, "Only 8-bit subregsize supported");
ASIMD2RegMisc(1, SubRegSize::i16Bit, 0b00101, rd, rn);
}
template<IsQOrDRegister T>
void fcmge(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b01100, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b01100, rd, rn);
}
}
template<IsQOrDRegister T>
void fcmle(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b01101, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b01101, rd, rn);
}
}
template<IsQOrDRegister T>
void fneg(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b01111, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b01111, rd, rn);
}
}
template<IsQOrDRegister T>
void frinti(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b11001, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b11001, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtpu(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b11010, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b11010, rd, rn);
}
}
template<IsQOrDRegister T>
void fcvtzu(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b11011, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b11011, rd, rn);
}
}
template<IsQOrDRegister T>
void ursqrte(SubRegSize size, T rd, T rn) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i32Bit, "Only 32-bit & 64-bit subregsize supported");
ASIMD2RegMisc(1, size, 0b11100, rd, rn);
}
template<IsQOrDRegister T>
void frsqrte(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b11101, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b11101, rd, rn);
}
}
template<IsQOrDRegister T>
void fsqrt(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDTwoRegMiscFP16(1, 1, 0b11111, rn, rd);
} else {
ASIMD2RegMisc(1, size, 0b11111, rd, rn);
}
}
// Advanced SIMD across lanes
///< size is the destination size.
///< source size is the next size up.
template<IsQOrDRegister T>
void saddlv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMDAcrossLanes<T>(0, ConvertedSize, 0b00011, rd, rn);
}
template<IsQOrDRegister T>
void smaxv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit && size != SubRegSize::i64Bit, "32/64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported");
ASIMDAcrossLanes<T>(0, size, 0b01010, rd, rn);
}
template<IsQOrDRegister T>
void sminv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit && size != SubRegSize::i64Bit, "32/64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported");
ASIMDAcrossLanes<T>(0, size, 0b11010, rd, rn);
}
template<IsQOrDRegister T>
void addv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit && size != SubRegSize::i64Bit, "32/64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported");
ASIMDAcrossLanes<T>(0, size, 0b11011, rd, rn);
}
template<IsQOrDRegister T>
void uaddlv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Destination 8-bit subregsize unsupported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMDAcrossLanes<T>(1, ConvertedSize, 0b00011, rd, rn);
}
template<IsQOrDRegister T>
void umaxv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit && size != SubRegSize::i64Bit, "32/64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported");
ASIMDAcrossLanes<T>(1, size, 0b01010, rd, rn);
}
template<IsQOrDRegister T>
void uminv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit && size != SubRegSize::i64Bit, "32/64-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Destination 64-bit subregsize unsupported");
ASIMDAcrossLanes<T>(1, size, 0b11010, rd, rn);
}
template<IsQOrDRegister T>
void fmaxnmv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit, "32-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
const auto U = size == SubRegSize::i16Bit ? 0 : 1;
ASIMDAcrossLanes<T>(U, ConvertedSize, 0b01100, rd, rn);
}
template<IsQOrDRegister T>
void fmaxv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit, "32-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
const auto U = size == ARMEmitter::SubRegSize::i16Bit ? 0 : 1;
ASIMDAcrossLanes<T>(U, ConvertedSize, 0b01111, rd, rn);
}
template<IsQOrDRegister T>
void fminnmv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit, "32-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i64Bit : SubRegSize::i32Bit;
const auto U = size == SubRegSize::i16Bit ? 0 : 1;
ASIMDAcrossLanes<T>(U, ConvertedSize, 0b01100, rd, rn);
}
template<IsQOrDRegister T>
void fminv(SubRegSize size, T rd, T rn) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i32Bit, "32-bit subregsize not supported");
}
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i64Bit, "Destination 8/64-bit subregsize unsupported");
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i64Bit : SubRegSize::i32Bit;
const auto U = size == SubRegSize::i16Bit ? 0 : 1;
ASIMDAcrossLanes<T>(U, ConvertedSize, 0b01111, rd, rn);
}
// Advanced SIMD three different
// TODO: Double check narrowing op size limits.
// TODO: Don't enforce DRegister/QRegister for Q check
///< Size is dest size
void saddl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void saddl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void saddw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void saddw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void ssubl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void ssubl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void ssubw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0011, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void ssubw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0011, ConvertedSize, rd, rn, rm);
}
void addhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(0, 0b0100, size, rd, rn, rm);
}
void addhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(0, 0b0100, size, rd, rn, rm);
}
///< Size is dest size
void sabal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0101, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sabal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0101, ConvertedSize, rd, rn, rm);
}
void subhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(0, 0b0110, size, rd, rn, rm);
}
void subhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(0, 0b0110, size, rd, rn, rm);
}
///< Size is dest size
void sabdl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0111, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sabdl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b0111, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1011, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1011, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1100, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void smull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1100, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1101, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void sqdmull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1101, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void pmull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i16Bit || size == SubRegSize::i128Bit, "Only 16-bit and 128-bit destination supported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1110, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void pmull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size == SubRegSize::i16Bit || size == SubRegSize::i128Bit, "Only 16-bit and 128-bit destination supported");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(0, 0b1110, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uaddl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uaddl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uaddw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uaddw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0001, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void usubl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void usubl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void usubw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0011, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void usubw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0011, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void raddhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(1, 0b0100, size, rd, rn, rm);
}
///< Size is dest size
void raddhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(1, 0b0100, size, rd, rn, rm);
}
///< Size is dest size
void uabal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0101, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uabal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0101, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void rsubhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(1, 0b0110, size, rd, rn, rm);
}
///< Size is dest size
void rsubhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
ASIMD3Different(1, 0b0110, size, rd, rn, rm);
}
///< Size is dest size
void uabdl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0111, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void uabdl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b0111, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1000, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1010, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1100, ConvertedSize, rd, rn, rm);
}
///< Size is dest size
void umull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
const auto ConvertedSize = SubRegSize {FEXCore::ToUnderlying(size) - 1};
ASIMD3Different(1, 0b1100, ConvertedSize, rd, rn, rm);
}
// Advanced SIMD three same
template<IsQOrDRegister T>
void shadd(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b00000, rd, rn, rm);
}
template<IsQOrDRegister T>
void sqadd(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit sqadd");
}
ASIMD3Same<T>(0, size, 0b00001, rd, rn, rm);
}
template<IsQOrDRegister T>
void srhadd(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b00010, rd, rn, rm);
}
template<IsQOrDRegister T>
void shsub(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b00100, rd, rn, rm);
}
template<IsQOrDRegister T>
void sqsub(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit sqsub");
}
ASIMD3Same<T>(0, size, 0b00101, rd, rn, rm);
}
template<IsQOrDRegister T>
void cmgt(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit cmgt");
}
ASIMD3Same<T>(0, size, 0b00110, rd, rn, rm);
}
template<IsQOrDRegister T>
void cmge(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit cmge");
}
ASIMD3Same<T>(0, size, 0b00111, rd, rn, rm);
}
template<IsQOrDRegister T>
void sshl(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit sshl");
}
ASIMD3Same<T>(0, size, 0b01000, rd, rn, rm);
}
template<IsQOrDRegister T>
void sqshl(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit sqshl");
}
ASIMD3Same<T>(0, size, 0b01001, rd, rn, rm);
}
template<IsQOrDRegister T>
void srshl(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit srshl");
}
ASIMD3Same<T>(0, size, 0b01010, rd, rn, rm);
}
template<IsQOrDRegister T>
void sqrshl(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit sqrshl");
}
ASIMD3Same<T>(0, size, 0b01011, rd, rn, rm);
}
template<IsQOrDRegister T>
void smax(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b01100, rd, rn, rm);
}
template<IsQOrDRegister T>
void smin(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b01101, rd, rn, rm);
}
template<IsQOrDRegister T>
void sabd(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b01110, rd, rn, rm);
}
template<IsQOrDRegister T>
void saba(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b01111, rd, rn, rm);
}
template<IsQOrDRegister T>
void add(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit add");
}
ASIMD3Same<T>(0, size, 0b10000, rd, rn, rm);
}
template<IsQOrDRegister T>
void cmtst(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit cmtst");
}
ASIMD3Same<T>(0, size, 0b10001, rd, rn, rm);
}
template<IsQOrDRegister T>
void mla(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b10010, rd, rn, rm);
}
template<IsQOrDRegister T>
void mul(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b10011, rd, rn, rm);
}
template<IsQOrDRegister T>
void smaxp(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b10100, rd, rn, rm);
}
template<IsQOrDRegister T>
void sminp(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b10101, rd, rn, rm);
}
template<IsQOrDRegister T>
void sqdmulh(SubRegSize size, T rd, T rn, T rm) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "64-bit subregsize not supported");
ASIMD3Same<T>(0, size, 0b10110, rd, rn, rm);
}
template<IsQOrDRegister T>
void addp(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
ASIMD3Same<T>(0, size, 0b10111, rd, rn, rm);
}
template<IsQOrDRegister T>
void fmaxnm(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b000, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11000, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fmla(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b001, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11001, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fadd(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b010, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11010, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fmulx(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b011, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11011, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fcmeq(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b100, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11100, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fmax(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b110, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11110, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void frecps(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 0, 0b111, rm, rn, rd);
} else {
const auto ConvertedSize = size == SubRegSize::i64Bit ? SubRegSize::i16Bit : SubRegSize::i8Bit;
ASIMD3Same<T>(0, ConvertedSize, 0b11111, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void and_(T rd, T rn, T rm) {
ASIMD3Same<T>(0, SubRegSize::i8Bit, 0b00011, rd, rn, rm);
}
template<IsQOrDRegister T>
void fmlal(T rd, T rn, T rm) {
ASIMD3Same<T>(0, SubRegSize::i8Bit, 0b11101, rd, rn, rm);
}
template<IsQOrDRegister T>
void fmlal2(T rd, T rn, T rm) {
ASIMD3Same<T>(1, SubRegSize::i8Bit, 0b11001, rd, rn, rm);
}
template<IsQOrDRegister T>
void bic(T rd, T rn, T rm) {
ASIMD3Same<T>(0, SubRegSize::i16Bit, 0b00011, rd, rn, rm);
}
template<IsQOrDRegister T>
void fminnm(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 1, 0b000, rm, rn, rd);
} else {
ASIMD3Same<T>(0, size, 0b11000, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fmls(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit subregsize supported");
if (size == SubRegSize::i16Bit) {
ASIMDThreeSameFP16(0, 1, 0b001, rm, rn, rd);
} else {
ASIMD3Same<T>(0, size, 0b11001, rd, rn, rm);
}
}
template<IsQOrDRegister T>
void fsub(SubRegSize size, T rd, T rn, T rm) {
if constexpr (std::is_same_v<DRegister, T>) {
LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit, "Invalid element size with 64-bit {}", __func__);
}
LOGMAN_THROW_A_FMT(IsStandardFloatSize(size), "Only 16/32/64-bit sub
gitextract_1dff4jwg/
├── .clang-format
├── .clang-format-ignore
├── .git-blame-ignore-revs
├── .github/
│ ├── ISSUE_TEMPLATE/
│ │ └── potential-game-bug.md
│ └── workflows/
│ ├── ccpp.yml
│ ├── glibc_fault.yml
│ ├── hostrunner.yml
│ ├── instcountci.yml
│ ├── mingw_build.yml
│ ├── pr-code-format.yml
│ ├── setup-env/
│ │ └── action.yml
│ ├── steamrt4.yml
│ ├── test/
│ │ └── action.yml
│ ├── vixl_simulator.yml
│ ├── wine_build/
│ │ └── action.yml
│ └── wine_dll_artifacts.yml
├── .gitignore
├── .gitlab-ci.yml
├── .gitmodules
├── CMakeLists.txt
├── CMakeSettings.json
├── CODE_OF_CONDUCT.md
├── CodeEmitter/
│ ├── CMakeLists.txt
│ └── CodeEmitter/
│ ├── ALUOps.inl
│ ├── ASIMDOps.inl
│ ├── BranchOps.inl
│ ├── Buffer.h
│ ├── Emitter.h
│ ├── LoadstoreOps.inl
│ ├── Registers.h
│ ├── SVEOps.inl
│ ├── ScalarOps.inl
│ ├── SystemOps.inl
│ └── VixlUtils.inl
├── Data/
│ ├── AppConfig/
│ │ ├── CMakeLists.txt
│ │ ├── client.json
│ │ └── steamwebhelper.json
│ ├── CI/
│ │ ├── FEXLinuxTestsThunks.json
│ │ ├── GLThunks.json
│ │ └── VulkanThunks.json
│ ├── CMake/
│ │ ├── FindZycore.cmake
│ │ ├── FindZydis.cmake
│ │ ├── Findxxhash.cmake
│ │ ├── LinkerGC.cmake
│ │ ├── cmake_uninstall.cmake.in
│ │ ├── toolchain_aarch64.cmake
│ │ ├── toolchain_mingw.cmake
│ │ ├── toolchain_x86_32.cmake
│ │ ├── toolchain_x86_64.cmake
│ │ └── version_to_variables.cmake
│ ├── Dockerfile
│ ├── ThunksDB.json
│ ├── binfmts/
│ │ ├── CMakeLists.txt
│ │ ├── FEX-x86.conf.in
│ │ ├── FEX-x86.in
│ │ ├── FEX-x86_64.conf.in
│ │ └── FEX-x86_64.in
│ └── nix/
│ ├── FEXLinuxTests/
│ │ └── shell.nix
│ ├── LibraryForwarding/
│ │ └── shell.nix
│ ├── WineOnArm/
│ │ └── shell.nix
│ ├── cmake_configure_woa32.sh
│ ├── cmake_configure_woa64.sh
│ ├── cmake_enable_flt.sh
│ └── cmake_enable_libfwd.sh
├── External/
│ ├── .clang-format
│ ├── SoftFloat-3e/
│ │ ├── CMakeLists.txt
│ │ ├── include/
│ │ │ └── SoftFloat-3e/
│ │ │ ├── opts-GCC.h
│ │ │ ├── platform.h
│ │ │ ├── primitiveTypes.h
│ │ │ ├── softfloat.h
│ │ │ └── softfloat_types.h
│ │ └── src/
│ │ ├── extF80_add.c
│ │ ├── extF80_div.c
│ │ ├── extF80_eq.c
│ │ ├── extF80_le.c
│ │ ├── extF80_lt.c
│ │ ├── extF80_mul.c
│ │ ├── extF80_rem.c
│ │ ├── extF80_roundToInt.c
│ │ ├── extF80_sqrt.c
│ │ ├── extF80_sub.c
│ │ ├── extF80_to_f128.c
│ │ ├── extF80_to_f32.c
│ │ ├── extF80_to_f64.c
│ │ ├── extF80_to_i32.c
│ │ ├── extF80_to_i64.c
│ │ ├── extF80_to_ui64.c
│ │ ├── f128_add.c
│ │ ├── f128_div.c
│ │ ├── f128_eq.c
│ │ ├── f128_eq_signaling.c
│ │ ├── f128_isSignalingNaN.c
│ │ ├── f128_le.c
│ │ ├── f128_le_quiet.c
│ │ ├── f128_lt.c
│ │ ├── f128_lt_quiet.c
│ │ ├── f128_mul.c
│ │ ├── f128_mulAdd.c
│ │ ├── f128_rem.c
│ │ ├── f128_sqrt.c
│ │ ├── f128_sub.c
│ │ ├── f128_to_extF80.c
│ │ ├── f128_to_f16.c
│ │ ├── f128_to_f32.c
│ │ ├── f128_to_f64.c
│ │ ├── f128_to_i32.c
│ │ ├── f128_to_i64.c
│ │ ├── f128_to_ui32.c
│ │ ├── f128_to_ui64.c
│ │ ├── f32_to_extF80.c
│ │ ├── f32_to_f128.c
│ │ ├── f64_to_extF80.c
│ │ ├── i32_to_extF80.c
│ │ ├── i32_to_f128.c
│ │ ├── internals.h
│ │ ├── primitives.h
│ │ ├── s_add128.c
│ │ ├── s_addMagsExtF80.c
│ │ ├── s_addMagsF128.c
│ │ ├── s_approxRecip32_1.c
│ │ ├── s_approxRecipSqrt32_1.c
│ │ ├── s_approxRecipSqrt_1Ks.c
│ │ ├── s_approxRecip_1Ks.c
│ │ ├── s_commonNaNToExtF80UI.c
│ │ ├── s_commonNaNToF128UI.c
│ │ ├── s_commonNaNToF32UI.c
│ │ ├── s_commonNaNToF64UI.c
│ │ ├── s_countLeadingZeros32.c
│ │ ├── s_countLeadingZeros64.c
│ │ ├── s_countLeadingZeros8.c
│ │ ├── s_extF80UIToCommonNaN.c
│ │ ├── s_f128UIToCommonNaN.c
│ │ ├── s_f32UIToCommonNaN.c
│ │ ├── s_f64UIToCommonNaN.c
│ │ ├── s_le128.c
│ │ ├── s_lt128.c
│ │ ├── s_mul64ByShifted32To128.c
│ │ ├── s_mul64To128.c
│ │ ├── s_normRoundPackToExtF80.c
│ │ ├── s_normRoundPackToF128.c
│ │ ├── s_normSubnormalExtF80Sig.c
│ │ ├── s_normSubnormalF128Sig.c
│ │ ├── s_normSubnormalF128SigM.c
│ │ ├── s_normSubnormalF32Sig.c
│ │ ├── s_normSubnormalF64Sig.c
│ │ ├── s_propagateNaNExtF80UI.c
│ │ ├── s_propagateNaNF128UI.c
│ │ ├── s_roundPackToExtF80.c
│ │ ├── s_roundPackToF128.c
│ │ ├── s_roundPackToF32.c
│ │ ├── s_roundPackToF64.c
│ │ ├── s_roundToI32.c
│ │ ├── s_roundToI64.c
│ │ ├── s_roundToUI64.c
│ │ ├── s_shiftRightJam128.c
│ │ ├── s_shiftRightJam128Extra.c
│ │ ├── s_shiftRightJam32.c
│ │ ├── s_shiftRightJam64.c
│ │ ├── s_shiftRightJam64Extra.c
│ │ ├── s_shortShiftLeft128.c
│ │ ├── s_shortShiftRight128.c
│ │ ├── s_shortShiftRightJam64.c
│ │ ├── s_shortShiftRightJam64Extra.c
│ │ ├── s_sub128.c
│ │ ├── s_subMagsExtF80.c
│ │ ├── s_subMagsF128.c
│ │ ├── softfloat_raiseFlags.c
│ │ ├── specialize.h
│ │ └── ui64_to_extF80.c
│ ├── cephes/
│ │ ├── CMakeLists.txt
│ │ ├── LICENSE
│ │ ├── include/
│ │ │ └── cephes_128bit.h
│ │ └── src/
│ │ └── 128bit/
│ │ ├── Impl.cpp
│ │ ├── atanll.c
│ │ ├── constll.c
│ │ ├── exp2ll.c
│ │ ├── floorll.c
│ │ ├── log2ll.c
│ │ ├── mconf.h
│ │ ├── mtherr.c
│ │ ├── polevll.c
│ │ ├── sinll.c
│ │ └── tanll.c
│ ├── code-format-helper/
│ │ ├── code-format-helper.py
│ │ ├── requirements_formatting.txt
│ │ └── requirements_formatting.txt.in
│ └── tiny-json/
│ ├── CMakeLists.txt
│ ├── LICENSE
│ ├── tiny-json.c
│ └── tiny-json.h
├── FEXCore/
│ ├── CMakeLists.txt
│ ├── LICENSE
│ ├── Readme.md
│ ├── Scripts/
│ │ ├── config_generator.py
│ │ ├── json_ir_doc_generator.py
│ │ └── json_ir_generator.py
│ ├── Source/
│ │ ├── CMakeLists.txt
│ │ ├── Common/
│ │ │ ├── BitSet.h
│ │ │ ├── JitSymbols.cpp
│ │ │ ├── JitSymbols.h
│ │ │ ├── SoftFloat.h
│ │ │ ├── StringConv.h
│ │ │ └── VectorRegType.h
│ │ ├── Interface/
│ │ │ ├── Config/
│ │ │ │ ├── Config.cpp
│ │ │ │ └── Config.json.in
│ │ │ ├── Context/
│ │ │ │ ├── Context.cpp
│ │ │ │ └── Context.h
│ │ │ ├── Core/
│ │ │ │ ├── Addressing.cpp
│ │ │ │ ├── Addressing.h
│ │ │ │ ├── ArchHelpers/
│ │ │ │ │ ├── Arm64Emitter.cpp
│ │ │ │ │ └── Arm64Emitter.h
│ │ │ │ ├── CPUBackend.cpp
│ │ │ │ ├── CPUBackend.h
│ │ │ │ ├── CPUID.cpp
│ │ │ │ ├── CPUID.h
│ │ │ │ ├── CodeCache.cpp
│ │ │ │ ├── Core.cpp
│ │ │ │ ├── Dispatcher/
│ │ │ │ │ ├── Dispatcher.cpp
│ │ │ │ │ └── Dispatcher.h
│ │ │ │ ├── Frontend.cpp
│ │ │ │ ├── Frontend.h
│ │ │ │ ├── Interpreter/
│ │ │ │ │ ├── Fallbacks/
│ │ │ │ │ │ ├── F80Fallbacks.h
│ │ │ │ │ │ ├── FallbackOpHandler.h
│ │ │ │ │ │ ├── InterpreterFallbacks.cpp
│ │ │ │ │ │ ├── StringCompareFallbacks.cpp
│ │ │ │ │ │ └── VectorFallbacks.h
│ │ │ │ │ └── InterpreterOps.h
│ │ │ │ ├── JIT/
│ │ │ │ │ ├── ALUOps.cpp
│ │ │ │ │ ├── Arm64Relocations.cpp
│ │ │ │ │ ├── AtomicOps.cpp
│ │ │ │ │ ├── BranchOps.cpp
│ │ │ │ │ ├── ConversionOps.cpp
│ │ │ │ │ ├── DebugData.h
│ │ │ │ │ ├── EncryptionOps.cpp
│ │ │ │ │ ├── JIT.cpp
│ │ │ │ │ ├── JITClass.h
│ │ │ │ │ ├── MemoryOps.cpp
│ │ │ │ │ ├── MiscOps.cpp
│ │ │ │ │ ├── MoveOps.cpp
│ │ │ │ │ ├── Relocations.h
│ │ │ │ │ └── VectorOps.cpp
│ │ │ │ ├── LookupCache.cpp
│ │ │ │ ├── LookupCache.h
│ │ │ │ ├── OpcodeDispatcher/
│ │ │ │ │ ├── AVX_128.cpp
│ │ │ │ │ ├── BaseTables.h
│ │ │ │ │ ├── Crypto.cpp
│ │ │ │ │ ├── DDDTables.h
│ │ │ │ │ ├── Flags.cpp
│ │ │ │ │ ├── H0F38Tables.h
│ │ │ │ │ ├── H0F3ATables.h
│ │ │ │ │ ├── PrimaryGroupTables.h
│ │ │ │ │ ├── SecondaryGroupTables.h
│ │ │ │ │ ├── SecondaryModRMTables.h
│ │ │ │ │ ├── SecondaryTables.h
│ │ │ │ │ ├── VEXTables.h
│ │ │ │ │ ├── Vector.cpp
│ │ │ │ │ ├── X87.cpp
│ │ │ │ │ └── X87F64.cpp
│ │ │ │ ├── OpcodeDispatcher.cpp
│ │ │ │ ├── OpcodeDispatcher.h
│ │ │ │ ├── VSyscall/
│ │ │ │ │ └── VSyscall.inc
│ │ │ │ └── X86Tables/
│ │ │ │ ├── BaseTables.cpp
│ │ │ │ ├── DDDTables.cpp
│ │ │ │ ├── H0F38Tables.cpp
│ │ │ │ ├── H0F3ATables.cpp
│ │ │ │ ├── PrimaryGroupTables.cpp
│ │ │ │ ├── SecondaryGroupTables.cpp
│ │ │ │ ├── SecondaryModRMTables.cpp
│ │ │ │ ├── SecondaryTables.cpp
│ │ │ │ ├── VEXTables.cpp
│ │ │ │ ├── X86Tables.h
│ │ │ │ └── X87Tables.cpp
│ │ │ ├── GDBJIT/
│ │ │ │ ├── GDBJIT.cpp
│ │ │ │ └── GDBJIT.h
│ │ │ └── IR/
│ │ │ ├── IR.h
│ │ │ ├── IR.json
│ │ │ ├── IRDumper.cpp
│ │ │ ├── IREmitter.cpp
│ │ │ ├── IREmitter.h
│ │ │ ├── IntrusiveIRList.h
│ │ │ ├── PassManager.cpp
│ │ │ ├── PassManager.h
│ │ │ ├── Passes/
│ │ │ │ ├── IRDumperPass.cpp
│ │ │ │ ├── IRValidation.cpp
│ │ │ │ ├── IRValidation.h
│ │ │ │ ├── RedundantFlagCalculationElimination.cpp
│ │ │ │ ├── RegisterAllocationPass.cpp
│ │ │ │ ├── RegisterAllocationPass.h
│ │ │ │ └── x87StackOptimizationPass.cpp
│ │ │ ├── Passes.h
│ │ │ └── RegisterAllocationData.h
│ │ └── Utils/
│ │ ├── Allocator/
│ │ │ ├── 64BitAllocator.cpp
│ │ │ ├── FlexBitSet.h
│ │ │ ├── HostAllocator.h
│ │ │ └── IntrusiveArenaAllocator.h
│ │ ├── Allocator.cpp
│ │ ├── Allocator.h
│ │ ├── AllocatorHooks.cpp
│ │ ├── AllocatorOverride.cpp
│ │ ├── ArchHelpers/
│ │ │ ├── Arm64.cpp
│ │ │ └── Arm64_stubs.cpp
│ │ ├── BucketList.h
│ │ ├── Config.h
│ │ ├── FileLoading.cpp
│ │ ├── ForcedAssert.cpp
│ │ ├── LogManager.cpp
│ │ ├── LongJump.cpp
│ │ ├── MemberFunctionToPointer.h
│ │ ├── Profiler.cpp
│ │ ├── SpinWaitLock.cpp
│ │ ├── SpinWaitLock.h
│ │ ├── Telemetry.cpp
│ │ ├── Threads.cpp
│ │ ├── WritePriorityMutex.h
│ │ └── variable_length_integer.h
│ ├── docs/
│ │ ├── CPUBackends.md
│ │ ├── CustomCPUBackend.md
│ │ ├── Frontend.md
│ │ ├── IR.md
│ │ ├── MemoryModelEmulation.md
│ │ └── OpDispatcher.md
│ ├── include/
│ │ ├── FEXCore/
│ │ │ ├── Config/
│ │ │ │ └── Config.h
│ │ │ ├── Core/
│ │ │ │ ├── CPUID.h
│ │ │ │ ├── CodeCache.h
│ │ │ │ ├── Context.h
│ │ │ │ ├── CoreState.h
│ │ │ │ ├── HostFeatures.h
│ │ │ │ ├── SignalDelegator.h
│ │ │ │ ├── Thunks.h
│ │ │ │ └── X86Enums.h
│ │ │ ├── Debug/
│ │ │ │ ├── GDBReaderInterface.h
│ │ │ │ └── InternalThreadState.h
│ │ │ ├── HLE/
│ │ │ │ ├── SourcecodeResolver.h
│ │ │ │ └── SyscallHandler.h
│ │ │ ├── IR/
│ │ │ │ └── IR.h
│ │ │ ├── Utils/
│ │ │ │ ├── Allocator.h
│ │ │ │ ├── AllocatorHooks.h
│ │ │ │ ├── ArchHelpers/
│ │ │ │ │ └── Arm64.h
│ │ │ │ ├── CompilerDefs.h
│ │ │ │ ├── EnumOperators.h
│ │ │ │ ├── EnumUtils.h
│ │ │ │ ├── Event.h
│ │ │ │ ├── FPState.h
│ │ │ │ ├── File.h
│ │ │ │ ├── FileLoading.h
│ │ │ │ ├── InterruptableConditionVariable.h
│ │ │ │ ├── IntervalList.h
│ │ │ │ ├── LogManager.h
│ │ │ │ ├── LongJump.h
│ │ │ │ ├── MathUtils.h
│ │ │ │ ├── PrctlUtils.h
│ │ │ │ ├── Profiler.h
│ │ │ │ ├── SHMStats.h
│ │ │ │ ├── SignalScopeGuards.h
│ │ │ │ ├── StringUtils.h
│ │ │ │ ├── Telemetry.h
│ │ │ │ ├── ThreadPoolAllocator.h
│ │ │ │ ├── Threads.h
│ │ │ │ └── TypeDefines.h
│ │ │ └── fextl/
│ │ │ ├── allocator.h
│ │ │ ├── deque.h
│ │ │ ├── fmt.h
│ │ │ ├── forward_list.h
│ │ │ ├── functional.h
│ │ │ ├── list.h
│ │ │ ├── map.h
│ │ │ ├── memory.h
│ │ │ ├── memory_resource.h
│ │ │ ├── queue.h
│ │ │ ├── robin_map.h
│ │ │ ├── robin_set.h
│ │ │ ├── set.h
│ │ │ ├── sstream.h
│ │ │ ├── stack.h
│ │ │ ├── string.h
│ │ │ ├── unordered_map.h
│ │ │ ├── unordered_set.h
│ │ │ └── vector.h
│ │ └── git_version.h.in
│ └── unittests/
│ ├── APITests/
│ │ ├── Allocator.cpp
│ │ ├── CMakeLists.txt
│ │ ├── FileLoading.cpp
│ │ ├── FlexBitSet.cpp
│ │ ├── FutexSpinTest.cpp
│ │ ├── ILog2.cpp
│ │ └── vl_integer.cpp
│ ├── CMakeLists.txt
│ └── Emitter/
│ ├── ALU_Tests.cpp
│ ├── ASIMD_Tests.cpp
│ ├── Branch_Tests.cpp
│ ├── CMakeLists.txt
│ ├── Loadstore_Tests.cpp
│ ├── SVE_Tests.cpp
│ ├── Scalar_Tests.cpp
│ ├── System_Tests.cpp
│ └── TestDisassembler.h
├── FEXHeaderUtils/
│ ├── CMakeLists.txt
│ └── FEXHeaderUtils/
│ ├── BitUtils.h
│ ├── Filesystem.h
│ ├── RingBuffer.h
│ ├── StringArgumentParser.h
│ ├── SymlinkChecks.h
│ └── Syscalls.h
├── LICENSE
├── Readme.md
├── Scripts/
│ ├── CI_FetchRootFS.py
│ ├── CheckBinfmtNotInstall.sh
│ ├── ClassifyCPU.py
│ ├── DefinitionExtract.py
│ ├── FEXUpdateAOTIRCache.sh
│ ├── GenerateSyscallNumbers.py
│ ├── InstallFEX.py
│ ├── InstructionCountParser.py
│ ├── NeedDisabledSVE.py
│ ├── StructPackVerifier.py
│ ├── Threaded_Lockstep_Runner.py
│ ├── UpdateInstructionCountJson.py
│ ├── aarch64_fit_native.py
│ ├── changelog_generator.py
│ ├── doc_outline_generator.py
│ ├── generate_changelog.sh
│ ├── generate_doc_outline.sh
│ ├── generate_release.sh
│ ├── guest_test_runner.py
│ ├── json_asm_config_parse.py
│ ├── json_config_parse.py
│ ├── json_ir_config_parse.py
│ ├── reformat.sh
│ ├── testharness_runner.py
│ └── update_instcountci.sh
├── Source/
│ ├── CMakeLists.txt
│ ├── Common/
│ │ ├── ArgumentLoader.cpp
│ │ ├── ArgumentLoader.h
│ │ ├── Async.h
│ │ ├── AsyncNet.h
│ │ ├── CMakeLists.txt
│ │ ├── CPUInfo.cpp
│ │ ├── CPUInfo.h
│ │ ├── Config.cpp
│ │ ├── Config.h
│ │ ├── FDUtils.h
│ │ ├── FEXServerClient.cpp
│ │ ├── FEXServerClient.h
│ │ ├── FileFormatCheck.cpp
│ │ ├── FileFormatCheck.h
│ │ ├── FileMappingBaseAddress.h
│ │ ├── HostFeatures.cpp
│ │ ├── HostFeatures.h
│ │ ├── JSONPool.cpp
│ │ ├── JSONPool.h
│ │ ├── Linux/
│ │ │ ├── SBRKAllocations.cpp
│ │ │ └── SBRKAllocations.h
│ │ ├── SHMStats.cpp
│ │ ├── SHMStats.h
│ │ ├── VolatileMetadata.cpp
│ │ ├── VolatileMetadata.h
│ │ └── X86Features.h
│ ├── Steam/
│ │ ├── CMakeLists.txt
│ │ ├── CompatTool.cpp
│ │ ├── ConfigTemplate.json
│ │ ├── ServerManager.cpp
│ │ ├── VERSIONS.txt.in
│ │ ├── emulator.json
│ │ └── toolmanifest.vdf
│ ├── Tools/
│ │ ├── CMakeLists.txt
│ │ ├── CodeSizeValidation/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── CommonTools/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── CodeLoader.h
│ │ │ ├── DummyHandlers.cpp
│ │ │ ├── DummyHandlers.h
│ │ │ ├── HarnessHelpers.h
│ │ │ ├── Linux/
│ │ │ │ └── Utils/
│ │ │ │ ├── ELFContainer.cpp
│ │ │ │ ├── ELFContainer.h
│ │ │ │ └── ELFParser.h
│ │ │ └── PortabilityInfo.h
│ │ ├── FEXBash/
│ │ │ ├── CMakeLists.txt
│ │ │ └── FEXBash.cpp
│ │ ├── FEXConfig/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Main.cpp
│ │ │ ├── Main.h
│ │ │ ├── main.qml
│ │ │ ├── qml5.qrc
│ │ │ ├── qml6.qrc
│ │ │ ├── qt5/
│ │ │ │ ├── FileDialog.qml
│ │ │ │ ├── FolderDialog.qml
│ │ │ │ └── MessageDialog.qml
│ │ │ └── qt6/
│ │ │ ├── FileDialog.qml
│ │ │ ├── FolderDialog.qml
│ │ │ └── MessageDialog.qml
│ │ ├── FEXGDBReader/
│ │ │ ├── CMakeLists.txt
│ │ │ └── FEXGDBReader.cpp
│ │ ├── FEXGetConfig/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── FEXInterpreter/
│ │ │ ├── AOT/
│ │ │ │ ├── AOTGenerator.cpp
│ │ │ │ └── AOTGenerator.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── ELFCodeLoader.h
│ │ │ └── FEXInterpreter.cpp
│ │ ├── FEXOfflineCompiler/
│ │ │ ├── CMakeLists.txt
│ │ │ └── Main.cpp
│ │ ├── FEXRootFSFetcher/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Main.cpp
│ │ │ ├── XXFileHash.cpp
│ │ │ └── XXFileHash.h
│ │ ├── FEXServer/
│ │ │ ├── ArgumentLoader.cpp
│ │ │ ├── ArgumentLoader.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── Logger.cpp
│ │ │ ├── Logger.h
│ │ │ ├── Main.cpp
│ │ │ ├── PipeScanner.cpp
│ │ │ ├── PipeScanner.h
│ │ │ ├── ProcessPipe.cpp
│ │ │ ├── ProcessPipe.h
│ │ │ ├── SquashFS.cpp
│ │ │ └── SquashFS.h
│ │ ├── LinuxEmulation/
│ │ │ ├── ArchHelpers/
│ │ │ │ ├── MContext.cpp
│ │ │ │ ├── MContext.h
│ │ │ │ ├── UContext.h
│ │ │ │ └── WinContext.h
│ │ │ ├── CMakeLists.txt
│ │ │ ├── GdbServer/
│ │ │ │ ├── Info.cpp
│ │ │ │ └── Info.h
│ │ │ ├── LinuxSyscalls/
│ │ │ │ ├── Arm64/
│ │ │ │ │ └── SyscallsEnum.h
│ │ │ │ ├── EmulatedFiles/
│ │ │ │ │ ├── EmulatedFiles.cpp
│ │ │ │ │ └── EmulatedFiles.h
│ │ │ │ ├── FaultSafeUserMemAccess.cpp
│ │ │ │ ├── FileManagement.cpp
│ │ │ │ ├── FileManagement.h
│ │ │ │ ├── GdbServer.cpp
│ │ │ │ ├── GdbServer.h
│ │ │ │ ├── LinuxAllocator.cpp
│ │ │ │ ├── LinuxAllocator.h
│ │ │ │ ├── Seccomp/
│ │ │ │ │ ├── BPFEmitter.cpp
│ │ │ │ │ ├── BPFEmitter.h
│ │ │ │ │ ├── Dumper.cpp
│ │ │ │ │ ├── SeccompEmulator.cpp
│ │ │ │ │ └── SeccompEmulator.h
│ │ │ │ ├── SignalDelegator/
│ │ │ │ │ └── GuestFramesManagement.cpp
│ │ │ │ ├── SignalDelegator.cpp
│ │ │ │ ├── SignalDelegator.h
│ │ │ │ ├── Syscalls/
│ │ │ │ │ ├── EPoll.cpp
│ │ │ │ │ ├── FD.cpp
│ │ │ │ │ ├── FS.cpp
│ │ │ │ │ ├── IO.cpp
│ │ │ │ │ ├── Info.cpp
│ │ │ │ │ ├── Memory.cpp
│ │ │ │ │ ├── NotImplemented.cpp
│ │ │ │ │ ├── Passthrough.cpp
│ │ │ │ │ ├── Signals.cpp
│ │ │ │ │ ├── Stubs.cpp
│ │ │ │ │ ├── Thread.cpp
│ │ │ │ │ ├── Thread.h
│ │ │ │ │ └── Timer.cpp
│ │ │ │ ├── Syscalls.cpp
│ │ │ │ ├── Syscalls.h
│ │ │ │ ├── SyscallsSMCTracking.cpp
│ │ │ │ ├── SyscallsVMATracking.cpp
│ │ │ │ ├── SyscallsVMATracking.h
│ │ │ │ ├── ThreadManager.cpp
│ │ │ │ ├── ThreadManager.h
│ │ │ │ ├── Types.h
│ │ │ │ ├── Utils/
│ │ │ │ │ ├── Threads.cpp
│ │ │ │ │ └── Threads.h
│ │ │ │ ├── x32/
│ │ │ │ │ ├── EPoll.cpp
│ │ │ │ │ ├── FD.cpp
│ │ │ │ │ ├── FS.cpp
│ │ │ │ │ ├── IO.cpp
│ │ │ │ │ ├── Info.cpp
│ │ │ │ │ ├── Ioctl/
│ │ │ │ │ │ ├── HelperDefines.h
│ │ │ │ │ │ ├── amdgpu_drm.inl
│ │ │ │ │ │ ├── asahi_drm.inl
│ │ │ │ │ │ ├── asound.h
│ │ │ │ │ │ ├── asound.inl
│ │ │ │ │ │ ├── drm.h
│ │ │ │ │ │ ├── drm.inl
│ │ │ │ │ │ ├── ext_fs.h
│ │ │ │ │ │ ├── ext_fs.inl
│ │ │ │ │ │ ├── f2fs.h
│ │ │ │ │ │ ├── f2fs.inl
│ │ │ │ │ │ ├── i915_drm.inl
│ │ │ │ │ │ ├── input.h
│ │ │ │ │ │ ├── input.inl
│ │ │ │ │ │ ├── joystick.h
│ │ │ │ │ │ ├── joystick.inl
│ │ │ │ │ │ ├── lima_drm.inl
│ │ │ │ │ │ ├── msdos_fs.h
│ │ │ │ │ │ ├── msdos_fs.inl
│ │ │ │ │ │ ├── msm_drm.inl
│ │ │ │ │ │ ├── nouveau_drm.inl
│ │ │ │ │ │ ├── nova_drm.inl
│ │ │ │ │ │ ├── panfrost_drm.inl
│ │ │ │ │ │ ├── panthor_drm.inl
│ │ │ │ │ │ ├── pvr_drm.inl
│ │ │ │ │ │ ├── radeon_drm.inl
│ │ │ │ │ │ ├── sockios.h
│ │ │ │ │ │ ├── sockios.inl
│ │ │ │ │ │ ├── streams.h
│ │ │ │ │ │ ├── streams.inl
│ │ │ │ │ │ ├── usbdev.h
│ │ │ │ │ │ ├── usbdev.inl
│ │ │ │ │ │ ├── v3d_drm.inl
│ │ │ │ │ │ ├── v4l2.h
│ │ │ │ │ │ ├── v4l2.inl
│ │ │ │ │ │ ├── vc4_drm.inl
│ │ │ │ │ │ ├── virtio_drm.inl
│ │ │ │ │ │ ├── wireless.h
│ │ │ │ │ │ ├── wireless.inl
│ │ │ │ │ │ └── xe_drm.inl
│ │ │ │ │ ├── IoctlEmulation.cpp
│ │ │ │ │ ├── IoctlEmulation.h
│ │ │ │ │ ├── Ioctls.inl
│ │ │ │ │ ├── Memory.cpp
│ │ │ │ │ ├── Msg.cpp
│ │ │ │ │ ├── NotImplemented.cpp
│ │ │ │ │ ├── Sched.cpp
│ │ │ │ │ ├── Semaphore.cpp
│ │ │ │ │ ├── Signals.cpp
│ │ │ │ │ ├── Socket.cpp
│ │ │ │ │ ├── Stubs.cpp
│ │ │ │ │ ├── Syscalls.cpp
│ │ │ │ │ ├── Syscalls.h
│ │ │ │ │ ├── SyscallsEnum.h
│ │ │ │ │ ├── SyscallsNames.inl
│ │ │ │ │ ├── Thread.cpp
│ │ │ │ │ ├── Thread.h
│ │ │ │ │ ├── Time.cpp
│ │ │ │ │ ├── Timer.cpp
│ │ │ │ │ └── Types.h
│ │ │ │ └── x64/
│ │ │ │ ├── EPoll.cpp
│ │ │ │ ├── FD.cpp
│ │ │ │ ├── Info.cpp
│ │ │ │ ├── Ioctl/
│ │ │ │ │ ├── HelperDefines.h
│ │ │ │ │ ├── amdgpu_drm.inl
│ │ │ │ │ ├── asound.h
│ │ │ │ │ ├── asound.inl
│ │ │ │ │ ├── drm.h
│ │ │ │ │ ├── drm.inl
│ │ │ │ │ ├── ext_fs.h
│ │ │ │ │ ├── ext_fs.inl
│ │ │ │ │ ├── f2fs.h
│ │ │ │ │ ├── f2fs.inl
│ │ │ │ │ ├── input.h
│ │ │ │ │ ├── input.inl
│ │ │ │ │ ├── joystick.h
│ │ │ │ │ ├── joystick.inl
│ │ │ │ │ ├── msdos_fs.h
│ │ │ │ │ ├── msdos_fs.inl
│ │ │ │ │ ├── msm_drm.inl
│ │ │ │ │ ├── sockios.h
│ │ │ │ │ ├── sockios.inl
│ │ │ │ │ ├── wireless.h
│ │ │ │ │ └── wireless.inl
│ │ │ │ ├── Memory.cpp
│ │ │ │ ├── NotImplemented.cpp
│ │ │ │ ├── Semaphore.cpp
│ │ │ │ ├── Signals.cpp
│ │ │ │ ├── Syscalls.cpp
│ │ │ │ ├── Syscalls.h
│ │ │ │ ├── SyscallsEnum.h
│ │ │ │ ├── SyscallsNames.inl
│ │ │ │ ├── Thread.cpp
│ │ │ │ ├── Thread.h
│ │ │ │ ├── Time.cpp
│ │ │ │ └── Types.h
│ │ │ ├── Thunks.cpp
│ │ │ ├── Thunks.h
│ │ │ ├── VDSO_Emulation.cpp
│ │ │ └── VDSO_Emulation.h
│ │ ├── TestHarnessRunner/
│ │ │ ├── CMakeLists.txt
│ │ │ ├── TestHarnessRunner/
│ │ │ │ ├── HostRunner.cpp
│ │ │ │ └── HostRunner.h
│ │ │ └── TestHarnessRunner.cpp
│ │ └── pidof/
│ │ ├── CMakeLists.txt
│ │ └── pidof.cpp
│ └── Windows/
│ ├── ARM64EC/
│ │ ├── BTInterface.h
│ │ ├── CMakeLists.txt
│ │ ├── Module.S
│ │ ├── Module.cpp
│ │ └── libarm64ecfex.def
│ ├── CMakeLists.txt
│ ├── Common/
│ │ ├── CMakeLists.txt
│ │ ├── CPUFeatures.cpp
│ │ ├── CPUFeatures.h
│ │ ├── CRT/
│ │ │ ├── Alloc.cpp
│ │ │ ├── CMakeLists.txt
│ │ │ ├── CRT.cpp
│ │ │ ├── CRT.h
│ │ │ ├── IO.cpp
│ │ │ ├── Math.cpp
│ │ │ ├── Misc.cpp
│ │ │ ├── Musl/
│ │ │ │ ├── CMakeLists.txt
│ │ │ │ ├── __math_divzero.c
│ │ │ │ ├── __math_invalid.c
│ │ │ │ ├── __math_oflow.c
│ │ │ │ ├── __math_uflow.c
│ │ │ │ ├── __math_xflow.c
│ │ │ │ ├── exp2.c
│ │ │ │ ├── exp_data.c
│ │ │ │ ├── exp_data.h
│ │ │ │ ├── fmod.c
│ │ │ │ ├── isnan.c
│ │ │ │ ├── libm.h
│ │ │ │ ├── log2.c
│ │ │ │ ├── log2_data.c
│ │ │ │ ├── log2_data.h
│ │ │ │ ├── remainder.c
│ │ │ │ ├── remquo.c
│ │ │ │ ├── strtoimax.c
│ │ │ │ ├── strtoll.c
│ │ │ │ ├── strtoull.c
│ │ │ │ └── strtoumax.c
│ │ │ └── String.cpp
│ │ ├── CallRetStack.h
│ │ ├── Exception.h
│ │ ├── Handle.h
│ │ ├── ImageTracker.cpp
│ │ ├── ImageTracker.h
│ │ ├── InvalidationTracker.cpp
│ │ ├── InvalidationTracker.h
│ │ ├── JITGuardPage.h
│ │ ├── LoadConfig.S
│ │ ├── Logging.cpp
│ │ ├── Logging.h
│ │ ├── Module.h
│ │ ├── OvercommitTracker.h
│ │ ├── PortabilityInfo.h
│ │ ├── Priv.h
│ │ ├── SHMStats.cpp
│ │ ├── SHMStats.h
│ │ ├── TSOHandlerConfig.h
│ │ └── WinAPI/
│ │ ├── Alloc.cpp
│ │ ├── CMakeLists.txt
│ │ ├── IO.cpp
│ │ ├── Misc.cpp
│ │ └── Sync.cpp
│ ├── Defs/
│ │ ├── ntdll.def
│ │ └── wow64.def
│ ├── WOW64/
│ │ ├── BTInterface.h
│ │ ├── CMakeLists.txt
│ │ ├── Module.cpp
│ │ └── libwow64fex.def
│ └── include/
│ ├── wine/
│ │ ├── debug.h
│ │ └── unixlib.h
│ ├── winnt.h
│ └── winternl.h
├── ThunkLibs/
│ ├── Generator/
│ │ ├── CMakeLists.txt
│ │ ├── analysis.cpp
│ │ ├── analysis.h
│ │ ├── data_layout.cpp
│ │ ├── data_layout.h
│ │ ├── diagnostics.h
│ │ ├── gen.cpp
│ │ ├── interface.h
│ │ └── main.cpp
│ ├── GuestLibs/
│ │ └── CMakeLists.txt
│ ├── HostLibs/
│ │ └── CMakeLists.txt
│ ├── README.md
│ ├── include/
│ │ └── common/
│ │ ├── GeneratorInterface.h
│ │ ├── Guest.h
│ │ ├── Host.h
│ │ ├── PackedArguments.h
│ │ └── X11Manager.h
│ ├── libEGL/
│ │ ├── libEGL_Guest.cpp
│ │ ├── libEGL_Host.cpp
│ │ └── libEGL_interface.cpp
│ ├── libGL/
│ │ ├── glcorearb.h
│ │ ├── libGL_Guest.cpp
│ │ ├── libGL_Host.cpp
│ │ └── libGL_interface.cpp
│ ├── libSDL2/
│ │ ├── libSDL2_Guest.cpp
│ │ └── libSDL2_Host.cpp
│ ├── libVDSO/
│ │ ├── Types.h
│ │ ├── libVDSO_Guest.cpp
│ │ ├── libVDSO_Guest.lds
│ │ ├── libVDSO_Guest_32.lds
│ │ └── libVDSO_interface.cpp
│ ├── libX11/
│ │ └── libX11_NativeGuest.cpp
│ ├── libasound/
│ │ ├── libasound_Guest.cpp
│ │ ├── libasound_Host.cpp
│ │ └── libasound_interface.cpp
│ ├── libdrm/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libdrm_interface.cpp
│ ├── libfex_malloc/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── Types.h
│ ├── libfex_malloc_loader/
│ │ └── Guest.cpp
│ ├── libfex_malloc_symbols/
│ │ └── Host.cpp
│ ├── libfex_thunk_test/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ ├── api.h
│ │ ├── lib.cpp
│ │ └── libfex_thunk_test_interface.cpp
│ ├── libvulkan/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libvulkan_interface.cpp
│ ├── libwayland-client/
│ │ ├── Guest.cpp
│ │ ├── Host.cpp
│ │ └── libwayland-client_interface.cpp
│ └── libxshmfence/
│ ├── Guest.cpp
│ ├── Host.cpp
│ └── libxshmfence_interface.cpp
├── docs/
│ ├── CPUID.md
│ ├── DeferredSignals.md
│ ├── ProgrammingConcerns.md
│ ├── Readme_CN.md
│ ├── ReleaseProcess.md
│ ├── SourceOutline.md
│ └── allocator_usage.md
└── unittests/
├── 32Bit_ASM/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Disabled_Tests_Simulator
│ ├── Disabled_Tests_host
│ ├── FEX_bugs/
│ │ ├── GOT_calculation.asm
│ │ ├── IMUL_garbagedata.asm
│ │ ├── InlineSyscall.asm
│ │ ├── InvertedCarrySet.asm
│ │ ├── LoopAddressSizeCheck.asm
│ │ ├── SignExtendBug.asm
│ │ ├── SubAddrBug.asm
│ │ ├── TelemetryFlags.asm
│ │ ├── VEXW_Bug.asm
│ │ ├── adc.asm
│ │ ├── rep_lods_bug.asm
│ │ └── x87_unordered_cmp_fix_32.asm
│ ├── Known_Failures
│ ├── Primary/
│ │ ├── Loops.asm
│ │ ├── Pop_Segments.asm
│ │ ├── Primary_00.asm
│ │ ├── Primary_00_2.asm
│ │ ├── Primary_00_3.asm
│ │ ├── Primary_27.asm
│ │ ├── Primary_2F.asm
│ │ ├── Primary_37.asm
│ │ ├── Primary_3F.asm
│ │ ├── Primary_60.asm
│ │ ├── Primary_60_2.asm
│ │ ├── Primary_61.asm
│ │ ├── Primary_61_2.asm
│ │ ├── Primary_8C.asm
│ │ ├── Primary_8C_2.asm
│ │ ├── Primary_8D.asm
│ │ ├── Primary_A0.asm
│ │ ├── Primary_A2.asm
│ │ ├── Primary_A6.asm
│ │ ├── Primary_A6_REP.asm
│ │ ├── Primary_A6_REPNE.asm
│ │ ├── Primary_A6_REPNE_Equal.asm
│ │ ├── Primary_A6_REP_Equal.asm
│ │ ├── Primary_A6_REP_Smaller.asm
│ │ ├── Primary_A6_REP_down.asm
│ │ ├── Primary_A6_REP_down_Equal.asm
│ │ ├── Primary_A6_down.asm
│ │ ├── Primary_A7_dword.asm
│ │ ├── Primary_A7_dword_down.asm
│ │ ├── Primary_A7_word.asm
│ │ ├── Primary_A7_word_down.asm
│ │ ├── Primary_AE.asm
│ │ ├── Primary_AE_REP.asm
│ │ ├── Primary_AE_REPNE.asm
│ │ ├── Primary_AE_REPNE_down.asm
│ │ ├── Primary_AE_REP_down.asm
│ │ ├── Primary_AF_REP_dword.asm
│ │ ├── Primary_AF_REP_word.asm
│ │ ├── Primary_C9.asm
│ │ ├── Primary_CE.asm
│ │ ├── Primary_CF.asm
│ │ ├── Primary_D4.asm
│ │ ├── Primary_D5.asm
│ │ ├── Primary_D6.asm
│ │ ├── Primary_E3.asm
│ │ ├── Primary_E8.asm
│ │ ├── Primary_E8_2.asm
│ │ ├── Primary_E9.asm
│ │ ├── Primary_E9_2.asm
│ │ └── Push_Segments.asm
│ ├── PrimaryGroup/
│ │ ├── 3_F6_05.asm
│ │ ├── 5_FF_02.asm
│ │ ├── 5_FF_02_2.asm
│ │ └── 5_FF_02_3.asm
│ ├── Secondary/
│ │ ├── 07_XX_00.asm
│ │ ├── 07_XX_04.asm
│ │ └── 15_XX_0.asm
│ ├── SecondaryModRM/
│ │ ├── Reg_7_1.asm
│ │ └── Reg_7_4_2.asm
│ ├── TwoByte/
│ │ ├── 0F_82.asm
│ │ └── 0F_82_2.asm
│ ├── VEX/
│ │ ├── vgather_qpd_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_4xdisp_overflow.asm
│ │ └── vpgather_qq_256bit_8xdisp_overflow.asm
│ ├── X87/
│ │ ├── D8_00.asm
│ │ ├── D8_01.asm
│ │ ├── D8_04.asm
│ │ ├── D8_05.asm
│ │ ├── D8_06.asm
│ │ ├── D8_07.asm
│ │ ├── D8_C0.asm
│ │ ├── D8_C8.asm
│ │ ├── D8_E0.asm
│ │ ├── D8_E8.asm
│ │ ├── D8_F0.asm
│ │ ├── D8_F0_2.asm
│ │ ├── D8_F8.asm
│ │ ├── D9_00.asm
│ │ ├── D9_02.asm
│ │ ├── D9_03.asm
│ │ ├── D9_05.asm
│ │ ├── D9_06.asm
│ │ ├── D9_06_2.asm
│ │ ├── D9_07.asm
│ │ ├── D9_C0.asm
│ │ ├── D9_C8.asm
│ │ ├── D9_D0.asm
│ │ ├── D9_E0.asm
│ │ ├── D9_E1.asm
│ │ ├── D9_E8.asm
│ │ ├── D9_E9.asm
│ │ ├── D9_EA.asm
│ │ ├── D9_EB.asm
│ │ ├── D9_EC.asm
│ │ ├── D9_ED.asm
│ │ ├── D9_EE.asm
│ │ ├── D9_F0.asm
│ │ ├── D9_F1.asm
│ │ ├── D9_F2.asm
│ │ ├── D9_F3.asm
│ │ ├── D9_F4.asm
│ │ ├── D9_F5.asm
│ │ ├── D9_F6.asm
│ │ ├── D9_F7.asm
│ │ ├── D9_F8.asm
│ │ ├── D9_F9.asm
│ │ ├── D9_FA.asm
│ │ ├── D9_FB.asm
│ │ ├── D9_FC.asm
│ │ ├── D9_FD.asm
│ │ ├── D9_FE.asm
│ │ ├── D9_FF.asm
│ │ ├── DA_00.asm
│ │ ├── DA_01.asm
│ │ ├── DA_04.asm
│ │ ├── DA_05.asm
│ │ ├── DA_06.asm
│ │ ├── DA_07.asm
│ │ ├── DA_C0.asm
│ │ ├── DA_C8.asm
│ │ ├── DA_D0.asm
│ │ ├── DA_D8.asm
│ │ ├── DB_00.asm
│ │ ├── DB_01.asm
│ │ ├── DB_02.asm
│ │ ├── DB_03.asm
│ │ ├── DB_05.asm
│ │ ├── DB_07.asm
│ │ ├── DB_C0.asm
│ │ ├── DB_C8.asm
│ │ ├── DB_D0.asm
│ │ ├── DB_D8.asm
│ │ ├── DB_E2.asm
│ │ ├── DB_E3.asm
│ │ ├── DB_E3_2.asm
│ │ ├── DC_00.asm
│ │ ├── DC_01.asm
│ │ ├── DC_04.asm
│ │ ├── DC_05.asm
│ │ ├── DC_06.asm
│ │ ├── DC_07.asm
│ │ ├── DC_C0.asm
│ │ ├── DC_C8.asm
│ │ ├── DC_E0.asm
│ │ ├── DC_E8.asm
│ │ ├── DC_F0.asm
│ │ ├── DC_F8.asm
│ │ ├── DD_00.asm
│ │ ├── DD_01.asm
│ │ ├── DD_02.asm
│ │ ├── DD_03.asm
│ │ ├── DD_04.asm
│ │ ├── DD_04_2.asm
│ │ ├── DD_07.asm
│ │ ├── DD_C0.asm
│ │ ├── DD_D0.asm
│ │ ├── DD_D8.asm
│ │ ├── DE_00.asm
│ │ ├── DE_01.asm
│ │ ├── DE_04.asm
│ │ ├── DE_05.asm
│ │ ├── DE_06.asm
│ │ ├── DE_07.asm
│ │ ├── DE_C0.asm
│ │ ├── DE_C8.asm
│ │ ├── DE_E0.asm
│ │ ├── DE_E8.asm
│ │ ├── DE_F0.asm
│ │ ├── DE_F8.asm
│ │ ├── DF_00.asm
│ │ ├── DF_01.asm
│ │ ├── DF_02.asm
│ │ ├── DF_03.asm
│ │ ├── DF_05.asm
│ │ ├── DF_07.asm
│ │ ├── DF_C0.asm
│ │ ├── DF_E0.asm
│ │ ├── FST_AddrModes.asm
│ │ ├── RoundingNeg.asm
│ │ ├── RoundingPos.asm
│ │ ├── invalid_div_zero.asm
│ │ ├── invalid_fcos_infinity.asm
│ │ ├── invalid_fist_nan.asm
│ │ ├── invalid_fist_overflow.asm
│ │ ├── invalid_fist_overflow_16bit.asm
│ │ ├── invalid_fist_overflow_32bit.asm
│ │ ├── invalid_fist_overflow_64bit.asm
│ │ ├── invalid_fprem_infinity.asm
│ │ ├── invalid_fptan_infinity.asm
│ │ ├── invalid_fsin_infinity.asm
│ │ ├── invalid_fsincos_infinity.asm
│ │ ├── invalid_infinity_fsub_memory.asm
│ │ ├── invalid_infinity_fsubr_infinity.asm
│ │ ├── invalid_infinity_mul_zero.asm
│ │ ├── invalid_infinity_ops.asm
│ │ ├── invalid_infinity_sub_infinity.asm
│ │ ├── invalid_neg_infinity_sub_neg_infinity.asm
│ │ ├── invalid_reduced_precision.asm
│ │ ├── invalid_simple_test.asm
│ │ ├── invalid_sqrt_negative.asm
│ │ ├── valid_fist_16bit.asm
│ │ └── valid_operation.asm
│ ├── arpl.asm
│ └── arpl_2.asm
├── APITests/
│ ├── Allocator.cpp
│ ├── ArgumentParser.cpp
│ ├── CMakeLists.txt
│ ├── ExtendedVolatileMetadata.cpp
│ ├── FileMappingBaseAddress.cpp
│ ├── Filesystem.cpp
│ ├── InterruptableConditionVariable.cpp
│ ├── StringUtils.cpp
│ └── fextl_function.cpp
├── ASM/
│ ├── 3DNow/
│ │ ├── 0C.asm
│ │ ├── 0D.asm
│ │ ├── 0E.asm
│ │ ├── 1C.asm
│ │ ├── 1D.asm
│ │ ├── 86.asm
│ │ ├── 87.asm
│ │ ├── 8A.asm
│ │ ├── 8E.asm
│ │ ├── 90.asm
│ │ ├── 94.asm
│ │ ├── 96.asm
│ │ ├── 97.asm
│ │ ├── 9A.asm
│ │ ├── 9E.asm
│ │ ├── A0.asm
│ │ ├── A4.asm
│ │ ├── A6.asm
│ │ ├── A7.asm
│ │ ├── AA.asm
│ │ ├── AE.asm
│ │ ├── B0.asm
│ │ ├── B4.asm
│ │ ├── B6.asm
│ │ ├── B7.asm
│ │ ├── BB.asm
│ │ └── BF.asm
│ ├── Atomics/
│ │ ├── adc_atomic16.asm
│ │ ├── adc_atomic32.asm
│ │ ├── adc_atomic64.asm
│ │ ├── neg_atomic16.asm
│ │ ├── neg_atomic32.asm
│ │ ├── neg_atomic64.asm
│ │ ├── not_atomic16.asm
│ │ ├── not_atomic32.asm
│ │ ├── not_atomic64.asm
│ │ ├── sbb_atomic16.asm
│ │ ├── sbb_atomic32.asm
│ │ └── sbb_atomic64.asm
│ ├── CALL.asm
│ ├── CMakeLists.txt
│ ├── ConstProp/
│ │ └── ConstPooling.asm
│ ├── DAZTest.asm
│ ├── Disabled_Tests
│ ├── Disabled_Tests_ARMv8.0
│ ├── Disabled_Tests_ARMv8.2
│ ├── Disabled_Tests_ARMv8.4
│ ├── Disabled_Tests_Simulator
│ ├── Disabled_Tests_host
│ ├── Disabled_Tests_x64
│ ├── Displacement_Encoding.asm
│ ├── FEX_bugs/
│ │ ├── 32bit_syscall.asm
│ │ ├── 3DNow_ModRMSIBDecode.asm
│ │ ├── BEXTR_flags.asm
│ │ ├── BLSI_flags.asm
│ │ ├── BLSMSK_flags.asm
│ │ ├── BLSR_flags.asm
│ │ ├── BT_flags.asm
│ │ ├── BZHI_Sign.asm
│ │ ├── BitConditionCheck.asm
│ │ ├── Blake3.asm
│ │ ├── BranchConditionCheck.asm
│ │ ├── CodeBufferOverflow.asm
│ │ ├── Divide32.asm
│ │ ├── H0F3AREXBug.asm
│ │ ├── IMUL_garbagedata_negative.asm
│ │ ├── InitialPFFlag.asm
│ │ ├── LargeRotatesForSmallSizes.asm
│ │ ├── LargeRotatesForSmallSizes_More.asm
│ │ ├── LoadAtBoundary_LowerPrecision.asm
│ │ ├── LongSignedDivide.asm
│ │ ├── LoopAddressSizeCheck.asm
│ │ ├── MinMaxNaN.asm
│ │ ├── MoveMerging.asm
│ │ ├── NegativeCallAddressSizeOverride.asm
│ │ ├── OptSizeConfusion.asm
│ │ ├── PSRLDQBuf.asm
│ │ ├── Push.asm
│ │ ├── REX/
│ │ │ ├── 0F_38.asm
│ │ │ ├── 0F_3A.asm
│ │ │ ├── DDDNow.asm
│ │ │ ├── Primary.asm
│ │ │ ├── Primary_2.asm
│ │ │ └── TwoByte.asm
│ │ ├── RegCacheMMX.asm
│ │ ├── SBCSmall.asm
│ │ ├── SHRD_OF.asm
│ │ ├── SIBScaleTranspose.asm
│ │ ├── SegmentAddressOverride.asm
│ │ ├── SelfPop.asm
│ │ ├── ShiftConstantBug.asm
│ │ ├── ShiftPF.asm
│ │ ├── ShiftZeroFlagsUpdate.asm
│ │ ├── SmallShiftFlags.asm
│ │ ├── Test_CmpSelect_Merge.asm
│ │ ├── Test_CmpSelect_Merge_Float.asm
│ │ ├── Test_CmpSelect_Merge_Float_branch.asm
│ │ ├── Test_CmpSelect_Merge_branch.asm
│ │ ├── Test_JP.asm
│ │ ├── Test_PF_Zero_Shift.asm
│ │ ├── TrickyRA.asm
│ │ ├── UnalignedLoadStoreSIGBUS.asm
│ │ ├── VectorLoadCrash.asm
│ │ ├── VectorShift_zero.asm
│ │ ├── VectorShift_zero_256.asm
│ │ ├── VectorShift_zero_avx_128.asm
│ │ ├── X87MMXNZCV.asm
│ │ ├── XeSS_quadratic.asm
│ │ ├── adcx_size.asm
│ │ ├── add_sub_carry.asm
│ │ ├── add_sub_carry_2.asm
│ │ ├── cmpxchg.asm
│ │ ├── fnsave_fnrstor_size.asm
│ │ ├── fxrstor_bug.asm
│ │ ├── fxsave_bug.asm
│ │ ├── issue5084_crossblock_const.asm
│ │ ├── mmx_x87_register_conflating.asm
│ │ ├── mov_address_size_override.asm
│ │ ├── non_fatal_syscall.asm
│ │ ├── nzcv_implicit_clobber.asm
│ │ ├── nzcv_rmw.asm
│ │ ├── nzcv_spill_enderlilies.asm
│ │ ├── overlapping_memcpy_bug.asm
│ │ ├── pcmpestri_garbage_rcx.asm
│ │ ├── repeat_on_incdec.asm
│ │ ├── repeat_stringops_crash.asm
│ │ ├── rex_b_mmx.asm
│ │ ├── rotate_zero_extend_with_zero.asm
│ │ ├── sbbNZCVBug.asm
│ │ ├── smallvectorload_regreg.asm
│ │ ├── tls_vector_element.asm
│ │ ├── vcvtdq2ps_incorrect_size.asm
│ │ ├── vgather_xmm4.asm
│ │ ├── vmov_size_test.asm
│ │ ├── vroundscalar_sve256.asm
│ │ ├── x87DecrementStackBug.asm
│ │ ├── x87IncrementStackBug.asm
│ │ ├── x87_fprem.asm
│ │ ├── x87_integer_indefinite.asm
│ │ ├── x87_unordered_cmp_fix.asm
│ │ ├── xor_flags.asm
│ │ └── zero-ah.asm
│ ├── Flags/
│ │ └── Shift.asm
│ ├── GameTests/
│ │ └── EnderLiliesFlash.asm
│ ├── H0F38/
│ │ ├── 0_F0.asm
│ │ ├── 0_F1.asm
│ │ ├── 66_00.asm
│ │ ├── 66_00_2.asm
│ │ ├── 66_01.asm
│ │ ├── 66_02.asm
│ │ ├── 66_03.asm
│ │ ├── 66_04.asm
│ │ ├── 66_05.asm
│ │ ├── 66_06.asm
│ │ ├── 66_07.asm
│ │ ├── 66_08.asm
│ │ ├── 66_09.asm
│ │ ├── 66_0A.asm
│ │ ├── 66_0B.asm
│ │ ├── 66_10.asm
│ │ ├── 66_14.asm
│ │ ├── 66_15.asm
│ │ ├── 66_17.asm
│ │ ├── 66_17_2.asm
│ │ ├── 66_1C.asm
│ │ ├── 66_1D.asm
│ │ ├── 66_1E.asm
│ │ ├── 66_20.asm
│ │ ├── 66_21.asm
│ │ ├── 66_22.asm
│ │ ├── 66_23.asm
│ │ ├── 66_24.asm
│ │ ├── 66_25.asm
│ │ ├── 66_28.asm
│ │ ├── 66_29.asm
│ │ ├── 66_2A.asm
│ │ ├── 66_2B.asm
│ │ ├── 66_30.asm
│ │ ├── 66_31.asm
│ │ ├── 66_32.asm
│ │ ├── 66_33.asm
│ │ ├── 66_34.asm
│ │ ├── 66_35.asm
│ │ ├── 66_37.asm
│ │ ├── 66_38.asm
│ │ ├── 66_39.asm
│ │ ├── 66_3A.asm
│ │ ├── 66_3B.asm
│ │ ├── 66_3C.asm
│ │ ├── 66_3D.asm
│ │ ├── 66_3E.asm
│ │ ├── 66_3F.asm
│ │ ├── 66_40.asm
│ │ ├── 66_41.asm
│ │ ├── 66_DB.asm
│ │ ├── 66_DC.asm
│ │ ├── 66_DD.asm
│ │ ├── 66_DE.asm
│ │ ├── 66_DF.asm
│ │ ├── 66_F0.asm
│ │ ├── 66_F0_2.asm
│ │ ├── 66_F1.asm
│ │ ├── 66_F1_2.asm
│ │ ├── 66_F1_3.asm
│ │ ├── F2_F0.asm
│ │ ├── F2_F1.asm
│ │ ├── XX_00.asm
│ │ ├── XX_00_2.asm
│ │ ├── XX_01.asm
│ │ ├── XX_02.asm
│ │ ├── XX_03.asm
│ │ ├── XX_04.asm
│ │ ├── XX_05.asm
│ │ ├── XX_06.asm
│ │ ├── XX_07.asm
│ │ ├── XX_08.asm
│ │ ├── XX_09.asm
│ │ ├── XX_0A.asm
│ │ ├── XX_0B.asm
│ │ ├── XX_1C.asm
│ │ ├── XX_1D.asm
│ │ ├── XX_1E.asm
│ │ ├── adcx.asm
│ │ ├── adox.asm
│ │ ├── sha1msg1.asm
│ │ ├── sha1msg2.asm
│ │ ├── sha1nexte.asm
│ │ ├── sha256msg1.asm
│ │ ├── sha256msg2.asm
│ │ └── sha256rnds2.asm
│ ├── H0F3A/
│ │ ├── 0_66_0F.asm
│ │ ├── 0_66_21.asm
│ │ ├── 0_66_DF.asm
│ │ ├── 0_XX_0F.asm
│ │ ├── 66_08.asm
│ │ ├── 66_09.asm
│ │ ├── 66_0A.asm
│ │ ├── 66_0B.asm
│ │ ├── 66_0C.asm
│ │ ├── 66_0D.asm
│ │ ├── 66_0E.asm
│ │ ├── 66_14.asm
│ │ ├── 66_14_2.asm
│ │ ├── 66_15.asm
│ │ ├── 66_16.asm
│ │ ├── 66_16_1.asm
│ │ ├── 66_17.asm
│ │ ├── 66_20.asm
│ │ ├── 66_20_1.asm
│ │ ├── 66_22.asm
│ │ ├── 66_22_1.asm
│ │ ├── 66_22_2.asm
│ │ ├── 66_40.asm
│ │ ├── 66_40_2.asm
│ │ ├── 66_41.asm
│ │ ├── 66_41_2.asm
│ │ ├── 66_42.asm
│ │ ├── pclmulqdq.asm
│ │ ├── pcmpestri_equal_any.asm
│ │ ├── pcmpestri_equal_each.asm
│ │ ├── pcmpestri_equal_ordered.asm
│ │ ├── pcmpestri_ranges.asm
│ │ ├── pcmpestrm_equal_any.asm
│ │ ├── pcmpestrm_equal_each.asm
│ │ ├── pcmpestrm_equal_ordered.asm
│ │ ├── pcmpestrm_ranges.asm
│ │ ├── pcmpistri_equal_any.asm
│ │ ├── pcmpistri_equal_each.asm
│ │ ├── pcmpistri_equal_ordered.asm
│ │ ├── pcmpistri_ranges.asm
│ │ ├── pcmpistrm_equal_any.asm
│ │ ├── pcmpistrm_equal_each.asm
│ │ ├── pcmpistrm_equal_ordered.asm
│ │ ├── pcmpistrm_ranges.asm
│ │ └── sha1rnds4.asm
│ ├── Includes/
│ │ ├── checkprecision.mac
│ │ ├── modrm_oob_macros.mac
│ │ ├── x87cw.mac
│ │ └── xsave_macros.mac
│ ├── JMP.asm
│ ├── Known_Failures
│ ├── Known_Failures_host
│ ├── Known_Failures_jit
│ ├── MOVHPD.asm
│ ├── MemoryData.asm
│ ├── Multiblock/
│ │ └── ReachableInvalidCode.asm
│ ├── OpSize/
│ │ ├── 15_BYTE.asm
│ │ ├── 66_10.asm
│ │ ├── 66_11.asm
│ │ ├── 66_12.asm
│ │ ├── 66_13.asm
│ │ ├── 66_14.asm
│ │ ├── 66_15.asm
│ │ ├── 66_16.asm
│ │ ├── 66_17.asm
│ │ ├── 66_28.asm
│ │ ├── 66_29.asm
│ │ ├── 66_2A.asm
│ │ ├── 66_2B.asm
│ │ ├── 66_2C.asm
│ │ ├── 66_2D.asm
│ │ ├── 66_2E.asm
│ │ ├── 66_2F.asm
│ │ ├── 66_50.asm
│ │ ├── 66_51.asm
│ │ ├── 66_54.asm
│ │ ├── 66_55.asm
│ │ ├── 66_56.asm
│ │ ├── 66_57.asm
│ │ ├── 66_58.asm
│ │ ├── 66_59.asm
│ │ ├── 66_5A.asm
│ │ ├── 66_5A_1.asm
│ │ ├── 66_5B.asm
│ │ ├── 66_5B_1.asm
│ │ ├── 66_5C.asm
│ │ ├── 66_5D.asm
│ │ ├── 66_5E.asm
│ │ ├── 66_5F.asm
│ │ ├── 66_60.asm
│ │ ├── 66_61.asm
│ │ ├── 66_62.asm
│ │ ├── 66_63.asm
│ │ ├── 66_64.asm
│ │ ├── 66_65.asm
│ │ ├── 66_66.asm
│ │ ├── 66_67.asm
│ │ ├── 66_68.asm
│ │ ├── 66_69.asm
│ │ ├── 66_6A.asm
│ │ ├── 66_6B.asm
│ │ ├── 66_6C.asm
│ │ ├── 66_6D.asm
│ │ ├── 66_6E.asm
│ │ ├── 66_6F.asm
│ │ ├── 66_70.asm
│ │ ├── 66_74.asm
│ │ ├── 66_75.asm
│ │ ├── 66_76.asm
│ │ ├── 66_7C.asm
│ │ ├── 66_7D.asm
│ │ ├── 66_7E.asm
│ │ ├── 66_7F.asm
│ │ ├── 66_C2.asm
│ │ ├── 66_C4.asm
│ │ ├── 66_C4_2.asm
│ │ ├── 66_C5.asm
│ │ ├── 66_C5_2.asm
│ │ ├── 66_C6.asm
│ │ ├── 66_D0.asm
│ │ ├── 66_D1.asm
│ │ ├── 66_D2.asm
│ │ ├── 66_D3.asm
│ │ ├── 66_D4.asm
│ │ ├── 66_D5.asm
│ │ ├── 66_D6.asm
│ │ ├── 66_D7.asm
│ │ ├── 66_D8.asm
│ │ ├── 66_D9.asm
│ │ ├── 66_DA.asm
│ │ ├── 66_DB.asm
│ │ ├── 66_DC.asm
│ │ ├── 66_DD.asm
│ │ ├── 66_DE.asm
│ │ ├── 66_DF.asm
│ │ ├── 66_E0.asm
│ │ ├── 66_E1.asm
│ │ ├── 66_E2.asm
│ │ ├── 66_E3.asm
│ │ ├── 66_E4.asm
│ │ ├── 66_E5.asm
│ │ ├── 66_E6.asm
│ │ ├── 66_E6_1.asm
│ │ ├── 66_E7.asm
│ │ ├── 66_E8.asm
│ │ ├── 66_E9.asm
│ │ ├── 66_EA.asm
│ │ ├── 66_EB.asm
│ │ ├── 66_EC.asm
│ │ ├── 66_ED.asm
│ │ ├── 66_EE.asm
│ │ ├── 66_EF.asm
│ │ ├── 66_F1.asm
│ │ ├── 66_F2.asm
│ │ ├── 66_F3.asm
│ │ ├── 66_F4.asm
│ │ ├── 66_F5.asm
│ │ ├── 66_F6.asm
│ │ ├── 66_F7.asm
│ │ ├── 66_F8.asm
│ │ ├── 66_F9.asm
│ │ ├── 66_FA.asm
│ │ ├── 66_FB.asm
│ │ ├── 66_FC.asm
│ │ ├── 66_FD.asm
│ │ └── 66_FE.asm
│ ├── Primary/
│ │ ├── Pause.asm
│ │ ├── Primary_00.asm
│ │ ├── Primary_01_Atomic16.asm
│ │ ├── Primary_01_Atomic32.asm
│ │ ├── Primary_01_Atomic64.asm
│ │ ├── Primary_08.asm
│ │ ├── Primary_09_Atomic16.asm
│ │ ├── Primary_09_Atomic32.asm
│ │ ├── Primary_09_Atomic64.asm
│ │ ├── Primary_10.asm
│ │ ├── Primary_10_2.asm
│ │ ├── Primary_10_3.asm
│ │ ├── Primary_10_4.asm
│ │ ├── Primary_18.asm
│ │ ├── Primary_18_2.asm
│ │ ├── Primary_18_3.asm
│ │ ├── Primary_18_4.asm
│ │ ├── Primary_20.asm
│ │ ├── Primary_23_Atomic16.asm
│ │ ├── Primary_23_Atomic32.asm
│ │ ├── Primary_23_Atomic64.asm
│ │ ├── Primary_28.asm
│ │ ├── Primary_29_Atomic16.asm
│ │ ├── Primary_29_Atomic32.asm
│ │ ├── Primary_29_Atomic64.asm
│ │ ├── Primary_30.asm
│ │ ├── Primary_31_Atomic16.asm
│ │ ├── Primary_31_Atomic32.asm
│ │ ├── Primary_31_Atomic64.asm
│ │ ├── Primary_38.asm
│ │ ├── Primary_39.asm
│ │ ├── Primary_3A.asm
│ │ ├── Primary_3B.asm
│ │ ├── Primary_3C.asm
│ │ ├── Primary_3D.asm
│ │ ├── Primary_50.asm
│ │ ├── Primary_50_2.asm
│ │ ├── Primary_63.asm
│ │ ├── Primary_63_2.asm
│ │ ├── Primary_68.asm
│ │ ├── Primary_69.asm
│ │ ├── Primary_6A.asm
│ │ ├── Primary_6A_2.asm
│ │ ├── Primary_6B.asm
│ │ ├── Primary_84.asm
│ │ ├── Primary_84_2.asm
│ │ ├── Primary_85.asm
│ │ ├── Primary_86.asm
│ │ ├── Primary_87.asm
│ │ ├── Primary_87_2.asm
│ │ ├── Primary_87_3.asm
│ │ ├── Primary_87_Atomic16.asm
│ │ ├── Primary_87_Atomic32.asm
│ │ ├── Primary_87_Atomic64.asm
│ │ ├── Primary_8C.asm
│ │ ├── Primary_8C_2.asm
│ │ ├── Primary_8D.asm
│ │ ├── Primary_8D_2.asm
│ │ ├── Primary_90.asm
│ │ ├── Primary_90_2.asm
│ │ ├── Primary_90_3.asm
│ │ ├── Primary_90_4.asm
│ │ ├── Primary_98.asm
│ │ ├── Primary_98_2.asm
│ │ ├── Primary_99.asm
│ │ ├── Primary_99_2.asm
│ │ ├── Primary_9B.asm
│ │ ├── Primary_9C.asm
│ │ ├── Primary_9D.asm
│ │ ├── Primary_9E.asm
│ │ ├── Primary_A0.asm
│ │ ├── Primary_A2.asm
│ │ ├── Primary_A4.asm
│ │ ├── Primary_A4_REP.asm
│ │ ├── Primary_A4_REPNE.asm
│ │ ├── Primary_A4_REPNE_Down.asm
│ │ ├── Primary_A4_REPNE_many.asm
│ │ ├── Primary_A4_REP_Down.asm
│ │ ├── Primary_A4_REP_Down_Overlapping.asm
│ │ ├── Primary_A4_REP_Overlapping.asm
│ │ ├── Primary_A4_REP_many.asm
│ │ ├── Primary_A5.asm
│ │ ├── Primary_A5_REP.asm
│ │ ├── Primary_A5_REPNE.asm
│ │ ├── Primary_A5_REPNE_Down.asm
│ │ ├── Primary_A5_REP_Down.asm
│ │ ├── Primary_A5_dword.asm
│ │ ├── Primary_A5_dword_REP.asm
│ │ ├── Primary_A5_dword_REPNE.asm
│ │ ├── Primary_A5_dword_REPNE_Down.asm
│ │ ├── Primary_A5_dword_REP_Down.asm
│ │ ├── Primary_A5_qword.asm
│ │ ├── Primary_A5_qword_REP.asm
│ │ ├── Primary_A5_qword_REPNE.asm
│ │ ├── Primary_A5_qword_REPNE_Down.asm
│ │ ├── Primary_A5_qword_REP_Down.asm
│ │ ├── Primary_A6.asm
│ │ ├── Primary_A6_REP.asm
│ │ ├── Primary_A6_REPNE.asm
│ │ ├── Primary_A6_REPNE_Equal.asm
│ │ ├── Primary_A6_REP_Equal.asm
│ │ ├── Primary_A6_REP_Smaller.asm
│ │ ├── Primary_A6_REP_addrmod.asm
│ │ ├── Primary_A6_REP_down.asm
│ │ ├── Primary_A6_REP_down_Equal.asm
│ │ ├── Primary_A6_addrmod.asm
│ │ ├── Primary_A6_down.asm
│ │ ├── Primary_A7_dword.asm
│ │ ├── Primary_A7_dword_down.asm
│ │ ├── Primary_A7_qword.asm
│ │ ├── Primary_A7_qword_down.asm
│ │ ├── Primary_A7_word.asm
│ │ ├── Primary_A7_word_down.asm
│ │ ├── Primary_A8.asm
│ │ ├── Primary_A9.asm
│ │ ├── Primary_AA.asm
│ │ ├── Primary_AA_REP.asm
│ │ ├── Primary_AA_REPNE.asm
│ │ ├── Primary_AA_REPNE_down.asm
│ │ ├── Primary_AA_REP_down.asm
│ │ ├── Primary_AB_dword.asm
│ │ ├── Primary_AB_dword_REP.asm
│ │ ├── Primary_AB_dword_REPNE.asm
│ │ ├── Primary_AB_dword_REPNE_down.asm
│ │ ├── Primary_AB_dword_REP_down.asm
│ │ ├── Primary_AB_qword.asm
│ │ ├── Primary_AB_qword_REP.asm
│ │ ├── Primary_AB_qword_REPNE.asm
│ │ ├── Primary_AB_qword_REPNE_down.asm
│ │ ├── Primary_AB_qword_REP_down.asm
│ │ ├── Primary_AB_word.asm
│ │ ├── Primary_AB_word_REP.asm
│ │ ├── Primary_AB_word_REPNE.asm
│ │ ├── Primary_AB_word_REPNE_down.asm
│ │ ├── Primary_AB_word_REP_down.asm
│ │ ├── Primary_AC.asm
│ │ ├── Primary_AC_REP.asm
│ │ ├── Primary_AC_REPNE.asm
│ │ ├── Primary_AC_REPNE_down.asm
│ │ ├── Primary_AC_REP_down.asm
│ │ ├── Primary_AD_REPNE_dword.asm
│ │ ├── Primary_AD_REPNE_dword_down.asm
│ │ ├── Primary_AD_REPNE_qword.asm
│ │ ├── Primary_AD_REPNE_qword_down.asm
│ │ ├── Primary_AD_REPNE_word.asm
│ │ ├── Primary_AD_REPNE_word_down.asm
│ │ ├── Primary_AD_REP_dword.asm
│ │ ├── Primary_AD_REP_dword_down.asm
│ │ ├── Primary_AD_REP_qword.asm
│ │ ├── Primary_AD_REP_qword_down.asm
│ │ ├── Primary_AD_REP_word.asm
│ │ ├── Primary_AD_REP_word_down.asm
│ │ ├── Primary_AD_dword.asm
│ │ ├── Primary_AD_qword.asm
│ │ ├── Primary_AD_word.asm
│ │ ├── Primary_AE.asm
│ │ ├── Primary_AE_REP.asm
│ │ ├── Primary_AE_REPNE.asm
│ │ ├── Primary_AE_REPNE_down.asm
│ │ ├── Primary_AE_REP_down.asm
│ │ ├── Primary_AE_addrmod.asm
│ │ ├── Primary_AF_REP_dword.asm
│ │ ├── Primary_AF_REP_qword.asm
│ │ ├── Primary_AF_REP_word.asm
│ │ ├── Primary_B0.asm
│ │ ├── Primary_B8.asm
│ │ ├── Primary_B8_2.asm
│ │ ├── Primary_B8_3.asm
│ │ ├── Primary_C2.asm
│ │ ├── Primary_C3.asm
│ │ ├── Primary_C8.asm
│ │ ├── Primary_C8_2.asm
│ │ ├── Primary_C8_o16.asm
│ │ ├── Primary_C9.asm
│ │ ├── Primary_C9_o16.asm
│ │ ├── Primary_CF.asm
│ │ ├── Primary_D7.asm
│ │ ├── Primary_E0.asm
│ │ ├── Primary_E1.asm
│ │ ├── Primary_E2.asm
│ │ ├── Primary_E3.asm
│ │ ├── Primary_E8.asm
│ │ ├── Primary_E9.asm
│ │ ├── Primary_EB.asm
│ │ ├── Primary_F5.asm
│ │ ├── Primary_F8.asm
│ │ ├── Primary_F9.asm
│ │ ├── Primary_FC.asm
│ │ ├── Primary_FD.asm
│ │ ├── Primary_FF_0_Atomic16.asm
│ │ ├── Primary_FF_0_Atomic32.asm
│ │ ├── Primary_FF_0_Atomic64.asm
│ │ ├── Primary_FF_1_Atomic16.asm
│ │ ├── Primary_FF_1_Atomic32.asm
│ │ ├── Primary_FF_1_Atomic64.asm
│ │ ├── ROL_Flags.asm
│ │ ├── ROL_OF.asm
│ │ ├── ROR_Flags.asm
│ │ ├── ROR_OF.asm
│ │ ├── SHL.asm
│ │ └── SHR.asm
│ ├── PrimaryGroup/
│ │ ├── 1_80_00.asm
│ │ ├── 1_80_01.asm
│ │ ├── 1_80_02.asm
│ │ ├── 1_80_02_2.asm
│ │ ├── 1_80_03.asm
│ │ ├── 1_80_03_2.asm
│ │ ├── 1_80_04.asm
│ │ ├── 1_80_05.asm
│ │ ├── 1_80_06.asm
│ │ ├── 1_80_07.asm
│ │ ├── 1_81_00.asm
│ │ ├── 1_81_01.asm
│ │ ├── 1_81_02.asm
│ │ ├── 1_81_02_2.asm
│ │ ├── 1_81_03.asm
│ │ ├── 1_81_03_2.asm
│ │ ├── 1_81_04.asm
│ │ ├── 1_81_05.asm
│ │ ├── 1_81_06.asm
│ │ ├── 1_81_07.asm
│ │ ├── 1_83_00.asm
│ │ ├── 1_83_01.asm
│ │ ├── 1_83_02.asm
│ │ ├── 1_83_02_2.asm
│ │ ├── 1_83_03.asm
│ │ ├── 1_83_03_2.asm
│ │ ├── 1_83_04.asm
│ │ ├── 1_83_05.asm
│ │ ├── 1_83_06.asm
│ │ ├── 1_83_07.asm
│ │ ├── 2_C0_00.asm
│ │ ├── 2_C0_01.asm
│ │ ├── 2_C0_02.asm
│ │ ├── 2_C0_02_2.asm
│ │ ├── 2_C0_02_3.asm
│ │ ├── 2_C0_02_4.asm
│ │ ├── 2_C0_03.asm
│ │ ├── 2_C0_03_2.asm
│ │ ├── 2_C0_03_3.asm
│ │ ├── 2_C0_03_4.asm
│ │ ├── 2_C0_04.asm
│ │ ├── 2_C0_05.asm
│ │ ├── 2_C0_07.asm
│ │ ├── 2_C0_07_2.asm
│ │ ├── 2_C1_00.asm
│ │ ├── 2_C1_01.asm
│ │ ├── 2_C1_04.asm
│ │ ├── 2_C1_05.asm
│ │ ├── 2_C1_05_2.asm
│ │ ├── 2_C1_07.asm
│ │ ├── 2_D0_00.asm
│ │ ├── 2_D0_01.asm
│ │ ├── 2_D0_02.asm
│ │ ├── 2_D0_02_2.asm
│ │ ├── 2_D0_03.asm
│ │ ├── 2_D0_03_2.asm
│ │ ├── 2_D0_04.asm
│ │ ├── 2_D0_05.asm
│ │ ├── 2_D0_07.asm
│ │ ├── 2_D1_00.asm
│ │ ├── 2_D1_01.asm
│ │ ├── 2_D1_02.asm
│ │ ├── 2_D1_02_2.asm
│ │ ├── 2_D1_02_3.asm
│ │ ├── 2_D1_02_4.asm
│ │ ├── 2_D1_02_5.asm
│ │ ├── 2_D1_02_6.asm
│ │ ├── 2_D1_03.asm
│ │ ├── 2_D1_03_2.asm
│ │ ├── 2_D1_03_3.asm
│ │ ├── 2_D1_03_4.asm
│ │ ├── 2_D1_03_5.asm
│ │ ├── 2_D1_03_6.asm
│ │ ├── 2_D1_04.asm
│ │ ├── 2_D1_05.asm
│ │ ├── 2_D1_07.asm
│ │ ├── 2_D1_07_2.asm
│ │ ├── 2_D2_02.asm
│ │ ├── 2_D2_02_2.asm
│ │ ├── 2_D2_02_3.asm
│ │ ├── 2_D2_03.asm
│ │ ├── 2_D2_03_2.asm
│ │ ├── 2_D2_03_3.asm
│ │ ├── 2_D3_00.asm
│ │ ├── 2_D3_00_2.asm
│ │ ├── 2_D3_00_3.asm
│ │ ├── 2_D3_01.asm
│ │ ├── 2_D3_01_2.asm
│ │ ├── 2_D3_01_3.asm
│ │ ├── 2_D3_02.asm
│ │ ├── 2_D3_02_2.asm
│ │ ├── 2_D3_02_3.asm
│ │ ├── 2_D3_02_4.asm
│ │ ├── 2_D3_02_5.asm
│ │ ├── 2_D3_03.asm
│ │ ├── 2_D3_03_2.asm
│ │ ├── 2_D3_03_3.asm
│ │ ├── 2_D3_03_4.asm
│ │ ├── 2_D3_03_5.asm
│ │ ├── 2_D3_03_6.asm
│ │ ├── 2_D3_03_7.asm
│ │ ├── 2_D3_03_8.asm
│ │ ├── 2_D3_04.asm
│ │ ├── 2_D3_05.asm
│ │ ├── 2_D3_07.asm
│ │ ├── 2_D3_07_2.asm
│ │ ├── 3_F6_00.asm
│ │ ├── 3_F6_02.asm
│ │ ├── 3_F6_02_2.asm
│ │ ├── 3_F6_03.asm
│ │ ├── 3_F6_03_2.asm
│ │ ├── 3_F6_04.asm
│ │ ├── 3_F6_05.asm
│ │ ├── 3_F6_05_2.asm
│ │ ├── 3_F6_05_3.asm
│ │ ├── 3_F6_05_4.asm
│ │ ├── 3_F6_05_5.asm
│ │ ├── 3_F6_06.asm
│ │ ├── 3_F6_07.asm
│ │ ├── 3_F6_07_2.asm
│ │ ├── 3_F7_00.asm
│ │ ├── 3_F7_00_2.asm
│ │ ├── 3_F7_02.asm
│ │ ├── 3_F7_02_2.asm
│ │ ├── 3_F7_02_3.asm
│ │ ├── 3_F7_03.asm
│ │ ├── 3_F7_03_2.asm
│ │ ├── 3_F7_04.asm
│ │ ├── 3_F7_05.asm
│ │ ├── 3_F7_05_2.asm
│ │ ├── 3_F7_06.asm
│ │ ├── 3_F7_06_2.asm
│ │ ├── 3_F7_07.asm
│ │ ├── 3_F7_07_2.asm
│ │ ├── 4_FE_00.asm
│ │ ├── 4_FE_01.asm
│ │ ├── 5_FF_00.asm
│ │ ├── 5_FF_00_2.asm
│ │ ├── 5_FF_00_3.asm
│ │ ├── 5_FF_01.asm
│ │ ├── 5_FF_01_2.asm
│ │ ├── 5_FF_01_3.asm
│ │ ├── 5_FF_02.asm
│ │ ├── 5_FF_04.asm
│ │ ├── 5_FF_05.asm
│ │ ├── 5_FF_05_03_o32.asm
│ │ ├── 5_FF_05_03_o32_imm.asm
│ │ ├── 5_FF_05_03_o64.asm
│ │ ├── 5_FF_05_03_o64_imm.asm
│ │ ├── 5_FF_06.asm
│ │ ├── 6_C6_00.asm
│ │ └── 6_C7_00.asm
│ ├── REP/
│ │ ├── F3_10.asm
│ │ ├── F3_10_1.asm
│ │ ├── F3_11.asm
│ │ ├── F3_11_1.asm
│ │ ├── F3_12.asm
│ │ ├── F3_16.asm
│ │ ├── F3_2A.asm
│ │ ├── F3_2A_1.asm
│ │ ├── F3_2A_2.asm
│ │ ├── F3_2B.asm
│ │ ├── F3_2C.asm
│ │ ├── F3_2D.asm
│ │ ├── F3_51.asm
│ │ ├── F3_52.asm
│ │ ├── F3_52_2.asm
│ │ ├── F3_53.asm
│ │ ├── F3_58.asm
│ │ ├── F3_59.asm
│ │ ├── F3_5A.asm
│ │ ├── F3_5A_1.asm
│ │ ├── F3_5B.asm
│ │ ├── F3_5B_1.asm
│ │ ├── F3_5C.asm
│ │ ├── F3_5D.asm
│ │ ├── F3_5E.asm
│ │ ├── F3_5F.asm
│ │ ├── F3_6F.asm
│ │ ├── F3_70.asm
│ │ ├── F3_7E.asm
│ │ ├── F3_7F.asm
│ │ ├── F3_B8.asm
│ │ ├── F3_BC.asm
│ │ ├── F3_BD.asm
│ │ ├── F3_BD_2.asm
│ │ ├── F3_BD_3.asm
│ │ ├── F3_BD_4.asm
│ │ ├── F3_C2.asm
│ │ ├── F3_D6.asm
│ │ ├── F3_E6.asm
│ │ └── F3_E6_1.asm
│ ├── REPNE/
│ │ ├── F2_10.asm
│ │ ├── F2_11.asm
│ │ ├── F2_12.asm
│ │ ├── F2_2A.asm
│ │ ├── F2_2A_1.asm
│ │ ├── F2_2B.asm
│ │ ├── F2_2C.asm
│ │ ├── F2_2D.asm
│ │ ├── F2_2D_1.asm
│ │ ├── F2_51.asm
│ │ ├── F2_58.asm
│ │ ├── F2_59.asm
│ │ ├── F2_5A.asm
│ │ ├── F2_5A_1.asm
│ │ ├── F2_5C.asm
│ │ ├── F2_5D.asm
│ │ ├── F2_5E.asm
│ │ ├── F2_5F.asm
│ │ ├── F2_70.asm
│ │ ├── F2_7C.asm
│ │ ├── F2_7D.asm
│ │ ├── F2_C2.asm
│ │ ├── F2_D0.asm
│ │ ├── F2_D6.asm
│ │ ├── F2_E6.asm
│ │ ├── F2_E6_1.asm
│ │ └── F2_F0.asm
│ ├── SSE4a/
│ │ ├── extrq_imm.asm
│ │ ├── extrq_variable.asm
│ │ ├── insertq_imm.asm
│ │ └── insertq_variable.asm
│ ├── STOS.asm
│ ├── STOSQ.asm
│ ├── STOSQ2.asm
│ ├── STOSQ2_REPNE.asm
│ ├── STOSQ_REPNE.asm
│ ├── STOS_REPNE.asm
│ ├── Secondary/
│ │ ├── 07_XX_00.asm
│ │ ├── 07_XX_04.asm
│ │ ├── 08_66_04.asm
│ │ ├── 08_66_04_2.asm
│ │ ├── 08_F2_04.asm
│ │ ├── 08_F2_04_2.asm
│ │ ├── 08_F2_07.asm
│ │ ├── 08_F3_04.asm
│ │ ├── 08_F3_04_2.asm
│ │ ├── 08_XX_04.asm
│ │ ├── 08_XX_04_2.asm
│ │ ├── 08_XX_04_3.asm
│ │ ├── 08_XX_05.asm
│ │ ├── 08_XX_05_2.asm
│ │ ├── 08_XX_05_3.asm
│ │ ├── 08_XX_05_3_Atomic.asm
│ │ ├── 08_XX_05_Atomic.asm
│ │ ├── 08_XX_06.asm
│ │ ├── 08_XX_06_2.asm
│ │ ├── 08_XX_06_3.asm
│ │ ├── 08_XX_06_3_Atomic.asm
│ │ ├── 08_XX_06_Atomic.asm
│ │ ├── 08_XX_07.asm
│ │ ├── 08_XX_07_2.asm
│ │ ├── 08_XX_07_3.asm
│ │ ├── 08_XX_07_3_Atomic.asm
│ │ ├── 08_XX_07_Atomic.asm
│ │ ├── 09_F3_07.asm
│ │ ├── 09_XX_01.asm
│ │ ├── 09_XX_01_10.asm
│ │ ├── 09_XX_01_11.asm
│ │ ├── 09_XX_01_12.asm
│ │ ├── 09_XX_01_13.asm
│ │ ├── 09_XX_01_14.asm
│ │ ├── 09_XX_01_15.asm
│ │ ├── 09_XX_01_16.asm
│ │ ├── 09_XX_01_17.asm
│ │ ├── 09_XX_01_18.asm
│ │ ├── 09_XX_01_19.asm
│ │ ├── 09_XX_01_2.asm
│ │ ├── 09_XX_01_3.asm
│ │ ├── 09_XX_01_4.asm
│ │ ├── 09_XX_01_5.asm
│ │ ├── 09_XX_01_6.asm
│ │ ├── 09_XX_01_7.asm
│ │ ├── 09_XX_01_8.asm
│ │ ├── 09_XX_01_9.asm
│ │ ├── 09_XX_06.asm
│ │ ├── 09_XX_07.asm
│ │ ├── 12_66_02.asm
│ │ ├── 12_66_04.asm
│ │ ├── 12_66_06.asm
│ │ ├── 13_66_02.asm
│ │ ├── 13_66_04.asm
│ │ ├── 13_66_06.asm
│ │ ├── 14_66_02.asm
│ │ ├── 14_66_06.asm
│ │ ├── 14_66_07.asm
│ │ ├── 14_XX_02.asm
│ │ ├── 15_F3_00.asm
│ │ ├── 15_F3_01.asm
│ │ ├── 15_F3_02.asm
│ │ ├── 15_F3_02_2.asm
│ │ ├── 15_F3_03.asm
│ │ ├── 15_F3_03_2.asm
│ │ ├── 15_XX_0.asm
│ │ ├── 15_XX_5.asm
│ │ ├── 15_XX_6.asm
│ │ ├── 15_XX_7.asm
│ │ ├── 15_XX_7_2.asm
│ │ ├── CLFLUSHOPT.asm
│ │ ├── CLWB.asm
│ │ ├── Prefetch.asm
│ │ ├── shufps_optimization.asm
│ │ ├── shufps_optimization_2.asm
│ │ └── xsave/
│ │ ├── xsave.asm
│ │ ├── xsave_avx.asm
│ │ ├── xsave_avx_x87.asm
│ │ ├── xsave_sse.asm
│ │ └── xsave_x87.asm
│ ├── SecondaryModRM/
│ │ ├── Reg_2_0.asm
│ │ ├── Reg_7_1.asm
│ │ ├── Reg_7_4.asm
│ │ └── Reg_7_4_2.asm
│ ├── SelfModifyingCode/
│ │ ├── Delinking.asm
│ │ ├── DifferentBlock.asm
│ │ └── SameBlock.asm
│ ├── TwoByte/
│ │ ├── 0F_02.asm
│ │ ├── 0F_0E.asm
│ │ ├── 0F_10.asm
│ │ ├── 0F_10_2.asm
│ │ ├── 0F_11.asm
│ │ ├── 0F_12.asm
│ │ ├── 0F_13.asm
│ │ ├── 0F_13_2.asm
│ │ ├── 0F_14.asm
│ │ ├── 0F_15.asm
│ │ ├── 0F_16.asm
│ │ ├── 0F_17.asm
│ │ ├── 0F_19.asm
│ │ ├── 0F_28.asm
│ │ ├── 0F_29.asm
│ │ ├── 0F_2A.asm
│ │ ├── 0F_2B.asm
│ │ ├── 0F_2C.asm
│ │ ├── 0F_2D.asm
│ │ ├── 0F_2E.asm
│ │ ├── 0F_2F.asm
│ │ ├── 0F_31.asm
│ │ ├── 0F_40.asm
│ │ ├── 0F_41.asm
│ │ ├── 0F_42.asm
│ │ ├── 0F_43.asm
│ │ ├── 0F_44.asm
│ │ ├── 0F_45.asm
│ │ ├── 0F_46.asm
│ │ ├── 0F_47.asm
│ │ ├── 0F_48.asm
│ │ ├── 0F_49.asm
│ │ ├── 0F_4A.asm
│ │ ├── 0F_4B.asm
│ │ ├── 0F_4C.asm
│ │ ├── 0F_4D.asm
│ │ ├── 0F_4E.asm
│ │ ├── 0F_4F.asm
│ │ ├── 0F_50.asm
│ │ ├── 0F_51.asm
│ │ ├── 0F_52.asm
│ │ ├── 0F_53.asm
│ │ ├── 0F_54.asm
│ │ ├── 0F_55.asm
│ │ ├── 0F_56.asm
│ │ ├── 0F_57.asm
│ │ ├── 0F_58.asm
│ │ ├── 0F_59.asm
│ │ ├── 0F_5A.asm
│ │ ├── 0F_5A_1.asm
│ │ ├── 0F_5B.asm
│ │ ├── 0F_5B_1.asm
│ │ ├── 0F_5C.asm
│ │ ├── 0F_5D.asm
│ │ ├── 0F_5E.asm
│ │ ├── 0F_5F.asm
│ │ ├── 0F_60.asm
│ │ ├── 0F_61.asm
│ │ ├── 0F_62.asm
│ │ ├── 0F_63.asm
│ │ ├── 0F_64.asm
│ │ ├── 0F_65.asm
│ │ ├── 0F_66.asm
│ │ ├── 0F_67.asm
│ │ ├── 0F_68.asm
│ │ ├── 0F_69.asm
│ │ ├── 0F_6A.asm
│ │ ├── 0F_6B.asm
│ │ ├── 0F_6E.asm
│ │ ├── 0F_6E_2.asm
│ │ ├── 0F_6F.asm
│ │ ├── 0F_70.asm
│ │ ├── 0F_74.asm
│ │ ├── 0F_75.asm
│ │ ├── 0F_76.asm
│ │ ├── 0F_77.asm
│ │ ├── 0F_7E.asm
│ │ ├── 0F_7F.asm
│ │ ├── 0F_80.asm
│ │ ├── 0F_81.asm
│ │ ├── 0F_82.asm
│ │ ├── 0F_83.asm
│ │ ├── 0F_84.asm
│ │ ├── 0F_85.asm
│ │ ├── 0F_86.asm
│ │ ├── 0F_87.asm
│ │ ├── 0F_88.asm
│ │ ├── 0F_89.asm
│ │ ├── 0F_8A.asm
│ │ ├── 0F_8B.asm
│ │ ├── 0F_8B_16.asm
│ │ ├── 0F_8B_32.asm
│ │ ├── 0F_8B_64.asm
│ │ ├── 0F_8C.asm
│ │ ├── 0F_8D.asm
│ │ ├── 0F_8E.asm
│ │ ├── 0F_8F.asm
│ │ ├── 0F_90.asm
│ │ ├── 0F_91.asm
│ │ ├── 0F_92.asm
│ │ ├── 0F_93.asm
│ │ ├── 0F_94.asm
│ │ ├── 0F_95.asm
│ │ ├── 0F_96.asm
│ │ ├── 0F_97.asm
│ │ ├── 0F_98.asm
│ │ ├── 0F_99.asm
│ │ ├── 0F_9A.asm
│ │ ├── 0F_9B.asm
│ │ ├── 0F_9C.asm
│ │ ├── 0F_9D.asm
│ │ ├── 0F_9E.asm
│ │ ├── 0F_9F.asm
│ │ ├── 0F_A2.asm
│ │ ├── 0F_A3.asm
│ │ ├── 0F_A3_2.asm
│ │ ├── 0F_A4.asm
│ │ ├── 0F_A4_2.asm
│ │ ├── 0F_A5.asm
│ │ ├── 0F_A5_2.asm
│ │ ├── 0F_A5_3.asm
│ │ ├── 0F_A5_4.asm
│ │ ├── 0F_A5_5.asm
│ │ ├── 0F_A5_6.asm
│ │ ├── 0F_A5_7.asm
│ │ ├── 0F_AB.asm
│ │ ├── 0F_AB_2.asm
│ │ ├── 0F_AB_2_Atomic.asm
│ │ ├── 0F_AB_Atomic.asm
│ │ ├── 0F_AC.asm
│ │ ├── 0F_AC_2.asm
│ │ ├── 0F_AD.asm
│ │ ├── 0F_AD_2.asm
│ │ ├── 0F_AD_3.asm
│ │ ├── 0F_AD_4.asm
│ │ ├── 0F_AD_5.asm
│ │ ├── 0F_AD_6.asm
│ │ ├── 0F_AD_7.asm
│ │ ├── 0F_AF.asm
│ │ ├── 0F_AF_2.asm
│ │ ├── 0F_B0.asm
│ │ ├── 0F_B0_10.asm
│ │ ├── 0F_B0_11.asm
│ │ ├── 0F_B0_2.asm
│ │ ├── 0F_B0_3.asm
│ │ ├── 0F_B0_4.asm
│ │ ├── 0F_B0_5.asm
│ │ ├── 0F_B0_6.asm
│ │ ├── 0F_B0_7.asm
│ │ ├── 0F_B0_8.asm
│ │ ├── 0F_B0_9.asm
│ │ ├── 0F_B3.asm
│ │ ├── 0F_B3_2.asm
│ │ ├── 0F_B3_2_Atomic.asm
│ │ ├── 0F_B3_Atomic.asm
│ │ ├── 0F_B6.asm
│ │ ├── 0F_B7.asm
│ │ ├── 0F_BB.asm
│ │ ├── 0F_BB_2.asm
│ │ ├── 0F_BB_2_Atomic.asm
│ │ ├── 0F_BB_Atomic.asm
│ │ ├── 0F_BC.asm
│ │ ├── 0F_BD.asm
│ │ ├── 0F_BE.asm
│ │ ├── 0F_BF.asm
│ │ ├── 0F_C0.asm
│ │ ├── 0F_C0_2.asm
│ │ ├── 0F_C0_Atomic16.asm
│ │ ├── 0F_C0_Atomic32.asm
│ │ ├── 0F_C0_Atomic64.asm
│ │ ├── 0F_C2.asm
│ │ ├── 0F_C3.asm
│ │ ├── 0F_C4.asm
│ │ ├── 0F_C4_2.asm
│ │ ├── 0F_C5.asm
│ │ ├── 0F_C5_2.asm
│ │ ├── 0F_C6.asm
│ │ ├── 0F_D1.asm
│ │ ├── 0F_D2.asm
│ │ ├── 0F_D3.asm
│ │ ├── 0F_D4.asm
│ │ ├── 0F_D5.asm
│ │ ├── 0F_D7.asm
│ │ ├── 0F_D8.asm
│ │ ├── 0F_D9.asm
│ │ ├── 0F_DA.asm
│ │ ├── 0F_DB.asm
│ │ ├── 0F_DC.asm
│ │ ├── 0F_DD.asm
│ │ ├── 0F_DE.asm
│ │ ├── 0F_DF.asm
│ │ ├── 0F_E0.asm
│ │ ├── 0F_E1.asm
│ │ ├── 0F_E2.asm
│ │ ├── 0F_E3.asm
│ │ ├── 0F_E4.asm
│ │ ├── 0F_E5.asm
│ │ ├── 0F_E7.asm
│ │ ├── 0F_E8.asm
│ │ ├── 0F_E9.asm
│ │ ├── 0F_EA.asm
│ │ ├── 0F_EB.asm
│ │ ├── 0F_EC.asm
│ │ ├── 0F_ED.asm
│ │ ├── 0F_EE.asm
│ │ ├── 0F_EF.asm
│ │ ├── 0F_F1.asm
│ │ ├── 0F_F2.asm
│ │ ├── 0F_F3.asm
│ │ ├── 0F_F4.asm
│ │ ├── 0F_F5.asm
│ │ ├── 0F_F6.asm
│ │ ├── 0F_F6_2.asm
│ │ ├── 0F_F7.asm
│ │ ├── 0F_F8.asm
│ │ ├── 0F_F9.asm
│ │ ├── 0F_FA.asm
│ │ ├── 0F_FB.asm
│ │ ├── 0F_FC.asm
│ │ ├── 0F_FD.asm
│ │ └── 0F_FE.asm
│ ├── VEX/
│ │ ├── andn.asm
│ │ ├── bextr.asm
│ │ ├── blsi.asm
│ │ ├── blsmsk.asm
│ │ ├── blsr.asm
│ │ ├── bzhi.asm
│ │ ├── fma_fmadd_pd.asm
│ │ ├── fma_fmadd_ps.asm
│ │ ├── fma_fmadd_sd.asm
│ │ ├── fma_fmadd_ss.asm
│ │ ├── fma_fmaddsub_pd.asm
│ │ ├── fma_fmaddsub_ps.asm
│ │ ├── fma_fmsub_pd.asm
│ │ ├── fma_fmsub_ps.asm
│ │ ├── fma_fmsub_sd.asm
│ │ ├── fma_fmsub_ss.asm
│ │ ├── fma_fmsubadd_pd.asm
│ │ ├── fma_fmsubadd_ps.asm
│ │ ├── fma_fnmadd_pd.asm
│ │ ├── fma_fnmadd_ps.asm
│ │ ├── fma_fnmadd_sd.asm
│ │ ├── fma_fnmadd_ss.asm
│ │ ├── fma_fnmsub_pd.asm
│ │ ├── fma_fnmsub_ps.asm
│ │ ├── fma_fnmsub_sd.asm
│ │ ├── fma_fnmsub_ss.asm
│ │ ├── full_vpermq_imm.asm
│ │ ├── mulx.asm
│ │ ├── pdep.asm
│ │ ├── pext.asm
│ │ ├── rorx.asm
│ │ ├── sarx.asm
│ │ ├── shlx.asm
│ │ ├── shrx.asm
│ │ ├── vaddpd.asm
│ │ ├── vaddps.asm
│ │ ├── vaddsd.asm
│ │ ├── vaddss.asm
│ │ ├── vaddsubpd.asm
│ │ ├── vaddsubps.asm
│ │ ├── vaesdec.asm
│ │ ├── vaesdec256.asm
│ │ ├── vaesdeclast.asm
│ │ ├── vaesdeclast256.asm
│ │ ├── vaesenc.asm
│ │ ├── vaesenc256.asm
│ │ ├── vaesenclast.asm
│ │ ├── vaesenclast256.asm
│ │ ├── vaesimc.asm
│ │ ├── vaeskeygenassist.asm
│ │ ├── vandnpd.asm
│ │ ├── vandnps.asm
│ │ ├── vandpd.asm
│ │ ├── vandps.asm
│ │ ├── vblendpd.asm
│ │ ├── vblendps.asm
│ │ ├── vblendvpd.asm
│ │ ├── vblendvps.asm
│ │ ├── vbroadcastf128.asm
│ │ ├── vbroadcasti128.asm
│ │ ├── vbroadcastsd.asm
│ │ ├── vbroadcastss.asm
│ │ ├── vcmppd.asm
│ │ ├── vcmppd_256.asm
│ │ ├── vcmppd_full.asm
│ │ ├── vcmpps.asm
│ │ ├── vcmpps_256.asm
│ │ ├── vcmpps_full.asm
│ │ ├── vcmpsd.asm
│ │ ├── vcmpsd_full.asm
│ │ ├── vcmpss.asm
│ │ ├── vcmpss_full.asm
│ │ ├── vcomisd.asm
│ │ ├── vcomiss.asm
│ │ ├── vcvtdq2pd.asm
│ │ ├── vcvtdq2ps.asm
│ │ ├── vcvtpd2dq.asm
│ │ ├── vcvtpd2dq_inexact.asm
│ │ ├── vcvtpd2ps.asm
│ │ ├── vcvtph2ps.asm
│ │ ├── vcvtps2dq.asm
│ │ ├── vcvtps2dq_inexact.asm
│ │ ├── vcvtps2pd.asm
│ │ ├── vcvtps2ph_rd.asm
│ │ ├── vcvtps2ph_rd_mxcsr.asm
│ │ ├── vcvtps2ph_rtne.asm
│ │ ├── vcvtps2ph_rtne_mxcsr.asm
│ │ ├── vcvtps2ph_ru.asm
│ │ ├── vcvtps2ph_ru_mxcsr.asm
│ │ ├── vcvtps2ph_trunc.asm
│ │ ├── vcvtps2ph_trunc_mxcsr.asm
│ │ ├── vcvtsd2si.asm
│ │ ├── vcvtsd2ss.asm
│ │ ├── vcvtsi2sd.asm
│ │ ├── vcvtsi2ss.asm
│ │ ├── vcvtss2sd.asm
│ │ ├── vcvtss2si.asm
│ │ ├── vcvttpd2dq.asm
│ │ ├── vcvttps2dq.asm
│ │ ├── vcvttsd2si.asm
│ │ ├── vcvttss2si.asm
│ │ ├── vdivpd.asm
│ │ ├── vdivps.asm
│ │ ├── vdivsd.asm
│ │ ├── vdivss.asm
│ │ ├── vdppd.asm
│ │ ├── vdpps_128.asm
│ │ ├── vdpps_256.asm
│ │ ├── vextractf128.asm
│ │ ├── vextracti128.asm
│ │ ├── vextractps.asm
│ │ ├── vgather_dpd_128bit_1xdisp.asm
│ │ ├── vgather_dpd_128bit_2xdisp.asm
│ │ ├── vgather_dpd_128bit_4xdisp.asm
│ │ ├── vgather_dpd_128bit_8xdisp.asm
│ │ ├── vgather_dpd_256bit_1xdisp.asm
│ │ ├── vgather_dpd_256bit_2xdisp.asm
│ │ ├── vgather_dpd_256bit_4xdisp.asm
│ │ ├── vgather_dpd_256bit_8xdisp.asm
│ │ ├── vgather_dps_128bit_1xdisp.asm
│ │ ├── vgather_dps_128bit_2xdisp.asm
│ │ ├── vgather_dps_128bit_4xdisp.asm
│ │ ├── vgather_dps_128bit_8xdisp.asm
│ │ ├── vgather_dps_256bit_1xdisp.asm
│ │ ├── vgather_dps_256bit_2xdisp.asm
│ │ ├── vgather_dps_256bit_4xdisp.asm
│ │ ├── vgather_dps_256bit_8xdisp.asm
│ │ ├── vgather_qpd_128bit_1xdisp.asm
│ │ ├── vgather_qpd_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_2xdisp.asm
│ │ ├── vgather_qpd_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_4xdisp.asm
│ │ ├── vgather_qpd_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_128bit_8xdisp.asm
│ │ ├── vgather_qpd_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_1xdisp.asm
│ │ ├── vgather_qpd_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_2xdisp.asm
│ │ ├── vgather_qpd_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_4xdisp.asm
│ │ ├── vgather_qpd_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qpd_256bit_8xdisp.asm
│ │ ├── vgather_qpd_256bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_1xdisp.asm
│ │ ├── vgather_qps_128bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_2xdisp.asm
│ │ ├── vgather_qps_128bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_4xdisp.asm
│ │ ├── vgather_qps_128bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_128bit_8xdisp.asm
│ │ ├── vgather_qps_128bit_8xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_1xdisp.asm
│ │ ├── vgather_qps_256bit_1xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_2xdisp.asm
│ │ ├── vgather_qps_256bit_2xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_4xdisp.asm
│ │ ├── vgather_qps_256bit_4xdisp_overflow.asm
│ │ ├── vgather_qps_256bit_8xdisp.asm
│ │ ├── vgather_qps_256bit_8xdisp_overflow.asm
│ │ ├── vhaddpd.asm
│ │ ├── vhaddps.asm
│ │ ├── vhsubpd.asm
│ │ ├── vhsubps.asm
│ │ ├── vinsertf128.asm
│ │ ├── vinserti128.asm
│ │ ├── vinsertps.asm
│ │ ├── vlddqu.asm
│ │ ├── vldmxcsr.asm
│ │ ├── vmaskmovdqu.asm
│ │ ├── vmaskmovpd_load.asm
│ │ ├── vmaskmovpd_store.asm
│ │ ├── vmaskmovps_load.asm
│ │ ├── vmaskmovps_store.asm
│ │ ├── vmaxpd.asm
│ │ ├── vmaxps.asm
│ │ ├── vmaxsd.asm
│ │ ├── vmaxss.asm
│ │ ├── vminpd.asm
│ │ ├── vminps.asm
│ │ ├── vminsd.asm
│ │ ├── vminss.asm
│ │ ├── vmovapd.asm
│ │ ├── vmovapd_mem.asm
│ │ ├── vmovaps.asm
│ │ ├── vmovaps_mem.asm
│ │ ├── vmovddup.asm
│ │ ├── vmovdqa.asm
│ │ ├── vmovdqu.asm
│ │ ├── vmovhlps.asm
│ │ ├── vmovhpd.asm
│ │ ├── vmovhps.asm
│ │ ├── vmovlhps.asm
│ │ ├── vmovlpd.asm
│ │ ├── vmovlps.asm
│ │ ├── vmovmskpd.asm
│ │ ├── vmovmskps.asm
│ │ ├── vmovntdq.asm
│ │ ├── vmovntdqa.asm
│ │ ├── vmovntpd.asm
│ │ ├── vmovntps.asm
│ │ ├── vmovq.asm
│ │ ├── vmovq_vmovd_reg.asm
│ │ ├── vmovsd_from_mem.asm
│ │ ├── vmovsd_to_mem.asm
│ │ ├── vmovsd_vectors.asm
│ │ ├── vmovshdup.asm
│ │ ├── vmovsldup.asm
│ │ ├── vmovss_from_mem.asm
│ │ ├── vmovss_to_mem.asm
│ │ ├── vmovss_vectors.asm
│ │ ├── vmovupd.asm
│ │ ├── vmovupd_mem.asm
│ │ ├── vmovups.asm
│ │ ├── vmovups_mem.asm
│ │ ├── vmpsadbw_128.asm
│ │ ├── vmpsadbw_256.asm
│ │ ├── vmulpd.asm
│ │ ├── vmulps.asm
│ │ ├── vmulsd.asm
│ │ ├── vmulss.asm
│ │ ├── vorpd.asm
│ │ ├── vorps.asm
│ │ ├── vpabsb.asm
│ │ ├── vpabsd.asm
│ │ ├── vpabsw.asm
│ │ ├── vpackssdw.asm
│ │ ├── vpacksswb.asm
│ │ ├── vpackusdw.asm
│ │ ├── vpackuswb.asm
│ │ ├── vpaddb.asm
│ │ ├── vpaddd.asm
│ │ ├── vpaddq.asm
│ │ ├── vpaddsb.asm
│ │ ├── vpaddsw.asm
│ │ ├── vpaddusb.asm
│ │ ├── vpaddusw.asm
│ │ ├── vpaddw.asm
│ │ ├── vpalignr.asm
│ │ ├── vpand.asm
│ │ ├── vpandn.asm
│ │ ├── vpavgb.asm
│ │ ├── vpavgb_aliasing.asm
│ │ ├── vpavgw.asm
│ │ ├── vpavgw_aliasing.asm
│ │ ├── vpblendd.asm
│ │ ├── vpblendvb.asm
│ │ ├── vpblendw.asm
│ │ ├── vpbroadcastb.asm
│ │ ├── vpbroadcastd.asm
│ │ ├── vpbroadcastq.asm
│ │ ├── vpbroadcastw.asm
│ │ ├── vpclmulqdq.asm
│ │ ├── vpclmulqdq_256.asm
│ │ ├── vpcmpeqb.asm
│ │ ├── vpcmpeqd.asm
│ │ ├── vpcmpeqq.asm
│ │ ├── vpcmpeqw.asm
│ │ ├── vpcmpestri_equal_any.asm
│ │ ├── vpcmpestri_equal_each.asm
│ │ ├── vpcmpestri_equal_ordered.asm
│ │ ├── vpcmpestri_ranges.asm
│ │ ├── vpcmpestrm_equal_any.asm
│ │ ├── vpcmpestrm_equal_each.asm
│ │ ├── vpcmpestrm_equal_ordered.asm
│ │ ├── vpcmpestrm_ranges.asm
│ │ ├── vpcmpgtb.asm
│ │ ├── vpcmpgtd.asm
│ │ ├── vpcmpgtq.asm
│ │ ├── vpcmpgtw.asm
│ │ ├── vpcmpistri_equal_any.asm
│ │ ├── vpcmpistri_equal_each.asm
│ │ ├── vpcmpistri_equal_ordered.asm
│ │ ├── vpcmpistri_ranges.asm
│ │ ├── vpcmpistrm_equal_any.asm
│ │ ├── vpcmpistrm_equal_each.asm
│ │ ├── vpcmpistrm_equal_ordered.asm
│ │ ├── vpcmpistrm_ranges.asm
│ │ ├── vperm2f128.asm
│ │ ├── vperm2i128.asm
│ │ ├── vpermd.asm
│ │ ├── vpermilpd_imm.asm
│ │ ├── vpermilpd_reg.asm
│ │ ├── vpermilps_imm.asm
│ │ ├── vpermilps_reg.asm
│ │ ├── vpermpd.asm
│ │ ├── vpermps.asm
│ │ ├── vpermq.asm
│ │ ├── vpextrb.asm
│ │ ├── vpextrd.asm
│ │ ├── vpextrq.asm
│ │ ├── vpextrw.asm
│ │ ├── vpgather_dd_128bit_1xdisp.asm
│ │ ├── vpgather_dd_128bit_2xdisp.asm
│ │ ├── vpgather_dd_128bit_4xdisp.asm
│ │ ├── vpgather_dd_128bit_8xdisp.asm
│ │ ├── vpgather_dd_256bit_1xdisp.asm
│ │ ├── vpgather_dd_256bit_2xdisp.asm
│ │ ├── vpgather_dd_256bit_4xdisp.asm
│ │ ├── vpgather_dd_256bit_8xdisp.asm
│ │ ├── vpgather_dq_128bit_1xdisp.asm
│ │ ├── vpgather_dq_128bit_2xdisp.asm
│ │ ├── vpgather_dq_128bit_4xdisp.asm
│ │ ├── vpgather_dq_128bit_8xdisp.asm
│ │ ├── vpgather_dq_256bit_1xdisp.asm
│ │ ├── vpgather_dq_256bit_2xdisp.asm
│ │ ├── vpgather_dq_256bit_4xdisp.asm
│ │ ├── vpgather_dq_256bit_8xdisp.asm
│ │ ├── vpgather_qd_128bit_1xdisp.asm
│ │ ├── vpgather_qd_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_2xdisp.asm
│ │ ├── vpgather_qd_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_4xdisp.asm
│ │ ├── vpgather_qd_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_128bit_8xdisp.asm
│ │ ├── vpgather_qd_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_1xdisp.asm
│ │ ├── vpgather_qd_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_2xdisp.asm
│ │ ├── vpgather_qd_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_4xdisp.asm
│ │ ├── vpgather_qd_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qd_256bit_8xdisp.asm
│ │ ├── vpgather_qd_256bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_1xdisp.asm
│ │ ├── vpgather_qq_128bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_2xdisp.asm
│ │ ├── vpgather_qq_128bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_4xdisp.asm
│ │ ├── vpgather_qq_128bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_128bit_8xdisp.asm
│ │ ├── vpgather_qq_128bit_8xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_1xdisp.asm
│ │ ├── vpgather_qq_256bit_1xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_2xdisp.asm
│ │ ├── vpgather_qq_256bit_2xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_4xdisp.asm
│ │ ├── vpgather_qq_256bit_4xdisp_overflow.asm
│ │ ├── vpgather_qq_256bit_8xdisp.asm
│ │ ├── vpgather_qq_256bit_8xdisp_overflow.asm
│ │ ├── vphaddd.asm
│ │ ├── vphaddsw.asm
│ │ ├── vphaddsw_256.asm
│ │ ├── vphaddw.asm
│ │ ├── vphminposuw.asm
│ │ ├── vphsubd.asm
│ │ ├── vphsubsw.asm
│ │ ├── vphsubsw_256.asm
│ │ ├── vphsubw.asm
│ │ ├── vpinsrb.asm
│ │ ├── vpinsrd.asm
│ │ ├── vpinsrq.asm
│ │ ├── vpinsrw.asm
│ │ ├── vpmaddubsw.asm
│ │ ├── vpmaddubsw_256.asm
│ │ ├── vpmaddwd.asm
│ │ ├── vpmaskmovd_load.asm
│ │ ├── vpmaskmovd_store.asm
│ │ ├── vpmaskmovq_load.asm
│ │ ├── vpmaskmovq_store.asm
│ │ ├── vpmaxsb.asm
│ │ ├── vpmaxsd.asm
│ │ ├── vpmaxsw.asm
│ │ ├── vpmaxub.asm
│ │ ├── vpmaxud.asm
│ │ ├── vpmaxuw.asm
│ │ ├── vpminsb.asm
│ │ ├── vpminsd.asm
│ │ ├── vpminsw.asm
│ │ ├── vpminub.asm
│ │ ├── vpminud.asm
│ │ ├── vpminuw.asm
│ │ ├── vpmovmskb.asm
│ │ ├── vpmovsxbd.asm
│ │ ├── vpmovsxbq.asm
│ │ ├── vpmovsxbw.asm
│ │ ├── vpmovsxdq.asm
│ │ ├── vpmovsxwd.asm
│ │ ├── vpmovsxwq.asm
│ │ ├── vpmovzxbd.asm
│ │ ├── vpmovzxbq.asm
│ │ ├── vpmovzxbw.asm
│ │ ├── vpmovzxdq.asm
│ │ ├── vpmovzxwd.asm
│ │ ├── vpmovzxwq.asm
│ │ ├── vpmuldq.asm
│ │ ├── vpmuldq_256.asm
│ │ ├── vpmulhrsw.asm
│ │ ├── vpmulhuw.asm
│ │ ├── vpmulhw.asm
│ │ ├── vpmulld.asm
│ │ ├── vpmullw.asm
│ │ ├── vpmuludq.asm
│ │ ├── vpor.asm
│ │ ├── vpsadbw.asm
│ │ ├── vpsadbw_256.asm
│ │ ├── vpshufb.asm
│ │ ├── vpshufd.asm
│ │ ├── vpshufhw.asm
│ │ ├── vpshuflw.asm
│ │ ├── vpsignb.asm
│ │ ├── vpsignd.asm
│ │ ├── vpsignw.asm
│ │ ├── vpslld.asm
│ │ ├── vpslld_imm.asm
│ │ ├── vpslldq.asm
│ │ ├── vpsllq.asm
│ │ ├── vpsllq_imm.asm
│ │ ├── vpsllvd.asm
│ │ ├── vpsllvq.asm
│ │ ├── vpsllw.asm
│ │ ├── vpsllw_imm.asm
│ │ ├── vpsrad.asm
│ │ ├── vpsrad_imm.asm
│ │ ├── vpsravd.asm
│ │ ├── vpsraw.asm
│ │ ├── vpsraw_imm.asm
│ │ ├── vpsrld.asm
│ │ ├── vpsrld_imm.asm
│ │ ├── vpsrldq.asm
│ │ ├── vpsrlq.asm
│ │ ├── vpsrlq_imm.asm
│ │ ├── vpsrlvd.asm
│ │ ├── vpsrlvq.asm
│ │ ├── vpsrlw.asm
│ │ ├── vpsrlw_imm.asm
│ │ ├── vpsubb.asm
│ │ ├── vpsubd.asm
│ │ ├── vpsubq.asm
│ │ ├── vpsubsb.asm
│ │ ├── vpsubsw.asm
│ │ ├── vpsubusb.asm
│ │ ├── vpsubusw.asm
│ │ ├── vpsubw.asm
│ │ ├── vptest.asm
│ │ ├── vpunpckhbw.asm
│ │ ├── vpunpckhdq.asm
│ │ ├── vpunpckhqdq.asm
│ │ ├── vpunpckhwd.asm
│ │ ├── vpunpcklbw.asm
│ │ ├── vpunpckldq.asm
│ │ ├── vpunpcklqdq.asm
│ │ ├── vpunpcklwd.asm
│ │ ├── vpxor.asm
│ │ ├── vrcpps.asm
│ │ ├── vrcpss.asm
│ │ ├── vroundpd.asm
│ │ ├── vroundps.asm
│ │ ├── vroundsd.asm
│ │ ├── vroundss.asm
│ │ ├── vrsqrtps.asm
│ │ ├── vrsqrtss.asm
│ │ ├── vshufpd.asm
│ │ ├── vshufps.asm
│ │ ├── vsqrtpd.asm
│ │ ├── vsqrtps.asm
│ │ ├── vsqrtsd.asm
│ │ ├── vsqrtss.asm
│ │ ├── vsubpd.asm
│ │ ├── vsubps.asm
│ │ ├── vsubsd.asm
│ │ ├── vsubss.asm
│ │ ├── vtestpd.asm
│ │ ├── vtestps.asm
│ │ ├── vucomisd.asm
│ │ ├── vucomiss.asm
│ │ ├── vunpckhpd.asm
│ │ ├── vunpckhps.asm
│ │ ├── vunpcklpd.asm
│ │ ├── vunpcklps.asm
│ │ ├── vxorpd.asm
│ │ ├── vxorps.asm
│ │ ├── vzeroall.asm
│ │ └── vzeroupper.asm
│ ├── X87/
│ │ ├── D8_00.asm
│ │ ├── D8_01.asm
│ │ ├── D8_04.asm
│ │ ├── D8_05.asm
│ │ ├── D8_06.asm
│ │ ├── D8_07.asm
│ │ ├── D8_C0.asm
│ │ ├── D8_C8.asm
│ │ ├── D8_D0.asm
│ │ ├── D8_D9.asm
│ │ ├── D8_E0.asm
│ │ ├── D8_E8.asm
│ │ ├── D8_F0.asm
│ │ ├── D8_F0_2.asm
│ │ ├── D8_F8.asm
│ │ ├── D9_00.asm
│ │ ├── D9_02.asm
│ │ ├── D9_03.asm
│ │ ├── D9_05.asm
│ │ ├── D9_06.asm
│ │ ├── D9_06_2.asm
│ │ ├── D9_07.asm
│ │ ├── D9_C0.asm
│ │ ├── D9_C8.asm
│ │ ├── D9_D0.asm
│ │ ├── D9_E0.asm
│ │ ├── D9_E1.asm
│ │ ├── D9_E4.asm
│ │ ├── D9_E8.asm
│ │ ├── D9_E9.asm
│ │ ├── D9_EA.asm
│ │ ├── D9_EB.asm
│ │ ├── D9_EC.asm
│ │ ├── D9_ED.asm
│ │ ├── D9_EE.asm
│ │ ├── D9_F0.asm
│ │ ├── D9_F1.asm
│ │ ├── D9_F2.asm
│ │ ├── D9_F3.asm
│ │ ├── D9_F4.asm
│ │ ├── D9_F4_02.asm
│ │ ├── D9_F5.asm
│ │ ├── D9_F5_2.asm
│ │ ├── D9_F5_3.asm
│ │ ├── D9_F6.asm
│ │ ├── D9_F7.asm
│ │ ├── D9_F8.asm
│ │ ├── D9_F9.asm
│ │ ├── D9_FA.asm
│ │ ├── D9_FB.asm
│ │ ├── D9_FC.asm
│ │ ├── D9_FD.asm
│ │ ├── D9_FD_2.asm
│ │ ├── D9_FE.asm
│ │ ├── D9_FF.asm
│ │ ├── DA_00.asm
│ │ ├── DA_01.asm
│ │ ├── DA_02.asm
│ │ ├── DA_04.asm
│ │ ├── DA_05.asm
│ │ ├── DA_06.asm
│ │ ├── DA_07.asm
│ │ ├── DA_C0.asm
│ │ ├── DA_C8.asm
│ │ ├── DA_D0.asm
│ │ ├── DA_D8.asm
│ │ ├── DA_D9.asm
│ │ ├── DA_E9.asm
│ │ ├── DB_00.asm
│ │ ├── DB_01.asm
│ │ ├── DB_02.asm
│ │ ├── DB_03.asm
│ │ ├── DB_05.asm
│ │ ├── DB_07.asm
│ │ ├── DB_07_2.asm
│ │ ├── DB_C0.asm
│ │ ├── DB_C8.asm
│ │ ├── DB_D0.asm
│ │ ├── DB_D8.asm
│ │ ├── DB_E2.asm
│ │ ├── DB_E3.asm
│ │ ├── DB_E3_2.asm
│ │ ├── DB_E8.asm
│ │ ├── DB_F0.asm
│ │ ├── DC_00.asm
│ │ ├── DC_01.asm
│ │ ├── DC_04.asm
│ │ ├── DC_05.asm
│ │ ├── DC_06.asm
│ │ ├── DC_07.asm
│ │ ├── DC_C0.asm
│ │ ├── DC_C8.asm
│ │ ├── DC_D0.asm
│ │ ├── DC_D9.asm
│ │ ├── DC_E0.asm
│ │ ├── DC_E8.asm
│ │ ├── DC_F0.asm
│ │ ├── DC_F8.asm
│ │ ├── DD_00.asm
│ │ ├── DD_01.asm
│ │ ├── DD_02.asm
│ │ ├── DD_03.asm
│ │ ├── DD_04.asm
│ │ ├── DD_04_2.asm
│ │ ├── DD_07.asm
│ │ ├── DD_C0.asm
│ │ ├── DD_C8.asm
│ │ ├── DD_D0.asm
│ │ ├── DD_D0_2.asm
│ │ ├── DD_D8.asm
│ │ ├── DD_E9.asm
│ │ ├── DE_00.asm
│ │ ├── DE_01.asm
│ │ ├── DE_02.asm
│ │ ├── DE_04.asm
│ │ ├── DE_05.asm
│ │ ├── DE_06.asm
│ │ ├── DE_07.asm
│ │ ├── DE_C0.asm
│ │ ├── DE_C8.asm
│ │ ├── DE_D0.asm
│ │ ├── DE_E0.asm
│ │ ├── DE_E8.asm
│ │ ├── DE_F0.asm
│ │ ├── DE_F8.asm
│ │ ├── DF_00.asm
│ │ ├── DF_01.asm
│ │ ├── DF_02.asm
│ │ ├── DF_03.asm
│ │ ├── DF_04.asm
│ │ ├── DF_05.asm
│ │ ├── DF_07.asm
│ │ ├── DF_C0.asm
│ │ ├── DF_C8.asm
│ │ ├── DF_D0.asm
│ │ ├── DF_D8.asm
│ │ ├── DF_E0.asm
│ │ ├── DF_E8.asm
│ │ ├── DF_F0.asm
│ │ ├── FISTTP_16bit.asm
│ │ ├── FISTTP_16bit_neg.asm
│ │ ├── FISTTP_32bit.asm
│ │ ├── FISTTP_32bit_neg.asm
│ │ ├── FISTTP_64bit.asm
│ │ ├── FISTTP_64bit_neg.asm
│ │ ├── FPREM1_Flags.asm
│ │ ├── FPREM_Flags.asm
│ │ ├── FST_AddrModes.asm
│ │ ├── FScale-Zero.asm
│ │ ├── FScaleFXtract.asm
│ │ ├── FXAM_Push.asm
│ │ ├── FXAM_Push_2.asm
│ │ ├── FXAM_Push_Simple.asm
│ │ ├── FXAM_Push_Simple_2.asm
│ │ ├── FXAM_Simple.asm
│ │ ├── LoadAtBoundary.asm
│ │ ├── Memcopy.asm
│ │ ├── MemcopyWithCPUID.asm
│ │ ├── Rounding.asm
│ │ ├── StoreAtBoundary.asm
│ │ ├── X87MMXInteraction.asm
│ │ ├── invalid_div_zero.asm
│ │ ├── invalid_fcos_infinity.asm
│ │ ├── invalid_fist_nan.asm
│ │ ├── invalid_fist_overflow.asm
│ │ ├── invalid_fist_overflow_16bit.asm
│ │ ├── invalid_fist_overflow_32bit.asm
│ │ ├── invalid_fist_overflow_64bit.asm
│ │ ├── invalid_fprem_infinity.asm
│ │ ├── invalid_fptan_infinity.asm
│ │ ├── invalid_fsin_infinity.asm
│ │ ├── invalid_fsin_neg_infinity.asm
│ │ ├── invalid_fsincos_infinity.asm
│ │ ├── invalid_infinity_fsubr_infinity.asm
│ │ ├── invalid_infinity_mul_zero.asm
│ │ ├── invalid_infinity_ops.asm
│ │ ├── invalid_infinity_sub_infinity.asm
│ │ ├── invalid_neg_infinity_sub_neg_infinity.asm
│ │ ├── invalid_reduced_precision.asm
│ │ ├── invalid_simple_test.asm
│ │ ├── invalid_sqrt_negative.asm
│ │ ├── precision_test_fabs.asm
│ │ ├── precision_test_fadd.asm
│ │ ├── precision_test_fcos.asm
│ │ ├── precision_test_fdiv.asm
│ │ ├── precision_test_fdivr.asm
│ │ ├── precision_test_fmul.asm
│ │ ├── precision_test_fprem.asm
│ │ ├── precision_test_fprem1.asm
│ │ ├── precision_test_fscale.asm
│ │ ├── precision_test_fsin.asm
│ │ ├── precision_test_fsqrt.asm
│ │ ├── precision_test_fsub.asm
│ │ ├── precision_test_fsubr.asm
│ │ ├── precision_test_ftan.asm
│ │ ├── precision_test_fyl2x.asm
│ │ ├── precision_test_fyl2xp1.asm
│ │ ├── precision_test_neg_fabs.asm
│ │ ├── precision_test_neg_fadd.asm
│ │ ├── precision_test_neg_fcos.asm
│ │ ├── precision_test_neg_fdiv.asm
│ │ ├── precision_test_neg_fdivr.asm
│ │ ├── precision_test_neg_fmul.asm
│ │ ├── precision_test_neg_fprem.asm
│ │ ├── precision_test_neg_fprem1.asm
│ │ ├── precision_test_neg_fscale.asm
│ │ ├── precision_test_neg_fsin.asm
│ │ ├── precision_test_neg_fsub.asm
│ │ ├── precision_test_neg_fsubr.asm
│ │ ├── precision_test_neg_ftan.asm
│ │ ├── precision_test_neg_fyl2x.asm
│ │ ├── precision_test_neg_fyl2xp1.asm
│ │ ├── valid_fist_16bit.asm
│ │ └── valid_operation.asm
│ ├── X87_F64/
│ │ ├── D8_00_F64.asm
│ │ ├── D8_01_F64.asm
│ │ ├── D8_04_F64.asm
│ │ ├── D8_05_F64.asm
│ │ ├── D8_06_F64.asm
│ │ ├── D8_07_F64.asm
│ │ ├── D8_C0_F64.asm
│ │ ├── D8_C8_F64.asm
│ │ ├── D8_D9_F64.asm
│ │ ├── D8_E0_F64.asm
│ │ ├── D8_E8_F64.asm
│ │ ├── D8_F0_2_F64.asm
│ │ ├── D8_F0_F64.asm
│ │ ├── D8_F8_F64.asm
│ │ ├── D9_00_F64.asm
│ │ ├── D9_02_F64.asm
│ │ ├── D9_03_F64.asm
│ │ ├── D9_05_F64.asm
│ │ ├── D9_06_2_F64.asm
│ │ ├── D9_06_F64.asm
│ │ ├── D9_07_F64.asm
│ │ ├── D9_C0_F64.asm
│ │ ├── D9_C8_F64.asm
│ │ ├── D9_D0_F64.asm
│ │ ├── D9_E0_F64.asm
│ │ ├── D9_E1_F64.asm
│ │ ├── D9_E4_F64.asm
│ │ ├── D9_E8_F64.asm
│ │ ├── D9_E9_F64.asm
│ │ ├── D9_EA_F64.asm
│ │ ├── D9_EB_F64.asm
│ │ ├── D9_EC_F64.asm
│ │ ├── D9_ED_F64.asm
│ │ ├── D9_EE_F64.asm
│ │ ├── D9_F0_F64.asm
│ │ ├── D9_F1_F64.asm
│ │ ├── D9_F2_F64.asm
│ │ ├── D9_F3_F64.asm
│ │ ├── D9_F4_02_F64.asm
│ │ ├── D9_F4_F64.asm
│ │ ├── D9_F5_F64.asm
│ │ ├── D9_F6_F64.asm
│ │ ├── D9_F7_F64.asm
│ │ ├── D9_F8_F64.asm
│ │ ├── D9_F9_F64.asm
│ │ ├── D9_FA_F64.asm
│ │ ├── D9_FB_F64.asm
│ │ ├── D9_FC_F64.asm
│ │ ├── D9_FD_2_F64.asm
│ │ ├── D9_FD_F64.asm
│ │ ├── D9_FE_F64.asm
│ │ ├── D9_FF_F64.asm
│ │ ├── DA_01_F64.asm
│ │ ├── DA_02_F64.asm
│ │ ├── DA_04_F64.asm
│ │ ├── DA_05_F64.asm
│ │ ├── DA_06_F64.asm
│ │ ├── DA_07_F64.asm
│ │ ├── DA_C0_F64.asm
│ │ ├── DA_C8_F64.asm
│ │ ├── DA_D0_F64.asm
│ │ ├── DA_D8_F64.asm
│ │ ├── DA_D9_F64.asm
│ │ ├── DA_E9_F64.asm
│ │ ├── DB_00_F64.asm
│ │ ├── DB_01_F64.asm
│ │ ├── DB_02_F64.asm
│ │ ├── DB_03_F64.asm
│ │ ├── DB_05_F64.asm
│ │ ├── DB_07_F64.asm
│ │ ├── DB_C0_F64.asm
│ │ ├── DB_C8_F64.asm
│ │ ├── DB_D0_F64.asm
│ │ ├── DB_D8_F64.asm
│ │ ├── DB_E3.asm
│ │ ├── DC_00_F64.asm
│ │ ├── DC_01_F64.asm
│ │ ├── DC_04_F64.asm
│ │ ├── DC_05_F64.asm
│ │ ├── DC_06_F64.asm
│ │ ├── DC_07_F64.asm
│ │ ├── DC_C0_F64.asm
│ │ ├── DC_C8_F64.asm
│ │ ├── DC_E0_F64.asm
│ │ ├── DC_E8_F64.asm
│ │ ├── DC_F0_F64.asm
│ │ ├── DC_F8_F64.asm
│ │ ├── DD_00_F64.asm
│ │ ├── DD_01_F64.asm
│ │ ├── DD_02_F64.asm
│ │ ├── DD_03_F64.asm
│ │ ├── DD_04_2_F64.asm
│ │ ├── DD_04_F64.asm
│ │ ├── DD_07_F64.asm
│ │ ├── DD_C0_F64.asm
│ │ ├── DD_D0_2_F64.asm
│ │ ├── DD_D0_F64.asm
│ │ ├── DD_D8_F64.asm
│ │ ├── DD_E9_F64.asm
│ │ ├── DE_00_F64.asm
│ │ ├── DE_01_F64.asm
│ │ ├── DE_02_F64.asm
│ │ ├── DE_04_F64.asm
│ │ ├── DE_05_F64.asm
│ │ ├── DE_06_F64.asm
│ │ ├── DE_07_F64.asm
│ │ ├── DE_C0_F64.asm
│ │ ├── DE_C8_F64.asm
│ │ ├── DE_E0_F64.asm
│ │ ├── DE_E8_F64.asm
│ │ ├── DE_F0_F64.asm
│ │ ├── DE_F8_F64.asm
│ │ ├── DF_00_F64.asm
│ │ ├── DF_01_F64.asm
│ │ ├── DF_02_F64.asm
│ │ ├── DF_03_F64.asm
│ │ ├── DF_04_F64.asm
│ │ ├── DF_05_F64.asm
│ │ ├── DF_07_F64.asm
│ │ ├── DF_E0_F64.asm
│ │ ├── FCOM_F64.asm
│ │ ├── FILD_NEG_F64.asm
│ │ ├── FIST_F64.asm
│ │ ├── FLDCW_F64.asm
│ │ ├── FLD_F64.asm
│ │ ├── FPREM1_Flags_F64.asm
│ │ ├── FPREM_Flags_F64.asm
│ │ ├── FScale-Zero_F64.asm
│ │ ├── FScaleFXtract_F64.asm
│ │ ├── FXAM_Push_2_F64.asm
│ │ ├── FXAM_Push_F64.asm
│ │ ├── Rounding_F64.asm
│ │ ├── fptan_neg_zero_F64.asm
│ │ ├── fptan_pos_zero_F64.asm
│ │ ├── fsin_neg_zero_F64.asm
│ │ ├── fsin_pos_zero_F64.asm
│ │ └── fsincos_neg_zero_F64.asm
│ ├── fadd.asm
│ ├── fld.asm
│ ├── full_pshufd_imm.asm
│ ├── full_vpblendw_imm.asm
│ ├── jump.asm
│ ├── lea.asm
│ ├── modrm_oob/
│ │ ├── DDD.asm
│ │ ├── H0F38.asm
│ │ ├── H0F3A.asm
│ │ ├── Primary.asm
│ │ ├── PrimaryGroup.asm
│ │ ├── Secondary.asm
│ │ ├── SecondaryGroup.asm
│ │ ├── SecondaryModRM.asm
│ │ ├── SecondaryOpSize.asm
│ │ ├── SecondaryREP.asm
│ │ ├── SecondaryREPNE.asm
│ │ ├── VEX.asm
│ │ ├── VEXGroup.asm
│ │ ├── X87.asm
│ │ └── X87_Reduced.asm
│ ├── mov.asm
│ ├── movups.asm
│ ├── movzx.asm
│ ├── pslldq.asm
│ └── x87_stack.asm
├── CMakeLists.txt
├── Example.asm
├── FEXLinuxTests/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Disabled_Tests_Host
│ ├── Expected_Output
│ ├── Flake_Tests
│ ├── Known_Failures
│ └── tests/
│ ├── CMakeLists.txt
│ ├── cpu/
│ │ └── cpu_count.cpp
│ ├── fd/
│ │ └── test_close_range.cpp
│ ├── fs/
│ │ └── self_symlink.cpp
│ ├── include/
│ │ ├── fpstate.h
│ │ └── simple_x86.h
│ ├── signal/
│ │ ├── Syscall_state.32.cpp
│ │ ├── Syscall_state.64.cpp
│ │ ├── SystemInstructions.64.cpp
│ │ ├── eflags_signal.cpp
│ │ ├── into.32.cpp
│ │ ├── invalid_hlt.cpp
│ │ ├── invalid_int.cpp
│ │ ├── invalid_int1.cpp
│ │ ├── invalid_int3.cpp
│ │ ├── invalid_ud2.cpp
│ │ ├── invalid_util.h
│ │ ├── invalid_vex.32.cpp
│ │ ├── noexec_protect.64.cpp
│ │ ├── pthread_cancel.cpp
│ │ ├── sigill_flags.cpp
│ │ ├── sigill_xstate_magic.cpp
│ │ ├── signal_df_reset.64.cpp
│ │ ├── signal_flags.cpp
│ │ ├── signal_order.cpp
│ │ ├── sigtest_defer.cpp
│ │ ├── sigtest_no_defer.cpp
│ │ ├── sigtest_samask.cpp
│ │ ├── sigtest_siginfo.32.cpp
│ │ ├── sigtest_siginfo.64.cpp
│ │ ├── sigtest_sigmask.cpp
│ │ ├── synchronous-signal-block.cpp
│ │ ├── timer-sigev-thread.cpp
│ │ ├── trap_flag.cpp
│ │ └── x87_state.64.cpp
│ ├── smc/
│ │ ├── smc-1-dynamic.cpp
│ │ ├── smc-2.cpp
│ │ ├── smc-common.h
│ │ ├── smc-exec-stack.cpp
│ │ ├── smc-missing-gnustack.cpp
│ │ ├── smc-mt-1.cpp
│ │ ├── smc-mt-2.cpp
│ │ ├── smc-shared-1.cpp
│ │ ├── smc-shared-2.cpp
│ │ └── smc-unexec-stack.cpp
│ ├── syscalls/
│ │ ├── execveat_memfd.cpp
│ │ ├── futimesat.cpp
│ │ ├── personality.cpp
│ │ ├── syscall_exit.cpp
│ │ ├── syscall_sigaltstack.cpp
│ │ └── syscalls_efault.cpp
│ ├── thunks/
│ │ └── thunk_testlib.cpp
│ └── vdso/
│ └── vdso_test.cpp
├── InstructionCountCI/
│ ├── AFP/
│ │ ├── H0F3A.json
│ │ ├── SVE256/
│ │ │ ├── Secondary.json
│ │ │ ├── Secondary_REP.json
│ │ │ └── Secondary_REPNE.json
│ │ ├── Secondary.json
│ │ ├── Secondary_REP.json
│ │ ├── Secondary_REPNE.json
│ │ ├── VEX_map1.json
│ │ └── VEX_map3.json
│ ├── AVX128/
│ │ ├── FMA4.json
│ │ ├── VEX_map1.json
│ │ ├── VEX_map1_FCMA.json
│ │ ├── VEX_map1_SVE128.json
│ │ ├── VEX_map1_flagm.json
│ │ ├── VEX_map2.json
│ │ ├── VEX_map2_AFP.json
│ │ ├── VEX_map2_SVE128.json
│ │ ├── VEX_map2_flagm.json
│ │ ├── VEX_map3.json
│ │ ├── VEX_map3_SVE128.json
│ │ └── VEX_map_group.json
│ ├── Atomics.json
│ ├── CMakeLists.txt
│ ├── Crypto/
│ │ ├── H0F38.json
│ │ └── H0F3A.json
│ ├── DDD.json
│ ├── FEXOpt/
│ │ ├── AddressingLimitations.json
│ │ ├── AddressingLimitations_32Bit.json
│ │ ├── MultiInst.json
│ │ ├── MultiInst_32bit.json
│ │ ├── MultiInst_AFP.json
│ │ ├── MultiInst_TSO.json
│ │ ├── MultiInst_TSO_32bit.json
│ │ └── libnss.json
│ ├── FlagM/
│ │ ├── Atomics.json
│ │ ├── FlagOpts.json
│ │ ├── H0F38.json
│ │ ├── HotBlocks.json
│ │ ├── HotBlocks_32Bit.json
│ │ ├── HotBlocks_AFP.json
│ │ ├── HotBlocks_TSO_32Bit.json
│ │ ├── Primary.json
│ │ ├── PrimaryGroup.json
│ │ ├── Primary_32Bit.json
│ │ ├── Secondary.json
│ │ ├── SecondaryGroup.json
│ │ ├── SecondaryModRM.json
│ │ ├── Secondary_OpSize.json
│ │ ├── Secondary_REP.json
│ │ ├── Secondary_REP_CSSC.json
│ │ ├── VEX_map1.json
│ │ ├── VEX_map2.json
│ │ ├── VEX_map_group.json
│ │ ├── x87-Crysis2Max-fmodel.json
│ │ ├── x87-HalfLife.json
│ │ ├── x87-Oblivion.json
│ │ ├── x87-Psychonauts.json
│ │ ├── x87.json
│ │ ├── x87_f64-Crysis2Max-fmodel.json
│ │ ├── x87_f64-HalfLife.json
│ │ ├── x87_f64-Oblivion.json
│ │ ├── x87_f64-Psychonauts.json
│ │ └── x87_f64.json
│ ├── H0F38.json
│ ├── H0F3A.json
│ ├── H0F3A_SVE128.json
│ ├── MOPS/
│ │ └── Primary.json
│ ├── Primary.json
│ ├── PrimaryGroup.json
│ ├── Primary_32Bit.json
│ ├── RPRES/
│ │ ├── DDD.json
│ │ ├── Secondary.json
│ │ ├── Secondary_REP_AFP.json
│ │ └── VEX_map1_AFP.json
│ ├── Repeat.json
│ ├── SSE42_Strings.json
│ ├── Secondary.json
│ ├── SecondaryGroup.json
│ ├── SecondaryModRM.json
│ ├── Secondary_32Bit.json
│ ├── Secondary_OpSize.json
│ ├── Secondary_OpSize_FCMA.json
│ ├── Secondary_OpSize_SVE128.json
│ ├── Secondary_OpSize_SVE256.json
│ ├── Secondary_REP.json
│ ├── Secondary_REPNE.json
│ ├── Secondary_REPNE_FCMA.json
│ ├── Secondary_REPNE_SVE128.json
│ ├── Secondary_REP_FRINTTS.json
│ ├── Secondary_SVE128.json
│ ├── VEX_map1.json
│ ├── VEX_map1_FCMA.json
│ ├── VEX_map1_FRINTTS.json
│ ├── VEX_map2.json
│ ├── VEX_map2_svebitperm.json
│ ├── VEX_map3.json
│ ├── VEX_map_group.json
│ ├── X87ldst-SVE.json
│ ├── x87.json
│ ├── x87_32Bit.json
│ ├── x87_f64.json
│ └── x87_f64_32Bit.json
├── POSIX/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ ├── Flake_Tests
│ └── Known_Failures
├── Readme.md
├── ThunkFunctionalTests/
│ └── CMakeLists.txt
├── ThunkLibs/
│ ├── CMakeLists.txt
│ ├── abi.cpp
│ ├── common.h
│ └── generator.cpp
├── Utilities/
│ ├── CMakeLists.txt
│ └── DeleteOldSHMRegions.cpp
├── gcc-target-tests-32/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ └── Known_Failures
├── gcc-target-tests-64/
│ ├── CMakeLists.txt
│ ├── Disabled_Tests
│ ├── Expected_Output
│ └── Known_Failures
└── gvisor-tests/
├── CMakeLists.txt
├── Disabled_Tests
├── Expected_Output
├── Flake_Tests
└── Known_Failures
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SYMBOL INDEX (10497 symbols across 632 files)
FILE: CodeEmitter/CodeEmitter/Buffer.h
function namespace (line 8) | namespace ARMEmitter {
FILE: CodeEmitter/CodeEmitter/Emitter.h
type class (line 62) | enum class
type class (line 76) | enum class
function IsStandardFloatSize (line 93) | [[nodiscard]]
type class (line 107) | enum class
function VectorRegSizePair (line 133) | [[nodiscard]]
function VectorRegSizePair (line 137) | [[nodiscard]]
type class (line 143) | enum class
type class (line 151) | enum class
type class (line 165) | enum class
type class (line 193) | enum class
type class (line 208) | enum class
function SVEModType (line 218) | enum class SVEModType : uint8_t {
function class (line 310) | class ExtendedMemOperand final {
type class (line 356) | enum class
type class (line 374) | enum class
type class (line 417) | enum class
type class (line 429) | enum class
type class (line 439) | enum class
type class (line 459) | enum class
type class (line 486) | enum class
type class (line 507) | enum class
type class (line 511) | enum class
function SVEFMaxMinImm (line 515) | enum class SVEFMaxMinImm : uint32_t {
FILE: CodeEmitter/CodeEmitter/Registers.h
function explicit (line 19) | constexpr explicit Register(uint32_t Idx)
function explicit (line 43) | constexpr explicit WRegister(uint32_t Idx)
function explicit (line 71) | constexpr explicit XRegister(uint32_t Idx)
function XRegister (line 101) | inline constexpr XRegister WRegister::X() const {
function WRegister (line 109) | inline constexpr WRegister XRegister::W() const {
function namespace (line 118) | namespace Reg {
function namespace (line 163) | namespace XReg {
function namespace (line 208) | namespace WReg {
function explicit (line 267) | constexpr explicit VRegister(uint32_t Idx)
function explicit (line 296) | constexpr explicit BRegister(uint32_t Idx)
function explicit (line 328) | constexpr explicit HRegister(uint32_t Idx)
function explicit (line 360) | constexpr explicit SRegister(uint32_t Idx)
function explicit (line 393) | constexpr explicit DRegister(uint32_t Idx)
function explicit (line 426) | constexpr explicit QRegister(uint32_t Idx)
function explicit (line 458) | constexpr explicit ZRegister(uint32_t Idx)
function QRegister (line 494) | inline constexpr QRegister VRegister::Q() const {
function QRegister (line 534) | inline constexpr QRegister HRegister::Q() const {
function QRegister (line 574) | inline constexpr QRegister DRegister::Q() const {
function ZRegister (line 597) | inline constexpr ZRegister QRegister::Z() const {
function HRegister (line 608) | inline constexpr HRegister ZRegister::H() const {
function DRegister (line 614) | inline constexpr DRegister ZRegister::D() const {
function namespace (line 622) | namespace VReg {
function namespace (line 658) | namespace BReg {
function namespace (line 694) | namespace HReg {
function namespace (line 730) | namespace SReg {
function namespace (line 766) | namespace DReg {
function namespace (line 802) | namespace QReg {
function namespace (line 838) | namespace ZReg {
function Register (line 874) | inline constexpr Register ToReg(HRegister Reg) {
function Register (line 877) | inline constexpr Register ToReg(SRegister Reg) {
function Register (line 880) | inline constexpr Register ToReg(DRegister Reg) {
function Register (line 883) | inline constexpr Register ToReg(VRegister Reg) {
function VRegister (line 888) | inline constexpr VRegister ToVReg(Register Reg) {
function VRegister (line 891) | inline constexpr VRegister ToVReg(XRegister Reg) {
function VRegister (line 894) | inline constexpr VRegister ToVReg(WRegister Reg) {
function Index (line 907) | constexpr PRegister(uint32_t Idx)
function PRegisterZero (line 916) | constexpr PRegisterZero Zeroing() const;
function class (line 955) | class PRegisterMerge {
function PRegisterZero (line 983) | inline constexpr PRegisterZero PRegister::Zeroing() const {
function PRegisterMerge (line 991) | inline constexpr PRegisterMerge PRegisterZero::Merging() const {
function OpType (line 1023) | enum class OpType : uint32_t {
FILE: External/SoftFloat-3e/include/SoftFloat-3e/opts-GCC.h
function INLINE (line 47) | INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
function INLINE (line 51) | INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
function INLINE (line 55) | INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
function uint128 (line 63) | uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
function uint128 (line 71) | uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
function uint128 (line 80) | uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
function INLINE (line 88) | INLINE
FILE: External/SoftFloat-3e/include/SoftFloat-3e/primitiveTypes.h
type uint128 (line 45) | struct uint128 { uint64_t v0, v64; }
type uint64_extra (line 46) | struct uint64_extra { uint64_t extra, v; }
type uint128_extra (line 47) | struct uint128_extra { uint64_t extra; struct uint128 v; }
type uint128 (line 49) | struct uint128 { uint64_t v64, v0; }
type uint64_extra (line 50) | struct uint64_extra { uint64_t v, extra; }
type uint128_extra (line 51) | struct uint128_extra { struct uint128 v; uint64_t extra; }
FILE: External/SoftFloat-3e/include/SoftFloat-3e/softfloat.h
type softfloat_state (line 57) | struct softfloat_state
type softfloat_state (line 151) | struct softfloat_state
type softfloat_state (line 152) | struct softfloat_state
type softfloat_state (line 187) | struct softfloat_state
type softfloat_state (line 214) | struct softfloat_state
type softfloat_state (line 216) | struct softfloat_state
type softfloat_state (line 218) | struct softfloat_state
type softfloat_state (line 225) | struct softfloat_state
type softfloat_state (line 227) | struct softfloat_state
type softfloat_state (line 229) | struct softfloat_state
type softfloat_state (line 231) | struct softfloat_state
type softfloat_state (line 233) | struct softfloat_state
type softfloat_state (line 235) | struct softfloat_state
type softfloat_state (line 237) | struct softfloat_state
type softfloat_state (line 239) | struct softfloat_state
type softfloat_state (line 241) | struct softfloat_state
type softfloat_state (line 243) | struct softfloat_state
type softfloat_state (line 245) | struct softfloat_state
type softfloat_state (line 246) | struct softfloat_state
type softfloat_state (line 248) | struct softfloat_state
function extFloat80_t (line 253) | static inline extFloat80_t extF80_complement_sign(extFloat80_t a) {
type softfloat_state (line 291) | struct softfloat_state
type softfloat_state (line 292) | struct softfloat_state
type softfloat_state (line 293) | struct softfloat_state
type softfloat_state (line 294) | struct softfloat_state
type softfloat_state (line 299) | struct softfloat_state
type softfloat_state (line 300) | struct softfloat_state
type softfloat_state (line 301) | struct softfloat_state
type softfloat_state (line 303) | struct softfloat_state
type softfloat_state (line 305) | struct softfloat_state
type softfloat_state (line 306) | struct softfloat_state
type softfloat_state (line 307) | struct softfloat_state
type softfloat_state (line 308) | struct softfloat_state
type softfloat_state (line 309) | struct softfloat_state
type softfloat_state (line 310) | struct softfloat_state
type softfloat_state (line 311) | struct softfloat_state
type softfloat_state (line 312) | struct softfloat_state
type softfloat_state (line 313) | struct softfloat_state
type softfloat_state (line 314) | struct softfloat_state
type softfloat_state (line 315) | struct softfloat_state
type softfloat_state (line 316) | struct softfloat_state
type softfloat_state (line 317) | struct softfloat_state
function float128_t (line 319) | static inline float128_t f128_complement_sign(float128_t a) {
FILE: External/SoftFloat-3e/include/SoftFloat-3e/softfloat_types.h
type float16_t (line 50) | typedef struct { uint16_t v; } float16_t;
type float32_t (line 51) | typedef struct { uint32_t v; } float32_t;
type float64_t (line 52) | typedef struct { uint64_t v; } float64_t;
type float128_t (line 53) | typedef struct { uint64_t v[2]; } float128_t;
type extFloat80M (line 61) | struct extFloat80M { uint64_t signif; uint16_t signExp; }
type extFloat80M (line 63) | struct extFloat80M { uint16_t signExp; uint64_t signif; }
type extFloat80_t (line 78) | typedef struct extFloat80M extFloat80_t;
type softfloat_state (line 102) | struct softfloat_state {
FILE: External/SoftFloat-3e/src/extF80_add.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_div.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_eq.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_le.c
function extF80_le (line 44) | bool extF80_le( struct softfloat_state *state, extFloat80_t a, extFloat8...
FILE: External/SoftFloat-3e/src/extF80_lt.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_mul.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_rem.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_roundToInt.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_sqrt.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_sub.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_f128.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_f32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_f64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_i32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_i64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/extF80_to_ui64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/f128_add.c
function float128_t (line 43) | float128_t f128_add( struct softfloat_state *state, float128_t a, float1...
FILE: External/SoftFloat-3e/src/f128_div.c
function float128_t (line 44) | float128_t f128_div( struct softfloat_state *state, float128_t a, float1...
FILE: External/SoftFloat-3e/src/f128_eq.c
function f128_eq (line 44) | bool f128_eq( struct softfloat_state *state, float128_t a, float128_t b )
FILE: External/SoftFloat-3e/src/f128_eq_signaling.c
function f128_eq_signaling (line 43) | bool f128_eq_signaling( struct softfloat_state *state, float128_t a, flo...
FILE: External/SoftFloat-3e/src/f128_isSignalingNaN.c
function f128_isSignalingNaN (line 43) | bool f128_isSignalingNaN( float128_t a )
FILE: External/SoftFloat-3e/src/f128_le.c
function f128_le (line 43) | bool f128_le( struct softfloat_state *state, float128_t a, float128_t b )
FILE: External/SoftFloat-3e/src/f128_le_quiet.c
function f128_le_quiet (line 44) | bool f128_le_quiet( struct softfloat_state *state, float128_t a, float12...
FILE: External/SoftFloat-3e/src/f128_lt.c
function f128_lt (line 43) | bool f128_lt( struct softfloat_state *state, float128_t a, float128_t b )
FILE: External/SoftFloat-3e/src/f128_lt_quiet.c
function f128_lt_quiet (line 44) | bool f128_lt_quiet( struct softfloat_state *state, float128_t a, float12...
FILE: External/SoftFloat-3e/src/f128_mul.c
function float128_t (line 44) | float128_t f128_mul( struct softfloat_state *state, float128_t a, float1...
FILE: External/SoftFloat-3e/src/f128_mulAdd.c
function float128_t (line 42) | float128_t f128_mulAdd( struct softfloat_state *state, float128_t a, flo...
FILE: External/SoftFloat-3e/src/f128_rem.c
function float128_t (line 44) | float128_t f128_rem( struct softfloat_state *state, float128_t a, float1...
FILE: External/SoftFloat-3e/src/f128_sqrt.c
function float128_t (line 44) | float128_t f128_sqrt( struct softfloat_state *state, float128_t a )
FILE: External/SoftFloat-3e/src/f128_sub.c
function float128_t (line 43) | float128_t f128_sub( struct softfloat_state *state, float128_t a, float1...
FILE: External/SoftFloat-3e/src/f128_to_extF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/f128_to_f16.c
function float16_t (line 44) | float16_t f128_to_f16( struct softfloat_state *state, float128_t a )
FILE: External/SoftFloat-3e/src/f128_to_f32.c
function float32_t (line 44) | float32_t f128_to_f32( struct softfloat_state *state, float128_t a )
FILE: External/SoftFloat-3e/src/f128_to_f64.c
function float64_t (line 44) | float64_t f128_to_f64( struct softfloat_state *state, float128_t a )
FILE: External/SoftFloat-3e/src/f128_to_i32.c
function int_fast32_t (line 44) | int_fast32_t f128_to_i32( struct softfloat_state *state, float128_t a, u...
FILE: External/SoftFloat-3e/src/f128_to_i64.c
function int_fast64_t (line 44) | int_fast64_t f128_to_i64( struct softfloat_state *state, float128_t a, u...
FILE: External/SoftFloat-3e/src/f128_to_ui32.c
function uint_fast32_t (line 44) | uint_fast32_t
FILE: External/SoftFloat-3e/src/f128_to_ui64.c
function uint_fast64_t (line 44) | uint_fast64_t
FILE: External/SoftFloat-3e/src/f32_to_extF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/f32_to_f128.c
function float128_t (line 44) | float128_t f32_to_f128( struct softfloat_state *state, float32_t a )
FILE: External/SoftFloat-3e/src/f64_to_extF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/i32_to_extF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/i32_to_f128.c
function float128_t (line 42) | float128_t i32_to_f128( int32_t a )
FILE: External/SoftFloat-3e/src/internals.h
type extFloat80M (line 50) | struct extFloat80M
type uint128 (line 51) | struct uint128
type softfloat_state (line 66) | struct softfloat_state
type softfloat_state (line 72) | struct softfloat_state
type softfloat_state (line 78) | struct softfloat_state
type exp8_sig16 (line 92) | struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; }
type exp8_sig16 (line 93) | struct exp8_sig16
type exp16_sig32 (line 113) | struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; }
type softfloat_state (line 118) | struct softfloat_state
type exp16_sig64 (line 136) | struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; }
type softfloat_state (line 141) | struct softfloat_state
type exp32_sig64 (line 163) | struct exp32_sig64 { int_fast32_t exp; uint64_t sig; }
type softfloat_state (line 170) | struct softfloat_state
type softfloat_state (line 174) | struct softfloat_state
type softfloat_state (line 178) | struct softfloat_state
type softfloat_state (line 181) | struct softfloat_state
type exp32_sig128 (line 192) | struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; }
type softfloat_state (line 199) | struct softfloat_state
type softfloat_state (line 203) | struct softfloat_state
type softfloat_state (line 208) | struct softfloat_state
type softfloat_state (line 212) | struct softfloat_state
type extFloat80M (line 232) | struct extFloat80M
type extFloat80M (line 233) | struct extFloat80M
type extFloat80M (line 234) | struct extFloat80M
type extFloat80M (line 236) | struct extFloat80M
type extFloat80M (line 242) | struct extFloat80M
type extFloat80M (line 245) | struct extFloat80M
type extFloat80M (line 249) | struct extFloat80M
type extFloat80M (line 250) | struct extFloat80M
type extFloat80M (line 251) | struct extFloat80M
type extFloat80M (line 257) | struct extFloat80M
type extFloat80M (line 257) | struct extFloat80M
FILE: External/SoftFloat-3e/src/primitives.h
function INLINE (line 52) | INLINE
function INLINE (line 72) | INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
function INLINE (line 94) | INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
function INLINE (line 118) | INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
function INLINE (line 139) | INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
function INLINE (line 231) | INLINE
function INLINE (line 246) | INLINE
function INLINE (line 262) | INLINE
function uint128 (line 278) | uint128
function uint128 (line 300) | uint128
function uint64_extra (line 322) | uint64_extra
type uint64_extra (line 332) | struct uint64_extra
function uint128 (line 348) | uint128
type uint128 (line 361) | struct uint128
function uint128_extra (line 374) | uint128_extra
type uint128_extra (line 386) | struct uint128_extra
function uint64_extra (line 411) | uint64_extra
type uint128 (line 445) | struct uint128
type uint128_extra (line 467) | struct uint128_extra
function uint128 (line 498) | uint128
function uint128 (line 534) | uint128
function uint128 (line 569) | uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
function uint128 (line 600) | uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
type uint128 (line 612) | struct uint128
function INLINE (line 670) | INLINE
FILE: External/SoftFloat-3e/src/s_add128.c
function uint128 (line 44) | uint128
FILE: External/SoftFloat-3e/src/s_addMagsExtF80.c
function extFloat80_t (line 44) | extFloat80_t
FILE: External/SoftFloat-3e/src/s_addMagsF128.c
function float128_t (line 43) | float128_t
FILE: External/SoftFloat-3e/src/s_approxRecip32_1.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_approxRecipSqrt32_1.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_commonNaNToExtF80UI.c
function uint128 (line 48) | uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
FILE: External/SoftFloat-3e/src/s_commonNaNToF128UI.c
function uint128 (line 47) | uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
FILE: External/SoftFloat-3e/src/s_commonNaNToF32UI.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_commonNaNToF64UI.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_countLeadingZeros32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_countLeadingZeros64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 45) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_extF80UIToCommonNaN.c
function FEXCORE_PRESERVE_ALL_ATTR (line 49) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_f128UIToCommonNaN.c
function FEXCORE_PRESERVE_ALL_ATTR (line 50) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_f32UIToCommonNaN.c
function FEXCORE_PRESERVE_ALL_ATTR (line 48) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_f64UIToCommonNaN.c
function FEXCORE_PRESERVE_ALL_ATTR (line 48) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_le128.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_lt128.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_mul64ByShifted32To128.c
function uint128 (line 44) | uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
FILE: External/SoftFloat-3e/src/s_mul64To128.c
function uint128 (line 44) | uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
FILE: External/SoftFloat-3e/src/s_normRoundPackToExtF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 42) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_normRoundPackToF128.c
function float128_t (line 42) | float128_t
FILE: External/SoftFloat-3e/src/s_normSubnormalExtF80Sig.c
function exp32_sig64 (line 42) | exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t sig )
FILE: External/SoftFloat-3e/src/s_normSubnormalF128Sig.c
function exp32_sig128 (line 42) | exp32_sig128
FILE: External/SoftFloat-3e/src/s_normSubnormalF128SigM.c
function softfloat_normSubnormalF128SigM (line 41) | int softfloat_normSubnormalF128SigM( uint32_t *sigPtr )
FILE: External/SoftFloat-3e/src/s_normSubnormalF32Sig.c
function exp16_sig32 (line 42) | exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig )
FILE: External/SoftFloat-3e/src/s_normSubnormalF64Sig.c
function exp16_sig64 (line 42) | exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig )
FILE: External/SoftFloat-3e/src/s_propagateNaNExtF80UI.c
function uint128 (line 54) | uint128
FILE: External/SoftFloat-3e/src/s_propagateNaNF128UI.c
function softfloat_propagateNaNF128UI (line 53) | struct uint128
FILE: External/SoftFloat-3e/src/s_roundPackToExtF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_roundPackToF128.c
function float128_t (line 43) | float128_t
FILE: External/SoftFloat-3e/src/s_roundPackToF32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_roundPackToF64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 43) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_roundToI32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_roundToI64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 44) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_roundToUI64.c
function uint_fast64_t (line 44) | uint_fast64_t
FILE: External/SoftFloat-3e/src/s_shiftRightJam128.c
function softfloat_shiftRightJam128 (line 43) | struct uint128
FILE: External/SoftFloat-3e/src/s_shiftRightJam128Extra.c
function softfloat_shiftRightJam128Extra (line 43) | struct uint128_extra
FILE: External/SoftFloat-3e/src/s_shiftRightJam32.c
function FEXCORE_PRESERVE_ALL_ATTR (line 42) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_shiftRightJam64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 42) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_shiftRightJam64Extra.c
function uint64_extra (line 44) | uint64_extra
FILE: External/SoftFloat-3e/src/s_shortShiftLeft128.c
function uint128 (line 44) | uint128
FILE: External/SoftFloat-3e/src/s_shortShiftRight128.c
function uint128 (line 44) | uint128
FILE: External/SoftFloat-3e/src/s_shortShiftRightJam64.c
function FEXCORE_PRESERVE_ALL_ATTR (line 42) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/s_shortShiftRightJam64Extra.c
function softfloat_shortShiftRightJam64Extra (line 43) | struct uint64_extra
FILE: External/SoftFloat-3e/src/s_sub128.c
function uint128 (line 44) | uint128
FILE: External/SoftFloat-3e/src/s_subMagsExtF80.c
function extFloat80_t (line 44) | extFloat80_t
FILE: External/SoftFloat-3e/src/s_subMagsF128.c
function float128_t (line 44) | float128_t
FILE: External/SoftFloat-3e/src/softfloat_raiseFlags.c
function FEXCORE_PRESERVE_ALL_ATTR (line 46) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/SoftFloat-3e/src/specialize.h
type commonNaN (line 76) | struct commonNaN {
type commonNaN (line 103) | struct commonNaN
type commonNaN (line 109) | struct commonNaN
type softfloat_state (line 139) | struct softfloat_state
type commonNaN (line 139) | struct commonNaN
type commonNaN (line 146) | struct commonNaN
type softfloat_state (line 176) | struct softfloat_state
type commonNaN (line 176) | struct commonNaN
type commonNaN (line 183) | struct commonNaN
type softfloat_state (line 225) | struct softfloat_state
type commonNaN (line 225) | struct commonNaN
type commonNaN (line 233) | struct commonNaN
type softfloat_state (line 247) | struct softfloat_state
type softfloat_state (line 278) | struct softfloat_state
type commonNaN (line 278) | struct commonNaN
type commonNaN (line 285) | struct commonNaN
type uint128 (line 296) | struct uint128
type softfloat_state (line 298) | struct softfloat_state
type extFloat80M (line 320) | struct extFloat80M
type commonNaN (line 320) | struct commonNaN
type commonNaN (line 329) | struct commonNaN
type extFloat80M (line 329) | struct extFloat80M
type extFloat80M (line 339) | struct extFloat80M
type extFloat80M (line 340) | struct extFloat80M
type extFloat80M (line 341) | struct extFloat80M
type commonNaN (line 361) | struct commonNaN
type commonNaN (line 370) | struct commonNaN
FILE: External/SoftFloat-3e/src/ui64_to_extF80.c
function FEXCORE_PRESERVE_ALL_ATTR (line 42) | FEXCORE_PRESERVE_ALL_ATTR
FILE: External/cephes/include/cephes_128bit.h
function namespace (line 8) | namespace FEXCore::cephes_128bit {
FILE: External/cephes/src/128bit/Impl.cpp
type FEXCore::cephes_128bit (line 13) | namespace FEXCore::cephes_128bit {
function float128_t (line 14) | float128_t atan2l(float128_t y, float128_t x) {
function float128_t (line 17) | float128_t cosl(float128_t x) {
function float128_t (line 20) | float128_t exp2l(float128_t x) {
function float128_t (line 23) | float128_t log2l(float128_t x) {
function float128_t (line 26) | float128_t sinl(float128_t x) {
function float128_t (line 29) | float128_t tanl(float128_t x) {
FILE: External/cephes/src/128bit/atanll.c
function float128_t (line 116) | float128_t cephes_f128_atanl(float128_t x)
type softfloat_state (line 167) | struct softfloat_state
FILE: External/cephes/src/128bit/exp2ll.c
function float128_t (line 87) | float128_t cephes_f128_exp2l(float128_t x) {
FILE: External/cephes/src/128bit/floorll.c
function float128_t (line 97) | float128_t cephes_f128_fabsl(float128_t x)
function float128_t (line 109) | float128_t cephes_f128_ceill(float128_t x)
function float128_t (line 152) | float128_t cephes_f128_floorl(float128_t x)
function float128_t (line 213) | float128_t cephes_f128_frexpl( float128_t x, int *pw2 )
function float128_t (line 263) | float128_t cephes_f128_ldexpl( float128_t x, int pw2 )
function cephes_f128_isnanl (line 341) | int cephes_f128_isnanl(float128_t x)
function cephes_f128_isfinitel (line 395) | int cephes_f128_isfinitel(float128_t x)
function cephes_f128_signbitl (line 440) | int cephes_f128_signbitl(float128_t x)
FILE: External/cephes/src/128bit/log2ll.c
function float128_t (line 126) | float128_t cephes_f128_log2l(float128_t x) {
FILE: External/cephes/src/128bit/mconf.h
type cmplx (line 83) | typedef struct
type cmplxf (line 89) | typedef struct
type cmplxl (line 97) | typedef struct
FILE: External/cephes/src/128bit/mtherr.c
function mtherr (line 61) | int mtherr( char *name, int code )
FILE: External/cephes/src/128bit/polevll.c
function float128_t (line 57) | float128_t cephes_f128_polevll( float128_t x, void *PP, int n )
function float128_t (line 79) | float128_t cephes_f128_p1evll( float128_t x, void *PP, int n )
FILE: External/cephes/src/128bit/sinll.c
function float128_t (line 147) | float128_t cephes_f128_sinl(float128_t x)
function float128_t (line 229) | float128_t cephes_f128_cosl(float128_t x)
FILE: External/cephes/src/128bit/tanll.c
type softfloat_state (line 125) | struct softfloat_state
function float128_t (line 127) | float128_t cephes_f128_tanl(float128_t x)
function float128_t (line 134) | float128_t cotl(float128_t x)
function float128_t (line 147) | static float128_t tancotl( struct softfloat_state *state, float128_t xx,...
FILE: External/code-format-helper/code-format-helper.py
class FormatArgs (line 38) | class FormatArgs:
method __init__ (line 48) | def __init__(self, args: argparse.Namespace = None) -> None:
class FormatHelper (line 59) | class FormatHelper:
method comment_tag (line 66) | def comment_tag(self) -> str:
method instructions (line 70) | def instructions(self) -> str:
method has_tool (line 73) | def has_tool(self) -> bool:
method format_run (line 76) | def format_run(self, changed_files: List[str], args: FormatArgs) -> Op...
method pr_comment_text_for_diff (line 79) | def pr_comment_text_for_diff(self, diff: str) -> str:
method find_comment (line 108) | def find_comment(self, pr: any) -> any:
method update_pr (line 114) | def update_pr(self, comment_text: str, args: FormatArgs, create_new: b...
method run (line 137) | def run(self, changed_files: List[str], args: FormatArgs) -> bool:
class ClangFormatHelper (line 171) | class ClangFormatHelper(FormatHelper):
method instructions (line 177) | def instructions(self) -> str:
method should_include_extensionless_file (line 180) | def should_include_extensionless_file(self, path: str) -> bool:
method filter_changed_files (line 183) | def filter_changed_files(self, changed_files: List[str]) -> List[str]:
method clang_fmt_path (line 194) | def clang_fmt_path(self) -> str:
method has_tool (line 199) | def has_tool(self) -> bool:
method format_run (line 208) | def format_run(self, changed_files: List[str], args: FormatArgs) -> Op...
function hook_main (line 244) | def hook_main():
FILE: External/tiny-json/tiny-json.c
type jsonStaticPool_t (line 37) | typedef struct jsonStaticPool_s {
function json_t (line 45) | json_t const* json_getProperty( json_t const* obj, char const* property ) {
function json_t (line 72) | json_t const* json_createWithPool( char *str, jsonPool_t *pool ) {
function json_t (line 85) | json_t const* json_create( char* str, json_t mem[], unsigned int qty ) {
function getEscape (line 101) | static char getEscape( char ch ) {
function getCharFromUnicode (line 119) | static unsigned char getCharFromUnicode( unsigned char const* str ) {
function add (line 315) | static void add( json_t* obj, json_t* property ) {
function json_t (line 391) | static json_t* poolInit( jsonPool_t* pool ) {
function json_t (line 401) | static json_t* poolAlloc( jsonPool_t* pool ) {
function isOneOfThem (line 411) | static bool isOneOfThem( char ch, char const* set ) {
function isEndOfPrimitive (line 463) | static bool isEndOfPrimitive( char ch ) {
function nibbletoch (line 540) | static int nibbletoch( int nibble ) {
function escape (line 547) | static int escape( int ch ) {
FILE: External/tiny-json/tiny-json.h
type jsonType_t (line 49) | typedef enum {
type json_t (line 55) | typedef struct json_s {
function jsonType_t (line 96) | static inline jsonType_t json_getType(const json_t* json) {
function json_t (line 104) | static inline const json_t* json_getSibling(const json_t* json) {
function json_t (line 128) | static inline const json_t* json_getChild(const json_t* json) {
function json_getBoolean (line 135) | static inline bool json_getBoolean(const json_t* property) {
function json_getInteger (line 142) | static inline int64_t json_getInteger(const json_t* property) {
function json_getReal (line 149) | static inline double json_getReal(const json_t* property) {
type jsonPool_t (line 155) | typedef struct jsonPool_s jsonPool_t;
type jsonPool_s (line 156) | struct jsonPool_s {
FILE: FEXCore/Scripts/config_generator.py
function print_header (line 5) | def print_header():
function print_tail (line 36) | def print_tail():
function print_config (line 49) | def print_config(type, group_name, json_name, default_value):
function print_options (line 52) | def print_options(options):
function print_unnamed_options (line 68) | def print_unnamed_options(options):
function print_man_option (line 85) | def print_man_option(short, long, desc, default):
function print_man_env_option (line 104) | def print_man_env_option(name, desc, default, no_json_key):
function print_man_environment (line 121) | def print_man_environment(options):
function print_man_environment_tail (line 152) | def print_man_environment_tail():
function print_man_header (line 212) | def print_man_header():
function print_man_tail (line 234) | def print_man_tail():
function print_config_option (line 249) | def print_config_option(type, group_name, json_name, default_value, shor...
function print_parse_envloader_options (line 330) | def print_parse_envloader_options(options):
function print_parse_jsonloader_options (line 350) | def print_parse_jsonloader_options(options):
function print_parse_enum_options (line 373) | def print_parse_enum_options(options):
FILE: FEXCore/Scripts/json_ir_doc_generator.py
function get_ir_classes (line 7) | def get_ir_classes(ops, defines):
function print_ir_op_index (line 20) | def print_ir_op_index():
function print_ir_ops (line 29) | def print_ir_ops():
function print_ir_defines (line 52) | def print_ir_defines(defines):
FILE: FEXCore/Scripts/json_ir_generator.py
function ExitError (line 7) | def ExitError(msg):
class IRType (line 12) | class IRType:
method __init__ (line 15) | def __init__(self, IRName, CXXName):
class OpArgument (line 20) | class OpArgument:
method __init__ (line 28) | def __init__(self):
method print (line 37) | def print(self):
class OpDefinition (line 42) | class OpDefinition:
method __init__ (line 66) | def __init__(self):
method print (line 91) | def print(self):
function is_ssa_type (line 101) | def is_ssa_type(op_type: str):
function parse_irtypes (line 104) | def parse_irtypes(irtypes):
function parse_ops (line 109) | def parse_ops(ops):
function print_enums (line 298) | def print_enums(enums):
function print_ir_structs (line 317) | def print_ir_structs(defines):
function print_ir_sizes (line 390) | def print_ir_sizes():
function print_ir_reg_classes (line 421) | def print_ir_reg_classes():
function print_ir_getname (line 452) | def print_ir_getname():
function print_ir_getraargs (line 470) | def print_ir_getraargs():
function print_ir_hassideeffects (line 505) | def print_ir_hassideeffects():
function print_ir_gethasdest (line 534) | def print_ir_gethasdest():
function print_ir_arg_printer (line 554) | def print_ir_arg_printer():
function print_validation (line 593) | def print_validation(op):
function print_ir_allocator_helpers (line 603) | def print_ir_allocator_helpers():
function print_ir_dispatcher_defs (line 824) | def print_ir_dispatcher_defs():
function print_ir_dispatcher_dispatch (line 833) | def print_ir_dispatcher_dispatch():
FILE: FEXCore/Source/Common/BitSet.h
function namespace (line 13) | namespace FEXCore {
FILE: FEXCore/Source/Common/JitSymbols.cpp
type FEXCore (line 9) | namespace FEXCore {
FILE: FEXCore/Source/Common/JitSymbols.h
function namespace (line 12) | namespace FEXCore {
FILE: FEXCore/Source/Common/SoftFloat.h
function X80SoftFloat (line 21) | struct FEX_PACKED X80SoftFloat {
function FEXCORE_PRESERVE_ALL_ATTR (line 66) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 86) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 106) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 126) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 146) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 214) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(softfloat_state* sta...
function FEXCORE_PRESERVE_ALL_ATTR (line 235) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* s...
function FEXCORE_PRESERVE_ALL_ATTR (line 239) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* s...
function FEXCORE_PRESERVE_ALL_ATTR (line 297) | FEXCORE_PRESERVE_ALL_ATTR static void
function extFloat80_t (line 325) | extFloat80_t Zero {0, 0};
function float128_t (line 356) | static const float128_t one {0x0ULL, 0x3fff000000000000ULL};
function FEXCORE_PRESERVE_ALL_ATTR (line 361) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(softfloat_state* sta...
function FEXCORE_PRESERVE_ALL_ATTR (line 385) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(softfloat_state* sta...
function FEXCORE_PRESERVE_ALL_ATTR (line 408) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 435) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 461) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(softfloat_state* stat...
function FEXCORE_PRESERVE_ALL_ATTR (line 487) | FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(softfloat_state* sta...
function ToF32 (line 506) | float ToF32(softfloat_state* state) const {
function ToF64 (line 511) | double ToF64(softfloat_state* state) const {
function BIGFLOAT (line 522) | BIGFLOAT ToFMax(softfloat_state* state) const {
function ToI16 (line 533) | int16_t ToI16(softfloat_state* state) const {
function ToI32 (line 543) | int32_t ToI32(softfloat_state* state) const {
function ToI64 (line 547) | int64_t ToI64(softfloat_state* state) const {
function ToUI64 (line 551) | uint64_t ToUI64(softfloat_state* state) const {
function operator (line 573) | operator void*() {
function extFloat80_t (line 620) | extFloat80_t Result {}
function IsNan (line 626) | static bool IsNan(const X80SoftFloat& lhs) {
function SignBit (line 630) | static bool SignBit(const X80SoftFloat& lhs) {
function FEXCORE_PRESERVE_ALL_ATTR (line 641) | FEXCORE_PRESERVE_ALL_ATTR static bool HandleInfinityOp(softfloat_state* ...
FILE: FEXCore/Source/Common/StringConv.h
function namespace (line 8) | namespace FEXCore::StrConv {
function Conv (line 25) | inline bool Conv(std::string_view Value, fextl::string* Result) {
FILE: FEXCore/Source/Common/VectorRegType.h
function namespace (line 11) | namespace FEXCore {
FILE: FEXCore/Source/Interface/Config/Config.cpp
type FEXCore::Context (line 28) | namespace FEXCore::Context {
class Context (line 29) | class Context
type FEXCore::Config (line 32) | namespace FEXCore::Config {
type detail (line 33) | namespace detail {
type Paths (line 42) | enum Paths {
function SetDataDirectory (line 54) | void SetDataDirectory(const std::string_view Path, bool Global) {
function SetConfigDirectory (line 58) | void SetConfigDirectory(const std::string_view Path, bool Global) {
function SetConfigFileLocation (line 62) | void SetConfigFileLocation(const std::string_view Path, bool Global) {
function GetApplicationConfig (line 93) | fextl::string GetApplicationConfig(const std::string_view Program, boo...
class MetaLayer (line 114) | class MetaLayer
method MetaLayer (line 131) | MetaLayer(const LayerType _Type)
method GetConv (line 138) | std::optional<T> GetConv(ConfigOption Option) {
class MetaLayer (line 129) | class MetaLayer final : public FEXCore::Config::Layer {
method MetaLayer (line 131) | MetaLayer(const LayerType _Type)
method GetConv (line 138) | std::optional<T> GetConv(ConfigOption Option) {
function Initialize (line 236) | void Initialize() {
function Shutdown (line 241) | void Shutdown() {
function Load (line 246) | void Load() {
function ExpandPath (line 255) | fextl::string ExpandPath(const fextl::string& ContainerPrefix, const f...
function FindContainer (line 307) | fextl::string FindContainer() {
function FindContainerPrefix (line 319) | fextl::string FindContainerPrefix() {
function ReloadMetaLayer (line 335) | void ReloadMetaLayer() {
function AddLayer (line 414) | void AddLayer(fextl::unique_ptr<FEXCore::Config::Layer> _Layer) {
function Exists (line 418) | bool Exists(ConfigOption Option) {
function All (line 422) | std::optional<StringArrayType*> All(ConfigOption Option) {
function Get (line 426) | std::optional<fextl::string*> Get(ConfigOption Option) {
function GetConv (line 431) | std::optional<T> GetConv(ConfigOption Option) {
function Set (line 441) | void Set(ConfigOption Option, std::string_view Data) {
function Erase (line 445) | void Erase(ConfigOption Option) {
function T (line 450) | T Value<T>::GetIfExists(FEXCore::Config::ConfigOption Option, T Defaul...
FILE: FEXCore/Source/Interface/Context/Context.cpp
type FEXCore::Context (line 17) | namespace FEXCore::Context {
FILE: FEXCore/Source/Interface/Context/Context.h
function namespace (line 28) | namespace FEXCore {
function namespace (line 48) | namespace FEXCore::Context {
function SetCodeMapWriter (line 198) | void SetCodeMapWriter(fextl::unique_ptr<CodeMapWriter> Writer) override {
function FlushAndCloseCodeMap (line 202) | void FlushAndCloseCodeMap() override {
function MarkMonoDetected (line 230) | void MarkMonoDetected() override {
function StrictSplitLockMutex (line 268) | uint32_t StrictSplitLockMutex {}
function SignalDelegator (line 280) | SignalDelegator* SignalDelegation {}
type GenerateIRResult (line 293) | struct GenerateIRResult {
type CompileCodeResult (line 304) | struct CompileCodeResult {
function SetHardwareTSOSupport (line 337) | void SetHardwareTSOSupport(bool HardwareTSOSupported) override {
function EnableExitOnHLT (line 342) | void EnableExitOnHLT() override {
function final (line 388) | struct CustomIRHandlerEntry final {
FILE: FEXCore/Source/Interface/Core/Addressing.cpp
type FEXCore::IR (line 8) | namespace FEXCore::IR {
function Ref (line 10) | Ref LoadEffectiveAddress(IREmitter* IREmit, const AddressMode& A, IR::...
function AddressMode (line 54) | AddressMode SelectAddressMode(IREmitter* IREmit, const AddressMode& A,...
FILE: FEXCore/Source/Interface/Core/Addressing.h
function namespace (line 7) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
type FEXCore::CPU (line 26) | namespace FEXCore::CPU {
type x64 (line 43) | namespace x64 {
type x32 (line 232) | namespace x32 {
FILE: FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
function namespace (line 24) | namespace FEXCore::Context {
function namespace (line 27) | namespace FEXCore::X86State {
type class (line 112) | enum class
type SpillStaticRegOptions (line 138) | struct SpillStaticRegOptions
function NZCV (line 142) | bool NZCV {true};
type FillStaticRegOptions (line 145) | struct FillStaticRegOptions
function FPRFillMask (line 149) | uint32_t FPRFillMask {~0U};
FILE: FEXCore/Source/Interface/Core/CPUBackend.cpp
type FEXCore (line 19) | namespace FEXCore {
type CPU (line 20) | namespace CPU {
type LUTType (line 69) | struct LUTType {
type LUTType (line 99) | struct LUTType {
type LUTType (line 130) | struct LUTType {
type LUTType (line 158) | struct LUTType {
type LUTType (line 201) | struct LUTType {
type LUTType (line 224) | struct LUTType {
type LUTType (line 245) | struct LUTType {
function GuestToHostMap (line 348) | GuestToHostMap& GetLookupCache(const CodeBuffer& Buffer) {
FILE: FEXCore/Source/Interface/Core/CPUBackend.h
function namespace (line 20) | namespace FEXCore::CPU {
function namespace (line 24) | namespace FEXCore {
FILE: FEXCore/Source/Interface/Core/CPUID.cpp
type FEXCore (line 25) | namespace FEXCore {
type ProductNames (line 26) | namespace ProductNames {
function GetCPUID_Syscall (line 102) | uint32_t GetCPUID_Syscall() {
type CPUFamily (line 108) | struct CPUFamily {
function GenerateFamily (line 117) | constexpr static uint32_t GenerateFamily(const CPUFamily Family) {
function GetCycleCounterFrequency (line 144) | uint64_t GetCycleCounterFrequency() {
function GetCPUID_TPIDRRO (line 150) | uint32_t GetCPUID_TPIDRRO() {
type CPUMIDR (line 179) | struct CPUMIDR {
function GetCycleCounterFrequency (line 411) | uint64_t GetCycleCounterFrequency() {
FILE: FEXCore/Source/Interface/Core/CPUID.h
function namespace (line 13) | namespace Context {
function DoesXCRFunctionReportConstantData (line 79) | bool DoesXCRFunctionReportConstantData(uint32_t Function) const {
type class (line 84) | enum class
type class (line 88) | enum class
type FunctionConstant (line 92) | struct FunctionConstant {
function FunctionConstant (line 97) | static constexpr FunctionConstant DoesFunctionReportConstantData(uint32_...
FILE: FEXCore/Source/Interface/Core/CodeCache.cpp
type FEXCore (line 25) | namespace FEXCore {
type FEXCore::Context (line 218) | namespace FEXCore::Context {
type CodeCacheHeader (line 234) | struct CodeCacheHeader {
FILE: FEXCore/Source/Interface/Core/Core.cpp
type FEXCore::Context (line 80) | namespace FEXCore::Context {
type GetFrameBlockInfoResult (line 108) | struct GetFrameBlockInfoResult {
function GetFrameBlockInfoResult (line 112) | static GetFrameBlockInfoResult GetFrameBlockInfo(FEXCore::Core::CpuSta...
function IRDumper (line 497) | static void IRDumper(FEXCore::Core::InternalThreadState* Thread, IR::I...
FILE: FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
type FEXCore::CPU (line 31) | namespace FEXCore::CPU {
function SleepThread (line 33) | static void SleepThread(FEXCore::Context::ContextImpl* CTX, FEXCore::C...
function SignalDelegatorConfig (line 1702) | SignalDelegatorConfig Dispatcher::MakeSignalDelegatorConfig() const {
FILE: FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
function namespace (line 14) | namespace FEXCore {
function namespace (line 19) | namespace FEXCore::Core {
function namespace (line 24) | namespace FEXCore::Context {
function namespace (line 28) | namespace FEXCore::CPU {
FILE: FEXCore/Source/Interface/Core/Frontend.cpp
type FEXCore::Frontend (line 28) | namespace FEXCore::Frontend {
function MapModRMToReg (line 33) | static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits...
function MapVEXToReg (line 61) | static uint32_t MapVEXToReg(uint8_t vvvv, bool HasXMM) {
type Encodings (line 216) | struct Encodings {
FILE: FEXCore/Source/Interface/Core/Frontend.h
function namespace (line 19) | namespace FEXCore::Context {
function namespace (line 22) | namespace FEXCore::HLE {
type class (line 29) | enum class
function final (line 38) | struct DecodedBlocks final {
function final (line 48) | struct DecodedBlockInformation final {
function DecodedBlockInformation (line 60) | const DecodedBlockInformation* GetDecodedBlockInfo() const {
function DecodedMinAddress (line 64) | uint64_t DecodedMinAddress {}
function DecodedMaxAddress (line 65) | uint64_t DecodedMaxAddress {~0ULL};
function InstructionSize (line 135) | uint8_t InstructionSize {}
function LastEscapePrefix (line 137) | uint8_t LastEscapePrefix {}
function EntryPoint (line 141) | uint64_t EntryPoint {}
function MaxCondBranchForward (line 142) | uint64_t MaxCondBranchForward {}
function SectionMinAddress (line 145) | uint64_t SectionMinAddress {}
function NextBlockStartAddress (line 146) | uint64_t NextBlockStartAddress {~0ULL};
FILE: FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h
function namespace (line 11) | namespace FEXCore::CPU {
function FEXCORE_PRESERVE_ALL_ATTR (line 39) | FEXCORE_PRESERVE_ALL_ATTR static void HandleX87Exception(const softfloat...
function class (line 47) | class ScopedSoftFloatState {
type OpHandlers (line 70) | struct OpHandlers
function ScopedSoftFloatState (line 73) | ScopedSoftFloatState State {FCW, Frame};
function FEXCORE_PRESERVE_ALL_ATTR (line 77) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle8(uint16_t FCW, dou...
type OpHandlers (line 85) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 86) | FEXCORE_PRESERVE_ALL_ATTR static uint64_t handle(uint16_t FCW, VectorReg...
type OpHandlers (line 108) | struct OpHandlers
function ScopedSoftFloatState (line 111) | ScopedSoftFloatState State {FCW, Frame};
function FEXCORE_PRESERVE_ALL_ATTR (line 115) | FEXCORE_PRESERVE_ALL_ATTR static double handle8(uint16_t FCW, VectorRegT...
type OpHandlers (line 123) | struct OpHandlers
function ScopedSoftFloatState (line 126) | ScopedSoftFloatState State {FCW, Frame};
function ScopedSoftFloatState (line 132) | ScopedSoftFloatState State {FCW, Frame};
function ScopedSoftFloatState (line 138) | ScopedSoftFloatState State {FCW, Frame};
function ScopedSoftFloatState (line 144) | ScopedSoftFloatState State {FCW, Frame};
function ScopedSoftFloatState (line 157) | ScopedSoftFloatState State {FCW, Frame};
function FEXCORE_PRESERVE_ALL_ATTR (line 161) | FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8t(uint16_t FCW, VectorRe...
function OP_F80CVTTOINT (line 169) | struct OpHandlers<IR::OP_F80CVTTOINT> {
type OpHandlers (line 182) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 183) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 191) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 192) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 200) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 201) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 209) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 210) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 218) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 219) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 227) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 228) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 236) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 237) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegPairType handle(uint16_t FCW, ...
function OP_F80XTRACT_EXP (line 245) | struct OpHandlers<IR::OP_F80XTRACT_EXP> {
function OP_F80XTRACT_SIG (line 253) | struct OpHandlers<IR::OP_F80XTRACT_SIG> {
type OpHandlers (line 261) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 262) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 270) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 271) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 279) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 280) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 288) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 289) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 297) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 298) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 306) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 307) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 315) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 316) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 324) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 325) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
type OpHandlers (line 333) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 334) | FEXCORE_PRESERVE_ALL_ATTR static VectorRegType handle(uint16_t FCW, Vect...
function OP_F64SIN (line 342) | struct OpHandlers<IR::OP_F64SIN> {
function OP_F64COS (line 350) | struct OpHandlers<IR::OP_F64COS> {
type OpHandlers (line 358) | struct OpHandlers
function FEXCORE_PRESERVE_ALL_ATTR (line 359) | FEXCORE_PRESERVE_ALL_ATTR static VectorScalarF64Pair handle(double src, ...
function OP_F64TAN (line 373) | struct OpHandlers<IR::OP_F64TAN> {
function OP_F64F2XM1 (line 381) | struct OpHandlers<IR::OP_F64F2XM1> {
function OP_F64ATAN (line 389) | struct OpHandlers<IR::OP_F64ATAN> {
function OP_F64FPREM (line 397) | struct OpHandlers<IR::OP_F64FPREM> {
function OP_F64FPREM1 (line 405) | struct OpHandlers<IR::OP_F64FPREM1> {
function OP_F64FYL2X (line 413) | struct OpHandlers<IR::OP_F64FYL2X> {
function OP_F64SCALE (line 421) | struct OpHandlers<IR::OP_F64SCALE> {
function OP_F80BCDSTORE (line 433) | struct OpHandlers<IR::OP_F80BCDSTORE> {
FILE: FEXCore/Source/Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h
function namespace (line 6) | namespace FEXCore::IR {
function namespace (line 10) | namespace FEXCore::CPU {
FILE: FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
type FEXCore::CPU (line 11) | namespace FEXCore::CPU {
function FallbackInfo (line 14) | static FallbackInfo GetFallbackInfo(R (*fn)(Args...), FEXCore::Core::F...
FILE: FEXCore/Source/Interface/Core/Interpreter/Fallbacks/StringCompareFallbacks.cpp
type FEXCore::CPU (line 11) | namespace FEXCore::CPU {
function FEXCORE_PRESERVE_ALL_ATTR (line 13) | FEXCORE_PRESERVE_ALL_ATTR static int32_t GetImplicitLength(FEXCore::Ve...
function FEXCORE_PRESERVE_ALL_ATTR (line 40) | FEXCORE_PRESERVE_ALL_ATTR static int32_t GetImplicitLength(FEXCore::Ve...
function FEXCORE_PRESERVE_ALL_ATTR (line 79) | FEXCORE_PRESERVE_ALL_ATTR uint32_t OpHandlers<IR::OP_VPCMPISTRX>::hand...
FILE: FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h
type OpHandlers (line 17) | struct OpHandlers
type class (line 18) | enum class
function SourceData (line 25) | enum class SourceData {
FILE: FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
function namespace (line 9) | namespace FEXCore::IR {
function namespace (line 14) | namespace FEXCore::CPU {
FILE: FEXCore/Source/Interface/Core/JIT/ALUOps.cpp
type FEXCore::CPU (line 14) | namespace FEXCore::CPU {
function DEF_OP (line 43) | DEF_OP(Constant) {
function DEF_OP (line 57) | DEF_OP(EntrypointOffset) {
function DEF_OP (line 70) | DEF_OP(InlineConstant) {
function DEF_OP (line 74) | DEF_OP(InlineEntrypointOffset) {
function DEF_OP (line 78) | DEF_OP(CycleCounter) {
function DEF_OP (line 93) | DEF_OP(AddShift) {
function DEF_OP (line 99) | DEF_OP(AddNZCV) {
function DEF_OP (line 119) | DEF_OP(AdcNZCV) {
function DEF_OP (line 125) | DEF_OP(AdcWithFlags) {
function DEF_OP (line 131) | DEF_OP(AdcZeroWithFlags) {
function DEF_OP (line 139) | DEF_OP(AdcZero) {
function DEF_OP (line 146) | DEF_OP(Adc) {
function DEF_OP (line 152) | DEF_OP(SbbWithFlags) {
function DEF_OP (line 158) | DEF_OP(SbbNZCV) {
function DEF_OP (line 164) | DEF_OP(Sbb) {
function DEF_OP (line 170) | DEF_OP(TestNZ) {
function DEF_OP (line 206) | DEF_OP(TestZ) {
function DEF_OP (line 230) | DEF_OP(SubShift) {
function DEF_OP (line 236) | DEF_OP(SubNZCV) {
function DEF_OP (line 264) | DEF_OP(CmpPairZ) {
function DEF_OP (line 285) | DEF_OP(CarryInvert) {
function DEF_OP (line 290) | DEF_OP(RmifNZCV) {
function DEF_OP (line 297) | DEF_OP(SetSmallNZV) {
function DEF_OP (line 311) | DEF_OP(AXFlag) {
function DEF_OP (line 330) | DEF_OP(Parity) {
function DEF_OP (line 351) | DEF_OP(CondAddNZCV) {
function DEF_OP (line 365) | DEF_OP(CondSubNZCV) {
function DEF_OP (line 379) | DEF_OP(Neg) {
function DEF_OP (line 389) | DEF_OP(Mul) {
function DEF_OP (line 395) | DEF_OP(UMul) {
function DEF_OP (line 401) | DEF_OP(UMull) {
function DEF_OP (line 406) | DEF_OP(SMull) {
function DEF_OP (line 411) | DEF_OP(MulH) {
function DEF_OP (line 431) | DEF_OP(UMulH) {
function DEF_OP (line 451) | DEF_OP(Orlshl) {
function DEF_OP (line 465) | DEF_OP(Orlshr) {
function DEF_OP (line 480) | DEF_OP(Ornror) {
function DEF_OP (line 490) | DEF_OP(AndWithFlags) {
function DEF_OP (line 525) | DEF_OP(AndShift) {
function DEF_OP (line 531) | DEF_OP(XorShift) {
function DEF_OP (line 537) | DEF_OP(XornShift) {
function DEF_OP (line 543) | DEF_OP(Ashr) {
function DEF_OP (line 572) | DEF_OP(ShiftFlags) {
function DEF_OP (line 670) | DEF_OP(RotateFlags) {
function DEF_OP (line 714) | DEF_OP(Extr) {
function DEF_OP (line 723) | DEF_OP(PDep) {
function DEF_OP (line 799) | DEF_OP(PExt) {
function DEF_OP (line 855) | DEF_OP(Div) {
function DEF_OP (line 955) | DEF_OP(UDiv) {
function DEF_OP (line 1038) | DEF_OP(Not) {
function DEF_OP (line 1047) | DEF_OP(Popcount) {
function DEF_OP (line 1100) | DEF_OP(FindLSB) {
function DEF_OP (line 1113) | DEF_OP(FindMSB) {
function DEF_OP (line 1136) | DEF_OP(FindTrailingZeroes) {
function DEF_OP (line 1161) | DEF_OP(CountLeadingZeroes) {
function DEF_OP (line 1183) | DEF_OP(Rev) {
function DEF_OP (line 1200) | DEF_OP(Rbit) {
function DEF_OP (line 1213) | DEF_OP(Bfi) {
function DEF_OP (line 1245) | DEF_OP(Bfxil) {
function DEF_OP (line 1269) | DEF_OP(Bfe) {
function DEF_OP (line 1288) | DEF_OP(Sbfe) {
function DEF_OP (line 1296) | DEF_OP(MaskGenerateFromBitWidth) {
function DEF_OP (line 1306) | DEF_OP(Select) {
function DEF_OP (line 1355) | DEF_OP(NZCVSelect) {
function DEF_OP (line 1384) | DEF_OP(NZCVSelectV) {
function DEF_OP (line 1392) | DEF_OP(NZCVSelectIncrement) {
function DEF_OP (line 1398) | DEF_OP(VExtractToGPR) {
function DEF_OP (line 1456) | DEF_OP(Float_ToGPR_ZS) {
function DEF_OP (line 1469) | DEF_OP(Float_ToGPR_S) {
function DEF_OP (line 1484) | DEF_OP(FCmp) {
FILE: FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp
type FEXCore::CPU (line 13) | namespace FEXCore::CPU {
function GetNamedSymbolLiteral (line 14) | uint64_t GetNamedSymbolLiteral(FEXCore::Context::ContextImpl& CTX, FEX...
FILE: FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp
type FEXCore::CPU (line 12) | namespace FEXCore::CPU {
function DEF_OP (line 13) | DEF_OP(CASPair) {
function DEF_OP (line 92) | DEF_OP(CAS) {
function DEF_OP (line 141) | DEF_OP(AtomicSwap) {
function DEF_OP (line 170) | DEF_OP(AtomicFetchAdd) {
function DEF_OP (line 191) | DEF_OP(AtomicFetchSub) {
function DEF_OP (line 213) | DEF_OP(AtomicFetchAnd) {
function DEF_OP (line 235) | DEF_OP(AtomicFetchCLR) {
function DEF_OP (line 256) | DEF_OP(AtomicFetchOr) {
function DEF_OP (line 277) | DEF_OP(AtomicFetchXor) {
function DEF_OP (line 298) | DEF_OP(AtomicFetchNeg) {
function DEF_OP (line 327) | DEF_OP(TelemetrySetValue) {
FILE: FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
type FEXCore::CPU (line 20) | namespace FEXCore::CPU {
function DEF_OP (line 22) | DEF_OP(CallbackReturn) {
function DEF_OP (line 46) | DEF_OP(ExitFunction) {
function DEF_OP (line 213) | DEF_OP(Jump) {
function DEF_OP (line 219) | DEF_OP(CondJump) {
function DEF_OP (line 256) | DEF_OP(Syscall) {
function DEF_OP (line 327) | DEF_OP(Thunk) {
function DEF_OP (line 357) | DEF_OP(ValidateCode) {
function DEF_OP (line 405) | DEF_OP(ThreadRemoveCodeEntry) {
function DEF_OP (line 429) | DEF_OP(CPUID) {
function DEF_OP (line 473) | DEF_OP(XGetBV) {
FILE: FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp
type FEXCore::CPU (line 11) | namespace FEXCore::CPU {
function DEF_OP (line 12) | DEF_OP(VInsGPR) {
function DEF_OP (line 87) | DEF_OP(VCastFromGPR) {
function DEF_OP (line 107) | DEF_OP(VLoadTwoGPRs) {
function DEF_OP (line 117) | DEF_OP(VDupFromGPR) {
function DEF_OP (line 136) | DEF_OP(Float_FromGPR_S) {
function DEF_OP (line 176) | DEF_OP(Float_FToF) {
function DEF_OP (line 212) | DEF_OP(Vector_SToF) {
function DEF_OP (line 245) | DEF_OP(Vector_FToZS) {
function DEF_OP (line 278) | DEF_OP(Vector_FToS) {
function DEF_OP (line 307) | DEF_OP(Vector_FToF) {
function DEF_OP (line 377) | DEF_OP(VFCVTL2) {
function DEF_OP (line 388) | DEF_OP(VFCVTN2) {
function DEF_OP (line 410) | DEF_OP(Vector_FToI) {
function DEF_OP (line 472) | DEF_OP(Vector_FToISized) {
function DEF_OP (line 526) | DEF_OP(Vector_F64ToI32) {
FILE: FEXCore/Source/Interface/Core/JIT/DebugData.h
function namespace (line 9) | namespace FEXCore::CPU {
function namespace (line 13) | namespace FEXCore::Core {
FILE: FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp
type FEXCore::CPU (line 10) | namespace FEXCore::CPU {
function DEF_OP (line 12) | DEF_OP(VAESImc) {
function DEF_OP (line 17) | DEF_OP(VAESEnc) {
function DEF_OP (line 42) | DEF_OP(VAESEncLast) {
function DEF_OP (line 65) | DEF_OP(VAESDec) {
function DEF_OP (line 90) | DEF_OP(VAESDecLast) {
function DEF_OP (line 113) | DEF_OP(VAESKeyGenAssist) {
function DEF_OP (line 146) | DEF_OP(CRC32) {
function DEF_OP (line 162) | DEF_OP(VSha1H) {
function DEF_OP (line 171) | DEF_OP(VSha1C) {
function DEF_OP (line 191) | DEF_OP(VSha1M) {
function DEF_OP (line 211) | DEF_OP(VSha1P) {
function DEF_OP (line 231) | DEF_OP(VSha1SU1) {
function DEF_OP (line 250) | DEF_OP(VSha256H) {
function DEF_OP (line 270) | DEF_OP(VSha256H2) {
function DEF_OP (line 290) | DEF_OP(VSha256U0) {
function DEF_OP (line 306) | DEF_OP(VSha256U1) {
function DEF_OP (line 323) | DEF_OP(PCLMUL) {
FILE: FEXCore/Source/Interface/Core/JIT/JIT.cpp
type DivRem (line 42) | struct DivRem {
function LUDIV (line 47) | static struct DivRem LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t D...
function LDIV (line 56) | static struct DivRem
function PrintValue (line 66) | static void
function PrintVectorValue (line 71) | static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
type FEXCore::CPU (line 76) | namespace FEXCore::CPU {
function DirectBlockDelinker (line 496) | static void DirectBlockDelinker(FEXCore::Context::ExitFunctionLinkData...
function IndirectBlockDelinker (line 514) | static void IndirectBlockDelinker(FEXCore::Context::ExitFunctionLinkDa...
function CreateArm64JITCore (line 1167) | fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Con...
FILE: FEXCore/Source/Interface/Core/JIT/JITClass.h
function namespace (line 37) | namespace FEXCore::Core {
function namespace (line 40) | namespace FEXCore::Context {
function namespace (line 43) | namespace FEXCore::IR {
function namespace (line 47) | namespace FEXCore::CPU {
type NamedSymbolLiteralPair (line 542) | struct NamedSymbolLiteralPair {
function SpillSlots (line 602) | uint32_t SpillSlots {}
FILE: FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp
type FEXCore::CPU (line 18) | namespace FEXCore::CPU {
function DEF_OP (line 20) | DEF_OP(LoadContext) {
function DEF_OP (line 52) | DEF_OP(LoadContextPair) {
function DEF_OP (line 77) | DEF_OP(StoreContext) {
function DEF_OP (line 109) | DEF_OP(StoreContextPair) {
function DEF_OP (line 135) | DEF_OP(LoadRegister) {
function DEF_OP (line 160) | DEF_OP(LoadPF) {
function DEF_OP (line 168) | DEF_OP(LoadAF) {
function DEF_OP (line 176) | DEF_OP(StoreRegister) {
function DEF_OP (line 201) | DEF_OP(StorePF) {
function DEF_OP (line 212) | DEF_OP(StoreAF) {
function DEF_OP (line 223) | DEF_OP(LoadContextIndexed) {
function DEF_OP (line 286) | DEF_OP(StoreContextIndexed) {
function DEF_OP (line 352) | DEF_OP(FormContextAddress) {
function DEF_OP (line 371) | DEF_OP(SpillRegister) {
function DEF_OP (line 460) | DEF_OP(FillRegister) {
function DEF_OP (line 549) | DEF_OP(LoadNZCV) {
function DEF_OP (line 555) | DEF_OP(StoreNZCV) {
function DEF_OP (line 561) | DEF_OP(LoadDF) {
function DEF_OP (line 569) | DEF_OP(ContextClear) {
function DEF_OP (line 704) | DEF_OP(LoadMem) {
function DEF_OP (line 741) | DEF_OP(LoadMemPair) {
function DEF_OP (line 767) | DEF_OP(LoadMemTSO) {
function DEF_OP (line 855) | DEF_OP(VLoadVectorMasked) {
function DEF_OP (line 959) | DEF_OP(VStoreVectorMasked) {
function DEF_OP (line 1170) | DEF_OP(VLoadVectorGatherMasked) {
function DEF_OP (line 1268) | DEF_OP(VLoadVectorGatherMaskedQPS) {
function DEF_OP (line 1349) | DEF_OP(VLoadVectorElement) {
function DEF_OP (line 1387) | DEF_OP(VStoreVectorElement) {
function DEF_OP (line 1421) | DEF_OP(VBroadcastFromMem) {
function DEF_OP (line 1468) | DEF_OP(Push) {
function DEF_OP (line 1553) | DEF_OP(PushTwo) {
function DEF_OP (line 1576) | DEF_OP(Pop) {
function DEF_OP (line 1608) | DEF_OP(PopTwo) {
function DEF_OP (line 1639) | DEF_OP(StoreMem) {
function DEF_OP (line 1690) | DEF_OP(StoreMemX87SVEOptPredicate) {
function DEF_OP (line 1721) | DEF_OP(LoadMemX87SVEOptPredicate) {
function DEF_OP (line 1752) | DEF_OP(StoreMemPair) {
function DEF_OP (line 1778) | DEF_OP(StoreMemTSO) {
function DEF_OP (line 1851) | DEF_OP(MemSet) {
function DEF_OP (line 2086) | DEF_OP(MemCpy) {
function DEF_OP (line 2391) | DEF_OP(CacheLineClear) {
function DEF_OP (line 2420) | DEF_OP(CacheLineClean) {
function DEF_OP (line 2443) | DEF_OP(CacheLineZero) {
function DEF_OP (line 2464) | DEF_OP(Prefetch) {
function DEF_OP (line 2502) | DEF_OP(VStoreNonTemporal) {
function DEF_OP (line 2528) | DEF_OP(VStoreNonTemporalPair) {
function DEF_OP (line 2544) | DEF_OP(VLoadNonTemporal) {
FILE: FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
type FEXCore::CPU (line 20) | namespace FEXCore::CPU {
function DEF_OP (line 22) | DEF_OP(WFET) {
function DEF_OP (line 42) | DEF_OP(GuestOpcode) {
function DEF_OP (line 48) | DEF_OP(Fence) {
function DEF_OP (line 59) | DEF_OP(Break) {
function DEF_OP (line 99) | DEF_OP(GetRoundingMode) {
function DEF_OP (line 120) | DEF_OP(SetRoundingMode) {
function DEF_OP (line 151) | DEF_OP(PushRoundingMode) {
function DEF_OP (line 179) | DEF_OP(PopRoundingMode) {
function DEF_OP (line 184) | DEF_OP(Print) {
function DEF_OP (line 213) | DEF_OP(ProcessorID) {
function DEF_OP (line 290) | DEF_OP(RDRAND) {
function DEF_OP (line 296) | DEF_OP(Yield) {
function DEF_OP (line 300) | DEF_OP(MonoBackpatcherWrite) {
FILE: FEXCore/Source/Interface/Core/JIT/MoveOps.cpp
type FEXCore::CPU (line 10) | namespace FEXCore::CPU {
function DEF_OP (line 11) | DEF_OP(Copy) {
function DEF_OP (line 17) | DEF_OP(RMWHandle) {
FILE: FEXCore/Source/Interface/Core/JIT/Relocations.h
function namespace (line 6) | namespace FEXCore::Context {
function namespace (line 10) | namespace FEXCore::CPU {
FILE: FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
type FEXCore::CPU (line 13) | namespace FEXCore::CPU {
function DEF_OP (line 442) | DEF_OP(VFMinScalarInsert) {
function DEF_OP (line 469) | DEF_OP(VFMaxScalarInsert) {
function DEF_OP (line 495) | DEF_OP(VFSqrtScalarInsert) {
function DEF_OP (line 514) | DEF_OP(VFRSqrtScalarInsert) {
function DEF_OP (line 552) | DEF_OP(VFRecpScalarInsert) {
function DEF_OP (line 589) | DEF_OP(VFToFScalarInsert) {
function DEF_OP (line 635) | DEF_OP(VSToFVectorInsert) {
function DEF_OP (line 692) | DEF_OP(VSToFGPRInsert) {
function DEF_OP (line 740) | DEF_OP(VFToIScalarInsert) {
function DEF_OP (line 767) | DEF_OP(VFCMPScalarInsert) {
function DEF_OP (line 927) | DEF_OP(VectorImm) {
function DEF_OP (line 958) | DEF_OP(LoadNamedVectorConstant) {
function DEF_OP (line 1009) | DEF_OP(LoadNamedVectorIndexedConstant) {
function DEF_OP (line 1033) | DEF_OP(VMov) {
function DEF_OP (line 1083) | DEF_OP(VAddP) {
function DEF_OP (line 1120) | DEF_OP(VOrn) {
function DEF_OP (line 1143) | DEF_OP(VFAddV) {
function DEF_OP (line 1174) | DEF_OP(VAddV) {
function DEF_OP (line 1210) | DEF_OP(VUMinV) {
function DEF_OP (line 1231) | DEF_OP(VUMaxV) {
function DEF_OP (line 1252) | DEF_OP(VURAvg) {
function DEF_OP (line 1285) | DEF_OP(VFAddP) {
function DEF_OP (line 1319) | DEF_OP(VFDiv) {
function DEF_OP (line 1375) | DEF_OP(VFMin) {
function DEF_OP (line 1448) | DEF_OP(VFMax) {
function DEF_OP (line 1506) | DEF_OP(VFRecp) {
function DEF_OP (line 1575) | DEF_OP(VFRecpPrecision) {
function DEF_OP (line 1615) | DEF_OP(VFRSqrt) {
function DEF_OP (line 1684) | DEF_OP(VFRSqrtPrecision) {
function DEF_OP (line 1728) | DEF_OP(VNot) {
function DEF_OP (line 1744) | DEF_OP(VUMin) {
function DEF_OP (line 1793) | DEF_OP(VSMin) {
function DEF_OP (line 1842) | DEF_OP(VUMax) {
function DEF_OP (line 1891) | DEF_OP(VSMax) {
function DEF_OP (line 1940) | DEF_OP(VBSL) {
function DEF_OP (line 2007) | DEF_OP(VCMPEQ) {
function DEF_OP (line 2047) | DEF_OP(VCMPEQZ) {
function DEF_OP (line 2089) | DEF_OP(VCMPGT) {
function DEF_OP (line 2129) | DEF_OP(VCMPGTZ) {
function DEF_OP (line 2168) | DEF_OP(VCMPLTZ) {
function DEF_OP (line 2207) | DEF_OP(VFCMPEQ) {
function DEF_OP (line 2246) | DEF_OP(VFCMPNEQ) {
function DEF_OP (line 2287) | DEF_OP(VFCMPLT) {
function DEF_OP (line 2326) | DEF_OP(VFCMPGT) {
function DEF_OP (line 2365) | DEF_OP(VFCMPLE) {
function DEF_OP (line 2404) | DEF_OP(VFCMPORD) {
function DEF_OP (line 2455) | DEF_OP(VFCMPUNO) {
function DEF_OP (line 2505) | DEF_OP(VUShl) {
function DEF_OP (line 2561) | DEF_OP(VUShr) {
function DEF_OP (line 2620) | DEF_OP(VSShr) {
function DEF_OP (line 2679) | DEF_OP(VUShlS) {
function DEF_OP (line 2708) | DEF_OP(VUShrS) {
function DEF_OP (line 2738) | DEF_OP(VUShrSWide) {
function DEF_OP (line 2804) | DEF_OP(VSShrSWide) {
function DEF_OP (line 2870) | DEF_OP(VUShlSWide) {
function DEF_OP (line 2935) | DEF_OP(VSShrS) {
function DEF_OP (line 2965) | DEF_OP(VInsElement) {
function DEF_OP (line 3045) | DEF_OP(VDupElement) {
function DEF_OP (line 3070) | DEF_OP(VExtr) {
function DEF_OP (line 3118) | DEF_OP(VUShrI) {
function DEF_OP (line 3161) | DEF_OP(VUShraI) {
function DEF_OP (line 3203) | DEF_OP(VSShrI) {
function DEF_OP (line 3243) | DEF_OP(VShlI) {
function DEF_OP (line 3286) | DEF_OP(VUShrNI) {
function DEF_OP (line 3310) | DEF_OP(VUShrNI2) {
function DEF_OP (line 3348) | DEF_OP(VSXTL) {
function DEF_OP (line 3366) | DEF_OP(VSXTL2) {
function DEF_OP (line 3384) | DEF_OP(VSSHLL) {
function DEF_OP (line 3406) | DEF_OP(VSSHLL2) {
function DEF_OP (line 3428) | DEF_OP(VUXTL) {
function DEF_OP (line 3446) | DEF_OP(VUXTL2) {
function DEF_OP (line 3464) | DEF_OP(VSQXTN) {
function DEF_OP (line 3516) | DEF_OP(VSQXTN2) {
function DEF_OP (line 3560) | DEF_OP(VSQXTNPair) {
function DEF_OP (line 3604) | DEF_OP(VSQXTUN) {
function DEF_OP (line 3623) | DEF_OP(VSQXTUN2) {
function DEF_OP (line 3669) | DEF_OP(VSQXTUNPair) {
function DEF_OP (line 3713) | DEF_OP(VSRSHR) {
function DEF_OP (line 3743) | DEF_OP(VSQSHL) {
function DEF_OP (line 3773) | DEF_OP(VMul) {
function DEF_OP (line 3793) | DEF_OP(VUMull) {
function DEF_OP (line 3814) | DEF_OP(VSMull) {
function DEF_OP (line 3835) | DEF_OP(VUMull2) {
function DEF_OP (line 3856) | DEF_OP(VSMull2) {
function DEF_OP (line 3877) | DEF_OP(VUMulH) {
function DEF_OP (line 3928) | DEF_OP(VSMulH) {
function DEF_OP (line 3979) | DEF_OP(VUABDL) {
function DEF_OP (line 4005) | DEF_OP(VUABDL2) {
function DEF_OP (line 4031) | DEF_OP(VTBL1) {
function DEF_OP (line 4058) | DEF_OP(VTBL2) {
function DEF_OP (line 4102) | DEF_OP(VTBX1) {
function DEF_OP (line 4155) | DEF_OP(VRev32) {
function DEF_OP (line 4193) | DEF_OP(VRev64) {
function DEF_OP (line 4232) | DEF_OP(VFCADD) {
function DEF_OP (line 4274) | DEF_OP(VFMLA) {
function DEF_OP (line 4340) | DEF_OP(VFMLS) {
function DEF_OP (line 4431) | DEF_OP(VFNMLA) {
function DEF_OP (line 4498) | DEF_OP(VFNMLS) {
function DEF_OP (line 4591) | DEF_OP(VFCopySign) {
function DEF_OP (line 4614) | DEF_OP(F64SIN) {
function DEF_OP (line 4627) | DEF_OP(F64COS) {
function DEF_OP (line 4640) | DEF_OP(F64TAN) {
FILE: FEXCore/Source/Interface/Core/LookupCache.cpp
type FEXCore (line 16) | namespace FEXCore {
FILE: FEXCore/Source/Interface/Core/LookupCache.h
function namespace (line 20) | namespace FEXCore {
function LookupCacheBaseLockToken (line 36) | struct LookupCacheReadLockToken : public LookupCacheBaseLockToken {
function AcquireReadLock (line 45) | struct GuestToHostMap {
type BlockEntry (line 84) | struct BlockEntry {
function BlockEntry (line 96) | const BlockEntry& AddBlockMapping(uint64_t Address, const fextl::vector<...
function BlockEntry (line 105) | const BlockEntry* FindBlock(uint64_t Address, const LookupCacheReadLockT...
function Erase (line 113) | bool Erase(uint64_t Address, const LookupCacheWriteLockToken&) {
function InvalidateRange (line 125) | void InvalidateRange(uint64_t Start, uint64_t Length) {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
type FEXCore::IR (line 32) | namespace FEXCore::IR {
function ParityJumpIsJP (line 616) | static bool ParityJumpIsJP(uint8_t OP) {
function Ref (line 621) | Ref OpDispatchBuilder::SelectCC0All1(uint8_t OP) {
function Ref (line 2828) | Ref OpDispatchBuilder::CalculateAFForDecimal(Ref A) {
function Ref (line 4035) | Ref OpDispatchBuilder::GetSegment(uint32_t Flags, uint32_t DefaultPref...
function Ref (line 4084) | Ref OpDispatchBuilder::AppendSegmentOffset(Ref Value, uint32_t Flags, ...
function AddressMode (line 4219) | AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedO...
function Ref (line 4304) | Ref OpDispatchBuilder::LoadSource_WithOpSize(RegClass Class, const X86...
function Ref (line 4356) | Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, IR::OpSize Size, ...
function Ref (line 4394) | Ref OpDispatchBuilder::LoadSource(RegClass Class, const X86Tables::Dec...
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher.h
function namespace (line 29) | namespace FEXCore::IR {
function InvalidateAF (line 1912) | void InvalidateAF() {
function InvalidatePF_AF (line 1917) | void InvalidatePF_AF() {
function CondClass (line 1923) | [[nodiscard]]
function CacheIndexToContextOffset (line 1950) | [[nodiscard]]
function RegClass (line 1959) | [[nodiscard]]
function IR (line 1968) | [[nodiscard]]
function RegCache (line 1979) | struct {
function InvalidateReg (line 1990) | void InvalidateReg(uint8_t Index) {
function Ref (line 1996) | Ref LoadRegCache(uint64_t Offset, uint8_t Index, RegClass Class, IR::OpS...
function RefPair (line 2037) | RefPair AllocatePair(RegClass Class, IR::OpSize Size) {
function RefPair (line 2045) | RefPair LoadContextPair_Uncached(RegClass Class, IR::OpSize Size, unsign...
function RefPair (line 2051) | RefPair LoadRegCachePair(uint64_t Offset, uint8_t Index, RegClass Class,...
function Ref (line 2076) | Ref LoadGPR(uint8_t Reg) {
function Ref (line 2080) | Ref LoadContext(IR::OpSize Size, uint8_t Index) {
function RefPair (line 2084) | RefPair LoadContextPair(IR::OpSize Size, uint8_t Index) {
function Ref (line 2088) | Ref LoadContext(uint8_t Index) {
function Ref (line 2092) | Ref LoadXMMRegister(uint8_t Reg) {
function Ref (line 2096) | Ref LoadDF() {
function StoreContext (line 2100) | void StoreContext(uint8_t Index, Ref Value) {
function InvalidateHighAVXRegisters (line 2111) | void InvalidateHighAVXRegisters() {
function StoreRegister (line 2117) | void StoreRegister(uint8_t Reg, bool FPR, Ref Value) {
function StoreDF (line 2121) | void StoreDF(Ref Value) {
function else (line 2148) | else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) {
function else (line 2150) | else if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) {
function Ref (line 2159) | Ref LoadDir(const unsigned Size) {
function Ref (line 2164) | Ref OffsetByDir(Ref X, const unsigned Size) {
function Ref (line 2285) | Ref CachedNamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_V...
type IndexNamedVectorMapKey (line 2286) | struct IndexNamedVectorMapKey {
function log2_size_in_bytes (line 2289) | uint8_t log2_size_in_bytes {}
function _pad (line 2290) | uint16_t _pad {}
type IndexNamedVectorMapKeyHasher (line 2294) | struct IndexNamedVectorMapKeyHasher {
function Ref (line 2302) | Ref LoadAndCacheNamedVectorConstant(IR::OpSize Size, FEXCore::IR::NamedV...
function Ref (line 2312) | Ref LoadAndCacheIndexedNamedVectorConstant(IR::OpSize Size, FEXCore::IR:...
function Ref (line 2329) | Ref LoadUncachedZeroVector(IR::OpSize Size) {
function Ref (line 2333) | Ref LoadZeroVector(IR::OpSize Size) {
function ClearCachedNamedConstants (line 2339) | void ClearCachedNamedConstants() {
function ZeroShiftResult (line 2352) | void ZeroShiftResult(FEXCore::X86Tables::DecodedOp Op) {
function ChgStateX87_MMX (line 2450) | void ChgStateX87_MMX() override {
function ChgStateMMX_X87 (line 2458) | void ChgStateMMX_X87() override {
function DestIsLockedMem (line 2469) | bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) const {
function DestIsMem (line 2473) | bool DestIsMem(FEXCore::X86Tables::DecodedOp Op) const {
function BlockSetRIP (line 2478) | bool BlockSetRIP {false};
function AddressMode (line 2548) | AddressMode SelectPairAddressMode(AddressMode A, IR::OpSize Size) {
function RefPair (line 2564) | RefPair LoadMemPair(RegClass Class, OpSize Size, Ref Base, uint32_t Offs...
function RefPair (line 2569) | RefPair LoadMemPairFPR(OpSize Size, Ref Base, uint32_t Offset) {
function Ref (line 2631) | Ref Pop(IR::OpSize Size, Ref SP_RMW) {
function Ref (line 2637) | Ref Pop(IR::OpSize Size) {
function Ref (line 2648) | Ref VZeroExtendOperand(OpSize Size, X86Tables::DecodedOperand Op, Ref Va...
function Push (line 2655) | void Push(IR::OpSize Size, Ref Value) {
type ArithRef (line 2662) | struct ArithRef {
function IsConstant (line 2664) | bool IsConstant {}
function ArithRef (line 2704) | ArithRef Bfe(unsigned Start, unsigned Size) {
function ArithRef (line 2712) | ArithRef Sbfe(unsigned Start, unsigned Size) {
function Ref (line 2727) | Ref BfiInto(Ref Bitfield, unsigned Start, unsigned Size) {
function ArithRef (line 2746) | ArithRef MaskBit(OpSize Size) {
function Ref (line 2760) | Ref Ref() {
function ArithRef (line 2769) | ArithRef ARef(Ref R) {
function ArithRef (line 2779) | ArithRef ARef(uint64_t K) {
function SegmentsNeedReadCheck (line 2784) | uint32_t SegmentsNeedReadCheck {~0U};
function InstallToTable (line 2789) | constexpr inline void InstallToTable(auto& FinalTable, const auto& Local...
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
type FEXCore::IR (line 19) | namespace FEXCore::IR {
class OrderedNode (line 20) | class OrderedNode
function Ref (line 114) | Ref OpDispatchBuilder::AVX128_LoadXMMRegister(uint32_t XMM, bool High) {
function Ref (line 621) | Ref OpDispatchBuilder::AVX128_PSIGNImpl(IR::OpSize ElementSize, Ref Sr...
type DataPacking (line 1373) | struct DataPacking {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
type FEXCore::IR (line 16) | namespace FEXCore::IR {
class OrderedNode (line 17) | class OrderedNode
function Ref (line 293) | Ref OpDispatchBuilder::AESKeyGenAssistImpl(OpcodeArgs) {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/DDDTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
type FEXCore::IR (line 19) | namespace FEXCore::IR {
function Ref (line 71) | Ref OpDispatchBuilder::GetPackedRFLAG(uint32_t FlagsMask) {
function Ref (line 174) | Ref OpDispatchBuilder::LoadPFRaw(bool Mask, bool Invert) {
function Ref (line 182) | Ref OpDispatchBuilder::LoadAF() {
function Ref (line 263) | Ref OpDispatchBuilder::IncrementByCarry(OpSize OpSize, Ref Src) {
function Ref (line 269) | Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1...
function Ref (line 304) | Ref OpDispatchBuilder::CalculateFlags_SBB(IR::OpSize SrcSize, Ref Src1...
function Ref (line 338) | Ref OpDispatchBuilder::CalculateFlags_SUB(IR::OpSize SrcSize, Ref Src1...
function Ref (line 368) | Ref OpDispatchBuilder::CalculateFlags_ADD(IR::OpSize SrcSize, Ref Src1...
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F38Tables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/H0F3ATables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/PrimaryGroupTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryGroupTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryModRMTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/SecondaryTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/VEXTables.h
function namespace (line 5) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
type FEXCore::IR (line 24) | namespace FEXCore::IR {
function Ref (line 304) | Ref OpDispatchBuilder::VectorScalarInsertALUOpImpl(OpcodeArgs, IROps I...
function Ref (line 360) | Ref OpDispatchBuilder::VectorScalarUnaryInsertALUOpImpl(OpcodeArgs, IR...
function Ref (line 426) | Ref OpDispatchBuilder::InsertCVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize ...
function Ref (line 473) | Ref OpDispatchBuilder::InsertScalar_CVT_Float_To_FloatImpl(OpcodeArgs,...
function RoundMode (line 508) | RoundMode OpDispatchBuilder::TranslateRoundType(uint8_t Mode) {
function Ref (line 522) | Ref OpDispatchBuilder::InsertScalarRoundImpl(OpcodeArgs, IR::OpSize Ds...
function Ref (line 563) | Ref OpDispatchBuilder::InsertScalarFCMPOpImpl(OpSize Size, IR::OpSize ...
function Ref (line 918) | Ref OpDispatchBuilder::GeneratePSHUFBMask(IR::OpSize SrcSize) {
function Ref (line 932) | Ref OpDispatchBuilder::PSHUFBOpImpl(IR::OpSize SrcSize, Ref Src1, Ref ...
function Ref (line 969) | Ref OpDispatchBuilder::PShufWLane(IR::OpSize Size, FEXCore::IR::IndexN...
function Ref (line 1033) | Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t...
function Ref (line 1314) | Ref OpDispatchBuilder::SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, IR::...
function Ref (line 1576) | Ref OpDispatchBuilder::PINSROpImpl(OpcodeArgs, IR::OpSize ElementSize,...
function Ref (line 1630) | Ref OpDispatchBuilder::InsertPSOpImpl(OpcodeArgs, const X86Tables::Dec...
function Ref (line 1740) | Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, IR::OpSize ElementSize, R...
function Ref (line 1774) | Ref OpDispatchBuilder::PSRLDOpImpl(OpcodeArgs, IR::OpSize ElementSize,...
function Ref (line 1836) | Ref OpDispatchBuilder::PSLLIImpl(OpcodeArgs, IR::OpSize ElementSize, R...
function Ref (line 1872) | Ref OpDispatchBuilder::PSLLImpl(OpcodeArgs, IR::OpSize ElementSize, Re...
function Ref (line 1901) | Ref OpDispatchBuilder::PSRAOpImpl(OpcodeArgs, IR::OpSize ElementSize, ...
function Ref (line 2119) | Ref OpDispatchBuilder::CVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstEle...
function Ref (line 2162) | Ref OpDispatchBuilder::CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSi...
function Ref (line 2208) | Ref OpDispatchBuilder::Vector_CVT_Int_To_FloatImpl(OpcodeArgs, IR::OpS...
function Ref (line 2241) | Ref OpDispatchBuilder::Vector_CVT_Float_To_Int32Impl(OpcodeArgs, IR::O...
function Ref (line 2293) | Ref OpDispatchBuilder::Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::O...
function Ref (line 2485) | Ref OpDispatchBuilder::VFCMPOpImpl(OpSize Size, IR::OpSize ElementSize...
function Ref (line 2600) | Ref OpDispatchBuilder::XSaveBase(X86Tables::DecodedOp Op) {
function Ref (line 2773) | Ref OpDispatchBuilder::GetMXCSR() {
function Ref (line 2944) | Ref OpDispatchBuilder::PALIGNROpImpl(OpcodeArgs, const X86Tables::Deco...
function Ref (line 3067) | Ref OpDispatchBuilder::PMULLOpImpl(OpSize Size, IR::OpSize ElementSize...
function Ref (line 3133) | Ref OpDispatchBuilder::ADDSUBPOpImpl(OpSize Size, IR::OpSize ElementSi...
function Ref (line 3300) | Ref OpDispatchBuilder::PMADDWDOpImpl(IR::OpSize Size, Ref Src1, Ref Sr...
function Ref (line 3343) | Ref OpDispatchBuilder::PMADDUBSWOpImpl(IR::OpSize Size, Ref Src1, Ref ...
function Ref (line 3405) | Ref OpDispatchBuilder::PMULHWOpImpl(OpcodeArgs, bool Signed, Ref Src1,...
function Ref (line 3444) | Ref OpDispatchBuilder::PMULHRSWOpImpl(OpSize Size, Ref Src1, Ref Src2) {
function Ref (line 3490) | Ref OpDispatchBuilder::HSUBPOpImpl(OpSize SrcSize, IR::OpSize ElementS...
function Ref (line 3524) | Ref OpDispatchBuilder::PHSUBOpImpl(OpSize Size, Ref Src1, Ref Src2, IR...
function Ref (line 3555) | Ref OpDispatchBuilder::PHADDSOpImpl(OpSize Size, Ref Src1, Ref Src2) {
function Ref (line 3591) | Ref OpDispatchBuilder::PHSUBSOpImpl(OpSize Size, Ref Src1, Ref Src2) {
function Ref (line 3625) | Ref OpDispatchBuilder::PSADBWOpImpl(IR::OpSize Size, Ref Src1, Ref Src...
function Ref (line 3684) | Ref OpDispatchBuilder::ExtendVectorElementsImpl(OpcodeArgs, IR::OpSize...
function Ref (line 3734) | Ref OpDispatchBuilder::VectorRoundImpl(OpSize Size, IR::OpSize Element...
function Ref (line 3771) | Ref OpDispatchBuilder::VectorBlend(OpSize Size, IR::OpSize ElementSize...
function Ref (line 4123) | Ref OpDispatchBuilder::PHMINPOSUWOpImpl(OpcodeArgs) {
function Ref (line 4167) | Ref OpDispatchBuilder::DPPOpImpl(IR::OpSize DstSize, Ref Src1, Ref Src...
function Ref (line 4356) | Ref OpDispatchBuilder::VDPPSOpImpl(OpcodeArgs, const X86Tables::Decode...
function Ref (line 4429) | Ref OpDispatchBuilder::MPSADBWOpImpl(IR::OpSize SrcSize, Ref Src1, Ref...
function Ref (line 4621) | Ref OpDispatchBuilder::VPERMDIndices(OpSize DstSize, Ref Indices, Ref ...
function Ref (line 4724) | Ref OpDispatchBuilder::VBLENDOpImpl(IR::OpSize VecSize, IR::OpSize Ele...
function Ref (line 4896) | Ref OpDispatchBuilder::VPERMILRegOpImpl(OpSize DstSize, IR::OpSize Ele...
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
type FEXCore::IR (line 23) | namespace FEXCore::IR {
class OrderedNode (line 24) | class OrderedNode
function Ref (line 27) | Ref OpDispatchBuilder::GetX87Top() {
function Ref (line 334) | Ref OpDispatchBuilder::GetX87FTW_Helper() {
function Ref (line 420) | Ref OpDispatchBuilder::ReconstructX87StateFromFSW_Helper(Ref FSW) {
function Ref (line 737) | Ref OpDispatchBuilder::ReconstructFSW_Helper(Ref T) {
FILE: FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
type FEXCore::IR (line 21) | namespace FEXCore::IR {
class OrderedNode (line 22) | class OrderedNode
FILE: FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp
type FEXCore::X86Tables (line 15) | namespace FEXCore::X86Tables {
type Primary_LUT (line 18) | enum Primary_LUT {
FILE: FEXCore/Source/Interface/Core/X86Tables/DDDTables.cpp
type FEXCore::X86Tables (line 13) | namespace FEXCore::X86Tables {
FILE: FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp
type FEXCore::X86Tables (line 14) | namespace FEXCore::X86Tables {
FILE: FEXCore/Source/Interface/Core/X86Tables/H0F3ATables.cpp
type FEXCore::X86Tables (line 16) | namespace FEXCore::X86Tables {
type H0F3A_LUT (line 22) | enum H0F3A_LUT {
FILE: FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp
type FEXCore::X86Tables (line 15) | namespace FEXCore::X86Tables {
type PrimaryGroup_LUT (line 17) | enum PrimaryGroup_LUT {
FILE: FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp
type FEXCore::X86Tables (line 14) | namespace FEXCore::X86Tables {
type SecondGroup_LUT (line 22) | enum SecondGroup_LUT {
FILE: FEXCore/Source/Interface/Core/X86Tables/SecondaryModRMTables.cpp
type FEXCore::X86Tables (line 13) | namespace FEXCore::X86Tables {
FILE: FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp
type FEXCore::X86Tables (line 15) | namespace FEXCore::X86Tables {
type Secondary_LUT (line 18) | enum Secondary_LUT {
FILE: FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
type FEXCore::X86Tables (line 13) | namespace FEXCore::X86Tables {
type AVX128 (line 16) | namespace AVX128 {
type AVX256 (line 462) | namespace AVX256 {
FILE: FEXCore/Source/Interface/Core/X86Tables/X86Tables.h
function namespace (line 19) | namespace FEXCore::IR {
function namespace (line 23) | namespace FEXCore::X86Tables {
type DecodedInst (line 211) | struct DecodedInst {
type InstType (line 248) | enum InstType {
function namespace (line 311) | namespace InstFlags {
function OpToIndex (line 444) | constexpr uint8_t OpToIndex(uint8_t Op) {
type X86InstInfo (line 477) | struct X86InstInfo
type X86InstInfo (line 480) | struct X86InstInfo {
function GenerateTable (line 557) | static inline void GenerateTable(X86InstInfo* FinalTable, const X86Table...
function GenerateTableWithCopy (line 575) | inline void GenerateTableWithCopy(X86InstInfo* FinalTable, const X86Tabl...
function GenerateX87Table (line 595) | inline void GenerateX87Table(X86InstInfo* FinalTable, const X86TablesInf...
FILE: FEXCore/Source/Interface/Core/X86Tables/X87Tables.cpp
type FEXCore::X86Tables (line 13) | namespace FEXCore::X86Tables {
FILE: FEXCore/Source/Interface/GDBJIT/GDBJIT.cpp
type jit_actions_t (line 14) | enum jit_actions_t { JIT_NOACTION = 0, JIT_REGISTER_FN, JIT_UNREGISTER_FN }
type jit_code_entry (line 16) | struct jit_code_entry {
type jit_descriptor (line 23) | struct jit_descriptor {
function __jit_debug_register_code (line 38) | void __attribute__((noinline)) __jit_debug_register_code() {
type FEXCore (line 43) | namespace FEXCore {
function GDBJITRegister (line 45) | void GDBJITRegister(const FEXCore::ExecutableFileInfo& Entry, uintptr_...
function GDBJITRegister (line 116) | void GDBJITRegister(const FEXCore::ExecutableFileInfo&, uintptr_t, uin...
type FEXCore (line 115) | namespace FEXCore {
function GDBJITRegister (line 45) | void GDBJITRegister(const FEXCore::ExecutableFileInfo& Entry, uintptr_...
function GDBJITRegister (line 116) | void GDBJITRegister(const FEXCore::ExecutableFileInfo&, uintptr_t, uin...
FILE: FEXCore/Source/Interface/GDBJIT/GDBJIT.h
function namespace (line 6) | namespace FEXCore {
FILE: FEXCore/Source/Interface/IR/IR.h
function namespace (line 20) | namespace FEXCore::IR {
type OrderedNodeHeader (line 204) | struct OrderedNodeHeader {
function class (line 226) | class OrderedNode final {
function class (line 420) | class NodeIterator {
type class (line 498) | enum class
type class (line 510) | enum class
type class (line 519) | enum class
type class (line 526) | enum class
function OpSize (line 531) | static inline OpSize SizeToOpSize(uint8_t Size) {
function OpSizeToSize (line 547) | static inline uint8_t OpSizeToSize(IR::OpSize Size) {
function OpSizeAsBits (line 562) | static inline uint16_t OpSizeAsBits(IR::OpSize Size) {
type std (line 691) | struct std
function const (line 692) | size_t operator()(const FEXCore::IR::NodeID& ID) const noexcept {
FILE: FEXCore/Source/Interface/IR/IRDumper.cpp
type FEXCore::IR (line 23) | namespace FEXCore::IR {
function PrintArg (line 33) | static void PrintArg(fextl::stringstream* out, const IRListView*, cons...
function PrintArg (line 37) | static void PrintArg(fextl::stringstream* out, const IRListView*, uint...
function PrintArg (line 41) | static void PrintArg(fextl::stringstream* out, const IRListView*, Cond...
function PrintArg (line 54) | static void PrintArg(fextl::stringstream* out, const IRListView*, MemO...
function PrintArg (line 64) | static void PrintArg(fextl::stringstream* out, const IRListView*, RegC...
function PrintArg (line 78) | static void PrintArg(fextl::stringstream* out, const IRListView* IR, O...
function PrintArg (line 127) | static void PrintArg(fextl::stringstream* out, const IRListView*, Fenc...
function PrintArg (line 139) | static void PrintArg(fextl::stringstream* out, const IRListView*, Roun...
function PrintArg (line 152) | static void PrintArg(fextl::stringstream* out, const IRListView*, Cons...
function PrintArg (line 163) | static void PrintArg(fextl::stringstream* out, const IRListView*, Name...
function PrintArg (line 255) | static void PrintArg(fextl::stringstream* out, const IRListView*, Inde...
function PrintArg (line 281) | static void PrintArg(fextl::stringstream* out, const IRListView*, OpSi...
function PrintArg (line 298) | static void PrintArg(fextl::stringstream* out, const IRListView*, Floa...
function PrintArg (line 312) | static void PrintArg(fextl::stringstream* out, const IRListView*, FEXC...
function PrintArg (line 319) | static void PrintArg(fextl::stringstream* out, const IRListView*, Shif...
function PrintArg (line 331) | static void PrintArg(fextl::stringstream* out, const IRListView*, Bran...
function PrintArg (line 343) | static void PrintArg(fextl::stringstream* out, const IRListView*, cons...
function Dump (line 347) | void Dump(fextl::stringstream* out, const IRListView* IR) {
FILE: FEXCore/Source/Interface/IR/IREmitter.cpp
type FEXCore::IR (line 18) | namespace FEXCore::IR {
function IsFragmentExit (line 20) | static bool IsFragmentExit(FEXCore::IR::IROps Op) {
function IsBlockExit (line 28) | bool IsBlockExit(FEXCore::IR::IROps Op) {
function RegClass (line 36) | RegClass IREmitter::WalkFindRegClass(Ref Node) {
FILE: FEXCore/Source/Interface/IR/IREmitter.h
function namespace (line 18) | namespace FEXCore::IR {
function IsValueInlineConstant (line 331) | bool IsValueInlineConstant(OrderedNodeWrapper ssa) {
function Ref (line 345) | Ref UnwrapNode(OrderedNodeWrapper ssa) {
function OrderedNodeWrapper (line 349) | OrderedNodeWrapper WrapNode(Ref node) {
function NodeIterator (line 353) | NodeIterator GetIterator(OrderedNodeWrapper wrapper) {
function ReplaceUsesWithAfter (line 359) | void ReplaceUsesWithAfter(Ref Node, Ref NewNode, AllNodesIterator After) {
function ReplaceUsesWithAfter (line 364) | void ReplaceUsesWithAfter(Ref Node, Ref NewNode, Ref After) {
function CopyData (line 376) | void CopyData(const IREmitter& rhs) {
function SetWriteCursor (line 390) | void SetWriteCursor(Ref Node) {
function SetWriteCursorBefore (line 395) | void SetWriteCursorBefore(Ref Node) {
function Ref (line 403) | Ref GetWriteCursor() {
function Ref (line 407) | Ref GetCurrentBlock() {
function LinkCodeBlocks (line 450) | void LinkCodeBlocks(Ref CodeNode, Ref Next) {
function Ref (line 468) | Ref CreateNode(IROp_Header* Op) {
function Ref (line 482) | Ref GetNode(uint32_t SSANode) {
function Ref (line 488) | Ref EmplaceOrphanedNode(Ref OldNode) {
function virtual (line 499) | virtual void RecordX87Use() {}
function virtual (line 500) | virtual void ChgStateX87_MMX() {}
function virtual (line 501) | virtual void ChgStateMMX_X87() {}
function virtual (line 502) | virtual void SaveNZCV(IROps Op) {}
function Ref (line 509) | Ref InvalidNode {}
function Ref (line 510) | Ref CurrentCodeBlock {}
function Entry (line 512) | uint64_t Entry {}
function SupportsTSOImm9 (line 513) | bool SupportsTSOImm9 {}
FILE: FEXCore/Source/Interface/IR/IntrusiveIRList.h
function namespace (line 15) | namespace FEXCore::IR {
function Data (line 98) | uintptr_t Data {}
function List (line 99) | uintptr_t List {}
function DataCurrentOffset (line 100) | size_t DataCurrentOffset {0}
function ListCurrentOffset (line 101) | size_t ListCurrentOffset {0};
function ReownOrClaimBuffer (line 123) | void ReownOrClaimBuffer() {
function DelayedDisownBuffer (line 128) | void DelayedDisownBuffer() {
function class (line 136) | class IRListView final {
function end (line 251) | struct CodeRange {
function CodeRange (line 299) | [[nodiscard]]
function AllCodeRange (line 304) | [[nodiscard]]
function iterator (line 321) | [[nodiscard]]
function iterator (line 337) | [[nodiscard]]
function iterator (line 344) | [[nodiscard]]
FILE: FEXCore/Source/Interface/IR/PassManager.cpp
type FEXCore::IR (line 18) | namespace FEXCore::IR {
class IREmitter (line 19) | class IREmitter
FILE: FEXCore/Source/Interface/IR/PassManager.h
function namespace (line 20) | namespace FEXCore::Context {
function namespace (line 24) | namespace FEXCore::HLE {
function namespace (line 28) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/IR/Passes.h
function namespace (line 6) | namespace FEXCore {
function namespace (line 11) | namespace FEXCore::Utils {
function namespace (line 15) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/IR/Passes/IRDumperPass.cpp
type FEXCore::IR::Debug (line 17) | namespace FEXCore::IR::Debug {
class IRDumper (line 18) | class IRDumper final : public FEXCore::IR::Pass {
function CreateIRDumper (line 70) | fextl::unique_ptr<FEXCore::IR::Pass> CreateIRDumper() {
FILE: FEXCore/Source/Interface/IR/Passes/IRValidation.cpp
type FEXCore::IR::Validation (line 28) | namespace FEXCore::IR::Validation {
function CreateIRValidation (line 274) | fextl::unique_ptr<FEXCore::IR::Pass> CreateIRValidation() {
FILE: FEXCore/Source/Interface/IR/Passes/IRValidation.h
function namespace (line 9) | namespace FEXCore::IR::Validation {
FILE: FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
type FEXCore::IR (line 32) | namespace FEXCore::IR {
type FlagInfoUnpacked (line 34) | struct FlagInfoUnpacked {
type FlagInfo (line 55) | struct FlagInfo {
method Pack (line 58) | static constexpr struct FlagInfo Pack(struct FlagInfoUnpacked F) {
method Trivial (line 64) | bool Trivial() const {
method Read (line 68) | unsigned Read() const {
method Write (line 72) | unsigned Write() const {
method CanEliminate (line 76) | bool CanEliminate() const {
method Special (line 80) | bool Special() const {
method IROps (line 84) | IROps Replacement() const {
method IROps (line 88) | IROps ReplacementNoWrite() const {
method Bits (line 93) | unsigned Bits(unsigned Start, unsigned Count) const {
type BlockInfo (line 98) | struct BlockInfo {
type ControlFlowGraph (line 105) | struct ControlFlowGraph {
method Init (line 109) | void Init(fextl::deque<uint32_t>& Worklist, uint32_t BlockCount) {
method BlockInfo (line 124) | BlockInfo* Get(uint32_t Block) {
method BlockInfo (line 128) | BlockInfo* Get(IROp_CodeBlock* Block) {
method BlockInfo (line 132) | BlockInfo* Get(OrderedNodeWrapper Block) {
method RecordEdge (line 136) | void RecordEdge(uint32_t From, OrderedNodeWrapper To) {
method AddWorklist (line 141) | void AddWorklist(fextl::deque<uint32_t>& Worklist, uint32_t Block) {
class DeadFlagCalculationEliminination (line 150) | class DeadFlagCalculationEliminination final : public FEXCore::IR::Pass {
function FlagInfo (line 199) | constexpr FlagInfo ClassifyConst(IROps Op) {
method Pack (line 58) | static constexpr struct FlagInfo Pack(struct FlagInfoUnpacked F) {
method Trivial (line 64) | bool Trivial() const {
method Read (line 68) | unsigned Read() const {
method Write (line 72) | unsigned Write() const {
method CanEliminate (line 76) | bool CanEliminate() const {
method Special (line 80) | bool Special() const {
method IROps (line 84) | IROps Replacement() const {
method IROps (line 88) | IROps ReplacementNoWrite() const {
method Bits (line 93) | unsigned Bits(unsigned Start, unsigned Count) const {
function FlagInfo (line 345) | FlagInfo DeadFlagCalculationEliminination::Classify(IROp_Header* IROp) {
method Pack (line 58) | static constexpr struct FlagInfo Pack(struct FlagInfoUnpacked F) {
method Trivial (line 64) | bool Trivial() const {
method Read (line 68) | unsigned Read() const {
method Write (line 72) | unsigned Write() const {
method CanEliminate (line 76) | bool CanEliminate() const {
method Special (line 80) | bool Special() const {
method IROps (line 84) | IROps Replacement() const {
method IROps (line 88) | IROps ReplacementNoWrite() const {
method Bits (line 93) | unsigned Bits(unsigned Start, unsigned Count) const {
function CondClass (line 457) | CondClass DeadFlagCalculationEliminination::X86ToArmFloatCond(CondClas...
type FlagInfo (line 566) | struct FlagInfo
method Pack (line 58) | static constexpr struct FlagInfo Pack(struct FlagInfoUnpacked F) {
method Trivial (line 64) | bool Trivial() const {
method Read (line 68) | unsigned Read() const {
method Write (line 72) | unsigned Write() const {
method CanEliminate (line 76) | bool CanEliminate() const {
method Special (line 80) | bool Special() const {
method IROps (line 84) | IROps Replacement() const {
method IROps (line 88) | IROps ReplacementNoWrite() const {
method Bits (line 93) | unsigned Bits(unsigned Start, unsigned Count) const {
function CreateDeadFlagCalculationEliminination (line 750) | fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminin...
FILE: FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
type FEXCore::IR (line 24) | namespace FEXCore::IR {
type RegisterClassData (line 26) | struct RegisterClassData {
function GetRegClassFromNode (line 36) | IR::RegClass GetRegClassFromNode(IR::IRListView* IR, IR::IROp_Header* ...
class ConstrainedRAPass (line 55) | class ConstrainedRAPass final : public RegisterAllocationPass {
method ConstrainedRAPass (line 57) | explicit ConstrainedRAPass(const FEXCore::CPUIDEmu* CPUID)
method Rematerializable (line 88) | bool Rematerializable(IROp_Header* IROp) {
method Ref (line 92) | Ref InsertFill(Ref Node) {
method IsValidArg (line 116) | bool IsValidArg(OrderedNodeWrapper Arg) {
method RegisterClassData (line 125) | RegisterClassData* GetClass(PhysicalRegister Reg) {
method GetRegBits (line 129) | uint32_t GetRegBits(PhysicalRegister Reg) {
method IsInRegisterFile (line 133) | bool IsInRegisterFile(Ref Node) {
method FreeReg (line 143) | void FreeReg(PhysicalRegister Reg) {
method HasSource (line 152) | bool HasSource(IROp_Header* I, PhysicalRegister Reg) {
method Ref (line 175) | Ref DecodeSRANode(const IROp_Header* IROp, Ref Node) {
method PhysicalRegister (line 191) | PhysicalRegister DecodeSRAReg(const IROp_Header* IROp, Ref Node) {
method IsTrivial (line 212) | bool IsTrivial(Ref Node, const IROp_Header* Header) {
method CalculateNextUses (line 228) | void CalculateNextUses(IROp_CodeBlock* BlockIROp, IROp_Header* Until) {
method SpillReg (line 272) | void SpillReg(RegisterClassData* Class, IROp_CodeBlock* Block, IROp_...
method RemapReg (line 345) | void RemapReg(Ref Node, PhysicalRegister Reg) {
method SetReg (line 356) | void SetReg(Ref Node, PhysicalRegister Reg) {
method AssignReg (line 369) | void AssignReg(IROp_Header* IROp, IROp_CodeBlock* Block, Ref CodeNod...
function KillMove (line 444) | inline bool KillMove(IROp_Header* LastOp, IROp_Header* IROp, Ref LastN...
function IsSignext (line 462) | inline bool IsSignext(const IROp_Header* IROp, OrderedNodeWrapper Src,...
function IsZero (line 471) | inline bool IsZero(const IROp_Header* IROp) {
function CreateRegisterAllocationPass (line 784) | fextl::unique_ptr<IR::RegisterAllocationPass> CreateRegisterAllocation...
FILE: FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.h
function namespace (line 14) | namespace FEXCore::IR {
FILE: FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp
type FEXCore::IR (line 32) | namespace FEXCore::IR {
function MMBaseOffset (line 35) | inline uint32_t MMBaseOffset() {
function DeriveOp (line 42) | void DeriveOp(Ref& RefV, IROps NewOp, IREmitter::IRPair<T> Expr) {
type StackSlot (line 47) | enum class StackSlot { UNUSED, INVALID, VALID }
class FixedSizeStack (line 52) | class FixedSizeStack {
type StackSlotEntry (line 54) | struct StackSlotEntry final {
method FixedSizeStack (line 67) | FixedSizeStack()
method push (line 70) | void push(const T& Value) {
method rotate (line 76) | void rotate(bool Right = true) {
method pop (line 86) | void pop() {
method StackSlotEntry (line 91) | const StackSlotEntry& top(size_t Offset = 0) const {
method setTop (line 95) | void setTop(T Value, size_t Offset = 0) {
method isValid (line 99) | bool isValid(size_t Offset) const {
method clear (line 103) | void clear() {
method dump (line 110) | void dump() const {
method setTagInvalid (line 124) | void setTagInvalid(size_t Index) {
method getValidMask (line 129) | uint8_t getValidMask() {
method getInvalidMask (line 140) | uint8_t getInvalidMask() {
class X87StackOptimization (line 154) | class X87StackOptimization final : public Pass {
method X87StackOptimization (line 156) | X87StackOptimization(const FEXCore::HostFeatures& Features, OpSize G...
method F80SplitStore_Helper (line 173) | void F80SplitStore_Helper(const IROp_StoreStackMem* Op, Ref StackNod...
method Store80BitToMem (line 189) | void Store80BitToMem(const IROp_StoreStackMem* Op, Ref StackNode, Re...
method StoreStackMem_Helper (line 204) | void StoreStackMem_Helper(const IROp_StoreStackMem* Op, Ref StackNod...
method StoreStackMem_Reduced_Helper (line 232) | void StoreStackMem_Reduced_Helper(const IROp_StoreStackMem* Op, Ref ...
type StackMemberInfo (line 294) | struct StackMemberInfo {
method StackMemberInfo (line 295) | StackMemberInfo() = delete;
method StackMemberInfo (line 296) | StackMemberInfo(Ref Data)
method StackMemberInfo (line 298) | StackMemberInfo(Ref Data, Ref Source, OpSize Size)
type StackMemberData (line 303) | struct StackMemberData final {
function Ref (line 387) | inline Ref X87StackOptimization::GetConstant(ssize_t Offset) {
function Ref (line 407) | inline Ref X87StackOptimization::GetTopWithCache_Slow() {
function Ref (line 414) | inline Ref X87StackOptimization::GetOffsetTopWithCache_Slow(uint8_t Of...
function Ref (line 435) | inline Ref X87StackOptimization::GetOffsetTopAddressWithCache_Slow(uin...
function Ref (line 452) | inline Ref X87StackOptimization::GetFTW() {
function Ref (line 464) | inline Ref X87StackOptimization::GetX87ValidTag_Slow(uint8_t Offset) {
function Ref (line 473) | inline Ref X87StackOptimization::LoadStackValueAtOffset_Slow(uint8_t O...
function Ref (line 492) | inline Ref X87StackOptimization::RotateRight8(uint32_t V, Ref Amount) {
function Ref (line 505) | inline Ref X87StackOptimization::LoadStackValue(uint8_t Offset) {
function Ref (line 672) | Ref X87StackOptimization::SynchronizeStackValues() {
function CreateX87StackOptimizationPass (line 1228) | fextl::unique_ptr<Pass> CreateX87StackOptimizationPass(const FEXCore::Ho...
FILE: FEXCore/Source/Interface/IR/RegisterAllocationData.h
function namespace (line 7) | namespace FEXCore::IR {
FILE: FEXCore/Source/Utils/Allocator.cpp
type fextl::pmr (line 28) | namespace fextl::pmr {
type FEXCore::Allocator (line 36) | namespace FEXCore::Allocator {
function VirtualName (line 61) | void VirtualName(const char* Name, void* Ptr, size_t Size) {
function FEX_munmap (line 72) | int FEX_munmap(void* addr, size_t length) {
function AssignHookOverrides (line 85) | static void AssignHookOverrides(size_t PageSize) {
function SetupHooks (line 92) | void SetupHooks(size_t PageSize) {
function ClearHooks (line 97) | void ClearHooks() {
function FEX_DEFAULT_VISIBILITY (line 106) | FEX_DEFAULT_VISIBILITY size_t DetermineVASize() {
function CollectMemoryGaps (line 147) | fextl::vector<MemoryRegion> CollectMemoryGaps(uintptr_t Begin, uintptr...
function StealMemoryRegion (line 225) | fextl::vector<MemoryRegion> StealMemoryRegion(uintptr_t Begin, uintptr...
function Setup48BitAllocatorIfExists (line 274) | fextl::vector<MemoryRegion> Setup48BitAllocatorIfExists(size_t PageSiz...
function ReclaimMemoryRegion (line 290) | void ReclaimMemoryRegion(const fextl::vector<MemoryRegion>& Regions) {
function LockBeforeFork (line 296) | void LockBeforeFork(FEXCore::Core::InternalThreadState* Thread) {
function UnlockAfterFork (line 302) | void UnlockAfterFork(FEXCore::Core::InternalThreadState* Thread, bool ...
FILE: FEXCore/Source/Utils/Allocator.h
function namespace (line 4) | namespace FEXCore::Core {
function namespace (line 8) | namespace FEXCore::Allocator {
FILE: FEXCore/Source/Utils/Allocator/64BitAllocator.cpp
type Alloc::OSAllocator (line 33) | namespace Alloc::OSAllocator {
class OSAllocator_64Bit (line 37) | class OSAllocator_64Bit final : public Alloc::HostAllocator {
method DeallocateSlab (line 46) | void DeallocateSlab(void* Ptr, size_t Size) override {}
method LockBeforeFork (line 51) | void LockBeforeFork(FEXCore::Core::InternalThreadState* Thread) over...
method UnlockAfterFork (line 55) | void UnlockAfterFork(FEXCore::Core::InternalThreadState* Thread, boo...
type ReservedVMARegion (line 73) | struct ReservedVMARegion {
method MergeReservedRegionIfPossible (line 79) | bool MergeReservedRegionIfPossible(ReservedVMARegion* Region, uintpt...
type LiveVMARegion (line 91) | struct LiveVMARegion {
method GetFEXManagedVMARegionSize (line 106) | static size_t GetFEXManagedVMARegionSize(size_t Size) {
method InitializeVMARegionUsed (line 117) | static void InitializeVMARegionUsed(LiveVMARegion* Region, size_t ...
method LiveVMARegion (line 157) | LiveVMARegion* MakeRegionActive(ReservedRegionListType::iterator Res...
method GetFEXManagedVMARegionSize (line 106) | static size_t GetFEXManagedVMARegionSize(size_t Size) {
method InitializeVMARegionUsed (line 117) | static void InitializeVMARegionUsed(LiveVMARegion* Region, size_t ...
type RangeResult (line 277) | struct RangeResult final {
function Create64BitAllocator (line 575) | fextl::unique_ptr<Alloc::HostAllocator> Create64BitAllocator() {
type alloc_delete (line 580) | struct alloc_delete : public std::default_delete<T> {
function make_alloc_unique (line 600) | fextl::unique_ptr<T> make_alloc_unique(FEXCore::Allocator::MemoryRegio...
function Create64BitAllocatorWithRegions (line 623) | fextl::unique_ptr<Alloc::HostAllocator> Create64BitAllocatorWithRegion...
type FEXCore::Allocator (line 638) | namespace FEXCore::Allocator {
function RegisterTLSData (line 639) | void RegisterTLSData(FEXCore::Core::InternalThreadState* Thread) {
function UninstallTLSData (line 643) | void UninstallTLSData(FEXCore::Core::InternalThreadState* Thread) {
FILE: FEXCore/Source/Utils/Allocator/FlexBitSet.h
function Get (line 22) | bool Get(size_t Element) const {
function TestAndClear (line 25) | bool TestAndClear(size_t Element) {
function TestAndSet (line 30) | bool TestAndSet(size_t Element) {
function Set (line 35) | void Set(size_t Element) {
function Clear (line 38) | void Clear(size_t Element) {
function MemClear (line 41) | void MemClear(size_t Elements) {
function MemSet (line 44) | void MemSet(size_t Elements) {
type BitsetScanResults (line 49) | struct BitsetScanResults {
function const (line 158) | bool operator[](size_t Element) const {
function SizeInBits (line 164) | constexpr static size_t SizeInBits(uint64_t Elements) {
function SizeInBytes (line 168) | constexpr static size_t SizeInBytes(uint64_t Elements) {
FILE: FEXCore/Source/Utils/Allocator/HostAllocator.h
function namespace (line 10) | namespace FEXCore::Allocator {
function namespace (line 13) | namespace FEXCore::Core {
function namespace (line 17) | namespace Alloc {
function namespace (line 53) | namespace Alloc::OSAllocator {
FILE: FEXCore/Source/Utils/Allocator/IntrusiveArenaAllocator.h
function do_deallocate (line 59) | void do_deallocate(void*, std::size_t, std::size_t) override {
function do_is_equal (line 63) | bool do_is_equal(const fex_pmr::memory_resource& other) const noexcept o...
function LastAllocation (line 74) | size_t LastAllocation {}
function AllocatedOffset (line 120) | uintptr_t AllocatedOffset {}
function do_deallocate (line 167) | void do_deallocate(void* p, std::size_t bytes, std::size_t alignment) ov...
function do_is_equal (line 181) | bool do_is_equal(const fex_pmr::memory_resource& other) const noexcept o...
function FreePages (line 192) | uint64_t FreePages {}
function LastAllocatedPageOffset (line 193) | size_t LastAllocatedPageOffset {}
FILE: FEXCore/Source/Utils/AllocatorHooks.cpp
type FEXCore::Allocator (line 21) | namespace FEXCore::Allocator {
function posix_memalign (line 59) | int posix_memalign(void** r, size_t a, size_t s) {
function free (line 68) | void free(void* ptr) {
function malloc_usable_size (line 71) | size_t malloc_usable_size(void* ptr) {
function aligned_free (line 77) | void aligned_free(void* ptr) {
function InitializeThread (line 81) | void InitializeThread() {
function AlignUp (line 86) | [[nodiscard]]
function FEX_rp_memory_commit (line 134) | static void FEX_rp_memory_commit(void* address, size_t size) {
function FEX_rp_memory_decommit (line 138) | static void FEX_rp_memory_decommit(void* address, size_t size) {
function FEX_rp_memory_unmap (line 148) | static void FEX_rp_memory_unmap(void* address, size_t offset, size_t m...
function SetupAllocatorHooks (line 157) | void SetupAllocatorHooks(mmap_hook_type MMapHook, munmap_hook_type Mun...
function InitializeAllocator (line 171) | void InitializeAllocator(size_t PageSize) {
function InitializeThread (line 183) | void InitializeThread() {}
function posix_memalign (line 197) | int posix_memalign(void** r, size_t a, size_t s) {
function free (line 203) | void free(void* ptr) {
function malloc_usable_size (line 206) | size_t malloc_usable_size(void* ptr) {
function aligned_free (line 212) | void aligned_free(void* ptr) {
function SetupAllocatorHooks (line 216) | void SetupAllocatorHooks(mmap_hook_type MMapHook, munmap_hook_type Mun...
function InitializeAllocator (line 218) | void InitializeAllocator(size_t PageSize) {}
FILE: FEXCore/Source/Utils/AllocatorOverride.cpp
type FEXCore::Allocator (line 49) | namespace FEXCore::Allocator {
function FEX_DEFAULT_VISIBILITY (line 79) | FEX_DEFAULT_VISIBILITY void YesIKnowImNotSupposedToUseTheGlibcAllocato...
function SetupFaultEvaluate (line 85) | void SetupFaultEvaluate() {
function ClearFaultEvaluate (line 90) | void ClearFaultEvaluate() {
function EvaluateReturnAddress (line 95) | void EvaluateReturnAddress(void* Return) {
function fault_free (line 125) | void fault_free(void* ptr) {
function fault_posix_memalign (line 145) | int fault_posix_memalign(void** r, size_t a, size_t s) {
function fault_malloc_usable_size (line 149) | size_t fault_malloc_usable_size(void* ptr) {
FILE: FEXCore/Source/Utils/ArchHelpers/Arm64.cpp
type FEXCore::ArchHelpers::Arm64 (line 16) | namespace FEXCore::ArchHelpers::Arm64 {
type ExclusiveAtomicPairType (line 80) | enum ExclusiveAtomicPairType {
function GetRdReg (line 110) | static constexpr uint32_t GetRdReg(uint32_t Instr) {
function GetRnReg (line 114) | static constexpr uint32_t GetRnReg(uint32_t Instr) {
function GetRmReg (line 118) | static constexpr uint32_t GetRmReg(uint32_t Instr) {
function ClearICache (line 122) | static void ClearICache(void* Begin, std::size_t Length) {
function __uint128_t (line 126) | static __uint128_t LoadAcquire128(uint64_t Addr) {
function LoadAcquire64 (line 146) | static uint64_t LoadAcquire64(uint64_t Addr) {
function StoreCAS64 (line 151) | static bool StoreCAS64(uint64_t& Expected, uint64_t Val, uint64_t Addr) {
function LoadAcquire32 (line 156) | static uint32_t LoadAcquire32(uint64_t Addr) {
function StoreCAS32 (line 161) | static bool StoreCAS32(uint32_t& Expected, uint32_t Val, uint64_t Addr) {
function LoadAcquire8 (line 166) | static uint8_t LoadAcquire8(uint64_t Addr) {
function StoreCAS8 (line 171) | static bool StoreCAS8(uint8_t& Expected, uint8_t Val, uint64_t Addr) {
function DoLoad16 (line 176) | static uint16_t DoLoad16(uint64_t Addr) {
function DoLoad32 (line 238) | static uint32_t DoLoad32(uint64_t Addr) {
function DoLoad64 (line 283) | static uint64_t DoLoad64(uint64_t Addr) {
function __uint128_t (line 312) | static __uint128_t DoLoad128(uint64_t Addr) {
function RunCASPAL (line 338) | static bool RunCASPAL(uint64_t* GPRs, uint32_t Size, uint32_t DesiredR...
function HandleCASPAL (line 523) | static bool HandleCASPAL(uint32_t Instr, uint64_t* GPRs, uint32_t* Str...
function HandleCASPAL_ARMv8 (line 535) | static uint64_t HandleCASPAL_ARMv8(uint32_t Instr, uintptr_t ProgramCo...
function DoCAS16 (line 626) | static uint16_t DoCAS16(uint16_t DesiredSrc, uint16_t ExpectedSrc, uin...
function DoCAS32 (line 901) | static uint32_t DoCAS32(uint32_t DesiredSrc, uint32_t ExpectedSrc, uin...
function DoCAS64 (line 1133) | static uint64_t DoCAS64(uint64_t DesiredSrc, uint64_t ExpectedSrc, uin...
function DoCAS (line 1299) | static std::optional<uint64_t> DoCAS(uint32_t Size, uint64_t Desired, ...
function RunCASAL (line 1354) | static bool RunCASAL(uint64_t* GPRs, uint32_t Size, uint32_t DesiredRe...
function HandleCASAL (line 1368) | static bool HandleCASAL(uint64_t* GPRs, uint32_t Instr, uint32_t* Stri...
function HandleAtomicMemOp (line 1377) | static bool HandleAtomicMemOp(uint32_t Instr, uint64_t* GPRs, uint32_t...
function HandleAtomicLoad (line 1527) | static bool HandleAtomicLoad(uint32_t Instr, uint64_t* GPRs, int64_t O...
function HandleAtomicStore (line 1566) | static bool HandleAtomicStore(uint32_t Instr, uint64_t* GPRs, int64_t ...
function HandleCAS_NoAtomics (line 1625) | static uint64_t HandleCAS_NoAtomics(uintptr_t ProgramCounter, uint64_t...
function HandleAtomicLoadstoreExclusive (line 1668) | static uint64_t HandleAtomicLoadstoreExclusive(uintptr_t ProgramCounte...
function HandleUnalignedAccess (line 1923) | [[nodiscard]]
FILE: FEXCore/Source/Utils/ArchHelpers/Arm64_stubs.cpp
type FEXCore::ArchHelpers::Arm64 (line 6) | namespace FEXCore::ArchHelpers::Arm64 {
function HandleUnalignedAccess (line 14) | std::optional<int32_t>
FILE: FEXCore/Source/Utils/BucketList.h
function namespace (line 8) | namespace FEXCore {
FILE: FEXCore/Source/Utils/Config.h
function namespace (line 4) | namespace FEXCore::Config {
FILE: FEXCore/Source/Utils/FileLoading.cpp
type FEXCore::FileLoading (line 15) | namespace FEXCore::FileLoading {
function LoadFileImpl (line 19) | static bool LoadFileImpl(T& Data, const fextl::string& Filepath, size_...
function LoadFileToBuffer (line 77) | ssize_t LoadFileToBuffer(const fextl::string& Filepath, std::span<char...
function LoadFileImpl (line 91) | static bool LoadFileImpl(T& Data, const fextl::string& Filepath, size_...
function LoadFileToBuffer (line 103) | ssize_t LoadFileToBuffer(const fextl::string& Filepath, std::span<char...
function LoadFile (line 110) | bool LoadFile(fextl::vector<char>& Data, const fextl::string& Filepath...
function LoadFile (line 114) | bool LoadFile(fextl::string& Data, const fextl::string& Filepath, size...
FILE: FEXCore/Source/Utils/ForcedAssert.cpp
type FEXCore::Assert (line 2) | namespace FEXCore::Assert {
function ForcedAssert (line 4) | [[noreturn]]
FILE: FEXCore/Source/Utils/LogManager.cpp
type LogMan (line 12) | namespace LogMan {
type Throw (line 14) | namespace Throw {
function InstallHandler (line 16) | void InstallHandler(ThrowHandler _Handler) {
function UnInstallHandler (line 19) | void UnInstallHandler() {
function MFmt (line 23) | void MFmt(const char* fmt, const fmt::format_args& args) {
type Msg (line 33) | namespace Msg {
function InstallHandler (line 35) | void InstallHandler(MsgHandler _Handler) {
function UnInstallHandler (line 38) | void UnInstallHandler() {
function MFmtImpl (line 42) | void MFmtImpl(DebugLevels level, const char* fmt, const fmt::format_...
FILE: FEXCore/Source/Utils/LongJump.cpp
type FEXCore::UncheckedLongJump (line 7) | namespace FEXCore::UncheckedLongJump {
function FEX_DEFAULT_VISIBILITY (line 9) | [[nodiscard]]
function FEX_DEFAULT_VISIBILITY (line 37) | [[noreturn]]
function FEX_DEFAULT_VISIBILITY (line 65) | FEX_DEFAULT_VISIBILITY void ManuallyLoadJumpBuf(const JumpBuf& Buffer,...
function FEX_DEFAULT_VISIBILITY (line 86) | [[nodiscard]]
function FEX_DEFAULT_VISIBILITY (line 112) | [[noreturn]]
function FEX_DEFAULT_VISIBILITY (line 142) | FEX_DEFAULT_VISIBILITY void ManuallyLoadJumpBuf(JumpBuf& Buffer, uint6...
FILE: FEXCore/Source/Utils/MemberFunctionToPointer.h
function namespace (line 8) | namespace FEXCore::Utils {
FILE: FEXCore/Source/Utils/Profiler.cpp
function GetTime (line 22) | static inline uint64_t GetTime() {
function GetTime (line 31) | static inline uint64_t GetTime() {
type FEXCore::Profiler (line 51) | namespace FEXCore::Profiler {
function Init (line 188) | void Init(std::string_view ProgramName, std::string_view ProgramPath) {
function PostForkAction (line 196) | void PostForkAction(bool IsChild) {
function IsActive (line 202) | bool IsActive() {
function Shutdown (line 212) | void Shutdown() {
function TraceObject (line 220) | void TraceObject(const std::string_view Format, uint64_t Duration) {
function TraceObject (line 228) | void TraceObject(const std::string_view Format) {
type GPUVis (line 62) | namespace GPUVis {
function Init (line 73) | void Init() {
function Shutdown (line 93) | void Shutdown() {
function TraceObject (line 100) | void TraceObject(const std::string_view Format, uint64_t Duration) {
function TraceObject (line 110) | void TraceObject(const std::string_view Format) {
type Tracy (line 121) | namespace Tracy {
function Init (line 125) | void Init(std::string_view ProgramName, std::string_view ProgramPath) {
function PostForkAction (line 142) | void PostForkAction(bool IsChild) {
function Shutdown (line 165) | void Shutdown() {
function TraceObject (line 172) | void TraceObject(const std::string_view Format, uint64_t Duration) {}
function TraceObject (line 174) | void TraceObject(const std::string_view Format) {
type FEXCore::Profiler (line 185) | namespace FEXCore::Profiler {
function Init (line 188) | void Init(std::string_view ProgramName, std::string_view ProgramPath) {
function PostForkAction (line 196) | void PostForkAction(bool IsChild) {
function IsActive (line 202) | bool IsActive() {
function Shutdown (line 212) | void Shutdown() {
function TraceObject (line 220) | void TraceObject(const std::string_view Format, uint64_t Duration) {
function TraceObject (line 228) | void TraceObject(const std::string_view Format) {
FILE: FEXCore/Source/Utils/SpinWaitLock.cpp
type FEXCore::Utils::SpinWaitLock (line 4) | namespace FEXCore::Utils::SpinWaitLock {
function GetCycleCounterFrequency (line 8) | static uint64_t GetCycleCounterFrequency() {
function CalculateCyclesPerNanosecond (line 14) | static uint64_t CalculateCyclesPerNanosecond() {
FILE: FEXCore/Source/Utils/SpinWaitLock.h
function namespace (line 12) | namespace FEXCore::Utils::SpinWaitLock {
FILE: FEXCore/Source/Utils/Telemetry.cpp
type FEXCore::Telemetry (line 17) | namespace FEXCore::Telemetry {
function Initialize (line 41) | void Initialize() {
function Shutdown (line 56) | void Shutdown(const fextl::string& ApplicationName) {
FILE: FEXCore/Source/Utils/Threads.cpp
type FEXCore::Threads (line 9) | namespace FEXCore::Threads {
function CreateThread_Default (line 10) | static fextl::unique_ptr<FEXCore::Threads::Thread> CreateThread_Defaul...
function CleanupAfterFork_Default (line 14) | static void CleanupAfterFork_Default() {
FILE: FEXCore/Source/Utils/WritePriorityMutex.h
function namespace (line 18) | namespace FEXCore::Utils::WritePriorityMutex {
FILE: FEXCore/Source/Utils/variable_length_integer.h
function namespace (line 11) | namespace FEXCore::Utils {
function Encode (line 66) | static size_t Encode(uint8_t* dst, int64_t Data) {
type vl8_enc (line 104) | struct vl8_enc {
type vl16_enc (line 110) | struct vl16_enc {
function vl32_enc (line 126) | struct FEX_PACKED vl32_enc {
function vl64_enc (line 132) | struct FEX_PACKED vl64_enc {
function final (line 194) | struct vl64pair final {
type Decoded (line 207) | struct Decoded {
function Decoded (line 213) | static Decoded Decode(const uint8_t* data) {
function Encode (line 229) | static size_t Encode(uint8_t* dst, uint64_t data_arm, uint64_t data_rip) {
type vl8_enc (line 269) | struct vl8_enc {
function Decoded (line 276) | static inline Decoded Decode(const vl8_enc* enc) {
FILE: FEXCore/include/FEXCore/Config/Config.h
function namespace (line 22) | namespace FEXCore::Config {
type ConfigSMCChecks (line 44) | enum ConfigSMCChecks {
function LayerType (line 50) | enum class LayerType {
function namespace (line 98) | namespace detail {
function class (line 129) | class FEX_DEFAULT_VISIBILITY Layer {
FILE: FEXCore/include/FEXCore/Core/CPUID.h
function namespace (line 5) | namespace FEXCore::CPUID {
FILE: FEXCore/include/FEXCore/Core/CodeCache.h
function namespace (line 20) | namespace FEXCore {
type CodeMapOpener (line 122) | struct CodeMapOpener {
function class (line 127) | class CodeMapWriter {
FILE: FEXCore/include/FEXCore/Core/Context.h
function namespace (line 17) | namespace FEXCore {
function namespace (line 23) | namespace FEXCore::Core {
function namespace (line 28) | namespace FEXCore::HLE {
function namespace (line 32) | namespace FEXCore::IR {
function namespace (line 36) | namespace FEXCore::Context {
FILE: FEXCore/include/FEXCore/Core/CoreState.h
function namespace (line 16) | namespace FEXCore::Core {
function gs_idx (line 122) | uint16_t gs_idx {}
function mxcsr (line 123) | uint32_t mxcsr {}
function es_cached (line 126) | uint32_t es_cached {}
function gs_cached (line 127) | uint64_t gs_cached {}
function fs_cached (line 128) | uint64_t fs_cached {}
type gdt_segment (line 133) | struct gdt_segment {
function gdt_segment (line 158) | gdt_segment* segment_arrays[2] {}
function gdt_segment (line 160) | static gdt_segment* GetSegmentFromIndex(CPUState& State, uint16_t Select...
function CalculateGDTBase (line 165) | static uint32_t CalculateGDTBase(gdt_segment GDT) {
function CalculateGDTLimit (line 173) | static uint32_t CalculateGDTLimit(gdt_segment GDT) {
function SetGDTBase (line 180) | static void SetGDTBase(gdt_segment* GDT, uint32_t Base) {
function SetGDTLimit (line 186) | static void SetGDTLimit(gdt_segment* GDT, uint32_t Limit) {
function FCW (line 191) | uint16_t FCW {0x37F};
FILE: FEXCore/include/FEXCore/Core/HostFeatures.h
function namespace (line 7) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Core/SignalDelegator.h
function namespace (line 8) | namespace FEXCore {
function class (line 58) | class SignalDelegator {
FILE: FEXCore/include/FEXCore/Core/Thunks.h
function namespace (line 10) | namespace FEXCore::IR {
function namespace (line 14) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Core/X86Enums.h
function namespace (line 6) | namespace FEXCore::X86State {
FILE: FEXCore/include/FEXCore/Debug/GDBReaderInterface.h
type blocks_t (line 9) | struct blocks_t {
type info_t (line 15) | struct info_t {
FILE: FEXCore/include/FEXCore/Debug/InternalThreadState.h
function namespace (line 16) | namespace FEXCore {
function namespace (line 22) | namespace FEXCore::Context {
function namespace (line 26) | namespace FEXCore::CPU {
function namespace (line 30) | namespace FEXCore::Frontend {
function namespace (line 34) | namespace FEXCore::IR {
function namespace (line 39) | namespace FEXCore::SHMStats {
function namespace (line 43) | namespace FEXCore::Core {
FILE: FEXCore/include/FEXCore/HLE/SourcecodeResolver.h
function namespace (line 12) | namespace FEXCore::HLE {
type SourcecodeMap (line 41) | struct SourcecodeMap {
function SourcecodeLineMapping (line 64) | const SourcecodeLineMapping* FindLineMapping(uintptr_t FileBegin) const {
function SourcecodeSymbolMapping (line 68) | const SourcecodeSymbolMapping* FindSymbolMapping(uintptr_t FileBegin) co...
function typename (line 73) | typename VecT::value_type* Find(uintptr_t FileBegin, const VecT& SortedM...
function class (line 85) | class SourcecodeResolver {
FILE: FEXCore/include/FEXCore/HLE/SyscallHandler.h
function namespace (line 10) | namespace FEXCore::Context {
function namespace (line 14) | namespace FEXCore::Core {
function namespace (line 19) | namespace FEXCore::HLE {
FILE: FEXCore/include/FEXCore/IR/IR.h
function namespace (line 10) | namespace FEXCore::IR {
FILE: FEXCore/include/FEXCore/Utils/Allocator.h
function namespace (line 10) | namespace FEXCore::Core {
function namespace (line 14) | namespace FEXCore::Allocator {
FILE: FEXCore/include/FEXCore/Utils/AllocatorHooks.h
type class (line 22) | enum class
function class (line 30) | class THPControl {
FILE: FEXCore/include/FEXCore/Utils/ArchHelpers/Arm64.h
function namespace (line 9) | namespace FEXCore::Core {
function namespace (line 13) | namespace FEXCore::ArchHelpers::Arm64 {
FILE: FEXCore/include/FEXCore/Utils/CompilerDefs.h
function namespace (line 34) | namespace FEXCore::Assert {
FILE: FEXCore/include/FEXCore/Utils/EnumUtils.h
function namespace (line 8) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Utils/Event.h
function class (line 7) | class Event final {
FILE: FEXCore/include/FEXCore/Utils/FPState.h
function namespace (line 6) | namespace FEXCore::FPState {
FILE: FEXCore/include/FEXCore/Utils/File.h
type class (line 17) | enum class
function SeekOp (line 24) | enum class SeekOp {
FILE: FEXCore/include/FEXCore/Utils/FileLoading.h
function namespace (line 9) | namespace FEXCore::FileLoading {
FILE: FEXCore/include/FEXCore/Utils/InterruptableConditionVariable.h
function namespace (line 18) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Utils/IntervalList.h
function namespace (line 9) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Utils/LogManager.h
function namespace (line 11) | namespace LogMan {
FILE: FEXCore/include/FEXCore/Utils/LongJump.h
function namespace (line 10) | namespace FEXCore::UncheckedLongJump {
FILE: FEXCore/include/FEXCore/Utils/MathUtils.h
function namespace (line 10) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Utils/Profiler.h
function namespace (line 16) | namespace FEXCore::Profiler {
FILE: FEXCore/include/FEXCore/Utils/SHMStats.h
function GetCycleCounter (line 18) | static inline uint64_t GetCycleCounter() {
function GetCycleCounter (line 28) | static inline uint64_t GetCycleCounter() {
type class (line 36) | enum class
type ThreadStatsHeader (line 45) | struct ThreadStatsHeader {
type ThreadStats (line 55) | struct ThreadStats {
function AccumulationBlock (line 79) | AccumulationBlock final {
FILE: FEXCore/include/FEXCore/Utils/SignalScopeGuards.h
function namespace (line 17) | namespace FEXCore {
FILE: FEXCore/include/FEXCore/Utils/StringUtils.h
function namespace (line 5) | namespace FEXCore::StringUtils {
function fextl (line 27) | inline fextl::string Trim(fextl::string String, std::string_view TrimTok...
FILE: FEXCore/include/FEXCore/Utils/Telemetry.h
function namespace (line 11) | namespace FEXCore::Telemetry {
FILE: FEXCore/include/FEXCore/Utils/ThreadPoolAllocator.h
type MemoryBuffer (line 42) | struct MemoryBuffer
type class (line 57) | enum class
type MemoryBuffer (line 65) | struct MemoryBuffer
function BufferOwnedFlag (line 74) | BufferOwnedFlag* CurrentClientOwnedFlag {}
function IsClientBufferOwned (line 88) | static bool IsClientBufferOwned(BufferOwnedFlag& CurrentClientFlag) {
function IsClientBufferFree (line 99) | static bool IsClientBufferFree(BufferOwnedFlag& CurrentClientFlag) {
function UnclaimBuffer (line 126) | void UnclaimBuffer(const ContainerType::iterator& Buffer, BufferOwnedFla...
function std (line 204) | constexpr static std::chrono::duration DURATION {std::chrono::seconds(5)};
function Free (line 368) | void Free(void* Ptr, size_t Size) override {
function Name (line 379) | PooledAllocatorVirtual(const char* Name)
function virtual (line 382) | virtual ~PooledAllocatorVirtual() {
function Free (line 395) | void Free(void* Ptr, size_t Size) override {
function Name (line 410) | PooledAllocatorVirtualWithGuard(const char* Name)
function virtual (line 413) | virtual ~PooledAllocatorVirtualWithGuard() {
function Free (line 431) | void Free(void* Ptr, size_t Size) override {
function PoolBufferWithTimedRetirement (line 477) | PoolBufferWithTimedRetirement final {
FILE: FEXCore/include/FEXCore/Utils/Threads.h
function namespace (line 6) | namespace FEXCore::Threads {
FILE: FEXCore/include/FEXCore/Utils/TypeDefines.h
function namespace (line 5) | namespace FEXCore::Utils {
FILE: FEXCore/include/FEXCore/fextl/allocator.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/deque.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/fmt.h
function namespace (line 11) | namespace fextl::fmt {
FILE: FEXCore/include/FEXCore/fextl/forward_list.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/functional.h
function namespace (line 10) | namespace fextl {
function else (line 29) | else if constexpr (std::is_nothrow_constructible_v<std::function<R(Args....
function moved_lambda (line 46) | auto moved_lambda = new (storage) Fnoref {std::move(f)};
FILE: FEXCore/include/FEXCore/fextl/list.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/map.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/memory.h
function const (line 11) | void operator()(T* ptr) const {
function Result (line 35) | auto Result = ::new (ptr) T(std::forward<Args>(args)...);
FILE: FEXCore/include/FEXCore/fextl/memory_resource.h
function namespace (line 12) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/queue.h
function namespace (line 8) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/robin_map.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/robin_set.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/set.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/sstream.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/stack.h
function namespace (line 8) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/string.h
function namespace (line 8) | namespace fextl {
function string (line 16) | struct std::hash<fextl::string> {
FILE: FEXCore/include/FEXCore/fextl/unordered_map.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/unordered_set.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/include/FEXCore/fextl/vector.h
function namespace (line 7) | namespace fextl {
FILE: FEXCore/unittests/APITests/Allocator.cpp
function HasSyscallError (line 10) | bool HasSyscallError(T Result) {
FILE: FEXCore/unittests/Emitter/TestDisassembler.h
function class (line 12) | class TestDisassembler : public ARMEmitter::Emitter {
function ResetFP (line 68) | void ResetFP() {
FILE: FEXHeaderUtils/FEXHeaderUtils/BitUtils.h
function namespace (line 12) | namespace FEXCore {
FILE: FEXHeaderUtils/FEXHeaderUtils/Filesystem.h
type class (line 22) | enum class
function CopyOptions (line 28) | enum class CopyOptions {
FILE: FEXHeaderUtils/FEXHeaderUtils/RingBuffer.h
function namespace (line 5) | namespace FHU {
FILE: FEXHeaderUtils/FEXHeaderUtils/StringArgumentParser.h
function namespace (line 9) | namespace FHU {
FILE: FEXHeaderUtils/FEXHeaderUtils/SymlinkChecks.h
function namespace (line 10) | namespace FHU::Symlinks {
FILE: FEXHeaderUtils/FEXHeaderUtils/Syscalls.h
function namespace (line 18) | namespace FHU::Syscalls {
FILE: Scripts/CI_FetchRootFS.py
function GetDistroInfo (line 8) | def GetDistroInfo():
function FindBestImageFit (line 25) | def FindBestImageFit(Distro, links_file):
function HashFile (line 71) | def HashFile(file):
function RemoveRootFSFolder (line 85) | def RemoveRootFSFolder(RootFSPath):
function CheckFilesystemForFS (line 91) | def CheckFilesystemForFS(RootFSMountPath, RootFSPath, DistroFit):
function main (line 161) | def main():
FILE: Scripts/ClassifyCPU.py
function ListContainsRequired (line 5) | def ListContainsRequired(Features, RequiredFeatures):
function GetCPUFeaturesVersion (line 11) | def GetCPUFeaturesVersion():
function main (line 44) | def main():
FILE: Scripts/DefinitionExtract.py
class TypeDefinition (line 14) | class TypeDefinition:
method __init__ (line 23) | def __init__(self, Name, Type):
method Name (line 28) | def Name(self):
method Type (line 31) | def Type(self):
class AliasType (line 35) | class AliasType:
method __init__ (line 43) | def __init__(self, Name, Type):
class StructDefinition (line 48) | class StructDefinition(TypeDefinition):
method __init__ (line 54) | def __init__(self, Name, Size):
class UnionDefinition (line 62) | class UnionDefinition(TypeDefinition):
method __init__ (line 68) | def __init__(self, Name, Size):
class FieldDefinition (line 76) | class FieldDefinition(TypeDefinition):
method __init__ (line 80) | def __init__(self, Name, Size, OffsetOf, Alignment):
class VarDeclDefinition (line 87) | class VarDeclDefinition(TypeDefinition):
method __init__ (line 93) | def __init__(self, Name, Size):
class ArchDB (line 100) | class ArchDB:
method __init__ (line 110) | def __init__(self, ArchName):
class FunctionDecl (line 122) | class FunctionDecl:
method __init__ (line 127) | def __init__(self, Name, Ret):
function HandleFunctionDeclCursor (line 134) | def HandleFunctionDeclCursor(Arch, Cursor):
function PrintFunctionDecls (line 169) | def PrintFunctionDecls():
function FindClangArguments (line 173) | def FindClangArguments(OriginalArguments):
function SetNamespace (line 202) | def SetNamespace(Arch):
function HandleStructDeclCursor (line 207) | def HandleStructDeclCursor(Arch, Cursor, NameOverride = ""):
function HandleUnionDeclCursor (line 234) | def HandleUnionDeclCursor(Arch, Cursor, NameOverride = ""):
function HandleVarDeclCursor (line 263) | def HandleVarDeclCursor(Arch, Cursor):
function HandleVarDeclElements (line 274) | def HandleVarDeclElements(Arch, VarDecl, Cursor):
function HandleTypeDefDeclCursor (line 307) | def HandleTypeDefDeclCursor(Arch, Cursor):
function HandleStructElements (line 345) | def HandleStructElements(Arch, Struct, Cursor):
function HandleTypeDefDecl (line 425) | def HandleTypeDefDecl(Arch, Cursor, Name):
function HandleCursor (line 444) | def HandleCursor(Arch, Cursor):
function GetDB (line 488) | def GetDB(Arch, filename, args):
function main (line 514) | def main():
FILE: Scripts/GenerateSyscallNumbers.py
class SyscallDefinition (line 20) | class SyscallDefinition:
method __init__ (line 26) | def __init__(self, Arch, SyscallNumber, ABI, Name, Entry):
method Arch (line 34) | def Arch(self):
method Number (line 38) | def Number(self):
method ABI (line 42) | def ABI(self):
method Name (line 46) | def Name(self):
method EntryName (line 50) | def EntryName(self):
function ParseArchSyscalls (line 78) | def ParseArchSyscalls(Defs, DefsDict, Arch, FilePath, IgnoreArch):
function ParseCommonArchSyscalls (line 121) | def ParseCommonArchSyscalls(Defs, DefsDict, Arch, FilePath):
function ExportSyscallDefines (line 192) | def ExportSyscallDefines(Defs, DefsDict, Arch, UnsupportedDefs):
function ExportCommonSyscallDefines (line 225) | def ExportCommonSyscallDefines():
function main (line 264) | def main():
FILE: Scripts/InstallFEX.py
function GetArch (line 14) | def GetArch():
function GetDistro (line 22) | def GetDistro():
function IsSupportedArch (line 80) | def IsSupportedArch():
function IsSupportedDistro (line 84) | def IsSupportedDistro():
function ListContainsRequired (line 94) | def ListContainsRequired(Features, RequiredFeatures):
function GetCPUFeaturesVersion (line 100) | def GetCPUFeaturesVersion():
function GetPPAStatus (line 138) | def GetPPAStatus():
function InstallPPA (line 158) | def InstallPPA():
function GetPackagesToInstall (line 185) | def GetPackagesToInstall():
function UpdatePPA (line 192) | def UpdatePPA():
function InstallPackages (line 211) | def InstallPackages(PackagesToInstall):
function CheckAndInstallPackageUpdates (line 228) | def CheckAndInstallPackageUpdates(PackagesToInstall, InstallIfNotFound=F...
function CheckPackageInstallStatus (line 256) | def CheckPackageInstallStatus():
function InstallPackages (line 265) | def InstallPackages(Packages):
function GetRootFSPath (line 285) | def GetRootFSPath():
function CheckRootFSInstallStatus (line 316) | def CheckRootFSInstallStatus():
function TryInstallRootFS (line 331) | def TryInstallRootFS():
function TryBasicProgramExecution (line 347) | def TryBasicProgramExecution():
function ExitWithStatus (line 351) | def ExitWithStatus(Status):
function GetKernelVersion (line 356) | def GetKernelVersion():
function IsSupportedKernel (line 360) | def IsSupportedKernel():
function main (line 363) | def main():
FILE: Scripts/InstructionCountParser.py
class TestData (line 15) | class TestData:
method __init__ (line 20) | def __init__(self, Name, ExpectedInstructionCount, Code, Instructions):
method Name (line 27) | def Name(self):
method ExpectedInstructionCount (line 31) | def ExpectedInstructionCount(self):
method Code (line 35) | def Code(self):
method Instructions (line 39) | def Instructions(self):
class HostFeatures (line 43) | class HostFeatures(Flag) :
function GetHostFeatures (line 85) | def GetHostFeatures(data):
function parse_json_data (line 98) | def parse_json_data(json_filepath, json_filename, json_data, output_bina...
function main (line 227) | def main():
FILE: Scripts/NeedDisabledSVE.py
function GetCPUFeatures (line 11) | def GetCPUFeatures():
function IsAffectedSnapdragon (line 39) | def IsAffectedSnapdragon():
function main (line 60) | def main():
FILE: Scripts/StructPackVerifier.py
class TypeDefinition (line 33) | class TypeDefinition:
method __init__ (line 42) | def __init__(self, Name, Type):
method Name (line 47) | def Name(self):
method Type (line 50) | def Type(self):
class AliasType (line 54) | class AliasType:
method __init__ (line 62) | def __init__(self, Name, Type):
class StructDefinition (line 67) | class StructDefinition(TypeDefinition):
method __init__ (line 73) | def __init__(self, Name, Size):
class UnionDefinition (line 81) | class UnionDefinition(TypeDefinition):
method __init__ (line 87) | def __init__(self, Name, Size):
class FieldDefinition (line 95) | class FieldDefinition(TypeDefinition):
method __init__ (line 99) | def __init__(self, Name, Size, OffsetOf, Alignment):
class VarDeclDefinition (line 106) | class VarDeclDefinition(TypeDefinition):
method __init__ (line 112) | def __init__(self, Name, Size):
class ArchDB (line 119) | class ArchDB:
method __init__ (line 129) | def __init__(self, ArchName):
class DBList (line 140) | class DBList:
method __init__ (line 142) | def __init__(self, DB32, DB64, DBAArch64, DBWin32, DBWin64):
function FindClangArguments (line 145) | def FindClangArguments(OriginalArguments):
function SetNamespace (line 174) | def SetNamespace(Arch):
function HandleStructDeclCursor (line 179) | def HandleStructDeclCursor(Arch, Cursor, NameOverride = ""):
function HandleUnionDeclCursor (line 206) | def HandleUnionDeclCursor(Arch, Cursor, NameOverride = ""):
function HandleVarDeclCursor (line 235) | def HandleVarDeclCursor(Arch, Cursor):
function HandleVarDeclElements (line 246) | def HandleVarDeclElements(Arch, VarDecl, Cursor):
function HandleTypeDefDeclCursor (line 280) | def HandleTypeDefDeclCursor(Arch, Cursor):
function HandleStructElements (line 318) | def HandleStructElements(Arch, Struct, Cursor):
function HandleTypeDefDecl (line 398) | def HandleTypeDefDecl(Arch, Cursor, Name):
function HandleCursor (line 417) | def HandleCursor(Arch, Cursor):
function GetDB (line 459) | def GetDB(Arch, filename, args):
function GetCompar (line 484) | def GetCompar(ComparisonName, DBs):
function PrintMissingMembers (line 496) | def PrintMissingMembers(Struct1, Struct2):
function CompareStructs (line 506) | def CompareStructs(Struct1, Struct2):
function CompareAliases (line 544) | def CompareAliases(DB, DBs):
function CompareCrossArch (line 591) | def CompareCrossArch(DB1, DB2):
function main (line 610) | def main():
FILE: Scripts/Threaded_Lockstep_Runner.py
function Threaded_Runner (line 28) | def Threaded_Runner(Args, ID, Client):
function Threaded_Manager (line 37) | def Threaded_Manager(Runner, ID, File):
FILE: Scripts/UpdateInstructionCountJson.py
function insert_before (line 8) | def insert_before(d, key, item):
function update_performance_numbers (line 13) | def update_performance_numbers(performance_json_path, performance_json, ...
function main (line 38) | def main():
FILE: Scripts/guest_test_runner.py
function DoesFEXSupportAVX (line 7) | def DoesFEXSupportAVX(mode):
function TestRequiresAVXSupport (line 25) | def TestRequiresAVXSupport():
function LoadTestsFile (line 49) | def LoadTestsFile(File):
function LoadTestsFileResults (line 62) | def LoadTestsFileResults(File):
FILE: Scripts/json_config_parse.py
class Regs (line 6) | class Regs(Flag):
class ABI (line 55) | class ABI(Flag) :
class Mode (line 60) | class Mode(Flag) :
class HostFeatures (line 64) | class HostFeatures(Flag) :
function parse_hexstring (line 178) | def parse_hexstring(s):
function parse_json (line 192) | def parse_json(json_text, output_file):
FILE: Source/Common/ArgumentLoader.cpp
type FEX::ArgLoader (line 10) | namespace FEX::ArgLoader {
FILE: Source/Common/ArgumentLoader.h
function namespace (line 8) | namespace FEX::ArgLoader {
FILE: Source/Common/Async.h
function namespace (line 24) | namespace fasio {
function mutable_buffer (line 278) | inline mutable_buffer Chained(std::span<mutable_buffer> Buffers) {
type dynamic_vector_buffer (line 288) | struct dynamic_vector_buffer {
function async_read_until (line 310) | void async_read_until(AsyncReadStream& Stream, dynamic_vector_buffer Buf...
type posix_descriptor (line 415) | struct posix_descriptor {
FILE: Source/Common/AsyncNet.h
function namespace (line 12) | namespace fasio {
function read_some (line 66) | size_t read_some(const mutable_buffer& Buffers, error& ec) {
function write_some (line 73) | size_t write_some(const mutable_buffer& Buffers, error& ec) {
function msghdr (line 129) | msghdr msg {
type cmsghdr (line 160) | struct cmsghdr
function tcp_acceptor (line 184) | struct tcp_acceptor {
function std (line 205) | static std::optional<tcp_acceptor> create(poll_reactor& Reactor, bool ab...
function async_accept (line 246) | void async_accept(fextl::move_only_function<post_callback(error, std::op...
FILE: Source/Common/CPUInfo.cpp
type FEX::CPUInfo (line 15) | namespace FEX::CPUInfo {
function CalculateNumberOfCPUs (line 17) | uint32_t CalculateNumberOfCPUs() {
function CalculateNumberOfCPUs (line 34) | uint32_t CalculateNumberOfCPUs() {
FILE: Source/Common/CPUInfo.h
function namespace (line 6) | namespace FEX::CPUInfo {
FILE: Source/Common/Config.cpp
type FEX::Config (line 29) | namespace FEX::Config {
type JSON (line 30) | namespace JSON {
function LoadJSonConfig (line 31) | static void LoadJSonConfig(const fextl::string& Config, std::functio...
function SaveLayerToJSON (line 98) | void SaveLayerToJSON(const fextl::string& Filename, const FEXCore::Con...
function SaveLayerToJSON (line 124) | void SaveLayerToJSON(const fextl::string& Filename, const FEXCore::Con...
class OptionMapper (line 156) | class OptionMapper : public FEXCore::Config::Layer {
method SetCurrentConfigFile (line 162) | void SetCurrentConfigFile(const fextl::string& Filename) {
class MainLoader (line 168) | class MainLoader final : public OptionMapper {
class AppLoader (line 180) | class AppLoader final : public OptionMapper {
class EnvLoader (line 189) | class EnvLoader final : public FEXCore::Config::Layer {
function CreateGlobalMainLayer (line 319) | fextl::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer() {
function CreateMainLayer (line 323) | fextl::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(const fextl:...
function CreateUserOverrideLayer (line 331) | fextl::unique_ptr<FEXCore::Config::Layer> CreateUserOverrideLayer(std:...
function CreateAppLayer (line 335) | fextl::unique_ptr<FEXCore::Config::Layer> CreateAppLayer(const fextl::...
function CreateEnvironmentLayer (line 339) | fextl::unique_ptr<FEXCore::Config::Layer> CreateEnvironmentLayer(char*...
function RecoverGuestProgramFilename (line 343) | fextl::string RecoverGuestProgramFilename(fextl::string Program, bool ...
function ApplicationNames (line 409) | ApplicationNames GetApplicationNames(const fextl::vector<fextl::string...
function LoadConfig (line 457) | void LoadConfig(fextl::string ProgramName, char** const envp, const Po...
function FindUserHomeThroughUID (line 501) | fextl::string FindUserHomeThroughUID() {
function GetHomeDirectory (line 552) | fextl::string GetHomeDirectory() {
function GetHomeDirectory (line 576) | fextl::string GetHomeDirectory() {
function GetDataDirectory (line 595) | fextl::string GetDataDirectory(bool Global, const PortableInformation&...
function GetConfigDirectory (line 635) | fextl::string GetConfigDirectory(bool Global, const PortableInformatio...
function GetCacheDirectory (line 683) | fextl::string GetCacheDirectory() {
function GetConfigFileLocation (line 706) | fextl::string GetConfigFileLocation(bool Global, const PortableInforma...
function InitializeConfigs (line 710) | void InitializeConfigs(const PortableInformation& PortableInfo) {
FILE: Source/Common/Config.h
function namespace (line 12) | namespace FEX::ArgLoader {
function namespace (line 18) | namespace FEX::Config {
FILE: Source/Common/FDUtils.h
function namespace (line 10) | namespace FEX {
FILE: Source/Common/FEXServerClient.cpp
type FEXServerClient (line 31) | namespace FEXServerClient {
function RequestPIDFDPacket (line 43) | int RequestPIDFDPacket(int ServerSocket, PacketType Type) {
function GetServerLockFolder (line 73) | fextl::string GetServerLockFolder() {
function GetServerLockFile (line 77) | fextl::string GetServerLockFile() {
function GetServerRootFSLockFile (line 81) | fextl::string GetServerRootFSLockFile() {
function GetTempFolder (line 85) | fextl::string GetTempFolder() {
function GetServerMountFolder (line 103) | fextl::string GetServerMountFolder() {
function GetServerSocketName (line 132) | fextl::string GetServerSocketName() {
function GetServerSocketPath (line 140) | fextl::string GetServerSocketPath() {
function GetServerFD (line 164) | int GetServerFD() {
function ConnectToServer (line 168) | int ConnectToServer(ConnectionOption ConnectionOption) {
function SetupClient (line 224) | bool SetupClient(std::string_view InterpreterPath) {
function StartServer (line 242) | int StartServer(std::string_view InterpreterPath, int watch_fd) {
function ConnectToAndStartServer (line 355) | int ConnectToAndStartServer(std::string_view InterpreterPath) {
function RequestServerKill (line 366) | void RequestServerKill(int ServerSocket) {
function RequestLogFD (line 376) | int RequestLogFD(int ServerSocket) {
function RequestRootFSPath (line 380) | fextl::string RequestRootFSPath(int ServerSocket) {
function RequestPIDFD (line 404) | int RequestPIDFD(int ServerSocket) {
function PopulateCodeCache (line 408) | void PopulateCodeCache(int ServerSocket, int ProgramFD, bool HasMultib...
function RequestCodeMapFD (line 431) | int RequestCodeMapFD(int ServerSocket, int ProgramFD, bool HasMultiblo...
function MsgHandler (line 469) | void MsgHandler(int FD, LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 491) | void AssertHandler(int FD, const char* Message) {
FILE: Source/Common/FEXServerClient.h
function namespace (line 11) | namespace LogMan {
function namespace (line 15) | namespace FEXServerClient {
FILE: Source/Common/FileFormatCheck.cpp
type FEX::FormatCheck (line 9) | namespace FEX::FormatCheck {
function IsSquashFS (line 10) | bool IsSquashFS(const fextl::string& Filename) {
function IsEroFS (line 52) | bool IsEroFS(const fextl::string& Filename) {
FILE: Source/Common/FileFormatCheck.h
function namespace (line 6) | namespace FEX::FormatCheck {
FILE: Source/Common/FileMappingBaseAddress.h
function namespace (line 12) | namespace FEXCore {
FILE: Source/Common/HostFeatures.cpp
type FEX (line 17) | namespace FEX {
function FillMIDRInformationViaLinux (line 19) | void FillMIDRInformationViaLinux(FEXCore::HostFeatures* Features) {
function ReadSVEVectorLengthInBits (line 42) | __attribute__((naked)) static uint64_t ReadSVEVectorLengthInBits() {
function ReadSVEVectorLengthInBits (line 50) | [[maybe_unused]]
class CPUFeaturesFromID (line 77) | class CPUFeaturesFromID final : public FEX::CPUFeatures {
method CPUFeaturesFromID (line 79) | CPUFeaturesFromID() {
function GetCPUFeaturesFromIDRegisters (line 103) | FEX::CPUFeatures GetCPUFeaturesFromIDRegisters() {
class CPUFeaturesFromConfig (line 108) | class CPUFeaturesFromConfig final : public FEX::CPUFeatures {
method CPUFeaturesFromConfig (line 110) | CPUFeaturesFromConfig(std::string_view Config) {
function GetCPUFeaturesFromConfig (line 176) | FEX::CPUFeatures GetCPUFeaturesFromConfig(std::string_view Config) {
class CPUFeaturesAll (line 180) | class CPUFeaturesAll final : public FEX::CPUFeatures {
method CPUFeaturesAll (line 182) | CPUFeaturesAll() {
function GetFPCR (line 450) | static uint32_t GetFPCR() {
function SetFPCR (line 456) | static void SetFPCR(uint64_t Value) {
function OverrideFeatures (line 462) | static void OverrideFeatures(FEXCore::HostFeatures* Features, uint64_t...
function HandleErrata (line 529) | static void HandleErrata(FEXCore::HostFeatures* HostFeatures, uint64_t...
function FetchHostFeatures (line 597) | void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatur...
function FetchHostFeatures (line 723) | FEXCore::HostFeatures FetchHostFeatures() {
FILE: Source/Common/HostFeatures.h
function namespace (line 8) | namespace FEX {
FILE: Source/Common/JSONPool.cpp
type FEX::JSON (line 4) | namespace FEX::JSON {
function json_t (line 5) | static json_t* PoolInit(jsonPool_t* Pool) {
function json_t (line 10) | static json_t* PoolAlloc(jsonPool_t* Pool) {
FILE: Source/Common/JSONPool.h
function namespace (line 8) | namespace FEX::JSON {
FILE: Source/Common/Linux/SBRKAllocations.cpp
type FEX::SBRKAllocations (line 10) | namespace FEX::SBRKAllocations {
function ReenableSBRKAllocations (line 52) | void ReenableSBRKAllocations(void* Ptr) {
FILE: Source/Common/Linux/SBRKAllocations.h
function namespace (line 4) | namespace FEX::SBRKAllocations {
FILE: Source/Common/SHMStats.cpp
type FEX::SHMStats (line 7) | namespace FEX::SHMStats {
FILE: Source/Common/SHMStats.h
function namespace (line 11) | namespace FEXCore::Core {
function store_memory_barrier (line 16) | static inline void store_memory_barrier() {
function store_memory_barrier (line 21) | static inline void store_memory_barrier() {
function namespace (line 27) | namespace FEX::SHMStats {
FILE: Source/Common/VolatileMetadata.cpp
type FEX::VolatileMetadata (line 11) | namespace FEX::VolatileMetadata {
function ParseExtendedVolatileMetadata (line 12) | fextl::unordered_map<fextl::string, ExtendedVolatileMetadata> ParseExt...
FILE: Source/Common/VolatileMetadata.h
function namespace (line 11) | namespace FEX::VolatileMetadata {
FILE: Source/Common/X86Features.h
function namespace (line 7) | namespace FEX::X86 {
FILE: Source/Steam/CompatTool.cpp
function GenerateSteamConfigTemplate (line 18) | fextl::string GenerateSteamConfigTemplate(const FEX::Config::PortableInf...
function GenerateSteamAppConfig (line 73) | fextl::string GenerateSteamAppConfig(const FEX::Config::PortableInformat...
function main (line 167) | int main(int argc, const char** argv) {
FILE: Source/Steam/ServerManager.cpp
function MsgHandler (line 10) | void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 17) | void AssertHandler(const char* Message) {
function SignalPVToContinue (line 21) | void SignalPVToContinue(int* original_stdout) {
type PipesType (line 31) | struct PipesType {
function PipesType (line 36) | PipesType get_pipe() {
function main (line 42) | int main(int argc, const char** argv, char** const envp) {
FILE: Source/Tools/CodeSizeValidation/Main.cpp
type CodeSize (line 15) | namespace CodeSize {
class CodeSizeValidation (line 16) | class CodeSizeValidation final {
method CodeSizeValidation (line 18) | CodeSizeValidation() {
type InstructionStats (line 31) | struct InstructionStats {
type InstructionData (line 40) | struct InstructionData {
method InstructionData (line 47) | InstructionData CompileAndGetStats(FEXCore::Context::Context* CTX, F...
method InfoPrintingDisabled (line 71) | bool InfoPrintingDisabled() const {
method ClearStats (line 77) | void ClearStats() {
function SanitizeDisassembly (line 99) | static std::string_view SanitizeDisassembly(std::string_view Message) {
function MsgHandler (line 193) | void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 209) | void AssertHandler(const char* Message) {
type TestInfo (line 216) | struct TestInfo {
type TestHeader (line 225) | struct TestHeader {
function TestInstructions (line 240) | static bool TestInstructions(FEXCore::Context::Context* CTX, FEXCore::Co...
function LoadTests (line 338) | bool LoadTests(const char* Path) {
class TestEnvLoader (line 379) | class TestEnvLoader final : public FEXCore::Config::Layer {
method TestEnvLoader (line 381) | explicit TestEnvLoader()
method Load (line 386) | void Load() override {
class SimpleSyscallHandler (line 439) | class SimpleSyscallHandler : public FEXCore::HLE::SyscallHandler, public...
method SimpleSyscallHandler (line 441) | SimpleSyscallHandler() {
method HandleSyscall (line 445) | uint64_t HandleSyscall(FEXCore::Core::CpuStateFrame* Frame, FEXCore::H...
method LookupExecutableFileSection (line 451) | std::optional<FEXCore::ExecutableFileSectionInfo>
method QueryGuestExecutableRange (line 456) | FEXCore::HLE::ExecutableRangeInfo QueryGuestExecutableRange(FEXCore::C...
function main (line 462) | int main(int argc, char** argv, char** const envp) {
FILE: Source/Tools/CommonTools/CodeLoader.h
function namespace (line 10) | namespace FEX {
FILE: Source/Tools/CommonTools/DummyHandlers.cpp
type FEX::DummyHandlers (line 4) | namespace FEX::DummyHandlers {
function CreateSyscallHandler (line 19) | fextl::unique_ptr<FEXCore::HLE::SyscallHandler> CreateSyscallHandler() {
function CreateSignalDelegator (line 23) | fextl::unique_ptr<FEX::DummyHandlers::DummySignalDelegator> CreateSign...
FILE: Source/Tools/CommonTools/DummyHandlers.h
function namespace (line 10) | namespace FEX::DummyHandlers {
FILE: Source/Tools/CommonTools/HarnessHelpers.h
function namespace (line 29) | namespace FEX::HarnessHelper {
function class (line 95) | class ConfigLoader final {
function LoadMemory (line 285) | void LoadMemory() {
type HostFeatures (line 298) | enum HostFeatures {
type ConfigStructBase (line 402) | struct ConfigStructBase {
type MemoryRegionBase (line 421) | struct MemoryRegionBase {
type RegDataStructBase (line 426) | struct RegDataStructBase {
type MemDataStructBase (line 432) | struct MemDataStructBase {
function StackSize (line 451) | uint64_t StackSize() const override {
function MapMemory (line 465) | bool MapMemory(const std::function<void*(uint64_t, size_t)>& DoMMap) {
FILE: Source/Tools/CommonTools/Linux/Utils/ELFContainer.cpp
type ELFLoader (line 27) | namespace ELFLoader {
function CheckELFType (line 29) | static ELFContainer::ELFType CheckELFType(uint8_t* Data) {
type stat (line 68) | struct stat
function ELFSymbol (line 282) | const ELFSymbol* ELFContainer::GetSymbol(const char* Name) {
function ELFSymbol (line 289) | const ELFSymbol* ELFContainer::GetSymbol(uint64_t Address) {
function ELFSymbol (line 296) | const ELFSymbol* ELFContainer::GetSymbolInRange(RangeType Address) {
type entry (line 470) | struct entry {
type entry (line 594) | struct entry {
FILE: Source/Tools/CommonTools/Linux/Utils/ELFContainer.h
type ELFSymbol (line 25) | struct ELFSymbol {
function final (line 48) | struct MemoryLayout final {
type BRKInfo (line 58) | struct BRKInfo {
function fextl (line 90) | const fextl::vector<const char*>* GetNecessaryLibs() const {
type ELFMode (line 117) | enum ELFMode {
type ELFType (line 129) | enum ELFType {
function IsSupportedELF (line 137) | static bool IsSupportedELF(const fextl::string& Filename) {
function MinPhysicalMemoryLocation (line 176) | uint64_t MinPhysicalMemoryLocation {0}
function MaxPhysicalMemoryLocation (line 177) | uint64_t MaxPhysicalMemoryLocation {0}
function PhysicalMemorySize (line 178) | uint64_t PhysicalMemorySize {0}
function BRKBase (line 180) | uint64_t BRKBase {}
function BRKSize (line 181) | uint64_t BRKSize {}
function ProgramHeader (line 182) | ProgramHeader InterpreterHeader {}
function DynamicProgram (line 183) | bool DynamicProgram {false};
FILE: Source/Tools/CommonTools/Linux/Utils/ELFParser.h
type ELFParser (line 21) | struct ELFParser {
function fd (line 28) | int fd {-1};
function std (line 461) | static std::optional<FEXCore::GuestRelocationType> ClassifyRelocation32(...
function std (line 474) | static std::optional<FEXCore::GuestRelocationType> ClassifyRelocation64(...
FILE: Source/Tools/CommonTools/PortabilityInfo.h
function namespace (line 5) | namespace FEX {
FILE: Source/Tools/FEXBash/FEXBash.cpp
function main (line 16) | int main(int argc, char** argv, char** const envp) {
FILE: Source/Tools/FEXConfig/Main.cpp
type fextl (line 30) | namespace fextl {
function string_from_path (line 32) | inline fextl::string string_from_path(const std::filesystem::path& Pat...
function LoadThunkDatabase (line 44) | static void LoadThunkDatabase(fextl::unordered_map<fextl::string, bool>&...
function QString (line 139) | QString ConfigModel::getString(const QString& Name, bool) const {
function QStringList (line 147) | QStringList ConfigModel::getStringList(const QString& Name, bool) const {
function LoadDefaultSettings (line 172) | static void LoadDefaultSettings() {
function ConfigInit (line 188) | static void ConfigInit(fextl::string ConfigFilename) {
function QUrl (line 341) | QUrl RootFSModel::getBaseUrl() const {
type inotify_event (line 350) | struct inotify_event
function OpenFile (line 364) | static bool OpenFile(fextl::string Filename) {
function main (line 452) | int main(int Argc, char** Argv) {
FILE: Source/Tools/FEXConfig/Main.h
function class (line 13) | class ConfigModel : public QStandardItemModel {
function class (line 38) | class HostLibsModel : public QStandardItemModel {
function class (line 55) | class RootFSModel : public QStandardItemModel {
function class (line 77) | class ConfigRuntime : public QObject {
FILE: Source/Tools/FEXGDBReader/FEXGDBReader.cpp
function read_debug_info (line 15) | static enum gdb_status read_debug_info(struct gdb_reader_funcs* self, st...
function unwind_frame (line 53) | enum gdb_status unwind_frame(struct gdb_reader_funcs* self, struct gdb_u...
function get_frame_id (line 57) | struct gdb_frame_id get_frame_id(struct gdb_reader_funcs* self, struct g...
function destroy_reader (line 62) | void destroy_reader(struct gdb_reader_funcs* self) {}
type gdb_reader_funcs (line 64) | struct gdb_reader_funcs
type gdb_reader_funcs (line 65) | struct gdb_reader_funcs
FILE: Source/Tools/FEXGetConfig/Main.cpp
type TSOEmulationFacts (line 19) | struct TSOEmulationFacts {
function CheckForHardwareTSO (line 26) | bool CheckForHardwareTSO() {
type ISAR0_FIELDS (line 45) | enum ISAR0_FIELDS {
type ISAR1_FIELDS (line 49) | enum ISAR1_FIELDS {
type MMFR2_FIELDS (line 53) | enum MMFR2_FIELDS {
function GetISAR0 (line 58) | uint64_t GetISAR0() {
function GetISAR1 (line 64) | uint64_t GetISAR1() {
function GetMMFR2 (line 70) | uint64_t GetMMFR2() {
function TSOEmulationFacts (line 76) | TSOEmulationFacts GetTSOEmulationFacts() {
function TSOEmulationFacts (line 91) | TSOEmulationFacts GetTSOEmulationFacts() {
function main (line 97) | int main(int argc, char** argv, char** envp) {
FILE: Source/Tools/FEXInterpreter/AOT/AOTGenerator.cpp
type FEX::AOT (line 19) | namespace FEX::AOT {
function AOTGenSection (line 20) | void AOTGenSection(FEXCore::Context::Context* CTX, ELFCodeLoader::Load...
FILE: Source/Tools/FEXInterpreter/AOT/AOTGenerator.h
function namespace (line 6) | namespace FEX::AOT {
FILE: Source/Tools/FEXInterpreter/ELFCodeLoader.h
function ELFParser (line 42) | ELFParser MainElf {}
function ELFParser (line 43) | ELFParser InterpElf {}
function ElfValid (line 45) | bool ElfValid {false};
function StackHint (line 459) | uint64_t StackHint {}
function ASLR_Offset (line 574) | uint64_t ASLR_Offset {}
function CloseFDs (line 685) | void CloseFDs() {
function SetupPointers (line 692) | static void SetupPointers(uintptr_t StackPointer, uint64_t AuxVOffset, u...
function ArgumentBackingSize (line 1038) | uint64_t ArgumentBackingSize {}
function ArgumentOffset (line 1039) | uint64_t ArgumentOffset {}
function EnvironmentBackingSize (line 1040) | uint64_t EnvironmentBackingSize {}
function BaseOffset (line 1041) | uint64_t BaseOffset {}
function HWCap (line 1043) | uint64_t HWCap {}
function HWCap2 (line 1044) | uint64_t HWCap2 {}
function SupportsAVX (line 1045) | bool SupportsAVX {}
function auxv_t (line 1047) | auxv_t* AuxRandom {}
function auxv_t (line 1048) | auxv_t* AuxPlatform {}
function auxv_t (line 1049) | auxv_t* AuxExecFN {}
FILE: Source/Tools/FEXInterpreter/FEXInterpreter.cpp
type FEX::Logging (line 68) | namespace FEX::Logging {
function MsgHandler (line 75) | void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 86) | void AssertHandler(const char* Message) {
type FEXServer (line 90) | namespace FEXServer {
function MsgHandler (line 93) | void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 97) | void AssertHandler(const char* Message) {
function Init (line 102) | void Init() {
type FEX::Allocator (line 145) | namespace FEX::Allocator {
function InitMemoryRegions (line 147) | fextl::vector<FEXCore::Allocator::MemoryRegion> InitMemoryRegions(bool...
function InitAllocator (line 160) | fextl::unique_ptr<FEX::HLE::MemAllocator> InitAllocator(bool Is64Bit) {
function Shutdown (line 186) | void Shutdown(fextl::vector<FEXCore::Allocator::MemoryRegion>&& Memory...
function InterpreterHandler (line 192) | bool InterpreterHandler(fextl::string* Filename, const fextl::string& Ro...
function QueryInterpreterInstalled (line 240) | bool QueryInterpreterInstalled(bool ExecutedWithFD, const FEX::Config::P...
type FEX::Kernel (line 252) | namespace FEX::Kernel {
type TSO (line 253) | namespace TSO {
function SetupTSOEmulation (line 254) | void SetupTSOEmulation(FEXCore::Context::Context* CTX) {
type CompatInput (line 281) | namespace CompatInput {
function SetupCompatInput (line 282) | void SetupCompatInput(bool enable) {
type GCS (line 298) | namespace GCS {
function CheckForGCS (line 299) | void CheckForGCS() {
type UnalignedAtomic (line 316) | namespace UnalignedAtomic {
function SetupKernelUnalignedAtomics (line 317) | void SetupKernelUnalignedAtomics() {
function Init (line 336) | void Init(bool Is64Bit, FEXCore::Context::Context* CTX) {
function StealFEXFDFromEnv (line 361) | static int StealFEXFDFromEnv(const char* Env) {
function main (line 372) | int main(int argc, char** argv, char** const envp) {
FILE: Source/Tools/FEXOfflineCompiler/Main.cpp
class AOTSyscallHandler (line 24) | class AOTSyscallHandler : public FEXCore::HLE::SyscallHandler, public FE...
method AOTSyscallHandler (line 26) | AOTSyscallHandler(FEXCore::HLE::SyscallOSABI SyscallOSABI) {
method HandleSyscall (line 30) | uint64_t HandleSyscall(FEXCore::Core::CpuStateFrame* Frame, FEXCore::H...
method LookupExecutableFileSection (line 41) | std::optional<FEXCore::ExecutableFileSectionInfo> LookupExecutableFile...
method QueryGuestExecutableRange (line 49) | FEXCore::HLE::ExecutableRangeInfo QueryGuestExecutableRange(FEXCore::C...
method GuestMunmap (line 63) | uint64_t GuestMunmap(FEXCore::Core::InternalThreadState*, void* addr, ...
function MsgHandler (line 68) | static void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 72) | static void AssertHandler(const char* Message) {
type FEXCore (line 76) | namespace FEXCore {
type std::hash<FEXCore::ExecutableFileInfo> (line 83) | struct std::hash<FEXCore::ExecutableFileInfo> {
function GenerateSingleCache (line 118) | static std::optional<std::string> GenerateSingleCache(FEXCore::Executabl...
function GenerateCache (line 229) | static int GenerateCache(int argc, const char** argv) {
function main (line 305) | int main(int argc, char** argv) {
FILE: Source/Tools/FEXRootFSFetcher/Main.cpp
type ArgOptions (line 28) | namespace ArgOptions {
type CompressedImageOption (line 30) | enum class CompressedImageOption {
type ListQueryOption (line 38) | enum class ListQueryOption {
type UIOverrideOption (line 50) | enum class UIOverrideOption {
function ParseArguments (line 58) | void ParseArguments(int argc, char** argv) {
type Exec (line 114) | namespace Exec {
function ExecAndWaitForResponse (line 115) | int32_t ExecAndWaitForResponse(const char* path, char* const* args) {
function ExecAndWaitForResponseRedirect (line 131) | int32_t ExecAndWaitForResponseRedirect(const char* path, char* const* ...
function ExecAndWaitForResponseText (line 168) | std::string ExecAndWaitForResponseText(const char* path, char* const* ...
type WorkingAppsTester (line 214) | namespace WorkingAppsTester {
function CheckCurl (line 224) | void CheckCurl() {
function CheckSquashfuse (line 236) | void CheckSquashfuse() {
function CheckUnsquashfs (line 247) | void CheckUnsquashfs() {
function CheckZenity (line 293) | void CheckZenity() {
function CheckEroFSFuse (line 306) | void CheckEroFSFuse() {
function CheckEroFSFsck (line 317) | void CheckEroFSFsck() {
function Init (line 328) | void Init() {
type DistroQuery (line 338) | namespace DistroQuery {
type DistroInfo (line 339) | struct DistroInfo {
function DistroInfo (line 346) | DistroInfo GetDistroInfo() {
type WebFileFetcher (line 480) | namespace WebFileFetcher {
type FileTargets (line 481) | struct FileTargets {
type FileType (line 496) | enum class FileType {
function DownloadToString (line 506) | std::string DownloadToString(const std::string& URL) {
function DownloadToPath (line 516) | bool DownloadToPath(const fextl::string& URL, const fextl::string& Pat...
function DownloadToPathWithZenityProgress (line 527) | bool DownloadToPathWithZenityProgress(const fextl::string& URL, const ...
function GetRootFSLinks (line 551) | std::optional<std::vector<FileTargets>> GetRootFSLinks() {
type Zenity (line 617) | namespace Zenity {
function ExecWithQuestion (line 618) | bool ExecWithQuestion(const fextl::string& Question) {
function ExecWithInfo (line 632) | void ExecWithInfo(const fextl::string& Text) {
function AskForConfirmation (line 644) | bool AskForConfirmation(const fextl::string& Question) {
function AskForConfirmationList (line 648) | int32_t AskForConfirmationList(const fextl::string& Text, const std::s...
function AskForComplexConfirmationList (line 674) | int32_t AskForComplexConfirmationList(const std::string& Text, const s...
function AskForDistroSelection (line 695) | int32_t AskForDistroSelection(DistroQuery::DistroInfo& Info, const std...
function ValidateCheckExists (line 737) | bool ValidateCheckExists(const WebFileFetcher::FileTargets& Target) {
function ValidateDownloadSelection (line 776) | bool ValidateDownloadSelection(const WebFileFetcher::FileTargets& Targ...
type TTY (line 804) | namespace TTY {
function AskForConfirmation (line 805) | bool AskForConfirmation(const fextl::string& Question) {
function ExecWithInfo (line 830) | void ExecWithInfo(const fextl::string& Text) {
function AskForConfirmationList (line 834) | int32_t AskForConfirmationList(const fextl::string& Text, std::span<co...
function AskForDistroSelection (line 858) | int32_t AskForDistroSelection(DistroQuery::DistroInfo& Info, const std...
function ValidateCheckExists (line 895) | bool ValidateCheckExists(const WebFileFetcher::FileTargets& Target) {
function ValidateDownloadSelection (line 933) | bool ValidateDownloadSelection(const WebFileFetcher::FileTargets& Targ...
function CheckTTY (line 980) | void CheckTTY() {
function AskForConfirmation (line 1013) | bool AskForConfirmation(const fextl::string& Question) {
function ExecWithInfo (line 1017) | void ExecWithInfo(const fextl::string& Text) {
function AskForConfirmationList (line 1021) | int32_t AskForConfirmationList(const fextl::string& Text, const std::spa...
function AskForDistroSelection (line 1025) | int32_t AskForDistroSelection(const std::span<const WebFileFetcher::File...
function ValidateCheckExists (line 1038) | bool ValidateCheckExists(const WebFileFetcher::FileTargets& Target) {
function ValidateDownloadSelection (line 1042) | bool ValidateDownloadSelection(const WebFileFetcher::FileTargets& Target) {
type ConfigSetter (line 1047) | namespace ConfigSetter {
function SetRootFSAsDefault (line 1048) | void SetRootFSAsDefault(const fextl::string& RootFS) {
type UnSquash (line 1057) | namespace UnSquash {
function UnsquashRootFS (line 1058) | bool UnsquashRootFS(const fextl::string& Path, const fextl::string& Ro...
function ExtractEroFS (line 1081) | bool ExtractEroFS(const fextl::string& Path, const fextl::string& Root...
function main (line 1111) | int main(int argc, char** argv, char** const envp) {
FILE: Source/Tools/FEXRootFSFetcher/XXFileHash.cpp
type XXFileHash (line 11) | namespace XXFileHash {
function HashFile (line 14) | std::optional<uint64_t> HashFile(const fextl::string& Filepath) {
FILE: Source/Tools/FEXRootFSFetcher/XXFileHash.h
function namespace (line 7) | namespace XXFileHash {
FILE: Source/Tools/FEXServer/ArgumentLoader.cpp
type FEXServer::Config (line 11) | namespace FEXServer::Config {
function FEXServerOptions (line 14) | FEXServerOptions Load(int argc, char** argv) {
FILE: Source/Tools/FEXServer/ArgumentLoader.h
function namespace (line 5) | namespace FEXServer::Config {
FILE: Source/Tools/FEXServer/Logger.cpp
type Logging (line 8) | namespace Logging {
type Logger (line 12) | namespace Logger {
function HandleLogData (line 16) | void HandleLogData(int Socket) {
function LogThreadFunc (line 57) | void LogThreadFunc() {
function StartLogThread (line 92) | void StartLogThread() {
function AppendLogFD (line 98) | void AppendLogFD(int FD) {
function LogThreadRunning (line 102) | bool LogThreadRunning() {
function Shutdown (line 106) | void Shutdown() {
FILE: Source/Tools/FEXServer/Logger.h
function namespace (line 4) | namespace Logger {
FILE: Source/Tools/FEXServer/Main.cpp
type Logging (line 39) | namespace Logging {
function MsgHandler (line 40) | void MsgHandler(LogMan::DebugLevels Level, const char* Message) {
function AssertHandler (line 45) | void AssertHandler(const char* Message) {
function ClientMsgHandler (line 49) | void ClientMsgHandler(int FD, FEXServerClient::Logging::PacketMsg* con...
function ActionHandler (line 67) | void ActionHandler(int sig, siginfo_t* info, void* context) {
function ActionIgnore (line 80) | void ActionIgnore(int sig, siginfo_t* info, void* context) {}
function SetupSignals (line 82) | void SetupSignals() {
function DeparentSelf (line 107) | void DeparentSelf() {
function main (line 124) | int main(int argc, char** argv, char** const envp) {
FILE: Source/Tools/FEXServer/PipeScanner.cpp
type PipeScanner (line 9) | namespace PipeScanner {
function SetWaitPipe (line 11) | void SetWaitPipe(int FD) {
function ClosePipes (line 18) | void ClosePipes() {
FILE: Source/Tools/FEXServer/PipeScanner.h
function namespace (line 3) | namespace PipeScanner {
FILE: Source/Tools/FEXServer/ProcessPipe.cpp
type FEXCore (line 32) | namespace FEXCore {
type std::hash<FEXCore::ExecutableFileInfo> (line 39) | struct std::hash<FEXCore::ExecutableFileInfo> {
type ProcessPipe (line 45) | namespace ProcessPipe {
type pollfd (line 54) | struct pollfd
function SetWatchFD (line 67) | void SetWatchFD(int FD) {
function GetNumFilesOpen (line 71) | size_t GetNumFilesOpen() {
function GetMaxFDs (line 78) | void GetMaxFDs() {
function CheckRaiseFDLimit (line 88) | void CheckRaiseFDLimit() {
function InitializeServerPipe (line 119) | bool InitializeServerPipe() {
function InitializeServerSocket (line 221) | bool InitializeServerSocket(bool abstract) {
function SendEmptyErrorPacket (line 274) | void SendEmptyErrorPacket(fasio::tcp_socket& Socket) {
function SendFDSuccessPacket (line 286) | void SendFDSuccessPacket(fasio::tcp_socket& Socket, int FD) {
function ImportPendingCodeMaps (line 299) | static std::map<FEXCore::ExecutableFileInfo, fextl::set<uintptr_t>>
function WriteNewCodeMap (line 357) | static void WriteNewCodeMap(const FEXCore::ExecutableFileInfo& File, c...
type NeedsCacheRefresh (line 392) | enum class NeedsCacheRefresh {
function AggregateCodeMaps (line 405) | static std::map<FEXCore::ExecutableFileInfo, NeedsCacheRefresh> Aggreg...
function EmbedSubprocess (line 452) | int32_t EmbedSubprocess(const char* path, char* const* args) {
function RunOfflineCompiler (line 472) | static int RunOfflineCompiler(const char* CodeMap) {
function HandleSocketData (line 477) | void HandleSocketData(fasio::tcp_socket& Socket) {
function CloseConnections (line 712) | void CloseConnections() {
function WaitForRequests (line 722) | void WaitForRequests() {
function SetConfiguration (line 762) | void SetConfiguration(bool Foreground, uint32_t PersistentTimeout) {
function Shutdown (line 770) | void Shutdown() {
FILE: Source/Tools/FEXServer/ProcessPipe.h
function namespace (line 5) | namespace ProcessPipe {
FILE: Source/Tools/FEXServer/SquashFS.cpp
type SquashFS (line 17) | namespace SquashFS {
function ShutdownImagePID (line 24) | void ShutdownImagePID() {
function InitializeSquashFSPipe (line 30) | bool InitializeSquashFSPipe() {
function DowngradeRootFSPipeToReadLock (line 87) | bool DowngradeRootFSPipeToReadLock() {
function MountRootFSImagePath (line 107) | bool MountRootFSImagePath(const fextl::string& SquashFS, bool EroFS) {
function UnmountRootFS (line 191) | void UnmountRootFS() {
function InitializeSquashFS (line 234) | bool InitializeSquashFS() {
FILE: Source/Tools/FEXServer/SquashFS.h
function namespace (line 5) | namespace SquashFS {
FILE: Source/Tools/LinuxEmulation/ArchHelpers/MContext.cpp
type FEX::ArchHelpers::Context (line 4) | namespace FEX::ArchHelpers::Context {
function GetESRName (line 6) | std::string_view GetESRName(uint64_t ESR) {
FILE: Source/Tools/LinuxEmulation/ArchHelpers/MContext.h
function namespace (line 18) | namespace FEX::ArchHelpers::Context {
FILE: Source/Tools/LinuxEmulation/ArchHelpers/UContext.h
function namespace (line 12) | namespace FEXCore {
FILE: Source/Tools/LinuxEmulation/ArchHelpers/WinContext.h
function namespace (line 7) | namespace FEX::ArchHelpers::Context {
FILE: Source/Tools/LinuxEmulation/GdbServer/Info.cpp
type FEX::GDB::Info (line 23) | namespace FEX::GDB::Info {
function GetGRegName (line 33) | std::string_view GetGRegName(unsigned Reg) {
function GetThreadName (line 55) | fextl::string GetThreadName(uint32_t PID, uint32_t ThreadID) {
function BuildOSXML (line 63) | fextl::string BuildOSXML() {
function BuildTargetXML (line 78) | fextl::string BuildTargetXML(bool Is64Bit) {
FILE: Source/Tools/LinuxEmulation/GdbServer/Info.h
function namespace (line 15) | namespace FEXCore::X86State {
function namespace (line 19) | namespace FEX::GDB::Info {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Arm64/SyscallsEnum.h
function namespace (line 9) | namespace FEX::HLE::Arm64 {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/EmulatedFiles/EmulatedFiles.cpp
type FEX::EmulatedFile (line 36) | namespace FEX::EmulatedFile {
function GenTmpFD (line 51) | static int GenTmpFD(const char* pathname, int flags) {
function SealTmpFD (line 62) | static void SealTmpFD(int fd) {
function GenerateCPUInfo (line 70) | fextl::string GenerateCPUInfo(FEXCore::Context::Context* ctx, uint32_t...
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/EmulatedFiles/EmulatedFiles.h
function namespace (line 17) | namespace FEXCore::Context {
function namespace (line 21) | namespace FEX::EmulatedFile {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/FaultSafeUserMemAccess.cpp
type FEX::HLE::FaultSafeUserMemAccess (line 4) | namespace FEX::HLE::FaultSafeUserMemAccess {
function CopyFromUser (line 6) | __attribute__((naked)) size_t CopyFromUser(void* Dest, const void* Src...
function CopyToUser (line 25) | __attribute__((naked)) size_t CopyToUser(void* Dest, const void* Src, ...
function VerifyIsReadableImpl (line 51) | __attribute__((naked)) bool VerifyIsReadableImpl(const void* Src, size...
function VerifyIsOnlyWritable (line 70) | __attribute__((naked)) bool VerifyIsOnlyWritable(void* Src, size_t Siz...
function VerifyIsStringReadableMaxSizeImpl (line 91) | __attribute__((naked)) bool VerifyIsStringReadableMaxSizeImpl(const ch...
function VerifyIsReadable (line 109) | void VerifyIsReadable(const void* Src, size_t Size) {
function VerifyIsStringReadable (line 113) | void VerifyIsStringReadable(const char* Src) {
function VerifyIsStringReadableMaxSize (line 117) | void VerifyIsStringReadableMaxSize(const char* Src, size_t MaxSize) {
function VerifyIsReadableOrNull (line 121) | void VerifyIsReadableOrNull(const void* Src, size_t Size) {
function VerifyIsWritable (line 129) | void VerifyIsWritable(void* Src, size_t Size) {
function VerifyIsWritableOrNull (line 136) | void VerifyIsWritableOrNull(void* Src, size_t Size) {
function IsFaultLocation (line 156) | bool IsFaultLocation(uint64_t PC) {
function CopyFromUser (line 169) | size_t CopyFromUser(void* Dest, const void* Src, size_t Size) {
function CopyToUser (line 174) | size_t CopyToUser(void* Dest, const void* Src, size_t Size) {
function IsFaultLocation (line 179) | bool IsFaultLocation(uint64_t PC) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/FileManagement.cpp
type FEX::HLE (line 47) | namespace FEX::HLE {
function SetupOverlay (line 286) | void SetupOverlay(const ThunkDBObject& DBDepend) {
function InsertDependencies (line 302) | void InsertDependencies(const fextl::unordered_set<fextl::string>& Dep...
type stat (line 336) | struct stat
type stat (line 379) | struct stat
type stat (line 380) | struct stat
type stat (line 524) | struct stat
function ShouldSkipOpenInEmu (line 607) | static bool ShouldSkipOpenInEmu(int flags) {
type stat (line 721) | struct stat
type stat (line 726) | struct stat
type stat (line 737) | struct stat
type stat (line 743) | struct stat
type statx (line 977) | struct statx
type statfs (line 1016) | struct statfs
type statfs (line 1021) | struct statfs
type stat (line 1024) | struct stat
type stat64 (line 1044) | struct stat64
type stat (line 1269) | struct stat
type stat (line 1303) | struct stat
type stat (line 1321) | struct stat
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/FileManagement.h
function namespace (line 30) | namespace FEXCore::Context {
function namespace (line 34) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/GdbServer.cpp
type FEX (line 61) | namespace FEX {
function calculateChecksum (line 129) | static int calculateChecksum(const fextl::string& packet) {
function hexstring (line 137) | static fextl::string hexstring(fextl::istringstream& ss, int delm) {
function appendHex (line 154) | static fextl::string appendHex(const char* data, size_t length) {
function encodeHex (line 158) | static fextl::string encodeHex(const unsigned char* data, size_t lengt...
function encodeHex (line 167) | static fextl::string encodeHex(std::string_view str) {
function escapePacket (line 234) | static fextl::string escapePacket(const fextl::string& packet) {
type FileData (line 347) | struct FileData {
type stat (line 376) | struct stat
function CheckMemMapping (line 569) | static size_t CheckMemMapping(uint64_t Address, size_t Size) {
type utsname (line 1007) | struct utsname
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/GdbServer.h
function AlertLibrariesChanged (line 34) | void AlertLibrariesChanged() {
function Event (line 49) | Event ThreadBreakEvent {}
type HandledPacketType (line 52) | struct HandledPacketType {
function fextl (line 73) | static fextl::string EncodeXferString(const fextl::string& data, int off...
type X80Float (line 121) | struct X80Float {
function GDBContextDefinition (line 125) | struct FEX_PACKED GDBContextDefinition {
function NoAckMode (line 154) | bool NoAckMode {false};
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/LinuxAllocator.cpp
type FEX::HLE (line 22) | namespace FEX::HLE {
class MemAllocator32Bit (line 23) | class MemAllocator32Bit final : public FEX::HLE::MemAllocator {
method MemAllocator32Bit (line 30) | MemAllocator32Bit() {
method SetUsedPages (line 58) | void SetUsedPages(uint64_t PageAddr, size_t PagesLength) {
method SetFreePages (line 67) | void SetFreePages(uint64_t PageAddr, size_t PagesLength) {
type shmid_ds (line 428) | struct shmid_ds
type shmid_ds (line 444) | struct shmid_ds
type shmid_ds (line 518) | struct shmid_ds
class MemAllocatorPassThrough (line 535) | class MemAllocatorPassThrough final : public FEX::HLE::MemAllocator {
method Munmap (line 545) | int Munmap(void* addr, size_t length) override {
method Shmat (line 558) | uint64_t Shmat(int shmid, const void* shmaddr, int shmflg, uint32_t*...
method Shmdt (line 567) | uint64_t Shmdt(const void* shmaddr) override {
function Create32BitAllocator (line 573) | fextl::unique_ptr<FEX::HLE::MemAllocator> Create32BitAllocator() {
function CreatePassthroughAllocator (line 577) | fextl::unique_ptr<FEX::HLE::MemAllocator> CreatePassthroughAllocator() {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/LinuxAllocator.h
function namespace (line 9) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Seccomp/BPFEmitter.cpp
type FEX::HLE (line 17) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Seccomp/BPFEmitter.h
type sock_fprog (line 16) | struct sock_fprog
type sock_filter (line 17) | struct sock_filter
function namespace (line 19) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Seccomp/Dumper.cpp
type FEX::HLE (line 14) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Seccomp/SeccompEmulator.cpp
type FEX::HLE (line 123) | namespace FEX::HLE {
type seccomp_notif_sizes (line 134) | struct seccomp_notif_sizes
type SerializedFilter (line 196) | struct SerializedFilter {
type SerializationHeader (line 203) | struct SerializationHeader {
type sock_filter (line 494) | struct sock_filter
type sock_filter (line 507) | struct sock_filter
type sock_filter (line 523) | struct sock_filter
type sock_filter (line 528) | struct sock_filter
type seccomp_notif_sizes (line 711) | struct seccomp_notif_sizes
type seccomp_notif (line 716) | struct seccomp_notif
type seccomp_notif_resp (line 717) | struct seccomp_notif_resp
type seccomp_data (line 718) | struct seccomp_data
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Seccomp/SeccompEmulator.h
type sock_fprog (line 19) | struct sock_fprog
type seccomp_data (line 20) | struct seccomp_data
type seccomp_notif_sizes (line 21) | struct seccomp_notif_sizes
function namespace (line 23) | namespace FEXCore {
function namespace (line 35) | namespace FEX::HLE {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.cpp
type FEX::HLE (line 44) | namespace FEX::HLE {
function sigrestore (line 46) | __attribute__((naked)) static void sigrestore() {
function SignalHandlerThunk (line 60) | static void SignalHandlerThunk(int Signal, siginfo_t* Info, void* UCon...
function SigIsMember (line 67) | uint64_t SigIsMember(GuestSAMask* Set, int Signal) {
function SetSignal (line 73) | uint64_t SetSignal(GuestSAMask* Set, int Signal) {
function IsAsyncSignal (line 533) | static bool IsAsyncSignal(const siginfo_t* Info, int Signal) {
function CheckForPendingSignals (line 1197) | static void CheckForPendingSignals(const FEX::HLE::ThreadStateObject* ...
type timespec (line 1317) | struct timespec
function CreateSignalDelegator (line 1354) | fextl::unique_ptr<FEX::HLE::SignalDelegator>
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator.h
function namespace (line 31) | namespace FEXCore::Context {
function namespace (line 34) | namespace FEXCore::Core {
function namespace (line 37) | namespace FEX::HLE {
type GuestSigAction (line 87) | struct GuestSigAction
type timespec (line 94) | struct timespec
function SetVDSOSymbols (line 111) | void SetVDSOSymbols() {
function HandleSignalHandlerReturn (line 120) | [[noreturn]]
function SetHostSignalHandler (line 164) | void SetHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, ...
function SetFrontendHostSignalHandler (line 167) | void SetFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunctio...
type DefaultBehaviourType (line 177) | enum DefaultBehaviourType {
type kernel_sigaction (line 185) | struct kernel_sigaction {
type SignalHandler (line 197) | struct SignalHandler {
function kernel_sigaction (line 200) | kernel_sigaction HostAction {}
function kernel_sigaction (line 201) | kernel_sigaction OldAction {}
function GuestSigAction (line 203) | GuestSigAction GuestAction {}
function DefaultBehaviourType (line 204) | DefaultBehaviourType DefaultBehaviour {DEFAULT_TERM};
function IsAddressInDispatcher (line 217) | bool IsAddressInDispatcher(uint64_t Address) const {
type SigFrame_i32 (line 231) | struct SigFrame_i32 {
type RTSigFrame_i32 (line 243) | struct RTSigFrame_i32 {
function RestoreType (line 276) | enum class RestoreType {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator/GuestFramesManagement.cpp
type FEX::HLE (line 23) | namespace FEX::HLE {
type SigInfoLayout (line 26) | enum class SigInfoLayout {
function SigInfoLayout (line 38) | static SigInfoLayout CalculateSigInfoLayout(int Signal, int si_code, u...
function ConvertSignalToTrapNo (line 76) | static uint32_t ConvertSignalToTrapNo(int Signal, siginfo_t* HostSigIn...
function ConvertSignalToError (line 90) | static uint32_t ConvertSignalToError(void* ucontext, int Signal, sigin...
function SetXStateInfo (line 106) | static void SetXStateInfo(T* xstate, bool is_avx_enabled) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls.cpp
type FEX::HLE (line 65) | namespace FEX::HLE {
class SignalDelegator (line 66) | class SignalDelegator
function GetDentsEmulation (line 70) | uint64_t GetDentsEmulation(int fd, T* dirp, uint32_t count) {
function GetShebangInterpFile (line 143) | static fextl::string GetShebangInterpFile(std::span<char> Data) {
function GetShebangInterpFD (line 172) | static fextl::string GetShebangInterpFD(int FD) {
function GetShebangInterpFilename (line 186) | static fextl::string GetShebangInterpFilename(const fextl::string& Fil...
function ExecveHandler (line 198) | uint64_t ExecveHandler(FEXCore::Core::CpuStateFrame* Frame, const char...
function AnyFlagsSet (line 449) | static bool AnyFlagsSet(uint64_t Flags, uint64_t Mask) {
function AllFlagsSet (line 453) | static bool AllFlagsSet(uint64_t Flags, uint64_t Mask) {
type StackFrameData (line 457) | struct StackFrameData {
type StackFramePlusRet (line 464) | struct StackFramePlusRet {
function CloneBody (line 470) | [[noreturn]]
function Clone3HandlerRet (line 482) | [[noreturn]]
function Clone2HandlerRet (line 488) | static int Clone2HandlerRet(void* arg) {
function PrintFlags (line 505) | static void PrintFlags(uint64_t Flags) {
function Clone2Handler (line 536) | static uint64_t Clone2Handler(FEXCore::Core::CpuStateFrame* Frame, FEX...
function Clone3Handler (line 560) | static uint64_t Clone3Handler(FEXCore::Core::CpuStateFrame* Frame, FEX...
function CloneHandler (line 590) | uint64_t CloneHandler(FEXCore::Core::CpuStateFrame* Frame, FEX::HLE::c...
type utsname (line 806) | struct utsname
function UnimplementedSyscall (line 892) | uint64_t UnimplementedSyscall(FEXCore::Core::CpuStateFrame* Frame, uin...
function UnimplementedSyscallSafe (line 897) | uint64_t UnimplementedSyscallSafe(FEXCore::Core::CpuStateFrame* Frame,...
function isHEX (line 932) | static bool isHEX(char c) {
type stat (line 944) | struct stat
type stat (line 960) | struct stat
type stat (line 972) | struct stat
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls.h
function namespace (line 57) | namespace FEX {
function namespace (line 61) | namespace FEXCore {
function namespace (line 70) | namespace FEX::HLE {
function KernelMajor (line 221) | static uint32_t KernelMajor(uint32_t Version) {
function KernelMinor (line 224) | static uint32_t KernelMinor(uint32_t Version) {
function KernelPatch (line 227) | static uint32_t KernelPatch(uint32_t Version) {
function virtual (line 231) | virtual FEX::HLE::MemAllocator* Get32BitAllocator() {
type LateApplyExtendedVolatileMetadata (line 250) | struct LateApplyExtendedVolatileMetadata {
function InvalidateCodeRangeIfNecessary (line 264) | void InvalidateCodeRangeIfNecessary(FEXCore::Core::InternalThreadState* ...
function InvalidateCodeRangeIfNecessaryOnRemap (line 270) | void InvalidateCodeRangeIfNecessaryOnRemap(FEXCore::Core::InternalThread...
function SourcecodeResolver (line 306) | SourcecodeResolver* GetSourcecodeResolver() override {
function SleepThread (line 310) | void SleepThread(FEXCore::Context::Context* CTX, FEXCore::Core::CpuState...
function DisableXIDCheck (line 317) | void DisableXIDCheck() {
function DataSpace (line 343) | uint64_t DataSpace {}
function DataSpaceSize (line 344) | uint64_t DataSpaceSize {}
function DataSpaceMappedSize (line 345) | uint64_t DataSpaceMappedSize {}
function HostKernelVersion (line 348) | uint32_t HostKernelVersion {}
function GuestKernelVersion (line 349) | uint32_t GuestKernelVersion {}
function NeedToCheckXID (line 362) | bool NeedToCheckXID {true};
function string (line 418) | string CollectArgsFmtString() {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/EPoll.cpp
type FEX::HLE (line 18) | namespace FEX::HLE {
function RegisterEpoll (line 19) | void RegisterEpoll(FEX::HLE::SyscallHandler* Handler) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/FD.cpp
type FEX::HLE (line 31) | namespace FEX::HLE {
function RegisterFD (line 32) | void RegisterFD(FEX::HLE::SyscallHandler* Handler) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/FS.cpp
type FEX::HLE (line 24) | namespace FEX::HLE {
function RegisterFS (line 25) | void RegisterFS(FEX::HLE::SyscallHandler* Handler) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/IO.cpp
type FEX::HLE (line 18) | namespace FEX::HLE {
function RegisterIO (line 19) | void RegisterIO(FEX::HLE::SyscallHandler* Handler) {
FILE: Source/Tools/LinuxEmulation/LinuxSyscalls/Syscalls/Info.cpp
type FEX::HLE (line 33) | namespace FEX::HLE {
function RegisterInfo (line 37) | void RegisterInfo(FEX::HLE::SyscallHa
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"chars": 479,
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"path": ".git-blame-ignore-revs",
"chars": 877,
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"chars": 1275,
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},
{
"path": ".github/workflows/wine_dll_artifacts.yml",
"chars": 1194,
"preview": "name: Wine DLL artifacts\n\non:\n push:\n branches:\n - main\n\nenv:\n BUILD_TYPE: Release\n\njobs:\n wine_dll_artifacts"
},
{
"path": ".gitignore",
"chars": 131,
"preview": "# Existing\n\ncompile_commands.json\nvim_rc\nConfig.json\n\n[Bb]uild*\n[Bb]in/\nout/\n.vscode/\n.vs/\n*.pyc\n.cache\n.idea/\nCMakeList"
},
{
"path": ".gitlab-ci.yml",
"chars": 2370,
"preview": "spec:\n inputs:\n PROMOTE_BRANCH:\n description: \"Branch to promote the build to. Empty means no promotion.\"\n "
},
{
"path": ".gitmodules",
"chars": 1930,
"preview": "[submodule \"External/vixl\"]\n\tshallow = true\n\tpath = External/vixl\n\turl = https://github.com/FEX-Emu/vixl.git\n[submodule "
},
{
"path": "CMakeLists.txt",
"chars": 24860,
"preview": "cmake_minimum_required(VERSION 3.14)\nproject(FEX C CXX ASM)\n\ninclude(CheckIncludeFiles)\ncheck_include_files(\"gdb/jit-rea"
},
{
"path": "CMakeSettings.json",
"chars": 3581,
"preview": "{\r\n\t\"environments\": [\r\n\t\t{\r\n\t\t\t\"BuildPath\": \"${projectDir}\\\\out\\\\build\\\\${name}\",\r\n\t\t\t\"InstallPath\": \"${projectDir}\\\\ou"
},
{
"path": "CODE_OF_CONDUCT.md",
"chars": 3348,
"preview": "# Contributor Covenant Code of Conduct\n\n## Our Pledge\n\nIn the interest of fostering an open and welcoming environment, w"
},
{
"path": "CodeEmitter/CMakeLists.txt",
"chars": 87,
"preview": "add_library(CodeEmitter INTERFACE)\ntarget_include_directories(CodeEmitter INTERFACE .)\n"
},
{
"path": "CodeEmitter/CodeEmitter/ALUOps.inl",
"chars": 52901,
"preview": "// SPDX-License-Identifier: MIT\n/* ALU instruction emitters.\n *\n * Almost all of these operations have `ARMEmitter::Size"
},
{
"path": "CodeEmitter/CodeEmitter/ASIMDOps.inl",
"chars": 181701,
"preview": "// SPDX-License-Identifier: MIT\n/* ASIMD instruction emitters.\n *\n * This contains emitters for vector operations explic"
},
{
"path": "CodeEmitter/CodeEmitter/BranchOps.inl",
"chars": 13349,
"preview": "// SPDX-License-Identifier: MIT\n/* Branch instruction emitters.\n *\n * Most of these instructions will use `BackwardLabel"
},
{
"path": "CodeEmitter/CodeEmitter/Buffer.h",
"chars": 2229,
"preview": "// SPDX-License-Identifier: MIT\n#pragma once\n#include <cstddef>\n#include <cstdint>\n#include <cstring>\n#include <type_tra"
},
{
"path": "CodeEmitter/CodeEmitter/Emitter.h",
"chars": 28550,
"preview": "// SPDX-License-Identifier: MIT\n#pragma once\n\n#include <FEXCore/Utils/CompilerDefs.h>\n#include <FEXCore/Utils/EnumUtils."
},
{
"path": "CodeEmitter/CodeEmitter/LoadstoreOps.inl",
"chars": 233011,
"preview": "// SPDX-License-Identifier: MIT\n/* Load-store instruction emitters\n *\n * For GPR load-stores that take a `Size` argument"
},
{
"path": "CodeEmitter/CodeEmitter/Registers.h",
"chars": 29601,
"preview": "// SPDX-License-Identifier: MIT\n#pragma once\n\n#include <FEXCore/Utils/EnumUtils.h>\n\n#include <compare>\n#include <cstdint"
},
{
"path": "CodeEmitter/CodeEmitter/SVEOps.inl",
"chars": 229874,
"preview": "// SPDX-License-Identifier: MIT\n/* SVE instruction emitters\n * These contain instruction emitters for AArch64 SVE and SV"
},
{
"path": "CodeEmitter/CodeEmitter/ScalarOps.inl",
"chars": 67466,
"preview": "// SPDX-License-Identifier: MIT\n/* Scalar instruction emitters.\n *\n * These contain instruction emitters for scalar ASIM"
},
{
"path": "CodeEmitter/CodeEmitter/SystemOps.inl",
"chars": 4984,
"preview": "// SPDX-License-Identifier: MIT\n/* System instruction emitters.\n *\n * This is mostly a mashup of various instruction typ"
},
{
"path": "CodeEmitter/CodeEmitter/VixlUtils.inl",
"chars": 12699,
"preview": "// Collection of utilities from vixl.\n// Following is the vixl license.\n// Copyright 2015, VIXL authors\n// All rights re"
},
{
"path": "Data/AppConfig/CMakeLists.txt",
"chars": 848,
"preview": "file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS *.json)\nfile(GLOB GEN_CONFIG_SOURCES CONFIGURE_DEPENDS *.json.in)\n\n# Any appl"
},
{
"path": "Data/AppConfig/client.json",
"chars": 51,
"preview": "{\n \"Config\": {\n \"HideHypervisorBit\": \"1\"\n }\n}\n"
},
{
"path": "Data/AppConfig/steamwebhelper.json",
"chars": 121,
"preview": "{\n \"Comment\": \"Bypasses libGL's glX and instead sends GLX requests directly via xcb\",\n \"ThunksDB\": {\n \"GL\": 0\n }\n}"
},
{
"path": "Data/CI/FEXLinuxTestsThunks.json",
"chars": 48,
"preview": "{\n \"ThunksDB\": {\n \"fex_thunk_test\": 1\n }\n}\n"
},
{
"path": "Data/CI/GLThunks.json",
"chars": 36,
"preview": "{\n \"ThunksDB\": {\n \"GL\": 1\n }\n}\n"
},
{
"path": "Data/CI/VulkanThunks.json",
"chars": 40,
"preview": "{\n \"ThunksDB\": {\n \"Vulkan\": 1\n }\n}\n"
},
{
"path": "Data/CMake/FindZycore.cmake",
"chars": 582,
"preview": "# SPDX-License-Identifier: MIT\n\nif (CMAKE_CROSSCOMPILING)\n return()\nendif()\n\ninclude(FindPackageHandleStandardArgs)\n\n"
},
{
"path": "Data/CMake/FindZydis.cmake",
"chars": 570,
"preview": "# SPDX-License-Identifier: MIT\n\nif (CMAKE_CROSSCOMPILING)\n return()\nendif()\n\ninclude(FindPackageHandleStandardArgs)\n\n"
},
{
"path": "Data/CMake/Findxxhash.cmake",
"chars": 504,
"preview": "# SPDX-License-Identifier: MIT\n\ninclude(FindPackageHandleStandardArgs)\n\nfind_package(PkgConfig QUIET)\npkg_search_module("
},
{
"path": "Data/CMake/LinkerGC.cmake",
"chars": 624,
"preview": "# SPDX-License-Identifier: MIT\n\n# This applies some common linker options that reduce code size and linking time in Rele"
},
{
"path": "Data/CMake/cmake_uninstall.cmake.in",
"chars": 852,
"preview": "if(NOT EXISTS \"@CMAKE_BINARY_DIR@/install_manifest.txt\")\n message(FATAL_ERROR \"Cannot find install manifest: @CMAKE_BIN"
},
{
"path": "Data/CMake/toolchain_aarch64.cmake",
"chars": 1190,
"preview": "# This is a reference AArch64 cross compile script\n# Pass in to cmake when building:\n# eg: cmake --toolchain ../Data/CMa"
},
{
"path": "Data/CMake/toolchain_mingw.cmake",
"chars": 1091,
"preview": "set(MINGW_TRIPLE \"\" CACHE STRING \"MinGW compiler target architecture triple\")\n\nset(CMAKE_RC_COMPILER ${MINGW_TRIPLE}-win"
},
{
"path": "Data/CMake/toolchain_x86_32.cmake",
"chars": 725,
"preview": "option(ENABLE_CLANG_THUNKS \"Enable building thunks with clang\" FALSE)\n\nset(CMAKE_SYSTEM_PROCESSOR i686)\n\nif (ENABLE_CLAN"
},
{
"path": "Data/CMake/toolchain_x86_64.cmake",
"chars": 699,
"preview": "option(ENABLE_CLANG_THUNKS \"Enable building thunks with clang\" FALSE)\n\nset(CMAKE_SYSTEM_PROCESSOR x86_64)\n\nif (ENABLE_CL"
},
{
"path": "Data/CMake/version_to_variables.cmake",
"chars": 1059,
"preview": "# Extracts a version from the passed in version string in the form of \"<Major>.<Minor>.<Patch>\".\n# If a part of the vers"
},
{
"path": "Data/Dockerfile",
"chars": 924,
"preview": "# --- Stage 1: Builder ---\nFROM ubuntu:22.04 as builder\n\nRUN DEBIAN_FRONTEND=\"noninteractive\" apt-get update\nRUN DEBIAN_"
},
{
"path": "Data/ThunksDB.json",
"chars": 1297,
"preview": "{\n \"DB\": {\n \"GL\": {\n \"Library\" : \"libGL-guest.so\",\n \"Overlay\": [\n \"@PREFIX_LIB@/libGL.so\",\n "
},
{
"path": "Data/binfmts/CMakeLists.txt",
"chars": 847,
"preview": "function(GenBinFmt Name)\n # Get the filename only component\n get_filename_component(FMT_NAME ${Name} NAME_WE)\n\n # Con"
},
{
"path": "Data/binfmts/FEX-x86.conf.in",
"chars": 202,
"preview": ":FEX-x86:M:0:\\x7fELF\\x01\\x01\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02\\x00\\x03\\x00:\\xff\\xff\\xff\\xff\\xff\\xfe\\xfe\\x00\\x0"
},
{
"path": "Data/binfmts/FEX-x86.in",
"chars": 272,
"preview": "package fex\ninterpreter @CMAKE_INSTALL_PREFIX@/bin/FEX\nmagic \\x7fELF\\x01\\x01\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02"
},
{
"path": "Data/binfmts/FEX-x86_64.conf.in",
"chars": 205,
"preview": ":FEX-x86_64:M:0:\\x7fELF\\x02\\x01\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02\\x00\\x3e\\x00:\\xff\\xff\\xff\\xff\\xff\\xfe\\xfe\\x00"
},
{
"path": "Data/binfmts/FEX-x86_64.in",
"chars": 272,
"preview": "package fex\ninterpreter @CMAKE_INSTALL_PREFIX@/bin/FEX\nmagic \\x7fELF\\x02\\x01\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02"
},
{
"path": "Data/nix/FEXLinuxTests/shell.nix",
"chars": 1104,
"preview": "{ pkgs ? import <nixpkgs> { } }:\n\nlet\n pkgsCross32 = pkgs.pkgsCross.gnu32;\n pkgsCross64 = pkgs.pkgsCross.gnu64;\n\n gcc"
},
{
"path": "Data/nix/LibraryForwarding/shell.nix",
"chars": 2879,
"preview": "{ pkgs ? import <nixpkgs> { } }:\n\nlet\n pkgsCross32 = pkgs.pkgsCross.gnu32;\n pkgsCross64 = pkgs.pkgsCross.gnu64;\n\n dev"
},
{
"path": "Data/nix/WineOnArm/shell.nix",
"chars": 2076,
"preview": "{ pkgs ? import <nixpkgs> { } }:\n\nlet\n toolchain = pkgs.fetchzip {\n url = \"https://github.com/bylaws/llvm-mingw/rele"
},
{
"path": "Data/nix/cmake_configure_woa32.sh",
"chars": 552,
"preview": "#! /usr/bin/env nix-shell\n#! nix-shell -i bash WineOnArm/shell.nix\n\n# Helper script to configure CMake for building FEX "
},
{
"path": "Data/nix/cmake_configure_woa64.sh",
"chars": 553,
"preview": "#! /usr/bin/env nix-shell\n#! nix-shell -i bash WineOnArm/shell.nix\n\n# Helper script to configure CMake for building FEX "
},
{
"path": "Data/nix/cmake_enable_flt.sh",
"chars": 495,
"preview": "#! /usr/bin/env nix-shell\n#! nix-shell -i bash FEXLinuxTests/shell.nix\n\n# Helper script to configure CMake for building "
},
{
"path": "Data/nix/cmake_enable_libfwd.sh",
"chars": 740,
"preview": "# Helper script to configure CMake for library forwarding in FEX.\n# Nix is used to install and manage the required cross"
},
{
"path": "External/.clang-format",
"chars": 20,
"preview": "DisableFormat: true\n"
},
{
"path": "External/SoftFloat-3e/CMakeLists.txt",
"chars": 2569,
"preview": "\nadd_library(softfloat_3e STATIC\n # F80 support\n src/extF80_add.c\n src/extF80_div.c\n src/extF80_sub.c\n src/extF80_m"
},
{
"path": "External/SoftFloat-3e/include/SoftFloat-3e/opts-GCC.h",
"chars": 4090,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/include/SoftFloat-3e/platform.h",
"chars": 2341,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/include/SoftFloat-3e/primitiveTypes.h",
"chars": 3482,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/include/SoftFloat-3e/softfloat.h",
"chars": 17822,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/include/SoftFloat-3e/softfloat_types.h",
"chars": 5887,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_add.c",
"chars": 2869,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_div.c",
"chars": 8218,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_eq.c",
"chars": 2901,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_le.c",
"chars": 2937,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_lt.c",
"chars": 2962,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_mul.c",
"chars": 6189,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_rem.c",
"chars": 9073,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_roundToInt.c",
"chars": 5938,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_sqrt.c",
"chars": 7581,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_sub.c",
"chars": 3209,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_f128.c",
"chars": 2965,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_f32.c",
"chars": 4050,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_f64.c",
"chars": 4037,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_i32.c",
"chars": 3565,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_i64.c",
"chars": 3989,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/extF80_to_ui64.c",
"chars": 3626,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_add.c",
"chars": 3015,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_div.c",
"chars": 8027,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_eq.c",
"chars": 2801,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_eq_signaling.c",
"chars": 2632,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_isSignalingNaN.c",
"chars": 2122,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_le.c",
"chars": 2858,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_le_quiet.c",
"chars": 3043,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_lt.c",
"chars": 2854,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_lt_quiet.c",
"chars": 3039,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_mul.c",
"chars": 6332,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_mulAdd.c",
"chars": 2489,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_rem.c",
"chars": 7710,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_sqrt.c",
"chars": 8902,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_sub.c",
"chars": 3015,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_extF80.c",
"chars": 4527,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_f16.c",
"chars": 3970,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_f32.c",
"chars": 3985,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_f64.c",
"chars": 4122,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_i32.c",
"chars": 3602,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_i64.c",
"chars": 4212,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_ui32.c",
"chars": 3580,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f128_to_ui64.c",
"chars": 4220,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f32_to_extF80.c",
"chars": 4058,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f32_to_f128.c",
"chars": 3824,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/f64_to_extF80.c",
"chars": 4063,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/i32_to_extF80.c",
"chars": 2591,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/i32_to_f128.c",
"chars": 2501,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/internals.h",
"chars": 11592,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/primitives.h",
"chars": 53268,
"preview": "\r\n/*============================================================================\r\n\r\nThis C header file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_add128.c",
"chars": 2193,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_addMagsExtF80.c",
"chars": 5850,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_addMagsF128.c",
"chars": 5242,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_approxRecip32_1.c",
"chars": 2707,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_approxRecipSqrt32_1.c",
"chars": 3021,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_approxRecipSqrt_1Ks.c",
"chars": 2324,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_approxRecip_1Ks.c",
"chars": 2316,
"preview": "\r\n/*============================================================================\r\n\r\nThis C source file is part of the So"
},
{
"path": "External/SoftFloat-3e/src/s_commonNaNToExtF80UI.c",
"chars": 2543,
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"path": "External/SoftFloat-3e/src/s_shiftRightJam64Extra.c",
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"path": "External/SoftFloat-3e/src/s_shortShiftLeft128.c",
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"path": "External/SoftFloat-3e/src/ui64_to_extF80.c",
"chars": 2373,
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{
"path": "External/cephes/CMakeLists.txt",
"chars": 469,
"preview": "add_library(cephes_128bit STATIC\n src/128bit/Impl.cpp\n src/128bit/atanll.c\n src/128bit/constll.c\n src/128bit/exp2ll."
},
{
"path": "External/cephes/LICENSE",
"chars": 4754,
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"path": "External/cephes/include/cephes_128bit.h",
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{
"path": "External/cephes/src/128bit/Impl.cpp",
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},
{
"path": "External/cephes/src/128bit/exp2ll.c",
"chars": 3565,
"preview": "/*\t\t\t\t\t\t\texp2l.c\n *\n *\tBase 2 exponential function, 128-bit float128_t precision\n *\n *\n *\n * SYNOPSIS:\n *\n * float128_t "
},
{
"path": "External/cephes/src/128bit/floorll.c",
"chars": 8385,
"preview": "/* ceill()\n * "
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"path": "External/cephes/src/128bit/log2ll.c",
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"preview": "/*\t\t\t\t\t\t\tcephes_f128_log2l.c\n *\n *\tBase 2 logarithm, float128_t precision\n *\n *\n *\n * SYNOPSIS:\n *\n * float128_t x, y, c"
},
{
"path": "External/cephes/src/128bit/mconf.h",
"chars": 5677,
"preview": "/*\t\t\t\t\t\t\tmconf.h\n *\n *\tCommon include file for math routines\n *\n *\n *\n * SYNOPSIS:\n *\n * #include \"mconf.h\"\n *\n *\n *\n * "
},
{
"path": "External/cephes/src/128bit/mtherr.c",
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"preview": "/*\t\t\t\t\t\t\tmtherr.c\n *\n *\tLibrary common error handling routine\n *\n *\n *\n * SYNOPSIS:\n *\n * char *fctnam;\n * int code;\n * "
},
{
"path": "External/cephes/src/128bit/polevll.c",
"chars": 1832,
"preview": "/*\t\t\t\t\t\t\tpolevll.c\n *\t\t\t\t\t\t\tp1evll.c\n *\n *\tEvaluate polynomial\n *\n *\n *\n * SYNOPSIS:\n *\n * int N;\n * float128_t x, y, co"
},
{
"path": "External/cephes/src/128bit/sinll.c",
"chars": 9422,
"preview": "/*\t\t\t\t\t\t\tsinl.c\n *\n *\tCircular sine, float128_t precision\n *\n *\n *\n * SYNOPSIS:\n *\n * float128_t x, y, sinl();\n *\n * y ="
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{
"path": "External/cephes/src/128bit/tanll.c",
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},
{
"path": "External/code-format-helper/code-format-helper.py",
"chars": 10570,
"preview": "#!/usr/bin/env python3\n#\n# ====- code-format-helper, runs code formatters from the ci or in a hook --*- python -*--==#\n#"
},
{
"path": "External/code-format-helper/requirements_formatting.txt",
"chars": 36735,
"preview": "#\n# This file is autogenerated by pip-compile with Python 3.13\n# by the following command:\n#\n# pip-compile --generate"
},
{
"path": "External/code-format-helper/requirements_formatting.txt.in",
"chars": 153,
"preview": "black>=26.3.1\ndarker==2.1.1\nPyGithub==2.6.1\ncryptography>=46.0.5\nurllib3>=2.6.3\nrequests>=2.32.4\nidna>=3.7\ncertifi>=2024"
},
{
"path": "External/tiny-json/CMakeLists.txt",
"chars": 191,
"preview": "set(NAME tiny-json)\nset(SRCS tiny-json.c)\nadd_library(${NAME} STATIC ${SRCS})\n\ntarget_include_directories(${NAME} PUBLIC"
},
{
"path": "External/tiny-json/LICENSE",
"chars": 1068,
"preview": "MIT License\n\nCopyright (c) 2018 Rafa Garcia\n\nPermission is hereby granted, free of charge, to any person obtaining a cop"
},
{
"path": "External/tiny-json/tiny-json.c",
"chars": 22536,
"preview": "\n/*\n\n<https://github.com/rafagafe/tiny-json>\n \n Licensed under the MIT License <http://opensource.org/licenses/MIT>"
},
{
"path": "External/tiny-json/tiny-json.h",
"chars": 10884,
"preview": "\n/*\n\n<https://github.com/rafagafe/tiny-json>\n \n Licensed under the MIT License <http://opensource.org/licenses/MIT>"
},
{
"path": "FEXCore/CMakeLists.txt",
"chars": 1377,
"preview": "cmake_minimum_required(VERSION 3.14)\nset(PROJECT_NAME FEXCore)\nproject(${PROJECT_NAME}\n VERSION 0.01\n LANGUAGES CXX)\n\n"
},
{
"path": "FEXCore/LICENSE",
"chars": 1094,
"preview": "MIT License\n\nCopyright (c) 2019 Ryan Houdek <Sonicadvance1@gmail.com>\n\nPermission is hereby granted, free of charge, to "
},
{
"path": "FEXCore/Readme.md",
"chars": 1733,
"preview": "# FEXCore - Fast x86 Core emulation library\nThis is the core emulation library that is used for the FEX emulator project"
},
{
"path": "FEXCore/Scripts/config_generator.py",
"chars": 16260,
"preview": "import datetime\nimport json\nimport sys\n\ndef print_header():\n header = '''#ifndef OPT_BASE\n#define OPT_BASE(type, grou"
},
{
"path": "FEXCore/Scripts/json_ir_doc_generator.py",
"chars": 2275,
"preview": "import collections\nimport json\nimport sys\n\nOpClasses = collections.OrderedDict()\n\ndef get_ir_classes(ops, defines):\n "
},
{
"path": "FEXCore/Scripts/json_ir_generator.py",
"chars": 34265,
"preview": "#!/bin/python3\nimport json\nimport sys\nfrom dataclasses import dataclass, field\nimport textwrap\n\ndef ExitError(msg):\n "
},
{
"path": "FEXCore/Source/CMakeLists.txt",
"chars": 10725,
"preview": "set(MAN_DIR share/man CACHE PATH \"MAN_DIR\")\n\nset(FEXCORE_BASE_SRCS\n Interface/Config/Config.cpp\n Utils/Allocator.cpp\n "
},
{
"path": "FEXCore/Source/Common/BitSet.h",
"chars": 3400,
"preview": "// SPDX-License-Identifier: MIT\n#pragma once\n\n#include <FEXCore/Utils/Allocator.h>\n#include <FEXCore/Utils/MathUtils.h>\n"
},
{
"path": "FEXCore/Source/Common/JitSymbols.cpp",
"chars": 4622,
"preview": "// SPDX-License-Identifier: MIT\n#include <FEXCore/fextl/fmt.h>\n\n#include \"Common/JitSymbols.h\"\n\n#include <fcntl.h>\n#incl"
},
{
"path": "FEXCore/Source/Common/JitSymbols.h",
"chars": 2141,
"preview": "// SPDX-License-Identifier: MIT\n#pragma once\n#include <FEXCore/Utils/TypeDefines.h>\n\n#include <FEXCore/fextl/memory.h>\n\n"
}
]
// ... and 3043 more files (download for full content)
About this extraction
This page contains the full source code of the FEX-Emu/FEX GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 3243 files (18.8 MB), approximately 5.1M tokens, and a symbol index with 10497 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.