[ { "path": ".github/dependabot.yml", "content": "version: 2\nupdates:\n - package-ecosystem: github-actions\n directory: \"/\"\n schedule:\n interval: \"daily\"\n target-branch: main\n" }, { "path": ".github/workflows/build.yml", "content": "name: Build\n\non:\n push:\n branches: ['**']\n tags: ['[0-9]*']\n pull_request:\n workflow_dispatch:\n\njobs:\n build:\n runs-on: ubuntu-latest\n container: archlinux:latest\n permissions:\n contents: write\n steps:\n - name: Install distro deps\n run: pacman --noconfirm -Syu && pacman --needed --noconfirm -S base-devel python git vim nasm\n\n - name: Mark workspace safe for git\n run: git config --global --add safe.directory '*'\n\n - uses: actions/checkout@v6\n with:\n submodules: true\n fetch-depth: 0\n fetch-tags: true\n\n - name: make x86_64\n run: |\n make ARCH=x86_64\n mkdir -p bin\n cp bin-x86_64/csmwrap.efi bin/csmwrapx64.efi\n\n - name: make ia32\n run: |\n make ARCH=ia32\n mkdir -p bin\n cp bin-ia32/csmwrap.efi bin/csmwrapia32.efi\n\n - uses: actions/upload-artifact@v7\n with:\n name: csmwrap.efi\n path: bin/*.efi\n\n - name: Create draft release\n if: startsWith(github.ref, 'refs/tags/')\n uses: softprops/action-gh-release@v3\n with:\n draft: true\n fail_on_unmatched_files: true\n files: |\n bin/csmwrapx64.efi\n bin/csmwrapia32.efi\n" }, { "path": ".gitignore", "content": "/compile_commands.json\n/.cache\n/boot\n/edk2-ovmf\n/src/bins\n/bin-*\n/obj-*\n" }, { "path": ".gitmodules", "content": "[submodule \"freestnd-c-hdrs\"]\n\tpath = freestnd-c-hdrs\n\turl = https://github.com/osdev0/freestnd-c-hdrs-0bsd.git\n[submodule \"cc-runtime\"]\n\tpath = cc-runtime\n\turl = https://github.com/osdev0/cc-runtime.git\n[submodule \"picoefi\"]\n\tpath = picoefi\n\turl = https://github.com/PicoEFI/PicoEFI.git\n[submodule \"nanoprintf\"]\n\tpath = nanoprintf\n\turl = https://github.com/charlesnicholson/nanoprintf.git\n[submodule \"seabios\"]\n\tpath = seabios\n\turl = https://github.com/CSMWrap/seabios-csmwrap.git\n[submodule \"uACPI\"]\n\tpath = uACPI\n\turl = https://github.com/uACPI/uACPI.git\n[submodule \"flanterm\"]\n\tpath = flanterm\n\turl = https://github.com/Mintsuki/Flanterm.git\n" }, { "path": "GNUmakefile", "content": "# Nuke built-in rules.\n.SUFFIXES:\n\n# This is the name that our final executable will have.\n# Change as needed.\noverride OUTPUT := csmwrap\n\n# Target architecture to build for. Default to x86_64.\nARCH := x86_64\n\n# Install prefix; /usr/local is a good, standard default pick.\nPREFIX := /usr/local\n\n# Check if the architecture is supported.\nifeq ($(filter $(ARCH),ia32 x86_64),)\n $(error Architecture $(ARCH) not supported)\nendif\n\n# Default user QEMU flags. These are appended to the QEMU command calls.\nQEMUFLAGS := -m 2G -smp 2\n\n# User controllable host C compiler.\nHOST_CC := cc\n\n# User controllable toolchain and toolchain prefix.\nTOOLCHAIN :=\nTOOLCHAIN_PREFIX :=\nifneq ($(TOOLCHAIN),)\n ifeq ($(TOOLCHAIN_PREFIX),)\n TOOLCHAIN_PREFIX := $(TOOLCHAIN)-\n endif\nendif\n\n# User controllable C compiler command.\nifneq ($(TOOLCHAIN_PREFIX),)\n CC := $(TOOLCHAIN_PREFIX)gcc\nelse\n CC := cc\nendif\n\n# User controllable linker command.\nLD := $(TOOLCHAIN_PREFIX)ld\n\n# User controllable objcopy command.\nOBJCOPY := $(TOOLCHAIN_PREFIX)objcopy\n\n# User controllable objdump command.\nOBJDUMP := $(TOOLCHAIN_PREFIX)objdump\n\n# User controllable strip command.\nSTRIP := $(TOOLCHAIN_PREFIX)strip\n\n# Defaults overrides for variables if using \"llvm\" as toolchain.\nifeq ($(TOOLCHAIN),llvm)\n CC := clang\n LD := ld.lld\nendif\n\n# User controllable C flags.\nCFLAGS := -g -O2 -pipe\n\n# User controllable C preprocessor flags. We set none by default.\nCPPFLAGS :=\n\n# User controllable nasm flags.\nNASMFLAGS := -g\n\n# User controllable linker flags. We set none by default.\nLDFLAGS :=\n\n# User controllable version string.\nBUILD_VERSION := $(shell git describe --tags --always 2>/dev/null || echo \"Unknown\")\n\n# Check if CC is Clang.\noverride CC_IS_CLANG := $(shell ! $(CC) --version 2>/dev/null | grep -q '^Target: '; echo $$?)\n\n# Save user CFLAGS, CPPFLAGS, and LDFLAGS before we append internal flags.\noverride USER_CFLAGS := $(CFLAGS)\noverride USER_CPPFLAGS := $(CPPFLAGS)\noverride USER_LDFLAGS := $(LDFLAGS)\n\noverride define SEABIOS_CALL\n\t$(MAKE) -C seabios $(1) \\\n\t\tHOSTCC=\"$(HOST_CC)\" \\\n\t\tCC=\"$(CC)\" \\\n\t\tLD=\"$(LD)\" \\\n\t\tOBJCOPY=\"$(OBJCOPY)\" \\\n\t\tOBJDUMP=\"$(OBJDUMP)\" \\\n\t\tSTRIP=\"$(STRIP)\" \\\n\t\tCFLAGS=\"$(USER_CFLAGS)\" \\\n\t\tCPPFLAGS=\"$(USER_CPPFLAGS)\" \\\n\t\tLDFLAGS=\"$(USER_LDFLAGS)\" \\\n\t\tEXTRAVERSION=\\\"$(SEABIOS_EXTRAVERSION)\\\"\nendef\n\n# Internal C flags that should not be changed by the user.\noverride CFLAGS += \\\n -Wall \\\n -Wextra \\\n -std=gnu11 \\\n -nostdinc \\\n -ffreestanding \\\n -fno-stack-protector \\\n -fno-stack-check \\\n -fno-delete-null-pointer-checks \\\n -fshort-wchar \\\n -fno-lto \\\n -fPIE \\\n -ffunction-sections \\\n -fdata-sections\n\n# Internal C preprocessor flags that should not be changed by the user.\noverride CPPFLAGS := \\\n -I src \\\n -I picoefi/inc \\\n -I flanterm/src \\\n -I uACPI/include \\\n -DUACPI_OVERRIDE_CONFIG \\\n -DBUILD_VERSION=\\\"$(BUILD_VERSION)\\\" \\\n -isystem freestnd-c-hdrs/include \\\n $(CPPFLAGS) \\\n -MMD \\\n -MP\n\nobj-$(ARCH)/flanterm/src/flanterm_backends/fb.c.o: override CPPFLAGS += \\\n\t-DFLANTERM_FB_DISABLE_BUMP_ALLOC\n\n# Internal nasm flags that should not be changed by the user.\noverride NASMFLAGS := \\\n $(patsubst -g,-g -F dwarf,$(NASMFLAGS)) \\\n -Wall\n\n# Architecture specific internal flags.\nifeq ($(ARCH),ia32)\n ifeq ($(CC_IS_CLANG),1)\n override CC += \\\n -target i686-unknown-none-elf\n endif\n override CFLAGS += \\\n -m32 \\\n -march=i686 \\\n -mabi=sysv \\\n -mno-80387 \\\n -mno-mmx \\\n -malign-double\n override LDFLAGS += \\\n -m elf_i386\n override NASMFLAGS := \\\n -f elf32 \\\n $(NASMFLAGS)\nendif\nifeq ($(ARCH),x86_64)\n ifeq ($(CC_IS_CLANG),1)\n override CC += \\\n -target x86_64-unknown-none-elf\n endif\n override CFLAGS += \\\n -m64 \\\n -march=x86-64 \\\n -mabi=sysv \\\n -mno-80387 \\\n -mno-mmx \\\n -mno-sse \\\n -mno-sse2 \\\n -mno-red-zone\n override LDFLAGS += \\\n -m elf_x86_64\n override NASMFLAGS := \\\n -f elf64 \\\n $(NASMFLAGS)\nendif\n\n# Internal linker flags that should not be changed by the user.\noverride LDFLAGS += \\\n -nostdlib \\\n -pie \\\n -z text \\\n -z max-page-size=0x1000 \\\n --gc-sections \\\n -T picoefi/$(ARCH)/link_script.lds\n\n# Use \"find\" to glob all *.c, *.S, and *.asm files in the tree\n# (except the src/arch/* directories, as those are gonna be added\n# in the next step).\noverride SRCFILES := $(shell find -L src cc-runtime/src picoefi/$(ARCH) flanterm/src uACPI/source -type f -not -path 'src/arch/*' 2>/dev/null | LC_ALL=C sort)\n# Add architecture specific files, if they exist.\noverride SRCFILES += $(shell find -L src/arch/$(ARCH) -type f 2>/dev/null | LC_ALL=C sort)\n# Obtain the object and header dependencies file names.\noverride CFILES := $(filter %.c,$(SRCFILES))\noverride ASFILES := $(filter %.S,$(SRCFILES))\nifneq ($(filter $(ARCH),ia32 x86_64),)\noverride NASMFILES := $(filter %.asm,$(SRCFILES))\nendif\noverride OBJ := $(addprefix obj-$(ARCH)/,$(CFILES:.c=.c.o) $(ASFILES:.S=.S.o))\nifneq ($(filter $(ARCH),ia32 x86_64),)\noverride OBJ += $(addprefix obj-$(ARCH)/,$(NASMFILES:.asm=.asm.o))\nendif\noverride HEADER_DEPS := $(addprefix obj-$(ARCH)/,$(CFILES:.c=.c.d) $(ASFILES:.S=.S.d))\n\n# Default target. This must come first, before header dependencies.\n.PHONY: all\nall:\n\t$(MAKE) seabios\n\t$(MAKE) bin-$(ARCH)/$(OUTPUT).efi\n\n# Include header dependencies.\n-include $(HEADER_DEPS)\n\nobj-$(ARCH)/src/csmwrap.c.o: src/bins/Csm16.h\n\nobj-$(ARCH)/src/video.c.o: src/bins/vgabios.h\n\nobj-$(ARCH)/src/printf.c.o: override CPPFLAGS += \\\n -I nanoprintf\n\n# Rule to convert the final ELF executable to a .EFI PE executable.\nbin-$(ARCH)/$(OUTPUT).efi: bin-$(ARCH)/$(OUTPUT) GNUmakefile\n\tmkdir -p \"$(dir $@)\"\n\t$(OBJCOPY) -O binary $< $@\n\tdd if=/dev/zero of=$@ bs=4096 count=0 seek=$$(( ($$(wc -c < $@) + 4095) / 4096 )) 2>/dev/null\n\n# Link rules for the final executable.\nbin-$(ARCH)/$(OUTPUT): GNUmakefile picoefi/$(ARCH)/link_script.lds $(OBJ)\n\tmkdir -p \"$(dir $@)\"\n\t$(LD) $(LDFLAGS) $(OBJ) -o $@\n\n# Compilation rules for *.c files.\nobj-$(ARCH)/%.c.o: %.c GNUmakefile\n\tmkdir -p \"$(dir $@)\"\n\t$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@\n\n# Compilation rules for *.S files.\nobj-$(ARCH)/%.S.o: %.S GNUmakefile\n\tmkdir -p \"$(dir $@)\"\n\t$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@\n\nifneq ($(filter $(ARCH),ia32 x86_64),)\n# Compilation rules for *.asm (nasm) files.\nobj-$(ARCH)/%.asm.o: %.asm GNUmakefile\n\tmkdir -p \"$(dir $@)\"\n\tnasm $(NASMFLAGS) $< -o $@\nendif\n\n# Rules to download the UEFI firmware per architecture for testing.\nedk2-ovmf:\n\tcurl -L https://github.com/osdev0/edk2-ovmf-nightly/releases/latest/download/edk2-ovmf.tar.gz | gunzip | tar -xf -\n\n# Rules for running our executable in QEMU.\n.PHONY: run\nrun: all edk2-ovmf\n\tmkdir -p boot/EFI/BOOT\nifeq ($(ARCH),ia32)\n\tcp bin-$(ARCH)/$(OUTPUT).efi boot/EFI/BOOT/BOOTIA32.EFI\n\tqemu-system-i386 \\\n\t\t-M q35 \\\n\t\t-drive if=pflash,unit=0,format=raw,file=edk2-ovmf/ovmf-code-$(ARCH).fd,readonly=on \\\n\t\t-drive file=fat:rw:boot \\\n\t\t$(QEMUFLAGS)\nendif\nifeq ($(ARCH),x86_64)\n\tcp bin-$(ARCH)/$(OUTPUT).efi boot/EFI/BOOT/BOOTX64.EFI\n\tqemu-system-x86_64 \\\n\t\t-M q35 \\\n\t\t-drive if=pflash,unit=0,format=raw,file=edk2-ovmf/ovmf-code-$(ARCH).fd,readonly=on \\\n\t\t-drive file=fat:rw:boot \\\n\t\t$(QEMUFLAGS)\nendif\n\trm -rf boot\n\n# Remove object files and the final executable.\n.PHONY: clean\nclean: seabios/.config\n\t$(call SEABIOS_CALL,clean)\n\trm -rf bin-$(ARCH) obj-$(ARCH)\n\n# Remove everything built and generated including downloaded dependencies.\n.PHONY: distclean\ndistclean: seabios/.config\n\t$(call SEABIOS_CALL,distclean)\n\trm -rf src/bins\n\trm -rf bin-* obj-* .cache compile_commands.json edk2-ovmf\n\n# Install the final built executable to its final on-root location.\n.PHONY: install\ninstall: all\n\tinstall -d \"$(DESTDIR)$(PREFIX)/share/$(OUTPUT)\"\n\tinstall -m 644 bin-$(ARCH)/$(OUTPUT).efi \"$(DESTDIR)$(PREFIX)/share/$(OUTPUT)/$(OUTPUT)-$(ARCH).efi\"\n\n# Try to undo whatever the \"install\" target did.\n.PHONY: uninstall\nuninstall:\n\trm -f \"$(DESTDIR)$(PREFIX)/share/$(OUTPUT)/$(OUTPUT)-$(ARCH).efi\"\n\t-rmdir \"$(DESTDIR)$(PREFIX)/share/$(OUTPUT)\"\n\n# SeaBIOS build targets.\nSEABIOS_EXTRAVERSION := -CSMWrap-$(BUILD_VERSION)\n.PHONY: seabios\nseabios: seabios/.config\n\t$(call SEABIOS_CALL,)\n\nsrc/bins/Csm16.h: GNUmakefile seabios/out/Csm16.bin\n\tmkdir -p src/bins\n\tcd seabios/out && xxd -i Csm16.bin >../../src/bins/Csm16.h\n\nsrc/bins/vgabios.h: GNUmakefile seabios/out/vgabios.bin\n\tmkdir -p src/bins\n\tcd seabios/out && xxd -i vgabios.bin >../../src/bins/vgabios.h\n\nseabios/.config: GNUmakefile seabios-config\n\tcp seabios-config seabios/.config\n\t$(call SEABIOS_CALL,olddefconfig)\n" }, { "path": "LICENSE", "content": " GNU LESSER GENERAL PUBLIC LICENSE\n Version 2.1, February 1999\n\n Copyright (C) 1991, 1999 Free Software Foundation, Inc.\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n[This is the first released version of the Lesser GPL. It also counts\n as the successor of the GNU Library Public License, version 2, hence\n the version number 2.1.]\n\n Preamble\n\n The licenses for most software are designed to take away your\nfreedom to share and change it. By contrast, the GNU General Public\nLicenses are intended to guarantee your freedom to share and change\nfree software--to make sure the software is free for all its users.\n\n This license, the Lesser General Public License, applies to some\nspecially designated software packages--typically libraries--of the\nFree Software Foundation and other authors who decide to use it. You\ncan use it too, but we suggest you first think carefully about whether\nthis license or the ordinary General Public License is the better\nstrategy to use in any particular case, based on the explanations below.\n\n When we speak of free software, we are referring to freedom of use,\nnot price. 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CSMWrap

\n\n

\n \"Build\n \"Discord\"\n

\n\n

\n \"CSMWrap\n

\n\nCSMWrap is an EFI application designed to be a drop-in solution to enable legacy BIOS booting on modern UEFI-only (class 3) systems.\nIt achieves this by wrapping a Compatibility Support Module (CSM) build of the [SeaBIOS project](https://www.seabios.org/)\nas an out-of-firmware EFI application, effectively creating a compatibility layer for traditional PC BIOS operation.\n\nLogo art by [conkkerxd](https://github.com/conkkerxd).\n\n## Executive Summary\n\nThe idea is to drop the 64-bit or 32-bit version of CSMWrap (depending on the hardware, dropping both also works) into a `/EFI/BOOT/`\ndirectory on a FAT (12, 16, or 32) partition on the medium containing the legacy BIOS OS. UEFI firmware will pick this up and show the\nmedium as a bootable device. Ideally, that's all that would be needed.\n\n1. **Download:** Get the latest `csmwrap.efi` from the [Releases page](https://github.com/CSMWrap/CSMWrap/releases).\n2. **Deploy:** Copy `csmwrap.efi` to a FAT-formatted partition, typically as `/EFI/BOOT/BOOTX64.EFI` (for 64-bit)\n or `/EFI/BOOT/BOOTIA32.EFI` (for 32-bit) (the hardcoded path is needed so that the firmware picks it up automatically).\n3. **Boot:** Select the UEFI boot entry for the drive onto which CSMWrap was deployed.\n\nIt is highly recommended that the partition table used is MBR (MS-DOS partition table), as UEFI firmwares are perfectly capable of\nbooting off of this format, and because it is the most compatible with most legacy OSes one may want to boot.\n\n## Additional Prerequisites\n\n### Secure Boot\n\nSecure boot should be disabled unless one wants to manually sign the CSMWrap EFI application, which is possible, but beyond the\nscope of this README.\n\n### Firmware Settings\n\nCSMWrap is designed to be as drop-in as possible, without requiring changes to firmware for settings that may not even be exposed\n(depending on the firmware), or that might conflict with other UEFI OSes being multi-booted on the system. That said, if at all\npossible, disabling these settings is highly recommended for best legacy OS compatibility:\n\n1. **X2APIC**\n\nAdditional settings to try to disable if things still do not work (ideally this should *not* be necessary, please report an issue\nif you need this on your hardware!):\n\n1. **Above 4G Decoding**\n2. **Resizable BAR/Smart Access Memory**\n\n### Video Card Considerations\n\nCSMWrap also wraps the \"SeaVGABIOS\" module of SeaBIOS for providing a bare bones implementation of a legacy Video BIOS. That said,\nSeaVGABIOS is far from ideal, and many, **many** things requiring more direct access to legacy video modes won't work properly\n(e.g. pretty much all MS-DOS games, MS-DOS Editor, etc.). More modern OSes using the VESA BIOS extensions (VBE) standard only\n(e.g. more modern Windows NT, Linux, etc.) should still work fine, though.\n\nTherefore it is **highly recommended**, if possible, to install a legacy-capable video card. If one is present, its Video BIOS\nwill be used instead of SeaVGABIOS, providing a much better, pretty much native-like, experience.\n\n## Configuration\n\nCSMWrap supports an optional INI-style configuration file. Place a file named `csmwrap.ini` in the same directory as the CSMWrap\nEFI executable (e.g. `/EFI/BOOT/csmwrap.ini`). If the file is absent, sensible defaults are used.\n\n### Options\n\n| Key | Type | Default | Description |\n|-----|------|---------|-------------|\n| `serial` | bool | `false` | Enable serial debug output |\n| `serial_port` | hex/int | `0x3f8` | Serial I/O port address (COM1=`0x3f8`, COM2=`0x2f8`, COM3=`0x3e8`, COM4=`0x2e8`) |\n| `serial_baud` | int | `115200` | Serial baud rate |\n| `vgabios` | string | *(empty)* | Path to a custom VBIOS file on the ESP (e.g. `\\EFI\\CSMWrap\\vgabios.bin`). When empty, the card's built-in OpROM is used, and, failing that, SeaVGABIOS is used |\n| `iommu_disable` | bool | `true` | Disable IOMMUs (Intel VT-d / AMD-Vi) before legacy boot |\n| `verbose` | bool | `false` | Show debug output on screen via Flanterm |\n| `vga` | PCI address | *(empty)* | PCI address of the VGA card to use (e.g. `00:02.0`). Format: `BB:DD.F` (hex). When empty, the first available card is used |\n| `system_thread` | int/hex | *(auto)* | APIC ID of the logical CPU to reserve as the CSMWrap system thread (see [the FAQs](#frequently-asked-questions)). Must be an enabled AP (not the BSP) and have an APIC ID below `0xFF`/`255`. When empty, CSMWrap auto-picks the highest-ID AP below `0xFF`/`255`. The selected CPU is hidden from the OS in both the MADT and the MP table |\n| `cpu_allowlist` | int/hex list | *(unset)* | Comma-separated list of APIC IDs of logical CPUs that should be exposed to the OS in the MADT and the MP table. Each entry is either a single ID or an inclusive range `N-M` (e.g. `0,2-4,7`). An empty value (`cpu_allowlist =`) is itself a setting and means \"hide every AP\" (only the BSP stays visible). The BSP is always exposed regardless. The system thread is always hidden regardless. Mutually exclusive with `cpu_blocklist` |\n| `cpu_blocklist` | int/hex list | *(unset)* | Comma-separated list of APIC IDs of logical CPUs that should be hidden from the OS in the MADT and the MP table. Each entry is either a single ID or an inclusive range `N-M` (e.g. `5-7`). An empty value (`cpu_blocklist =`) is a no-op for visibility but still claims the slot, so `cpu_allowlist` cannot also be set. The BSP is always exposed regardless. The system thread is always hidden regardless. Mutually exclusive with `cpu_allowlist` |\n\nBoolean values accept `true`/`yes`/`1` and `false`/`no`/`0` (case-insensitive). Comments start with `;` or `#`.\n\n### Example\n\n```ini\n; CSMWrap configuration\nserial = true\nserial_port = 0x3f8\nserial_baud = 115200\nvgabios = \\EFI\\CSMWrap\\vgabios.bin\niommu_disable = true\n\n; Pin the system thread to APIC ID 7 and hide APIC IDs 4 through 6 from the OS.\nsystem_thread = 7\ncpu_blocklist = 4-6\n```\n\n## Frequently Asked Questions\n\n### Is this an emulator?\n\nNo! At least not in the sense of it being a full-screened emulator window. Running a legacy OS with CSMWrap means that it is *natively*\nrunning on the system. CSMWrap attempts to recreate, natively, and as closely as possible, a legacy BIOS PC environment on modern\nUEFI class 3 systems.\n\n### I booted a multi-core capable OS and I am missing a logical processor (thread), what gives?\n\nThis is expected. CSMWrap reserves 1 logical processor for \"system\" use due to the limitations of running out-of-firmware and not being able to\nuse [SMM (System Management Mode)](https://en.wikipedia.org/wiki/System_Management_Mode).\n\nTherefore, this means that CSMWrap **does not support running on systems with only 1 logical processor (i.e. only 1 core and no SMT/hyperthreading)**.\nThat said, most systems that CSMWrap targets (i.e. modern UEFI class 3 systems) will definitely have way more than a single logical processor,\nso this is mostly a non-issue.\n\n### Does CSMWrap have any advantages over native CSM?\n\nYes! Native CSM firmware is often riddled with issues and hardly tested against legacy OSes anymore. CSMWrap ships a reliable, free, and open-source\nlegacy BIOS implementation - SeaBIOS - and it is tested against legacy OSes. Issues affecting modern, commonly shipped CSM implementations do\nnot affect CSMWrap, like for example:\n\n- Dirty control register values at handoff. (This is something that [cregfix](https://github.com/mintsuki/cregfix) was created to work around).\n- Legacy BIOS routines failing to reliably run when called from Virtual 8086 Mode. EMM386, Windows 3.x under 386 enhanced mode, and more, are affected\n by this issue and it results in crashes. The reason for this is a bit technical for this README file, but CSMWrap is not affected.\n\nAnd when it comes to improvements that are not necessarily bugs in CSM implementations, CSMWrap, amongst other things:\n\n- Generates MP tables for legacy OSes that support the legacy Intel MultiProcessor Specification standard but not ACPI.\n- Allows one to select a non-primary video card for VGA output which native CSM implementations do not allow. This is useful for\n multi-booting modern and legacy OSes.\n\n## Contributing\n\nContributions are welcome! Whether it's reporting bugs, suggesting features, improving documentation, or submitting code changes, your help is appreciated.\n\nAdditionally, one can join our [Discord server](https://discord.gg/3CCgJpzNXH) for any project-related discussion, or to otherwise chat with likeminded\npeople.\n\n## Credits & Acknowledgements\n\n* The **[SeaBIOS project](https://www.seabios.org/)** for their CSM and VBIOS code.\n* **[PicoEFI](https://github.com/PicoEFI/PicoEFI)** for the EFI C runtime, build system, and headers.\n* **[EDK2 (TianoCore)](https://github.com/tianocore/edk2)** for UEFI specifications and some code snippets.\n* **[uACPI](https://github.com/uACPI/uACPI)** for ACPI table handling.\n* **@CanonKong** for test feedback and general knowledge.\n* All contributors and testers from the community!\n" }, { "path": "seabios-config", "content": "CONFIG_CSM=y\n# CONFIG_FLASH_FLOPPY is not set\n# CONFIG_VGAHOOKS is not set\n# CONFIG_TCGBIOS is not set\nCONFIG_VGA_COREBOOT=y\n" }, { "path": "src/acpi.c", "content": "#include \n#include \n#include \n#include \n#include \n#include \"csmwrap.h\"\n\n#include \n#include \n#include \n\nuintptr_t g_rsdp = 0;\n\nstatic inline const char *uacpi_log_level_to_string(uacpi_log_level lvl) {\n switch (lvl) {\n case UACPI_LOG_DEBUG:\n return \"DEBUG\";\n case UACPI_LOG_TRACE:\n return \"TRACE\";\n case UACPI_LOG_INFO:\n return \"INFO\";\n case UACPI_LOG_WARN:\n return \"WARN\";\n case UACPI_LOG_ERROR:\n default:\n return \"ERROR\";\n }\n}\n\nvoid uacpi_kernel_log(enum uacpi_log_level lvl, const char *text) {\n printf(\"[uACPI][%s] %s\", uacpi_log_level_to_string(lvl), text);\n}\n\nvoid *uacpi_kernel_map(uacpi_phys_addr addr, EFI_UNUSED uacpi_size len) {\n return (void*)((uintptr_t)addr);\n}\n\nvoid uacpi_kernel_unmap(EFI_UNUSED void *ptr, EFI_UNUSED uacpi_size len) {\n}\n\nuacpi_status uacpi_kernel_pci_device_open(uacpi_pci_address address, uacpi_handle *out_handle) {\n void *handle;\n if (gBS->AllocatePool(EfiLoaderData, sizeof(struct pci_address), &handle) != EFI_SUCCESS) {\n return UACPI_STATUS_OUT_OF_MEMORY;\n }\n\n struct pci_address *pci_address = (struct pci_address *)handle;\n pci_address->segment = address.segment;\n pci_address->bus = address.bus;\n pci_address->slot = address.device;\n pci_address->function = address.function;\n\n *out_handle = handle;\n return UACPI_STATUS_OK;\n}\n\nvoid uacpi_kernel_pci_device_close(uacpi_handle handle) {\n gBS->FreePool(handle);\n}\n\nuacpi_status uacpi_kernel_pci_read8(uacpi_handle device, uacpi_size offset, uacpi_u8 *value) {\n *value = pci_read8((struct pci_address *)device, offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_pci_read16(uacpi_handle device, uacpi_size offset, uacpi_u16 *value) {\n *value = pci_read16((struct pci_address *)device, offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_pci_read32(uacpi_handle device, uacpi_size offset, uacpi_u32 *value) {\n *value = pci_read32((struct pci_address *)device, offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_pci_write8(uacpi_handle device, uacpi_size offset, uacpi_u8 value) {\n pci_write8((struct pci_address *)device, offset, value);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_pci_write16(uacpi_handle device, uacpi_size offset, uacpi_u16 value) {\n pci_write16((struct pci_address *)device, offset, value);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_pci_write32(uacpi_handle device, uacpi_size offset, uacpi_u32 value) {\n pci_write32((struct pci_address *)device, offset, value);\n return UACPI_STATUS_OK;\n}\n\nstruct mapped_io {\n uacpi_io_addr base;\n uacpi_size len;\n};\n\nuacpi_status uacpi_kernel_io_map(uacpi_io_addr base, uacpi_size len, uacpi_handle *out_handle) {\n void *handle;\n if (gBS->AllocatePool(EfiLoaderData, sizeof(struct mapped_io), &handle) != EFI_SUCCESS) {\n return UACPI_STATUS_OUT_OF_MEMORY;\n }\n\n struct mapped_io *io = (struct mapped_io *)handle;\n io->base = base;\n io->len = len;\n\n *out_handle = handle;\n return UACPI_STATUS_OK;\n}\n\nvoid uacpi_kernel_io_unmap(uacpi_handle handle) {\n gBS->FreePool(handle);\n}\n\nuacpi_status uacpi_kernel_io_read8(uacpi_handle handle, uacpi_size offset, uacpi_u8 *out_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n *out_value = inb(io->base + offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_io_read16(uacpi_handle handle, uacpi_size offset, uacpi_u16 *out_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n *out_value = inw(io->base + offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_io_read32(uacpi_handle handle, uacpi_size offset, uacpi_u32 *out_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n *out_value = inl(io->base + offset);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_io_write8(uacpi_handle handle, uacpi_size offset, uacpi_u8 in_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n outb(io->base + offset, in_value);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_io_write16(uacpi_handle handle, uacpi_size offset, uacpi_u16 in_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n outw(io->base + offset, in_value);\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_io_write32(uacpi_handle handle, uacpi_size offset, uacpi_u32 in_value) {\n struct mapped_io *io = (struct mapped_io *)handle;\n if (offset >= io->len) {\n return UACPI_STATUS_INVALID_ARGUMENT;\n }\n\n outl(io->base + offset, in_value);\n return UACPI_STATUS_OK;\n}\n\nuacpi_interrupt_state uacpi_kernel_disable_interrupts(void) {\n uacpi_interrupt_state flags;\n asm volatile (\"pushf; pop %0; cli\" : \"=rm\"(flags) :: \"memory\");\n return flags;\n}\n\nvoid uacpi_kernel_restore_interrupts(uacpi_interrupt_state state) {\n asm volatile (\"push %0; popf\" :: \"rm\"(state) : \"memory\", \"cc\");\n}\n\nuacpi_handle uacpi_kernel_create_spinlock(void) {\n void *handle;\n if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {\n return NULL;\n }\n\n return handle;\n}\n\nvoid uacpi_kernel_free_spinlock(uacpi_handle handle) {\n gBS->FreePool(handle);\n}\n\nuacpi_cpu_flags uacpi_kernel_lock_spinlock(uacpi_handle handle) {\n (void)handle;\n return 0;\n}\n\nvoid uacpi_kernel_unlock_spinlock(uacpi_handle handle, uacpi_cpu_flags cpu_flags) {\n (void)handle;\n (void)cpu_flags;\n}\n\nuacpi_handle uacpi_kernel_create_event(void) {\n void *handle;\n if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {\n return NULL;\n }\n\n return handle;\n}\n\nvoid uacpi_kernel_free_event(uacpi_handle handle) {\n gBS->FreePool(handle);\n}\n\nuacpi_bool uacpi_kernel_wait_for_event(uacpi_handle handle, uacpi_u16 timeout) {\n (void)handle;\n (void)timeout;\n return UACPI_TRUE;\n}\n\nvoid uacpi_kernel_signal_event(uacpi_handle handle) {\n (void)handle;\n}\n\nvoid uacpi_kernel_reset_event(uacpi_handle handle) {\n (void)handle;\n}\n\nuacpi_u64 uacpi_kernel_get_nanoseconds_since_boot(void) {\n return get_nanoseconds_since_boot();\n}\n\nvoid uacpi_kernel_stall(uacpi_u8 usec) {\n gBS->Stall(usec);\n}\n\nvoid uacpi_kernel_sleep(uacpi_u64 msec) {\n gBS->Stall(msec * 1000);\n}\n\nuacpi_thread_id uacpi_kernel_get_thread_id(void) {\n return (uacpi_thread_id)1;\n}\n\nuacpi_status uacpi_kernel_handle_firmware_request(uacpi_firmware_request *request) {\n (void)request;\n return UACPI_STATUS_UNIMPLEMENTED;\n}\n\nuacpi_status uacpi_kernel_install_interrupt_handler(\n uacpi_u32 irq, uacpi_interrupt_handler handler, uacpi_handle ctx,\n uacpi_handle *out_irq_handle) {\n (void)irq;\n (void)handler;\n (void)ctx;\n (void)out_irq_handle;\n return UACPI_STATUS_OK;\n}\n\nuacpi_status uacpi_kernel_uninstall_interrupt_handler(uacpi_interrupt_handler handler, uacpi_handle irq_handle) {\n (void)handler;\n (void)irq_handle;\n return UACPI_STATUS_UNIMPLEMENTED;\n}\n\nuacpi_status uacpi_kernel_schedule_work(uacpi_work_type work_type, uacpi_work_handler handler, uacpi_handle ctx) {\n (void)work_type;\n (void)handler;\n (void)ctx;\n return UACPI_STATUS_UNIMPLEMENTED;\n}\n\nuacpi_status uacpi_kernel_wait_for_work_completion(void) {\n return UACPI_STATUS_UNIMPLEMENTED;\n}\n\nvoid *uacpi_kernel_alloc(uacpi_size size) {\n void *result;\n if (gBS->AllocatePool(EfiLoaderData, size, &result) != EFI_SUCCESS) {\n return NULL;\n }\n\n return result;\n}\n\nvoid uacpi_kernel_free(void *mem) {\n if (mem != NULL) {\n gBS->FreePool(mem);\n }\n}\n\nuacpi_handle uacpi_kernel_create_mutex(void) {\n void *handle;\n if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {\n return NULL;\n }\n\n return handle;\n}\n\nvoid uacpi_kernel_free_mutex(uacpi_handle handle) {\n gBS->FreePool(handle);\n}\n\nuacpi_status uacpi_kernel_acquire_mutex(uacpi_handle handle, uacpi_u16 timeout) {\n (void)handle;\n (void)timeout;\n return UACPI_STATUS_OK;\n}\n\nvoid uacpi_kernel_release_mutex(uacpi_handle handle) {\n (void)handle;\n}\n\nuacpi_status uacpi_kernel_get_rsdp(uacpi_phys_addr *rsdp) {\n if (!g_rsdp) {\n return UACPI_STATUS_NOT_FOUND;\n }\n\n *rsdp = g_rsdp;\n return UACPI_STATUS_OK;\n}\n\nstatic void *early_table_buffer;\n\nbool acpi_init(struct csmwrap_priv *priv) {\n UINTN i;\n EFI_GUID acpiGuid = ACPI_TABLE_GUID;\n EFI_GUID acpi2Guid = ACPI_20_TABLE_GUID;\n void *table_target = priv->csm_bin + (priv->csm_efi_table->AcpiRsdPtrPointer - priv->csm_bin_base);\n\n for (i = 0; i < gST->NumberOfTableEntries; i++) {\n EFI_CONFIGURATION_TABLE *table;\n table = gST->ConfigurationTable + i;\n\n if (!efi_guidcmp(table->VendorGuid, acpi2Guid)) {\n printf(\"Found ACPI 2.0 RSDT at %x, copied to %x\\n\", (uintptr_t)table->VendorTable, (uintptr_t)table_target);\n memcpy(table_target, table->VendorTable, sizeof(EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER));\n g_rsdp = (uintptr_t)table->VendorTable;\n break;\n }\n }\n\n if (g_rsdp == 0) {\n for (i = 0; i < gST->NumberOfTableEntries; i++) {\n EFI_CONFIGURATION_TABLE *table;\n table = gST->ConfigurationTable + i;\n\n if (!efi_guidcmp(table->VendorGuid, acpiGuid)) {\n printf(\"Found ACPI 1.0 RSDT at %x, copied to %x\\n\", (uintptr_t)table->VendorTable, (uintptr_t)table_target);\n memcpy(table_target, table->VendorTable, sizeof(EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER));\n g_rsdp = (uintptr_t)table->VendorTable;\n break;\n }\n }\n }\n\n if (g_rsdp) {\n const size_t table_buffer_size = 4096;\n\n if (gBS->AllocatePool(EfiLoaderData, table_buffer_size, &early_table_buffer) != EFI_SUCCESS) {\n return false;\n }\n\n enum uacpi_status uacpi_status;\n uacpi_status = uacpi_setup_early_table_access(early_table_buffer, table_buffer_size);\n if (uacpi_status != UACPI_STATUS_OK) {\n printf(\"uACPI early table setup failed: %s\\n\", uacpi_status_to_string(uacpi_status));\n return false;\n }\n\n return true;\n }\n\n printf(\"No ACPI RSDT found\\n\");\n return false;\n}\n\n/*\n * Initialize ACPI namespace without running _INI methods.\n * This is sufficient for PCI root bridge discovery via _CRS evaluation.\n * Avoids side effects like changing power button behavior.\n */\nbool acpi_namespace_init(void) {\n enum uacpi_status uacpi_status;\n\n uacpi_status = uacpi_initialize(UACPI_FLAG_NO_ACPI_MODE);\n if (uacpi_status != UACPI_STATUS_OK) {\n printf(\"uACPI initialization failed: %s\\n\", uacpi_status_to_string(uacpi_status));\n return false;\n }\n\n uacpi_status = uacpi_namespace_load();\n if (uacpi_status != UACPI_STATUS_OK) {\n printf(\"uACPI namespace load failed: %s\\n\", uacpi_status_to_string(uacpi_status));\n return false;\n }\n\n /* Note: We intentionally skip uacpi_namespace_initialize() which runs _INI methods */\n\n return true;\n}\n" }, { "path": "src/ap_trampoline.asm", "content": "; AP Trampoline for BIOS Proxy Helper Core\n; This code is copied to 0x7000 and runs when an AP wakes from SIPI\n; AP starts at CS:IP = 0x0700:0x0000 = linear 0x7000\n;\n; This trampoline stays in 16-bit real mode and jumps to the SeaBIOS\n; 16-bit entry point, which handles the GDT load and 32-bit mode switch.\n\nbits 16\n\nsection .rodata\n\n; APIC MSR\n%define MSR_IA32_APIC_BASE 0x1B\n%define APIC_BASE_EXTD (1 << 10)\n%define APIC_BASE_EN (1 << 11)\n\n; AMD MTRR MSR addresses\n%define MSR_SYS_CFG 0xC0010010\n%define SYS_CFG_MTRR_FIX_DRAM_EN (1 << 18)\n%define SYS_CFG_MTRR_FIX_DRAM_MOD_EN (1 << 19)\n; Fixed MTRRs for conventional memory (0x00000-0x9FFFF)\n%define AMD_MTRR_FIX64k_00000 0x250 ; 0x00000-0x7FFFF (512KB, 8x64KB)\n%define AMD_MTRR_FIX16k_80000 0x258 ; 0x80000-0x9FFFF (128KB, 8x16KB)\n%define AMD_MTRR_FIX16k_A0000 0x259 ; 0xA0000-0xBFFFF (VGA, 128KB, 8x16KB)\n; Fixed MTRRs for BIOS region (0xC0000-0xFFFFF)\n%define AMD_MTRR_FIX4k_C0000 0x268\n%define AMD_MTRR_FIX4k_C8000 0x269\n%define AMD_MTRR_FIX4k_D0000 0x26A\n%define AMD_MTRR_FIX4k_D8000 0x26B\n%define AMD_MTRR_FIX4k_E0000 0x26C\n%define AMD_MTRR_FIX4k_E8000 0x26D\n%define AMD_MTRR_FIX4k_F0000 0x26E\n%define AMD_MTRR_FIX4k_F8000 0x26F\n; WB_DRAM = 0x1E per segment (8 segments per MSR = 0x1E1E1E1E1E1E1E1E)\n%define MTRR_WB_DRAM_LO 0x1E1E1E1E\n%define MTRR_WB_DRAM_HI 0x1E1E1E1E\n\nglobal ap_trampoline_start\nap_trampoline_start:\n cli\n cld\n\n ; Set up DS=0 so we can read from trampoline data area\n xor ax, ax\n mov ds, ax\n mov es, ax\n mov ss, ax\n jmp 0x0000:word (0x7000 + .reload_cs - ap_trampoline_start)\n.reload_cs:\n\n ; ========================================\n ; AMD MTRR unlock for low memory (00000-FFFFF)\n ; Sets conventional memory and BIOS region to WB_DRAM\n ; Required for helper core to access EBDA and F-segment\n ; Skipped on Intel (PAM registers are global, already unlocked by BSP)\n ; Skipped if region is already writable (e.g., under hypervisors)\n ; ========================================\n\n ; First test if the BIOS region is already writable\n ; Try writing a test pattern to 0xF0000 and reading it back\n ; Use segmentation: 0xF000:0x0000 = linear 0xF0000\n ; Save and restore original value to avoid corrupting CSM code\n mov ax, 0xF000\n mov fs, ax\n mov eax, [fs:0] ; save original value\n mov ebx, eax\n xor eax, 0xFFFFFFFF ; flip all bits to create test pattern\n mov [fs:0], eax ; try to write\n cmp [fs:0], eax ; did the write succeed?\n mov [fs:0], ebx ; restore original (regardless of result)\n je .skip_mtrr_unlock ; Region already writable, skip MTRR unlock\n\n ; Region not writable - check if this is AMD\n ; On Intel, PAM registers are global so BSP unlock applies to all cores\n ; If we get here on Intel, something is wrong - halt\n mov eax, 0\n cpuid\n cmp ebx, 0x68747541 ; \"Auth\" (AuthenticAMD)\n jne .unlock_failed ; Not AMD and not writable - halt\n\n ; AMD APM Vol 2 §7.6.3: disable cache and flush around MTRR change.\n ; Paging is off in real mode so no TLB / PGE handling is required.\n ; (CD=1, NW=1) is unsupported per Intel SDM Vol 3A §11.5.3.\n mov eax, cr0\n mov edi, eax ; save CR0\n or eax, 0x40000000 ; CR0.CD = 1\n and eax, ~0x20000000 ; CR0.NW = 0\n mov cr0, eax\n wbinvd\n\n ; AMD system with locked region - attempt MTRR unlock\n ; Enable MTRR modification: set SYS_CFG.MtrrFixDramModEn (bit 19)\n mov ecx, MSR_SYS_CFG\n rdmsr\n or eax, SYS_CFG_MTRR_FIX_DRAM_MOD_EN\n wrmsr\n\n ; Set conventional memory (00000-9FFFF) to WB_DRAM\n mov eax, MTRR_WB_DRAM_LO\n mov edx, MTRR_WB_DRAM_HI\n mov ecx, AMD_MTRR_FIX64k_00000 ; 0x00000-0x7FFFF\n wrmsr\n mov ecx, AMD_MTRR_FIX16k_80000 ; 0x80000-0x9FFFF (includes EBDA)\n wrmsr\n\n ; Set VGA region (A0000-BFFFF) to UC (MMIO)\n xor eax, eax\n xor edx, edx\n mov ecx, AMD_MTRR_FIX16k_A0000\n wrmsr\n\n ; Set BIOS region (C0000-FFFFF) to WB_DRAM\n mov eax, MTRR_WB_DRAM_LO\n mov edx, MTRR_WB_DRAM_HI\n mov ecx, AMD_MTRR_FIX4k_C0000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_C8000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_D0000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_D8000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_E0000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_E8000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_F0000\n wrmsr\n mov ecx, AMD_MTRR_FIX4k_F8000\n wrmsr\n\n ; Disable modification, enable fixed MTRR DRAM attributes\n mov ecx, MSR_SYS_CFG\n rdmsr\n and eax, ~SYS_CFG_MTRR_FIX_DRAM_MOD_EN\n or eax, SYS_CFG_MTRR_FIX_DRAM_EN\n wrmsr\n\n wbinvd\n mov cr0, edi ; restore CR0\n\n ; Verify the unlock worked by testing write again\n ; FS still points to 0xF000 from earlier\n ; Save and restore original value to avoid corrupting CSM code\n mov eax, [fs:0] ; save original value\n mov ebx, eax\n xor eax, 0xFFFFFFFF ; flip all bits to create test pattern\n mov [fs:0], eax ; try to write\n cmp [fs:0], eax ; did the write succeed?\n mov [fs:0], ebx ; restore original (regardless of result)\n jne .unlock_failed ; MTRR unlock didn't help - halt\n\n.skip_mtrr_unlock:\n ; Continue to load registers and jump to SeaBIOS\n jmp .continue_boot\n\n.unlock_failed:\n ; Region still not writable - halt so BSP detects timeout\n hlt\n jmp .unlock_failed\n\n.continue_boot:\n\n ; Hardware-disable LAPIC to prevent the legacy OS from sending IPIs\n ; (including INIT) to this core. The helper core communicates via\n ; memory mailbox only and does not need interrupt delivery.\n ; Must clear both EN (bit 11) and EXTD (bit 10) simultaneously\n ; to correctly transition from x2APIC mode to disabled state.\n ;\n ; If the AP came up already in x2APIC mode (EXTD set), the BSP-side\n ; apic_prepare_for_legacy() must have left x2APIC alone, meaning the\n ; mode is locked (e.g. Nova Lake xAPIC deprecation) or the silicon has\n ; no xAPIC support at all. In either case clearing EXTD here would #GP,\n ; so we leave the APIC enabled. A legacy OS cannot send x2APIC-mode\n ; IPIs via MMIO anyway, so the helper stays unreachable to it.\n mov ecx, MSR_IA32_APIC_BASE\n rdmsr\n test eax, APIC_BASE_EXTD\n jnz .skip_apic_disable\n and eax, ~(APIC_BASE_EN | APIC_BASE_EXTD)\n wrmsr\n.skip_apic_disable:\n\n ; Load 32-bit values into registers for SeaBIOS\n ; (16-bit mode can still use 32-bit registers with operand size prefix)\n mov ebx, [0x7000 + trampoline_mailbox - ap_trampoline_start]\n mov esp, [0x7000 + trampoline_stack - ap_trampoline_start]\n mov esi, (0x7000 + trampoline_helper_ready - ap_trampoline_start)\n\n ; Far jump to SeaBIOS 16-bit entry point (segment:offset)\n jmp far [0x7000 + trampoline_target16 - ap_trampoline_start]\n\n; --- Data area (filled in by C code) ---\n\nalign 4\ntrampoline_mailbox:\n dd 0\n\ntrampoline_stack:\n dd 0\n\n; Far pointer for 16-bit jump: offset (16-bit) then segment (16-bit)\ntrampoline_target16:\n dw 0 ; offset\n dw 0 ; segment\n\ntrampoline_helper_ready:\n dd 0\n\nap_trampoline_end:\n\nglobal ap_trampoline_size\nap_trampoline_size: equ (ap_trampoline_end - ap_trampoline_start)\n\n; Export size and offsets for C code\nglobal ap_trampoline_size_value\nap_trampoline_size_value: dd ap_trampoline_size\n\nglobal ap_trampoline_mailbox_offset\nap_trampoline_mailbox_offset: dd (trampoline_mailbox - ap_trampoline_start)\n\nglobal ap_trampoline_stack_offset\nap_trampoline_stack_offset: dd (trampoline_stack - ap_trampoline_start)\n\nglobal ap_trampoline_target16_offset\nap_trampoline_target16_offset: dd (trampoline_target16 - ap_trampoline_start)\n\nglobal ap_trampoline_helper_ready_offset\nap_trampoline_helper_ready_offset: dd (trampoline_helper_ready - ap_trampoline_start)\n\nsection .note.GNU-stack noalloc noexec nowrite progbits\n" }, { "path": "src/apic.c", "content": "/*\n * APIC handling for legacy BIOS compatibility\n *\n * Modern UEFI systems boot with x2APIC enabled, which prevents legacy PIC\n * interrupts (like IRQ0 timer) from reaching the CPU. This module handles\n * the transition to a state compatible with legacy BIOS operation.\n *\n * References:\n * - Intel 64 Architecture x2APIC Specification\n * - EDK2 BaseXApicX2ApicLib\n * - Linux kernel x86/apic code\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n/* MSR addresses */\n#define MSR_IA32_APIC_BASE 0x1B\n#define MSR_IA32_ARCH_CAPABILITIES 0x10A\n#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD\n\n/* IA32_APIC_BASE bits */\n#define APIC_BASE_BSP (1ULL << 8) /* Bootstrap processor */\n#define APIC_BASE_EXTD (1ULL << 10) /* x2APIC mode enable */\n#define APIC_BASE_EN (1ULL << 11) /* APIC global enable */\n#define APIC_BASE_ADDR_MASK 0xFFFFFFFFFFFFF000ULL\n\n/* IA32_ARCH_CAPABILITIES bits */\n#define ARCH_CAP_XAPIC_DISABLE (1ULL << 21) /* IA32_XAPIC_DISABLE_STATUS exists */\n\n/* IA32_XAPIC_DISABLE_STATUS bits */\n#define XAPIC_DISABLE_LEGACY_DISABLED (1ULL << 0) /* xAPIC mode locked out */\n\n/* x2APIC MSR addresses (base 0x800, offset = xAPIC offset >> 4) */\n#define X2APIC_MSR_SIVR 0x80F /* Spurious Interrupt Vector (0xF0 >> 4) */\n#define X2APIC_MSR_LVT_CMCI 0x82F /* LVT CMCI (0x2F0 >> 4) */\n#define X2APIC_MSR_LVT_TIMER 0x832 /* LVT Timer (0x320 >> 4) */\n#define X2APIC_MSR_LVT_THERMAL 0x833 /* LVT Thermal (0x330 >> 4) */\n#define X2APIC_MSR_LVT_PMC 0x834 /* LVT PMC (0x340 >> 4) */\n#define X2APIC_MSR_LVT_LINT0 0x835 /* LVT LINT0 (0x350 >> 4) */\n#define X2APIC_MSR_LVT_LINT1 0x836 /* LVT LINT1 (0x360 >> 4) */\n#define X2APIC_MSR_LVT_ERROR 0x837 /* LVT Error (0x370 >> 4) */\n#define X2APIC_MSR_VERSION 0x803 /* Version (0x030 >> 4) */\n#define X2APIC_MSR_TPR 0x808 /* Task Priority (0x080 >> 4) */\n\n/* xAPIC MMIO offsets (from APIC base, typically 0xFEE00000) */\n#define XAPIC_VERSION_OFFSET 0x030\n#define XAPIC_TPR_OFFSET 0x080\n#define XAPIC_SIVR_OFFSET 0x0F0\n#define XAPIC_LVT_CMCI_OFFSET 0x2F0\n#define XAPIC_LVT_TIMER_OFFSET 0x320\n#define XAPIC_LVT_THERMAL_OFFSET 0x330\n#define XAPIC_LVT_PMC_OFFSET 0x340\n#define XAPIC_LVT_LINT0_OFFSET 0x350\n#define XAPIC_LVT_LINT1_OFFSET 0x360\n#define XAPIC_LVT_ERROR_OFFSET 0x370\n\n/* LVT register bits */\n#define LVT_VECTOR_MASK 0xFF\n#define LVT_DELIVERY_MODE_SHIFT 8\n#define LVT_DELIVERY_MODE_MASK (0x7 << LVT_DELIVERY_MODE_SHIFT)\n#define LVT_DELIVERY_FIXED (0 << LVT_DELIVERY_MODE_SHIFT)\n#define LVT_DELIVERY_NMI (4 << LVT_DELIVERY_MODE_SHIFT)\n#define LVT_DELIVERY_EXTINT (7 << LVT_DELIVERY_MODE_SHIFT)\n#define LVT_POLARITY_ACTIVE_LOW (1 << 13)\n#define LVT_TRIGGER_LEVEL (1 << 15)\n#define LVT_MASK (1 << 16)\n\n/* Spurious Interrupt Vector Register bits */\n#define SIVR_VECTOR_MASK 0xFF\n#define SIVR_APIC_ENABLE (1 << 8)\n#define SIVR_FOCUS_DISABLE (1 << 9)\n\n/*\n * Check if x2APIC mode is locked and cannot be disabled.\n * Returns true if x2APIC is locked (will #GP on disable attempt).\n */\nstatic bool x2apic_is_locked(void)\n{\n uint32_t eax, ebx, ecx, edx;\n\n /* Check CPUID for IA32_ARCH_CAPABILITIES support (leaf 7, ECX bit 29) */\n asm volatile (\"cpuid\"\n : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx)\n : \"a\"(7), \"c\"(0));\n\n if (!(edx & (1 << 29))) {\n /* IA32_ARCH_CAPABILITIES not supported, no lock possible */\n return false;\n }\n\n /* Check if IA32_XAPIC_DISABLE_STATUS MSR exists */\n uint64_t arch_cap = rdmsr(MSR_IA32_ARCH_CAPABILITIES);\n if (!(arch_cap & ARCH_CAP_XAPIC_DISABLE)) {\n /* MSR not supported, no lock possible */\n return false;\n }\n\n /* Read the lock status */\n uint64_t xapic_status = rdmsr(MSR_IA32_XAPIC_DISABLE_STATUS);\n return !!(xapic_status & XAPIC_DISABLE_LEGACY_DISABLED);\n}\n\nstatic bool lvt_should_mask(uint32_t lvt)\n{\n switch ((lvt >> LVT_DELIVERY_MODE_SHIFT) & 7) {\n case 0b000: /* Fixed */\n case 0b001: /* Lowest Priority */\n case 0b100: /* NMI */\n case 0b111: /* ExtINT */\n return true;\n default: /* SMI, INIT, Reserved */\n return false;\n }\n}\n\n/* MADT NMI routing (loaded once by apic_prepare_for_legacy). */\nstatic uint8_t g_nmi_lint = 1; /* default: NMI on LINT1 */\nstatic uint16_t g_nmi_madt_flags = 0; /* MADT polarity/trigger flags */\n\nstatic void load_nmi_madt_info(void)\n{\n struct uacpi_table madt_table;\n if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table)\n != UACPI_STATUS_OK) {\n return;\n }\n struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;\n uint8_t *entry = (uint8_t *)(madt + 1);\n uint8_t *end = (uint8_t *)madt + madt->hdr.length;\n\n while (entry < end) {\n struct acpi_entry_hdr *hdr = (struct acpi_entry_hdr *)entry;\n if (hdr->length < 2) break;\n if (hdr->type == ACPI_MADT_ENTRY_TYPE_LAPIC_NMI) {\n struct acpi_madt_lapic_nmi *nmi =\n (struct acpi_madt_lapic_nmi *)entry;\n g_nmi_lint = nmi->lint & 1;\n g_nmi_madt_flags = nmi->flags;\n break;\n }\n if (hdr->type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC_NMI) {\n struct acpi_madt_x2apic_nmi *nmi =\n (struct acpi_madt_x2apic_nmi *)entry;\n g_nmi_lint = nmi->lint & 1;\n g_nmi_madt_flags = nmi->flags;\n break;\n }\n entry += hdr->length;\n }\n uacpi_table_unref(&madt_table);\n}\n\n/* Build the LVT value (delivery mode + polarity/trigger) for one LINT pin.\n * The pin matching MADT's NMI routing gets NMI delivery with MADT-supplied\n * polarity/trigger; the other gets ExtINT (edge, active high). */\nstatic uint32_t lint_lvt_value(int pin)\n{\n if (pin == g_nmi_lint) {\n uint32_t val = LVT_DELIVERY_NMI;\n if ((g_nmi_madt_flags & ACPI_MADT_POLARITY_MASK)\n == ACPI_MADT_POLARITY_ACTIVE_LOW)\n val |= LVT_POLARITY_ACTIVE_LOW;\n if ((g_nmi_madt_flags & ACPI_MADT_TRIGGERING_MASK)\n == ACPI_MADT_TRIGGERING_LEVEL)\n val |= LVT_TRIGGER_LEVEL;\n return val;\n }\n return LVT_DELIVERY_EXTINT;\n}\n\n/*\n * Configure LAPIC for legacy BIOS operation in x2APIC mode (MSR access).\n * Sets up LINT0/LINT1 per MADT-reported NMI routing (default: LINT1=NMI).\n *\n * Note: The LAPIC ignores trigger mode for ExtINT and NMI delivery modes,\n * always using edge-triggered internally.\n */\nstatic void x2apic_configure_for_legacy(void)\n{\n uint64_t val;\n uint32_t max_lvt = ((uint32_t)rdmsr(X2APIC_MSR_VERSION) >> 16) & 0xFF;\n\n /* Clear task priority to allow all interrupts */\n wrmsr(X2APIC_MSR_TPR, 0);\n\n /* Mask stale LVT entries to prevent unexpected interrupts.\n * Only mask entries with Fixed, Lowest Priority, NMI, or ExtINT delivery\n * mode. Leave SMI, INIT, and reserved delivery modes untouched as firmware\n * may rely on them (e.g. thermal management via SMI). */\n uint64_t lvt;\n lvt = rdmsr(X2APIC_MSR_LVT_TIMER);\n if (lvt_should_mask(lvt))\n wrmsr(X2APIC_MSR_LVT_TIMER, lvt | LVT_MASK);\n lvt = rdmsr(X2APIC_MSR_LVT_ERROR);\n if (lvt_should_mask(lvt))\n wrmsr(X2APIC_MSR_LVT_ERROR, lvt | LVT_MASK);\n if (max_lvt >= 4) {\n lvt = rdmsr(X2APIC_MSR_LVT_PMC);\n if (lvt_should_mask(lvt))\n wrmsr(X2APIC_MSR_LVT_PMC, lvt | LVT_MASK);\n }\n if (max_lvt >= 5) {\n lvt = rdmsr(X2APIC_MSR_LVT_THERMAL);\n if (lvt_should_mask(lvt))\n wrmsr(X2APIC_MSR_LVT_THERMAL, lvt | LVT_MASK);\n }\n if (max_lvt >= 6) {\n lvt = rdmsr(X2APIC_MSR_LVT_CMCI);\n if (lvt_should_mask(lvt))\n wrmsr(X2APIC_MSR_LVT_CMCI, lvt | LVT_MASK);\n }\n\n /* Configure LINT0 / LINT1: one gets NMI (per MADT), the other ExtINT. */\n val = rdmsr(X2APIC_MSR_LVT_LINT0);\n printf(\" x2APIC LINT0 before: 0x%08lx\\n\", (uint32_t)val);\n val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |\n LVT_POLARITY_ACTIVE_LOW | LVT_MASK);\n val |= lint_lvt_value(0);\n wrmsr(X2APIC_MSR_LVT_LINT0, val);\n printf(\" x2APIC LINT0 after: 0x%08lx\\n\", (uint32_t)rdmsr(X2APIC_MSR_LVT_LINT0));\n\n val = rdmsr(X2APIC_MSR_LVT_LINT1);\n printf(\" x2APIC LINT1 before: 0x%08lx\\n\", (uint32_t)val);\n val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |\n LVT_POLARITY_ACTIVE_LOW | LVT_MASK);\n val |= lint_lvt_value(1);\n wrmsr(X2APIC_MSR_LVT_LINT1, val);\n printf(\" x2APIC LINT1 after: 0x%08lx\\n\", (uint32_t)rdmsr(X2APIC_MSR_LVT_LINT1));\n\n /* Configure Spurious Interrupt Vector Register:\n * - APIC software enable (bit 8) - required for LAPIC to work\n * - Spurious vector = 0x0F (matches legacy 8259 PIC IRQ7 spurious interrupt)\n */\n val = rdmsr(X2APIC_MSR_SIVR);\n printf(\" x2APIC SIVR before: 0x%08lx\\n\", (uint32_t)val);\n val &= ~SIVR_VECTOR_MASK;\n val |= SIVR_APIC_ENABLE | 0x0F;\n wrmsr(X2APIC_MSR_SIVR, val);\n printf(\" x2APIC SIVR after: 0x%08lx\\n\", (uint32_t)rdmsr(X2APIC_MSR_SIVR));\n}\n\n/*\n * Configure LAPIC for legacy BIOS operation in xAPIC mode (MMIO access).\n * Sets up LINT0 for ExtINT, LINT1 for NMI per Intel SDM Appendix D.\n *\n * Note: The LAPIC ignores trigger mode for ExtINT and NMI delivery modes,\n * always using edge-triggered internally. We set edge-triggered explicitly\n * to match Intel's documented example (0x0700 for ExtINT, 0x0400 for NMI).\n */\nstatic void xapic_configure_for_legacy(uintptr_t apic_base)\n{\n volatile uint32_t *lint0_reg = (volatile uint32_t *)(apic_base + XAPIC_LVT_LINT0_OFFSET);\n volatile uint32_t *lint1_reg = (volatile uint32_t *)(apic_base + XAPIC_LVT_LINT1_OFFSET);\n volatile uint32_t *sivr_reg = (volatile uint32_t *)(apic_base + XAPIC_SIVR_OFFSET);\n uint32_t val;\n uint32_t max_lvt = (*(volatile uint32_t *)(apic_base + XAPIC_VERSION_OFFSET) >> 16) & 0xFF;\n\n /* Clear task priority to allow all interrupts */\n *(volatile uint32_t *)(apic_base + XAPIC_TPR_OFFSET) = 0;\n\n /* Mask stale LVT entries to prevent unexpected interrupts.\n * Only mask entries with Fixed, Lowest Priority, NMI, or ExtINT delivery\n * mode. Leave SMI, INIT, and reserved delivery modes untouched as firmware\n * may rely on them (e.g. thermal management via SMI). */\n uint32_t lvt;\n lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_TIMER_OFFSET);\n if (lvt_should_mask(lvt))\n *(volatile uint32_t *)(apic_base + XAPIC_LVT_TIMER_OFFSET) = lvt | LVT_MASK;\n lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_ERROR_OFFSET);\n if (lvt_should_mask(lvt))\n *(volatile uint32_t *)(apic_base + XAPIC_LVT_ERROR_OFFSET) = lvt | LVT_MASK;\n if (max_lvt >= 4) {\n lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_PMC_OFFSET);\n if (lvt_should_mask(lvt))\n *(volatile uint32_t *)(apic_base + XAPIC_LVT_PMC_OFFSET) = lvt | LVT_MASK;\n }\n if (max_lvt >= 5) {\n lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_THERMAL_OFFSET);\n if (lvt_should_mask(lvt))\n *(volatile uint32_t *)(apic_base + XAPIC_LVT_THERMAL_OFFSET) = lvt | LVT_MASK;\n }\n if (max_lvt >= 6) {\n lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_CMCI_OFFSET);\n if (lvt_should_mask(lvt))\n *(volatile uint32_t *)(apic_base + XAPIC_LVT_CMCI_OFFSET) = lvt | LVT_MASK;\n }\n\n /* Configure LINT0 / LINT1: one gets NMI (per MADT), the other ExtINT. */\n val = *lint0_reg;\n printf(\" xAPIC LINT0 before: 0x%08x\\n\", val);\n val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |\n LVT_POLARITY_ACTIVE_LOW | LVT_MASK);\n val |= lint_lvt_value(0);\n *lint0_reg = val;\n printf(\" xAPIC LINT0 after: 0x%08x\\n\", *lint0_reg);\n\n val = *lint1_reg;\n printf(\" xAPIC LINT1 before: 0x%08x\\n\", val);\n val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |\n LVT_POLARITY_ACTIVE_LOW | LVT_MASK);\n val |= lint_lvt_value(1);\n *lint1_reg = val;\n printf(\" xAPIC LINT1 after: 0x%08x\\n\", *lint1_reg);\n\n /* Configure Spurious Interrupt Vector Register:\n * - APIC software enable (bit 8) - required for LAPIC to work\n * - Spurious vector = 0x0F (matches legacy 8259 PIC IRQ7 spurious interrupt)\n */\n val = *sivr_reg;\n printf(\" xAPIC SIVR before: 0x%08x\\n\", val);\n val &= ~SIVR_VECTOR_MASK;\n val |= SIVR_APIC_ENABLE | 0x0F;\n *sivr_reg = val;\n printf(\" xAPIC SIVR after: 0x%08x\\n\", *sivr_reg);\n}\n\n/*\n * Prepare APIC for legacy BIOS operation.\n *\n * This function handles the APIC configuration needed for legacy software\n * that expects PIC interrupts (especially IRQ0 timer) to work correctly.\n *\n * Strategy: Keep LAPIC enabled in xAPIC mode with LINT0 configured for\n * ExtINT passthrough. This matches QEMU's default behavior and is the\n * standard configuration for legacy BIOS systems.\n *\n * - If in x2APIC mode (not locked): transition to xAPIC, configure ExtINT\n * - If in x2APIC mode (locked): configure ExtINT via MSR (cannot leave x2APIC)\n * - If already in xAPIC mode: configure ExtINT via MMIO\n */\nvoid apic_prepare_for_legacy(void)\n{\n uint64_t apic_base_msr;\n uintptr_t apic_base_addr;\n bool lapic_enabled, x2apic_enabled;\n\n printf(\"Configuring APIC for legacy BIOS compatibility...\\n\");\n\n load_nmi_madt_info();\n printf(\" NMI on LINT%u (MADT flags 0x%04x)\\n\", g_nmi_lint, g_nmi_madt_flags);\n\n /* Read current APIC state */\n apic_base_msr = rdmsr(MSR_IA32_APIC_BASE);\n apic_base_addr = apic_base_msr & APIC_BASE_ADDR_MASK;\n lapic_enabled = !!(apic_base_msr & APIC_BASE_EN);\n x2apic_enabled = !!(apic_base_msr & APIC_BASE_EXTD);\n\n printf(\" IA32_APIC_BASE: 0x%016lx (addr=0x%lx, EN=%d, x2APIC=%d, BSP=%d)\\n\",\n apic_base_msr, apic_base_addr,\n lapic_enabled, x2apic_enabled,\n !!(apic_base_msr & APIC_BASE_BSP));\n\n if (!lapic_enabled) {\n printf(\" LAPIC disabled, enabling in xAPIC mode\\n\");\n apic_base_msr |= APIC_BASE_EN;\n apic_base_msr &= ~APIC_BASE_EXTD;\n wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);\n apic_base_addr = apic_base_msr & APIC_BASE_ADDR_MASK;\n xapic_configure_for_legacy(apic_base_addr);\n printf(\" APIC configuration complete\\n\");\n return;\n }\n\n if (x2apic_enabled) {\n /* Check if x2APIC mode is locked */\n bool locked = x2apic_is_locked();\n printf(\" x2APIC lock status: %s\\n\", locked ? \"LOCKED\" : \"not locked\");\n\n if (!locked) {\n /*\n * Transition from x2APIC to xAPIC mode.\n * Cannot go directly x2APIC -> xAPIC (causes #GP).\n * Must disable first, then re-enable in xAPIC mode.\n */\n printf(\" Transitioning x2APIC -> xAPIC mode\\n\");\n\n /* Step 1: Disable LAPIC (clear both EN and EXTD) */\n apic_base_msr &= ~(APIC_BASE_EN | APIC_BASE_EXTD);\n wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);\n\n /* Step 2: Re-enable in xAPIC mode (set EN, keep EXTD clear) */\n apic_base_msr |= APIC_BASE_EN;\n wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);\n\n /* Verify transition */\n apic_base_msr = rdmsr(MSR_IA32_APIC_BASE);\n printf(\" IA32_APIC_BASE after: 0x%016lx (EN=%d, x2APIC=%d)\\n\",\n apic_base_msr,\n !!(apic_base_msr & APIC_BASE_EN),\n !!(apic_base_msr & APIC_BASE_EXTD));\n\n /* Now configure LAPIC via MMIO */\n xapic_configure_for_legacy(apic_base_addr);\n } else {\n /*\n * x2APIC is locked. Cannot leave x2APIC mode without #GP.\n * Configure LAPIC for legacy operation via MSR.\n */\n printf(\" x2APIC locked, configuring for legacy via MSR\\n\");\n x2apic_configure_for_legacy();\n }\n } else {\n /*\n * Already in xAPIC mode. Configure LAPIC via MMIO.\n * This matches QEMU's default LAPIC configuration.\n */\n printf(\" Configuring xAPIC for legacy operation\\n\");\n xapic_configure_for_legacy(apic_base_addr);\n }\n\n printf(\" APIC configuration complete\\n\");\n}\n" }, { "path": "src/apic.h", "content": "/*\n * APIC handling for legacy BIOS compatibility\n */\n\n#ifndef _APIC_H\n#define _APIC_H\n\n/*\n * Prepare APIC for legacy BIOS operation.\n *\n * Disables LAPIC or configures it for ExtINT passthrough so that\n * legacy 8259 PIC interrupts (especially IRQ0 timer) can reach the CPU.\n *\n * Must be called after ExitBootServices but before CSM initialization.\n */\nvoid apic_prepare_for_legacy(void);\n\n#endif /* _APIC_H */\n" }, { "path": "src/arch/ia32/Thunk16.asm", "content": ";------------------------------------------------------------------------------\n;\n; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
\n; SPDX-License-Identifier: BSD-2-Clause-Patent\n;\n; Module Name:\n;\n; Thunk.asm\n;\n; Abstract:\n;\n; Real mode thunk\n;\n;------------------------------------------------------------------------------\n\n%define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001\n%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\n%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\n\n%define ASM_PFX(name) name\n\nglobal ASM_PFX(m16Size)\nglobal ASM_PFX(mThunk16Attr)\nglobal ASM_PFX(m16Gdt)\nglobal ASM_PFX(m16GdtrBase)\nglobal ASM_PFX(mTransition)\nglobal ASM_PFX(m16Start)\n\nstruc IA32_REGS\n\n ._EDI: resd 1\n ._ESI: resd 1\n ._EBP: resd 1\n ._ESP: resd 1\n ._EBX: resd 1\n ._EDX: resd 1\n ._ECX: resd 1\n ._EAX: resd 1\n ._DS: resw 1\n ._ES: resw 1\n ._FS: resw 1\n ._GS: resw 1\n ._EFLAGS: resd 1\n ._EIP: resd 1\n ._CS: resw 1\n ._SS: resw 1\n .size:\n\nendstruc\n\n;; .const\n\nSECTION .data\n\n;\n; These are global constant to convey information to C code.\n;\nASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\nASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)\nASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start)\nASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)\nASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)\n\nSECTION .text\n\nASM_PFX(m16Start):\n\nSavedGdt:\n dw 0\n dd 0\n\n;------------------------------------------------------------------------------\n; _BackFromUserCode() takes control in real mode after 'retf' has been executed\n; by user code. It will be shadowed to somewhere in memory below 1MB.\n;------------------------------------------------------------------------------\n_BackFromUserCode:\n ;\n ; The order of saved registers on the stack matches the order they appears\n ; in IA32_REGS structure. This facilitates wrapper function to extract them\n ; into that structure.\n ;\nBITS 16\n push ss\n push cs\n ;\n ; Note: We can't use o32 on the next instruction because of a bug\n ; in NASM 2.09.04 through 2.10rc1.\n ;\n call dword .Base ; push eip\n.Base:\n pushfd\n cli ; disable interrupts\n push gs\n push fs\n push es\n push ds\n pushad\n mov edx, strict dword 0\n.ThunkAttrEnd:\n test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15\n jz .1\n mov ax, 2401h\n int 15h\n cli ; disable interrupts\n jnc .2\n.1:\n test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL\n jz .2\n in al, 92h\n or al, 2\n out 92h, al ; deactivate A20M#\n.2:\n xor eax, eax\n mov ax, ss\n lea ebp, [esp + IA32_REGS.size]\n mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp\n mov bx, [bp - IA32_REGS.size + IA32_REGS._EIP]\n shl eax, 4 ; shl eax, 4\n add ebp, eax ; add ebp, eax\n mov eax, strict dword 0\n.SavedCr4End:\n mov cr4, eax\no32 lgdt [cs:bx + (SavedGdt - .Base)]\n mov eax, strict dword 0\n.SavedCr3End:\n mov cr3, eax ; restore page tables before enabling paging\n mov eax, strict dword 0\n.SavedCr0End:\n mov cr0, eax\n mov ax, strict word 0\n.SavedSsEnd:\n mov ss, eax\n mov esp, strict dword 0\n.SavedEspEnd:\no32 retf ; return to protected mode\n\n_EntryPoint:\n DD _ToUserCode - ASM_PFX(m16Start)\n DW 8h\n_16Idtr:\n DW (1 << 10) - 1\n DD 0\n_16Gdtr_zero:\n DW 0\n DD 0\n_16Gdtr:\n DW GdtEnd - _NullSegDesc - 1\n_16GdtrBase:\n DD 0\n\n;------------------------------------------------------------------------------\n; _ToUserCode() takes control in real mode before passing control to user code.\n; It will be shadowed to somewhere in memory below 1MB.\n;------------------------------------------------------------------------------\n_ToUserCode:\nBITS 16\n mov dx, ss\n mov ss, cx ; set new segment selectors\n mov ds, cx\n mov es, cx\n mov fs, cx\n mov gs, cx\n and byte [edi + 5], 0xFD ; clear TSS busy bit for next ltr\n mov cx, TSS_SEL\n ltr cx\n mov cr0, eax ; real mode starts at next instruction\n ; which (per SDM) *must* be a far JMP.\n jmp 0:strict word 0\n.RealAddrEnd:\n mov cr4, ebp\n xor eax, eax\n mov cr3, eax ; clear stale page table pointer\n mov ss, si ; set up 16-bit stack segment\n xchg esp, ebx ; set up 16-bit stack pointer\n mov bp, [esp + IA32_REGS.size]\n mov [cs:bp + (_BackFromUserCode.SavedSsEnd - 2 - _BackFromUserCode)], dx\n mov [cs:bp + (_BackFromUserCode.SavedEspEnd - 4 - _BackFromUserCode)], ebx\n lidt [cs:bp + (_16Idtr - _BackFromUserCode)]\n lgdt [cs:bp + (_16Gdtr_zero - _BackFromUserCode)]\n\n popad\n pop ds\n pop es\n pop fs\n pop gs\n popfd\n\no32 retf ; transfer control to user code\n\nALIGN 16\n_NullSegDesc DQ 0\n_16CsDesc:\n DW -1\n DW 0\n DB 0\n DB 9bh\n DB 8fh ; 16-bit segment, 4GB limit\n DB 0\n_16DsDesc:\n DW -1\n DW 0\n DB 0\n DB 93h\n DB 8fh ; 16-bit segment, 4GB limit\n DB 0\n_TssSeg:\n DW 0FFFFh ; Limit (match BIOS default)\n DW 0 ; Base 15:0\n DB 0 ; Base 23:16\n DB 89h ; P=1, DPL=0, Type=9 (available TSS)\n DB 0 ; G=0, Limit 19:16=0\n DB 0 ; Base 31:24\n\nTSS_SEL equ _TssSeg - _NullSegDesc\n\nGdtEnd:\n\n;------------------------------------------------------------------------------\n; IA32_REGISTER_SET *\n; EFIAPI\n; InternalAsmThunk16 (\n; IN IA32_REGISTER_SET *RegisterSet,\n; IN OUT VOID *Transition\n; );\n;------------------------------------------------------------------------------\nglobal ASM_PFX(InternalAsmThunk16)\nASM_PFX(InternalAsmThunk16):\nBITS 32\n push ebp\n push ebx\n push esi\n push edi\n push ds\n push es\n push fs\n push gs\n mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter\n movzx edx, word [esi + IA32_REGS._SS]\n mov edi, [esi + IA32_REGS._ESP]\n add edi, - (IA32_REGS.size + 4) ; reserve stack space\n mov ebx, edi ; ebx <- stack offset\n imul eax, edx, 16 ; eax <- edx * 16\n push IA32_REGS.size / 4\n add edi, eax ; edi <- linear address of 16-bit stack\n pop ecx\n rep movsd ; copy RegSet\n mov eax, [esp + 40] ; eax <- address of transition code\n mov esi, edx ; esi <- 16-bit stack segment\n lea edx, [eax + (_BackFromUserCode.SavedCr0End - ASM_PFX(m16Start))]\n mov ecx, eax\n and ecx, 0fh\n shl eax, 12\n lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))]\n mov ax, cx\n stosd ; [edi] <- return address of user code\n add eax, _ToUserCode.RealAddrEnd - _BackFromUserCode\n mov [edx + (_ToUserCode.RealAddrEnd - 4 - _BackFromUserCode.SavedCr0End)], eax\n sgdt [edx + (SavedGdt - _BackFromUserCode.SavedCr0End)]\n sidt [esp + 36] ; save IDT stack in argument space\n mov eax, cr0\n mov [edx - 4], eax ; save CR0 in _BackFromUserCode.SavedCr0End - 4\n mov eax, 00000010h ; clear all bits except ET\n mov ebp, cr4\n mov [edx + (_BackFromUserCode.SavedCr4End - 4 - _BackFromUserCode.SavedCr0End)], ebp\n xor ebp, ebp ; zero out CR4\n push eax ; save CR0 value (0x10)\n mov eax, cr3\n mov [edx + (_BackFromUserCode.SavedCr3End - 4 - _BackFromUserCode.SavedCr0End)], eax\n pop eax ; restore CR0 value\n lea edi, [edx + (_TssSeg - _BackFromUserCode.SavedCr0End)]\n push 10h\n pop ecx ; ecx <- selector for data segments\n lgdt [edx + (_16Gdtr - _BackFromUserCode.SavedCr0End)]\n pushfd ; Save df/if indeed\n call dword far [edx + (_EntryPoint - _BackFromUserCode.SavedCr0End)]\n popfd\n lidt [esp + 36] ; restore protected mode IDTR\n lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS\n pop gs\n pop fs\n pop es\n pop ds\n pop edi\n pop esi\n pop ebx\n pop ebp\n ret\n" }, { "path": "src/arch/x86_64/Thunk16.asm", "content": ";------------------------------------------------------------------------------\n;\n; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n; SPDX-License-Identifier: BSD-2-Clause-Patent\n;\n; Module Name:\n;\n; Thunk.asm\n;\n; Abstract:\n;\n; Real mode thunk\n;\n;------------------------------------------------------------------------------\n\n%define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001\n%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\n%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\n\n%define ASM_PFX(name) name\n\nglobal ASM_PFX(m16Size)\nglobal ASM_PFX(mThunk16Attr)\nglobal ASM_PFX(m16Gdt)\nglobal ASM_PFX(m16GdtrBase)\nglobal ASM_PFX(mTransition)\nglobal ASM_PFX(m16Start)\n\nstruc IA32_REGS\n\n ._EDI: resd 1\n ._ESI: resd 1\n ._EBP: resd 1\n ._ESP: resd 1\n ._EBX: resd 1\n ._EDX: resd 1\n ._ECX: resd 1\n ._EAX: resd 1\n ._DS: resw 1\n ._ES: resw 1\n ._FS: resw 1\n ._GS: resw 1\n ._EFLAGS: resq 1\n ._EIP: resd 1\n ._CS: resw 1\n ._SS: resw 1\n .size:\n\nendstruc\n\nSECTION .data\n\n;\n; These are global constant to convey information to C code.\n;\nASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\nASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)\nASM_PFX(m16Gdt) DW _NullSeg - ASM_PFX(m16Start)\nASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)\nASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)\n\nSECTION .text\n\nASM_PFX(m16Start):\n\nSavedGdt:\n dw 0\n dq 0\n\n;------------------------------------------------------------------------------\n; _BackFromUserCode() takes control in real mode after 'retf' has been executed\n; by user code. It will be shadowed to somewhere in memory below 1MB.\n;------------------------------------------------------------------------------\n_BackFromUserCode:\n ;\n ; The order of saved registers on the stack matches the order they appears\n ; in IA32_REGS structure. This facilitates wrapper function to extract them\n ; into that structure.\n ;\nBITS 16\n push ss\n push cs\n ;\n ; Note: We can't use o32 on the next instruction because of a bug\n ; in NASM 2.09.04 through 2.10rc1.\n ;\n call dword .Base ; push eip\n.Base:\n push dword 0 ; reserved high order 32 bits of EFlags\n pushfd\n cli ; disable interrupts\n push gs\n push fs\n push es\n push ds\n pushad\n mov edx, strict dword 0\n.ThunkAttrEnd:\n test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15\n jz .1\n mov ax, 2401h\n int 15h\n cli ; disable interrupts\n jnc .2\n.1:\n test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL\n jz .2\n in al, 92h\n or al, 2\n out 92h, al ; deactivate A20M#\n.2:\n xor eax, eax\n mov ax, ss\n lea ebp, [esp + IA32_REGS.size]\n mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp\n mov ebx, [bp - IA32_REGS.size + IA32_REGS._EIP]\n shl eax, 4 ; shl eax, 4\n add ebp, eax ; add ebp, eax\n mov eax, cs\n shl eax, 4\n lea eax, [eax + ebx + (.X64JmpEnd - .Base)]\n mov [cs:bx + (.X64JmpEnd - 6 - .Base)], eax\n mov eax, strict dword 0\n.SavedCr4End:\n mov cr4, eax\no32 lgdt [cs:bx + (SavedGdt - .Base)]\n mov ecx, 0c0000080h\n mov eax, strict dword 0\n.SavedEFERLowEnd:\n mov edx, strict dword 0\n.SavedEFERHighEnd:\n wrmsr\n mov eax, strict dword 0\n.SavedCr3End:\n mov cr3, eax ; restore page tables before enabling paging\n mov eax, strict dword 0\n.SavedCr0End:\n mov cr0, eax\n jmp 0:strict dword 0\n.X64JmpEnd:\nBITS 64\n nop\n mov rsp, strict qword 0\n.SavedSpEnd:\n nop\n ret\n\n_EntryPoint:\n DD _ToUserCode - ASM_PFX(m16Start)\n DW CODE16\n_16Gdtr:\n DW GDT_SIZE - 1\n_16GdtrBase:\n DQ 0\n_16Idtr:\n DW (1 << 10) - 1\n DD 0\n_16Gdtr_zero:\n DW 0\n DD 0\n\n;------------------------------------------------------------------------------\n; _ToUserCode() takes control in real mode before passing control to user code.\n; It will be shadowed to somewhere in memory below 1MB.\n;------------------------------------------------------------------------------\n_ToUserCode:\nBITS 16\n mov ss, dx ; set new segment selectors\n mov ds, dx\n mov es, dx\n mov fs, dx\n mov gs, dx\n and byte [edi + 5], 0xFD ; clear TSS busy bit for next ltr\n mov cx, TSS_SEL\n ltr cx\n mov ecx, 0c0000080h\n mov cr0, eax ; real mode starts at next instruction\n xor eax, eax\n mov cr3, eax ; clear stale page table pointer\n xor edx, edx\n wrmsr\n mov cr4, ebp\n mov ss, si ; set up 16-bit stack segment\n mov esp, ebx ; set up 16-bit stack pointer\n call dword .Base ; push eip\n.Base:\n pop ebp ; ebp <- address of .Base\n push word [dword esp + IA32_REGS.size + 2]\n lea ax, [bp + (.RealMode - .Base)]\n push ax\n retf ; execution begins at next instruction\n.RealMode:\n\no32 lidt [cs:bp + (_16Idtr - .Base)]\no32 lgdt [cs:bp + (_16Gdtr_zero - .Base)]\n\n popad\n pop ds\n pop es\n pop fs\n pop gs\n popfd\n lea esp, [esp + 4] ; skip high order 32 bits of EFlags\n\no32 retf ; transfer control to user code\n\nALIGN 8\n\nCODE16 equ _16Code - $\nDATA16 equ _16Data - $\nDATA32 equ _32Data - $\n\n_NullSeg DQ 0\n_16Code:\n DW -1\n DW 0\n DB 0\n DB 9bh\n DB 8fh ; 16-bit segment, 4GB limit\n DB 0\n_16Data:\n DW -1\n DW 0\n DB 0\n DB 93h\n DB 8fh ; 16-bit segment, 4GB limit\n DB 0\n_32Data:\n DW -1\n DW 0\n DB 0\n DB 93h\n DB 0cfh ; 16-bit segment, 4GB limit\n DB 0\n_TssSeg:\n DW 0FFFFh ; Limit (match BIOS default)\n DW 0 ; Base 15:0\n DB 0 ; Base 23:16\n DB 89h ; P=1, DPL=0, Type=9 (available TSS)\n DB 0 ; G=0, Limit 19:16=0\n DB 0 ; Base 31:24\n DD 0 ; Base 63:32 (64-bit TSS descriptor\n DD 0 ; requires 16 bytes in long mode)\n\nTSS_SEL equ _TssSeg - _NullSeg\n\nGDT_SIZE equ $ - _NullSeg\n\n;------------------------------------------------------------------------------\n; IA32_REGISTER_SET *\n; EFIAPI\n; InternalAsmThunk16 (\n; IN IA32_REGISTER_SET *RegisterSet,\n; IN OUT VOID *Transition\n; );\n;------------------------------------------------------------------------------\nglobal ASM_PFX(InternalAsmThunk16)\nASM_PFX(InternalAsmThunk16):\nBITS 64\n push rbp\n push rbx\n push rsi\n push rdi\n\n mov ebx, ds\n push rbx ; Save ds segment register on the stack\n mov ebx, es\n push rbx ; Save es segment register on the stack\n mov ebx, ss\n push rbx ; Save ss segment register on the stack\n\n push fs\n push gs\n mov rsi, rcx\n movzx r8d, word [rsi + IA32_REGS._SS]\n mov edi, [rsi + IA32_REGS._ESP]\n lea rdi, [edi - (IA32_REGS.size + 4)]\n imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16\n mov ebx, edi ; ebx <- stack for 16-bit code\n push IA32_REGS.size / 4\n add edi, eax ; edi <- linear address of 16-bit stack\n pop rcx\n rep movsd ; copy RegSet\n lea ecx, [rdx + (_BackFromUserCode.SavedCr4End - ASM_PFX(m16Start))]\n mov eax, edx ; eax <- transition code address\n and edx, 0fh\n shl eax, 12 ; segment address in high order 16 bits\n lea ax, [rdx + (_BackFromUserCode - ASM_PFX(m16Start))] ; offset address\n stosd ; [edi] <- return address of user code\n\n sgdt [rsp + 60h] ; save GDT stack in argument space\n movzx r10, word [rsp + 60h] ; r10 <- GDT limit\n lea r11, [rcx + (ASM_PFX(InternalAsmThunk16) - _BackFromUserCode.SavedCr4End) + 0xf]\n and r11, ~0xf ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer\n\n mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End)], r10w ; save the limit of shadowed GDT table\n mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End) + 2], r11 ; save the base address of shadowed GDT table\n\n mov rsi, [rsp + 62h] ; rsi <- the original GDT base address\n xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table\n inc rcx ; rcx <- the size of memory to copy\n xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table\n rep movsb ; perform memory copy to shadow GDT table\n mov rcx, r10 ; restore the orignal rcx before memory copy\n mov rdi, r11 ; restore the original rdi before memory copy\n\n sidt [rsp + 50h] ; save IDT stack in argument space\n mov rax, cr0\n mov [rcx + (_BackFromUserCode.SavedCr0End - 4 - _BackFromUserCode.SavedCr4End)], eax\n mov eax, 00000010h ; clear all bits except ET\n push rax\n push rcx\n push rdx\n mov ecx, 0c0000080h\n rdmsr\n btr eax, 10 ; Reset LMA flag to avoid crash on AMD Zen CPUs\n mov r10d, eax\n mov r11d, edx\n pop rdx\n pop rcx\n pop rax\n mov [rcx + (_BackFromUserCode.SavedEFERLowEnd - 4 - _BackFromUserCode.SavedCr4End)], r10d\n mov [rcx + (_BackFromUserCode.SavedEFERHighEnd - 4 - _BackFromUserCode.SavedCr4End)], r11d\n mov rbp, cr4\n mov [rcx - 4], ebp ; save CR4 in _BackFromUserCode.SavedCr4End - 4\n xor ebp, ebp ; zero out CR4\n push rax ; save CR0 value (0x10)\n mov rax, cr3\n mov [rcx + (_BackFromUserCode.SavedCr3End - 4 - _BackFromUserCode.SavedCr4End)], eax\n pop rax ; restore CR0 value\n lea edi, [rcx + (_TssSeg - _BackFromUserCode.SavedCr4End)]\n mov esi, r8d ; esi <- 16-bit stack segment\n push DATA32\n pop rdx ; rdx <- 32-bit data segment selector\n lgdt [rcx + (_16Gdtr - _BackFromUserCode.SavedCr4End)]\n mov ss, edx\n pushfq\n lea edx, [rdx + DATA16 - DATA32]\n lea r8, [REL .RetFromRealMode]\n push r8\n mov r8d, cs\n mov [rcx + (_BackFromUserCode.X64JmpEnd - 2 - _BackFromUserCode.SavedCr4End)], r8w\n mov [rcx + (_BackFromUserCode.SavedSpEnd - 8 - _BackFromUserCode.SavedCr4End)], rsp\n jmp dword far [rcx + (_EntryPoint - _BackFromUserCode.SavedCr4End)]\n.RetFromRealMode:\n popfq\n lgdt [rsp + 60h] ; restore protected mode GDTR\n lidt [rsp + 50h] ; restore protected mode IDTR\n lea eax, [rbp - IA32_REGS.size]\n pop gs\n pop fs\n pop rbx\n mov ss, ebx\n pop rbx\n mov es, ebx\n pop rbx\n mov ds, ebx\n\n pop rdi\n pop rsi\n pop rbx\n pop rbp\n\n ret\n" }, { "path": "src/bios_proxy.c", "content": "/*\n * BIOS Proxy Helper Core Support\n *\n * Starts a dedicated CPU core to handle BIOS calls when the main core\n * is running in V86 mode (under EMM386). The helper core stays in\n * protected mode and can execute call32 normally.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Must match the signature in SeaBIOS stacks.c so it can find the mailbox. */\n#define BIOS_PROXY_SIGNATURE 0x79787250504D5343ULL /* \"CSMPPrxy\" */\n\n/* Authoritative size of the helper core's stack. SeaBIOS does not allocate\n * or switch stacks for the helper - it runs every dispatched func_ptr (reset\n * path, V86 BIOS handlers via call32_proxy, etc.) on this exact buffer - so\n * this has to be deep enough for the worst-case proxied call chain. */\n#define HELPER_STACK_SIZE 32768\n\nstruct bios_proxy_mailbox {\n uint64_t signature;\n volatile uint32_t request_pending;\n uint32_t func_ptr;\n uint32_t arg_eax;\n uint32_t arg_edx;\n uint32_t arg_ecx;\n uint32_t result;\n uint32_t helper_core_id;\n /* UEFI reset callback fields (populated by CSMWrap) */\n uint32_t reset_cr3;\n uint32_t reset_fn_lo;\n uint32_t reset_fn_hi;\n};\n\n/* Separately allocated stack for helper core */\nstatic uint8_t *helper_stack_buffer = NULL;\n\n/* Local APIC register offsets (xAPIC MMIO mode) */\n#define LAPIC_ID 0x020\n#define LAPIC_ICR_LOW 0x300\n#define LAPIC_ICR_HIGH 0x310\n\n/* APIC MSRs */\n#define IA32_APIC_BASE_MSR 0x1B\n#define APIC_BASE_ADDR_MASK 0xFFFFFFFFFFFFF000ULL /* Bits 12-51 contain base address */\n#define APIC_BASE_EXTD (1 << 10) /* x2APIC mode enabled */\n\n/* x2APIC MSRs */\n#define X2APIC_ICR 0x830\n#define X2APIC_ID 0x802\n\n/* Get the LAPIC base address from IA32_APIC_BASE MSR */\nstatic uintptr_t get_lapic_base(void)\n{\n return (uintptr_t)(rdmsr(IA32_APIC_BASE_MSR) & APIC_BASE_ADDR_MASK);\n}\n\n/* AP trampoline will be placed here */\n#define AP_TRAMPOLINE_ADDR 0x7000\n#define AP_TRAMPOLINE_VECTOR 0x07 /* SIPI vector = addr / 0x1000 */\n\nstatic struct bios_proxy_mailbox *mailbox = NULL;\nstatic uintptr_t mailbox_offset = 0;\nstatic int selected_ap_id = -1;\nstatic uint64_t reset_cr3_value = 0;\n\n/*\n * Build minimal identity-mapping page tables for the 64-bit reset path.\n * Maps the first 4GB using 2MB pages (works on all x86-64 CPUs).\n *\n * Layout (6 pages = 24KB):\n * Page 0: PML4 (1 entry → PDPT)\n * Page 1: PDPT (4 entries → PD[0..3])\n * Pages 2-5: PD[0..3] (512 × 2MB entries each = 1GB per PD)\n */\n#define PT_P (1ULL << 0) /* Present */\n#define PT_RW (1ULL << 1) /* Read/Write */\n#define PT_PS (1ULL << 7) /* Page Size (2MB) */\n#define RESET_PT_PAGES 6\n\nstatic int build_reset_page_tables(void)\n{\n EFI_PHYSICAL_ADDRESS pt_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiRuntimeServicesData,\n RESET_PT_PAGES,\n &pt_addr\n );\n if (EFI_ERROR(status)) {\n printf(\"Failed to allocate reset page tables\\n\");\n return -1;\n }\n\n memset((void *)(uintptr_t)pt_addr, 0, RESET_PT_PAGES * 4096);\n\n uint64_t *pml4 = (uint64_t *)(uintptr_t)pt_addr;\n uint64_t *pdpt = (uint64_t *)(uintptr_t)(pt_addr + 0x1000);\n\n /* PML4[0] → PDPT */\n pml4[0] = (pt_addr + 0x1000) | PT_P | PT_RW;\n\n /* PDPT[0..3] → PD[0..3], each covering 1GB */\n for (int i = 0; i < 4; i++) {\n uint64_t pd_phys = pt_addr + 0x2000 + (uint64_t)i * 0x1000;\n pdpt[i] = pd_phys | PT_P | PT_RW;\n\n /* Fill PD with 512 × 2MB identity-mapped pages */\n uint64_t *pd = (uint64_t *)(uintptr_t)pd_phys;\n for (int j = 0; j < 512; j++) {\n uint64_t phys = ((uint64_t)i * 512 + j) * 0x200000ULL;\n pd[j] = phys | PT_P | PT_RW | PT_PS;\n }\n }\n\n reset_cr3_value = pt_addr;\n printf(\"Reset page tables at %p (4GB identity map, 2MB pages)\\n\",\n (void *)(uintptr_t)pt_addr);\n return 0;\n}\n\n/* Detect if running in x2APIC mode */\nstatic int is_x2apic_mode(void)\n{\n uint64_t apic_base = rdmsr(IA32_APIC_BASE_MSR);\n return (apic_base & APIC_BASE_EXTD) != 0;\n}\n\n/*\n * Find the BIOS proxy mailbox in the CSM binary by scanning for signature.\n */\nstatic uintptr_t find_proxy_mailbox(void *csm_base, size_t csm_size)\n{\n uint64_t *ptr = (uint64_t *)csm_base;\n uint64_t *end = (uint64_t *)((uint8_t *)csm_base + csm_size - sizeof(struct bios_proxy_mailbox));\n\n while (ptr < end) {\n if (*ptr == BIOS_PROXY_SIGNATURE) {\n return (uintptr_t)ptr - (uintptr_t)csm_base;\n }\n ptr++;\n }\n return 0;\n}\n\n/* Signature before 16-bit helper entry: \"PRXY16EP\" */\n#define HELPER_16_ENTRY_SIGNATURE 0x5045363159585250ULL\n\n/*\n * Find the bios_proxy_helper_16_entry in the CSM binary by scanning for signature.\n * Returns the linear address of the entry point.\n */\nstatic uint32_t find_helper_16_entry(void *csm_base, size_t csm_size, uintptr_t final_base)\n{\n /* Signature is 8-byte aligned in romlayout.S */\n uint64_t *base = (uint64_t *)csm_base;\n uint64_t *end = (uint64_t *)((uint8_t *)csm_base + csm_size - 16);\n\n for (uint64_t *ptr = base; ptr < end; ptr++) {\n if (*ptr == HELPER_16_ENTRY_SIGNATURE) {\n uint32_t offset_in_binary = ((uint8_t *)ptr - (uint8_t *)csm_base) + 8; /* Skip signature */\n return (uint32_t)final_base + offset_in_binary;\n }\n }\n return 0;\n}\n\n/* Trampoline from assembly file */\nextern uint8_t ap_trampoline_start[];\nextern uint32_t ap_trampoline_size_value;\nextern uint32_t ap_trampoline_mailbox_offset;\nextern uint32_t ap_trampoline_stack_offset;\nextern uint32_t ap_trampoline_target16_offset;\nextern uint32_t ap_trampoline_helper_ready_offset;\n\n/*\n * Create AP trampoline code at AP_TRAMPOLINE_ADDR\n * target16_addr is a linear address which will be converted to segment:offset\n */\nstatic void create_ap_trampoline(uint32_t target16_addr, uint32_t mailbox_addr, uint32_t stack_top)\n{\n uint8_t *tramp = (uint8_t *)AP_TRAMPOLINE_ADDR;\n uint32_t size = ap_trampoline_size_value;\n\n /* Convert linear address to segment:offset for far jump\n * SeaBIOS is at 0xF0000 and expects CS=0xF000 (uses %cs: prefix for data access)\n */\n uint16_t target_segment = 0xF000;\n uint16_t target_offset = (uint16_t)(target16_addr - 0xF0000);\n\n memcpy(tramp, ap_trampoline_start, size);\n *(uint32_t *)(tramp + ap_trampoline_mailbox_offset) = mailbox_addr;\n *(uint32_t *)(tramp + ap_trampoline_stack_offset) = stack_top;\n /* Far pointer: offset first, then segment (little-endian) */\n *(uint16_t *)(tramp + ap_trampoline_target16_offset) = target_offset;\n *(uint16_t *)(tramp + ap_trampoline_target16_offset + 2) = target_segment;\n}\n\n/*\n * Wait for ICR delivery to complete (xAPIC mode only)\n */\nstatic void wait_icr_idle_xapic(uintptr_t lapic_base)\n{\n volatile uint32_t *icr_low = (volatile uint32_t *)(lapic_base + LAPIC_ICR_LOW);\n int count = 0;\n while (*icr_low & (1 << 12)) {\n asm volatile (\"pause\");\n if (++count > 1000000) return;\n }\n}\n\n/*\n * Send INIT-SIPI sequence (xAPIC MMIO mode)\n */\nstatic void start_ap_xapic(uint32_t apic_id)\n{\n uintptr_t lapic_base = get_lapic_base();\n volatile uint32_t *icr_high = (volatile uint32_t *)(lapic_base + LAPIC_ICR_HIGH);\n volatile uint32_t *icr_low = (volatile uint32_t *)(lapic_base + LAPIC_ICR_LOW);\n uint32_t dest = (apic_id & 0xFF) << 24; /* xAPIC physical destination is 8-bit */\n\n wait_icr_idle_xapic(lapic_base);\n *icr_high = dest;\n *icr_low = 0x4500; /* INIT */\n stall(10000);\n wait_icr_idle_xapic(lapic_base);\n\n *icr_high = dest;\n *icr_low = 0x4600 | AP_TRAMPOLINE_VECTOR; /* SIPI */\n stall(200);\n wait_icr_idle_xapic(lapic_base);\n\n *icr_high = dest;\n *icr_low = 0x4600 | AP_TRAMPOLINE_VECTOR; /* SIPI (retry) */\n wait_icr_idle_xapic(lapic_base);\n}\n\n/*\n * Send INIT-SIPI sequence (x2APIC MSR mode)\n */\nstatic void start_ap_x2apic(uint32_t apic_id)\n{\n wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4500); /* INIT */\n stall(10000);\n wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4600 | AP_TRAMPOLINE_VECTOR); /* SIPI */\n stall(200);\n wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4600 | AP_TRAMPOLINE_VECTOR); /* SIPI (retry) */\n}\n\nstatic void start_ap(uint32_t apic_id)\n{\n if (is_x2apic_mode()) {\n start_ap_x2apic(apic_id);\n } else {\n start_ap_xapic(apic_id);\n }\n}\n\nstatic uint32_t get_bsp_apic_id(void)\n{\n if (is_x2apic_mode()) {\n return (uint32_t)rdmsr(X2APIC_ID);\n }\n uintptr_t lapic_base = get_lapic_base();\n volatile uint32_t *lapic_id_reg = (volatile uint32_t *)(lapic_base + LAPIC_ID);\n return (*lapic_id_reg >> 24) & 0xFF;\n}\n\n/*\n * Walk the MADT and check if the given APIC ID names an enabled AP that\n * we can deliver INIT-SIPI to (i.e. xAPIC-addressable: id < 0xFF).\n */\nstatic bool madt_apic_id_is_valid_ap(uint32_t apic_id, uint32_t bsp_id)\n{\n if (apic_id == bsp_id || apic_id >= 0xFF)\n return false;\n\n struct uacpi_table madt_table;\n if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table)\n != UACPI_STATUS_OK) {\n return false;\n }\n\n struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;\n uint8_t *entry = (uint8_t *)(madt + 1);\n uint8_t *end = (uint8_t *)madt + madt->hdr.length;\n bool ok = false;\n\n while (entry < end) {\n uint8_t type = entry[0];\n uint8_t len = entry[1];\n if (len < 2) break;\n\n if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {\n struct acpi_madt_lapic *lapic = (struct acpi_madt_lapic *)entry;\n if (lapic->id == apic_id && (lapic->flags & ACPI_PIC_ENABLED)) {\n ok = true;\n break;\n }\n } else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {\n struct acpi_madt_x2apic *x2apic = (struct acpi_madt_x2apic *)entry;\n if (x2apic->id == apic_id && (x2apic->flags & ACPI_PIC_ENABLED)) {\n ok = true;\n break;\n }\n }\n entry += len;\n }\n\n uacpi_table_unref(&madt_table);\n return ok;\n}\n\n/*\n * Find an available AP to use as the system thread by parsing the MADT.\n *\n * If the user has pinned a specific APIC ID via the 'system_thread' config\n * key, validate and use that. Otherwise, return the highest APIC ID AP so\n * the system thread is least likely to be the one the OS would use first.\n */\nstatic int find_available_ap(void)\n{\n uint32_t bsp_id = get_bsp_apic_id();\n\n if (gConfig.system_thread_specified) {\n uint32_t want = gConfig.system_thread_apic_id;\n if (!madt_apic_id_is_valid_ap(want, bsp_id)) {\n printf(\"BIOS proxy: configured system_thread APIC ID %u is not \"\n \"a usable AP (must be enabled, not BSP %u, and < 0xFF)\\n\",\n want, bsp_id);\n return -1;\n }\n printf(\"BIOS proxy: using configured system thread (APIC ID %u)\\n\",\n want);\n return (int)want;\n }\n\n struct uacpi_table madt_table;\n if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table) != UACPI_STATUS_OK) {\n return -1;\n }\n\n struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;\n uint8_t *entry = (uint8_t *)(madt + 1);\n uint8_t *end = (uint8_t *)madt + madt->hdr.length;\n\n int highest_ap_id = -1;\n\n while (entry < end) {\n uint8_t type = entry[0];\n uint8_t len = entry[1];\n if (len < 2) break;\n\n if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {\n struct acpi_madt_lapic *lapic = (struct acpi_madt_lapic *)entry;\n if ((lapic->flags & 0x3) && lapic->id != bsp_id) {\n if (lapic->id > highest_ap_id) highest_ap_id = lapic->id;\n }\n } else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {\n struct acpi_madt_x2apic *x2apic = (struct acpi_madt_x2apic *)entry;\n /* Only consider APs with xAPIC-addressable IDs (<255) so we can\n deliver INIT-SIPI; ID 0xFF is broadcast in physical dest mode */\n if ((x2apic->flags & 0x3) && x2apic->id != bsp_id && x2apic->id < 0xFF) {\n if ((int)x2apic->id > highest_ap_id) highest_ap_id = x2apic->id;\n }\n }\n entry += len;\n }\n\n uacpi_table_unref(&madt_table);\n return highest_ap_id;\n}\n\n/*\n * Compute ACPI table checksum (sum of all bytes must be 0)\n */\nstatic uint8_t acpi_checksum(void *data, size_t len)\n{\n uint8_t sum = 0;\n uint8_t *p = (uint8_t *)data;\n for (size_t i = 0; i < len; i++) {\n sum += p[i];\n }\n return sum;\n}\n\nstatic void acpi_fix_checksum(struct acpi_sdt_hdr *hdr)\n{\n hdr->checksum = 0;\n hdr->checksum = -acpi_checksum(hdr, hdr->length);\n}\n\n/* Pointers to allocated patched tables */\nstatic void *patched_madt = NULL;\nstatic void *patched_rsdt = NULL;\nstatic void *patched_xsdt = NULL;\n\n/*\n * Decide whether a CPU MADT entry should appear in the OS-visible MADT.\n *\n * - The system thread (helper core) is always hidden.\n * - The BSP is always kept (we run on it; the OS must see it).\n * - Otherwise the user-configured allow/block list decides.\n */\nstatic bool cpu_visible_to_os(uint32_t apic_id, uint32_t bsp_id,\n int helper_apic_id)\n{\n if (helper_apic_id >= 0 && apic_id == (uint32_t)helper_apic_id)\n return false;\n if (apic_id == bsp_id)\n return true;\n return config_cpu_in_filter(apic_id);\n}\n\n/*\n * Create a patched MADT with the helper core entry removed and any CPUs\n * filtered out by the user's cpu_allowlist / cpu_blocklist also removed.\n * Returns the new MADT or NULL on failure.\n */\nstatic struct acpi_madt *create_patched_madt(int helper_apic_id)\n{\n struct uacpi_table madt_table;\n if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table) != UACPI_STATUS_OK) {\n return NULL;\n }\n\n struct acpi_madt *orig_madt = (struct acpi_madt *)madt_table.virt_addr;\n uint32_t orig_len = orig_madt->hdr.length;\n uint32_t bsp_id = get_bsp_apic_id();\n\n /* First pass: find entries to remove and calculate new size */\n uint8_t *entry = (uint8_t *)(orig_madt + 1);\n uint8_t *end = (uint8_t *)orig_madt + orig_len;\n uint32_t removed_bytes = 0;\n uint32_t removed_count = 0;\n bool found_helper = false;\n\n while (entry < end) {\n uint8_t type = entry[0];\n uint8_t len = entry[1];\n if (len < 2) break;\n\n uint32_t cpu_id;\n bool is_cpu = false;\n if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {\n cpu_id = ((struct acpi_madt_lapic *)entry)->id;\n is_cpu = true;\n } else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {\n cpu_id = ((struct acpi_madt_x2apic *)entry)->id;\n is_cpu = true;\n }\n\n if (is_cpu) {\n if (helper_apic_id >= 0 && cpu_id == (uint32_t)helper_apic_id)\n found_helper = true;\n if (!cpu_visible_to_os(cpu_id, bsp_id, helper_apic_id)) {\n removed_bytes += len;\n removed_count++;\n }\n }\n entry += len;\n }\n\n if (helper_apic_id >= 0 && !found_helper) {\n printf(\"Warning: helper core APIC ID %d not found in MADT\\n\", helper_apic_id);\n uacpi_table_unref(&madt_table);\n return NULL;\n }\n\n /* Allocate new MADT (must be < 4GB for legacy OS) */\n uint32_t new_len = orig_len - removed_bytes;\n EFI_PHYSICAL_ADDRESS new_madt_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiACPIReclaimMemory,\n (new_len + 4095) / 4096,\n &new_madt_addr\n );\n if (EFI_ERROR(status)) {\n printf(\"Failed to allocate memory for patched MADT\\n\");\n uacpi_table_unref(&madt_table);\n return NULL;\n }\n\n struct acpi_madt *new_madt = (struct acpi_madt *)(uintptr_t)new_madt_addr;\n\n /* Copy MADT header */\n memcpy(new_madt, orig_madt, sizeof(struct acpi_madt));\n\n /* Copy entries, skipping helper core and any filtered-out CPUs */\n uint8_t *dst = (uint8_t *)(new_madt + 1);\n entry = (uint8_t *)(orig_madt + 1);\n\n while (entry < end) {\n uint8_t type = entry[0];\n uint8_t len = entry[1];\n if (len < 2) break;\n\n bool skip = false;\n if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {\n uint32_t id = ((struct acpi_madt_lapic *)entry)->id;\n if (!cpu_visible_to_os(id, bsp_id, helper_apic_id))\n skip = true;\n } else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {\n uint32_t id = ((struct acpi_madt_x2apic *)entry)->id;\n if (!cpu_visible_to_os(id, bsp_id, helper_apic_id))\n skip = true;\n }\n\n if (!skip) {\n memcpy(dst, entry, len);\n dst += len;\n }\n entry += len;\n }\n\n /* Update header */\n new_madt->hdr.length = new_len;\n acpi_fix_checksum(&new_madt->hdr);\n\n uacpi_table_unref(&madt_table);\n printf(\"Created patched MADT at %p (removed %u CPU entries, \"\n \"system thread APIC ID %d)\\n\",\n (void *)new_madt, removed_count, helper_apic_id);\n return new_madt;\n}\n\n/*\n * Create patched RSDT with updated MADT pointer.\n */\nstatic struct acpi_rsdt *create_patched_rsdt(struct acpi_rsdp *rsdp, uintptr_t new_madt_addr)\n{\n if (!rsdp->rsdt_addr) {\n return NULL;\n }\n\n struct acpi_rsdt *orig_rsdt = (struct acpi_rsdt *)(uintptr_t)rsdp->rsdt_addr;\n uint32_t len = orig_rsdt->hdr.length;\n size_t num_entries = (len - sizeof(struct acpi_sdt_hdr)) / sizeof(uint32_t);\n\n /* Allocate new RSDT */\n EFI_PHYSICAL_ADDRESS new_rsdt_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiACPIReclaimMemory,\n (len + 4095) / 4096,\n &new_rsdt_addr\n );\n if (EFI_ERROR(status)) {\n printf(\"Failed to allocate memory for patched RSDT\\n\");\n return NULL;\n }\n\n struct acpi_rsdt *new_rsdt = (struct acpi_rsdt *)(uintptr_t)new_rsdt_addr;\n memcpy(new_rsdt, orig_rsdt, len);\n\n /* Find and update all MADT entries (some firmware lists it more than once) */\n for (size_t i = 0; i < num_entries; i++) {\n struct acpi_sdt_hdr *hdr = (struct acpi_sdt_hdr *)(uintptr_t)new_rsdt->entries[i];\n if (hdr && memcmp(hdr->signature, ACPI_MADT_SIGNATURE, 4) == 0) {\n new_rsdt->entries[i] = (uint32_t)new_madt_addr;\n }\n }\n\n acpi_fix_checksum(&new_rsdt->hdr);\n printf(\"Created patched RSDT at %p\\n\", (void *)new_rsdt);\n return new_rsdt;\n}\n\n/*\n * Create patched XSDT with updated MADT pointer.\n */\nstatic struct acpi_xsdt *create_patched_xsdt(struct acpi_rsdp *rsdp, uintptr_t new_madt_addr)\n{\n if (rsdp->revision < 2 || !rsdp->xsdt_addr) {\n return NULL;\n }\n\n struct acpi_xsdt *orig_xsdt = (struct acpi_xsdt *)(uintptr_t)rsdp->xsdt_addr;\n uint32_t len = orig_xsdt->hdr.length;\n size_t num_entries = (len - sizeof(struct acpi_sdt_hdr)) / sizeof(uint64_t);\n\n /* Allocate new XSDT */\n EFI_PHYSICAL_ADDRESS new_xsdt_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiACPIReclaimMemory,\n (len + 4095) / 4096,\n &new_xsdt_addr\n );\n if (EFI_ERROR(status)) {\n printf(\"Failed to allocate memory for patched XSDT\\n\");\n return NULL;\n }\n\n struct acpi_xsdt *new_xsdt = (struct acpi_xsdt *)(uintptr_t)new_xsdt_addr;\n memcpy(new_xsdt, orig_xsdt, len);\n\n /* Find and update all MADT entries (some firmware lists it more than once) */\n for (size_t i = 0; i < num_entries; i++) {\n struct acpi_sdt_hdr *hdr = (struct acpi_sdt_hdr *)(uintptr_t)new_xsdt->entries[i];\n if (hdr && memcmp(hdr->signature, ACPI_MADT_SIGNATURE, 4) == 0) {\n new_xsdt->entries[i] = (uint64_t)new_madt_addr;\n }\n }\n\n acpi_fix_checksum(&new_xsdt->hdr);\n printf(\"Created patched XSDT at %p\\n\", (void *)new_xsdt);\n return new_xsdt;\n}\n\n/*\n * Patch ACPI tables to hide the helper core from the OS.\n * Updates the RSDP copy in CSM region to point to patched tables.\n */\nstatic int patch_acpi_hide_helper(void *rsdp_copy, int helper_apic_id)\n{\n extern uintptr_t g_rsdp; /* Original RSDP from acpi.c */\n\n if (!g_rsdp) {\n printf(\"No RSDP available for MADT patching\\n\");\n return -1;\n }\n\n struct acpi_rsdp *orig_rsdp = (struct acpi_rsdp *)g_rsdp;\n struct acpi_rsdp *copy_rsdp = (struct acpi_rsdp *)rsdp_copy;\n\n /* Create patched MADT */\n struct acpi_madt *new_madt = create_patched_madt(helper_apic_id);\n if (!new_madt) {\n return -1;\n }\n patched_madt = new_madt;\n\n /* Create patched RSDT */\n struct acpi_rsdt *new_rsdt = create_patched_rsdt(orig_rsdp, (uintptr_t)new_madt);\n if (new_rsdt) {\n patched_rsdt = new_rsdt;\n copy_rsdp->rsdt_addr = (uint32_t)(uintptr_t)new_rsdt;\n }\n\n /* Create patched XSDT (if ACPI 2.0+) */\n struct acpi_xsdt *new_xsdt = create_patched_xsdt(orig_rsdp, (uintptr_t)new_madt);\n if (new_xsdt) {\n patched_xsdt = new_xsdt;\n copy_rsdp->xsdt_addr = (uint64_t)(uintptr_t)new_xsdt;\n }\n\n /* Fix RSDP checksums */\n copy_rsdp->checksum = 0;\n copy_rsdp->checksum = -acpi_checksum(copy_rsdp, 20); /* First 20 bytes for ACPI 1.0 */\n\n if (copy_rsdp->revision >= 2) {\n copy_rsdp->extended_checksum = 0;\n copy_rsdp->extended_checksum = -acpi_checksum(copy_rsdp, copy_rsdp->length);\n }\n\n printf(\"ACPI tables patched to hide helper core (APIC ID %d)\\n\", helper_apic_id);\n return 0;\n}\n\nstatic void *saved_csm_base = NULL;\nstatic size_t saved_csm_size = 0;\nstatic void *saved_rsdp_copy = NULL;\n\n/*\n * Initialize the BIOS proxy helper core.\n * Call after CSM binary is loaded but before ExitBootServices.\n *\n * Parameters:\n * csm_base - Pointer to the loaded CSM binary\n * csm_size - Size of the CSM binary\n * rsdp_copy - Pointer to the RSDP copy in CSM region (for MADT patching)\n */\nint bios_proxy_init(void *csm_base, size_t csm_size, void *rsdp_copy)\n{\n printf(\"Initializing BIOS proxy helper core...\\n\");\n\n saved_csm_base = csm_base;\n saved_csm_size = csm_size;\n saved_rsdp_copy = rsdp_copy;\n\n mailbox_offset = find_proxy_mailbox(csm_base, csm_size);\n if (!mailbox_offset) {\n printf(\"BIOS proxy mailbox not found\\n\");\n return -1;\n }\n\n selected_ap_id = find_available_ap();\n if (selected_ap_id < 0) {\n printf(\"No AP available for BIOS proxy\\n\");\n return -1;\n }\n\n /* Patch ACPI tables to hide the helper core from the OS */\n if (rsdp_copy) {\n if (patch_acpi_hide_helper(rsdp_copy, selected_ap_id) < 0) {\n printf(\"Warning: Failed to patch MADT, OS may see helper core\\n\");\n /* Continue anyway - helper will still work */\n }\n }\n\n /* Build identity-mapping page tables for the 64-bit reset path */\n if (build_reset_page_tables() < 0) {\n printf(\"Warning: UEFI reset callback will not be available\\n\");\n }\n\n /* Allocate stack for helper core (must be < 4GB) */\n EFI_PHYSICAL_ADDRESS stack_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiRuntimeServicesData,\n (HELPER_STACK_SIZE + 4095) / 4096,\n &stack_addr\n );\n if (EFI_ERROR(status)) {\n printf(\"Failed to allocate helper stack\\n\");\n return -1;\n }\n helper_stack_buffer = (uint8_t *)(uintptr_t)stack_addr;\n\n printf(\"BIOS proxy ready (AP %d)\\n\", selected_ap_id);\n return 0;\n}\n\n/*\n * Start the helper core.\n * Call after ExitBootServices.\n */\nint bios_proxy_start_helper(uintptr_t csm_final_base)\n{\n if (!mailbox_offset || !saved_csm_base || selected_ap_id < 0) {\n return -1;\n }\n\n uint32_t target16_addr = find_helper_16_entry(saved_csm_base, saved_csm_size, csm_final_base);\n if (!target16_addr) {\n return -1;\n }\n\n mailbox = (struct bios_proxy_mailbox *)(csm_final_base + mailbox_offset);\n\n /* Populate UEFI reset callback fields in the mailbox */\n if (reset_cr3_value && gRT && gRT->ResetSystem) {\n uint64_t fn = (uint64_t)(uintptr_t)gRT->ResetSystem;\n mailbox->reset_cr3 = (uint32_t)reset_cr3_value;\n mailbox->reset_fn_lo = (uint32_t)fn;\n mailbox->reset_fn_hi = (uint32_t)(fn >> 32);\n printf(\"UEFI ResetSystem callback at %p (CR3=%p)\\n\",\n (void *)(uintptr_t)fn, (void *)(uintptr_t)reset_cr3_value);\n } else {\n mailbox->reset_cr3 = 0;\n mailbox->reset_fn_lo = 0;\n mailbox->reset_fn_hi = 0;\n printf(\"Warning: UEFI ResetSystem callback not available\\n\");\n }\n\n if (!helper_stack_buffer) {\n return -1;\n }\n uint32_t stack_top = (uint32_t)(uintptr_t)(helper_stack_buffer + HELPER_STACK_SIZE);\n\n create_ap_trampoline(target16_addr, (uint32_t)(uintptr_t)mailbox, stack_top);\n\n start_ap(selected_ap_id);\n\n /* Wait for helper to signal ready */\n volatile uint32_t *helper_ready = (volatile uint32_t *)(uintptr_t)(AP_TRAMPOLINE_ADDR + ap_trampoline_helper_ready_offset);\n for (int timeout = 0; timeout < 100; timeout++) {\n asm volatile (\"\" ::: \"memory\");\n if (*helper_ready) {\n return 0;\n }\n stall(10000);\n }\n\n return -1;\n}\n\n/*\n * Get the APIC ID of the helper core.\n * Returns -1 if no helper core has been selected.\n */\nint bios_proxy_get_helper_apic_id(void)\n{\n return selected_ap_id;\n}\n" }, { "path": "src/bios_proxy.h", "content": "/*\n * BIOS Proxy Helper Core Support\n *\n * Provides a dedicated CPU core to handle BIOS calls when the main core\n * is running in V86 mode (under EMM386).\n */\n\n#ifndef _BIOS_PROXY_H\n#define _BIOS_PROXY_H\n\n#include \n#include \n\n/*\n * Initialize the BIOS proxy helper core.\n * Call this after CSM binary is loaded but before Legacy16Boot.\n *\n * @param csm_base Base address of the loaded CSM binary\n * @param csm_size Size of the CSM binary in bytes\n * @param rsdp_copy Pointer to the RSDP copy in CSM region (for MADT patching)\n * If NULL, MADT patching is skipped.\n * @return 0 on success, -1 on failure\n */\nint bios_proxy_init(void *csm_base, size_t csm_size, void *rsdp_copy);\n\n/*\n * Start the helper core.\n * Call this after ExitBootServices when we have full control of the system,\n * and after the CSM binary has been copied to its final location.\n *\n * @param csm_final_base The address where the CSM binary was copied to\n * @return 0 on success, -1 on failure\n */\nint bios_proxy_start_helper(uintptr_t csm_final_base);\n\n/*\n * Get the APIC ID of the helper core.\n * Returns -1 if no helper core has been selected.\n * Used by mptable generation to exclude the helper from MP tables.\n */\nint bios_proxy_get_helper_apic_id(void);\n\n#endif /* _BIOS_PROXY_H */\n" }, { "path": "src/bootdev.c", "content": "#include \n#include \n#include \n#include \n\n/*\n * Boot device detection and BBS table building for CSMWrap\n *\n * This module detects which drive CSMWrap was booted from and creates\n * a BBS table that prioritizes that drive for SeaBIOS boot order.\n */\n\n/*\n * Parse device path to extract boot device information\n */\nstatic bool parse_device_path(EFI_DEVICE_PATH_PROTOCOL *device_path,\n struct boot_device_info *info)\n{\n EFI_DEVICE_PATH_PROTOCOL *node;\n bool found_pci = false;\n\n if (!device_path || !info) {\n return false;\n }\n\n memset(info, 0, sizeof(*info));\n info->device_type = BBS_HARDDISK; /* Default to hard disk */\n\n /* Walk the device path to extract information */\n for (node = device_path; !IsDevicePathEnd(node); node = NextDevicePathNode(node)) {\n uint8_t type = DevicePathType(node);\n uint8_t subtype = DevicePathSubType(node);\n\n switch (type) {\n case HARDWARE_DEVICE_PATH:\n if (subtype == HW_PCI_DP) {\n PCI_DEVICE_PATH *pci = (PCI_DEVICE_PATH *)node;\n info->bus = 0; /* Will be updated if we find ACPI path first */\n info->device = pci->Device;\n info->function = pci->Function;\n found_pci = true;\n }\n break;\n\n case MESSAGING_DEVICE_PATH:\n switch (subtype) {\n case MSG_SATA_DP:\n {\n SATA_DEVICE_PATH *sata = (SATA_DEVICE_PATH *)node;\n info->sata_port = sata->HBAPortNumber;\n info->device_type = BBS_HARDDISK;\n }\n break;\n case MSG_USB_DP:\n info->is_usb = true;\n info->device_type = BBS_USB;\n break;\n case MSG_ATAPI_DP:\n {\n ATAPI_DEVICE_PATH *atapi = (ATAPI_DEVICE_PATH *)node;\n /* Check if this is a CD-ROM based on typical ATAPI usage */\n (void)atapi; /* May use later for more specific detection */\n }\n break;\n case MSG_SCSI_DP:\n info->device_type = BBS_HARDDISK;\n break;\n }\n break;\n\n case MEDIA_DEVICE_PATH:\n switch (subtype) {\n case MEDIA_HARDDRIVE_DP:\n info->device_type = BBS_HARDDISK;\n break;\n case MEDIA_CDROM_DP:\n info->device_type = BBS_CDROM;\n break;\n }\n break;\n }\n }\n\n info->valid = found_pci;\n return found_pci;\n}\n\n/*\n * Get PCI bus number by walking up to the PCI I/O protocol\n */\nstatic bool get_pci_location(EFI_HANDLE device_handle, struct boot_device_info *info)\n{\n EFI_STATUS status;\n EFI_GUID pci_io_guid = EFI_PCI_IO_PROTOCOL_GUID;\n EFI_GUID device_path_guid = EFI_DEVICE_PATH_PROTOCOL_GUID;\n EFI_DEVICE_PATH_PROTOCOL *device_path;\n EFI_PCI_IO_PROTOCOL *pci_io;\n EFI_HANDLE pci_handle;\n UINTN seg, bus, dev, func;\n\n /* First get the device path */\n status = gBS->HandleProtocol(device_handle, &device_path_guid,\n (void **)&device_path);\n if (EFI_ERROR(status) || !device_path) {\n printf(\"bootdev: Failed to get device path: %d\\n\", (int)status);\n return false;\n }\n\n /* Parse the device path for basic info */\n parse_device_path(device_path, info);\n\n /* Try to find PCI I/O protocol on this device path */\n status = gBS->LocateDevicePath(&pci_io_guid, &device_path, &pci_handle);\n if (EFI_ERROR(status)) {\n printf(\"bootdev: No PCI I/O on device path: %d\\n\", (int)status);\n return info->valid; /* Return what we got from device path parsing */\n }\n\n /* Get the PCI I/O protocol */\n status = gBS->HandleProtocol(pci_handle, &pci_io_guid, (void **)&pci_io);\n if (EFI_ERROR(status)) {\n printf(\"bootdev: Failed to get PCI I/O protocol: %d\\n\", (int)status);\n return info->valid;\n }\n\n /* Get the actual PCI location */\n status = pci_io->GetLocation(pci_io, &seg, &bus, &dev, &func);\n if (EFI_ERROR(status)) {\n printf(\"bootdev: Failed to get PCI location: %d\\n\", (int)status);\n return info->valid;\n }\n\n info->bus = (uint8_t)bus;\n info->device = (uint8_t)dev;\n info->function = (uint8_t)func;\n info->valid = true;\n\n /* Read PCI class code from config space offset 0x0B (class) and 0x0A (subclass) */\n uint8_t class_code[2];\n status = pci_io->Pci.Read(pci_io, EfiPciIoWidthUint8, 0x0A, 2, class_code);\n if (!EFI_ERROR(status)) {\n info->pci_subclass = class_code[0]; /* Offset 0x0A */\n info->pci_class = class_code[1]; /* Offset 0x0B */\n }\n\n printf(\"bootdev: PCI location %02x:%02x.%x class=%02x subclass=%02x\\n\",\n info->bus, info->device, info->function, info->pci_class, info->pci_subclass);\n\n return true;\n}\n\n/*\n * Check if two boot device info structures match (same controller)\n */\nstatic bool devices_match(const struct boot_device_info *a,\n const struct boot_device_info *b)\n{\n if (!a->valid || !b->valid) {\n return false;\n }\n\n return (a->bus == b->bus &&\n a->device == b->device &&\n a->function == b->function);\n}\n\n/*\n * Get device type string for debug output\n */\nstatic const char *device_type_str(uint16_t type)\n{\n switch (type) {\n case BBS_FLOPPY: return \"Floppy\";\n case BBS_HARDDISK: return \"HDD\";\n case BBS_CDROM: return \"CDROM\";\n case BBS_PCMCIA: return \"PCMCIA\";\n case BBS_USB: return \"USB\";\n case BBS_EMBED_NETWORK: return \"Network\";\n default: return \"Unknown\";\n }\n}\n\n/*\n * Add a BBS entry for a block device\n *\n * priority: 0 = highest (boot device), 1+ = lower priority\n */\nstatic void add_bbs_entry(struct low_stub *low_stub,\n const struct boot_device_info *info,\n int priority)\n{\n BBS_TABLE *entry;\n char *desc;\n size_t idx;\n\n if (low_stub->bbs_entry_count >= MAX_BBS_ENTRIES) {\n printf(\"bootdev: BBS table full, skipping device\\n\");\n return;\n }\n\n idx = low_stub->bbs_entry_count;\n entry = &low_stub->bbs_entries[idx];\n desc = low_stub->bbs_desc_strings[idx];\n\n memset(entry, 0, sizeof(*entry));\n\n /* Set boot priority - 0 is highest, higher numbers = lower priority */\n entry->BootPriority = priority;\n\n /* PCI location */\n entry->Bus = info->bus;\n entry->Device = info->device;\n entry->Function = info->function;\n\n /* Device type */\n entry->DeviceType = info->device_type;\n\n /* PCI class codes - use actual values from device */\n entry->Class = info->pci_class;\n entry->SubClass = info->pci_subclass;\n\n /* Status flags - mark as enabled and media present */\n entry->StatusFlags.Enabled = 1;\n entry->StatusFlags.MediaPresent = 2; /* Media present and bootable */\n\n /* Description string - stored in low memory */\n if (priority == 0) {\n snprintf(desc, BBS_DESC_STRING_SIZE, \"Boot %s %02x:%02x.%x\",\n device_type_str(info->device_type),\n info->bus, info->device, info->function);\n } else {\n snprintf(desc, BBS_DESC_STRING_SIZE, \"%s %02x:%02x.%x\",\n device_type_str(info->device_type),\n info->bus, info->device, info->function);\n }\n\n /* Set description string pointer (segment:offset for real mode) */\n uintptr_t desc_addr = (uintptr_t)desc;\n entry->DescStringSegment = EFI_SEGMENT(desc_addr);\n entry->DescStringOffset = EFI_OFFSET(desc_addr);\n\n printf(\"bootdev: BBS[%zu] %s pri=%d\\n\", idx, desc, entry->BootPriority);\n\n low_stub->bbs_entry_count++;\n}\n\n/*\n * Enumerate block I/O devices and build BBS entries\n */\nstatic int enumerate_block_devices(struct low_stub *low_stub,\n const struct boot_device_info *boot_info)\n{\n EFI_STATUS status;\n EFI_GUID block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;\n EFI_HANDLE *handles = NULL;\n UINTN handle_count = 0;\n int next_priority = 1; /* Priority 0 reserved for boot device */\n\n /* Find all block I/O devices */\n status = gBS->LocateHandleBuffer(ByProtocol, &block_io_guid, NULL,\n &handle_count, &handles);\n if (EFI_ERROR(status)) {\n printf(\"bootdev: Failed to locate block devices: %d\\n\", (int)status);\n return -1;\n }\n\n printf(\"bootdev: Found %lu block devices\\n\", (unsigned long)handle_count);\n\n for (UINTN i = 0; i < handle_count; i++) {\n EFI_BLOCK_IO_PROTOCOL *block_io;\n struct boot_device_info dev_info;\n\n status = gBS->HandleProtocol(handles[i], &block_io_guid, (void **)&block_io);\n if (EFI_ERROR(status)) {\n continue;\n }\n\n /* Skip logical partitions, only want raw devices */\n if (block_io->Media->LogicalPartition) {\n continue;\n }\n\n /* Get PCI location for this device */\n if (!get_pci_location(handles[i], &dev_info)) {\n continue;\n }\n\n bool is_boot_device = boot_info->valid && devices_match(&dev_info, boot_info);\n int priority = is_boot_device ? 0 : next_priority++;\n\n add_bbs_entry(low_stub, &dev_info, priority);\n }\n\n gBS->FreePool(handles);\n\n return 0;\n}\n\n/*\n * Main entry point: build BBS table for SeaBIOS\n */\nint build_bbs_table(struct csmwrap_priv *priv, EFI_HANDLE image_handle)\n{\n EFI_STATUS status;\n EFI_GUID loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;\n EFI_LOADED_IMAGE_PROTOCOL *loaded_image = NULL;\n struct boot_device_info boot_info = {0};\n struct low_stub *low_stub = priv->low_stub;\n\n if (!low_stub) {\n printf(\"bootdev: low_stub not initialized\\n\");\n return -1;\n }\n\n printf(\"bootdev: Building BBS table...\\n\");\n\n /* Get loaded image protocol to find boot device */\n status = gBS->HandleProtocol(image_handle, &loaded_image_guid,\n (void **)&loaded_image);\n if (EFI_ERROR(status) || !loaded_image) {\n printf(\"bootdev: Failed to get loaded image: %d\\n\", (int)status);\n /* Continue without boot device info - will enumerate all devices */\n } else if (loaded_image->DeviceHandle) {\n /* Get boot device information */\n printf(\"bootdev: Detecting boot device...\\n\");\n if (get_pci_location(loaded_image->DeviceHandle, &boot_info)) {\n printf(\"bootdev: Boot device: PCI %02x:%02x.%x type=%s\\n\",\n boot_info.bus, boot_info.device, boot_info.function,\n device_type_str(boot_info.device_type));\n }\n }\n\n /* Reset BBS table */\n low_stub->bbs_entry_count = 0;\n memset(low_stub->bbs_entries, 0, sizeof(low_stub->bbs_entries));\n memset(low_stub->bbs_desc_strings, 0, sizeof(low_stub->bbs_desc_strings));\n\n /* Enumerate all block devices and build BBS entries */\n if (enumerate_block_devices(low_stub, &boot_info) < 0) {\n printf(\"bootdev: Failed to enumerate block devices\\n\");\n /* Not fatal - SeaBIOS can still enumerate drives itself */\n }\n\n /* Set up boot_table to point to our BBS table */\n if (low_stub->bbs_entry_count > 0) {\n low_stub->boot_table.NumberBbsEntries = low_stub->bbs_entry_count;\n low_stub->boot_table.BbsTable = (uintptr_t)low_stub->bbs_entries;\n printf(\"bootdev: BBS table built with %zu entries\\n\", low_stub->bbs_entry_count);\n } else {\n printf(\"bootdev: No BBS entries created\\n\");\n }\n\n return 0;\n}\n" }, { "path": "src/bootdev.h", "content": "#ifndef _BOOTDEV_H\n#define _BOOTDEV_H\n\n#include \n\n/* Forward declaration */\nstruct csmwrap_priv;\n\n/*\n * Boot device detection and BBS table building\n *\n * This module detects the boot device (the drive CSMWrap was loaded from)\n * and builds a BBS (BIOS Boot Specification) table for SeaBIOS with the\n * boot device prioritized first.\n */\n\n/* Boot device information extracted from device path */\nstruct boot_device_info {\n bool valid;\n uint8_t bus;\n uint8_t device;\n uint8_t function;\n uint8_t pci_class; /* PCI class code */\n uint8_t pci_subclass; /* PCI subclass code */\n uint16_t device_type; /* BBS_HARDDISK, BBS_CDROM, etc. */\n bool is_usb;\n uint16_t sata_port; /* SATA port number if applicable */\n};\n\n/*\n * Detect boot device and build BBS table\n *\n * This function:\n * 1. Parses the device path of the boot device to get PCI location\n * 2. Enumerates all block I/O devices\n * 3. Builds a BBS table with the boot device at highest priority\n *\n * @param priv CSMWrap private data structure (must have low_stub initialized)\n * @param image_handle EFI image handle (used to get loaded image info)\n * @return 0 on success, -1 on failure\n */\nint build_bbs_table(struct csmwrap_priv *priv, EFI_HANDLE image_handle);\n\n#endif /* _BOOTDEV_H */\n" }, { "path": "src/config.c", "content": "#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\nstruct csmwrap_config gConfig = {\n .serial_debug = false,\n .serial_port = 0x3f8,\n .serial_baud = 115200,\n .vgabios_path = {0},\n .iommu_disable = true,\n .verbose = false,\n .vga_specified = false,\n .vga_bus = 0,\n .vga_device = 0,\n .vga_function = 0,\n .system_thread_specified = false,\n .system_thread_apic_id = 0,\n .cpu_filter_mode = CPU_FILTER_NONE,\n .cpu_filter_list = NULL,\n .cpu_filter_count = 0,\n};\n\nbool config_cpu_in_filter(uint32_t apic_id)\n{\n if (gConfig.cpu_filter_mode == CPU_FILTER_NONE)\n return true;\n\n bool found = false;\n for (size_t i = 0; i < gConfig.cpu_filter_count; i++) {\n if (gConfig.cpu_filter_list[i] == apic_id) {\n found = true;\n break;\n }\n }\n\n if (gConfig.cpu_filter_mode == CPU_FILTER_ALLOWLIST)\n return found;\n /* CPU_FILTER_BLOCKLIST */\n return !found;\n}\n\nstatic bool char_eq_nocase(char a, char b)\n{\n if (a >= 'A' && a <= 'Z') a += 'a' - 'A';\n if (b >= 'A' && b <= 'Z') b += 'a' - 'A';\n return a == b;\n}\n\nstatic bool streq_nocase(const char *a, const char *b)\n{\n while (*a && *b) {\n if (!char_eq_nocase(*a, *b))\n return false;\n a++;\n b++;\n }\n return *a == *b;\n}\n\nstatic bool parse_bool(const char *val, bool *out)\n{\n if (streq_nocase(val, \"true\") || streq_nocase(val, \"yes\") || streq_nocase(val, \"1\")) {\n *out = true;\n return true;\n }\n if (streq_nocase(val, \"false\") || streq_nocase(val, \"no\") || streq_nocase(val, \"0\")) {\n *out = false;\n return true;\n }\n return false;\n}\n\nstatic bool parse_uint32(const char *val, uint32_t *out)\n{\n uint32_t result = 0;\n bool hex = false;\n\n if (val[0] == '0' && (val[1] == 'x' || val[1] == 'X')) {\n hex = true;\n val += 2;\n }\n\n if (*val == '\\0')\n return false;\n\n while (*val) {\n char c = *val;\n uint32_t digit;\n if (c >= '0' && c <= '9') {\n digit = c - '0';\n } else if (hex && c >= 'a' && c <= 'f') {\n digit = 10 + c - 'a';\n } else if (hex && c >= 'A' && c <= 'F') {\n digit = 10 + c - 'A';\n } else {\n return false;\n }\n result = result * (hex ? 16 : 10) + digit;\n val++;\n }\n\n *out = result;\n return true;\n}\n\nstatic bool parse_hex_byte(const char *s, size_t len, uint32_t *out)\n{\n if (len == 0)\n return false;\n\n uint32_t result = 0;\n for (size_t i = 0; i < len; i++) {\n char c = s[i];\n uint32_t digit;\n if (c >= '0' && c <= '9')\n digit = c - '0';\n else if (c >= 'a' && c <= 'f')\n digit = 10 + c - 'a';\n else if (c >= 'A' && c <= 'F')\n digit = 10 + c - 'A';\n else\n return false;\n result = result * 16 + digit;\n }\n *out = result;\n return true;\n}\n\n/*\n * Parse a single token (already null-terminated) of the form \"N\" or \"N-M\"\n * into either a single value or an inclusive range. Both N and M are\n * decimal or 0x-prefixed hex. Whitespace around the '-' is allowed.\n *\n * Returns false on malformed input or if N > M.\n */\nstatic bool parse_apic_id_token(char *tok, uint32_t *lo, uint32_t *hi)\n{\n char *dash = NULL;\n /* Skip a leading 0x prefix when scanning for '-' so we don't mistake\n * the hex digit sequence for a range delimiter (no negatives allowed). */\n char *scan = tok;\n if (scan[0] == '0' && (scan[1] == 'x' || scan[1] == 'X'))\n scan += 2;\n for (char *q = scan; *q; q++) {\n if (*q == '-') { dash = q; break; }\n }\n\n if (!dash) {\n uint32_t v;\n if (!parse_uint32(tok, &v))\n return false;\n *lo = *hi = v;\n return true;\n }\n\n /* Split into \"lo\" and \"hi\" halves, trimming whitespace around the dash. */\n char *lo_end = dash;\n while (lo_end > tok && (lo_end[-1] == ' ' || lo_end[-1] == '\\t'))\n lo_end--;\n char *hi_start = dash + 1;\n while (*hi_start == ' ' || *hi_start == '\\t')\n hi_start++;\n\n if (lo_end == tok || *hi_start == '\\0')\n return false;\n\n *lo_end = '\\0';\n\n uint32_t lo_v, hi_v;\n if (!parse_uint32(tok, &lo_v) || !parse_uint32(hi_start, &hi_v))\n return false;\n if (lo_v > hi_v)\n return false;\n\n *lo = lo_v;\n *hi = hi_v;\n return true;\n}\n\n/*\n * Parse a comma-separated list of APIC IDs.\n *\n * Each entry is either a single ID (decimal or 0x-prefixed hex) or an\n * inclusive range \"N-M\". Whitespace around commas and dashes is ignored.\n *\n * If out is non-NULL, expanded IDs are written to out[0 .. *out_count - 1]\n * and parsing fails if more than out_capacity entries would be produced.\n * If out is NULL, the call counts entries without writing anything; this\n * lets callers size an allocation up front.\n *\n * Returns false on malformed input.\n */\nstatic bool parse_apic_id_list(const char *val, uint32_t *out,\n size_t out_capacity, size_t *out_count)\n{\n size_t count = 0;\n const char *p = val;\n\n while (*p) {\n while (*p == ' ' || *p == '\\t')\n p++;\n if (*p == '\\0' || *p == ',') {\n if (*p == ',') p++;\n continue;\n }\n\n const char *start = p;\n while (*p && *p != ',')\n p++;\n\n const char *end = p;\n while (end > start && (end[-1] == ' ' || end[-1] == '\\t'))\n end--;\n\n char buf[64];\n size_t len = (size_t)(end - start);\n if (len == 0 || len >= sizeof(buf))\n return false;\n for (size_t i = 0; i < len; i++)\n buf[i] = start[i];\n buf[len] = '\\0';\n\n uint32_t lo, hi;\n if (!parse_apic_id_token(buf, &lo, &hi))\n return false;\n\n for (uint32_t v = lo; ; v++) {\n if (out != NULL) {\n if (count >= out_capacity)\n return false;\n out[count] = v;\n }\n /* Guard against size_t overflow: a single uint32_t range can\n * span 2^32 entries, which wraps size_t on 32-bit builds. */\n if (count == SIZE_MAX)\n return false;\n count++;\n if (v == hi)\n break;\n }\n\n if (*p == ',')\n p++;\n }\n\n *out_count = count;\n return true;\n}\n\n/*\n * Parse a PCI address in BB:DD.F format (all hex).\n */\nstatic bool parse_pci_address(const char *val, uint8_t *bus, uint8_t *device, uint8_t *function)\n{\n /* Find ':' separator between bus and device */\n const char *colon = NULL;\n for (const char *p = val; *p; p++) {\n if (*p == ':') { colon = p; break; }\n }\n if (!colon)\n return false;\n\n /* Find '.' separator between device and function */\n const char *dot = NULL;\n for (const char *p = colon + 1; *p; p++) {\n if (*p == '.') { dot = p; break; }\n }\n if (!dot)\n return false;\n\n uint32_t b, d, f;\n if (!parse_hex_byte(val, (size_t)(colon - val), &b) || b > 0xFF)\n return false;\n if (!parse_hex_byte(colon + 1, (size_t)(dot - colon - 1), &d) || d > 0x1F)\n return false;\n size_t flen = 0;\n while (dot[1 + flen]) flen++;\n if (!parse_hex_byte(dot + 1, flen, &f) || f > 0x7)\n return false;\n\n *bus = (uint8_t)b;\n *device = (uint8_t)d;\n *function = (uint8_t)f;\n return true;\n}\n\nstatic const char *skip_whitespace(const char *s)\n{\n while (*s == ' ' || *s == '\\t')\n s++;\n return s;\n}\n\nstatic size_t trim_trailing(const char *start, size_t len)\n{\n while (len > 0 && (start[len - 1] == ' ' || start[len - 1] == '\\t' ||\n start[len - 1] == '\\r' || start[len - 1] == '\\n'))\n len--;\n return len;\n}\n\n/*\n * Parse a single key=value line and apply it to gConfig.\n * key and val are null-terminated, trimmed strings.\n */\nstatic void config_apply(const char *key, const char *val)\n{\n if (streq_nocase(key, \"serial\")) {\n bool v;\n if (parse_bool(val, &v)) {\n gConfig.serial_debug = v;\n printf(\" serial = %s\\n\", v ? \"true\" : \"false\");\n } else {\n printf(\" warning: invalid value for 'serial': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"serial_port\")) {\n uint32_t v;\n if (parse_uint32(val, &v) && v <= 0xFFFF) {\n gConfig.serial_port = (uint16_t)v;\n printf(\" serial_port = 0x%x\\n\", gConfig.serial_port);\n } else {\n printf(\" warning: invalid value for 'serial_port': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"serial_baud\")) {\n uint32_t v;\n if (parse_uint32(val, &v) && v > 0) {\n gConfig.serial_baud = v;\n printf(\" serial_baud = %u\\n\", gConfig.serial_baud);\n } else {\n printf(\" warning: invalid value for 'serial_baud': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"vgabios\")) {\n /* Convert ASCII path to CHAR16 */\n size_t i;\n for (i = 0; val[i] && i < CONFIG_VGABIOS_PATH_MAX - 1; i++)\n gConfig.vgabios_path[i] = (CHAR16)(unsigned char)val[i];\n gConfig.vgabios_path[i] = 0;\n printf(\" vgabios = %s\\n\", val);\n } else if (streq_nocase(key, \"iommu_disable\")) {\n bool v;\n if (parse_bool(val, &v)) {\n gConfig.iommu_disable = v;\n printf(\" iommu_disable = %s\\n\", v ? \"true\" : \"false\");\n } else {\n printf(\" warning: invalid value for 'iommu_disable': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"verbose\")) {\n bool v;\n if (parse_bool(val, &v)) {\n gConfig.verbose = v;\n printf(\" verbose = %s\\n\", v ? \"true\" : \"false\");\n } else {\n printf(\" warning: invalid value for 'verbose': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"vga\")) {\n uint8_t b, d, f;\n if (parse_pci_address(val, &b, &d, &f)) {\n gConfig.vga_specified = true;\n gConfig.vga_bus = b;\n gConfig.vga_device = d;\n gConfig.vga_function = f;\n printf(\" vga = %02x:%02x.%x\\n\", b, d, f);\n } else {\n printf(\" warning: invalid PCI address for 'vga': %s (expected BB:DD.F)\\n\", val);\n }\n } else if (streq_nocase(key, \"system_thread\")) {\n uint32_t v;\n if (parse_uint32(val, &v)) {\n gConfig.system_thread_specified = true;\n gConfig.system_thread_apic_id = v;\n printf(\" system_thread = APIC ID %u\\n\", v);\n } else {\n printf(\" warning: invalid value for 'system_thread': %s\\n\", val);\n }\n } else if (streq_nocase(key, \"cpu_allowlist\") ||\n streq_nocase(key, \"cpu_blocklist\")) {\n enum csmwrap_cpu_filter_mode mode =\n streq_nocase(key, \"cpu_allowlist\") ? CPU_FILTER_ALLOWLIST\n : CPU_FILTER_BLOCKLIST;\n if (gConfig.cpu_filter_mode != CPU_FILTER_NONE &&\n gConfig.cpu_filter_mode != mode) {\n printf(\" warning: '%s' ignored - cpu_allowlist and cpu_blocklist \"\n \"are mutually exclusive\\n\", key);\n } else {\n /* First pass: validate syntax and compute the expanded count. */\n size_t count = 0;\n if (!parse_apic_id_list(val, NULL, 0, &count)) {\n printf(\" warning: invalid value for '%s': %s\\n\", key, val);\n } else if (count > SIZE_MAX / sizeof(uint32_t)) {\n /* Allocation size would wrap size_t. */\n printf(\" warning: '%s' has too many entries (%zu)\\n\",\n key, count);\n } else {\n uint32_t *list = NULL;\n if (count > 0) {\n EFI_STATUS st = gBS->AllocatePool(\n EfiLoaderData, count * sizeof(uint32_t),\n (void **)&list);\n if (EFI_ERROR(st)) {\n printf(\" warning: out of memory for '%s' (%zu IDs)\\n\",\n key, count);\n goto cpu_filter_done;\n }\n\n /* Second pass: actually fill the buffer. */\n size_t actual = 0;\n if (!parse_apic_id_list(val, list, count, &actual)\n || actual != count) {\n gBS->FreePool(list);\n printf(\" warning: parse mismatch for '%s'\\n\", key);\n goto cpu_filter_done;\n }\n }\n\n /* Replace any previously-set list. */\n if (gConfig.cpu_filter_list) {\n gBS->FreePool(gConfig.cpu_filter_list);\n gConfig.cpu_filter_list = NULL;\n }\n gConfig.cpu_filter_mode = mode;\n gConfig.cpu_filter_list = list;\n gConfig.cpu_filter_count = count;\n\n if (count == 0) {\n printf(\" %s = (empty)%s\\n\", key,\n mode == CPU_FILTER_ALLOWLIST\n ? \" - only the BSP will be visible to the OS\"\n : \" - no CPUs hidden\");\n } else {\n printf(\" %s = %zu APIC ID(s):\", key, count);\n /* Cap the printed list so a giant range doesn't spam. */\n size_t shown = count < 16 ? count : 16;\n for (size_t i = 0; i < shown; i++)\n printf(\" %u\", list[i]);\n if (shown < count)\n printf(\" ... (+%zu more)\", count - shown);\n printf(\"\\n\");\n }\n }\n cpu_filter_done: ;\n }\n } else {\n printf(\" warning: unknown config key '%s'\\n\", key);\n }\n}\n\n/*\n * Parse an INI-style buffer (flat key=value, no sections).\n */\nstatic void config_parse(char *buf, size_t len)\n{\n char *line = buf;\n char *end = buf + len;\n\n while (line < end) {\n /* Find end of line */\n char *eol = line;\n while (eol < end && *eol != '\\n')\n eol++;\n\n /* Null-terminate the line */\n if (eol < end)\n *eol = '\\0';\n\n const char *p = skip_whitespace(line);\n\n /* Skip empty lines and comments */\n if (*p == '\\0' || *p == ';' || *p == '#') {\n line = eol + 1;\n continue;\n }\n\n /* Find '=' separator */\n const char *eq = p;\n while (*eq && *eq != '=')\n eq++;\n\n if (*eq != '=') {\n printf(\" warning: malformed line (no '='): %s\\n\", p);\n line = eol + 1;\n continue;\n }\n\n /* Extract key: from p to eq, trimmed */\n size_t key_len = trim_trailing(p, (size_t)(eq - p));\n if (key_len == 0) {\n line = eol + 1;\n continue;\n }\n\n /* Null-terminate key in place */\n char *key_start = (char *)p;\n key_start[key_len] = '\\0';\n\n /* Extract value: after '=', trimmed */\n const char *val_start = skip_whitespace(eq + 1);\n size_t val_len = trim_trailing(val_start, eol - val_start);\n\n /* Null-terminate value in place */\n char *val_mut = (char *)val_start;\n val_mut[val_len] = '\\0';\n\n config_apply(key_start, val_mut);\n\n line = eol + 1;\n }\n}\n\n/*\n * Build the config file path by finding the directory of the running\n * EFI executable from its device path and appending \"csmwrap.ini\".\n */\nstatic bool config_build_path(EFI_DEVICE_PATH_PROTOCOL *file_path,\n CHAR16 *out, size_t out_chars)\n{\n if (!file_path)\n return false;\n\n /* Reconstruct the file path string from FILEPATH_DEVICE_PATH nodes */\n size_t pos = 0;\n out[0] = 0;\n\n EFI_DEVICE_PATH_PROTOCOL *node;\n for (node = file_path; !IsDevicePathEnd(node); node = NextDevicePathNode(node)) {\n if (DevicePathType(node) == MEDIA_DEVICE_PATH &&\n DevicePathSubType(node) == MEDIA_FILEPATH_DP) {\n FILEPATH_DEVICE_PATH *fp = (FILEPATH_DEVICE_PATH *)node;\n CHAR16 *src = fp->PathName;\n while (*src && pos < out_chars - 1) {\n out[pos++] = *src++;\n }\n }\n }\n out[pos] = 0;\n\n if (pos == 0)\n return false;\n\n /* Find the last backslash to strip the filename */\n size_t last_sep = 0;\n bool found_sep = false;\n for (size_t i = 0; i < pos; i++) {\n if (out[i] == L'\\\\' || out[i] == L'/') {\n last_sep = i;\n found_sep = true;\n }\n }\n\n size_t dir_end;\n if (found_sep) {\n dir_end = last_sep + 1; /* keep the trailing backslash */\n } else {\n /* No separator - file is at root, prepend backslash */\n dir_end = 0;\n if (pos + 1 < out_chars) {\n out[0] = L'\\\\';\n dir_end = 1;\n }\n }\n\n /* Append \"csmwrap.ini\" */\n static const CHAR16 ini_name[] = L\"csmwrap.ini\";\n size_t name_len = sizeof(ini_name) / sizeof(CHAR16) - 1;\n if (dir_end + name_len >= out_chars)\n return false;\n\n for (size_t i = 0; i <= name_len; i++)\n out[dir_end + i] = ini_name[i];\n\n return true;\n}\n\nvoid config_load(EFI_FILE_PROTOCOL *root_dir, EFI_DEVICE_PATH_PROTOCOL *file_path)\n{\n if (!root_dir || !file_path)\n return;\n\n CHAR16 path[512];\n if (!config_build_path(file_path, path, ARRAY_SIZE(path))) {\n printf(\"Config: could not determine executable directory\\n\");\n return;\n }\n\n EFI_FILE_PROTOCOL *file = NULL;\n EFI_STATUS status = root_dir->Open(root_dir, &file, path, EFI_FILE_MODE_READ, 0);\n if (status != EFI_SUCCESS) {\n /* Not an error - config file is optional */\n return;\n }\n\n /* Get file size via EFI_FILE_INFO */\n EFI_GUID fi_guid = EFI_FILE_INFO_ID;\n UINTN info_size = 0;\n file->GetInfo(file, &fi_guid, &info_size, NULL);\n\n void *info_buf = NULL;\n if (gBS->AllocatePool(EfiLoaderData, info_size, &info_buf) != EFI_SUCCESS) {\n file->Close(file);\n return;\n }\n\n UINTN file_size = 0;\n if (file->GetInfo(file, &fi_guid, &info_size, info_buf) == EFI_SUCCESS) {\n EFI_FILE_INFO *fi = info_buf;\n file_size = (UINTN)fi->FileSize;\n }\n gBS->FreePool(info_buf);\n\n if (file_size == 0 || file_size > 64 * 1024) {\n printf(\"Config: file empty or too large (%lu bytes)\\n\", (unsigned long)file_size);\n file->Close(file);\n return;\n }\n\n /* Read file contents */\n char *buf = NULL;\n if (gBS->AllocatePool(EfiLoaderData, file_size + 1, (void **)&buf) != EFI_SUCCESS) {\n file->Close(file);\n return;\n }\n\n UINTN read_size = file_size;\n if (file->Read(file, &read_size, buf) != EFI_SUCCESS) {\n gBS->FreePool(buf);\n file->Close(file);\n return;\n }\n buf[read_size] = '\\0';\n file->Close(file);\n\n printf(\"Config: loaded csmwrap.ini (%lu bytes)\\n\", (unsigned long)read_size);\n config_parse(buf, read_size);\n\n gBS->FreePool(buf);\n}\n" }, { "path": "src/config.h", "content": "#ifndef CONFIG_H\n#define CONFIG_H\n\n#include \n#include \n#include \n#include \n\n#define CONFIG_VGABIOS_PATH_MAX 256\n\nenum csmwrap_cpu_filter_mode {\n CPU_FILTER_NONE = 0,\n CPU_FILTER_ALLOWLIST,\n CPU_FILTER_BLOCKLIST,\n};\n\nstruct csmwrap_config {\n bool serial_debug;\n uint16_t serial_port;\n uint32_t serial_baud;\n CHAR16 vgabios_path[CONFIG_VGABIOS_PATH_MAX];\n bool iommu_disable;\n bool verbose;\n bool vga_specified;\n uint8_t vga_bus;\n uint8_t vga_device;\n uint8_t vga_function;\n\n bool system_thread_specified;\n uint32_t system_thread_apic_id;\n\n /*\n * cpu_filter_list points to an EFI-pool-allocated array of length\n * cpu_filter_count, or is NULL when cpu_filter_count == 0. An empty\n * list with mode ALLOWLIST means \"no APs visible to the OS\"; an\n * empty list with mode BLOCKLIST means \"no APs hidden from the OS\".\n */\n enum csmwrap_cpu_filter_mode cpu_filter_mode;\n uint32_t *cpu_filter_list;\n size_t cpu_filter_count;\n};\n\nextern struct csmwrap_config gConfig;\n\n/*\n * Returns true if the CPU with the given APIC ID is allowed by the\n * user-configured allow/block list. Does NOT consider BSP-must-keep or\n * system-thread-must-hide rules - callers handle those separately.\n *\n * With CPU_FILTER_NONE this always returns true.\n */\nbool config_cpu_in_filter(uint32_t apic_id);\n\n/*\n * Load configuration from csmwrap.ini next to the running EFI executable.\n * root_dir: filesystem root opened via EFI_SIMPLE_FILE_SYSTEM_PROTOCOL\n * file_path: loaded image's FilePath device path (used to find our directory)\n *\n * If the file is missing or unreadable, defaults are silently retained.\n */\nvoid config_load(EFI_FILE_PROTOCOL *root_dir, EFI_DEVICE_PATH_PROTOCOL *file_path);\n\n#endif\n" }, { "path": "src/coreboot.c", "content": "#include \n#include \"csmwrap.h\"\n\nstatic UINT16\nCbCheckSum16 (\n IN UINT16 *Buffer,\n IN UINTN Length\n )\n{\n UINT32 Sum;\n UINT32 TmpValue;\n UINTN Idx;\n UINT8 *TmpPtr;\n\n Sum = 0;\n TmpPtr = (UINT8 *)Buffer;\n for (Idx = 0; Idx < Length; Idx++) {\n TmpValue = TmpPtr[Idx];\n if (Idx % 2 == 1) {\n TmpValue <<= 8;\n }\n\n Sum += TmpValue;\n\n // Wrap\n if (Sum >= 0x10000) {\n Sum = (Sum + (Sum >> 16)) & 0xFFFF;\n }\n }\n\n return (UINT16)((~Sum) & 0xFFFF);\n}\n\nint build_coreboot_table(struct csmwrap_priv *priv)\n{\n void *p = (void *)CB_TABLE_START;\n void *tables;\n uint32_t table_entries = 0;\n\n struct cb_header *header = (struct cb_header *)p;\n memset(header, 0, sizeof(struct cb_header));\n header->signature = CB_HEADER_SIGNATURE;\n header->header_bytes = sizeof(struct cb_header);\n p += header->header_bytes;\n tables = p;\n\n /* cb_framebuffer */\n if (priv->video_type != CSMWRAP_VIDEO_OPROM) {\n struct cb_framebuffer *framebuffer = (struct cb_framebuffer *)p;\n memcpy(framebuffer, &priv->cb_fb, sizeof(struct cb_framebuffer));\n framebuffer->tag = CB_TAG_FRAMEBUFFER;\n framebuffer->size = sizeof(struct cb_framebuffer);\n p += framebuffer->size;\n table_entries++;\n }\n\n /* Last header stuff */\n header->table_entries = table_entries;\n header->table_bytes = (uint32_t)((uintptr_t)p - (uintptr_t)tables);\n header->table_checksum = CbCheckSum16((UINT16*)tables, header->table_bytes);\n header->header_checksum = CbCheckSum16((UINT16*)header, header->header_bytes);\n\n return 0;\n}\n" }, { "path": "src/csmwrap.c", "content": "#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n// Generated by: xxd -i Csm16.bin >> Csm16.h\n#include \n\n\n#ifndef BUILD_VERSION\n#define BUILD_VERSION \"Unknown\"\n#endif\n\nconst char *banner =\n \"\\033[38;2;0;102;128m _,,,,,,,,,,_\\n\"\n \" _,;l!l'''''''''''''l;l;,_\\n\"\n \" ,;l!''....................`ql;,_\\n\"\n \" ,;l'`............................`ql;_\\n\"\n \" ,;l'..........\\033[38;2;141;211;95m_____\\033[38;2;0;102;128m...................`ql,\\n\"\n \" lp`.........\\033[38;2;141;211;95m,;#######;,\\033[38;2;0;102;128m..................'ql\\n\"\n \" ,l'......\\033[38;2;141;211;95m_,;####\\033[38;2;228;230;109mooooooo\\033[38;2;141;211;95m##;_\\033[38;2;0;102;128m..................ql,\\n\"\n \" ,l'....\\033[38;2;141;211;95m,#######################+,\\033[38;2;0;102;128m..............ql,\\n\"\n \",l'...\\033[38;2;141;211;95m,##############################,\\033[38;2;0;102;128m...........ql,\\n\"\n \"lp....\\033[38;2;199;221;133m############\\033[38;2;141;211;95m######################,\\033[38;2;0;102;128m.........ql \\n\"\n \"lp....\\033[38;2;199;221;133m###############\\033[38;2;141;211;95m######################,\\033[38;2;0;102;128m......ql\\n\"\n \"lp....\\033[38;2;199;221;133m`################\\033[38;2;141;211;95m#####################\\\\\\033[38;2;0;102;128m.....ql \\n\"\n \"lp.....\\033[38;2;199;221;133m`################\\033[38;2;141;211;95m#####################\\\\\\033[38;2;0;102;128m....ql\\n\"\n \"`l,......\\033[38;2;199;221;133m`###############\\033[38;2;141;211;95m#####################\\033[38;2;0;102;128m...,l'\\n\"\n \" `l........\\033[38;2;199;221;133m`\\\"#########\\033[38;2;141;211;95m########################\\033[38;2;0;102;128m..,l'\\n\"\n \" `l,.........\\033[38;2;199;221;133m`\\\"\\\"#####\\033[38;2;141;211;95m######################%\\033[38;2;0;102;128m..,l'\\n\"\n \" `l,.........\\033[38;2;141;211;95m,,,,,;####################%\\\"\\033[38;2;0;102;128m...,l' \\n\"\n \" `l;,...\\033[38;2;141;211;95m\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"\\\"'\\033[38;2;0;102;128m.....,;l' \\n\"\n \" `l;,_.............................._,;l' \\n\"\n \" `l;,_......................._,;l'' \\n\"\n \" `'l;p,_............_,,;lll'`\\n\"\n \" `'''::::::::::'''\\033[0m\\n\"\n \"CSMWrap Version \" BUILD_VERSION \"\\n\"\n \"https://github.com/CSMWrap/CSMWrap\\n\"\n \"By: Jiaxun Yang \\n\"\n \"And: Mintsuki \\n\";\n\nEFI_SYSTEM_TABLE *gST;\nEFI_BOOT_SERVICES *gBS;\nEFI_RUNTIME_SERVICES *gRT;\nEFI_TIME gTimeAtBoot;\nbool gBootServicesExited = false;\n\nstruct csmwrap_priv priv = {\n .csm_bin = Csm16_bin,\n};\n\n/*\n * UEFI memory allocation wrappers for Flanterm.\n * These use EFI Boot Services pool allocation.\n */\nstatic void *flanterm_uefi_malloc(size_t size)\n{\n void *ptr = NULL;\n if (gBS->AllocatePool(EfiLoaderData, size, &ptr) != EFI_SUCCESS) {\n return NULL;\n }\n return ptr;\n}\n\nstatic void flanterm_uefi_free(void *ptr, size_t size)\n{\n (void)size; /* UEFI FreePool doesn't need size */\n if (ptr != NULL) {\n gBS->FreePool(ptr);\n }\n}\n\nstatic void *find_table(uint32_t signature, uint8_t *csm_bin_base, size_t size)\n{\n /* Compatibility16 header: signature[4], checksum[1], length[1], ... */\n for (uint8_t *Ptr = csm_bin_base; Ptr + 6 <= csm_bin_base + size; Ptr += 0x10) {\n if (*(uint32_t *)Ptr != signature)\n continue;\n uint8_t table_len = Ptr[5];\n if (table_len < 6 || (size_t)(Ptr - csm_bin_base) + table_len > size)\n continue;\n uint8_t sum = 0;\n for (uint8_t i = 0; i < table_len; i++)\n sum += Ptr[i];\n if (sum == 0)\n return Ptr;\n }\n return NULL;\n}\n\n/*\n * SMBIOS entry point structures\n */\n#define SMBIOS_21_SIGNATURE 0x5f4d535f /* \"_SM_\" */\n#define SMBIOS_21_ENTRY_POINT_LENGTH 0x1F /* Standard length */\n\n#pragma pack(1)\nstruct smbios_21_entry_point {\n uint32_t signature; /* \"_SM_\" */\n uint8_t checksum; /* Checksum of bytes 0x00-0x0F */\n uint8_t length; /* Entry point length (usually 0x1F) */\n uint8_t smbios_major_version;\n uint8_t smbios_minor_version;\n uint16_t max_structure_size;\n uint8_t entry_point_revision;\n uint8_t formatted_area[5];\n char intermediate_anchor_string[5]; /* \"_DMI_\" */\n uint8_t intermediate_checksum; /* Checksum of bytes 0x10-0x1E */\n uint16_t structure_table_length; /* Total length of structure table */\n uint32_t structure_table_address; /* Physical address of structure table */\n uint16_t number_of_structures;\n uint8_t smbios_bcd_revision;\n};\n\nstruct smbios_30_entry_point {\n char signature[5]; /* \"_SM3_\" */\n uint8_t checksum;\n uint8_t length;\n uint8_t smbios_major_version;\n uint8_t smbios_minor_version;\n uint8_t smbios_docrev;\n uint8_t entry_point_revision;\n uint8_t reserved;\n uint32_t structure_table_max_size;\n uint64_t structure_table_address; /* 64-bit! */\n};\n\n/* SMBIOS structure header - at the start of every structure */\nstruct smbios_structure_header {\n uint8_t type;\n uint8_t length; /* Length of formatted area only, not including strings */\n uint16_t handle;\n};\n#pragma pack()\n\nstatic uint8_t smbios_checksum(const void *data, size_t len)\n{\n const uint8_t *p = data;\n uint8_t sum = 0;\n for (size_t i = 0; i < len; i++)\n sum += p[i];\n return sum;\n}\n\n/*\n * Statistics gathered from walking the SMBIOS structure table.\n * Using uint32_t for sizes to avoid overflow during calculation,\n * even though SMBIOS 2.x limits these to 16-bit values.\n */\nstruct smbios_table_stats {\n uint32_t number_of_structures;\n uint32_t max_structure_size;\n uint32_t table_length;\n};\n\n/*\n * Walk the SMBIOS structure table and gather statistics.\n * The structure table format is the same for SMBIOS 2.x and 3.0.\n *\n * Each structure consists of:\n * - Formatted area (header.length bytes, starting with the header)\n * - Unformatted area (null-terminated strings, ending with double-null)\n *\n * Returns true on success, false if the table appears corrupted.\n */\nstatic bool smbios_walk_table(const void *table, uint32_t max_size, struct smbios_table_stats *stats)\n{\n const uint8_t *ptr = table;\n const uint8_t *end = ptr + max_size;\n\n stats->number_of_structures = 0;\n stats->max_structure_size = 0;\n stats->table_length = 0;\n\n while (ptr + sizeof(struct smbios_structure_header) <= end) {\n const struct smbios_structure_header *hdr = (const struct smbios_structure_header *)ptr;\n\n /* Sanity check: length must be at least header size */\n if (hdr->length < sizeof(struct smbios_structure_header)) {\n printf(\" Warning: Invalid structure length %u at offset %u\\n\",\n hdr->length, (uint32_t)(ptr - (const uint8_t *)table));\n return false;\n }\n\n /* Check formatted area doesn't exceed bounds */\n if (ptr + hdr->length > end) {\n printf(\" Warning: Structure exceeds table bounds\\n\");\n return false;\n }\n\n /* Find the end of the unformatted area (strings) */\n const uint8_t *strings_start = ptr + hdr->length;\n const uint8_t *strings_ptr = strings_start;\n\n /* Look for double-null terminator */\n bool found_terminator = false;\n while (strings_ptr + 1 < end) {\n if (strings_ptr[0] == 0 && strings_ptr[1] == 0) {\n strings_ptr += 2; /* Include both nulls */\n found_terminator = true;\n break;\n }\n strings_ptr++;\n }\n\n if (!found_terminator) {\n printf(\" Warning: Missing double-null terminator\\n\");\n return false;\n }\n\n /* Calculate this structure's total size */\n uint32_t struct_size = (uint32_t)(strings_ptr - ptr);\n if (struct_size > stats->max_structure_size) {\n stats->max_structure_size = struct_size;\n }\n\n stats->number_of_structures++;\n\n /* Type 127 marks end of table */\n if (hdr->type == 127) {\n stats->table_length = (uint32_t)(strings_ptr - (const uint8_t *)table);\n return true;\n }\n\n ptr = strings_ptr;\n }\n\n /* Reached end without finding type 127 - use what we have */\n stats->table_length = (uint32_t)(ptr - (const uint8_t *)table);\n return true;\n}\n\n/*\n * Allocated buffer for synthesized/relocated SMBIOS data.\n */\nstatic void *smbios_buffer = NULL;\n\n/*\n * Synthesize an SMBIOS 2.x entry point from SMBIOS 3.0 data.\n * The structure table data format is identical; only the entry point differs.\n *\n * Allocates memory for entry point + structure table below 4GB.\n * Returns the new SMBIOS 2.x entry point, or NULL on failure.\n */\nstatic struct smbios_21_entry_point *synthesize_smbios_21_from_30(\n struct smbios_30_entry_point *ep30,\n uint64_t st_addr,\n uint32_t st_max_size)\n{\n /* Walk the structure table to get accurate statistics */\n struct smbios_table_stats stats;\n if (!smbios_walk_table((void *)(uintptr_t)st_addr, st_max_size, &stats)) {\n printf(\" Failed to parse SMBIOS structure table\\n\");\n return NULL;\n }\n\n printf(\" Table stats: %u structures, max size %u, actual length %u\\n\",\n stats.number_of_structures, stats.max_structure_size, stats.table_length);\n\n /* Check for SMBIOS 2.x limitations (16-bit fields) */\n if (stats.table_length > 0xFFFF) {\n printf(\" Warning: Table length %u exceeds SMBIOS 2.x limit (65535)\\n\",\n stats.table_length);\n /* Truncate - some data will be missing but better than nothing */\n stats.table_length = 0xFFFF;\n }\n if (stats.max_structure_size > 0xFFFF) {\n printf(\" Warning: Max structure size exceeds SMBIOS 2.x limit\\n\");\n stats.max_structure_size = 0xFFFF;\n }\n if (stats.number_of_structures > 0xFFFF) {\n printf(\" Warning: Structure count exceeds SMBIOS 2.x limit\\n\");\n stats.number_of_structures = 0xFFFF;\n }\n\n /* Allocate buffer for entry point + structure table below 4GB */\n size_t total_size = SMBIOS_21_ENTRY_POINT_LENGTH + stats.table_length;\n EFI_PHYSICAL_ADDRESS max_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiRuntimeServicesData,\n (total_size + EFI_PAGE_SIZE - 1) / EFI_PAGE_SIZE,\n &max_addr\n );\n\n if (status != EFI_SUCCESS) {\n printf(\" Failed to allocate memory for SMBIOS synthesis\\n\");\n return NULL;\n }\n\n smbios_buffer = (void *)(uintptr_t)max_addr;\n printf(\" Synthesizing SMBIOS 2.x at %p\\n\", smbios_buffer);\n\n /* Build the SMBIOS 2.x entry point */\n struct smbios_21_entry_point *ep21 = smbios_buffer;\n memset(ep21, 0, SMBIOS_21_ENTRY_POINT_LENGTH);\n\n ep21->signature = SMBIOS_21_SIGNATURE;\n ep21->length = SMBIOS_21_ENTRY_POINT_LENGTH;\n ep21->smbios_major_version = ep30->smbios_major_version;\n ep21->smbios_minor_version = ep30->smbios_minor_version;\n ep21->max_structure_size = (uint16_t)stats.max_structure_size;\n ep21->entry_point_revision = 0;\n memcpy(ep21->intermediate_anchor_string, \"_DMI_\", 5);\n ep21->structure_table_length = (uint16_t)stats.table_length;\n ep21->number_of_structures = stats.number_of_structures;\n\n /* BCD revision: major in high nibble, minor in low nibble */\n ep21->smbios_bcd_revision = ((ep30->smbios_major_version & 0xF) << 4) |\n (ep30->smbios_minor_version & 0xF);\n\n /* Copy structure table after entry point */\n void *st_dest = (uint8_t *)smbios_buffer + SMBIOS_21_ENTRY_POINT_LENGTH;\n memcpy(st_dest, (void *)(uintptr_t)st_addr, stats.table_length);\n ep21->structure_table_address = (uint32_t)(uintptr_t)st_dest;\n\n /* Calculate checksums */\n ep21->checksum = 0;\n ep21->intermediate_checksum = 0;\n ep21->intermediate_checksum = -smbios_checksum((uint8_t *)ep21 + 0x10,\n SMBIOS_21_ENTRY_POINT_LENGTH - 0x10);\n ep21->checksum = -smbios_checksum(ep21, SMBIOS_21_ENTRY_POINT_LENGTH);\n\n printf(\" Synthesis complete: SMBIOS %u.%u, %u structures, table at %x\\n\",\n ep21->smbios_major_version, ep21->smbios_minor_version,\n ep21->number_of_structures, ep21->structure_table_address);\n\n return ep21;\n}\n\n#ifdef __x86_64__\n/*\n * Relocate SMBIOS 2.x entry point and structure table to below 4GB.\n * Only needed on 64-bit systems where SMBIOS data may be above 4GB.\n * Returns the new entry point address, or NULL on failure.\n */\nstatic struct smbios_21_entry_point *relocate_smbios_21(\n struct smbios_21_entry_point *ep,\n uint64_t st_addr,\n uint32_t st_size)\n{\n size_t ep_size = ep->length;\n size_t total_size = ep_size + st_size;\n\n /* Allocate below 4GB */\n EFI_PHYSICAL_ADDRESS max_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiRuntimeServicesData,\n (total_size + EFI_PAGE_SIZE - 1) / EFI_PAGE_SIZE,\n &max_addr\n );\n\n if (status != EFI_SUCCESS) {\n printf(\" Failed to allocate memory for SMBIOS relocation\\n\");\n return NULL;\n }\n\n smbios_buffer = (void *)(uintptr_t)max_addr;\n printf(\" Relocating SMBIOS to %p\\n\", smbios_buffer);\n\n /* Copy entry point */\n struct smbios_21_entry_point *new_ep = smbios_buffer;\n memcpy(new_ep, ep, ep_size);\n\n /* Copy structure table right after entry point */\n void *new_st = (uint8_t *)smbios_buffer + ep_size;\n memcpy(new_st, (void *)(uintptr_t)st_addr, st_size);\n\n /* Update structure table address in the new entry point */\n new_ep->structure_table_address = (uint32_t)(uintptr_t)new_st;\n\n /* Recalculate checksums */\n new_ep->checksum = 0;\n new_ep->intermediate_checksum = 0;\n new_ep->intermediate_checksum = -smbios_checksum((uint8_t *)new_ep + 0x10, ep_size - 0x10);\n new_ep->checksum = -smbios_checksum(new_ep, ep_size);\n\n printf(\" Relocation complete, new structure table at %x\\n\",\n new_ep->structure_table_address);\n\n return new_ep;\n}\n#endif /* __x86_64__ */\n\nint set_smbios_table()\n{\n EFI_GUID smbiosGuid = SMBIOS_TABLE_GUID;\n EFI_GUID smbios3Guid = SMBIOS3_TABLE_GUID;\n struct smbios_21_entry_point *result_ep = NULL;\n\n /* First, try to find SMBIOS 2.x table (preferred for legacy compatibility) */\n for (size_t i = 0; i < gST->NumberOfTableEntries; i++) {\n EFI_CONFIGURATION_TABLE *table = gST->ConfigurationTable + i;\n\n if (!efi_guidcmp(table->VendorGuid, smbiosGuid)) {\n struct smbios_21_entry_point *ep = table->VendorTable;\n printf(\"Found SMBIOS 2.x entry point at %p\\n\", (void *)ep);\n\n /* Validate signature */\n if (ep->signature != SMBIOS_21_SIGNATURE) {\n printf(\" Invalid signature, skipping\\n\");\n continue;\n }\n\n /* Validate checksums */\n if (smbios_checksum(ep, 0x10) != 0) {\n printf(\" Invalid entry point checksum, skipping\\n\");\n continue;\n }\n if (memcmp(ep->intermediate_anchor_string, \"_DMI_\", 5) != 0) {\n printf(\" Invalid DMI anchor, skipping\\n\");\n continue;\n }\n if (smbios_checksum((uint8_t *)ep + 0x10, ep->length - 0x10) != 0) {\n printf(\" Invalid intermediate checksum, skipping\\n\");\n continue;\n }\n\n printf(\" Version: %u.%u, structure table at %x, length %u\\n\",\n ep->smbios_major_version, ep->smbios_minor_version,\n ep->structure_table_address, ep->structure_table_length);\n\n#ifdef __x86_64__\n /* Check if entry point or structure table is above 4GB */\n uint64_t ep_addr = (uint64_t)(uintptr_t)ep;\n uint64_t st_addr = ep->structure_table_address;\n\n if (ep_addr >= 0x100000000ULL || st_addr >= 0x100000000ULL) {\n printf(\" Entry point or structure table above 4GB, relocation needed\\n\");\n result_ep = relocate_smbios_21(ep, st_addr, ep->structure_table_length);\n break;\n }\n#endif\n result_ep = ep;\n break;\n }\n }\n\n /*\n * If SMBIOS 2.x not found/usable, try SMBIOS 3.0.\n * We synthesize an SMBIOS 2.x entry point from the 3.0 data since\n * SeaBIOS and legacy operating systems only understand 2.x format.\n */\n if (!result_ep) {\n for (size_t i = 0; i < gST->NumberOfTableEntries; i++) {\n EFI_CONFIGURATION_TABLE *table = gST->ConfigurationTable + i;\n\n if (!efi_guidcmp(table->VendorGuid, smbios3Guid)) {\n struct smbios_30_entry_point *ep = table->VendorTable;\n printf(\"Found SMBIOS 3.0 entry point at %p\\n\", (void *)ep);\n\n /* Validate signature */\n if (memcmp(ep->signature, \"_SM3_\", 5) != 0) {\n printf(\" Invalid signature, skipping\\n\");\n continue;\n }\n\n /* Validate checksum */\n if (smbios_checksum(ep, ep->length) != 0) {\n printf(\" Invalid checksum, skipping\\n\");\n continue;\n }\n\n printf(\" Version: %u.%u, structure table at %lx, max size %u\\n\",\n ep->smbios_major_version, ep->smbios_minor_version,\n (unsigned long)ep->structure_table_address,\n ep->structure_table_max_size);\n\n /* Synthesize SMBIOS 2.x from 3.0 */\n result_ep = synthesize_smbios_21_from_30(\n ep, ep->structure_table_address, ep->structure_table_max_size);\n break;\n }\n }\n }\n\n if (!result_ep) {\n printf(\"No usable SMBIOS table found\\n\");\n return -1;\n }\n\n priv.low_stub->boot_table.SmbiosTable = (uintptr_t)result_ep;\n priv.low_stub->boot_table.SmbiosTableLength = result_ep->structure_table_length;\n return 0;\n}\n\nvoid __attribute__((noreturn)) panic(const char *fmt, ...)\n{\n gConfig.verbose = true;\n printf(\"\\n*** PANIC: \");\n va_list l;\n va_start(l, fmt);\n vprintf(fmt, l);\n va_end(l);\n printf(\"*** System halted.\\n\");\n for (;;) { asm volatile(\"hlt\"); }\n}\n\nEFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)\n{\n EFI_PHYSICAL_ADDRESS HiPmm;\n uintptr_t csm_bin_base;\n EFI_STATUS Status;\n EFI_IA32_REGISTER_SET Regs;\n\n gST = SystemTable;\n gBS = SystemTable->BootServices;\n gRT = SystemTable->RuntimeServices;\n\n calibrate_tsc();\n\n csmwrap_video_early_init(&priv);\n\n /* Initialise Flanterm (output gated on verbose; panics always show) */\n if (priv.cb_fb.physical_address != 0) {\n flanterm_ctx = flanterm_fb_init(\n flanterm_uefi_malloc, flanterm_uefi_free,\n (void *)(uintptr_t)priv.cb_fb.physical_address, priv.cb_fb.x_resolution, priv.cb_fb.y_resolution, priv.cb_fb.bytes_per_line,\n priv.cb_fb.red_mask_size, priv.cb_fb.red_mask_pos, priv.cb_fb.green_mask_size, priv.cb_fb.green_mask_pos, priv.cb_fb.blue_mask_size, priv.cb_fb.blue_mask_pos,\n NULL,\n NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0, 0, 0, 0, 0, 0,\n FLANTERM_FB_ROTATE_0\n );\n }\n\n gBS->SetWatchdogTimer(0, 0, 0, NULL);\n\n /* Banner is always shown on screen */\n gConfig.verbose = true;\n printf(\"%s\", banner);\n gConfig.verbose = false;\n\n for (EFI_PHYSICAL_ADDRESS i = 0; i < 0x100000; i += EFI_PAGE_SIZE) {\n EFI_PHYSICAL_ADDRESS j = i;\n if (gBS->AllocatePages(AllocateAddress, EfiLoaderData, 1, &j) != EFI_SUCCESS) {\n if (i < 0xa0000) {\n printf(\"warning: Early AllocatePages() failed for address 0x%llx\\n\", (unsigned long long)i);\n }\n }\n }\n\n if (gRT->GetTime(&gTimeAtBoot, NULL) != EFI_SUCCESS) {\n panic(\"Failed to query current time\\n\");\n }\n\n EFI_GUID loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;\n EFI_LOADED_IMAGE_PROTOCOL *loaded_image = NULL;\n if (gBS->HandleProtocol(ImageHandle, &loaded_image_guid, (void **)&loaded_image) != EFI_SUCCESS) {\n loaded_image = NULL;\n }\n\n EFI_GUID sfs_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;\n EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *sfs_protocol = NULL;\n if (loaded_image == NULL || gBS->HandleProtocol(loaded_image->DeviceHandle, &sfs_protocol_guid, (void **)&sfs_protocol) != EFI_SUCCESS) {\n sfs_protocol = NULL;\n }\n\n EFI_FILE_PROTOCOL *sfs_dir = NULL;\n if (sfs_protocol == NULL || sfs_protocol->OpenVolume(sfs_protocol, &sfs_dir) != EFI_SUCCESS) {\n sfs_dir = NULL;\n }\n\n /* Load configuration from csmwrap.ini next to our executable */\n if (sfs_dir != NULL && loaded_image != NULL) {\n config_load(sfs_dir, loaded_image->FilePath);\n }\n\n /* Load custom VGABIOS from config path if specified */\n EFI_FILE_PROTOCOL *vgabios_file_handle = NULL;\n if (sfs_dir != NULL && gConfig.vgabios_path[0] != 0) {\n if (sfs_dir->Open(sfs_dir, &vgabios_file_handle, gConfig.vgabios_path, EFI_FILE_MODE_READ, 0) == EFI_SUCCESS) {\n UINTN max_size = 256 * 1024;\n if (gBS->AllocatePool(EfiLoaderData, max_size, &vbios_loc) != EFI_SUCCESS) {\n vbios_loc = NULL;\n } else {\n if (vgabios_file_handle->Read(vgabios_file_handle, &max_size, vbios_loc) == EFI_SUCCESS) {\n printf(\"Loaded custom VBIOS from config. Using it as our VBIOS!\\n\");\n vbios_size = max_size;\n } else {\n gBS->FreePool(vbios_loc);\n vbios_loc = NULL;\n }\n }\n vgabios_file_handle->Close(vgabios_file_handle);\n } else {\n printf(\"warning: could not open configured vgabios path\\n\");\n }\n }\n\n if (sfs_dir != NULL) {\n sfs_dir->Close(sfs_dir);\n }\n\n if (unlock_bios_region()) {\n panic(\"Unable to unlock BIOS region\\n\");\n }\n printf(\"Unlock!\\n\");\n\n apply_intel_platform_workarounds();\n\n csm_bin_base = (uintptr_t)BIOSROM_END - sizeof(Csm16_bin);\n priv.csm_bin_base = csm_bin_base;\n printf(\"csm_bin_base: 0x%lx\\n\", csm_bin_base);\n if (csm_bin_base < VGABIOS_END) {\n panic(\"Illegal csm_bin size\\n\");\n }\n\n priv.csm_efi_table = find_table(EFI_COMPATIBILITY16_TABLE_SIGNATURE, Csm16_bin, sizeof(Csm16_bin));\n if (priv.csm_efi_table == NULL) {\n panic(\"EFI_COMPATIBILITY16_TABLE not found\\n\");\n }\n\n /* Initialize ACPI first (needed for MADT parsing in bios_proxy_init) */\n if (!acpi_init(&priv)) {\n panic(\"ACPI initialization failed\\n\");\n }\n\n /* Calculate RSDP copy location for MADT patching */\n void *rsdp_copy = priv.csm_bin + (priv.csm_efi_table->AcpiRsdPtrPointer - priv.csm_bin_base);\n\n /* Initialize BIOS proxy (find mailbox and helper entry in CSM binary) */\n if (bios_proxy_init(Csm16_bin, sizeof(Csm16_bin), rsdp_copy) != 0) {\n panic(\"BIOS proxy initialization failed\\n\");\n }\n bool pci_initialized = pci_early_initialize();\n if (!pci_initialized)\n printf(\"pci_early_initialize failed, PCI BAR relocation will be skipped\\n\");\n\n Status = csmwrap_video_init(&priv);\n\n /* Enumerate non-VGA PCI option ROMs while boot services are available */\n struct pci_oprom_list oprom_list;\n oprom_enumerate(&priv, &oprom_list);\n\n HiPmm = 0xffffffff;\n if (gBS->AllocatePages(AllocateMaxAddress, EfiRuntimeServicesData, HIPMM_SIZE / EFI_PAGE_SIZE, &HiPmm) != EFI_SUCCESS) {\n panic(\"Unable to alloc HiPmm\\n\");\n }\n\n priv.low_stub = (struct low_stub *)LOW_STUB_BASE;\n memset((void*)LOW_STUB_BASE, 0, CONVEN_END - LOW_STUB_BASE);\n\n set_smbios_table();\n priv.low_stub->boot_table.AcpiTable = priv.csm_efi_table->AcpiRsdPtrPointer;\n\n uintptr_t pmm_base = LegacyBiosInitializeThunkAndTable(LOW_STUB_BASE, sizeof(struct low_stub));\n\n printf(\"Init Thunk pmm: %lx\\n\", (uintptr_t)pmm_base);\n\n priv.low_stub->init_table.BiosLessThan1MB = 0; // SeaBIOS does not actually use this field.\n priv.low_stub->init_table.ThunkStart = (uint32_t)(uintptr_t)priv.low_stub;\n priv.low_stub->init_table.ThunkSizeInBytes = sizeof(struct low_stub);\n priv.low_stub->init_table.LowPmmMemory = (uint32_t)pmm_base;\n priv.low_stub->init_table.LowPmmMemorySizeInBytes = (uint32_t)CONVEN_END - (uint32_t)pmm_base;\n priv.low_stub->init_table.HiPmmMemorySizeInBytes = HIPMM_SIZE;\n priv.low_stub->init_table.HiPmmMemory = HiPmm;\n\n priv.low_stub->vga_oprom_table.OpromSegment = EFI_SEGMENT(VGABIOS_START);\n priv.low_stub->vga_oprom_table.PciBus = priv.vga_pci_bus;\n priv.low_stub->vga_oprom_table.PciDeviceFunction = priv.vga_pci_devfn;\n\n /* Build BBS table with boot device prioritized */\n build_bbs_table(&priv, ImageHandle);\n\n /* Build MP table from ACPI MADT (excludes helper core) */\n mptable_init(&priv);\n\n /* Build $PIR table from ACPI _PRT for legacy PCI BIOS callers */\n pir_init(&priv);\n\n printf(\"CALL16 %x:%x\\n\", priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset);\n\n /* WARNING: No EFI Video afterwards */\n csmwrap_video_prepare_exitbs(&priv);\n\n /* WARNING: No EFI runtime service afterwards */\n UINTN efi_mmap_size = 0, efi_desc_size = 0, efi_mmap_key = 0;\n UINT32 efi_desc_ver = 0;\n EFI_MEMORY_DESCRIPTOR *efi_mmap = NULL;\n UINTN efi_mmap_alloc = 0;\n\n for (size_t retries = 0; ; retries++) {\n if (retries == 128) {\n panic(\"Failed to exit boot services\\n\");\n }\n\n efi_mmap_size = efi_mmap_alloc;\n Status = gBS->GetMemoryMap(&efi_mmap_size, efi_mmap, &efi_mmap_key,\n &efi_desc_size, &efi_desc_ver);\n if (Status == EFI_BUFFER_TOO_SMALL) {\n /* Map grew (or first call) - reallocate with slack for the\n * descriptors that AllocatePool itself may add. */\n if (efi_mmap != NULL) {\n gBS->FreePool(efi_mmap);\n }\n efi_mmap_alloc = efi_mmap_size + 4096;\n if (gBS->AllocatePool(EfiLoaderData, efi_mmap_alloc,\n (void **)&efi_mmap) != EFI_SUCCESS) {\n panic(\"AllocatePool() for EFI memory map failed\\n\");\n }\n continue;\n }\n if (Status != EFI_SUCCESS) {\n panic(\"GetMemoryMap() failed\\n\");\n }\n\n Status = gBS->ExitBootServices(ImageHandle, efi_mmap_key);\n if (Status == EFI_SUCCESS) {\n break;\n }\n /* Key invalidated by a memory-map change - retry. */\n }\n\n /* Boot services protocols (including serial I/O) are no longer usable */\n gBootServicesExited = true;\n\n /* Disable external interrupts */\n asm volatile (\"cli\");\n\n /* Disable IOMMUs before PCI relocation and CSM init */\n if (gConfig.iommu_disable)\n iommu_disable();\n\n /* Prepare APIC for legacy BIOS operation (disable or configure for ExtINT) */\n apic_prepare_for_legacy();\n\n pci_late_initialize();\n\n build_coreboot_table(&priv);\n\n build_e820_map(&priv, efi_mmap, efi_mmap_size, efi_desc_size);\n uintptr_t e820_low = (uintptr_t)&priv.low_stub->e820_map;\n priv.csm_efi_table->E820Pointer = e820_low;\n priv.csm_efi_table->E820Length = sizeof(EFI_E820_ENTRY64) * priv.low_stub->e820_entries;\n\n /* Hand SeaBIOS the exact extra root bus numbers we discovered via\n * uACPI. Setting the pointer (even with count==0) signals authoritative\n * info; if discovery failed we leave the fields zero and SeaBIOS uses\n * its pre-extension default. */\n if (pci_initialized) {\n size_t extra_root_count = pci_get_extra_root_buses(\n priv.low_stub->extra_pci_roots, EXTRA_PCI_ROOTS_MAX);\n priv.low_stub->extra_pci_roots_count = (uint8_t)extra_root_count;\n priv.csm_efi_table->ExtraPciRootListPointer =\n (uint32_t)(uintptr_t)&priv.low_stub->extra_pci_roots[0];\n priv.csm_efi_table->ExtraPciRootListCount = (uint8_t)extra_root_count;\n printf(\"Reporting %zu extra PCI root bus(es) to SeaBIOS:\", extra_root_count);\n for (size_t i = 0; i < extra_root_count; i++)\n printf(\" %u\", priv.low_stub->extra_pci_roots[i]);\n printf(\"\\n\");\n }\n\n /* Disable 8259 PIC */\n outb(0x21, 0xff);\n outb(0xa1, 0xff);\n outb(0x43, 0x36);\n /* Program PIT to default */\n outb(0x40, 0x00);\n outb(0x40, 0x00);\n\n /* Copy ROM to location, as late as possible */\n memcpy((void*)csm_bin_base, Csm16_bin, sizeof(Csm16_bin));\n if (vbios_loc != NULL) {\n uintptr_t max_vbios_size = csm_bin_base - VGABIOS_START;\n if (vbios_size > max_vbios_size) {\n panic(\"VBIOS too large (%u bytes, max %u)\\n\",\n (unsigned)vbios_size, (unsigned)max_vbios_size);\n }\n memcpy((void*)VGABIOS_START, vbios_loc, vbios_size);\n }\n\n /*\n * Start the BIOS proxy helper core now that CSM is in its final location.\n * The helper core will handle BIOS calls when the main core is in V86 mode.\n */\n if (bios_proxy_start_helper(csm_bin_base) != 0) {\n panic(\"Failed to start BIOS proxy helper core\\n\");\n }\n\n /* Disable flanterm after last potential panic point - SeaBIOS will take over video */\n flanterm_ctx = NULL;\n\n memset(&Regs, 0, sizeof(EFI_IA32_REGISTER_SET));\n Regs.X.AX = Legacy16InitializeYourself;\n Regs.X.ES = EFI_SEGMENT(&priv.low_stub->init_table);\n Regs.X.BX = EFI_OFFSET(&priv.low_stub->init_table);\n\n LegacyBiosFarCall86(priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset,\n &Regs,\n NULL,\n 0);\n\n if (priv.vga_pci_io != NULL) {\n pci_enable_for_oprom(priv.vga_pci_bus, priv.vga_pci_devfn);\n }\n\n memset(&Regs, 0, sizeof(EFI_IA32_REGISTER_SET));\n Regs.X.AX = Legacy16DispatchOprom;\n Regs.X.ES = EFI_SEGMENT(&priv.low_stub->vga_oprom_table);\n Regs.X.BX = EFI_OFFSET(&priv.low_stub->vga_oprom_table);\n LegacyBiosFarCall86(priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset,\n &Regs,\n NULL,\n 0);\n\n /* Dispatch non-VGA option ROMs (storage, network, etc.) */\n oprom_dispatch_all(&priv, &oprom_list);\n\n memset(&Regs, 0, sizeof(EFI_IA32_REGISTER_SET));\n Regs.X.AX = Legacy16UpdateBbs;\n Regs.X.ES = EFI_SEGMENT(&priv.low_stub->boot_table);\n Regs.X.BX = EFI_OFFSET(&priv.low_stub->boot_table);\n LegacyBiosFarCall86(priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset,\n &Regs,\n NULL,\n 0);\n\n memset(&Regs, 0, sizeof(EFI_IA32_REGISTER_SET));\n Regs.X.AX = Legacy16PrepareToBoot;\n Regs.X.ES = EFI_SEGMENT(&priv.low_stub->boot_table);\n Regs.X.BX = EFI_OFFSET(&priv.low_stub->boot_table);\n\n LegacyBiosFarCall86(priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset,\n &Regs,\n NULL,\n 0);\n\n memset(&Regs, 0, sizeof(EFI_IA32_REGISTER_SET));\n Regs.X.AX = Legacy16Boot;\n // No arguments?\n\n LegacyBiosFarCall86(priv.csm_efi_table->Compatibility16CallSegment,\n priv.csm_efi_table->Compatibility16CallOffset,\n &Regs,\n NULL,\n 0);\n\n return 0;\n}\n" }, { "path": "src/csmwrap.h", "content": "#ifndef _CSM_WRAP_H\n#define _CSM_WRAP_H\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nextern EFI_SYSTEM_TABLE *gST;\nextern EFI_BOOT_SERVICES *gBS;\nextern EFI_RUNTIME_SERVICES *gRT;\nextern EFI_TIME gTimeAtBoot;\nextern bool gBootServicesExited;\n\nenum csmwrap_video_type {\n CSMWRAP_VIDEO_NONE,\n CSMWRAP_VIDEO_OPROM,\n CSMWRAP_VIDEO_SEAVGABIOS,\n};\n\nstruct csmwrap_priv {\n uint8_t *csm_bin;\n\n EFI_COMPATIBILITY16_TABLE *csm_efi_table;\n uintptr_t csm_bin_base;\n struct low_stub *low_stub;\n\n /* VGA stuff */\n enum csmwrap_video_type video_type;\n EFI_GRAPHICS_OUTPUT_PROTOCOL *gop;\n EFI_HANDLE gop_handle;\n EFI_PCI_IO_PROTOCOL *vga_pci_io;\n uint8_t vga_pci_bus;\n uint8_t vga_pci_devfn;\n uint16_t vga_vendor_id;\n uint16_t vga_device_id;\n struct cb_framebuffer cb_fb;\n};\n\nextern struct csmwrap_priv priv;\n\nextern int unlock_bios_region();\nextern int build_coreboot_table(struct csmwrap_priv *priv);\nbool acpi_init(struct csmwrap_priv *priv);\nbool acpi_namespace_init(void);\nint build_e820_map(struct csmwrap_priv *priv, EFI_MEMORY_DESCRIPTOR *memory_map, UINTN memory_map_size, UINTN descriptor_size);\nint apply_intel_platform_workarounds(void);\nvoid __attribute__((noreturn)) panic(const char *fmt, ...);\n\n\nstatic inline int\nefi_guidcmp (EFI_GUID left, EFI_GUID right)\n{\n\treturn memcmp(&left, &right, sizeof (EFI_GUID));\n}\n\n\n#define E820_MAX_ENTRIES 128\n#define MAX_BBS_ENTRIES 32\n#define BBS_DESC_STRING_SIZE 32\n#define EXTRA_PCI_ROOTS_MAX 255\n\n#pragma pack(1)\nstruct low_stub {\n LOW_MEMORY_THUNK thunk;\n\n EFI_TO_COMPATIBILITY16_INIT_TABLE init_table;\n EFI_TO_COMPATIBILITY16_BOOT_TABLE boot_table;\n EFI_DISPATCH_OPROM_TABLE vga_oprom_table;\n EFI_DISPATCH_OPROM_TABLE oprom_table; /* Reused for each non-VGA oprom dispatch */\n\n /* E820 memory map */\n int e820_entries;\n EFI_E820_ENTRY64 e820_map[E820_MAX_ENTRIES];\n\n /* BBS table for boot device priority */\n size_t bbs_entry_count;\n BBS_TABLE bbs_entries[MAX_BBS_ENTRIES];\n char bbs_desc_strings[MAX_BBS_ENTRIES][BBS_DESC_STRING_SIZE];\n\n /* Extra (non-zero) PCI root bus numbers, exposed to SeaBIOS so it can\n * skip its brute-force scan past MaxPCIBus. */\n uint8_t extra_pci_roots[EXTRA_PCI_ROOTS_MAX];\n uint8_t extra_pci_roots_count;\n};\n#pragma pack()\n\n/* Memory map information */\n/* In low memory */\n#define CB_TABLE_START 0x00000500\n#define CONVEN_START 0x00007E00\n/* We may have some stack here */\n#define LOW_STUB_BASE 0x00020000\n/*\n * Conventional memory ends at 640KB (0xA0000) - EBDA size.\n * The 1KB initial EBDA matches SeaBIOS's EBDA_SIZE_START on entry; SeaBIOS\n * may grow the EBDA downward during option ROM dispatch and will update its\n * own e820 accordingly, so this constant only describes the starting layout.\n * The PMM (Post Memory Manager) area is between low_stub and CONVEN_END.\n */\n#define CONVEN_END 0x0009FC00\n#define EBDA_BASE CONVEN_END\n#define VGABIOS_START 0x000C0000\n#define VGABIOS_END 0x000C8000\n#define BIOSROM_START VGABIOS_END\n#define BIOSROM_END 0x00100000\n/* End of low 1MiB */\n#define HIPMM_SIZE 0x400000 /* Allocated on runtime, can be anywhere in 32bit */\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))\n#endif\n\n#ifdef ALIGN\n# undef ALIGN\n#endif\n#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL)\n#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))\n#define ALIGN_UP(x, a) ALIGN((x), (a))\n#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL))\n#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0)\n\n#ifdef ACCESS_PAGE0_CODE\n# undef ACCESS_PAGE0_CODE\n#endif\n\n#define ACCESS_PAGE0_CODE(statements) \\\n do { \\\n statements; \\\n \\\n } while (FALSE)\n\n#endif\n" }, { "path": "src/e820.c", "content": "#include \n\n#include \n#include \"csmwrap.h\"\n#include \"io.h\"\n\n/* This is not in E820.h */\n#define EfiAcpiAddressRangeHole (-1ULL)\n\nstatic const char *\ne820_type_name(uint32_t type)\n{\n switch (type) {\n case EfiAcpiAddressRangeMemory: return \"RAM\";\n case EfiAcpiAddressRangeReserved: return \"RESERVED\";\n case EfiAcpiAddressRangeACPI: return \"ACPI\";\n case EfiAcpiAddressRangeNVS: return \"NVS\";\n default: return \"UNKNOWN\";\n }\n}\n\n// Remove an entry from the e820_map.\nstatic void\nremove_e820(struct csmwrap_priv *priv, int i)\n{\n EFI_E820_ENTRY64 *e820_map = priv->low_stub->e820_map;\n int *e820_count = &priv->low_stub->e820_entries;\n\n if (i < 0 || i >= *e820_count) {\n printf(\"e820_map remove index out of range\\n\");\n return;\n }\n\n (*e820_count)--;\n memmove(&e820_map[i], &e820_map[i+1],\n sizeof(EFI_E820_ENTRY64) * (*e820_count - i));\n}\n\n// Insert an entry in the e820_map at the given position.\nstatic void\ninsert_e820(struct csmwrap_priv *priv,\n int i, uint64_t start, uint64_t size, uint64_t type)\n{\n EFI_E820_ENTRY64 *e820_map = priv->low_stub->e820_map;\n int *e820_count = &priv->low_stub->e820_entries;\n\n if (*e820_count >= E820_MAX_ENTRIES) {\n printf(\"e820_map overflow\\n\");\n return;\n }\n\n memmove(&e820_map[i + 1], &e820_map[i],\n sizeof(EFI_E820_ENTRY64) * (*e820_count - i));\n\n (*e820_count)++;\n EFI_E820_ENTRY64 *e = &e820_map[i];\n e->BaseAddr = start;\n e->Length = size;\n e->Type = type;\n}\n\n// Show the current e820_map.\nstatic void\ndump_map(struct csmwrap_priv *priv)\n{\n EFI_E820_ENTRY64 *e820_map = priv->low_stub->e820_map;\n int e820_count = priv->low_stub->e820_entries;\n\n printf(\"csmwrap e820 map has %d items:\\n\", e820_count);\n int i;\n for (i = 0; i < e820_count; i++) {\n EFI_E820_ENTRY64 *e = &e820_map[i];\n uint64_t e_end = e->BaseAddr + e->Length;\n\n printf(\" %d: %016llx - %016llx = %d %s\\n\", i,\n e->BaseAddr, e_end, e->Type, e820_type_name(e->Type));\n }\n}\n\nstatic const char *\nefi_memory_type_name(uint32_t type)\n{\n switch (type) {\n case EfiReservedMemoryType: return \"Reserved\";\n case EfiLoaderCode: return \"LoaderCode\";\n case EfiLoaderData: return \"LoaderData\";\n case EfiBootServicesCode: return \"BSCode\";\n case EfiBootServicesData: return \"BSData\";\n case EfiRuntimeServicesCode: return \"RTCode\";\n case EfiRuntimeServicesData: return \"RTData\";\n case EfiConventionalMemory: return \"Conventional\";\n case EfiUnusableMemory: return \"Unusable\";\n case EfiACPIReclaimMemory: return \"ACPIReclaim\";\n case EfiACPIMemoryNVS: return \"ACPINVS\";\n case EfiMemoryMappedIO: return \"MMIO\";\n case EfiMemoryMappedIOPortSpace: return \"MMIOPort\";\n case EfiPalCode: return \"PalCode\";\n case EfiPersistentMemory: return \"Persistent\";\n case EfiUnacceptedMemoryType: return \"Unaccepted\";\n default: return \"UNKNOWN\";\n }\n}\n\n// Show the raw UEFI memory map that build_e820_map() consumes.\nstatic void\ndump_efi_memory_map(EFI_MEMORY_DESCRIPTOR *memory_map,\n UINTN memory_map_size, UINTN descriptor_size)\n{\n EFI_MEMORY_DESCRIPTOR *end = (EFI_MEMORY_DESCRIPTOR *)\n ((uint8_t *)memory_map + memory_map_size);\n int count = descriptor_size ? (int)(memory_map_size / descriptor_size) : 0;\n\n printf(\"EFI memory map has %d entries (descriptor_size=%u):\\n\",\n count, (unsigned)descriptor_size);\n\n int i = 0;\n for (EFI_MEMORY_DESCRIPTOR *d = memory_map; d < end;\n d = NextMemoryDescriptor(d, descriptor_size), i++) {\n uint64_t bytes = d->NumberOfPages * EFI_PAGE_SIZE;\n uint64_t end_addr = d->PhysicalStart + bytes;\n\n printf(\" %3d: %016llx - %016llx (%6llu pages) %2u %-13s attr=%016llx%s\\n\",\n i, d->PhysicalStart, end_addr,\n (unsigned long long)d->NumberOfPages,\n d->Type, efi_memory_type_name(d->Type),\n (unsigned long long)d->Attribute,\n (d->Attribute & EFI_MEMORY_RUNTIME) ? \" RT\" : \"\");\n }\n}\n\nvoid e820_add(struct csmwrap_priv *priv, uint64_t start,\n uint64_t size, uint64_t type)\n{\n EFI_E820_ENTRY64 *e820_map = priv->low_stub->e820_map;\n int *e820_count = &priv->low_stub->e820_entries;\n\n if (!size)\n return;\n\n // Find position of new item (splitting existing item if needed).\n uint64_t end = start + size;\n int i;\n for (i = 0; i < *e820_count; i++) {\n EFI_E820_ENTRY64 *e = &e820_map[i];\n uint64_t e_end = e->BaseAddr + e->Length;\n if (start > e_end)\n continue;\n // Found position - check if an existing item needs to be split.\n if (start > e->BaseAddr) {\n if (type == e->Type) {\n // Same type - merge them.\n size += start - e->BaseAddr;\n start = e->BaseAddr;\n } else {\n // Split existing item.\n e->Length = start - e->BaseAddr;\n i++;\n if (e_end > end)\n insert_e820(priv, i, end, e_end - end, e->Type);\n }\n }\n break;\n }\n // Remove/adjust existing items that are overlapping.\n while (i < *e820_count) {\n EFI_E820_ENTRY64 *e = &e820_map[i];\n if (end < e->BaseAddr)\n // No overlap - done.\n break;\n uint64_t e_end = e->BaseAddr + e->Length;\n if (end >= e_end) {\n // Existing item completely overlapped - remove it.\n remove_e820(priv, i);\n continue;\n }\n // Not completely overlapped - adjust its start.\n e->BaseAddr = end;\n e->Length = e_end - end;\n if (type == e->Type) {\n // Same type - merge them.\n size += e->Length;\n remove_e820(priv, i);\n }\n break;\n }\n // Insert new item.\n if (type != EfiAcpiAddressRangeHole)\n insert_e820(priv, i, start, size, type);\n}\n\n// Remove any definitions in a memory range (make a memory hole).\nvoid\ne820_remove(struct csmwrap_priv *priv, uint64_t start, uint64_t size)\n{\n e820_add(priv, start, size, EfiAcpiAddressRangeHole);\n}\n\n/*\n * Convert UEFI memory types to E820 types\n * See https://uefi.org/sites/default/files/resources/ACPI_4_Errata_A.pdf Table 14-6\n */\nstatic uint32_t convert_memory_type(EFI_MEMORY_TYPE type)\n{\n switch (type) {\n case EfiConventionalMemory:\n case EfiLoaderCode:\n case EfiLoaderData:\n case EfiBootServicesCode:\n case EfiBootServicesData:\n return EfiAcpiAddressRangeMemory;\n case EfiACPIReclaimMemory:\n return EfiAcpiAddressRangeACPI;\n case EfiACPIMemoryNVS:\n return EfiAcpiAddressRangeNVS;\n case EfiUnusableMemory:\n case EfiReservedMemoryType:\n case EfiRuntimeServicesCode:\n case EfiRuntimeServicesData:\n case EfiMemoryMappedIO:\n case EfiMemoryMappedIOPortSpace:\n case EfiPalCode:\n default:\n return EfiAcpiAddressRangeReserved;\n }\n}\n\nstatic inline void cmos_write(uint8_t reg, uint8_t val)\n{\n outb(0x70, 0x80 | reg);\n outb(0x80, 0);\n outb(0x71, val);\n}\n\n/*\n * Write CMOS memory size registers to match the E820 map.\n *\n * UEFI firmware does not initialize legacy CMOS memory registers, leaving them\n * with garbage values. Some legacy software (notably Windows 95 setup) reads\n * CMOS directly to detect extended memory size, bypassing INT 15h and XMS.\n *\n * CMOS layout:\n * 0x15/0x16: Base memory in KB (should be 640)\n * 0x17/0x18: Total extended memory in KB, saturated to 65535\n * 0x30/0x31: Total extended memory in KB, saturated to 65535 (mirror of 0x17/0x18)\n * 0x34/0x35: Extended memory above 16MB, in 64KB blocks (max 65535)\n * 0x5B/0x5C/0x5D: Extended memory above 4GB, in 64KB blocks (24-bit, max 0xFFFFFF)\n */\nstatic void\ne820_update_cmos(struct csmwrap_priv *priv)\n{\n EFI_E820_ENTRY64 *e820_map = priv->low_stub->e820_map;\n int e820_count = priv->low_stub->e820_entries;\n\n /* Find end of contiguous RAM starting from 1MB */\n uint64_t ram_end = 0x100000;\n int progress = 1;\n while (progress) {\n progress = 0;\n for (int i = 0; i < e820_count; i++) {\n EFI_E820_ENTRY64 *e = &e820_map[i];\n uint64_t e_end = e->BaseAddr + e->Length;\n if (e->Type != EfiAcpiAddressRangeMemory &&\n e->Type != EfiAcpiAddressRangeACPI)\n continue;\n if (e_end > 0xFFFFFFFFULL)\n continue;\n if (e->BaseAddr <= ram_end && e_end > ram_end) {\n ram_end = e_end;\n progress = 1;\n }\n }\n }\n\n uint64_t ext_kb = (ram_end > 0x100000) ? (ram_end - 0x100000) / 1024 : 0;\n uint64_t above_16m_64k = (ram_end > 0x1000000) ?\n (ram_end - 0x1000000) / 65536 : 0;\n\n /* Find end of contiguous RAM starting from 4GB */\n uint64_t high_ram_end = 0x100000000ULL;\n progress = 1;\n while (progress) {\n progress = 0;\n for (int i = 0; i < e820_count; i++) {\n EFI_E820_ENTRY64 *e = &e820_map[i];\n uint64_t e_end = e->BaseAddr + e->Length;\n if (e->Type != EfiAcpiAddressRangeMemory &&\n e->Type != EfiAcpiAddressRangeACPI)\n continue;\n if (e->BaseAddr <= high_ram_end && e_end > high_ram_end) {\n high_ram_end = e_end;\n progress = 1;\n }\n }\n }\n\n uint64_t above_4g_64k = (high_ram_end > 0x100000000ULL) ?\n (high_ram_end - 0x100000000ULL) / 65536 : 0;\n\n /* Cap to register widths */\n uint16_t cmos_17_18 = (ext_kb > 65535) ? 65535 : (uint16_t)ext_kb;\n uint16_t cmos_30_31 = (ext_kb > 65535) ? 65535 : (uint16_t)ext_kb;\n uint16_t cmos_34_35 = (above_16m_64k > 65535) ? 65535 :\n (uint16_t)above_16m_64k;\n uint32_t cmos_5b_5d = (above_4g_64k > 0xFFFFFF) ? 0xFFFFFF :\n (uint32_t)above_4g_64k;\n\n printf(\"CMOS: base=640 ext=%u KB >16M=%u x64KB >4G=%u x64KB (ram_end=0x%llx high_end=0x%llx)\\n\",\n cmos_30_31, cmos_34_35, cmos_5b_5d, ram_end, high_ram_end);\n\n /* Base memory: 640 KB */\n cmos_write(0x15, 640 & 0xFF);\n cmos_write(0x16, 640 >> 8);\n\n /* Extended memory 1-16MB range in KB */\n cmos_write(0x17, cmos_17_18 & 0xFF);\n cmos_write(0x18, cmos_17_18 >> 8);\n\n /* Extended memory 1-64MB range in KB */\n cmos_write(0x30, cmos_30_31 & 0xFF);\n cmos_write(0x31, cmos_30_31 >> 8);\n\n /* Extended memory above 16MB in 64KB blocks */\n cmos_write(0x34, cmos_34_35 & 0xFF);\n cmos_write(0x35, cmos_34_35 >> 8);\n\n /* Extended memory above 4GB in 64KB blocks (24-bit) */\n cmos_write(0x5B, cmos_5b_5d & 0xFF);\n cmos_write(0x5C, (cmos_5b_5d >> 8) & 0xFF);\n cmos_write(0x5D, (cmos_5b_5d >> 16) & 0xFF);\n\n /* Bit 7 of port 0x70 is the chipset NMI mask; clear it so we don't\n * hand off to legacy BIOS with NMI delivery gated. */\n outb(0x70, 0x0D);\n inb(0x71); /* complete the CMOS access cycle */\n}\n\n/*\n * Build E820 memory map based on UEFI GetMemoryMap\n * Return the number of entries in the E820 map\n */\nint build_e820_map(struct csmwrap_priv *priv, EFI_MEMORY_DESCRIPTOR *memory_map, UINTN memory_map_size, UINTN descriptor_size)\n{\n EFI_MEMORY_DESCRIPTOR *memory_map_end;\n EFI_MEMORY_DESCRIPTOR *memory_map_ptr;\n\n memory_map_end = (EFI_MEMORY_DESCRIPTOR *)((uint8_t *)memory_map + memory_map_size);\n\n dump_efi_memory_map(memory_map, memory_map_size, descriptor_size);\n\n /* Process each memory descriptor and convert to E820 format */\n for (memory_map_ptr = memory_map; \n memory_map_ptr < memory_map_end;\n memory_map_ptr = NextMemoryDescriptor(memory_map_ptr, descriptor_size)) {\n\n uint64_t start = memory_map_ptr->PhysicalStart;\n uint64_t end = start + (memory_map_ptr->NumberOfPages * EFI_PAGE_SIZE);\n uint32_t type = convert_memory_type(memory_map_ptr->Type);\n \n /* Skip zero-length regions */\n if (start == end)\n continue;\n\n e820_add(priv, start, end - start, type);\n }\n\n /* Remove whole 1MB, we are going to fix it later */\n e820_remove(priv, 0, 0x100000);\n /*\n * Reproduce SeaBIOS's initial low-memory layout: 639KB usable + 1KB EBDA.\n * SeaBIOS recomputes its own e820 from endlow/ebda_seg during init and\n * may grow the EBDA further (option ROMs allocating BBS/ATA/MPT space),\n * so this map is a starting snapshot, not the final OS-visible map.\n * Reporting only 512KB here previously confused HIMEM.SYS / EMM386.\n */\n e820_add(priv, 0, 0x9FC00, EfiAcpiAddressRangeMemory);\n e820_add(priv, 0x9FC00, 0x400, EfiAcpiAddressRangeReserved);\n /* Reserve Expansion BIOS (video RAM, option ROMs, system ROM) */\n e820_add(priv, 0xa0000, 0x100000 - 0xa0000, EfiAcpiAddressRangeReserved);\n\n dump_map(priv);\n\n e820_update_cmos(priv);\n\n return 0;\n}\n" }, { "path": "src/edk2/Acpi.h", "content": "/** @file\n This file contains the latest ACPI definitions that are\n consumed by drivers that do not care about ACPI versions.\n\n Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
\n Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
\n Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _ACPI_H_\n#define _ACPI_H_\n\n#include \"Acpi65.h\"\n\n#endif\n" }, { "path": "src/edk2/Acpi10.h", "content": "/** @file\n ACPI 1.0b definitions from the ACPI Specification, revision 1.0b\n\nCopyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\nCopyright (c) 2020, Arm Limited. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_1_0_H_\n#define _ACPI_1_0_H_\n\n#include \"Edk2Compat.h\"\n#include \"AcpiAml.h\"\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure.\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_COMMON_HEADER;\n\n#pragma pack(1)\n///\n/// The common ACPI description table header. This structure prefaces most ACPI tables.\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT8 Revision;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT64 OemTableId;\n UINT32 OemRevision;\n UINT32 CreatorId;\n UINT32 CreatorRevision;\n} EFI_ACPI_DESCRIPTION_HEADER;\n#pragma pack()\n\n//\n// Define for Descriptor\n//\n#define ACPI_SMALL_ITEM_FLAG 0x00\n#define ACPI_LARGE_ITEM_FLAG 0x01\n\n//\n// Small Item Descriptor Name\n//\n#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04\n#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05\n#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06\n#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07\n#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08\n#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09\n#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E\n#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F\n\n//\n// Large Item Descriptor Name\n//\n#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01\n#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04\n#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05\n#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06\n#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07\n#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08\n#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09\n#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A\n\n//\n// Small Item Descriptor Value\n//\n#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22\n#define ACPI_IRQ_DESCRIPTOR 0x23\n#define ACPI_DMA_DESCRIPTOR 0x2A\n#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30\n#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31\n#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38\n#define ACPI_IO_PORT_DESCRIPTOR 0x47\n#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B\n#define ACPI_END_TAG_DESCRIPTOR 0x79\n\n//\n// Large Item Descriptor Value\n//\n#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81\n#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85\n#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86\n#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87\n#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88\n#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89\n#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A\n#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A\n\n//\n// Resource Type\n//\n#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00\n#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01\n#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02\n\n///\n/// Power Management Timer frequency is fixed at 3.579545MHz.\n///\n#define ACPI_TIMER_FREQUENCY 3579545\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// The common definition of QWORD, DWORD, and WORD\n/// Address Space Descriptors.\n///\ntypedef PACKED struct {\n UINT8 Desc;\n UINT16 Len;\n UINT8 ResType;\n UINT8 GenFlag;\n UINT8 SpecificFlag;\n UINT64 AddrSpaceGranularity;\n UINT64 AddrRangeMin;\n UINT64 AddrRangeMax;\n UINT64 AddrTranslationOffset;\n UINT64 AddrLen;\n} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;\n\ntypedef PACKED union {\n UINT8 Byte;\n PACKED struct {\n UINT8 Length : 3;\n UINT8 Name : 4;\n UINT8 Type : 1;\n } Bits;\n} ACPI_SMALL_RESOURCE_HEADER;\n\ntypedef PACKED struct {\n PACKED union {\n UINT8 Byte;\n PACKED struct {\n UINT8 Name : 7;\n UINT8 Type : 1;\n } Bits;\n } Header;\n UINT16 Length;\n} ACPI_LARGE_RESOURCE_HEADER;\n\n///\n/// IRQ Descriptor.\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT16 Mask;\n} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;\n\n///\n/// IRQ Descriptor.\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT16 Mask;\n UINT8 Information;\n} EFI_ACPI_IRQ_DESCRIPTOR;\n\n///\n/// DMA Descriptor.\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT8 ChannelMask;\n UINT8 Information;\n} EFI_ACPI_DMA_DESCRIPTOR;\n\n///\n/// I/O Port Descriptor\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT8 Information;\n UINT16 BaseAddressMin;\n UINT16 BaseAddressMax;\n UINT8 Alignment;\n UINT8 Length;\n} EFI_ACPI_IO_PORT_DESCRIPTOR;\n\n///\n/// Fixed Location I/O Port Descriptor.\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT16 BaseAddress;\n UINT8 Length;\n} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;\n\n///\n/// 24-Bit Memory Range Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 Information;\n UINT16 BaseAddressMin;\n UINT16 BaseAddressMax;\n UINT16 Alignment;\n UINT16 Length;\n} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR;\n\n///\n/// 32-Bit Memory Range Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 Information;\n UINT32 BaseAddressMin;\n UINT32 BaseAddressMax;\n UINT32 Alignment;\n UINT32 Length;\n} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR;\n\n///\n/// Fixed 32-Bit Fixed Memory Range Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 Information;\n UINT32 BaseAddress;\n UINT32 Length;\n} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;\n\n///\n/// QWORD Address Space Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 ResType;\n UINT8 GenFlag;\n UINT8 SpecificFlag;\n UINT64 AddrSpaceGranularity;\n UINT64 AddrRangeMin;\n UINT64 AddrRangeMax;\n UINT64 AddrTranslationOffset;\n UINT64 AddrLen;\n} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR;\n\n///\n/// DWORD Address Space Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 ResType;\n UINT8 GenFlag;\n UINT8 SpecificFlag;\n UINT32 AddrSpaceGranularity;\n UINT32 AddrRangeMin;\n UINT32 AddrRangeMax;\n UINT32 AddrTranslationOffset;\n UINT32 AddrLen;\n} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR;\n\n///\n/// WORD Address Space Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 ResType;\n UINT8 GenFlag;\n UINT8 SpecificFlag;\n UINT16 AddrSpaceGranularity;\n UINT16 AddrRangeMin;\n UINT16 AddrRangeMax;\n UINT16 AddrTranslationOffset;\n UINT16 AddrLen;\n} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR;\n\n///\n/// Extended Interrupt Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 InterruptVectorFlags;\n UINT8 InterruptTableLength;\n UINT32 InterruptNumber[1];\n} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR;\n\n#pragma pack()\n\n///\n/// The End tag identifies an end of resource data.\n///\ntypedef struct {\n UINT8 Desc;\n UINT8 Checksum;\n} EFI_ACPI_END_TAG_DESCRIPTOR;\n\n//\n// General use definitions\n//\n#define EFI_ACPI_RESERVED_BYTE 0x00\n#define EFI_ACPI_RESERVED_WORD 0x0000\n#define EFI_ACPI_RESERVED_DWORD 0x00000000\n#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000\n\n//\n// Resource Type Specific Flags\n// Ref ACPI specification 6.4.3.5.5\n//\n// Bit [0] : Write Status, _RW\n//\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)\n//\n// Bit [2:1] : Memory Attributes, _MEM\n//\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)\n//\n// Bit [4:3] : Memory Attributes, _MTP\n//\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)\n#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)\n//\n// Bit [5] : Memory to I/O Translation, _TTP\n//\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)\n#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)\n\n//\n// IRQ Information\n// Ref ACPI specification 6.4.2.1\n//\n#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10\n#define EFI_ACPI_IRQ_SHARABLE 0x10\n\n#define EFI_ACPI_IRQ_POLARITY_MASK 0x08\n#define EFI_ACPI_IRQ_HIGH_TRUE 0x00\n#define EFI_ACPI_IRQ_LOW_FALSE 0x08\n\n#define EFI_ACPI_IRQ_MODE 0x01\n#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00\n#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01\n\n//\n// DMA Information\n// Ref ACPI specification 6.4.2.2\n//\n#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60\n#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00\n#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20\n#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40\n#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60\n\n#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04\n#define EFI_ACPI_DMA_BUS_MASTER 0x04\n\n#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03\n#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00\n#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01\n#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02\n\n//\n// IO Information\n// Ref ACPI specification 6.4.2.5\n//\n#define EFI_ACPI_IO_DECODE_MASK 0x01\n#define EFI_ACPI_IO_DECODE_16_BIT 0x01\n#define EFI_ACPI_IO_DECODE_10_BIT 0x00\n\n//\n// Memory Information\n// Ref ACPI specification 6.4.3.4\n//\n#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01\n#define EFI_ACPI_MEMORY_WRITABLE 0x01\n#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00\n\n//\n// Interrupt Vector Flags definitions for Extended Interrupt Descriptor\n// Ref ACPI specification 6.4.3.6\n//\n#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0\n#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1\n#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2\n#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3\n#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n//\n// ACPI 1.0b table structures\n//\n\n///\n/// Root System Description Pointer Structure.\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Reserved;\n UINT32 RsdtAddress;\n} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 1.0b specification).\n///\n#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT).\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 IntModel;\n UINT8 Reserved1;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 Reserved2;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 Reserved3;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT8 Reserved4;\n UINT8 Reserved5;\n UINT8 Reserved6;\n UINT32 Flags;\n} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 1.0b specification).\n///\n#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01\n\n#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0\n#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_1_0_WBINVD BIT0\n#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_1_0_PROC_C1 BIT2\n#define EFI_ACPI_1_0_P_LVL2_UP BIT3\n#define EFI_ACPI_1_0_PWR_BUTTON BIT4\n#define EFI_ACPI_1_0_SLP_BUTTON BIT5\n#define EFI_ACPI_1_0_FIX_RTC BIT6\n#define EFI_ACPI_1_0_RTC_S4 BIT7\n#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_1_0_DCK_CAP BIT9\n\n///\n/// Firmware ACPI Control Structure.\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT8 Reserved[40];\n} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// Firmware Control Structure Feature Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_1_0_S4BIOS_F BIT0\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform-specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 1.0b specification).\n///\n#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_1_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x05 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_1_0_IO_APIC 0x01\n#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 SystemVectorBase;\n} EFI_ACPI_1_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterruptVector;\n UINT16 Flags;\n} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Non-Maskable Interrupt Source Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterruptVector;\n} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicInti;\n} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer.\n///\n#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table.\n///\n#define EFI_ACPI_1_0_APIC_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"DSDT\" Differentiated System Description Table.\n///\n#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure.\n///\n#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FACP\" Fixed ACPI Description Table.\n///\n#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"PSDT\" Persistent System Description Table.\n///\n#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RSDT\" Root System Description Table.\n///\n#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table.\n///\n#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table.\n///\n#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi20.h", "content": "/** @file\n ACPI 2.0 definitions from the ACPI Specification, revision 2.0\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_2_0_H_\n#define _ACPI_2_0_H_\n\n#include \"Acpi10.h\"\n\n//\n// Define for Descriptor\n//\n#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\n\n#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// Generic Register Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AddressSize;\n UINT64 RegisterAddress;\n} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR;\n\n#pragma pack()\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 2.0 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 Reserved;\n UINT64 Address;\n} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_2_0_SYSTEM_MEMORY 0\n#define EFI_ACPI_2_0_SYSTEM_IO 1\n#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_2_0_SMBUS 4\n#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// ACPI 2.0 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_2_0_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT8 Reserved2[3];\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\n#define EFI_ACPI_2_0_8042 BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_2_0_WBINVD BIT0\n#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_2_0_PROC_C1 BIT2\n#define EFI_ACPI_2_0_P_LVL2_UP BIT3\n#define EFI_ACPI_2_0_PWR_BUTTON BIT4\n#define EFI_ACPI_2_0_SLP_BUTTON BIT5\n#define EFI_ACPI_2_0_FIX_RTC BIT6\n#define EFI_ACPI_2_0_RTC_S4 BIT7\n#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_2_0_DCK_CAP BIT9\n#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\n#define EFI_ACPI_2_0_SEALED_CASE BIT11\n#define EFI_ACPI_2_0_HEADLESS BIT12\n#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved[31];\n} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_2_0_S4BIOS_F BIT0\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x09 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_2_0_IO_APIC 0x01\n#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_2_0_IO_SAPIC 0x06\n#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07\n#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_2_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 Reserved;\n} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 2.0 spec.)\n///\n#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"SPIC\" Multiple SAPIC Description Table\n///\n/// BUGBUG: Don't know where this came from except SR870BN4 uses it.\n/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053\n///\n#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"DBGP\" MS Bebug Port Spec\n///\n#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SRAT\" Static Resource Affinity Table\n///\n#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi30.h", "content": "/** @file\n ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_3_0_H_\n#define _ACPI_3_0_H_\n\n#include \"Acpi20.h\"\n\n///\n/// _CSD Revision for ACPI 3.0\n///\n#define EFI_ACPI_3_0_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 3.0\n///\n#define EFI_ACPI_3_0_AML_CSD_NUM_ENTRIES 6\n\n//\n// Define for Descriptor\n//\n#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B\n\n#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B\n\n///\n/// C-state Coordination Types\n/// See s8.4.2.2 _CSD (C-State Dependency)\n///\n#define ACPI_AML_COORD_TYPE_SW_ALL 0xFC\n#define ACPI_AML_COORD_TYPE_SW_ANY 0xFD\n#define ACPI_AML_COORD_TYPE_HW_ALL 0xFE\n\n///\n/// _PSD Revision for ACPI 3.0\n// See s8.4.4.5 _PSD (P-State Dependency)\n///\n#define EFI_ACPI_3_0_AML_PSD_REVISION 0\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// Extended Address Space Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 ResType;\n UINT8 GenFlag;\n UINT8 SpecificFlag;\n UINT8 RevisionId;\n UINT8 Reserved;\n UINT64 AddrSpaceGranularity;\n UINT64 AddrRangeMin;\n UINT64 AddrRangeMax;\n UINT64 AddrTranslationOffset;\n UINT64 AddrLen;\n UINT64 TypeSpecificAttribute;\n} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR;\n\n#pragma pack()\n\n//\n// Memory Type Specific Flags\n//\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010\n#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 3.0 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_3_0_SYSTEM_MEMORY 0\n#define EFI_ACPI_3_0_SYSTEM_IO 1\n#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_3_0_SMBUS 4\n#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_3_0_UNDEFINED 0\n#define EFI_ACPI_3_0_BYTE 1\n#define EFI_ACPI_3_0_WORD 2\n#define EFI_ACPI_3_0_DWORD 3\n#define EFI_ACPI_3_0_QWORD 4\n\n//\n// ACPI 3.0 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)\n///\n#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_3_0_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT8 Reserved2[3];\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0\n#define EFI_ACPI_3_0_8042 BIT1\n#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_3_0_WBINVD BIT0\n#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_3_0_PROC_C1 BIT2\n#define EFI_ACPI_3_0_P_LVL2_UP BIT3\n#define EFI_ACPI_3_0_PWR_BUTTON BIT4\n#define EFI_ACPI_3_0_SLP_BUTTON BIT5\n#define EFI_ACPI_3_0_FIX_RTC BIT6\n#define EFI_ACPI_3_0_RTC_S4 BIT7\n#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_3_0_DCK_CAP BIT9\n#define EFI_ACPI_3_0_RESET_REG_SUP BIT10\n#define EFI_ACPI_3_0_SEALED_CASE BIT11\n#define EFI_ACPI_3_0_HEADLESS BIT12\n#define EFI_ACPI_3_0_CPU_SW_SLP BIT13\n#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14\n#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved[31];\n} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_3_0_S4BIOS_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_3_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x09 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_3_0_IO_APIC 0x01\n#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_3_0_IO_SAPIC 0x06\n#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07\n#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_3_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_3_0_POLARITY (3 << 0)\n#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02\n\n//\n// SRAT structure types.\n// All other values between 0x02 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT8 Reserved[4];\n} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 3.0 spec.)\n///\n#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WSPT\" Windows Specific Properties Table\n///\n#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'P', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi40.h", "content": "/** @file\n ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010\n\n Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_4_0_H_\n#define _ACPI_4_0_H_\n\n#include \"Acpi30.h\"\n\n///\n/// _CSD Revision for ACPI 4.0\n///\n#define EFI_ACPI_4_0_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 4.0\n///\n#define EFI_ACPI_4_0_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 4.0\n///\n#define EFI_ACPI_4_0_AML_PSD_REVISION 0\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 4.0 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_4_0_SYSTEM_MEMORY 0\n#define EFI_ACPI_4_0_SYSTEM_IO 1\n#define EFI_ACPI_4_0_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_4_0_SMBUS 4\n#define EFI_ACPI_4_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_4_0_UNDEFINED 0\n#define EFI_ACPI_4_0_BYTE 1\n#define EFI_ACPI_4_0_WORD 2\n#define EFI_ACPI_4_0_DWORD 3\n#define EFI_ACPI_4_0_QWORD 4\n\n//\n// ACPI 4.0 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 4.0b spec.)\n///\n#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_4_0_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT8 Reserved2[3];\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_4_0_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_4_0_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_4_0_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_4_0_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_4_0_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_4_0_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_4_0_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER 7\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0\n#define EFI_ACPI_4_0_8042 BIT1\n#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_4_0_WBINVD BIT0\n#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_4_0_PROC_C1 BIT2\n#define EFI_ACPI_4_0_P_LVL2_UP BIT3\n#define EFI_ACPI_4_0_PWR_BUTTON BIT4\n#define EFI_ACPI_4_0_SLP_BUTTON BIT5\n#define EFI_ACPI_4_0_FIX_RTC BIT6\n#define EFI_ACPI_4_0_RTC_S4 BIT7\n#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_4_0_DCK_CAP BIT9\n#define EFI_ACPI_4_0_RESET_REG_SUP BIT10\n#define EFI_ACPI_4_0_SEALED_CASE BIT11\n#define EFI_ACPI_4_0_HEADLESS BIT12\n#define EFI_ACPI_4_0_CPU_SW_SLP BIT13\n#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14\n#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_4_0_S4BIOS_F BIT0\n#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_4_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0B an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_4_0_IO_APIC 0x01\n#define EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_4_0_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_4_0_IO_SAPIC 0x06\n#define EFI_ACPI_4_0_LOCAL_SAPIC 0x07\n#define EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_4_0_LOCAL_X2APIC_NMI 0x0A\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_4_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_4_0_POLARITY (3 << 0)\n#define EFI_ACPI_4_0_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x03 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_4_0_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_4_0_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE 0x00\n#define EFI_ACPI_4_0_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_4_0_ERROR_SEVERITY_NONE 0x03\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR 0x09\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03\n#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03\n#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_4_0_ERST_NOOP 0x04\n#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_4_0_ERST_ADD 0x08\n#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09\n#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_4_0_ERST_STALL 0x0C\n#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_4_0_ERST_GOTO 0x0F\n#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 4.0 spec.)\n///\n#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_4_0_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_4_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_4_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_4_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_4_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_4_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_4_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_4_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_4_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_4_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_4_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_4_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_4_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_4_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Enlightenment Table\n///\n#define EFI_ACPI_4_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_4_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_4_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi50.h", "content": "/** @file\n ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.\n\n Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
\n Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.
\n Copyright (c) 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_5_0_H_\n#define _ACPI_5_0_H_\n\n#include \"Acpi40.h\"\n\n///\n/// _CSD Revision for ACPI 5.0\n///\n#define EFI_ACPI_5_0_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 5.0\n///\n#define EFI_ACPI_5_0_AML_CSD_NUM_ENTRIES 6\n\n//\n// Define for Descriptor\n//\n#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A\n#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C\n#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E\n\n#define ACPI_FIXED_DMA_DESCRIPTOR 0x55\n#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C\n#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E\n\n///\n/// _PSD Revision for ACPI 5.0\n///\n#define EFI_ACPI_5_0_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 5.0\n///\n#define EFI_ACPI_5_0_AML_CPC_REVISION 1\n\n#pragma pack(1)\n\n///\n/// Generic DMA Descriptor.\n///\ntypedef PACKED struct {\n ACPI_SMALL_RESOURCE_HEADER Header;\n UINT16 DmaRequestLine;\n UINT16 DmaChannel;\n UINT8 DmaTransferWidth;\n} EFI_ACPI_FIXED_DMA_DESCRIPTOR;\n\n///\n/// GPIO Connection Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT8 ConnectionType;\n UINT16 GeneralFlags;\n UINT16 InterruptFlags;\n UINT8 PinConfiguration;\n UINT16 OutputDriveStrength;\n UINT16 DebounceTimeout;\n UINT16 PinTableOffset;\n UINT8 ResourceSourceIndex;\n UINT16 ResourceSourceNameOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;\n\n#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0\n#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1\n\n///\n/// Serial Bus Resource Descriptor (Generic)\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT8 ResourceSourceIndex;\n UINT8 SerialBusType;\n UINT8 GeneralFlags;\n UINT16 TypeSpecificFlags;\n UINT8 TypeSpecificRevisionId;\n UINT16 TypeDataLength;\n // Type specific data\n} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;\n\n#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C 0x1\n#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_SPI 0x2\n#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_UART 0x3\n\n///\n/// Serial Bus Resource Descriptor (I2C)\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT8 ResourceSourceIndex;\n UINT8 SerialBusType;\n UINT8 GeneralFlags;\n UINT16 TypeSpecificFlags;\n UINT8 TypeSpecificRevisionId;\n UINT16 TypeDataLength;\n UINT32 ConnectionSpeed;\n UINT16 SlaveAddress;\n} EFI_ACPI_SERIAL_BUS_RESOURCE_I2C_DESCRIPTOR;\n\n///\n/// Serial Bus Resource Descriptor (SPI)\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT8 ResourceSourceIndex;\n UINT8 SerialBusType;\n UINT8 GeneralFlags;\n UINT16 TypeSpecificFlags;\n UINT8 TypeSpecificRevisionId;\n UINT16 TypeDataLength;\n UINT32 ConnectionSpeed;\n UINT8 DataBitLength;\n UINT8 Phase;\n UINT8 Polarity;\n UINT16 DeviceSelection;\n} EFI_ACPI_SERIAL_BUS_RESOURCE_SPI_DESCRIPTOR;\n\n///\n/// Serial Bus Resource Descriptor (UART)\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT8 ResourceSourceIndex;\n UINT8 SerialBusType;\n UINT8 GeneralFlags;\n UINT16 TypeSpecificFlags;\n UINT8 TypeSpecificRevisionId;\n UINT16 TypeDataLength;\n UINT32 DefaultBaudRate;\n UINT16 RxFIFO;\n UINT16 TxFIFO;\n UINT8 Parity;\n UINT8 SerialLinesEnabled;\n} EFI_ACPI_SERIAL_BUS_RESOURCE_UART_DESCRIPTOR;\n\n#pragma pack()\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 5.0 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_5_0_SYSTEM_MEMORY 0\n#define EFI_ACPI_5_0_SYSTEM_IO 1\n#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_5_0_SMBUS 4\n#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_5_0_UNDEFINED 0\n#define EFI_ACPI_5_0_BYTE 1\n#define EFI_ACPI_5_0_WORD 2\n#define EFI_ACPI_5_0_DWORD 3\n#define EFI_ACPI_5_0_QWORD 4\n\n//\n// ACPI 5.0 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_5_0_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT8 Reserved2[3];\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_5_0_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_5_0_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_5_0_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_5_0_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_5_0_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_5_0_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_5_0_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0\n#define EFI_ACPI_5_0_8042 BIT1\n#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_0_WBINVD BIT0\n#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_5_0_PROC_C1 BIT2\n#define EFI_ACPI_5_0_P_LVL2_UP BIT3\n#define EFI_ACPI_5_0_PWR_BUTTON BIT4\n#define EFI_ACPI_5_0_SLP_BUTTON BIT5\n#define EFI_ACPI_5_0_FIX_RTC BIT6\n#define EFI_ACPI_5_0_RTC_S4 BIT7\n#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_5_0_DCK_CAP BIT9\n#define EFI_ACPI_5_0_RESET_REG_SUP BIT10\n#define EFI_ACPI_5_0_SEALED_CASE BIT11\n#define EFI_ACPI_5_0_HEADLESS BIT12\n#define EFI_ACPI_5_0_CPU_SW_SLP BIT13\n#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14\n#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_0_S4BIOS_F BIT0\n#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_5_0_IO_APIC 0x01\n#define EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_5_0_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_5_0_IO_SAPIC 0x06\n#define EFI_ACPI_5_0_LOCAL_SAPIC 0x07\n#define EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_5_0_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_5_0_GIC 0x0B\n#define EFI_ACPI_5_0_GICD 0x0C\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_5_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_0_POLARITY (3 << 0)\n#define EFI_ACPI_5_0_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicId;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n} EFI_ACPI_5_0_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_0_GIC_ENABLED BIT0\n#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT32 Reserved2;\n} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x03 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_5_0_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_5_0_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_5_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01\n#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_5_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_5_0_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01\n#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED\n#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior to when the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 PhysicalAddress;\n UINT32 GlobalFlags;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Global Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0\n#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE 0x00\n#define EFI_ACPI_5_0_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE 0x03\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR 0x09\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03\n#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_5_0_ERST_NOOP 0x04\n#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_5_0_ERST_ADD 0x08\n#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09\n#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_5_0_ERST_STALL 0x0C\n#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_5_0_ERST_GOTO 0x0F\n#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_5_0_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 5.0 spec.)\n///\n#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_5_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 GenerateSci : 1;\n} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 SciDoorbell : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_5_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_5_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_5_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_5_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_5_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_5_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_5_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_5_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_5_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_5_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_5_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_5_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_5_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_5_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_5_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_5_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_5_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi51.h", "content": "/** @file\n ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.\n\n Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
\n Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
\n (C) Copyright 2015 Hewlett Packard Enterprise Development LP
\n Copyright (c) 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_5_1_H_\n#define _ACPI_5_1_H_\n\n#include \"Acpi50.h\"\n\n///\n/// _CSD Revision for ACPI 5.1\n///\n#define EFI_ACPI_5_1_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 5.1\n///\n#define EFI_ACPI_5_1_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 5.1\n///\n#define EFI_ACPI_5_1_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 5.1\n///\n#define EFI_ACPI_5_1_AML_CPC_REVISION 2\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 5.1 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_5_1_SYSTEM_MEMORY 0\n#define EFI_ACPI_5_1_SYSTEM_IO 1\n#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_5_1_SMBUS 4\n#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_5_1_UNDEFINED 0\n#define EFI_ACPI_5_1_BYTE 1\n#define EFI_ACPI_5_1_WORD 2\n#define EFI_ACPI_5_1_DWORD 3\n#define EFI_ACPI_5_1_QWORD 4\n\n//\n// ACPI 5.1 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_5_1_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05\n#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_5_1_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_5_1_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_5_1_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_5_1_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_5_1_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_5_1_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_5_1_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_5_1_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0\n#define EFI_ACPI_5_1_8042 BIT1\n#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_1_WBINVD BIT0\n#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1\n#define EFI_ACPI_5_1_PROC_C1 BIT2\n#define EFI_ACPI_5_1_P_LVL2_UP BIT3\n#define EFI_ACPI_5_1_PWR_BUTTON BIT4\n#define EFI_ACPI_5_1_SLP_BUTTON BIT5\n#define EFI_ACPI_5_1_FIX_RTC BIT6\n#define EFI_ACPI_5_1_RTC_S4 BIT7\n#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8\n#define EFI_ACPI_5_1_DCK_CAP BIT9\n#define EFI_ACPI_5_1_RESET_REG_SUP BIT10\n#define EFI_ACPI_5_1_SEALED_CASE BIT11\n#define EFI_ACPI_5_1_HEADLESS BIT12\n#define EFI_ACPI_5_1_CPU_SW_SLP BIT13\n#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14\n#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_1_S4BIOS_F BIT0\n#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_1_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_5_1_IO_APIC 0x01\n#define EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_5_1_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_5_1_IO_SAPIC 0x06\n#define EFI_ACPI_5_1_LOCAL_SAPIC 0x07\n#define EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_5_1_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_5_1_GIC 0x0B\n#define EFI_ACPI_5_1_GICD 0x0C\n#define EFI_ACPI_5_1_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_5_1_GICR 0x0E\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_5_1_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_5_1_POLARITY (3 << 0)\n#define EFI_ACPI_5_1_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n} EFI_ACPI_5_1_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GIC_ENABLED BIT0\n#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_5_1_GIC_V1 0x01\n#define EFI_ACPI_5_1_GIC_V2 0x02\n#define EFI_ACPI_5_1_GIC_V3 0x03\n#define EFI_ACPI_5_1_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_5_1_GICR_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x04 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_5_1_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_5_1_GICC_AFFINITY 0x03\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_5_1_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_5_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01\n#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_5_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_5_1_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_5_1_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior to when the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_5_1_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0\n#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// SBSA Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_5_1_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_5_1_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_5_1_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_5_1_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR 0x09\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03\n#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_5_1_ERST_NOOP 0x04\n#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_5_1_ERST_ADD 0x08\n#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09\n#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_5_1_ERST_STALL 0x0C\n#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_5_1_ERST_GOTO 0x0F\n#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_5_1_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 5.1 spec.)\n///\n#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_5_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 GenerateSci : 1;\n} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 SciDoorbell : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_5_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_5_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_5_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_5_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_5_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_5_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_5_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_5_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_5_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_5_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_5_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_5_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_5_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_5_1_IO_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_5_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_5_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_5_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_5_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_5_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_5_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_5_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_5_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_5_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi60.h", "content": "/** @file\n ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.\n\n Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
\n (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
\n Copyright (c) 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_6_0_H_\n#define _ACPI_6_0_H_\n\n#include \"Acpi51.h\"\n\n///\n/// _CSD Revision for ACPI 6.0\n///\n#define EFI_ACPI_6_0_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.0\n///\n#define EFI_ACPI_6_0_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 6.0\n///\n#define EFI_ACPI_6_0_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.0\n///\n#define EFI_ACPI_6_0_AML_CPC_REVISION 2\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 6.0 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_0_SYSTEM_MEMORY 0\n#define EFI_ACPI_6_0_SYSTEM_IO 1\n#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_6_0_SMBUS 4\n#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_0_UNDEFINED 0\n#define EFI_ACPI_6_0_BYTE 1\n#define EFI_ACPI_6_0_WORD 2\n#define EFI_ACPI_6_0_DWORD 3\n#define EFI_ACPI_6_0_QWORD 4\n\n//\n// ACPI 6.0 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_0_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x00\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_0_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_0_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_0_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_0_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_0_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_0_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_0_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_0_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_0_8042 BIT1\n#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_0_WBINVD BIT0\n#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_0_PROC_C1 BIT2\n#define EFI_ACPI_6_0_P_LVL2_UP BIT3\n#define EFI_ACPI_6_0_PWR_BUTTON BIT4\n#define EFI_ACPI_6_0_SLP_BUTTON BIT5\n#define EFI_ACPI_6_0_FIX_RTC BIT6\n#define EFI_ACPI_6_0_RTC_S4 BIT7\n#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_0_DCK_CAP BIT9\n#define EFI_ACPI_6_0_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_0_SEALED_CASE BIT11\n#define EFI_ACPI_6_0_HEADLESS BIT12\n#define EFI_ACPI_6_0_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_0_S4BIOS_F BIT0\n#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.0 Errata A spec.)\n///\n#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_0_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_0_IO_APIC 0x01\n#define EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_0_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_0_IO_SAPIC 0x06\n#define EFI_ACPI_6_0_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_0_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_0_GIC 0x0B\n#define EFI_ACPI_6_0_GICD 0x0C\n#define EFI_ACPI_6_0_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_0_GICR 0x0E\n#define EFI_ACPI_6_0_GIC_ITS 0x0F\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_0_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_0_POLARITY (3 << 0)\n#define EFI_ACPI_6_0_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_0_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GIC_ENABLED BIT0\n#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_0_GIC_V1 0x01\n#define EFI_ACPI_6_0_GIC_V2 0x02\n#define EFI_ACPI_6_0_GIC_V3 0x03\n#define EFI_ACPI_6_0_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_0_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_0_GIC_ITS_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x04 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_0_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_0_GICC_AFFINITY 0x03\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_0_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01\n#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_0_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_0_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior to when the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_0_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// SBSA Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.0 spec.)\n//\n#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 MemoryDevicePhysicalID;\n UINT16 MemoryDeviceRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 MemoryDeviceRegionSize;\n UINT64 RegionOffset;\n UINT64 MemoryDevicePhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 MemoryDeviceStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 Reserved_18[6];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_0_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_0_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_0_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_0_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR 0x09\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_0_ERST_NOOP 0x04\n#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_0_ERST_ADD 0x08\n#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_0_ERST_STALL 0x0C\n#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_0_ERST_GOTO 0x0F\n#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_0_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.0 spec.)\n///\n#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 GenerateSci : 1;\n} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 SciDoorbell : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 DoorbellInterrupt;\n UINT8 DoorbellInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 DoorbellInterrupt;\n UINT8 DoorbellInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\n UINT64 DoorbellAckPreserve;\n UINT64 DoorbellAckWrite;\n} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_0_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_0_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_0_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi61.h", "content": "/** @file\n ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.\n\n Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
\n (C) Copyright 2016 Hewlett Packard Enterprise Development LP
\n Copyright (c) 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_6_1_H_\n#define _ACPI_6_1_H_\n\n#include \"Acpi60.h\"\n\n///\n/// _CSD Revision for ACPI 6.1\n///\n#define EFI_ACPI_6_1_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.1\n///\n#define EFI_ACPI_6_1_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 6.1\n///\n#define EFI_ACPI_6_1_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.1\n///\n#define EFI_ACPI_6_1_AML_CPC_REVISION 2\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 6.1 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_1_SYSTEM_MEMORY 0\n#define EFI_ACPI_6_1_SYSTEM_IO 1\n#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_6_1_SMBUS 4\n#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_1_UNDEFINED 0\n#define EFI_ACPI_6_1_BYTE 1\n#define EFI_ACPI_6_1_WORD 2\n#define EFI_ACPI_6_1_DWORD 3\n#define EFI_ACPI_6_1_QWORD 4\n\n//\n// ACPI 6.1 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_1_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_1_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_1_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_1_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_1_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_1_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_1_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_1_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_1_8042 BIT1\n#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_1_WBINVD BIT0\n#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_1_PROC_C1 BIT2\n#define EFI_ACPI_6_1_P_LVL2_UP BIT3\n#define EFI_ACPI_6_1_PWR_BUTTON BIT4\n#define EFI_ACPI_6_1_SLP_BUTTON BIT5\n#define EFI_ACPI_6_1_FIX_RTC BIT6\n#define EFI_ACPI_6_1_RTC_S4 BIT7\n#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_1_DCK_CAP BIT9\n#define EFI_ACPI_6_1_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_1_SEALED_CASE BIT11\n#define EFI_ACPI_6_1_HEADLESS BIT12\n#define EFI_ACPI_6_1_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_1_S4BIOS_F BIT0\n#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_1_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_1_IO_APIC 0x01\n#define EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_1_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_1_IO_SAPIC 0x06\n#define EFI_ACPI_6_1_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_1_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_1_GIC 0x0B\n#define EFI_ACPI_6_1_GICD 0x0C\n#define EFI_ACPI_6_1_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_1_GICR 0x0E\n#define EFI_ACPI_6_1_GIC_ITS 0x0F\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_1_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_1_POLARITY (3 << 0)\n#define EFI_ACPI_6_1_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_1_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GIC_ENABLED BIT0\n#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_1_GIC_V1 0x01\n#define EFI_ACPI_6_1_GIC_V2 0x02\n#define EFI_ACPI_6_1_GIC_V3 0x03\n#define EFI_ACPI_6_1_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_1_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_1_GIC_ITS_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x04 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_1_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_1_GICC_AFFINITY 0x03\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_1_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01\n#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_1_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_1_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior to when the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_1_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// SBSA Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.1 spec.)\n//\n#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\n#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NVDIMMPhysicalID;\n UINT16 NVDIMMRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 NVDIMMRegionSize;\n UINT64 RegionOffset;\n UINT64 NVDIMMPhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 NVDIMMStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\n\n#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 ValidFields;\n UINT8 ManufacturingLocation;\n UINT16 ManufacturingDate;\n UINT8 Reserved_22[2];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_1_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_1_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_1_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_1_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n UINT8 Timestamp[8];\n} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR 0x09\n#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\n#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Version 2 Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\n UINT64 ReadAckPreserve;\n UINT64 ReadAckWrite;\n} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_1_ERST_NOOP 0x04\n#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_1_ERST_ADD 0x08\n#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_1_ERST_STALL 0x0C\n#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_1_ERST_GOTO 0x0F\n#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_1_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09\n#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_1_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.1 spec.)\n///\n#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 GenerateSci : 1;\n} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 SciDoorbell : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 DoorbellInterrupt;\n UINT8 DoorbellInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 DoorbellInterrupt;\n UINT8 DoorbellInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\n UINT64 DoorbellAckPreserve;\n UINT64 DoorbellAckWrite;\n} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_1_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_1_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_1_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi62.h", "content": "/** @file\n ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.\n\n Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
\n Copyright (c) 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_6_2_H_\n#define _ACPI_6_2_H_\n\n#include \"Acpi61.h\"\n\n///\n/// _CSD Revision for ACPI 6.2\n///\n#define EFI_ACPI_6_2_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.2\n///\n#define EFI_ACPI_6_2_AML_CSD_NUM_ENTRIES 6\n\n//\n// Large Item Descriptor Name\n//\n#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D\n#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F\n#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10\n#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11\n#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12\n\n//\n// Large Item Descriptor Value\n//\n#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D\n#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F\n#define ACPI_PIN_GROUP_DESCRIPTOR 0x90\n#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91\n#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92\n\n///\n/// _PSD Revision for ACPI 6.2\n///\n#define EFI_ACPI_6_2_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.2\n///\n#define EFI_ACPI_6_2_AML_CPC_REVISION 3\n\n#pragma pack(1)\n\n///\n/// Pin Function Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT16 Flags;\n UINT8 PinPullConfiguration;\n UINT16 FunctionNumber;\n UINT16 PinTableOffset;\n UINT8 ResourceSourceIndex;\n UINT16 ResourceSourceNameOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR;\n\n///\n/// Pin Configuration Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT16 Flags;\n UINT8 PinConfigurationType;\n UINT32 PinConfigurationValue;\n UINT16 PinTableOffset;\n UINT8 ResourceSourceIndex;\n UINT16 ResourceSourceNameOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR;\n\n///\n/// Pin Group Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT16 Flags;\n UINT16 PinTableOffset;\n UINT16 ResourceLabelOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_PIN_GROUP_DESCRIPTOR;\n\n///\n/// Pin Group Function Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT16 Flags;\n UINT16 FunctionNumber;\n UINT8 ResourceSourceIndex;\n UINT16 ResourceSourceNameOffset;\n UINT16 ResourceSourceLabelOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR;\n\n///\n/// Pin Group Configuration Descriptor\n///\ntypedef PACKED struct {\n ACPI_LARGE_RESOURCE_HEADER Header;\n UINT8 RevisionId;\n UINT16 Flags;\n UINT8 PinConfigurationType;\n UINT32 PinConfigurationValue;\n UINT8 ResourceSourceIndex;\n UINT16 ResourceSourceNameOffset;\n UINT16 ResourceSourceLabelOffset;\n UINT16 VendorDataOffset;\n UINT16 VendorDataLength;\n} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR;\n\n#pragma pack()\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 6.2 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_2_SYSTEM_MEMORY 0\n#define EFI_ACPI_6_2_SYSTEM_IO 1\n#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2\n#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3\n#define EFI_ACPI_6_2_SMBUS 4\n#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_2_UNDEFINED 0\n#define EFI_ACPI_6_2_BYTE 1\n#define EFI_ACPI_6_2_WORD 2\n#define EFI_ACPI_6_2_DWORD 3\n#define EFI_ACPI_6_2_QWORD 4\n\n//\n// ACPI 6.2 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_2_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_2_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_2_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_2_8042 BIT1\n#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_2_WBINVD BIT0\n#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_2_PROC_C1 BIT2\n#define EFI_ACPI_6_2_P_LVL2_UP BIT3\n#define EFI_ACPI_6_2_PWR_BUTTON BIT4\n#define EFI_ACPI_6_2_SLP_BUTTON BIT5\n#define EFI_ACPI_6_2_FIX_RTC BIT6\n#define EFI_ACPI_6_2_RTC_S4 BIT7\n#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_2_DCK_CAP BIT9\n#define EFI_ACPI_6_2_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_2_SEALED_CASE BIT11\n#define EFI_ACPI_6_2_HEADLESS BIT12\n#define EFI_ACPI_6_2_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_2_S4BIOS_F BIT0\n#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_2_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_2_IO_APIC 0x01\n#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_2_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_2_IO_SAPIC 0x06\n#define EFI_ACPI_6_2_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_2_GIC 0x0B\n#define EFI_ACPI_6_2_GICD 0x0C\n#define EFI_ACPI_6_2_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_2_GICR 0x0E\n#define EFI_ACPI_6_2_GIC_ITS 0x0F\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_2_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_2_POLARITY (3 << 0)\n#define EFI_ACPI_6_2_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_2_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GIC_ENABLED BIT0\n#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_2_GIC_V1 0x01\n#define EFI_ACPI_6_2_GIC_V2 0x02\n#define EFI_ACPI_6_2_GIC_V3 0x03\n#define EFI_ACPI_6_2_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_2_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x05 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_2_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_2_GICC_AFFINITY 0x03\n#define EFI_ACPI_6_2_GIC_ITS_AFFINITY 0x04\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)\n\n///\n/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT8 Reserved[2];\n UINT32 ItsId;\n} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_2_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\n#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\n#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\n#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\n#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_2_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior to when the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// SBSA Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.2 spec.)\n//\n#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\n#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NVDIMMPhysicalID;\n UINT16 NVDIMMRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 NVDIMMRegionSize;\n UINT64 RegionOffset;\n UINT64 NVDIMMPhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 NVDIMMStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\n\n#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 ValidFields;\n UINT8 ManufacturingLocation;\n UINT16 ManufacturingDate;\n UINT8 Reserved_22[2];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n//\n// Definition for Platform Capabilities Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT8 HighestValidCapability;\n UINT8 Reserved_5[3];\n UINT32 Capabilities;\n UINT8 Reserved_12[4];\n} EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;\n\n#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0\n#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1\n#define EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2\n\n///\n/// Secure DEVices Table (SDEV)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;\n\n///\n/// SDEV Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\n\n///\n/// Secure Device types\n///\n#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\n#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\n\n///\n/// Secure Device flags\n///\n#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\n\n///\n/// SDEV Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;\n\n///\n/// PCIe Endpoint Device based Secure Device Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n UINT16 PciSegmentNumber;\n UINT16 StartBusNumber;\n UINT16 PciPathOffset;\n UINT16 PciPathLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\n\n///\n/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n UINT16 DeviceIdentifierOffset;\n UINT16 DeviceIdentifierLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_2_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n UINT8 Timestamp[8];\n} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR 0x09\n#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\n#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Version 2 Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\n UINT64 ReadAckPreserve;\n UINT64 ReadAckWrite;\n} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// IA-32 Architecture Deferred Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// HMAT - Heterogeneous Memory Attribute Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[4];\n} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\n\n///\n/// HMAT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01\n\n///\n/// HMAT types\n///\n#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00\n#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\n#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\n\n///\n/// HMAT Structure Header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;\n\n///\n/// Memory Subsystem Address Range Structure flags\n///\ntypedef struct {\n UINT16 ProcessorProximityDomainValid : 1;\n UINT16 MemoryProximityDomainValid : 1;\n UINT16 ReservationHint : 1;\n UINT16 Reserved : 13;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;\n\n///\n/// Memory Subsystem Address Range Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;\n UINT8 Reserved1[2];\n UINT32 ProcessorProximityDomain;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved2[4];\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;\n\n///\n/// System Locality Latency and Bandwidth Information Structure flags\n///\ntypedef struct {\n UINT8 MemoryHierarchy : 5;\n UINT8 Reserved : 3;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\n\n///\n/// System Locality Latency and Bandwidth Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\n UINT8 DataType;\n UINT8 Reserved1[2];\n UINT32 NumberOfInitiatorProximityDomains;\n UINT32 NumberOfTargetProximityDomains;\n UINT8 Reserved2[4];\n UINT64 EntryBaseUnit;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\n\n///\n/// Memory Side Cache Information Structure cache attributes\n///\ntypedef struct {\n UINT32 TotalCacheLevels : 4;\n UINT32 CacheLevel : 4;\n UINT32 CacheAssociativity : 4;\n UINT32 WritePolicy : 4;\n UINT32 CacheLineSize : 16;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\n\n///\n/// Memory Side Cache Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved1[4];\n UINT64 MemorySideCacheSize;\n EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\n UINT8 Reserved2[2];\n UINT16 NumberOfSmbiosHandles;\n} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_2_ERST_NOOP 0x04\n#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_2_ERST_ADD 0x08\n#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_2_ERST_STALL 0x0C\n#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_2_ERST_GOTO 0x0F\n#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_2_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09\n#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_2_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 NotifyOnCompletion : 1;\n} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 PlatformInterrupt : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckWrite;\n} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 3 Extended PCC Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT32 AddressLength;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT32 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckSet;\n UINT8 Reserved1[8];\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\n UINT64 CommandCompleteUpdatePreserve;\n UINT64 CommandCompleteUpdateSet;\n EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;\n\n///\n/// Type 4 Extended PCC Subspace Structure\n///\ntypedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;\n\n#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\n\ntypedef struct {\n UINT32 Signature;\n UINT32 Flags;\n UINT32 Length;\n UINT32 Command;\n} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\n\n///\n/// Platform Debug Trigger Table (PDTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 TriggerCount;\n UINT8 Reserved[3];\n UINT32 TriggerIdentifierArrayOffset;\n} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\n\n///\n/// PDTT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\n\n///\n/// PDTT Platform Communication Channel Identifier Structure\n///\ntypedef struct {\n UINT16 SubChannelIdentifer : 8;\n UINT16 Runtime : 1;\n UINT16 WaitForCompletion : 1;\n UINT16 Reserved : 6;\n} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;\n\n///\n/// PCC Commands Codes used by Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\n#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\n\n///\n/// PPTT Platform Communication Channel\n///\ntypedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC;\n\n///\n/// Processor Properties Topology Table (PPTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\n\n///\n/// PPTT Revision (as defined in ACPI 6.2 spec.)\n///\n#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// PPTT types\n///\n#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00\n#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01\n#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02\n\n///\n/// PPTT Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;\n\n///\n/// For PPTT struct processor flags\n///\n#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0\n#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1\n\n///\n/// Processor hierarchy node structure flags\n///\ntypedef struct {\n UINT32 PhysicalPackage : 1;\n UINT32 AcpiProcessorIdValid : 1;\n UINT32 Reserved : 30;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;\n\n///\n/// Processor hierarchy node structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\n UINT32 Parent;\n UINT32 AcpiProcessorId;\n UINT32 NumberOfPrivateResources;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;\n\n///\n/// Cache Type Structure flags\n///\ntypedef struct {\n UINT32 SizePropertyValid : 1;\n UINT32 NumberOfSetsValid : 1;\n UINT32 AssociativityValid : 1;\n UINT32 AllocationTypeValid : 1;\n UINT32 CacheTypeValid : 1;\n UINT32 WritePolicyValid : 1;\n UINT32 LineSizeValid : 1;\n UINT32 Reserved : 25;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;\n\n///\n/// For cache attributes\n///\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\n#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\n\n///\n/// Cache Type Structure cache attributes\n///\ntypedef struct {\n UINT8 AllocationType : 2;\n UINT8 CacheType : 2;\n UINT8 WritePolicy : 1;\n UINT8 Reserved : 3;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\n\n///\n/// Cache Type Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;\n UINT32 NextLevelOfCache;\n UINT32 Size;\n UINT32 NumberOfSets;\n UINT8 Associativity;\n EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\n UINT16 LineSize;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;\n\n///\n/// ID structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 VendorId;\n UINT64 Level1Id;\n UINT64 Level2Id;\n UINT16 MajorRev;\n UINT16 MinorRev;\n UINT16 SpinRev;\n} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"HMAT\" Heterogeneous Memory Attribute Table\n///\n#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PDTT\" Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PPTT\" Processor Properties Topology Table\n///\n#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SDEV\" Secure DEVices Table\n///\n#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DPPT\" DMA Protection Policy Table\n///\n#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_2_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SDEI\" Software Delegated Exceptions Interface Table\n///\n#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Console Redirection Table\n///\n#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"WSMT\" Windows SMM Security Mitigation Table\n///\n#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi63.h", "content": "/** @file\n ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.\n\n Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
\n Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef _ACPI_6_3_H_\n#define _ACPI_6_3_H_\n\n#include \"Acpi62.h\"\n\n///\n/// _CSD Revision for ACPI 6.3\n///\n#define EFI_ACPI_6_3_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.3\n///\n#define EFI_ACPI_6_3_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 6.3\n///\n#define EFI_ACPI_6_3_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.3\n///\n#define EFI_ACPI_6_3_AML_CPC_REVISION 3\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 6.3 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_3_SYSTEM_MEMORY 0x00\n#define EFI_ACPI_6_3_SYSTEM_IO 0x01\n#define EFI_ACPI_6_3_PCI_CONFIGURATION_SPACE 0x02\n#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER 0x03\n#define EFI_ACPI_6_3_SMBUS 0x04\n#define EFI_ACPI_6_3_SYSTEM_CMOS 0x05\n#define EFI_ACPI_6_3_PCI_BAR_TARGET 0x06\n#define EFI_ACPI_6_3_IPMI 0x07\n#define EFI_ACPI_6_3_GENERAL_PURPOSE_IO 0x08\n#define EFI_ACPI_6_3_GENERIC_SERIAL_BUS 0x09\n#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_3_UNDEFINED 0\n#define EFI_ACPI_6_3_BYTE 1\n#define EFI_ACPI_6_3_WORD 2\n#define EFI_ACPI_6_3_DWORD 3\n#define EFI_ACPI_6_3_QWORD 4\n\n//\n// ACPI 6.3 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_3_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_3_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_3_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_3_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_3_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_3_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_3_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_3_8042 BIT1\n#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_3_WBINVD BIT0\n#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_3_PROC_C1 BIT2\n#define EFI_ACPI_6_3_P_LVL2_UP BIT3\n#define EFI_ACPI_6_3_PWR_BUTTON BIT4\n#define EFI_ACPI_6_3_SLP_BUTTON BIT5\n#define EFI_ACPI_6_3_FIX_RTC BIT6\n#define EFI_ACPI_6_3_RTC_S4 BIT7\n#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_3_DCK_CAP BIT9\n#define EFI_ACPI_6_3_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_3_SEALED_CASE BIT11\n#define EFI_ACPI_6_3_HEADLESS BIT12\n#define EFI_ACPI_6_3_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_3_S4BIOS_F BIT0\n#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_3_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x0D and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_3_IO_APIC 0x01\n#define EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_3_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_3_IO_SAPIC 0x06\n#define EFI_ACPI_6_3_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_3_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_3_GIC 0x0B\n#define EFI_ACPI_6_3_GICD 0x0C\n#define EFI_ACPI_6_3_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_3_GICR 0x0E\n#define EFI_ACPI_6_3_GIC_ITS 0x0F\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_LOCAL_APIC_ENABLED BIT0\n#define EFI_ACPI_6_3_LOCAL_APIC_ONLINE_CAPABLE BIT1\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_3_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_3_POLARITY (3 << 0)\n#define EFI_ACPI_6_3_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2;\n UINT16 SpeOverflowInterrupt;\n} EFI_ACPI_6_3_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GIC_ENABLED BIT0\n#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_3_GIC_V1 0x01\n#define EFI_ACPI_6_3_GIC_V2 0x02\n#define EFI_ACPI_6_3_GIC_V3 0x03\n#define EFI_ACPI_6_3_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_3_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x06 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_3_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_3_GICC_AFFINITY 0x03\n#define EFI_ACPI_6_3_GIC_ITS_AFFINITY 0x04\n#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY 0x05\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)\n\n///\n/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT8 Reserved[2];\n UINT32 ItsId;\n} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;\n\n//\n// Generic Initiator Affinity Structure Device Handle Types\n// All other values between 0x02 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00\n#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01\n\n///\n/// Device Handle - ACPI\n///\ntypedef struct {\n UINT64 AcpiHid;\n UINT32 AcpiUid;\n UINT8 Reserved[4];\n} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;\n\n///\n/// Device Handle - PCI\n///\ntypedef struct {\n UINT16 PciSegment;\n UINT16 PciBdfNumber;\n UINT8 Reserved[12];\n} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;\n\n///\n/// Generic Initiator Affinity Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1;\n UINT8 DeviceHandleType;\n UINT32 ProximityDomain;\n\n union {\n EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;\n EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;\n } DeviceHandle;\n\n UINT32 Flags;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;\n\n///\n/// Generic Initiator Affinity Structure Flags. All other bits are reserved\n/// and must be 0.\n///\n#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_3_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_3_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\n#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\n#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\n#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\n#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_3_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\n\n///\n/// Common Memory Aggregator Device Structure.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Memory Aggregator Device Type\n///\n#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\n\n///\n/// Socket Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\n} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// MemoryController Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT32 ReadLatency;\n UINT32 WriteLatency;\n UINT32 ReadBandwidth;\n UINT32 WriteBandwidth;\n UINT16 OptimalAccessUnit;\n UINT16 OptimalAccessAlignment;\n UINT16 Reserved;\n UINT16 NumberOfProximityDomains;\n // UINT32 ProximityDomain[NumberOfProximityDomains];\n // EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\n} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// DIMM Memory Aggregator Device Structure.\n///\ntypedef struct {\n EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\n UINT16 PhysicalComponentIdentifier;\n UINT16 Reserved;\n UINT32 SizeOfDimm;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:1] = Reserved (must be zero)\n /// Bit [0] = Valid. A one indicates the boot image graphic is valid.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_3_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_3_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior towhen the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n UINT32 VirtualPL2TimerGSIV;\n UINT32 VirtualPL2TimerFlags;\n} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// SBSA Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.3 spec.)\n//\n#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\n#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NVDIMMPhysicalID;\n UINT16 NVDIMMRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 NVDIMMRegionSize;\n UINT64 RegionOffset;\n UINT64 NVDIMMPhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 NVDIMMStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\n\n#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 ValidFields;\n UINT8 ManufacturingLocation;\n UINT16 ManufacturingDate;\n UINT8 Reserved_22[2];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n//\n// Definition for Platform Capabilities Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT8 HighestValidCapability;\n UINT8 Reserved_5[3];\n UINT32 Capabilities;\n UINT8 Reserved_12[4];\n} EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;\n\n#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0\n#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1\n#define EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2\n\n///\n/// Secure DEVices Table (SDEV)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;\n\n///\n/// SDEV Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01\n\n///\n/// Secure Devcice types\n///\n#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\n#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\n\n///\n/// Secure Devcice flags\n///\n#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0\n\n///\n/// SDEV Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;\n\n///\n/// PCIe Endpoint Device based Secure Device Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n UINT16 PciSegmentNumber;\n UINT16 StartBusNumber;\n UINT16 PciPathOffset;\n UINT16 PciPathLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\n\n///\n/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n UINT16 DeviceIdentifierOffset;\n UINT16 DeviceIdentifierLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_3_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n UINT8 Timestamp[8];\n} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR 0x09\n#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\n#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Version 2 Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\n UINT64 ReadAckPreserve;\n UINT64 ReadAckWrite;\n} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// IA-32 Architecture Deferred Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// HMAT - Heterogeneous Memory Attribute Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[4];\n} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\n\n///\n/// HMAT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\n\n///\n/// HMAT types\n///\n#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\n#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\n#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\n\n///\n/// HMAT Structure Header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;\n\n///\n/// Memory Proximity Domain Attributes Structure flags\n///\ntypedef struct {\n UINT16 InitiatorProximityDomainValid : 1;\n UINT16 Reserved : 15;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;\n\n///\n/// Memory Proximity Domain Attributes Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\n UINT8 Reserved1[2];\n UINT32 InitiatorProximityDomain;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved2[20];\n} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;\n\n///\n/// System Locality Latency and Bandwidth Information Structure flags\n///\ntypedef struct {\n UINT8 MemoryHierarchy : 4;\n UINT8 Reserved : 4;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\n\n///\n/// System Locality Latency and Bandwidth Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\n UINT8 DataType;\n UINT8 Reserved1[2];\n UINT32 NumberOfInitiatorProximityDomains;\n UINT32 NumberOfTargetProximityDomains;\n UINT8 Reserved2[4];\n UINT64 EntryBaseUnit;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\n\n///\n/// Memory Side Cache Information Structure cache attributes\n///\ntypedef struct {\n UINT32 TotalCacheLevels : 4;\n UINT32 CacheLevel : 4;\n UINT32 CacheAssociativity : 4;\n UINT32 WritePolicy : 4;\n UINT32 CacheLineSize : 16;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\n\n///\n/// Memory Side Cache Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved1[4];\n UINT64 MemorySideCacheSize;\n EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\n UINT8 Reserved2[2];\n UINT16 NumberOfSmbiosHandles;\n} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_3_ERST_NOOP 0x04\n#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_3_ERST_ADD 0x08\n#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_3_ERST_STALL 0x0C\n#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_3_ERST_GOTO 0x0F\n#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_3_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09\n#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_3_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 NotifyOnCompletion : 1;\n} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 PlatformInterrupt : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckWrite;\n} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 3 Extended PCC Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT32 AddressLength;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT32 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckSet;\n UINT8 Reserved1[8];\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\n UINT64 CommandCompleteUpdatePreserve;\n UINT64 CommandCompleteUpdateSet;\n EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;\n\n///\n/// Type 4 Extended PCC Subspace Structure\n///\ntypedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;\n\n#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\n\ntypedef struct {\n UINT32 Signature;\n UINT32 Flags;\n UINT32 Length;\n UINT32 Command;\n} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\n\n///\n/// Platform Debug Trigger Table (PDTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 TriggerCount;\n UINT8 Reserved[3];\n UINT32 TriggerIdentifierArrayOffset;\n} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\n\n///\n/// PDTT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\n\n///\n/// PDTT Platform Communication Channel Identifier Structure\n///\ntypedef struct {\n UINT16 SubChannelIdentifer : 8;\n UINT16 Runtime : 1;\n UINT16 WaitForCompletion : 1;\n UINT16 TriggerOrder : 1;\n UINT16 Reserved : 5;\n} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;\n\n///\n/// PCC Commands Codes used by Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\n#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\n\n///\n/// PPTT Platform Communication Channel\n///\ntypedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_PCC;\n\n///\n/// Processor Properties Topology Table (PPTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\n\n///\n/// PPTT Revision (as defined in ACPI 6.3 spec.)\n///\n#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02\n\n///\n/// PPTT types\n///\n#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00\n#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01\n#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02\n\n///\n/// PPTT Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;\n\n///\n/// For PPTT struct processor flags\n///\n#define EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL 0x0\n#define EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL 0x1\n#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD 0x0\n#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD 0x1\n#define EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF 0x0\n#define EFI_ACPI_6_3_PPTT_NODE_IS_LEAF 0x1\n#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0\n#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL 0x1\n\n///\n/// Processor hierarchy node structure flags\n///\ntypedef struct {\n UINT32 PhysicalPackage : 1;\n UINT32 AcpiProcessorIdValid : 1;\n UINT32 ProcessorIsAThread : 1;\n UINT32 NodeIsALeaf : 1;\n UINT32 IdenticalImplementation : 1;\n UINT32 Reserved : 27;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;\n\n///\n/// Processor hierarchy node structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\n UINT32 Parent;\n UINT32 AcpiProcessorId;\n UINT32 NumberOfPrivateResources;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;\n\n///\n/// For PPTT struct cache flags\n///\n#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1\n#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1\n\n///\n/// Cache Type Structure flags\n///\ntypedef struct {\n UINT32 SizePropertyValid : 1;\n UINT32 NumberOfSetsValid : 1;\n UINT32 AssociativityValid : 1;\n UINT32 AllocationTypeValid : 1;\n UINT32 CacheTypeValid : 1;\n UINT32 WritePolicyValid : 1;\n UINT32 LineSizeValid : 1;\n UINT32 Reserved : 25;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;\n\n///\n/// For cache attributes\n///\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\n#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\n\n///\n/// Cache Type Structure cache attributes\n///\ntypedef struct {\n UINT8 AllocationType : 2;\n UINT8 CacheType : 2;\n UINT8 WritePolicy : 1;\n UINT8 Reserved : 3;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\n\n///\n/// Cache Type Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;\n UINT32 NextLevelOfCache;\n UINT32 Size;\n UINT32 NumberOfSets;\n UINT8 Associativity;\n EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\n UINT16 LineSize;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;\n\n///\n/// ID structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 VendorId;\n UINT64 Level1Id;\n UINT64 Level2Id;\n UINT16 MajorRev;\n UINT16 MinorRev;\n UINT16 SpinRev;\n} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CDIT\" Component Distance Information Table\n///\n#define EFI_ACPI_6_3_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"CRAT\" Component Resource Attribute Table\n///\n#define EFI_ACPI_6_3_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"HMAT\" Heterogeneous Memory Attribute Table\n///\n#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PDTT\" Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_3_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PPTT\" Processor Properties Topology Table\n///\n#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_3_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_3_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_3_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SDEV\" Secure DEVices Table\n///\n#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_3_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_3_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_3_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DPPT\" DMA Protection Policy Table\n///\n#define EFI_ACPI_6_3_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_3_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_3_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_3_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_3_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_3_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_3_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_3_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"SDEI\" Software Delegated Exceptions Interface Table\n///\n#define EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_3_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Concole Redirection Table\n///\n#define EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_3_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_3_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_3_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_3_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_3_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_3_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_3_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"WSMT\" Windows SMM Security Mitigation Table\n///\n#define EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_3_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi64.h", "content": "/** @file\n ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021.\n\n Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
\n Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef ACPI_6_4_H_\n#define ACPI_6_4_H_\n\n#include \"Acpi63.h\"\n\n///\n/// _CSD Revision for ACPI 6.4\n///\n#define EFI_ACPI_6_4_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.4\n///\n#define EFI_ACPI_6_4_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 6.4\n///\n#define EFI_ACPI_6_4_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.4\n///\n#define EFI_ACPI_6_4_AML_CPC_REVISION 3\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// ACPI 6.4 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_4_SYSTEM_MEMORY 0x00\n#define EFI_ACPI_6_4_SYSTEM_IO 0x01\n#define EFI_ACPI_6_4_PCI_CONFIGURATION_SPACE 0x02\n#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER 0x03\n#define EFI_ACPI_6_4_SMBUS 0x04\n#define EFI_ACPI_6_4_SYSTEM_CMOS 0x05\n#define EFI_ACPI_6_4_PCI_BAR_TARGET 0x06\n#define EFI_ACPI_6_4_IPMI 0x07\n#define EFI_ACPI_6_4_GENERAL_PURPOSE_IO 0x08\n#define EFI_ACPI_6_4_GENERIC_SERIAL_BUS 0x09\n#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_4_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_4_UNDEFINED 0\n#define EFI_ACPI_6_4_BYTE 1\n#define EFI_ACPI_6_4_WORD 2\n#define EFI_ACPI_6_4_DWORD 3\n#define EFI_ACPI_6_4_QWORD 4\n\n//\n// ACPI 6.4 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_4_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x04\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_4_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_4_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_4_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_4_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_4_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_4_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_4_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_4_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_4_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_4_8042 BIT1\n#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_4_WBINVD BIT0\n#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_4_PROC_C1 BIT2\n#define EFI_ACPI_6_4_P_LVL2_UP BIT3\n#define EFI_ACPI_6_4_PWR_BUTTON BIT4\n#define EFI_ACPI_6_4_SLP_BUTTON BIT5\n#define EFI_ACPI_6_4_FIX_RTC BIT6\n#define EFI_ACPI_6_4_RTC_S4 BIT7\n#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_4_DCK_CAP BIT9\n#define EFI_ACPI_6_4_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_4_SEALED_CASE BIT11\n#define EFI_ACPI_6_4_HEADLESS BIT12\n#define EFI_ACPI_6_4_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_4_S4BIOS_F BIT0\n#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_4_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x10 and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_4_IO_APIC 0x01\n#define EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_4_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_4_IO_SAPIC 0x06\n#define EFI_ACPI_6_4_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_4_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_4_GIC 0x0B\n#define EFI_ACPI_6_4_GICD 0x0C\n#define EFI_ACPI_6_4_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_4_GICR 0x0E\n#define EFI_ACPI_6_4_GIC_ITS 0x0F\n#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP 0x10\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_LOCAL_APIC_ENABLED BIT0\n#define EFI_ACPI_6_4_LOCAL_APIC_ONLINE_CAPABLE BIT1\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_4_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_4_POLARITY (3 << 0)\n#define EFI_ACPI_6_4_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_4_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2;\n UINT16 SpeOverflowInterrupt;\n} EFI_ACPI_6_4_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GIC_ENABLED BIT0\n#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_4_GIC_V1 0x01\n#define EFI_ACPI_6_4_GIC_V2 0x02\n#define EFI_ACPI_6_4_GIC_V3 0x03\n#define EFI_ACPI_6_4_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_4_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_4_GIC_ITS_STRUCTURE;\n\n///\n/// Multiprocessor Wakeup Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 MailBoxVersion;\n UINT32 Reserved;\n UINT64 MailBoxAddress;\n} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE;\n\n///\n/// Multiprocessor Wakeup Mailbox Structure\n///\ntypedef struct {\n UINT16 Command;\n UINT16 Reserved;\n UINT32 AcpiId;\n UINT64 WakeupVector;\n UINT8 ReservedForOs[2032];\n UINT8 ReservedForFirmware[2048];\n} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;\n\n#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000\n#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x06 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_4_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_4_GICC_AFFINITY 0x03\n#define EFI_ACPI_6_4_GIC_ITS_AFFINITY 0x04\n#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY 0x05\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)\n\n///\n/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT8 Reserved[2];\n UINT32 ItsId;\n} EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE;\n\n//\n// Generic Initiator Affinity Structure Device Handle Types\n// All other values between 0x02 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00\n#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01\n\n///\n/// Device Handle - ACPI\n///\ntypedef struct {\n UINT64 AcpiHid;\n UINT32 AcpiUid;\n UINT8 Reserved[4];\n} EFI_ACPI_6_4_DEVICE_HANDLE_ACPI;\n\n///\n/// Device Handle - PCI\n///\ntypedef struct {\n UINT16 PciSegment;\n UINT16 PciBdfNumber;\n UINT8 Reserved[12];\n} EFI_ACPI_6_4_DEVICE_HANDLE_PCI;\n\n///\n/// Device Handle\n///\ntypedef union {\n EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;\n EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;\n} EFI_ACPI_6_4_DEVICE_HANDLE;\n\n///\n/// Generic Initiator Affinity Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1;\n UINT8 DeviceHandleType;\n UINT32 ProximityDomain;\n EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;\n UINT32 Flags;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE;\n\n///\n/// Generic Initiator Affinity Structure Flags. All other bits are reserved\n/// and must be 0.\n///\n#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0\n#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_4_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_4_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\n#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\n#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\n#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\n#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_4_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Platform Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 NumberOfMemoryDevices;\n // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\n} EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02\n\n///\n/// Common Memory Device.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n UINT32 NumberOfMemoryDevices;\n // UINT8 TypeSpecificData[];\n // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\n} EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE;\n\n///\n/// Memory Device Type.\n///\n#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2\n#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF\n\n///\n/// Socket Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA;\n\n///\n/// Memory Controller Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT16 MemoryControllerIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA;\n\n///\n/// DIMM Type Specific Data.\n///\ntypedef struct {\n EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA;\n\n///\n/// Vendor Specific Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT8 TypeUuid[16];\n // EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];\n // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:3] = Reserved (must be zero)\n /// Bits[2:1] = Orientation Offset. These bits describe the clockwise\n /// degree offset from the image's default orientation.\n /// [00] = 0, no offset\n /// [01] = 90\n /// [10] = 180\n /// [11] = 270\n /// Bit [0] = Displayed. A one indicates the boot image graphic is\n /// displayed.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_4_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_4_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior towhen the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_4_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n UINT32 VirtualPL2TimerGSIV;\n UINT32 VirtualPL2TimerFlags;\n} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// Arm Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.4 spec.)\n//\n#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2\n\n#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n UINT64 SPALocationCookie;\n} EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_4_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\n#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NVDIMMPhysicalID;\n UINT16 NVDIMMRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 NVDIMMRegionSize;\n UINT64 RegionOffset;\n UINT64 NVDIMMPhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 NVDIMMStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\n\n#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 ValidFields;\n UINT8 ManufacturingLocation;\n UINT16 ManufacturingDate;\n UINT8 Reserved_22[2];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n//\n// Definition for Platform Capabilities Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT8 HighestValidCapability;\n UINT8 Reserved_5[3];\n UINT32 Capabilities;\n UINT8 Reserved_12[4];\n} EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;\n\n#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0\n#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1\n#define EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2\n\n///\n/// Secure DEVices Table (SDEV)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER;\n\n///\n/// SDEV Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01\n\n///\n/// Secure Device types\n///\n#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\n#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\n\n///\n/// Secure Device flags\n///\n#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0\n#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1\n\n///\n/// SDEV Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n} EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER;\n\n///\n/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\n///\ntypedef struct {\n EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\n UINT16 DeviceIdentifierOffset;\n UINT16 DeviceIdentifierLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n UINT16 SecureAccessComponentsOffset;\n UINT16 SecureAccessComponentsLength;\n} EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\n\n///\n/// Secure Access Component Types\n///\n#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00\n#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01\n\n///\n/// Identification Based Secure Access Component\n///\ntypedef struct {\n EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\n UINT16 HardwareIdentifierOffset;\n UINT16 HardwareIdentifierLength;\n UINT16 SubsystemIdentifierOffset;\n UINT16 SubsystemIdentifierLength;\n UINT16 HardwareRevision;\n UINT8 HardwareRevisionPresent;\n UINT8 ClassCodePresent;\n UINT8 PciCompatibleBaseClass;\n UINT8 PciCompatibleSubClass;\n UINT8 PciCompatibleProgrammingInterface;\n} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;\n\n///\n/// Memory-based Secure Access Component\n///\ntypedef struct {\n EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\n UINT32 Reserved;\n UINT64 MemoryAddressBase;\n UINT64 MemoryLength;\n} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;\n\n///\n/// PCIe Endpoint Device based Secure Device Structure\n///\ntypedef struct {\n EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\n UINT16 PciSegmentNumber;\n UINT16 StartBusNumber;\n UINT16 PciPathOffset;\n UINT16 PciPathLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_4_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_4_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_4_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_4_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n UINT8 Timestamp[8];\n} EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR 0x09\n#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\n#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Version 2 Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\n UINT64 ReadAckPreserve;\n UINT64 ReadAckWrite;\n} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// IA-32 Architecture Deferred Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// HMAT - Heterogeneous Memory Attribute Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[4];\n} EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\n\n///\n/// HMAT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\n\n///\n/// HMAT types\n///\n#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\n#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\n#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\n\n///\n/// HMAT Structure Header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER;\n\n///\n/// Memory Proximity Domain Attributes Structure flags\n///\ntypedef struct {\n UINT16 InitiatorProximityDomainValid : 1;\n UINT16 Reserved : 15;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;\n\n///\n/// Memory Proximity Domain Attributes Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\n UINT8 Reserved1[2];\n UINT32 InitiatorProximityDomain;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved2[20];\n} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;\n\n///\n/// System Locality Latency and Bandwidth Information Structure flags\n///\ntypedef struct {\n UINT8 MemoryHierarchy : 4;\n UINT8 AccessAttributes : 2;\n UINT8 Reserved : 2;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\n\n///\n/// System Locality Latency and Bandwidth Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\n UINT8 DataType;\n UINT8 MinTransferSize;\n UINT8 Reserved1;\n UINT32 NumberOfInitiatorProximityDomains;\n UINT32 NumberOfTargetProximityDomains;\n UINT8 Reserved2[4];\n UINT64 EntryBaseUnit;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\n\n///\n/// Memory Side Cache Information Structure cache attributes\n///\ntypedef struct {\n UINT32 TotalCacheLevels : 4;\n UINT32 CacheLevel : 4;\n UINT32 CacheAssociativity : 4;\n UINT32 WritePolicy : 4;\n UINT32 CacheLineSize : 16;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\n\n///\n/// Memory Side Cache Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved1[4];\n UINT64 MemorySideCacheSize;\n EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\n UINT8 Reserved2[2];\n UINT16 NumberOfSmbiosHandles;\n} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_4_ERST_NOOP 0x04\n#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_4_ERST_ADD 0x08\n#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_4_ERST_STALL 0x0C\n#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_4_ERST_GOTO 0x0F\n#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_4_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09\n#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_4_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_4_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 NotifyOnCompletion : 1;\n} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 PlatformInterrupt : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckWrite;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 3 Extended PCC Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT32 AddressLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT32 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckSet;\n UINT8 Reserved1[8];\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\n UINT64 CommandCompleteUpdatePreserve;\n UINT64 CommandCompleteUpdateSet;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC;\n\n///\n/// Type 4 Extended PCC Subspace Structure\n///\ntypedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBSPACE_4_EXTENDED_PCC;\n\n#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\n\ntypedef struct {\n UINT32 Signature;\n UINT32 Flags;\n UINT32 Length;\n UINT32 Command;\n} EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\n\n///\n/// Type 5 HW Registers based Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Version;\n UINT64 BaseAddress;\n UINT64 SharedMemoryRangeLength;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n UINT32 NominalLatency;\n UINT32 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;\n\n///\n/// Reduced PCC Subspace Shared Memory Region\n///\ntypedef struct {\n UINT32 Signature;\n // UINT8 CommunicationSubspace[];\n} EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;\n\n///\n/// Platform Debug Trigger Table (PDTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 TriggerCount;\n UINT8 Reserved[3];\n UINT32 TriggerIdentifierArrayOffset;\n} EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\n\n///\n/// PDTT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\n\n///\n/// PDTT Platform Communication Channel Identifier Structure\n///\ntypedef struct {\n UINT16 SubChannelIdentifer : 8;\n UINT16 Runtime : 1;\n UINT16 WaitForCompletion : 1;\n UINT16 TriggerOrder : 1;\n UINT16 Reserved : 5;\n} EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER;\n\n///\n/// PCC Commands Codes used by Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\n#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\n\n///\n/// PDTT Platform Communication Channel\n///\ntypedef EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_4_PDTT_PCC;\n\n///\n/// Processor Properties Topology Table (PPTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\n\n///\n/// PPTT Revision (as defined in ACPI 6.4 spec.)\n///\n#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03\n\n///\n/// PPTT types\n///\n#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00\n#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01\n\n///\n/// PPTT Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n} EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER;\n\n///\n/// For PPTT struct processor flags\n///\n#define EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL 0x0\n#define EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL 0x1\n#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD 0x0\n#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_THREAD 0x1\n#define EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF 0x0\n#define EFI_ACPI_6_4_PPTT_NODE_IS_LEAF 0x1\n#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0\n#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL 0x1\n\n///\n/// Processor hierarchy node structure flags\n///\ntypedef struct {\n UINT32 PhysicalPackage : 1;\n UINT32 AcpiProcessorIdValid : 1;\n UINT32 ProcessorIsAThread : 1;\n UINT32 NodeIsALeaf : 1;\n UINT32 IdenticalImplementation : 1;\n UINT32 Reserved : 27;\n} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS;\n\n///\n/// Processor hierarchy node structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\n UINT32 Parent;\n UINT32 AcpiProcessorId;\n UINT32 NumberOfPrivateResources;\n} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR;\n\n///\n/// For PPTT struct cache flags\n///\n#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1\n#define EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID 0x0\n#define EFI_ACPI_6_4_PPTT_CACHE_ID_VALID 0x1\n\n///\n/// Cache Type Structure flags\n///\ntypedef struct {\n UINT32 SizePropertyValid : 1;\n UINT32 NumberOfSetsValid : 1;\n UINT32 AssociativityValid : 1;\n UINT32 AllocationTypeValid : 1;\n UINT32 CacheTypeValid : 1;\n UINT32 WritePolicyValid : 1;\n UINT32 LineSizeValid : 1;\n UINT32 CacheIdValid : 1;\n UINT32 Reserved : 24;\n} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS;\n\n///\n/// For cache attributes\n///\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\n#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\n\n///\n/// Cache Type Structure cache attributes\n///\ntypedef struct {\n UINT8 AllocationType : 2;\n UINT8 CacheType : 2;\n UINT8 WritePolicy : 1;\n UINT8 Reserved : 3;\n} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\n\n///\n/// Cache Type Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;\n UINT32 NextLevelOfCache;\n UINT32 Size;\n UINT32 NumberOfSets;\n UINT8 Associativity;\n EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\n UINT16 LineSize;\n UINT32 CacheId;\n} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;\n\n///\n/// Platform Health Assessment Table (PHAT) Format\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n // UINT8 PlatformTelemetryRecords[];\n} EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE;\n\n#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01\n\n///\n/// PHAT Record Format\n///\ntypedef struct {\n UINT16 PlatformHealthAssessmentRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n // UINT8 Data[];\n} EFI_ACPI_6_4_PHAT_RECORD;\n\n///\n/// PHAT Record Type Format\n///\n#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000\n#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001\n\n///\n/// PHAT Version Element\n///\ntypedef struct {\n GUID ComponentId;\n UINT64 VersionValue;\n UINT32 ProducerId;\n} EFI_ACPI_6_4_PHAT_VERSION_ELEMENT;\n\n///\n/// PHAT Firmware Version Data Record\n///\ntypedef struct {\n UINT16 PlatformRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n UINT8 Reserved[3];\n UINT32 RecordCount;\n // UINT8 PhatVersionElement[];\n} EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD;\n\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01\n\n///\n/// Firmware Health Data Record Structure\n///\ntypedef struct {\n UINT16 PlatformRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n UINT16 Reserved;\n UINT8 AmHealthy;\n GUID DeviceSignature;\n UINT32 DeviceSpecificDataOffset;\n // UINT8 DevicePath[];\n // UINT8 DeviceSpecificData[];\n} EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;\n\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01\n\n///\n/// Firmware Health Data Record device health state\n///\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02\n#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03\n\n///\n/// CEDT Table Revision\n///\n#define EFI_ACPI_6_4_CEDT_CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x01\n\n///\n/// CEDT Structure Type\n///\n#define EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_HOST_BRIDGE_STRUCTURE 0x00\n#define EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_FIXED_MEMORY_WINDOW_STRUCTURE 0x01\n#define EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_XOR_INTERLEAVE_MATH_STRUCTURE 0x02\n#define EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE 0x03\n\n///\n/// CEDT CXL Host Bridge Structure\n///\ntypedef struct {\n UINT8 Type; // Set to EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_HOST_BRIDGE_STRUCTURE\n UINT8 Reserved0;\n UINT16 RecordLength;\n UINT32 Uid;\n UINT32 CxlVersion;\n UINT32 Reserved1;\n UINT64 Base;\n UINT64 Length;\n} EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_STRUCTURE;\n\n///\n/// CEDT CXL Version\n///\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_STRUCTURE_CXL_VERSION_RCH 0x00\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_STRUCTURE_CXL_VERSION_HB 0x01\n\n///\n/// CEDT CXL Fixed Memory Window Structure\n///\ntypedef struct {\n UINT8 Type; // Set to EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_FIXED_MEMORY_WINDOW_STRUCTURE\n UINT8 Reserved0;\n UINT16 RecordLength;\n UINT32 Reserved1;\n UINT64 BaseHpa;\n UINT64 WindowSize;\n UINT8 EncodedNumberOfInterleaveWays;\n UINT8 InterleaveArithmetic;\n UINT16 Reserved2;\n UINT32 HostBridgeInterleaveGranularity;\n UINT16 WindowRestrictions;\n UINT16 QtgId;\n UINT32 InterleaveTargetList[];\n} EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE;\n\n///\n/// CEDT Fixed Memory Window Structure Host Bridge Interleave Ways\n///\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_NONE 0x0\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_2_WAY 0x1\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_4_WAY 0x2\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_8_WAY 0x3\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_16_WAY 0x4\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_3_WAY 0x8\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_6_WAY 0x9\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_WAYS_12_WAY 0xA\n\n///\n/// CEDT Fixed Memory Window Structure Interleave Arithmetic Type\n///\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_ARITHMETIC_STANDARD_MODULO 0x00\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_INTERLEAVE_ARITHMETIC_MODULO_XOR 0x01\n\n///\n/// CEDT Host Bridge Interleave Granularity\n///\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_256B 0x0\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_512B 0x1\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_1024B 0x2\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_2048B 0x3\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_4096B 0x4\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_8192B 0x5\n#define EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_INTERLEAVE_GRANULARITY_16384B 0x6\n\n///\n/// CEDT Fixed Memory Window Structure Window Restriction\n///\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_WINDOW_RESTRICTIONS_DEVICE_COHERENT BIT0\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_WINDOW_RESTRICTIONS_HOST_ONLY_COHERENT BIT1\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_WINDOW_RESTRICTIONS_VOLATILE BIT2\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_WINDOW_RESTRICTIONS_PERSISTENT BIT3\n#define EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE_WINDOW_RESTRICTIONS_FIXED_DEVICE_CONFIGURATION BIT4\n\n///\n/// CEDT CXL XOR Interleave Math Structure\n///\ntypedef struct {\n UINT8 Type; // Set to EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_CXL_XOR_INTERLEAVE_MATH_STRUCTURE\n UINT8 Reserved0;\n UINT16 RecordLength;\n UINT16 Reserved1;\n UINT8 HostBridgeInterleaveGranularity;\n UINT8 NumberOfBitmapEntries;\n UINT64 XormapList[];\n} EFI_ACPI_6_4_CEDT_CXL_XOR_INTERLEAVE_MATH_STRUCTURE;\n\n///\n/// CEDT RCEC Downstream Port Association Structure\n///\ntypedef struct {\n UINT8 Type; // Set to EFI_ACPI_6_4_CEDT_STRUCTURE_TYPE_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE\n UINT8 Reserved0;\n UINT16 RecordLength;\n UINT16 RcecSegmentNumber;\n UINT16 RcecBusDeviceFunction;\n UINT8 ProtocolType;\n UINT64 BaseAddress;\n} EFI_ACPI_6_4_CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE;\n\n///\n/// CEDT RCEC Protocol Type\n///\n#define EFI_ACPI_6_4_CEDT_RCEC_PROTOCOL_TYPE_CXL_IO 0x00\n#define EFI_ACPI_6_4_CEDT_RCEC_PROTOCOL_TYPE_CXL_CACHEMEM 0x01\n\n///\n/// CXL Early Discovery Table (\"CEDT\") Format\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n\n // CedtStructure is a heterogeneous, packed list of any of the following:\n // - CXL Host Bridge Structure\n // - CXL Fixed Memory Window Structure\n // - CXL XOR Interleave Math Structure\n // - RCEC Downstream Port Association Structure\n // The structures share common Type and RecordLength fields that are used to\n // identify the type of structure and traverse the list.\n UINT8 CedtStructure[];\n} EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE;\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"APMT\" Arm Performance Monitoring Unit Table\n///\n#define EFI_ACPI_6_4_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CDIT\" Component Distance Information Table\n///\n#define EFI_ACPI_6_4_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')\n\n///\n/// \"CEDT\" CXL Early Discovery Table\n///\n#define EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32('C', 'E', 'D', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"CRAT\" Component Resource Attribute Table\n///\n#define EFI_ACPI_6_4_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"HMAT\" Heterogeneous Memory Attribute Table\n///\n#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PDTT\" Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PPTT\" Processor Properties Topology Table\n///\n#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_4_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_4_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_4_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SDEV\" Secure DEVices Table\n///\n#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_4_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_4_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_4_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_4_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_4_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_4_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_4_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_4_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_4_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_4_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_4_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_4_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_4_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_4_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_4_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_4_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"PHAT\" Platform Health Assessment Table\n///\n#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')\n\n///\n/// \"SDEI\" Software Delegated Exceptions Interface Table\n///\n#define EFI_ACPI_6_4_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_4_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Concole Redirection Table\n///\n#define EFI_ACPI_6_4_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_4_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_4_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_4_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_4_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_4_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_4_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_4_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"WSMT\" Windows SMM Security Mitigation Table\n///\n#define EFI_ACPI_6_4_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_4_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Acpi65.h", "content": "/** @file\n ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.\n\n Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
\n Copyright (c) 2019 - 2024, ARM Ltd. All rights reserved.
\n Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.
\n Copyright (C) 2025, Advanced Micro Devices, Inc. All rights reserved.\n\n SPDX-License-Identifier: BSD-2-Clause-Patent\n**/\n\n#ifndef ACPI_6_5_H_\n#define ACPI_6_5_H_\n\n#include \"Acpi64.h\"\n\n//\n// Ensure proper structure formats\n//\n#pragma pack(1)\n\n///\n/// _STA bit definitions ACPI 6.5 s6.3.7\n///\n#define ACPI_AML_STA_DEVICE_STATUS_PRESET 0x1\n#define ACPI_AML_STA_DEVICE_STATUS_ENABLED 0x2\n#define ACPI_AML_STA_DEVICE_STATUS_UI 0x4\n#define ACPI_AML_STA_DEVICE_STATUS_FUNCTIONING 0x8\n#define ACPI_AML_STA_DEVICE_STATUS_BATTERY 0x10\n\n///\n/// _CSD Revision for ACPI 6.5\n///\n#define EFI_ACPI_6_5_AML_CSD_REVISION 0\n\n///\n/// _CSD NumEntries for ACPI 6.5\n///\n#define EFI_ACPI_6_5_AML_CSD_NUM_ENTRIES 6\n\n///\n/// _PSD Revision for ACPI 6.5\n///\n#define EFI_ACPI_6_5_AML_PSD_REVISION 0\n\n///\n/// _CPC Revision for ACPI 6.5\n///\n#define EFI_ACPI_6_5_AML_CPC_REVISION 3\n\n///\n/// ACPI 6.5 Generic Address Space definition\n///\ntypedef struct {\n UINT8 AddressSpaceId;\n UINT8 RegisterBitWidth;\n UINT8 RegisterBitOffset;\n UINT8 AccessSize;\n UINT64 Address;\n} EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE;\n\n//\n// Generic Address Space Address IDs\n//\n#define EFI_ACPI_6_5_SYSTEM_MEMORY 0x00\n#define EFI_ACPI_6_5_SYSTEM_IO 0x01\n#define EFI_ACPI_6_5_PCI_CONFIGURATION_SPACE 0x02\n#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER 0x03\n#define EFI_ACPI_6_5_SMBUS 0x04\n#define EFI_ACPI_6_5_SYSTEM_CMOS 0x05\n#define EFI_ACPI_6_5_PCI_BAR_TARGET 0x06\n#define EFI_ACPI_6_5_IPMI 0x07\n#define EFI_ACPI_6_5_GENERAL_PURPOSE_IO 0x08\n#define EFI_ACPI_6_5_GENERIC_SERIAL_BUS 0x09\n#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL 0x0A\n#define EFI_ACPI_6_5_PLATFORM_RUNTIME_MECHANISM 0x0B\n#define EFI_ACPI_6_5_FUNCTIONAL_FIXED_HARDWARE 0x7F\n\n//\n// Generic Address Space Access Sizes\n//\n#define EFI_ACPI_6_5_UNDEFINED 0\n#define EFI_ACPI_6_5_BYTE 1\n#define EFI_ACPI_6_5_WORD 2\n#define EFI_ACPI_6_5_DWORD 3\n#define EFI_ACPI_6_5_QWORD 4\n\n//\n// ACPI 6.5 table structures\n//\n\n///\n/// Root System Description Pointer Structure\n///\ntypedef struct {\n UINT64 Signature;\n UINT8 Checksum;\n UINT8 OemId[6];\n UINT8 Revision;\n UINT32 RsdtAddress;\n UINT32 Length;\n UINT64 XsdtAddress;\n UINT8 ExtendedChecksum;\n UINT8 Reserved[3];\n} EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER;\n\n///\n/// RSD_PTR Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.5) says current value is 2\n\n///\n/// Common table header, this prefaces all ACPI tables, including FACS, but\n/// excluding the RSD PTR structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_5_COMMON_HEADER;\n\n//\n// Root System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.\n//\n\n///\n/// RSDT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n//\n// Extended System Description Table\n// No definition needed as it is a common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.\n//\n\n///\n/// XSDT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Fixed ACPI Description Table Structure (FADT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 FirmwareCtrl;\n UINT32 Dsdt;\n UINT8 Reserved0;\n UINT8 PreferredPmProfile;\n UINT16 SciInt;\n UINT32 SmiCmd;\n UINT8 AcpiEnable;\n UINT8 AcpiDisable;\n UINT8 S4BiosReq;\n UINT8 PstateCnt;\n UINT32 Pm1aEvtBlk;\n UINT32 Pm1bEvtBlk;\n UINT32 Pm1aCntBlk;\n UINT32 Pm1bCntBlk;\n UINT32 Pm2CntBlk;\n UINT32 PmTmrBlk;\n UINT32 Gpe0Blk;\n UINT32 Gpe1Blk;\n UINT8 Pm1EvtLen;\n UINT8 Pm1CntLen;\n UINT8 Pm2CntLen;\n UINT8 PmTmrLen;\n UINT8 Gpe0BlkLen;\n UINT8 Gpe1BlkLen;\n UINT8 Gpe1Base;\n UINT8 CstCnt;\n UINT16 PLvl2Lat;\n UINT16 PLvl3Lat;\n UINT16 FlushSize;\n UINT16 FlushStride;\n UINT8 DutyOffset;\n UINT8 DutyWidth;\n UINT8 DayAlrm;\n UINT8 MonAlrm;\n UINT8 Century;\n UINT16 IaPcBootArch;\n UINT8 Reserved1;\n UINT32 Flags;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ResetReg;\n UINT8 ResetValue;\n UINT16 ArmBootArch;\n UINT8 MinorVersion;\n UINT64 XFirmwareCtrl;\n UINT64 XDsdt;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\n UINT64 HypervisorVendorIdentity;\n} EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE;\n\n///\n/// FADT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\n#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x05\n\n//\n// Fixed ACPI Description Table Preferred Power Management Profile\n//\n#define EFI_ACPI_6_5_PM_PROFILE_UNSPECIFIED 0\n#define EFI_ACPI_6_5_PM_PROFILE_DESKTOP 1\n#define EFI_ACPI_6_5_PM_PROFILE_MOBILE 2\n#define EFI_ACPI_6_5_PM_PROFILE_WORKSTATION 3\n#define EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER 4\n#define EFI_ACPI_6_5_PM_PROFILE_SOHO_SERVER 5\n#define EFI_ACPI_6_5_PM_PROFILE_APPLIANCE_PC 6\n#define EFI_ACPI_6_5_PM_PROFILE_PERFORMANCE_SERVER 7\n#define EFI_ACPI_6_5_PM_PROFILE_TABLET 8\n\n//\n// Fixed ACPI Description Table Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_5_LEGACY_DEVICES BIT0\n#define EFI_ACPI_6_5_8042 BIT1\n#define EFI_ACPI_6_5_VGA_NOT_PRESENT BIT2\n#define EFI_ACPI_6_5_MSI_NOT_SUPPORTED BIT3\n#define EFI_ACPI_6_5_PCIE_ASPM_CONTROLS BIT4\n#define EFI_ACPI_6_5_CMOS_RTC_NOT_PRESENT BIT5\n\n//\n// Fixed ACPI Description Table Arm Boot Architecture Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_5_ARM_PSCI_COMPLIANT BIT0\n#define EFI_ACPI_6_5_ARM_PSCI_USE_HVC BIT1\n\n//\n// Fixed ACPI Description Table Fixed Feature Flags\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_5_WBINVD BIT0\n#define EFI_ACPI_6_5_WBINVD_FLUSH BIT1\n#define EFI_ACPI_6_5_PROC_C1 BIT2\n#define EFI_ACPI_6_5_P_LVL2_UP BIT3\n#define EFI_ACPI_6_5_PWR_BUTTON BIT4\n#define EFI_ACPI_6_5_SLP_BUTTON BIT5\n#define EFI_ACPI_6_5_FIX_RTC BIT6\n#define EFI_ACPI_6_5_RTC_S4 BIT7\n#define EFI_ACPI_6_5_TMR_VAL_EXT BIT8\n#define EFI_ACPI_6_5_DCK_CAP BIT9\n#define EFI_ACPI_6_5_RESET_REG_SUP BIT10\n#define EFI_ACPI_6_5_SEALED_CASE BIT11\n#define EFI_ACPI_6_5_HEADLESS BIT12\n#define EFI_ACPI_6_5_CPU_SW_SLP BIT13\n#define EFI_ACPI_6_5_PCI_EXP_WAK BIT14\n#define EFI_ACPI_6_5_USE_PLATFORM_CLOCK BIT15\n#define EFI_ACPI_6_5_S4_RTC_STS_VALID BIT16\n#define EFI_ACPI_6_5_REMOTE_POWER_ON_CAPABLE BIT17\n#define EFI_ACPI_6_5_FORCE_APIC_CLUSTER_MODEL BIT18\n#define EFI_ACPI_6_5_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\n#define EFI_ACPI_6_5_HW_REDUCED_ACPI BIT20\n#define EFI_ACPI_6_5_LOW_POWER_S0_IDLE_CAPABLE BIT21\n\n///\n/// Firmware ACPI Control Structure\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n UINT32 HardwareSignature;\n UINT32 FirmwareWakingVector;\n UINT32 GlobalLock;\n UINT32 Flags;\n UINT64 XFirmwareWakingVector;\n UINT8 Version;\n UINT8 Reserved0[3];\n UINT32 OspmFlags;\n UINT8 Reserved1[24];\n} EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE;\n\n///\n/// FACS Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02\n\n///\n/// Firmware Control Structure Feature Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_5_S4BIOS_F BIT0\n#define EFI_ACPI_6_5_64BIT_WAKE_SUPPORTED_F BIT1\n\n///\n/// OSPM Enabled Firmware Control Structure Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_5_OSPM_64BIT_WAKE_F BIT0\n\n//\n// Differentiated System Description Table,\n// Secondary System Description Table\n// and Persistent System Description Table,\n// no definition needed as they are common description table header, the same with\n// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\n//\n#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\n\n///\n/// Multiple APIC Description Table header definition. The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 LocalApicAddress;\n UINT32 Flags;\n} EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\n\n///\n/// MADT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x06\n\n///\n/// Multiple APIC Flags\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_5_PCAT_COMPAT BIT0\n\n//\n// Multiple APIC Description Table APIC structure types\n// All other values between 0x18 and 0x7F are reserved and\n// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\n//\n#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC 0x00\n#define EFI_ACPI_6_5_IO_APIC 0x01\n#define EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE 0x02\n#define EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE 0x03\n#define EFI_ACPI_6_5_LOCAL_APIC_NMI 0x04\n#define EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE 0x05\n#define EFI_ACPI_6_5_IO_SAPIC 0x06\n#define EFI_ACPI_6_5_LOCAL_SAPIC 0x07\n#define EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES 0x08\n#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC 0x09\n#define EFI_ACPI_6_5_LOCAL_X2APIC_NMI 0x0A\n#define EFI_ACPI_6_5_GIC 0x0B\n#define EFI_ACPI_6_5_GICD 0x0C\n#define EFI_ACPI_6_5_GIC_MSI_FRAME 0x0D\n#define EFI_ACPI_6_5_GICR 0x0E\n#define EFI_ACPI_6_5_GIC_ITS 0x0F\n#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP 0x10\n#define EFI_ACPI_6_5_CORE_PIC 0x11\n#define EFI_ACPI_6_5_LIO_PIC 0x12\n#define EFI_ACPI_6_5_HT_PIC 0x13\n#define EFI_ACPI_6_5_EIO_PIC 0x14\n#define EFI_ACPI_6_5_MSI_PIC 0x15\n#define EFI_ACPI_6_5_BIO_PIC 0x16\n#define EFI_ACPI_6_5_LPC_PIC 0x17\n\n//\n// APIC Structure Definitions\n//\n\n///\n/// Processor Local APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT8 ApicId;\n UINT32 Flags;\n} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE;\n\n///\n/// Local APIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_LOCAL_APIC_ENABLED BIT0\n#define EFI_ACPI_6_5_LOCAL_APIC_ONLINE_CAPABLE BIT1\n\n///\n/// IO APIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 IoApicAddress;\n UINT32 GlobalSystemInterruptBase;\n} EFI_ACPI_6_5_IO_APIC_STRUCTURE;\n\n///\n/// Interrupt Source Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Bus;\n UINT8 Source;\n UINT32 GlobalSystemInterrupt;\n UINT16 Flags;\n} EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n UINT8 CpeiProcessorOverride;\n UINT8 Reserved[31];\n} EFI_ACPI_6_5_PLATFORM_INTERRUPT_APIC_STRUCTURE;\n\n//\n// MPS INTI flags.\n// All other bits are reserved and must be set to 0.\n//\n#define EFI_ACPI_6_5_POLARITY (3 << 0)\n#define EFI_ACPI_6_5_TRIGGER_MODE (3 << 2)\n\n///\n/// Non-Maskable Interrupt Source Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 GlobalSystemInterrupt;\n} EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\n\n///\n/// Local APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorUid;\n UINT16 Flags;\n UINT8 LocalApicLint;\n} EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE;\n\n///\n/// Local APIC Address Override Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 LocalApicAddress;\n} EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\n\n///\n/// IO SAPIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 IoApicId;\n UINT8 Reserved;\n UINT32 GlobalSystemInterruptBase;\n UINT64 IoSapicAddress;\n} EFI_ACPI_6_5_IO_SAPIC_STRUCTURE;\n\n///\n/// Local SAPIC Structure\n/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 AcpiProcessorId;\n UINT8 LocalSapicId;\n UINT8 LocalSapicEid;\n UINT8 Reserved[3];\n UINT32 Flags;\n UINT32 ACPIProcessorUIDValue;\n} EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\n\n///\n/// Platform Interrupt Sources Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT8 InterruptType;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT8 IoSapicVector;\n UINT32 GlobalSystemInterrupt;\n UINT32 PlatformInterruptSourceFlags;\n} EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\n\n///\n/// Platform Interrupt Source Flags.\n/// All other bits are reserved and must be set to 0.\n///\n#define EFI_ACPI_6_5_CPEI_PROCESSOR_OVERRIDE BIT0\n\n///\n/// Processor Local x2APIC Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 AcpiProcessorUid;\n} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\n\n///\n/// Local x2APIC NMI Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Flags;\n UINT32 AcpiProcessorUid;\n UINT8 LocalX2ApicLint;\n UINT8 Reserved[3];\n} EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE;\n\n///\n/// GIC Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 CPUInterfaceNumber;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ParkingProtocolVersion;\n UINT32 PerformanceInterruptGsiv;\n UINT64 ParkedAddress;\n UINT64 PhysicalBaseAddress;\n UINT64 GICV;\n UINT64 GICH;\n UINT32 VGICMaintenanceInterrupt;\n UINT64 GICRBaseAddress;\n UINT64 MPIDR;\n UINT8 ProcessorPowerEfficiencyClass;\n UINT8 Reserved2;\n UINT16 SpeOverflowInterrupt;\n UINT16 TrbeInterrupt;\n} EFI_ACPI_6_5_GIC_STRUCTURE;\n\n///\n/// GIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GIC_ENABLED BIT0\n#define EFI_ACPI_6_5_PERFORMANCE_INTERRUPT_MODEL BIT1\n#define EFI_ACPI_6_5_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\n#define EFI_ACPI_6_5_GIC_ONLINE_CAPABLE BIT3\n\n///\n/// GIC Distributor Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicId;\n UINT64 PhysicalBaseAddress;\n UINT32 SystemVectorBase;\n UINT8 GicVersion;\n UINT8 Reserved2[3];\n} EFI_ACPI_6_5_GIC_DISTRIBUTOR_STRUCTURE;\n\n///\n/// GIC Version\n///\n#define EFI_ACPI_6_5_GIC_V1 0x01\n#define EFI_ACPI_6_5_GIC_V2 0x02\n#define EFI_ACPI_6_5_GIC_V3 0x03\n#define EFI_ACPI_6_5_GIC_V4 0x04\n\n///\n/// GIC MSI Frame Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved1;\n UINT32 GicMsiFrameId;\n UINT64 PhysicalBaseAddress;\n UINT32 Flags;\n UINT16 SPICount;\n UINT16 SPIBase;\n} EFI_ACPI_6_5_GIC_MSI_FRAME_STRUCTURE;\n\n///\n/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_SPI_COUNT_BASE_SELECT BIT0\n\n///\n/// GICR Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT64 DiscoveryRangeBaseAddress;\n UINT32 DiscoveryRangeLength;\n} EFI_ACPI_6_5_GICR_STRUCTURE;\n\n///\n/// GIC Interrupt Translation Service Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Reserved;\n UINT32 GicItsId;\n UINT64 PhysicalBaseAddress;\n UINT32 Reserved2;\n} EFI_ACPI_6_5_GIC_ITS_STRUCTURE;\n\n///\n/// Multiprocessor Wakeup Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 MailBoxVersion;\n UINT32 Reserved;\n UINT64 MailBoxAddress;\n} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_STRUCTURE;\n\n///\n/// Multiprocessor Wakeup Mailbox Structure\n///\ntypedef struct {\n UINT16 Command;\n UINT16 Reserved;\n UINT32 AcpiId;\n UINT64 WakeupVector;\n UINT8 ReservedForOs[2032];\n UINT8 ReservedForFirmware[2048];\n} EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;\n\n#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000\n#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001\n\n///\n/// Core Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT32 ProcessorId;\n UINT32 CoreId;\n UINT32 Flags;\n} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;\n\n///\n/// Legacy I/O Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT64 Address;\n UINT16 Size;\n UINT8 Cascade[2];\n UINT32 CascadeMap[2];\n} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;\n\n///\n/// HyperTransport Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT64 Address;\n UINT16 Size;\n UINT8 Cascade[8];\n} EFI_ACPI_6_5_HT_PIC_STRUCTURE;\n\n///\n/// Extend I/O Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT8 Cascade;\n UINT8 Node;\n UINT64 NodeMap;\n} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;\n\n///\n/// MSI Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT64 MsgAddress;\n UINT32 Start;\n UINT32 Count;\n} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;\n\n///\n/// Bridge I/O Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT64 Address;\n UINT16 Size;\n UINT16 Id;\n UINT16 GsiBase;\n} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;\n\n///\n/// Low Pin Count Programmable Interrupt Controller\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Version;\n UINT64 Address;\n UINT16 Size;\n UINT8 Cascade;\n} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;\n\n///\n/// Smart Battery Description Table (SBST)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 WarningEnergyLevel;\n UINT32 LowEnergyLevel;\n UINT32 CriticalEnergyLevel;\n} EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE;\n\n///\n/// SBST Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\n\n///\n/// Embedded Controller Boot Resources Table (ECDT)\n/// The table is followed by a null terminated ASCII string that contains\n/// a fully qualified reference to the name space object.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcControl;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE EcData;\n UINT32 Uid;\n UINT8 GpeBit;\n} EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\n\n///\n/// ECDT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01\n\n///\n/// System Resource Affinity Table (SRAT). The rest of the table\n/// must be defined in a platform specific manner.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved1; ///< Must be set to 1\n UINT64 Reserved2;\n} EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\n\n///\n/// SRAT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03\n\n//\n// SRAT structure types.\n// All other values between 0x06 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\n#define EFI_ACPI_6_5_MEMORY_AFFINITY 0x01\n#define EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02\n#define EFI_ACPI_6_5_GICC_AFFINITY 0x03\n#define EFI_ACPI_6_5_GIC_ITS_AFFINITY 0x04\n#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY 0x05\n\n///\n/// Processor Local APIC/SAPIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProximityDomain7To0;\n UINT8 ApicId;\n UINT32 Flags;\n UINT8 LocalSapicEid;\n UINT8 ProximityDomain31To8[3];\n UINT32 ClockDomain;\n} EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\n\n///\n/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\n\n///\n/// Memory Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT16 Reserved1;\n UINT32 AddressBaseLow;\n UINT32 AddressBaseHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n UINT32 Reserved2;\n UINT32 Flags;\n UINT64 Reserved3;\n} EFI_ACPI_6_5_MEMORY_AFFINITY_STRUCTURE;\n\n//\n// Memory Flags. All other bits are reserved and must be 0.\n//\n#define EFI_ACPI_6_5_MEMORY_ENABLED (1 << 0)\n#define EFI_ACPI_6_5_MEMORY_HOT_PLUGGABLE (1 << 1)\n#define EFI_ACPI_6_5_MEMORY_NONVOLATILE (1 << 2)\n\n///\n/// Processor Local x2APIC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1[2];\n UINT32 ProximityDomain;\n UINT32 X2ApicId;\n UINT32 Flags;\n UINT32 ClockDomain;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT32 AcpiProcessorUid;\n UINT32 Flags;\n UINT32 ClockDomain;\n} EFI_ACPI_6_5_GICC_AFFINITY_STRUCTURE;\n\n///\n/// GICC Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GICC_ENABLED (1 << 0)\n\n///\n/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 ProximityDomain;\n UINT8 Reserved[2];\n UINT32 ItsId;\n} EFI_ACPI_6_5_GIC_ITS_AFFINITY_STRUCTURE;\n\n//\n// Generic Initiator Affinity Structure Device Handle Types\n// All other values between 0x02 an 0xFF are reserved and\n// will be ignored by OSPM.\n//\n#define EFI_ACPI_6_5_ACPI_DEVICE_HANDLE 0x00\n#define EFI_ACPI_6_5_PCI_DEVICE_HANDLE 0x01\n\n///\n/// Device Handle - ACPI\n///\ntypedef struct {\n UINT64 AcpiHid;\n UINT32 AcpiUid;\n UINT8 Reserved[4];\n} EFI_ACPI_6_5_DEVICE_HANDLE_ACPI;\n\n///\n/// Device Handle - PCI\n///\ntypedef struct {\n UINT16 PciSegment;\n UINT16 PciBdfNumber;\n UINT8 Reserved[12];\n} EFI_ACPI_6_5_DEVICE_HANDLE_PCI;\n\n///\n/// Device Handle\n///\ntypedef union {\n EFI_ACPI_6_5_DEVICE_HANDLE_ACPI Acpi;\n EFI_ACPI_6_5_DEVICE_HANDLE_PCI Pci;\n} EFI_ACPI_6_5_DEVICE_HANDLE;\n\n///\n/// Generic Initiator Affinity Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved1;\n UINT8 DeviceHandleType;\n UINT32 ProximityDomain;\n EFI_ACPI_6_5_DEVICE_HANDLE DeviceHandle;\n UINT32 Flags;\n UINT8 Reserved2[4];\n} EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE;\n\n///\n/// Generic Initiator Affinity Structure Flags. All other bits are reserved\n/// and must be 0.\n///\n#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0\n#define EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1\n\n///\n/// System Locality Distance Information Table (SLIT).\n/// The rest of the table is a matrix.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 NumberOfSystemLocalities;\n} EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\n\n///\n/// SLIT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01\n\n///\n/// Corrected Platform Error Polling Table (CPEP)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[8];\n} EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\n\n///\n/// CPEP Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\n\n//\n// CPEP processor structure types.\n//\n#define EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC 0x00\n\n///\n/// Corrected Platform Error Polling Processor Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 ProcessorId;\n UINT8 ProcessorEid;\n UINT32 PollingInterval;\n} EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\n\n///\n/// Maximum System Characteristics Table (MSCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 OffsetProxDomInfo;\n UINT32 MaximumNumberOfProximityDomains;\n UINT32 MaximumNumberOfClockDomains;\n UINT64 MaximumPhysicalAddress;\n} EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\n\n///\n/// MSCT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\n\n///\n/// Maximum Proximity Domain Information Structure Definition\n///\ntypedef struct {\n UINT8 Revision;\n UINT8 Length;\n UINT32 ProximityDomainRangeLow;\n UINT32 ProximityDomainRangeHigh;\n UINT32 MaximumProcessorCapacity;\n UINT64 MaximumMemoryCapacity;\n} EFI_ACPI_6_5_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\n\n///\n/// ACPI RAS Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier[12];\n} EFI_ACPI_6_5_RAS_FEATURE_TABLE;\n\n///\n/// RASF Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_RAS_FEATURE_TABLE_REVISION 0x01\n\n///\n/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT16 Version;\n UINT8 RASCapabilities[16];\n UINT8 SetRASCapabilities[16];\n UINT16 NumberOfRASFParameterBlocks;\n UINT32 SetRASCapabilitiesStatus;\n} EFI_ACPI_6_5_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI RASF PCC command code\n///\n#define EFI_ACPI_6_5_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01\n\n///\n/// ACPI RASF Platform RAS Capabilities\n///\n#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\n#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\n#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\n#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\n#define EFI_ACPI_6_5_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\n\n///\n/// ACPI RASF Parameter Block structure for PATROL_SCRUB\n///\ntypedef struct {\n UINT16 Type;\n UINT16 Version;\n UINT16 Length;\n UINT16 PatrolScrubCommand;\n UINT64 RequestedAddressRange[2];\n UINT64 ActualAddressRange[2];\n UINT16 Flags;\n UINT8 RequestedSpeed;\n} EFI_ACPI_6_5_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\n\n///\n/// ACPI RASF Patrol Scrub command\n///\n#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\n#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\n#define EFI_ACPI_6_5_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\n\n///\n/// ACPI RAS2 PCC Descriptor\n///\ntypedef struct {\n UINT8 PccId;\n UINT8 Reserved[2];\n UINT8 RasFeatureType;\n UINT32 Instance;\n} EFI_ACPI_RAS2_PCC_DESCRIPTOR;\n\n///\n/// ACPI RAS2 Feature Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT16 Reserved;\n UINT16 PccCount;\n // EFI_ACPI_RAS2_PCC_DESCRIPTOR Descriptors[PccCount];\n} EFI_ACPI_6_5_RAS2_FEATURE_TABLE;\n\n///\n/// Memory Power State Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 PlatformCommunicationChannelIdentifier;\n UINT8 Reserved[3];\n // Memory Power Node Structure\n // Memory Power State Characteristics\n} EFI_ACPI_6_5_MEMORY_POWER_STATUS_TABLE;\n\n///\n/// MPST Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_REVISION 0x01\n\n///\n/// MPST Platform Communication Channel Shared Memory Region definition.\n///\ntypedef struct {\n UINT32 Signature;\n UINT16 Command;\n UINT16 Status;\n UINT32 MemoryPowerCommandRegister;\n UINT32 MemoryPowerStatusRegister;\n UINT32 PowerStateId;\n UINT32 MemoryPowerNodeId;\n UINT64 MemoryEnergyConsumed;\n UINT64 ExpectedAveragePowerComsuned;\n} EFI_ACPI_6_5_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\n\n///\n/// ACPI MPST PCC command code\n///\n#define EFI_ACPI_6_5_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03\n\n///\n/// ACPI MPST Memory Power command\n///\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\n\n///\n/// MPST Memory Power Node Table\n///\ntypedef struct {\n UINT8 PowerStateValue;\n UINT8 PowerStateInformationIndex;\n} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE;\n\ntypedef struct {\n UINT8 Flag;\n UINT8 Reserved;\n UINT16 MemoryPowerNodeId;\n UINT32 Length;\n UINT64 AddressBase;\n UINT64 AddressLength;\n UINT32 NumberOfPowerStates;\n UINT32 NumberOfPhysicalComponents;\n // EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\n // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\n} EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE;\n\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\n\ntypedef struct {\n UINT16 MemoryPowerNodeCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_5_MPST_MEMORY_POWER_NODE_TABLE;\n\n///\n/// MPST Memory Power State Characteristics Table\n///\ntypedef struct {\n UINT8 PowerStateStructureID;\n UINT8 Flag;\n UINT16 Reserved;\n UINT32 AveragePowerConsumedInMPS0;\n UINT32 RelativePowerSavingToMPS0;\n UINT64 ExitLatencyToMPS0;\n} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\n\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\n#define EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\n\ntypedef struct {\n UINT16 MemoryPowerStateCharacteristicsCount;\n UINT8 Reserved[2];\n} EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\n\n///\n/// Platform Memory Topology Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 NumberOfMemoryDevices;\n // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\n} EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE;\n\n///\n/// PMTT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_MEMORY_TOPOLOGY_TABLE_REVISION 0x02\n\n///\n/// Common Memory Device.\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Reserved;\n UINT16 Length;\n UINT16 Flags;\n UINT16 Reserved1;\n UINT32 NumberOfMemoryDevices;\n // UINT8 TypeSpecificData[];\n // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\n} EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE;\n\n///\n/// Memory Device Type.\n///\n#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0\n#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\n#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2\n#define EFI_ACPI_6_5_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF\n\n///\n/// Socket Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT16 SocketIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_5_PMTT_SOCKET_TYPE_DATA;\n\n///\n/// Memory Controller Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT16 MemoryControllerIdentifier;\n UINT16 Reserved;\n // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_5_PMTT_MEMORY_CONTROLLER_TYPE_DATA;\n\n///\n/// DIMM Type Specific Data.\n///\ntypedef struct {\n EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT32 SmbiosHandle;\n} EFI_ACPI_6_5_PMTT_DIMM_TYPE_SPECIFIC_DATA;\n\n///\n/// Vendor Specific Type Data.\n///\ntypedef struct {\n EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\n UINT8 TypeUuid[16];\n // EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];\n // EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\n} EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA;\n\n///\n/// Boot Graphics Resource Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n ///\n /// 2-bytes (16 bit) version ID. This value must be 1.\n ///\n UINT16 Version;\n ///\n /// 1-byte status field indicating current status about the table.\n /// Bits[7:3] = Reserved (must be zero)\n /// Bits[2:1] = Orientation Offset. These bits describe the clockwise\n /// degree offset from the image's default orientation.\n /// [00] = 0, no offset\n /// [01] = 90\n /// [10] = 180\n /// [11] = 270\n /// Bit [0] = Displayed. A one indicates the boot image graphic is\n /// displayed.\n ///\n UINT8 Status;\n ///\n /// 1-byte enumerated type field indicating format of the image.\n /// 0 = Bitmap\n /// 1 - 255 Reserved (for future use)\n ///\n UINT8 ImageType;\n ///\n /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\n /// of the image bitmap.\n ///\n UINT64 ImageAddress;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetX;\n ///\n /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\n /// (X, Y) display offset of the top left corner of the boot image.\n /// The top left corner of the display is at offset (0, 0).\n ///\n UINT32 ImageOffsetY;\n} EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE;\n\n///\n/// BGRT Revision\n///\n#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\n\n///\n/// BGRT Version\n///\n#define EFI_ACPI_6_5_BGRT_VERSION 0x01\n\n///\n/// BGRT Status\n///\n#define EFI_ACPI_6_5_BGRT_STATUS_NOT_DISPLAYED 0x00\n#define EFI_ACPI_6_5_BGRT_STATUS_DISPLAYED 0x01\n\n///\n/// BGRT Image Type\n///\n#define EFI_ACPI_6_5_BGRT_IMAGE_TYPE_BMP 0x00\n\n///\n/// FPDT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\n\n///\n/// FPDT Performance Record Types\n///\n#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\n#define EFI_ACPI_6_5_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\n\n///\n/// FPDT Performance Record Revision\n///\n#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\n#define EFI_ACPI_6_5_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\n\n///\n/// FPDT Runtime Performance Record Types\n///\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\n\n///\n/// FPDT Runtime Performance Record Revision\n///\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01\n#define EFI_ACPI_6_5_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02\n\n///\n/// FPDT Performance Record header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Length;\n UINT8 Revision;\n} EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER;\n\n///\n/// FPDT Performance Table header\n///\ntypedef struct {\n UINT32 Signature;\n UINT32 Length;\n} EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER;\n\n///\n/// FPDT Firmware Basic Boot Performance Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the Basic Boot Performance Table.\n ///\n UINT64 BootPerformanceTablePointer;\n} EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT S3 Performance Table Pointer Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// 64-bit processor-relative physical address of the S3 Performance Table.\n ///\n UINT64 S3PerformanceTablePointer;\n} EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Record Structure\n///\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;\n UINT32 Reserved;\n ///\n /// Timer value logged at the beginning of firmware image execution.\n /// This may not always be zero or near zero.\n ///\n UINT64 ResetEnd;\n ///\n /// Timer value logged just prior to loading the OS boot loader into memory.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 OsLoaderLoadImageStart;\n ///\n /// Timer value logged just prior to launching the previously loaded OS boot loader image.\n /// For non-UEFI compatible boots, the timer value logged will be just prior\n /// to the INT 19h handler invocation.\n ///\n UINT64 OsLoaderStartImageStart;\n ///\n /// Timer value logged at the point when the OS loader calls the\n /// ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesEntry;\n ///\n /// Timer value logged at the point just prior towhen the OS loader gaining\n /// control back from calls the ExitBootServices function for UEFI compatible firmware.\n /// For non-UEFI compatible boots, this field must be zero.\n ///\n UINT64 ExitBootServicesExit;\n} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\n\n///\n/// FPDT Firmware Basic Boot Performance Table signature\n///\n#define EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T')\n\n//\n// FPDT Firmware Basic Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_TABLE;\n\n///\n/// FPDT \"S3PT\" S3 Performance Table\n///\n#define EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T')\n\n//\n// FPDT Firmware S3 Boot Performance Table\n//\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER Header;\n //\n // one or more Performance Records.\n //\n} EFI_ACPI_6_5_FPDT_FIRMWARE_S3_BOOT_TABLE;\n\n///\n/// FPDT Basic S3 Resume Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// A count of the number of S3 resume cycles since the last full boot sequence.\n ///\n UINT32 ResumeCount;\n ///\n /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\n /// OS waking vector. Only the most recent resume cycle's time is retained.\n ///\n UINT64 FullResume;\n ///\n /// Average timer value of all resume cycles logged since the last full boot\n /// sequence, including the most recent resume. Note that the entire log of\n /// timer values does not need to be retained in order to calculate this average.\n ///\n UINT64 AverageResume;\n} EFI_ACPI_6_5_FPDT_S3_RESUME_RECORD;\n\n///\n/// FPDT Basic S3 Suspend Performance Record\n///\ntypedef struct {\n EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER Header;\n ///\n /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendStart;\n ///\n /// Timer value recorded at the final firmware write to SLP_TYP (or other\n /// mechanism) used to trigger hardware entry to S3.\n /// Only the most recent suspend cycle's timer value is retained.\n ///\n UINT64 SuspendEnd;\n} EFI_ACPI_6_5_FPDT_S3_SUSPEND_RECORD;\n\n///\n/// Firmware Performance Record Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_RECORD_TABLE;\n\n///\n/// Generic Timer Description Table definition.\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT64 CntControlBasePhysicalAddress;\n UINT32 Reserved;\n UINT32 SecurePL1TimerGSIV;\n UINT32 SecurePL1TimerFlags;\n UINT32 NonSecurePL1TimerGSIV;\n UINT32 NonSecurePL1TimerFlags;\n UINT32 VirtualTimerGSIV;\n UINT32 VirtualTimerFlags;\n UINT32 NonSecurePL2TimerGSIV;\n UINT32 NonSecurePL2TimerFlags;\n UINT64 CntReadBasePhysicalAddress;\n UINT32 PlatformTimerCount;\n UINT32 PlatformTimerOffset;\n UINT32 VirtualPL2TimerGSIV;\n UINT32 VirtualPL2TimerFlags;\n} EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE;\n\n///\n/// GTDT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\n\n///\n/// Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_5_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\n\n///\n/// Platform Timer Type\n///\n#define EFI_ACPI_6_5_GTDT_GT_BLOCK 0\n#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG 1\n\n///\n/// GT Block Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 CntCtlBase;\n UINT32 GTBlockTimerCount;\n UINT32 GTBlockTimerOffset;\n} EFI_ACPI_6_5_GTDT_GT_BLOCK_STRUCTURE;\n\n///\n/// GT Block Timer Structure\n///\ntypedef struct {\n UINT8 GTFrameNumber;\n UINT8 Reserved[3];\n UINT64 CntBaseX;\n UINT64 CntEL0BaseX;\n UINT32 GTxPhysicalTimerGSIV;\n UINT32 GTxPhysicalTimerFlags;\n UINT32 GTxVirtualTimerGSIV;\n UINT32 GTxVirtualTimerFlags;\n UINT32 GTxCommonFlags;\n} EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_STRUCTURE;\n\n///\n/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n\n///\n/// Common Flags Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\n#define EFI_ACPI_6_5_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\n\n///\n/// Arm Generic Watchdog Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT16 Length;\n UINT8 Reserved;\n UINT64 RefreshFramePhysicalAddress;\n UINT64 WatchdogControlFramePhysicalAddress;\n UINT32 WatchdogTimerGSIV;\n UINT32 WatchdogTimerFlags;\n} EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;\n\n///\n/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\n///\n#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\n#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\n#define EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\n\n//\n// NVDIMM Firmware Interface Table definition.\n//\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Reserved;\n} EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE;\n\n//\n// NFIT Version (as defined in ACPI 6.5 spec.)\n//\n#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\n\n//\n// Definition for NFIT Table Structure Types\n//\n#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\n#define EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\n#define EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\n#define EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\n#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\n#define EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\n#define EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\n#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE_TYPE 7\n\n//\n// Definition for NFIT Structure Header\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n} EFI_ACPI_6_5_NFIT_STRUCTURE_HEADER;\n\n//\n// Definition for System Physical Address Range Structure\n//\n#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\n#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\n#define EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2\n\n#define EFI_ACPI_6_5_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\n#define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\n#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\n#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\n#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\n#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\n#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\n#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 SPARangeStructureIndex;\n UINT16 Flags;\n UINT32 Reserved_8;\n UINT32 ProximityDomain;\n GUID AddressRangeTypeGUID;\n UINT64 SystemPhysicalAddressRangeBase;\n UINT64 SystemPhysicalAddressRangeLength;\n UINT64 AddressRangeMemoryMappingAttribute;\n UINT64 SPALocationCookie;\n} EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\n\n//\n// Definition for Memory Device to System Physical Address Range Mapping Structure\n//\ntypedef struct {\n UINT32 DIMMNumber : 4;\n UINT32 MemoryChannelNumber : 4;\n UINT32 MemoryControllerID : 4;\n UINT32 SocketID : 4;\n UINT32 NodeControllerID : 12;\n UINT32 Reserved_28 : 4;\n} EFI_ACPI_6_5_NFIT_DEVICE_HANDLE;\n\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\n#define EFI_ACPI_6_5_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NVDIMMPhysicalID;\n UINT16 NVDIMMRegionID;\n UINT16 SPARangeStructureIndex;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT64 NVDIMMRegionSize;\n UINT64 RegionOffset;\n UINT64 NVDIMMPhysicalAddressRegionBase;\n UINT16 InterleaveStructureIndex;\n UINT16 InterleaveWays;\n UINT16 NVDIMMStateFlags;\n UINT16 Reserved_46;\n} EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\n\n//\n// Definition for Interleave Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 InterleaveStructureIndex;\n UINT16 Reserved_6;\n UINT32 NumberOfLines;\n UINT32 LineSize;\n // UINT32 LineOffset[NumberOfLines];\n} EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE;\n\n//\n// Definition for SMBIOS Management Information Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT32 Reserved_4;\n // UINT8 Data[];\n} EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\n\n//\n// Definition for NVDIMM Control Region Structure\n//\n#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\n\n#define EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\n\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 VendorID;\n UINT16 DeviceID;\n UINT16 RevisionID;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemDeviceID;\n UINT16 SubsystemRevisionID;\n UINT8 ValidFields;\n UINT8 ManufacturingLocation;\n UINT16 ManufacturingDate;\n UINT8 Reserved_22[2];\n UINT32 SerialNumber;\n UINT16 RegionFormatInterfaceCode;\n UINT16 NumberOfBlockControlWindows;\n UINT64 SizeOfBlockControlWindow;\n UINT64 CommandRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfCommandRegisterInBlockControlWindows;\n UINT64 StatusRegisterOffsetInBlockControlWindow;\n UINT64 SizeOfStatusRegisterInBlockControlWindows;\n UINT16 NVDIMMControlRegionFlag;\n UINT8 Reserved_74[6];\n} EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\n\n//\n// Definition for NVDIMM Block Data Window Region Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT16 NVDIMMControlRegionStructureIndex;\n UINT16 NumberOfBlockDataWindows;\n UINT64 BlockDataWindowStartOffset;\n UINT64 SizeOfBlockDataWindow;\n UINT64 BlockAccessibleMemoryCapacity;\n UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\n} EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\n\n//\n// Definition for Flush Hint Address Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n EFI_ACPI_6_5_NFIT_DEVICE_HANDLE NFITDeviceHandle;\n UINT16 NumberOfFlushHintAddresses;\n UINT8 Reserved_10[6];\n // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\n} EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\n\n//\n// Definition for Platform Capabilities Structure\n//\ntypedef struct {\n UINT16 Type;\n UINT16 Length;\n UINT8 HighestValidCapability;\n UINT8 Reserved_5[3];\n UINT32 Capabilities;\n UINT8 Reserved_12[4];\n} EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE;\n\n#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT0\n#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT1\n#define EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT2\n\n///\n/// Secure DEVices Table (SDEV)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_5_SECURE_DEVICES_TABLE_HEADER;\n\n///\n/// SDEV Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_REVISION 0x01\n\n///\n/// Secure Device types\n///\n#define EFI_ACPI_6_5_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\n#define EFI_ACPI_6_5_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\n\n///\n/// Secure Device flags\n///\n#define EFI_ACPI_6_5_SDEV_FLAG_ALLOW_HANDOFF BIT0\n#define EFI_ACPI_6_5_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1\n\n///\n/// SDEV Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Flags;\n UINT16 Length;\n} EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER;\n\n///\n/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\n///\ntypedef struct {\n EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;\n UINT16 DeviceIdentifierOffset;\n UINT16 DeviceIdentifierLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n UINT16 SecureAccessComponentsOffset;\n UINT16 SecureAccessComponentsLength;\n} EFI_ACPI_6_5_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\n\n///\n/// Secure Access Component Types\n///\n#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00\n#define EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01\n\n///\n/// Identification Based Secure Access Component\n///\ntypedef struct {\n EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;\n UINT16 HardwareIdentifierOffset;\n UINT16 HardwareIdentifierLength;\n UINT16 SubsystemIdentifierOffset;\n UINT16 SubsystemIdentifierLength;\n UINT16 HardwareRevision;\n UINT8 HardwareRevisionPresent;\n UINT8 ClassCodePresent;\n UINT8 PciCompatibleBaseClass;\n UINT8 PciCompatibleSubClass;\n UINT8 PciCompatibleProgrammingInterface;\n} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;\n\n///\n/// Memory-based Secure Access Component\n///\ntypedef struct {\n EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;\n UINT32 Reserved;\n UINT64 MemoryAddressBase;\n UINT64 MemoryLength;\n} EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;\n\n///\n/// PCIe Endpoint Device based Secure Device Structure\n///\ntypedef struct {\n EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER Header;\n UINT16 PciSegmentNumber;\n UINT16 StartBusNumber;\n UINT16 PciPathOffset;\n UINT16 PciPathLength;\n UINT16 VendorSpecificDataOffset;\n UINT16 VendorSpecificDataLength;\n} EFI_ACPI_6_5_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\n\n///\n/// Boot Error Record Table (BERT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 BootErrorRegionLength;\n UINT64 BootErrorRegion;\n} EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_HEADER;\n\n///\n/// BERT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\n\n///\n/// Boot Error Region Block Status Definition\n///\ntypedef struct {\n UINT32 UncorrectableErrorValid : 1;\n UINT32 CorrectableErrorValid : 1;\n UINT32 MultipleUncorrectableErrors : 1;\n UINT32 MultipleCorrectableErrors : 1;\n UINT32 ErrorDataEntryCount : 10;\n UINT32 Reserved : 18;\n} EFI_ACPI_6_5_ERROR_BLOCK_STATUS;\n\n///\n/// Boot Error Region Definition\n///\ntypedef struct {\n EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_5_BOOT_ERROR_REGION_STRUCTURE;\n\n//\n// Boot Error Severity types\n//\n#define EFI_ACPI_6_5_ERROR_SEVERITY_RECOVERABLE 0x00\n#define EFI_ACPI_6_5_ERROR_SEVERITY_FATAL 0x01\n#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTED 0x02\n#define EFI_ACPI_6_5_ERROR_SEVERITY_NONE 0x03\n//\n// The term 'Correctable' is no longer being used as an error severity of the\n// reported error since ACPI Specification Version 5.1 Errata B.\n// The below macro is considered as deprecated and should no longer be used.\n//\n#define EFI_ACPI_6_5_ERROR_SEVERITY_CORRECTABLE 0x00\n\n///\n/// Generic Error Data Entry Definition\n///\ntypedef struct {\n UINT8 SectionType[16];\n UINT32 ErrorSeverity;\n UINT16 Revision;\n UINT8 ValidationBits;\n UINT8 Flags;\n UINT32 ErrorDataLength;\n UINT8 FruId[16];\n UINT8 FruText[20];\n UINT8 Timestamp[8];\n} EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\n\n///\n/// Generic Error Data Entry Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300\n\n///\n/// HEST - Hardware Error Source Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 ErrorSourceCount;\n} EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\n\n///\n/// HEST Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x02\n\n//\n// Error Source structure types.\n//\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR 0x02\n#define EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER 0x06\n#define EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER 0x07\n#define EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER 0x08\n#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR 0x09\n#define EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B\n\n//\n// Error Source structure flags.\n//\n#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\n#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\n#define EFI_ACPI_6_5_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\n\n///\n/// IA-32 Architecture Machine Check Exception Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT64 GlobalCapabilityInitData;\n UINT64 GlobalControlInitData;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[7];\n} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure Definition\n///\ntypedef struct {\n UINT8 BankNumber;\n UINT8 ClearStatusOnInitialization;\n UINT8 StatusDataFormat;\n UINT8 Reserved0;\n UINT32 ControlRegisterMsrAddress;\n UINT64 ControlInitData;\n UINT32 StatusRegisterMsrAddress;\n UINT32 AddressRegisterMsrAddress;\n UINT32 MiscRegisterMsrAddress;\n} EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\n\n///\n/// IA-32 Architecture Machine Check Bank Structure MCA data format\n///\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\n#define EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\n\n//\n// Hardware Error Notification types. All other values are reserved\n//\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\n#define EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\n\n///\n/// Hardware Error Notification Configuration Write Enable Structure Definition\n///\ntypedef struct {\n UINT16 Type : 1;\n UINT16 PollInterval : 1;\n UINT16 SwitchToPollingThresholdValue : 1;\n UINT16 SwitchToPollingThresholdWindow : 1;\n UINT16 ErrorThresholdValue : 1;\n UINT16 ErrorThresholdWindow : 1;\n UINT16 Reserved : 10;\n} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\n\n///\n/// Hardware Error Notification Structure Definition\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\n UINT32 PollInterval;\n UINT32 Vector;\n UINT32 SwitchToPollingThresholdValue;\n UINT32 SwitchToPollingThresholdWindow;\n UINT32 ErrorThresholdValue;\n UINT32 ErrorThresholdWindow;\n} EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\n\n///\n/// IA-32 Architecture Corrected Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// IA-32 Architecture NMI Error Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n} EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\n\n///\n/// PCI Express Root Port AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 RootErrorCommand;\n} EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\n\n///\n/// PCI Express Device AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\n\n///\n/// PCI Express Bridge AER Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 Bus;\n UINT16 Device;\n UINT16 Function;\n UINT16 DeviceControl;\n UINT8 Reserved1[2];\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 SecondaryUncorrectableErrorMask;\n UINT32 SecondaryUncorrectableErrorSeverity;\n UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\n} EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\n\n///\n/// Generic Hardware Error Source Version 2 Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT16 RelatedSourceId;\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n UINT32 MaxRawDataLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\n EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT32 ErrorStatusBlockLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\n UINT64 ReadAckPreserve;\n UINT64 ReadAckWrite;\n} EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\n\n///\n/// Generic Error Status Definition\n///\ntypedef struct {\n EFI_ACPI_6_5_ERROR_BLOCK_STATUS BlockStatus;\n UINT32 RawDataOffset;\n UINT32 RawDataLength;\n UINT32 DataLength;\n UINT32 ErrorSeverity;\n} EFI_ACPI_6_5_GENERIC_ERROR_STATUS_STRUCTURE;\n\n///\n/// IA-32 Architecture Deferred Machine Check Structure Definition\n///\ntypedef struct {\n UINT16 Type;\n UINT16 SourceId;\n UINT8 Reserved0[2];\n UINT8 Flags;\n UINT8 Enabled;\n UINT32 NumberOfRecordsToPreAllocate;\n UINT32 MaxSectionsPerRecord;\n EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\n UINT8 NumberOfHardwareBanks;\n UINT8 Reserved1[3];\n} EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\n\n///\n/// HMAT - Heterogeneous Memory Attribute Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 Reserved[4];\n} EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\n\n///\n/// HMAT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\n\n///\n/// HMAT types\n///\n#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\n#define EFI_ACPI_6_5_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\n#define EFI_ACPI_6_5_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\n\n///\n/// HMAT Structure Header\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_HEADER;\n\n///\n/// Memory Proximity Domain Attributes Structure flags\n///\ntypedef struct {\n UINT16 InitiatorProximityDomainValid : 1;\n UINT16 Reserved : 15;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;\n\n///\n/// Memory Proximity Domain Attributes Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\n UINT8 Reserved1[2];\n UINT32 InitiatorProximityDomain;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved2[20];\n} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;\n\n///\n/// System Locality Latency and Bandwidth Information Structure flags\n///\ntypedef struct {\n UINT8 MemoryHierarchy : 4;\n UINT8 AccessAttributes : 2;\n UINT8 Reserved : 2;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\n\n///\n/// System Locality Latency and Bandwidth Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\n UINT8 DataType;\n UINT8 MinTransferSize;\n UINT8 Reserved1;\n UINT32 NumberOfInitiatorProximityDomains;\n UINT32 NumberOfTargetProximityDomains;\n UINT8 Reserved2[4];\n UINT64 EntryBaseUnit;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\n\n///\n/// Memory Side Cache Information Structure cache attributes\n///\ntypedef struct {\n UINT32 TotalCacheLevels : 4;\n UINT32 CacheLevel : 4;\n UINT32 CacheAssociativity : 4;\n UINT32 WritePolicy : 4;\n UINT32 CacheLineSize : 16;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\n\n///\n/// Memory Side Cache Information Structure\n///\ntypedef struct {\n UINT16 Type;\n UINT8 Reserved[2];\n UINT32 Length;\n UINT32 MemoryProximityDomain;\n UINT8 Reserved1[4];\n UINT64 MemorySideCacheSize;\n EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\n UINT8 Reserved2[2];\n UINT16 NumberOfSmbiosHandles;\n} EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\n\n///\n/// ERST - Error Record Serialization Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 SerializationHeaderSize;\n UINT8 Reserved0[4];\n UINT32 InstructionEntryCount;\n} EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\n\n///\n/// ERST Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\n\n///\n/// ERST Serialization Actions\n///\n#define EFI_ACPI_6_5_ERST_BEGIN_WRITE_OPERATION 0x00\n#define EFI_ACPI_6_5_ERST_BEGIN_READ_OPERATION 0x01\n#define EFI_ACPI_6_5_ERST_BEGIN_CLEAR_OPERATION 0x02\n#define EFI_ACPI_6_5_ERST_END_OPERATION 0x03\n#define EFI_ACPI_6_5_ERST_SET_RECORD_OFFSET 0x04\n#define EFI_ACPI_6_5_ERST_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_5_ERST_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_5_ERST_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_5_ERST_GET_RECORD_IDENTIFIER 0x08\n#define EFI_ACPI_6_5_ERST_SET_RECORD_IDENTIFIER 0x09\n#define EFI_ACPI_6_5_ERST_GET_RECORD_COUNT 0x0A\n#define EFI_ACPI_6_5_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\n#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\n#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\n#define EFI_ACPI_6_5_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\n#define EFI_ACPI_6_5_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\n\n///\n/// ERST Action Command Status\n///\n#define EFI_ACPI_6_5_ERST_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_5_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\n#define EFI_ACPI_6_5_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\n#define EFI_ACPI_6_5_ERST_STATUS_FAILED 0x03\n#define EFI_ACPI_6_5_ERST_STATUS_RECORD_STORE_EMPTY 0x04\n#define EFI_ACPI_6_5_ERST_STATUS_RECORD_NOT_FOUND 0x05\n\n///\n/// ERST Serialization Instructions\n///\n#define EFI_ACPI_6_5_ERST_READ_REGISTER 0x00\n#define EFI_ACPI_6_5_ERST_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_5_ERST_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_5_ERST_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_5_ERST_NOOP 0x04\n#define EFI_ACPI_6_5_ERST_LOAD_VAR1 0x05\n#define EFI_ACPI_6_5_ERST_LOAD_VAR2 0x06\n#define EFI_ACPI_6_5_ERST_STORE_VAR1 0x07\n#define EFI_ACPI_6_5_ERST_ADD 0x08\n#define EFI_ACPI_6_5_ERST_SUBTRACT 0x09\n#define EFI_ACPI_6_5_ERST_ADD_VALUE 0x0A\n#define EFI_ACPI_6_5_ERST_SUBTRACT_VALUE 0x0B\n#define EFI_ACPI_6_5_ERST_STALL 0x0C\n#define EFI_ACPI_6_5_ERST_STALL_WHILE_TRUE 0x0D\n#define EFI_ACPI_6_5_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\n#define EFI_ACPI_6_5_ERST_GOTO 0x0F\n#define EFI_ACPI_6_5_ERST_SET_SRC_ADDRESS_BASE 0x10\n#define EFI_ACPI_6_5_ERST_SET_DST_ADDRESS_BASE 0x11\n#define EFI_ACPI_6_5_ERST_MOVE_DATA 0x12\n\n///\n/// ERST Instruction Flags\n///\n#define EFI_ACPI_6_5_ERST_PRESERVE_REGISTER 0x01\n\n///\n/// ERST Serialization Instruction Entry\n///\ntypedef struct {\n UINT8 SerializationAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_5_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ - Error Injection Table\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 InjectionHeaderSize;\n UINT8 InjectionFlags;\n UINT8 Reserved0[3];\n UINT32 InjectionEntryCount;\n} EFI_ACPI_6_5_ERROR_INJECTION_TABLE_HEADER;\n\n///\n/// EINJ Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x02\n\n///\n/// EINJ Error Injection Actions\n///\n#define EFI_ACPI_6_5_EINJ_BEGIN_INJECTION_OPERATION 0x00\n#define EFI_ACPI_6_5_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\n#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE 0x02\n#define EFI_ACPI_6_5_EINJ_GET_ERROR_TYPE 0x03\n#define EFI_ACPI_6_5_EINJ_END_OPERATION 0x04\n#define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05\n#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06\n#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07\n#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08\n#define EFI_ACPI_6_5_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09\n#define EFI_ACPI_6_5_EINJ_EINJV2_SET_ERROR_TYPE 0x10\n#define EFI_ACPI_6_5_EINJ_EINJV2_GET_ERROR_TYPE 0x11\n#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF\n\n///\n/// EINJ Action Command Status\n///\n#define EFI_ACPI_6_5_EINJ_STATUS_SUCCESS 0x00\n#define EFI_ACPI_6_5_EINJ_STATUS_UNKNOWN_FAILURE 0x01\n#define EFI_ACPI_6_5_EINJ_STATUS_INVALID_ACCESS 0x02\n\n///\n/// EINJ Error Type Definition\n///\n#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\n#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\n#define EFI_ACPI_6_5_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\n#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\n#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\n#define EFI_ACPI_6_5_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\n#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\n#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\n#define EFI_ACPI_6_5_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\n#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\n#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\n#define EFI_ACPI_6_5_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\n\n///\n/// EINJ Injection Instructions\n///\n#define EFI_ACPI_6_5_EINJ_READ_REGISTER 0x00\n#define EFI_ACPI_6_5_EINJ_READ_REGISTER_VALUE 0x01\n#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER 0x02\n#define EFI_ACPI_6_5_EINJ_WRITE_REGISTER_VALUE 0x03\n#define EFI_ACPI_6_5_EINJ_NOOP 0x04\n\n///\n/// EINJ Instruction Flags\n///\n#define EFI_ACPI_6_5_EINJ_PRESERVE_REGISTER 0x01\n\n///\n/// EINJ Injection Instruction Entry\n///\ntypedef struct {\n UINT8 InjectionAction;\n UINT8 Instruction;\n UINT8 Flags;\n UINT8 Reserved0;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\n UINT64 Value;\n UINT64 Mask;\n} EFI_ACPI_6_5_EINJ_INJECTION_INSTRUCTION_ENTRY;\n\n///\n/// EINJ Trigger Action Table\n///\ntypedef struct {\n UINT32 HeaderSize;\n UINT32 Revision;\n UINT32 TableSize;\n UINT32 EntryCount;\n} EFI_ACPI_6_5_EINJ_TRIGGER_ACTION_TABLE;\n\n///\n/// Platform Communications Channel Table (PCCT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT32 Flags;\n UINT64 Reserved;\n} EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\n\n///\n/// PCCT Version (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\n\n///\n/// PCCT Global Flags\n///\n#define EFI_ACPI_6_5_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0\n\n//\n// PCCT Subspace type\n//\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_GENERIC 0x00\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05\n\n///\n/// PCC Subspace Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_HEADER;\n\n///\n/// Generic Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[6];\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_GENERIC;\n\n///\n/// Generic Communications Channel Shared Memory Region\n///\n\ntypedef struct {\n UINT8 Command;\n UINT8 Reserved : 7;\n UINT8 NotifyOnCompletion : 1;\n} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\n\ntypedef struct {\n UINT8 CommandComplete : 1;\n UINT8 PlatformInterrupt : 1;\n UINT8 Error : 1;\n UINT8 PlatformNotification : 1;\n UINT8 Reserved : 4;\n UINT8 Reserved1;\n} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\n\ntypedef struct {\n UINT32 Signature;\n EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command;\n EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\n} EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\n\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\n#define EFI_ACPI_6_5_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\n\n///\n/// Type 1 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 2 HW-Reduced Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT64 AddressLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT16 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckWrite;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\n\n///\n/// Type 3 Extended PCC Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT32 PlatformInterrupt;\n UINT8 PlatformInterruptFlags;\n UINT8 Reserved;\n UINT64 BaseAddress;\n UINT32 AddressLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n UINT32 NominalLatency;\n UINT32 MaximumPeriodicAccessRate;\n UINT32 MinimumRequestTurnaroundTime;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\n UINT64 PlatformInterruptAckPreserve;\n UINT64 PlatformInterruptAckSet;\n UINT8 Reserved1[8];\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\n UINT64 CommandCompleteUpdatePreserve;\n UINT64 CommandCompleteUpdateSet;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC;\n\n///\n/// Type 4 Extended PCC Subspace Structure\n///\ntypedef EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_5_PCCT_SUBSPACE_4_EXTENDED_PCC;\n\n#define EFI_ACPI_6_5_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\n\ntypedef struct {\n UINT32 Signature;\n UINT32 Flags;\n UINT32 Length;\n UINT32 Command;\n} EFI_ACPI_6_5_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\n\n///\n/// Type 5 HW Registers based Communications Subspace Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT16 Version;\n UINT64 BaseAddress;\n UINT64 SharedMemoryRangeLength;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\n UINT64 DoorbellPreserve;\n UINT64 DoorbellWrite;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\n UINT64 CommandCompleteCheckMask;\n EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\n UINT64 ErrorStatusMask;\n UINT32 NominalLatency;\n UINT32 MinimumRequestTurnaroundTime;\n} EFI_ACPI_6_5_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;\n\n///\n/// Reduced PCC Subspace Shared Memory Region\n///\ntypedef struct {\n UINT32 Signature;\n // UINT8 CommunicationSubspace[];\n} EFI_6_5_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;\n\n///\n/// Platform Debug Trigger Table (PDTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n UINT8 TriggerCount;\n UINT8 Reserved[3];\n UINT32 TriggerIdentifierArrayOffset;\n} EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\n\n///\n/// PDTT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\n\n///\n/// PDTT Platform Communication Channel Identifier Structure\n///\ntypedef struct {\n UINT16 SubChannelIdentifer : 8;\n UINT16 Runtime : 1;\n UINT16 WaitForCompletion : 1;\n UINT16 TriggerOrder : 1;\n UINT16 Reserved : 5;\n} EFI_ACPI_6_5_PDTT_PCC_IDENTIFIER;\n\n///\n/// PCC Commands Codes used by Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\n#define EFI_ACPI_6_5_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\n\n///\n/// PDTT Platform Communication Channel\n///\ntypedef EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_5_PDTT_PCC;\n\n///\n/// Processor Properties Topology Table (PPTT)\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\n\n///\n/// PPTT Revision (as defined in ACPI 6.5 spec.)\n///\n#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03\n\n///\n/// PPTT types\n///\n#define EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR 0x00\n#define EFI_ACPI_6_5_PPTT_TYPE_CACHE 0x01\n\n///\n/// PPTT Structure Header\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n} EFI_ACPI_6_5_PPTT_STRUCTURE_HEADER;\n\n///\n/// For PPTT struct processor flags\n///\n#define EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL 0x0\n#define EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL 0x1\n#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD 0x0\n#define EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD 0x1\n#define EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF 0x0\n#define EFI_ACPI_6_5_PPTT_NODE_IS_LEAF 0x1\n#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0\n#define EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL 0x1\n\n///\n/// Processor hierarchy node structure flags\n///\ntypedef struct {\n UINT32 PhysicalPackage : 1;\n UINT32 AcpiProcessorIdValid : 1;\n UINT32 ProcessorIsAThread : 1;\n UINT32 NodeIsALeaf : 1;\n UINT32 IdenticalImplementation : 1;\n UINT32 Reserved : 27;\n} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS;\n\n///\n/// Processor hierarchy node structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\n UINT32 Parent;\n UINT32 AcpiProcessorId;\n UINT32 NumberOfPrivateResources;\n} EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR;\n\n///\n/// For PPTT struct cache flags\n///\n#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_CACHE_SIZE_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_NUMBER_OF_SETS_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_ASSOCIATIVITY_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_ALLOCATION_TYPE_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_CACHE_TYPE_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_WRITE_POLICY_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_LINE_SIZE_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_LINE_SIZE_VALID 0x1\n#define EFI_ACPI_6_5_PPTT_CACHE_ID_INVALID 0x0\n#define EFI_ACPI_6_5_PPTT_CACHE_ID_VALID 0x1\n\n///\n/// Cache Type Structure flags\n///\ntypedef struct {\n UINT32 SizePropertyValid : 1;\n UINT32 NumberOfSetsValid : 1;\n UINT32 AssociativityValid : 1;\n UINT32 AllocationTypeValid : 1;\n UINT32 CacheTypeValid : 1;\n UINT32 WritePolicyValid : 1;\n UINT32 LineSizeValid : 1;\n UINT32 CacheIdValid : 1;\n UINT32 Reserved : 24;\n} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS;\n\n///\n/// For cache attributes\n///\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\n#define EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\n\n///\n/// Cache Type Structure cache attributes\n///\ntypedef struct {\n UINT8 AllocationType : 2;\n UINT8 CacheType : 2;\n UINT8 WritePolicy : 1;\n UINT8 Reserved : 3;\n} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\n\n///\n/// Cache Type Structure\n///\ntypedef struct {\n UINT8 Type;\n UINT8 Length;\n UINT8 Reserved[2];\n EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS Flags;\n UINT32 NextLevelOfCache;\n UINT32 Size;\n UINT32 NumberOfSets;\n UINT8 Associativity;\n EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\n UINT16 LineSize;\n UINT32 CacheId;\n} EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE;\n\n///\n/// Platform Health Assessment Table (PHAT) Format\n///\ntypedef struct {\n EFI_ACPI_DESCRIPTION_HEADER Header;\n // UINT8 PlatformTelemetryRecords[];\n} EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE;\n\n#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01\n\n///\n/// PHAT Record Format\n///\ntypedef struct {\n UINT16 PlatformHealthAssessmentRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n // UINT8 Data[];\n} EFI_ACPI_6_5_PHAT_RECORD;\n\n///\n/// PHAT Record Type Format\n///\n#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000\n#define EFI_ACPI_6_5_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001\n\n///\n/// PHAT Version Element\n///\ntypedef struct {\n GUID ComponentId;\n UINT64 VersionValue;\n UINT32 ProducerId;\n} EFI_ACPI_6_5_PHAT_VERSION_ELEMENT;\n\n///\n/// PHAT Firmware Version Data Record\n///\ntypedef struct {\n UINT16 PlatformRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n UINT8 Reserved[3];\n UINT32 RecordCount;\n // UINT8 PhatVersionElement[];\n} EFI_ACPI_6_5_PHAT_FIRMWARE_VERISON_DATA_RECORD;\n\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01\n\n///\n/// Firmware Health Data Record Structure\n///\ntypedef struct {\n UINT16 PlatformRecordType;\n UINT16 RecordLength;\n UINT8 Revision;\n UINT16 Reserved;\n UINT8 AmHealthy;\n GUID DeviceSignature;\n UINT32 DeviceSpecificDataOffset;\n // UINT8 DevicePath[];\n // UINT8 DeviceSpecificData[];\n} EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;\n\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01\n\n///\n/// Firmware Health Data Record device health state\n///\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02\n#define EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03\n\n///\n/// Reset Reason Health Record Vendor Data Entry\n///\ntypedef struct {\n GUID VendorDataID;\n UINT16 Length;\n UINT16 Revision;\n // UINTN Data[];\n} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY;\n\n///\n/// Reset Reason Health Record Structure\n///\ntypedef struct {\n UINT8 SupportedSources;\n UINT8 Source;\n UINT8 SubSource;\n UINT8 Reason;\n UINT16 VendorCount;\n // EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY VendorSpecificResetReasonEntry[];\n} EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_STRUCTURE;\n\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_HEADER_GUID { 0x7a014ce2, 0xf263, 0x4b77, { 0xb8, 0x8a, 0xe6, 0x33, 0x6b, 0x78, 0x2c, 0x14 }}\n\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_UNKNOWN BIT0\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_HARDWARE BIT1\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_FIRMWARE BIT2\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SOFTWARE BIT3\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SUPPORTED_SOURCES_SUPERVISOR BIT4\n\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_UNKNOWN BIT0\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_HARDWARE BIT1\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_FIRMWARE BIT2\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SOFTWARE BIT3\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_SOURCES_SUPERVISOR BIT4\n\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNKNOWN 0x00\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_BOOT 0x01\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_COLD_RESET 0x02\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_WARM_RESET 0x03\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UPDATE 0x04\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_UNEXPECTED_RESET 0x20\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_FAULT 0x21\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_TIMEOUT 0x22\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_THERMAL 0x23\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_LOSS 0x24\n#define EFI_ACPI_6_5_PHAT_RESET_REASON_REASON_POWER_BUTTON 0x25\n\n//\n// Known table signatures\n//\n\n///\n/// \"RSD PTR \" Root System Description Pointer\n///\n#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')\n\n///\n/// \"APIC\" Multiple APIC Description Table\n///\n#define EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C')\n\n///\n/// \"APMT\" Arm Performance Monitoring Unit Table\n///\n#define EFI_ACPI_6_5_ARM_PERFORMANCE_MONITORING_UNIT_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T')\n\n///\n/// \"BERT\" Boot Error Record Table\n///\n#define EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T')\n\n///\n/// \"BGRT\" Boot Graphics Resource Table\n///\n#define EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T')\n\n///\n/// \"CDIT\" Component Distance Information Table\n///\n#define EFI_ACPI_6_5_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T')\n\n///\n/// \"CPEP\" Corrected Platform Error Polling Table\n///\n#define EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P')\n\n///\n/// \"CRAT\" Component Resource Attribute Table\n///\n#define EFI_ACPI_6_5_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T')\n\n///\n/// \"DSDT\" Differentiated System Description Table\n///\n#define EFI_ACPI_6_5_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T')\n\n///\n/// \"ECDT\" Embedded Controller Boot Resources Table\n///\n#define EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T')\n\n///\n/// \"EINJ\" Error Injection Table\n///\n#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J')\n\n///\n/// \"ERST\" Error Record Serialization Table\n///\n#define EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T')\n\n///\n/// \"FACP\" Fixed ACPI Description Table\n///\n#define EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P')\n\n///\n/// \"FACS\" Firmware ACPI Control Structure\n///\n#define EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S')\n\n///\n/// \"FPDT\" Firmware Performance Data Table\n///\n#define EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T')\n\n///\n/// \"GTDT\" Generic Timer Description Table\n///\n#define EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T')\n\n///\n/// \"HEST\" Hardware Error Source Table\n///\n#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T')\n\n///\n/// \"HMAT\" Heterogeneous Memory Attribute Table\n///\n#define EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')\n\n///\n/// \"MPST\" Memory Power State Table\n///\n#define EFI_ACPI_6_5_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T')\n\n///\n/// \"MSCT\" Maximum System Characteristics Table\n///\n#define EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T')\n\n///\n/// \"NFIT\" NVDIMM Firmware Interface Table\n///\n#define EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T')\n\n///\n/// \"PDTT\" Platform Debug Trigger Table\n///\n#define EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T')\n\n///\n/// \"PMTT\" Platform Memory Topology Table\n///\n#define EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T')\n\n///\n/// \"PPTT\" Processor Properties Topology Table\n///\n#define EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T')\n\n///\n/// \"PSDT\" Persistent System Description Table\n///\n#define EFI_ACPI_6_5_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T')\n\n///\n/// \"RAS2\" ACPI RAS2 Feature Table\n///\n#define EFI_ACPI_6_5_ACPI_RAS2_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', '2')\n\n///\n/// \"RASF\" ACPI RAS Feature Table\n///\n#define EFI_ACPI_6_5_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F')\n\n///\n/// \"RSDT\" Root System Description Table\n///\n#define EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T')\n\n///\n/// \"SBST\" Smart Battery Specification Table\n///\n#define EFI_ACPI_6_5_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T')\n\n///\n/// \"SDEV\" Secure DEVices Table\n///\n#define EFI_ACPI_6_5_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V')\n\n///\n/// \"SLIT\" System Locality Information Table\n///\n#define EFI_ACPI_6_5_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T')\n\n///\n/// \"SRAT\" System Resource Affinity Table\n///\n#define EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T')\n\n///\n/// \"SSDT\" Secondary System Description Table\n///\n#define EFI_ACPI_6_5_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\n\n///\n/// \"XSDT\" Extended System Description Table\n///\n#define EFI_ACPI_6_5_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T')\n\n///\n/// \"BOOT\" MS Simple Boot Spec\n///\n#define EFI_ACPI_6_5_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T')\n\n///\n/// \"CSRT\" MS Core System Resource Table\n///\n#define EFI_ACPI_6_5_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T')\n\n///\n/// \"DBG2\" MS Debug Port 2 Spec\n///\n#define EFI_ACPI_6_5_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2')\n\n///\n/// \"DBGP\" MS Debug Port Spec\n///\n#define EFI_ACPI_6_5_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P')\n\n///\n/// \"DMAR\" DMA Remapping Table\n///\n#define EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R')\n\n///\n/// \"DRTM\" Dynamic Root of Trust for Measurement Table\n///\n#define EFI_ACPI_6_5_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M')\n\n///\n/// \"ETDT\" Event Timer Description Table\n///\n#define EFI_ACPI_6_5_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T')\n\n///\n/// \"HPET\" IA-PC High Precision Event Timer Table\n///\n#define EFI_ACPI_6_5_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T')\n\n///\n/// \"iBFT\" iSCSI Boot Firmware Table\n///\n#define EFI_ACPI_6_5_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\n\n///\n/// \"IORT\" I/O Remapping Table\n///\n#define EFI_ACPI_6_5_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T')\n\n///\n/// \"IVRS\" I/O Virtualization Reporting Structure\n///\n#define EFI_ACPI_6_5_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S')\n\n///\n/// \"LPIT\" Low Power Idle Table\n///\n#define EFI_ACPI_6_5_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T')\n\n///\n/// \"MCFG\" PCI Express Memory Mapped Configuration Space Base Address Description Table\n///\n#define EFI_ACPI_6_5_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\n\n///\n/// \"MCHI\" Management Controller Host Interface Table\n///\n#define EFI_ACPI_6_5_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I')\n\n///\n/// \"MSDM\" MS Data Management Table\n///\n#define EFI_ACPI_6_5_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M')\n\n///\n/// \"PCCT\" Platform Communications Channel Table\n///\n#define EFI_ACPI_6_5_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T')\n\n///\n/// \"PHAT\" Platform Health Assessment Table\n///\n#define EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')\n\n///\n/// \"SDEI\" Software Delegated Exceptions Interface Table\n///\n#define EFI_ACPI_6_5_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I')\n\n///\n/// \"SLIC\" MS Software Licensing Table Specification\n///\n#define EFI_ACPI_6_5_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C')\n\n///\n/// \"SPCR\" Serial Port Concole Redirection Table\n///\n#define EFI_ACPI_6_5_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R')\n\n///\n/// \"SPMI\" Server Platform Management Interface Table\n///\n#define EFI_ACPI_6_5_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I')\n\n///\n/// \"STAO\" _STA Override Table\n///\n#define EFI_ACPI_6_5_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O')\n\n///\n/// \"TCPA\" Trusted Computing Platform Alliance Capabilities Table\n///\n#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A')\n\n///\n/// \"TPM2\" Trusted Computing Platform 1 Table\n///\n#define EFI_ACPI_6_5_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2')\n\n///\n/// \"UEFI\" UEFI ACPI Data Table\n///\n#define EFI_ACPI_6_5_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I')\n\n///\n/// \"WAET\" Windows ACPI Emulated Devices Table\n///\n#define EFI_ACPI_6_5_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\n\n///\n/// \"WDAT\" Watchdog Action Table\n///\n#define EFI_ACPI_6_5_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T')\n\n///\n/// \"WDRT\" Watchdog Resource Table\n///\n#define EFI_ACPI_6_5_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T')\n\n///\n/// \"WPBT\" MS Platform Binary Table\n///\n#define EFI_ACPI_6_5_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T')\n\n///\n/// \"WSMT\" Windows SMM Security Mitigation Table\n///\n#define EFI_ACPI_6_5_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T')\n\n///\n/// \"XENV\" Xen Project Table\n///\n#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')\n\n///\n/// \"MPAM\" Memory System Resource Partitioning and Monitoring Table\n///\n#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'A', 'M')\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/AcpiAml.h", "content": "/** @file\n This file contains AML code definition in the latest ACPI spec.\n\n Copyright (c) 2011, Intel Corporation. All rights reserved.
\n Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _ACPI_AML_H_\n#define _ACPI_AML_H_\n\n//\n// ACPI AML definition\n//\n\n//\n// Primary OpCode\n//\n#define AML_ZERO_OP 0x00\n#define AML_ONE_OP 0x01\n#define AML_ALIAS_OP 0x06\n#define AML_NAME_OP 0x08\n#define AML_BYTE_PREFIX 0x0a\n#define AML_WORD_PREFIX 0x0b\n#define AML_DWORD_PREFIX 0x0c\n#define AML_STRING_PREFIX 0x0d\n#define AML_QWORD_PREFIX 0x0e\n#define AML_SCOPE_OP 0x10\n#define AML_BUFFER_OP 0x11\n#define AML_PACKAGE_OP 0x12\n#define AML_VAR_PACKAGE_OP 0x13\n#define AML_METHOD_OP 0x14\n#define AML_EXTERNAL_OP 0x15\n#define AML_DUAL_NAME_PREFIX 0x2e\n#define AML_MULTI_NAME_PREFIX 0x2f\n#define AML_NAME_CHAR_A 0x41\n#define AML_NAME_CHAR_B 0x42\n#define AML_NAME_CHAR_C 0x43\n#define AML_NAME_CHAR_D 0x44\n#define AML_NAME_CHAR_E 0x45\n#define AML_NAME_CHAR_F 0x46\n#define AML_NAME_CHAR_G 0x47\n#define AML_NAME_CHAR_H 0x48\n#define AML_NAME_CHAR_I 0x49\n#define AML_NAME_CHAR_J 0x4a\n#define AML_NAME_CHAR_K 0x4b\n#define AML_NAME_CHAR_L 0x4c\n#define AML_NAME_CHAR_M 0x4d\n#define AML_NAME_CHAR_N 0x4e\n#define AML_NAME_CHAR_O 0x4f\n#define AML_NAME_CHAR_P 0x50\n#define AML_NAME_CHAR_Q 0x51\n#define AML_NAME_CHAR_R 0x52\n#define AML_NAME_CHAR_S 0x53\n#define AML_NAME_CHAR_T 0x54\n#define AML_NAME_CHAR_U 0x55\n#define AML_NAME_CHAR_V 0x56\n#define AML_NAME_CHAR_W 0x57\n#define AML_NAME_CHAR_X 0x58\n#define AML_NAME_CHAR_Y 0x59\n#define AML_NAME_CHAR_Z 0x5a\n#define AML_ROOT_CHAR 0x5c\n#define AML_PARENT_PREFIX_CHAR 0x5e\n#define AML_NAME_CHAR__ 0x5f\n#define AML_LOCAL0 0x60\n#define AML_LOCAL1 0x61\n#define AML_LOCAL2 0x62\n#define AML_LOCAL3 0x63\n#define AML_LOCAL4 0x64\n#define AML_LOCAL5 0x65\n#define AML_LOCAL6 0x66\n#define AML_LOCAL7 0x67\n#define AML_ARG0 0x68\n#define AML_ARG1 0x69\n#define AML_ARG2 0x6a\n#define AML_ARG3 0x6b\n#define AML_ARG4 0x6c\n#define AML_ARG5 0x6d\n#define AML_ARG6 0x6e\n#define AML_STORE_OP 0x70\n#define AML_REF_OF_OP 0x71\n#define AML_ADD_OP 0x72\n#define AML_CONCAT_OP 0x73\n#define AML_SUBTRACT_OP 0x74\n#define AML_INCREMENT_OP 0x75\n#define AML_DECREMENT_OP 0x76\n#define AML_MULTIPLY_OP 0x77\n#define AML_DIVIDE_OP 0x78\n#define AML_SHIFT_LEFT_OP 0x79\n#define AML_SHIFT_RIGHT_OP 0x7a\n#define AML_AND_OP 0x7b\n#define AML_NAND_OP 0x7c\n#define AML_OR_OP 0x7d\n#define AML_NOR_OP 0x7e\n#define AML_XOR_OP 0x7f\n#define AML_NOT_OP 0x80\n#define AML_FIND_SET_LEFT_BIT_OP 0x81\n#define AML_FIND_SET_RIGHT_BIT_OP 0x82\n#define AML_DEREF_OF_OP 0x83\n#define AML_CONCAT_RES_OP 0x84\n#define AML_MOD_OP 0x85\n#define AML_NOTIFY_OP 0x86\n#define AML_SIZE_OF_OP 0x87\n#define AML_INDEX_OP 0x88\n#define AML_MATCH_OP 0x89\n#define AML_CREATE_DWORD_FIELD_OP 0x8a\n#define AML_CREATE_WORD_FIELD_OP 0x8b\n#define AML_CREATE_BYTE_FIELD_OP 0x8c\n#define AML_CREATE_BIT_FIELD_OP 0x8d\n#define AML_OBJECT_TYPE_OP 0x8e\n#define AML_CREATE_QWORD_FIELD_OP 0x8f\n#define AML_LAND_OP 0x90\n#define AML_LOR_OP 0x91\n#define AML_LNOT_OP 0x92\n#define AML_LEQUAL_OP 0x93\n#define AML_LGREATER_OP 0x94\n#define AML_LLESS_OP 0x95\n#define AML_TO_BUFFER_OP 0x96\n#define AML_TO_DEC_STRING_OP 0x97\n#define AML_TO_HEX_STRING_OP 0x98\n#define AML_TO_INTEGER_OP 0x99\n#define AML_TO_STRING_OP 0x9c\n#define AML_COPY_OBJECT_OP 0x9d\n#define AML_MID_OP 0x9e\n#define AML_CONTINUE_OP 0x9f\n#define AML_IF_OP 0xa0\n#define AML_ELSE_OP 0xa1\n#define AML_WHILE_OP 0xa2\n#define AML_NOOP_OP 0xa3\n#define AML_RETURN_OP 0xa4\n#define AML_BREAK_OP 0xa5\n#define AML_BREAK_POINT_OP 0xcc\n#define AML_ONES_OP 0xff\n\n//\n// Extended OpCode\n//\n#define AML_EXT_OP 0x5b\n\n#define AML_EXT_MUTEX_OP 0x01\n#define AML_EXT_EVENT_OP 0x02\n#define AML_EXT_COND_REF_OF_OP 0x12\n#define AML_EXT_CREATE_FIELD_OP 0x13\n#define AML_EXT_LOAD_TABLE_OP 0x1f\n#define AML_EXT_LOAD_OP 0x20\n#define AML_EXT_STALL_OP 0x21\n#define AML_EXT_SLEEP_OP 0x22\n#define AML_EXT_ACQUIRE_OP 0x23\n#define AML_EXT_SIGNAL_OP 0x24\n#define AML_EXT_WAIT_OP 0x25\n#define AML_EXT_RESET_OP 0x26\n#define AML_EXT_RELEASE_OP 0x27\n#define AML_EXT_FROM_BCD_OP 0x28\n#define AML_EXT_TO_BCD_OP 0x29\n#define AML_EXT_UNLOAD_OP 0x2a\n#define AML_EXT_REVISION_OP 0x30\n#define AML_EXT_DEBUG_OP 0x31\n#define AML_EXT_FATAL_OP 0x32\n#define AML_EXT_TIMER_OP 0x33\n#define AML_EXT_REGION_OP 0x80\n#define AML_EXT_FIELD_OP 0x81\n#define AML_EXT_DEVICE_OP 0x82\n#define AML_EXT_PROCESSOR_OP 0x83\n#define AML_EXT_POWER_RES_OP 0x84\n#define AML_EXT_THERMAL_ZONE_OP 0x85\n#define AML_EXT_INDEX_FIELD_OP 0x86\n#define AML_EXT_BANK_FIELD_OP 0x87\n#define AML_EXT_DATA_REGION_OP 0x88\n\n//\n// FieldElement OpCode\n//\n#define AML_FIELD_RESERVED_OP 0x00\n#define AML_FIELD_ACCESS_OP 0x01\n#define AML_FIELD_CONNECTION_OP 0x02\n#define AML_FIELD_EXT_ACCESS_OP 0x03\n\n//\n// AML Name segment definitions\n//\n#define AML_NAME_SEG_SIZE 4\n\n#endif\n" }, { "path": "src/edk2/Coreboot.h", "content": "/** @file\n Coreboot PEI module include file.\n\n Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n/*\n * This file is part of the libpayload project.\n *\n * Copyright (C) 2008 Advanced Micro Devices, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#ifndef _COREBOOT_PEI_H_INCLUDED_\n#define _COREBOOT_PEI_H_INCLUDED_\n\n#include \n\n#if defined (_MSC_VER)\n #pragma warning( disable : 4200 )\n#endif\n\n#define DYN_CBMEM_ALIGN_SIZE (4096)\n\n#define IMD_ENTRY_MAGIC (~0xC0389481)\n#define CBMEM_ENTRY_MAGIC (~0xC0389479)\n\nstruct cbmem_entry {\n UINT32 magic;\n UINT32 start;\n UINT32 size;\n UINT32 id;\n};\n\nstruct cbmem_root {\n UINT32 max_entries;\n UINT32 num_entries;\n UINT32 locked;\n UINT32 size;\n struct cbmem_entry entries[0];\n};\n\nstruct imd_entry {\n UINT32 magic;\n UINT32 start_offset;\n UINT32 size;\n UINT32 id;\n};\n\nstruct imd_root {\n UINT32 max_entries;\n UINT32 num_entries;\n UINT32 flags;\n UINT32 entry_align;\n UINT32 max_offset;\n struct imd_entry entries[0];\n};\n\nstruct cbuint64 {\n UINT32 lo;\n UINT32 hi;\n};\n\n#define CB_HEADER_SIGNATURE 0x4F49424C\n\nstruct cb_header {\n UINT32 signature;\n UINT32 header_bytes;\n UINT32 header_checksum;\n UINT32 table_bytes;\n UINT32 table_checksum;\n UINT32 table_entries;\n};\n\nstruct cb_record {\n UINT32 tag;\n UINT32 size;\n};\n\n#define CB_TAG_UNUSED 0x0000\n#define CB_TAG_MEMORY 0x0001\n\nstruct cb_memory_range {\n struct cbuint64 start;\n struct cbuint64 size;\n UINT32 type;\n};\n\n#define CB_MEM_RAM 1\n#define CB_MEM_RESERVED 2\n#define CB_MEM_ACPI 3\n#define CB_MEM_NVS 4\n#define CB_MEM_UNUSABLE 5\n#define CB_MEM_VENDOR_RSVD 6\n#define CB_MEM_TABLE 16\n\nstruct cb_memory {\n UINT32 tag;\n UINT32 size;\n struct cb_memory_range map[0];\n};\n\n#define CB_TAG_MAINBOARD 0x0003\n\nstruct cb_mainboard {\n UINT32 tag;\n UINT32 size;\n UINT8 vendor_idx;\n UINT8 part_number_idx;\n UINT8 strings[0];\n};\n\n#define CB_TAG_VERSION 0x0004\n#define CB_TAG_EXTRA_VERSION 0x0005\n#define CB_TAG_BUILD 0x0006\n#define CB_TAG_COMPILE_TIME 0x0007\n#define CB_TAG_COMPILE_BY 0x0008\n#define CB_TAG_COMPILE_HOST 0x0009\n#define CB_TAG_COMPILE_DOMAIN 0x000a\n#define CB_TAG_COMPILER 0x000b\n#define CB_TAG_LINKER 0x000c\n#define CB_TAG_ASSEMBLER 0x000d\n\nstruct cb_string {\n UINT32 tag;\n UINT32 size;\n UINT8 string[0];\n};\n\n#define CB_TAG_SERIAL 0x000f\n\nstruct cb_serial {\n UINT32 tag;\n UINT32 size;\n #define CB_SERIAL_TYPE_IO_MAPPED 1\n #define CB_SERIAL_TYPE_MEMORY_MAPPED 2\n UINT32 type;\n UINT32 baseaddr;\n UINT32 baud;\n UINT32 regwidth;\n\n // Crystal or input frequency to the chip containing the UART.\n // Provide the board specific details to allow the payload to\n // initialize the chip containing the UART and make independent\n // decisions as to which dividers to select and their values\n // to eventually arrive at the desired console baud-rate.\n UINT32 input_hertz;\n\n // UART PCI address: bus, device, function\n // 1 << 31 - Valid bit, PCI UART in use\n // Bus << 20\n // Device << 15\n // Function << 12\n UINT32 uart_pci_addr;\n};\n\n#define CB_TAG_CONSOLE 0x00010\n\nstruct cb_console {\n UINT32 tag;\n UINT32 size;\n UINT16 type;\n};\n\n#define CB_TAG_CONSOLE_SERIAL8250 0\n#define CB_TAG_CONSOLE_VGA 1 // OBSOLETE\n#define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE\n#define CB_TAG_CONSOLE_LOGBUF 3\n#define CB_TAG_CONSOLE_SROM 4// OBSOLETE\n#define CB_TAG_CONSOLE_EHCI 5\n\n#define CB_TAG_FORWARD 0x00011\n\nstruct cb_forward {\n UINT32 tag;\n UINT32 size;\n UINT64 forward;\n};\n\nstruct cb_cbmem_ref {\n UINT32 tag;\n // Field contains size of this struct == 0x0010\n UINT32 size;\n UINT64 cbmem_addr;\n};\n\n#define CB_TAG_FRAMEBUFFER 0x0012\nstruct cb_framebuffer {\n UINT32 tag;\n UINT32 size;\n\n UINT64 physical_address;\n UINT32 x_resolution;\n UINT32 y_resolution;\n UINT32 bytes_per_line;\n UINT8 bits_per_pixel;\n UINT8 red_mask_pos;\n UINT8 red_mask_size;\n UINT8 green_mask_pos;\n UINT8 green_mask_size;\n UINT8 blue_mask_pos;\n UINT8 blue_mask_size;\n UINT8 reserved_mask_pos;\n UINT8 reserved_mask_size;\n};\n\n#define CB_TAG_VDAT 0x0015\nstruct cb_vdat {\n UINT32 tag;\n UINT32 size; /* size of the entire entry */\n UINT64 vdat_addr;\n UINT32 vdat_size;\n};\n\n#define CB_TAG_TIMESTAMPS 0x0016\n#define CB_TAG_CBMEM_CONSOLE 0x0017\nstruct cbmem_console {\n UINT32 size;\n UINT32 cursor;\n UINT8 body[0];\n} __attribute__ ((packed));\n\n#define CB_TAG_MRC_CACHE 0x0018\nstruct cb_cbmem_tab {\n UINT32 tag;\n UINT32 size;\n UINT64 cbmem_tab;\n};\n\n#define CB_TAG_SMMSTOREV2 0x0039\nstruct cb_smmstorev2 {\n UINT32 tag;\n UINT32 size;\n UINT32 num_blocks; /* Number of writeable blocks in Smm */\n UINT32 block_size; /* Size of a block in byte. Default: 64 KiB */\n UINT32 mmap_addr; /* MMIO address of the store for read only access */\n UINT32 com_buffer; /* Physical address of the communication buffer */\n UINT32 com_buffer_size; /* Size of the communication buffer in byte */\n UINT8 apm_cmd; /* The command byte to write to the APM I/O port */\n UINT8 unused[3]; /* Set to zero */\n UINT64 mmap_addr_ext; /* 64-bit MMIO address of the store for read only access.\n * Only available when size field >= 40. */\n} __attribute__ ((packed));\n\n#define CB_TAG_CFR_ROOT 0x0047\nstruct cb_cfr {\n UINT32 tag;\n UINT32 size;\n UINT32 version;\n UINT32 checksum; /* Of the following data only; excludes these 3 fields */\n /* CFR_FORM forms[] */\n};\n\n/* Helpful macros */\n\n#define MEM_RANGE_COUNT(_rec) \\\n (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))\n\n#define MEM_RANGE_PTR(_rec, _idx) \\\n (void *)(((UINT8 *) (_rec)) + sizeof(*(_rec)) \\\n + (sizeof((_rec)->map[0]) * (_idx)))\n\ntypedef struct cb_memory CB_MEMORY;\n\n#define CB_TAG_TPM_PPI_HANDOFF 0x003a\n\nenum lb_tmp_ppi_tpm_version {\n\tLB_TPM_VERSION_UNSPEC = 0,\n\tLB_TPM_VERSION_TPM_VERSION_1_2,\n\tLB_TPM_VERSION_TPM_VERSION_2,\n};\n\n/*\n * Handoff buffer for TPM Physical Presence Interface.\n * * ppi_address Pointer to PPI buffer shared with ACPI\n * The layout of the buffer matches the QEMU virtual memory device\n * that is generated by QEMU.\n * See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h'\n * for details.\n * * tpm_version TPM version: 1 for TPM1.2, 2 for TPM2.0\n * * ppi_version BCD encoded version of TPM PPI interface\n */\nstruct cb_tpm_physical_presence {\n\tUINT32 tag;\n\tUINT32 size;\n\tUINT32 ppi_address;\t/* Address of ACPI PPI communication buffer */\n\tUINT8 tpm_version;\t/* 1: TPM1.2, 2: TPM2.0 */\n\tUINT8 ppi_version;\t/* BCD encoded */\n} __attribute__((packed));\n\n#endif // _COREBOOT_PEI_H_INCLUDED_\n" }, { "path": "src/edk2/E820.h", "content": "/** @file\n\nCopyright (c) 2013, Citrix Systems UK Ltd.\nCopyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
\n\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef __E820_H__\n#define __E820_H__\n\n#include \n\n#pragma pack(1)\n\ntypedef enum {\n EfiAcpiAddressRangeMemory = 1,\n EfiAcpiAddressRangeReserved = 2,\n EfiAcpiAddressRangeACPI = 3,\n EfiAcpiAddressRangeNVS = 4\n} EFI_ACPI_MEMORY_TYPE;\n\ntypedef struct {\n UINT64 BaseAddr;\n UINT64 Length;\n EFI_ACPI_MEMORY_TYPE Type;\n} EFI_E820_ENTRY64;\n\ntypedef struct {\n UINT32 BassAddrLow;\n UINT32 BaseAddrHigh;\n UINT32 LengthLow;\n UINT32 LengthHigh;\n EFI_ACPI_MEMORY_TYPE Type;\n} EFI_E820_ENTRY;\n\n#pragma pack()\n\n#endif /* __E820_H__ */\n" }, { "path": "src/edk2/Edk2Compat.h", "content": "#ifndef _EDK2_COMPAT_H_\n#define _EDK2_COMPAT_H_\n\n#include \n\n/* Packed is already handled by pragmas */\n#define PACKED\n\n#define GUID EFI_GUID\n\n#define SIGNATURE_16(A,B) EFI_SIGNATURE_16(A,B)\n#define SIGNATURE_32(A,B,C,D) EFI_SIGNATURE_32(A,B,C,D)\n#define SIGNATURE_64(A,B,C,D,E,F,G,H) EFI_SIGNATURE_64(A,B,C,D,E,F,G,H)\n\n/* Debug Macros */\n\n//\n// Declare bits for PcdDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint()\n//\n#define DEBUG_INIT 0x00000001 // Initialization\n#define DEBUG_WARN 0x00000002 // Warnings\n#define DEBUG_LOAD 0x00000004 // Load events\n#define DEBUG_FS 0x00000008 // EFI File system\n#define DEBUG_POOL 0x00000010 // Alloc & Free (pool)\n#define DEBUG_PAGE 0x00000020 // Alloc & Free (page)\n#define DEBUG_INFO 0x00000040 // Informational debug messages\n#define DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers\n#define DEBUG_VARIABLE 0x00000100 // Variable\n#define DEBUG_BM 0x00000400 // Boot Manager\n#define DEBUG_BLKIO 0x00001000 // BlkIo Driver\n#define DEBUG_NET 0x00004000 // Network Io Driver\n#define DEBUG_UNDI 0x00010000 // UNDI Driver\n#define DEBUG_LOADFILE 0x00020000 // LoadFile\n#define DEBUG_EVENT 0x00080000 // Event messages\n#define DEBUG_GCD 0x00100000 // Global Coherency Database changes\n#define DEBUG_CACHE 0x00200000 // Memory range cachability changes\n#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may\n // significantly impact boot performance\n#define DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload manageability messages\n // related to modules such as Redfish, IPMI, MCTP etc.\n#define DEBUG_ERROR 0x80000000 // Error messages\n\n#ifndef DEBUG_PRINT_LEVEL\n#define DEBUG_PRINT_LEVEL (DEBUG_ERROR)\n#endif\n\n#define _DEBUG_PRINT(PrintLevel, ...) \\\n do { \\\n if (PrintLevel & DEBUG_PRINT_LEVEL) { \\\n printf (#__VA_ARGS__); \\\n } \\\n } while (FALSE)\n#define _DEBUGLIB_DEBUG(Expression) _DEBUG_PRINT Expression\n\n#define DEBUG(Expression) \\\n do { \\\n if (TRUE) { \\\n _DEBUGLIB_DEBUG (Expression); \\\n } \\\n } while (FALSE)\n\n#endif /* _EDK2_COMPAT_H_ */\n" }, { "path": "src/edk2/LegacyBios.h", "content": "/** @file\n The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage\n under EFI and Legacy OS boot. This file also includes all the related\n COMPATIBILITY16 structures and definitions.\n\n Note: The names for EFI_IA32_REGISTER_SET elements were picked to follow\n well known naming conventions.\n\n Thunk is the code that switches from 32-bit protected environment into the 16-bit real-mode\n environment. Reverse thunk is the code that does the opposite.\n\nCopyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n @par Revision Reference:\n This protocol is defined in Framework for EFI Compatibility Support Module spec\n Version 0.98.\n\n**/\n\n#ifndef _EFI_LEGACY_BIOS_H_\n#define _EFI_LEGACY_BIOS_H_\n\n#include \n\n///\n///\n///\n#pragma pack(1)\n\ntypedef UINT8 SERIAL_MODE;\ntypedef UINT8 PARALLEL_MODE;\n\n#define EFI_COMPATIBILITY16_TABLE_SIGNATURE EFI_SIGNATURE_32 ('I', 'F', 'E', '$')\n\n///\n/// There is a table located within the traditional BIOS in either the 0xF000:xxxx or 0xE000:xxxx\n/// physical address range. It is located on a 16-byte boundary and provides the physical address of the\n/// entry point for the Compatibility16 functions. These functions provide the platform-specific\n/// information that is required by the generic EfiCompatibility code. The functions are invoked via\n/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit physical\n/// entry point.\n///\ntypedef struct {\n ///\n /// The string \"$EFI\" denotes the start of the EfiCompatibility table. Byte 0 is \"I,\" byte\n /// 1 is \"F,\" byte 2 is \"E,\" and byte 3 is \"$\" and is normally accessed as a DWORD or UINT32.\n ///\n UINT32 Signature;\n\n ///\n /// The value required such that byte checksum of TableLength equals zero.\n ///\n UINT8 TableChecksum;\n\n ///\n /// The length of this table.\n ///\n UINT8 TableLength;\n\n ///\n /// The major EFI revision for which this table was generated.\n ///\n UINT8 EfiMajorRevision;\n\n ///\n /// The minor EFI revision for which this table was generated.\n ///\n UINT8 EfiMinorRevision;\n\n ///\n /// The major revision of this table.\n ///\n UINT8 TableMajorRevision;\n\n ///\n /// The minor revision of this table.\n ///\n UINT8 TableMinorRevision;\n\n ///\n /// Reserved for future usage.\n ///\n UINT16 Reserved;\n\n ///\n /// The segment of the entry point within the traditional BIOS for Compatibility16 functions.\n ///\n UINT16 Compatibility16CallSegment;\n\n ///\n /// The offset of the entry point within the traditional BIOS for Compatibility16 functions.\n ///\n UINT16 Compatibility16CallOffset;\n\n ///\n /// The segment of the entry point within the traditional BIOS for EfiCompatibility\n /// to invoke the PnP installation check.\n ///\n UINT16 PnPInstallationCheckSegment;\n\n ///\n /// The Offset of the entry point within the traditional BIOS for EfiCompatibility\n /// to invoke the PnP installation check.\n ///\n UINT16 PnPInstallationCheckOffset;\n\n ///\n /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the IntelPlatform\n ///Innovation Framework for EFI Driver Execution Environment Core Interface Specification (DXE CIS).\n ///\n UINT32 EfiSystemTable;\n\n ///\n /// The address of an OEM-provided identifier string. The string is null terminated.\n ///\n UINT32 OemIdStringPointer;\n\n ///\n /// The 32-bit physical address where ACPI RSD PTR is stored within the traditional\n /// BIOS. The remained of the ACPI tables are located at their EFI addresses. The size\n /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill in the ACPI\n /// RSD PTR with either the ACPI 1.0b or 2.0 values.\n ///\n UINT32 AcpiRsdPtrPointer;\n\n ///\n /// The OEM revision number. Usage is undefined but provided for OEM module usage.\n ///\n UINT16 OemRevision;\n\n ///\n /// The 32-bit physical address where INT15 E820 data is stored within the traditional\n /// BIOS. The EfiCompatibility code will fill in the E820Pointer value and copy the\n /// data to the indicated area.\n ///\n UINT32 E820Pointer;\n\n ///\n /// The length of the E820 data and is filled in by the EfiCompatibility code.\n ///\n UINT32 E820Length;\n\n ///\n /// The 32-bit physical address where the $PIR table is stored in the traditional BIOS.\n /// The EfiCompatibility code will fill in the IrqRoutingTablePointer value and\n /// copy the data to the indicated area.\n ///\n UINT32 IrqRoutingTablePointer;\n\n ///\n /// The length of the $PIR table and is filled in by the EfiCompatibility code.\n ///\n UINT32 IrqRoutingTableLength;\n\n ///\n /// The 32-bit physical address where the MP table is stored in the traditional BIOS.\n /// The EfiCompatibility code will fill in the MpTablePtr value and copy the data\n /// to the indicated area.\n ///\n UINT32 MpTablePtr;\n\n ///\n /// The length of the MP table and is filled in by the EfiCompatibility code.\n ///\n UINT32 MpTableLength;\n\n ///\n /// The segment of the OEM-specific INT table/code.\n ///\n UINT16 OemIntSegment;\n\n ///\n /// The offset of the OEM-specific INT table/code.\n ///\n UINT16 OemIntOffset;\n\n ///\n /// The segment of the OEM-specific 32-bit table/code.\n ///\n UINT16 Oem32Segment;\n\n ///\n /// The offset of the OEM-specific 32-bit table/code.\n ///\n UINT16 Oem32Offset;\n\n ///\n /// The segment of the OEM-specific 16-bit table/code.\n ///\n UINT16 Oem16Segment;\n\n ///\n /// The offset of the OEM-specific 16-bit table/code.\n ///\n UINT16 Oem16Offset;\n\n ///\n /// The segment of the TPM binary passed to 16-bit CSM.\n ///\n UINT16 TpmSegment;\n\n ///\n /// The offset of the TPM binary passed to 16-bit CSM.\n ///\n UINT16 TpmOffset;\n\n ///\n /// A pointer to a string identifying the independent BIOS vendor.\n ///\n UINT32 IbvPointer;\n\n ///\n /// This field is NULL for all systems not supporting PCI Express. This field is the base\n /// value of the start of the PCI Express memory-mapped configuration registers and\n /// must be filled in prior to EfiCompatibility code issuing the Compatibility16 function\n /// Compatibility16InitializeYourself().\n /// Compatibility16InitializeYourself() is defined in Compatibility16\n /// Functions.\n ///\n UINT32 PciExpressBase;\n\n ///\n /// Maximum PCI bus number assigned.\n ///\n UINT8 LastPciBus;\n\n ///\n /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If\n /// UmaAddress is a valid address in the shadow RAM, it also indicates that the region\n /// from 0xC0000 to (UmaAddress - 1) can be used for Option ROM.\n ///\n UINT32 UmaAddress;\n\n ///\n /// Upper Memory Area size in bytes to be set as Read/Write. If zero, no UMA region\n /// will be set as Read/Write (i.e. all Shadow RAM is set as Read-Only).\n ///\n UINT32 UmaSize;\n\n ///\n /// Start Address of high memory that can be used for permanent allocation. If zero,\n /// high memory is not available for permanent allocation.\n ///\n UINT32 HiPermanentMemoryAddress;\n\n ///\n /// Size of high memory that can be used for permanent allocation in bytes. If zero,\n /// high memory is not available for permanent allocation.\n ///\n UINT32 HiPermanentMemorySize;\n\n ///\n /// CSMWrap extension. 32-bit physical address of a u8 array of extra\n /// PCI root bus numbers (i.e., roots other than bus 0). Zero if the\n /// loader does not provide a list.\n ///\n UINT32 ExtraPciRootListPointer;\n\n ///\n /// CSMWrap extension. Number of entries in the array pointed to by\n /// ExtraPciRootListPointer.\n ///\n UINT8 ExtraPciRootListCount;\n} EFI_COMPATIBILITY16_TABLE;\n\n///\n/// Functions provided by the CSM binary which communicate between the EfiCompatibility\n/// and Compatibility16 code.\n///\n/// Inconsistent with the specification here:\n/// The member's name started with \"Compatibility16\" [defined in Intel Framework\n/// Compatibility Support Module Specification / 0.97 version]\n/// has been changed to \"Legacy16\" since keeping backward compatible.\n///\ntypedef enum {\n ///\n /// Causes the Compatibility16 code to do any internal initialization required.\n /// Input:\n /// AX = Compatibility16InitializeYourself\n /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE\n /// Return:\n /// AX = Return Status codes\n ///\n Legacy16InitializeYourself = 0x0000,\n\n ///\n /// Causes the Compatibility16 BIOS to perform any drive number translations to match the boot sequence.\n /// Input:\n /// AX = Compatibility16UpdateBbs\n /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE\n /// Return:\n /// AX = Returned status codes\n ///\n Legacy16UpdateBbs = 0x0001,\n\n ///\n /// Allows the Compatibility16 code to perform any final actions before booting. The Compatibility16\n /// code is read/write.\n /// Input:\n /// AX = Compatibility16PrepareToBoot\n /// ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure\n /// Return:\n /// AX = Returned status codes\n ///\n Legacy16PrepareToBoot = 0x0002,\n\n ///\n /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is Read/Only.\n /// Input:\n /// AX = Compatibility16Boot\n /// Output:\n /// AX = Returned status codes\n ///\n Legacy16Boot = 0x0003,\n\n ///\n /// Allows the Compatibility16 code to get the last device from which a boot was attempted. This is\n /// stored in CMOS and is the priority number of the last attempted boot device.\n /// Input:\n /// AX = Compatibility16RetrieveLastBootDevice\n /// Output:\n /// AX = Returned status codes\n /// BX = Priority number of the boot device.\n ///\n Legacy16RetrieveLastBootDevice = 0x0004,\n\n ///\n /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 after dispatching a legacy OpROM.\n /// Input:\n /// AX = Compatibility16DispatchOprom\n /// ES:BX = Pointer to EFI_DISPATCH_OPROM_TABLE\n /// Output:\n /// AX = Returned status codes\n /// BX = Number of non-BBS-compliant devices found. Equals 0 if BBS compliant.\n ///\n Legacy16DispatchOprom = 0x0005,\n\n ///\n /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified length and returns the address\n /// of that region.\n /// Input:\n /// AX = Compatibility16GetTableAddress\n /// BX = Allocation region\n /// 00 = Allocate from either 0xE0000 or 0xF0000 64 KB blocks.\n /// Bit 0 = 1 Allocate from 0xF0000 64 KB block\n /// Bit 1 = 1 Allocate from 0xE0000 64 KB block\n /// CX = Requested length in bytes.\n /// DX = Required address alignment. Bit mapped. First non-zero bit from the right is the alignment.\n /// Output:\n /// AX = Returned status codes\n /// DS:BX = Address of the region\n ///\n Legacy16GetTableAddress = 0x0006,\n\n ///\n /// Enables the EfiCompatibility module to do any nonstandard processing of keyboard LEDs or state.\n /// Input:\n /// AX = Compatibility16SetKeyboardLeds\n /// CL = LED status.\n /// Bit 0 Scroll Lock 0 = Off\n /// Bit 1 NumLock\n /// Bit 2 Caps Lock\n /// Output:\n /// AX = Returned status codes\n ///\n Legacy16SetKeyboardLeds = 0x0007,\n\n ///\n /// Enables the EfiCompatibility module to install an interrupt handler for PCI mass media devices that\n /// do not have an OpROM associated with them. An example is SATA.\n /// Input:\n /// AX = Compatibility16InstallPciHandler\n /// ES:BX = Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure\n /// Output:\n /// AX = Returned status codes\n ///\n Legacy16InstallPciHandler = 0x0008\n} EFI_COMPATIBILITY_FUNCTIONS;\n\n\n///\n/// EFI_DISPATCH_OPROM_TABLE\n///\ntypedef struct {\n UINT16 PnPInstallationCheckSegment; ///< A pointer to the PnpInstallationCheck data structure.\n UINT16 PnPInstallationCheckOffset; ///< A pointer to the PnpInstallationCheck data structure.\n UINT16 OpromSegment; ///< The segment where the OpROM was placed. Offset is assumed to be 3.\n UINT8 PciBus; ///< The PCI bus.\n UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI function.\n UINT8 NumberBbsEntries; ///< The number of valid BBS table entries upon entry and exit. The IBV code may\n ///< increase this number, if BBS-compliant devices also hook INTs in order to force the\n ///< OpROM BIOS Setup to be executed.\n UINT32 BbsTablePointer; ///< A pointer to the BBS table.\n UINT16 RuntimeSegment; ///< The segment where the OpROM can be relocated to. If this value is 0x0000, this\n ///< means that the relocation of this run time code is not supported.\n ///< Inconsistent with specification here:\n ///< The member's name \"OpromDestinationSegment\" [defined in Intel Framework Compatibility Support Module Specification / 0.97 version]\n ///< has been changed to \"RuntimeSegment\" since keeping backward compatible.\n\n} EFI_DISPATCH_OPROM_TABLE;\n\n///\n/// EFI_TO_COMPATIBILITY16_INIT_TABLE\n///\ntypedef struct {\n ///\n /// Starting address of memory under 1 MB. The ending address is assumed to be 640 KB or 0x9FFFF.\n ///\n UINT32 BiosLessThan1MB;\n\n ///\n /// The starting address of the high memory block.\n ///\n UINT32 HiPmmMemory;\n\n ///\n /// The length of high memory block.\n ///\n UINT32 HiPmmMemorySizeInBytes;\n\n ///\n /// The segment of the reverse thunk call code.\n ///\n UINT16 ReverseThunkCallSegment;\n\n ///\n /// The offset of the reverse thunk call code.\n ///\n UINT16 ReverseThunkCallOffset;\n\n ///\n /// The number of E820 entries copied to the Compatibility16 BIOS.\n ///\n UINT32 NumberE820Entries;\n\n ///\n /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory.\n ///\n UINT32 OsMemoryAbove1Mb;\n\n ///\n /// The start of thunk code in main memory. Memory cannot be used by BIOS or PMM.\n ///\n UINT32 ThunkStart;\n\n ///\n /// The size of the thunk code.\n ///\n UINT32 ThunkSizeInBytes;\n\n ///\n /// Starting address of memory under 1 MB.\n ///\n UINT32 LowPmmMemory;\n\n ///\n /// The length of low Memory block.\n ///\n UINT32 LowPmmMemorySizeInBytes;\n} EFI_TO_COMPATIBILITY16_INIT_TABLE;\n\n///\n/// DEVICE_PRODUCER_SERIAL.\n///\ntypedef struct {\n UINT16 Address; ///< I/O address assigned to the serial port.\n UINT8 Irq; ///< IRQ assigned to the serial port.\n SERIAL_MODE Mode; ///< Mode of serial port. Values are defined below.\n} DEVICE_PRODUCER_SERIAL;\n\n///\n/// DEVICE_PRODUCER_SERIAL's modes.\n///@{\n#define DEVICE_SERIAL_MODE_NORMAL 0x00\n#define DEVICE_SERIAL_MODE_IRDA 0x01\n#define DEVICE_SERIAL_MODE_ASK_IR 0x02\n#define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00\n#define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10\n///@)\n\n///\n/// DEVICE_PRODUCER_PARALLEL.\n///\ntypedef struct {\n UINT16 Address; ///< I/O address assigned to the parallel port.\n UINT8 Irq; ///< IRQ assigned to the parallel port.\n UINT8 Dma; ///< DMA assigned to the parallel port.\n PARALLEL_MODE Mode; ///< Mode of the parallel port. Values are defined below.\n} DEVICE_PRODUCER_PARALLEL;\n\n///\n/// DEVICE_PRODUCER_PARALLEL's modes.\n///@{\n#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00\n#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01\n#define DEVICE_PARALLEL_MODE_MODE_EPP 0x02\n#define DEVICE_PARALLEL_MODE_MODE_ECP 0x03\n///@}\n\n///\n/// DEVICE_PRODUCER_FLOPPY\n///\ntypedef struct {\n UINT16 Address; ///< I/O address assigned to the floppy.\n UINT8 Irq; ///< IRQ assigned to the floppy.\n UINT8 Dma; ///< DMA assigned to the floppy.\n UINT8 NumberOfFloppy; ///< Number of floppies in the system.\n} DEVICE_PRODUCER_FLOPPY;\n\n///\n/// LEGACY_DEVICE_FLAGS\n///\ntypedef struct {\n UINT32 A20Kybd : 1; ///< A20 controller by keyboard controller.\n UINT32 A20Port90 : 1; ///< A20 controlled by port 0x92.\n UINT32 Reserved : 30; ///< Reserved for future usage.\n} LEGACY_DEVICE_FLAGS;\n\n///\n/// DEVICE_PRODUCER_DATA_HEADER\n///\ntypedef struct {\n DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial port x. Type DEVICE_PRODUCER_SERIAL is defined below.\n DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel port x. Type DEVICE_PRODUCER_PARALLEL is defined below.\n DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. Type DEVICE_PRODUCER_FLOPPY is defined below.\n UINT8 MousePresent; ///< Flag to indicate if mouse is present.\n LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boolean state information passed to CSM.\n} DEVICE_PRODUCER_DATA_HEADER;\n\n///\n/// ATAPI_IDENTIFY\n///\ntypedef struct {\n UINT16 Raw[256]; ///< Raw data from the IDE IdentifyDrive command.\n} ATAPI_IDENTIFY;\n\n///\n/// HDD_INFO\n///\ntypedef struct {\n ///\n /// Status of IDE device. Values are defined below. There is one HDD_INFO structure\n /// per IDE controller. The IdentifyDrive is per drive. Index 0 is master and index\n /// 1 is slave.\n ///\n UINT16 Status;\n\n ///\n /// PCI bus of IDE controller.\n ///\n UINT32 Bus;\n\n ///\n /// PCI device of IDE controller.\n ///\n UINT32 Device;\n\n ///\n /// PCI function of IDE controller.\n ///\n UINT32 Function;\n\n ///\n /// Command ports base address.\n ///\n UINT16 CommandBaseAddress;\n\n ///\n /// Control ports base address.\n ///\n UINT16 ControlBaseAddress;\n\n ///\n /// Bus master address.\n ///\n UINT16 BusMasterAddress;\n\n UINT8 HddIrq;\n\n ///\n /// Data that identifies the drive data; one per possible attached drive.\n ///\n ATAPI_IDENTIFY IdentifyDrive[2];\n} HDD_INFO;\n\n///\n/// HDD_INFO status bits\n///\n#define HDD_PRIMARY 0x01\n#define HDD_SECONDARY 0x02\n#define HDD_MASTER_ATAPI_CDROM 0x04\n#define HDD_SLAVE_ATAPI_CDROM 0x08\n#define HDD_MASTER_IDE 0x20\n#define HDD_SLAVE_IDE 0x40\n#define HDD_MASTER_ATAPI_ZIPDISK 0x10\n#define HDD_SLAVE_ATAPI_ZIPDISK 0x80\n\n///\n/// BBS_STATUS_FLAGS;\\.\n///\ntypedef struct {\n UINT16 OldPosition : 4; ///< Prior priority.\n UINT16 Reserved1 : 4; ///< Reserved for future use.\n UINT16 Enabled : 1; ///< If 0, ignore this entry.\n UINT16 Failed : 1; ///< 0 = Not known if boot failure occurred.\n ///< 1 = Boot attempted failed.\n\n ///\n /// State of media present.\n /// 00 = No bootable media is present in the device.\n /// 01 = Unknown if a bootable media present.\n /// 10 = Media is present and appears bootable.\n /// 11 = Reserved.\n ///\n UINT16 MediaPresent : 2;\n UINT16 Reserved2 : 4; ///< Reserved for future use.\n} BBS_STATUS_FLAGS;\n\n///\n/// BBS_TABLE, device type values & boot priority values.\n///\ntypedef struct {\n ///\n /// The boot priority for this boot device. Values are defined below.\n ///\n UINT16 BootPriority;\n\n ///\n /// The PCI bus for this boot device.\n ///\n UINT32 Bus;\n\n ///\n /// The PCI device for this boot device.\n ///\n UINT32 Device;\n\n ///\n /// The PCI function for the boot device.\n ///\n UINT32 Function;\n\n ///\n /// The PCI class for this boot device.\n ///\n UINT8 Class;\n\n ///\n /// The PCI Subclass for this boot device.\n ///\n UINT8 SubClass;\n\n ///\n /// Segment:offset address of an ASCIIZ description string describing the manufacturer.\n ///\n UINT16 MfgStringOffset;\n\n ///\n /// Segment:offset address of an ASCIIZ description string describing the manufacturer.\n ///\n UINT16 MfgStringSegment;\n\n ///\n /// BBS device type. BBS device types are defined below.\n ///\n UINT16 DeviceType;\n\n ///\n /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below.\n ///\n BBS_STATUS_FLAGS StatusFlags;\n\n ///\n /// Segment:Offset address of boot loader for IPL devices or install INT13 handler for\n /// BCV devices.\n ///\n UINT16 BootHandlerOffset;\n\n ///\n /// Segment:Offset address of boot loader for IPL devices or install INT13 handler for\n /// BCV devices.\n ///\n UINT16 BootHandlerSegment;\n\n ///\n /// Segment:offset address of an ASCIIZ description string describing this device.\n ///\n UINT16 DescStringOffset;\n\n ///\n /// Segment:offset address of an ASCIIZ description string describing this device.\n ///\n UINT16 DescStringSegment;\n\n ///\n /// Reserved.\n ///\n UINT32 InitPerReserved;\n\n ///\n /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\n /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\n /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\n ///\n UINT32 AdditionalIrq13Handler;\n\n ///\n /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\n /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\n /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\n ///\n UINT32 AdditionalIrq18Handler;\n\n ///\n /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\n /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\n /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\n ///\n UINT32 AdditionalIrq19Handler;\n\n ///\n /// The use of these fields is IBV dependent. They can be used to flag that an OpROM\n /// has hooked the specified IRQ. The OpROM may be BBS compliant as some SCSI\n /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS Setup\n ///\n UINT32 AdditionalIrq40Handler;\n UINT8 AssignedDriveNumber;\n UINT32 AdditionalIrq41Handler;\n UINT32 AdditionalIrq46Handler;\n UINT32 IBV1;\n UINT32 IBV2;\n} BBS_TABLE;\n\n///\n/// BBS device type values\n///@{\n#define BBS_FLOPPY 0x01\n#define BBS_HARDDISK 0x02\n#define BBS_CDROM 0x03\n#define BBS_PCMCIA 0x04\n#define BBS_USB 0x05\n#define BBS_EMBED_NETWORK 0x06\n#define BBS_BEV_DEVICE 0x80\n#define BBS_UNKNOWN 0xff\n///@}\n\n///\n/// BBS boot priority values\n///@{\n#define BBS_DO_NOT_BOOT_FROM 0xFFFC\n#define BBS_LOWEST_PRIORITY 0xFFFD\n#define BBS_UNPRIORITIZED_ENTRY 0xFFFE\n#define BBS_IGNORE_ENTRY 0xFFFF\n///@}\n\n///\n/// SMM_ATTRIBUTES\n///\ntypedef struct {\n ///\n /// Access mechanism used to generate the soft SMI. Defined types are below. The other\n /// values are reserved for future usage.\n ///\n UINT16 Type : 3;\n\n ///\n /// The size of \"port\" in bits. Defined values are below.\n ///\n UINT16 PortGranularity : 3;\n\n ///\n /// The size of data in bits. Defined values are below.\n ///\n UINT16 DataGranularity : 3;\n\n ///\n /// Reserved for future use.\n ///\n UINT16 Reserved : 7;\n} SMM_ATTRIBUTES;\n\n///\n/// SMM_ATTRIBUTES type values.\n///@{\n#define STANDARD_IO 0x00\n#define STANDARD_MEMORY 0x01\n///@}\n\n///\n/// SMM_ATTRIBUTES port size constants.\n///@{\n#define PORT_SIZE_8 0x00\n#define PORT_SIZE_16 0x01\n#define PORT_SIZE_32 0x02\n#define PORT_SIZE_64 0x03\n///@}\n\n///\n/// SMM_ATTRIBUTES data size constants.\n///@{\n#define DATA_SIZE_8 0x00\n#define DATA_SIZE_16 0x01\n#define DATA_SIZE_32 0x02\n#define DATA_SIZE_64 0x03\n///@}\n\n///\n/// SMM_FUNCTION & relating constants.\n///\ntypedef struct {\n UINT16 Function : 15;\n UINT16 Owner : 1;\n} SMM_FUNCTION;\n\n///\n/// SMM_FUNCTION Function constants.\n///@{\n#define INT15_D042 0x0000\n#define GET_USB_BOOT_INFO 0x0001\n#define DMI_PNP_50_57 0x0002\n///@}\n\n///\n/// SMM_FUNCTION Owner constants.\n///@{\n#define STANDARD_OWNER 0x0\n#define OEM_OWNER 0x1\n///@}\n\n///\n/// This structure assumes both port and data sizes are 1. SmmAttribute must be\n/// properly to reflect that assumption.\n///\ntypedef struct {\n ///\n /// Describes the access mechanism, SmmPort, and SmmData sizes. Type\n /// SMM_ATTRIBUTES is defined below.\n ///\n SMM_ATTRIBUTES SmmAttributes;\n\n ///\n /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below.\n ///\n SMM_FUNCTION SmmFunction;\n\n ///\n /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16 bytes.\n ///\n UINT8 SmmPort;\n\n ///\n /// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16 bytes.\n ///\n UINT8 SmmData;\n} SMM_ENTRY;\n\n///\n/// SMM_TABLE\n///\ntypedef struct {\n UINT16 NumSmmEntries; ///< Number of entries represented by SmmEntry.\n SMM_ENTRY SmmEntry; ///< One entry per function. Type SMM_ENTRY is defined below.\n} SMM_TABLE;\n\n///\n/// UDC_ATTRIBUTES\n///\ntypedef struct {\n ///\n /// This bit set indicates that the ServiceAreaData is valid.\n ///\n UINT8 DirectoryServiceValidity : 1;\n\n ///\n /// This bit set indicates to use the Reserve Area Boot Code Address (RACBA) only if\n /// DirectoryServiceValidity is 0.\n ///\n UINT8 RabcaUsedFlag : 1;\n\n ///\n /// This bit set indicates to execute hard disk diagnostics.\n ///\n UINT8 ExecuteHddDiagnosticsFlag : 1;\n\n ///\n /// Reserved for future use. Set to 0.\n ///\n UINT8 Reserved : 5;\n} UDC_ATTRIBUTES;\n\n///\n/// UD_TABLE\n///\ntypedef struct {\n ///\n /// This field contains the bit-mapped attributes of the PARTIES information. Type\n /// UDC_ATTRIBUTES is defined below.\n ///\n UDC_ATTRIBUTES Attributes;\n\n ///\n /// This field contains the zero-based device on which the selected\n /// ServiceDataArea is present. It is 0 for master and 1 for the slave device.\n ///\n UINT8 DeviceNumber;\n\n ///\n /// This field contains the zero-based index into the BbsTable for the parent device.\n /// This index allows the user to reference the parent device information such as PCI\n /// bus, device function.\n ///\n UINT8 BbsTableEntryNumberForParentDevice;\n\n ///\n /// This field contains the zero-based index into the BbsTable for the boot entry.\n ///\n UINT8 BbsTableEntryNumberForBoot;\n\n ///\n /// This field contains the zero-based index into the BbsTable for the HDD diagnostics entry.\n ///\n UINT8 BbsTableEntryNumberForHddDiag;\n\n ///\n /// The raw Beer data.\n ///\n UINT8 BeerData[128];\n\n ///\n /// The raw data of selected service area.\n ///\n UINT8 ServiceAreaData[64];\n} UD_TABLE;\n\n#define EFI_TO_LEGACY_MAJOR_VERSION 0x02\n#define EFI_TO_LEGACY_MINOR_VERSION 0x00\n#define MAX_IDE_CONTROLLER 8\n\n///\n/// EFI_TO_COMPATIBILITY16_BOOT_TABLE\n///\ntypedef struct {\n UINT16 MajorVersion; ///< The EfiCompatibility major version number.\n UINT16 MinorVersion; ///< The EfiCompatibility minor version number.\n UINT32 AcpiTable; ///< The location of the RSDT ACPI table. < 4G range.\n UINT32 SmbiosTable; ///< The location of the SMBIOS table in EFI memory. < 4G range.\n UINT32 SmbiosTableLength;\n //\n // Legacy SIO state\n //\n DEVICE_PRODUCER_DATA_HEADER SioData; ///< Standard traditional device information.\n UINT16 DevicePathType; ///< The default boot type.\n UINT16 PciIrqMask; ///< Mask of which IRQs have been assigned to PCI.\n UINT32 NumberE820Entries; ///< Number of E820 entries. The number can change from the\n ///< Compatibility16InitializeYourself() function.\n //\n // Controller & Drive Identify[2] per controller information\n //\n HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Hard disk drive information, including raw Identify Drive data.\n UINT32 NumberBbsEntries; ///< Number of entries in the BBS table\n UINT32 BbsTable; ///< A pointer to the BBS table. Type BBS_TABLE is defined below.\n UINT32 SmmTable; ///< A pointer to the SMM table. Type SMM_TABLE is defined below.\n UINT32 OsMemoryAbove1Mb; ///< The amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can\n ///< differ from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more\n ///< memory may have been discovered.\n UINT32 UnconventionalDeviceTable; ///< Information to boot off an unconventional device like a PARTIES partition. Type\n ///< UD_TABLE is defined below.\n //\n // CSMWrap extension: MP table pointer (not part of original EFI CSM spec)\n //\n UINT32 MpTable; ///< The location of the MP floating pointer structure. < 4G range.\n} EFI_TO_COMPATIBILITY16_BOOT_TABLE;\n\n///\n/// EFI_LEGACY_INSTALL_PCI_HANDLER\n///\ntypedef struct {\n UINT8 PciBus; ///< The PCI bus of the device.\n UINT8 PciDeviceFun; ///< The PCI device in bits 7:3 and function in bits 2:0.\n UINT8 PciSegment; ///< The PCI segment of the device.\n UINT8 PciClass; ///< The PCI class code of the device.\n UINT8 PciSubclass; ///< The PCI subclass code of the device.\n UINT8 PciInterface; ///< The PCI interface code of the device.\n //\n // Primary section\n //\n UINT8 PrimaryIrq; ///< The primary device IRQ.\n UINT8 PrimaryReserved; ///< Reserved.\n UINT16 PrimaryControl; ///< The primary device control I/O base.\n UINT16 PrimaryBase; ///< The primary device I/O base.\n UINT16 PrimaryBusMaster; ///< The primary device bus master I/O base.\n //\n // Secondary Section\n //\n UINT8 SecondaryIrq; ///< The secondary device IRQ.\n UINT8 SecondaryReserved; ///< Reserved.\n UINT16 SecondaryControl; ///< The secondary device control I/O base.\n UINT16 SecondaryBase; ///< The secondary device I/O base.\n UINT16 SecondaryBusMaster; ///< The secondary device bus master I/O base.\n} EFI_LEGACY_INSTALL_PCI_HANDLER;\n\n//\n// Restore default pack value\n//\n#pragma pack()\n\n#define EFI_LEGACY_BIOS_PROTOCOL_GUID \\\n { \\\n 0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } \\\n }\n\ntypedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL;\n\n///\n/// Flags returned by CheckPciRom().\n///\n#define NO_ROM 0x00\n#define ROM_FOUND 0x01\n#define VALID_LEGACY_ROM 0x02\n#define ROM_WITH_CONFIG 0x04 ///< Not defined in the Framework CSM Specification.\n\n///\n/// The following macros do not appear in the Framework CSM Specification and\n/// are kept for backward compatibility only. They convert 32-bit address (_Adr)\n/// to Segment:Offset 16-bit form.\n///\n///@{\n#define EFI_SEGMENT(_Adr) (UINT16) ((UINT16) (((UINTN) (_Adr)) >> 4) & 0xf000)\n#define EFI_OFFSET(_Adr) (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xffff)\n///@}\n\n#define CARRY_FLAG 0x01\n\n///\n/// EFI_EFLAGS_REG\n///\ntypedef struct {\n UINT32 CF:1;\n UINT32 Reserved1:1;\n UINT32 PF:1;\n UINT32 Reserved2:1;\n UINT32 AF:1;\n UINT32 Reserved3:1;\n UINT32 ZF:1;\n UINT32 SF:1;\n UINT32 TF:1;\n UINT32 IF:1;\n UINT32 DF:1;\n UINT32 OF:1;\n UINT32 IOPL:2;\n UINT32 NT:1;\n UINT32 Reserved4:2;\n UINT32 VM:1;\n UINT32 Reserved5:14;\n} EFI_EFLAGS_REG;\n\n///\n/// EFI_DWORD_REGS\n///\ntypedef struct {\n UINT32 EAX;\n UINT32 EBX;\n UINT32 ECX;\n UINT32 EDX;\n UINT32 ESI;\n UINT32 EDI;\n EFI_EFLAGS_REG EFlags;\n UINT16 ES;\n UINT16 CS;\n UINT16 SS;\n UINT16 DS;\n UINT16 FS;\n UINT16 GS;\n UINT32 EBP;\n UINT32 ESP;\n} EFI_DWORD_REGS;\n\n///\n/// EFI_FLAGS_REG\n///\ntypedef struct {\n UINT16 CF:1;\n UINT16 Reserved1:1;\n UINT16 PF:1;\n UINT16 Reserved2:1;\n UINT16 AF:1;\n UINT16 Reserved3:1;\n UINT16 ZF:1;\n UINT16 SF:1;\n UINT16 TF:1;\n UINT16 IF:1;\n UINT16 DF:1;\n UINT16 OF:1;\n UINT16 IOPL:2;\n UINT16 NT:1;\n UINT16 Reserved4:1;\n} EFI_FLAGS_REG;\n\n///\n/// EFI_WORD_REGS\n///\ntypedef struct {\n UINT16 AX;\n UINT16 ReservedAX;\n UINT16 BX;\n UINT16 ReservedBX;\n UINT16 CX;\n UINT16 ReservedCX;\n UINT16 DX;\n UINT16 ReservedDX;\n UINT16 SI;\n UINT16 ReservedSI;\n UINT16 DI;\n UINT16 ReservedDI;\n EFI_FLAGS_REG Flags;\n UINT16 ReservedFlags;\n UINT16 ES;\n UINT16 CS;\n UINT16 SS;\n UINT16 DS;\n UINT16 FS;\n UINT16 GS;\n UINT16 BP;\n UINT16 ReservedBP;\n UINT16 SP;\n UINT16 ReservedSP;\n} EFI_WORD_REGS;\n\n///\n/// EFI_BYTE_REGS\n///\ntypedef struct {\n UINT8 AL, AH;\n UINT16 ReservedAX;\n UINT8 BL, BH;\n UINT16 ReservedBX;\n UINT8 CL, CH;\n UINT16 ReservedCX;\n UINT8 DL, DH;\n UINT16 ReservedDX;\n} EFI_BYTE_REGS;\n\n///\n/// EFI_IA32_REGISTER_SET\n///\ntypedef union {\n EFI_DWORD_REGS E;\n EFI_WORD_REGS X;\n EFI_BYTE_REGS H;\n} EFI_IA32_REGISTER_SET;\n\n/**\n Thunk to 16-bit real mode and execute a software interrupt with a vector\n of BiosInt. Regs will contain the 16-bit register context on entry and\n exit.\n\n @param[in] This The protocol instance pointer.\n @param[in] BiosInt The processor interrupt vector to invoke.\n @param[in,out] Reg Register contexted passed into (and returned) from thunk to\n 16-bit mode.\n\n @retval TRUE Thunk completed with no BIOS errors in the target code. See Regs for status.\n @retval FALSE There was a BIOS error in the target code.\n**/\ntypedef\nBOOLEAN\n(EFIAPI *EFI_LEGACY_BIOS_INT86)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UINT8 BiosInt,\n IN OUT EFI_IA32_REGISTER_SET *Regs\n );\n\n/**\n Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the\n 16-bit register context on entry and exit. Arguments can be passed on\n the Stack argument\n\n @param[in] This The protocol instance pointer.\n @param[in] Segment The segemnt of 16-bit mode call.\n @param[in] Offset The offset of 16-bit mdoe call.\n @param[in] Reg Register contexted passed into (and returned) from thunk to\n 16-bit mode.\n @param[in] Stack The caller allocated stack used to pass arguments.\n @param[in] StackSize The size of Stack in bytes.\n\n @retval FALSE Thunk completed with no BIOS errors in the target code. See Regs for status. @retval TRUE There was a BIOS error in the target code.\n**/\ntypedef\nBOOLEAN\n(EFIAPI *EFI_LEGACY_BIOS_FARCALL86)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UINT16 Segment,\n IN UINT16 Offset,\n IN EFI_IA32_REGISTER_SET *Regs,\n IN VOID *Stack,\n IN UINTN StackSize\n );\n\n/**\n Test to see if a legacy PCI ROM exists for this device. Optionally return\n the Legacy ROM instance for this PCI device.\n\n @param[in] This The protocol instance pointer.\n @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded\n @param[out] RomImage Return the legacy PCI ROM for this device.\n @param[out] RomSize The size of ROM Image.\n @param[out] Flags Indicates if ROM found and if PC-AT. Multiple bits can be set as follows:\n - 00 = No ROM.\n - 01 = ROM Found.\n - 02 = ROM is a valid legacy ROM.\n\n @retval EFI_SUCCESS The Legacy Option ROM available for this device\n @retval EFI_UNSUPPORTED The Legacy Option ROM is not supported.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_CHECK_ROM)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN EFI_HANDLE PciHandle,\n OUT VOID **RomImage, OPTIONAL\n OUT UINTN *RomSize, OPTIONAL\n OUT UINTN *Flags\n );\n\n/**\n Load a legacy PC-AT OPROM on the PciHandle device. Return information\n about how many disks were added by the OPROM and the shadow address and\n size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:\n\n @param[in] This The protocol instance pointer.\n @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded.\n This value is NULL if RomImage is non-NULL. This is the normal\n case.\n @param[in] RomImage A PCI PC-AT ROM image. This argument is non-NULL if there is\n no hardware associated with the ROM and thus no PciHandle,\n otherwise is must be NULL.\n Example is PXE base code.\n @param[out] Flags The type of ROM discovered. Multiple bits can be set, as follows:\n - 00 = No ROM.\n - 01 = ROM found.\n - 02 = ROM is a valid legacy ROM.\n @param[out] DiskStart The disk number of first device hooked by the ROM. If DiskStart\n is the same as DiskEnd no disked were hooked.\n @param[out] DiskEnd disk number of the last device hooked by the ROM.\n @param[out] RomShadowAddress Shadow address of PC-AT ROM.\n @param[out] RomShadowSize Size of RomShadowAddress in bytes.\n\n @retval EFI_SUCCESS Thunk completed, see Regs for status.\n @retval EFI_INVALID_PARAMETER PciHandle not found\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_INSTALL_ROM)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN EFI_HANDLE PciHandle,\n IN VOID **RomImage,\n OUT UINTN *Flags,\n OUT UINT8 *DiskStart, OPTIONAL\n OUT UINT8 *DiskEnd, OPTIONAL\n OUT VOID **RomShadowAddress, OPTIONAL\n OUT UINT32 *ShadowedRomSize OPTIONAL\n );\n\n/**\n This function attempts to traditionally boot the specified BootOption. If the EFI context has\n been compromised, this function will not return. This procedure is not used for loading an EFI-aware\n OS off a traditional device. The following actions occur:\n - Get EFI SMBIOS data structures, convert them to a traditional format, and copy to\n Compatibility16.\n - Get a pointer to ACPI data structures and copy the Compatibility16 RSD PTR to F0000 block.\n - Find the traditional SMI handler from a firmware volume and register the traditional SMI\n handler with the EFI SMI handler.\n - Build onboard IDE information and pass this information to the Compatibility16 code.\n - Make sure all PCI Interrupt Line registers are programmed to match 8259.\n - Reconfigure SIO devices from EFI mode (polled) into traditional mode (interrupt driven).\n - Shadow all PCI ROMs.\n - Set up BDA and EBDA standard areas before the legacy boot.\n - Construct the Compatibility16 boot memory map and pass it to the Compatibility16 code.\n - Invoke the Compatibility16 table function Compatibility16PrepareToBoot(). This\n invocation causes a thunk into the Compatibility16 code, which sets all appropriate internal\n data structures. The boot device list is a parameter.\n - Invoke the Compatibility16 Table function Compatibility16Boot(). This invocation\n causes a thunk into the Compatibility16 code, which does an INT19.\n - If the Compatibility16Boot() function returns, then the boot failed in a graceful\n manner--meaning that the EFI code is still valid. An ungraceful boot failure causes a reset because the state\n of EFI code is unknown.\n\n @param[in] This The protocol instance pointer.\n @param[in] BootOption The EFI Device Path from BootXXXX variable.\n @param[in] LoadOptionSize The size of LoadOption in size.\n @param[in] LoadOption LThe oadOption from BootXXXX variable.\n\n @retval EFI_DEVICE_ERROR Failed to boot from any boot device and memory is uncorrupted. Note: This function normally does not returns. It will either boot the OS or reset the system if memory has been \"corrupted\" by loading a boot sector and passing control to it.\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_BOOT)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN BBS_BBS_DEVICE_PATH *BootOption,\n IN UINT32 LoadOptionsSize,\n IN VOID *LoadOptions\n );\n\n/**\n This function takes the Leds input parameter and sets/resets the BDA accordingly.\n Leds is also passed to Compatibility16 code, in case any special processing is required.\n This function is normally called from EFI Setup drivers that handle user-selectable\n keyboard options such as boot with NUM LOCK on/off. This function does not\n touch the keyboard or keyboard LEDs but only the BDA.\n\n @param[in] This The protocol instance pointer.\n @param[in] Leds The status of current Scroll, Num & Cap lock LEDS:\n - Bit 0 is Scroll Lock 0 = Not locked.\n - Bit 1 is Num Lock.\n - Bit 2 is Caps Lock.\n\n @retval EFI_SUCCESS The BDA was updated successfully.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UINT8 Leds\n );\n\n/**\n Retrieve legacy BBS info and assign boot priority.\n\n @param[in] This The protocol instance pointer.\n @param[out] HddCount The number of HDD_INFO structures.\n @param[out] HddInfo Onboard IDE controller information.\n @param[out] BbsCount The number of BBS_TABLE structures.\n @param[in,out] BbsTable Points to List of BBS_TABLE.\n\n @retval EFI_SUCCESS Tables were returned.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_GET_BBS_INFO)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n OUT UINT16 *HddCount,\n OUT HDD_INFO **HddInfo,\n OUT UINT16 *BbsCount,\n IN OUT BBS_TABLE **BbsTable\n );\n\n/**\n Assign drive number to legacy HDD drives prior to booting an EFI\n aware OS so the OS can access drives without an EFI driver.\n\n @param[in] This The protocol instance pointer.\n @param[out] BbsCount The number of BBS_TABLE structures\n @param[out] BbsTable List of BBS entries\n\n @retval EFI_SUCCESS Drive numbers assigned.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n OUT UINT16 *BbsCount,\n OUT BBS_TABLE **BbsTable\n );\n\n/**\n To boot from an unconventional device like parties and/or execute\n HDD diagnostics.\n\n @param[in] This The protocol instance pointer.\n @param[in] Attributes How to interpret the other input parameters.\n @param[in] BbsEntry The 0-based index into the BbsTable for the parent\n device.\n @param[in] BeerData A pointer to the 128 bytes of ram BEER data.\n @param[in] ServiceAreaData A pointer to the 64 bytes of raw Service Area data. The\n caller must provide a pointer to the specific Service\n Area and not the start all Service Areas.\n\n @retval EFI_INVALID_PARAMETER If error. Does NOT return if no error.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UDC_ATTRIBUTES Attributes,\n IN UINTN BbsEntry,\n IN VOID *BeerData,\n IN VOID *ServiceAreaData\n );\n\n/**\n Shadow all legacy16 OPROMs that haven't been shadowed.\n Warning: Use this with caution. This routine disconnects all EFI\n drivers. If used externally, then the caller must re-connect EFI\n drivers.\n\n @param[in] This The protocol instance pointer.\n\n @retval EFI_SUCCESS OPROMs were shadowed.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This\n );\n\n/**\n Get a region from the LegacyBios for S3 usage.\n\n @param[in] This The protocol instance pointer.\n @param[in] LegacyMemorySize The size of required region.\n @param[in] Region The region to use.\n 00 = Either 0xE0000 or 0xF0000 block.\n - Bit0 = 1 0xF0000 block.\n - Bit1 = 1 0xE0000 block.\n @param[in] Alignment Address alignment. Bit mapped. The first non-zero\n bit from right is alignment.\n @param[out] LegacyMemoryAddress The Region Assigned\n\n @retval EFI_SUCCESS The Region was assigned.\n @retval EFI_ACCESS_DENIED The function was previously invoked.\n @retval Other The Region was not assigned.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_GET_LEGACY_REGION)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UINTN LegacyMemorySize,\n IN UINTN Region,\n IN UINTN Alignment,\n OUT VOID **LegacyMemoryAddress\n );\n\n/**\n Get a region from the LegacyBios for Tiano usage. Can only be invoked once.\n\n @param[in] This The protocol instance pointer.\n @param[in] LegacyMemorySize The size of data to copy.\n @param[in] LegacyMemoryAddress The Legacy Region destination address.\n Note: must be in region assigned by\n LegacyBiosGetLegacyRegion.\n @param[in] LegacyMemorySourceAddress The source of the data to copy.\n\n @retval EFI_SUCCESS The Region assigned.\n @retval EFI_ACCESS_DENIED Destination was outside an assigned region.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_BIOS_COPY_LEGACY_REGION)(\n IN EFI_LEGACY_BIOS_PROTOCOL *This,\n IN UINTN LegacyMemorySize,\n IN VOID *LegacyMemoryAddress,\n IN VOID *LegacyMemorySourceAddress\n );\n\n///\n/// Abstracts the traditional BIOS from the rest of EFI. The LegacyBoot()\n/// member function allows the BDS to support booting a traditional OS.\n/// EFI thunks drivers that make EFI bindings for BIOS INT services use\n/// all the other member functions.\n///\nstruct _EFI_LEGACY_BIOS_PROTOCOL {\n ///\n /// Performs traditional software INT. See the Int86() function description.\n ///\n EFI_LEGACY_BIOS_INT86 Int86;\n\n ///\n /// Performs a far call into Compatibility16 or traditional OpROM code.\n ///\n EFI_LEGACY_BIOS_FARCALL86 FarCall86;\n\n ///\n /// Checks if a traditional OpROM exists for this device.\n ///\n EFI_LEGACY_BIOS_CHECK_ROM CheckPciRom;\n\n ///\n /// Loads a traditional OpROM in traditional OpROM address space.\n ///\n EFI_LEGACY_BIOS_INSTALL_ROM InstallPciRom;\n\n ///\n /// Boots a traditional OS.\n ///\n EFI_LEGACY_BIOS_BOOT LegacyBoot;\n\n ///\n /// Updates BDA to reflect the current EFI keyboard LED status.\n ///\n EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS UpdateKeyboardLedStatus;\n\n ///\n /// Allows an external agent, such as BIOS Setup, to get the BBS data.\n ///\n EFI_LEGACY_BIOS_GET_BBS_INFO GetBbsInfo;\n\n ///\n /// Causes all legacy OpROMs to be shadowed.\n ///\n EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS ShadowAllLegacyOproms;\n\n ///\n /// Performs all actions prior to boot. Used when booting an EFI-aware OS\n /// rather than a legacy OS.\n ///\n EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI PrepareToBootEfi;\n\n ///\n /// Allows EFI to reserve an area in the 0xE0000 or 0xF0000 block.\n ///\n EFI_LEGACY_BIOS_GET_LEGACY_REGION GetLegacyRegion;\n\n ///\n /// Allows EFI to copy data to the area specified by GetLegacyRegion.\n ///\n EFI_LEGACY_BIOS_COPY_LEGACY_REGION CopyLegacyRegion;\n\n ///\n /// Allows the user to boot off an unconventional device such as a PARTIES partition.\n ///\n EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE BootUnconventionalDevice;\n};\n\n//\n// Legacy BIOS needs to access memory in page 0 (0-4095), which is disabled if\n// NULL pointer detection feature is enabled. Following macro can be used to\n// enable/disable page 0 before/after accessing it.\n//\n#define ACCESS_PAGE0_CODE(statements) \\\n do { \\\n EFI_STATUS Status_; \\\n EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc_; \\\n \\\n Desc_.Attributes = 0; \\\n Status_ = gDS->GetMemorySpaceDescriptor (0, &Desc_); \\\n ASSERT_EFI_ERROR (Status_); \\\n if ((Desc_.Attributes & EFI_MEMORY_RP) != 0) { \\\n Status_ = gDS->SetMemorySpaceAttributes ( \\\n 0, \\\n EFI_PAGES_TO_SIZE(1), \\\n Desc_.Attributes & ~(UINT64)EFI_MEMORY_RP \\\n ); \\\n ASSERT_EFI_ERROR (Status_); \\\n } \\\n \\\n { \\\n statements; \\\n } \\\n \\\n if ((Desc_.Attributes & EFI_MEMORY_RP) != 0) { \\\n Status_ = gDS->SetMemorySpaceAttributes ( \\\n 0, \\\n EFI_PAGES_TO_SIZE(1), \\\n Desc_.Attributes \\\n ); \\\n ASSERT_EFI_ERROR (Status_); \\\n } \\\n } while (FALSE)\n\nextern EFI_GUID gEfiLegacyBiosProtocolGuid;\n\n#endif\n" }, { "path": "src/edk2/LegacyRegion2.h", "content": "/** @file\n The Legacy Region Protocol controls the read, write and boot-lock attributes for\n the region 0xC0000 to 0xFFFFF.\n\n Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n @par Revision Reference:\n This Protocol is defined in UEFI Platform Initialization Specification 1.2\n Volume 5: Standards\n\n**/\n\n#ifndef __LEGACY_REGION2_H__\n#define __LEGACY_REGION2_H__\n\n#include \n\n#define EFI_LEGACY_REGION2_PROTOCOL_GUID \\\n{ \\\n 0x70101eaf, 0x85, 0x440c, {0xb3, 0x56, 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } \\\n}\n\ntypedef struct _EFI_LEGACY_REGION2_PROTOCOL EFI_LEGACY_REGION2_PROTOCOL;\n\n/**\n Modify the hardware to allow (decode) or disallow (not decode) memory reads in a region.\n\n If the On parameter evaluates to TRUE, this function enables memory reads in the address range\n Start to (Start + Length - 1).\n If the On parameter evaluates to FALSE, this function disables memory reads in the address range\n Start to (Start + Length - 1).\n\n @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.\n @param Start[in] The beginning of the physical address of the region whose attributes\n should be modified.\n @param Length[in] The number of bytes of memory whose attributes should be modified.\n The actual number of bytes modified may be greater than the number\n specified.\n @param Granularity[out] The number of bytes in the last region affected. This may be less\n than the total number of bytes affected if the starting address\n was not aligned to a region's starting address or if the length\n was greater than the number of bytes in the first region.\n @param On[in] Decode / Non-Decode flag.\n\n @retval EFI_SUCCESS The region's attributes were successfully modified.\n @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_REGION2_DECODE)(\n IN EFI_LEGACY_REGION2_PROTOCOL *This,\n IN UINT32 Start,\n IN UINT32 Length,\n OUT UINT32 *Granularity,\n IN BOOLEAN *On\n );\n\n/**\n Modify the hardware to disallow memory writes in a region.\n\n This function changes the attributes of a memory range to not allow writes.\n\n @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.\n @param Start[in] The beginning of the physical address of the region whose\n attributes should be modified.\n @param Length[in] The number of bytes of memory whose attributes should be modified.\n The actual number of bytes modified may be greater than the number\n specified.\n @param Granularity[out] The number of bytes in the last region affected. This may be less\n than the total number of bytes affected if the starting address was\n not aligned to a region's starting address or if the length was\n greater than the number of bytes in the first region.\n\n @retval EFI_SUCCESS The region's attributes were successfully modified.\n @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_REGION2_LOCK)(\n IN EFI_LEGACY_REGION2_PROTOCOL *This,\n IN UINT32 Start,\n IN UINT32 Length,\n OUT UINT32 *Granularity\n );\n\n/**\n Modify the hardware to disallow memory attribute changes in a region.\n\n This function makes the attributes of a region read only. Once a region is boot-locked with this\n function, the read and write attributes of that region cannot be changed until a power cycle has\n reset the boot-lock attribute. Calls to Decode(), Lock() and Unlock() will have no effect.\n\n @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.\n @param Start[in] The beginning of the physical address of the region whose\n attributes should be modified.\n @param Length[in] The number of bytes of memory whose attributes should be modified.\n The actual number of bytes modified may be greater than the number\n specified.\n @param Granularity[out] The number of bytes in the last region affected. This may be less\n than the total number of bytes affected if the starting address was\n not aligned to a region's starting address or if the length was\n greater than the number of bytes in the first region.\n\n @retval EFI_SUCCESS The region's attributes were successfully modified.\n @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.\n @retval EFI_UNSUPPORTED The chipset does not support locking the configuration registers in\n a way that will not affect memory regions outside the legacy memory\n region.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_REGION2_BOOT_LOCK)(\n IN EFI_LEGACY_REGION2_PROTOCOL *This,\n IN UINT32 Start,\n IN UINT32 Length,\n OUT UINT32 *Granularity OPTIONAL\n );\n\n/**\n Modify the hardware to allow memory writes in a region.\n\n This function changes the attributes of a memory range to allow writes.\n\n @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.\n @param Start[in] The beginning of the physical address of the region whose\n attributes should be modified.\n @param Length[in] The number of bytes of memory whose attributes should be modified.\n The actual number of bytes modified may be greater than the number\n specified.\n @param Granularity[out] The number of bytes in the last region affected. This may be less\n than the total number of bytes affected if the starting address was\n not aligned to a region's starting address or if the length was\n greater than the number of bytes in the first region.\n\n @retval EFI_SUCCESS The region's attributes were successfully modified.\n @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_REGION2_UNLOCK)(\n IN EFI_LEGACY_REGION2_PROTOCOL *This,\n IN UINT32 Start,\n IN UINT32 Length,\n OUT UINT32 *Granularity\n );\n\ntypedef enum {\n LegacyRegionDecoded, ///< This region is currently set to allow reads.\n LegacyRegionNotDecoded, ///< This region is currently set to not allow reads.\n LegacyRegionWriteEnabled, ///< This region is currently set to allow writes.\n LegacyRegionWriteDisabled, ///< This region is currently set to write protected.\n LegacyRegionBootLocked, ///< This region's attributes are locked, cannot be modified until\n ///< after a power cycle.\n LegacyRegionNotLocked ///< This region's attributes are not locked.\n} EFI_LEGACY_REGION_ATTRIBUTE;\n\ntypedef struct {\n ///\n /// The beginning of the physical address of this\n /// region.\n ///\n UINT32 Start;\n ///\n /// The number of bytes in this region.\n ///\n UINT32 Length;\n ///\n /// Attribute of the Legacy Region Descriptor that\n /// describes the capabilities for that memory region.\n ///\n EFI_LEGACY_REGION_ATTRIBUTE Attribute;\n ///\n /// Describes the byte length programmability\n /// associated with the Start address and the specified\n /// Attribute setting.\n UINT32 Granularity;\n} EFI_LEGACY_REGION_DESCRIPTOR;\n\n/**\n Get region information for the attributes of the Legacy Region.\n\n This function is used to discover the granularity of the attributes for the memory in the legacy\n region. Each attribute may have a different granularity and the granularity may not be the same\n for all memory ranges in the legacy region.\n\n @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.\n @param DescriptorCount[out] The number of region descriptor entries returned in the Descriptor\n buffer.\n @param Descriptor[out] A pointer to a pointer used to return a buffer where the legacy\n region information is deposited. This buffer will contain a list of\n DescriptorCount number of region descriptors. This function will\n provide the memory for the buffer.\n\n @retval EFI_SUCCESS The information structure was returned.\n @retval EFI_UNSUPPORTED This function is not supported.\n\n**/\ntypedef\nEFI_STATUS\n(EFIAPI *EFI_LEGACY_REGION_GET_INFO)(\n IN EFI_LEGACY_REGION2_PROTOCOL *This,\n OUT UINT32 *DescriptorCount,\n OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor\n );\n\n///\n/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory\n/// attributes of the Option ROM shadowing region, 0xC0000 to 0xFFFFF.\n/// There are three memory attributes that can be modified through this protocol: read, write and\n/// boot-lock. These protocols may be set in any combination.\n///\nstruct _EFI_LEGACY_REGION2_PROTOCOL {\n EFI_LEGACY_REGION2_DECODE Decode;\n EFI_LEGACY_REGION2_LOCK Lock;\n EFI_LEGACY_REGION2_BOOT_LOCK BootLock;\n EFI_LEGACY_REGION2_UNLOCK UnLock;\n EFI_LEGACY_REGION_GET_INFO GetInfo;\n};\n\n#endif\n" }, { "path": "src/edk2/Pci.h", "content": "/** @file\n Support for the latest PCI standard.\n\nCopyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCI_H_\n#define _PCI_H_\n\n#include \"PciExpress60.h\"\n#include \"PciCodeId.h\"\n\n#endif\n" }, { "path": "src/edk2/Pci22.h", "content": "/** @file\n Support for PCI 2.2 standard.\n\n This file includes the definitions in the following specifications,\n PCI Local Bus Specification, 2.2\n PCI-to-PCI Bridge Architecture Specification, Revision 1.2\n PC Card Standard, 8.0\n PCI Power Management Interface Specification, Revision 1.2\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCI22_H_\n#define _PCI22_H_\n\n#include \"Edk2Compat.h\"\n\n#define PCI_MAX_BUS 255\n#define PCI_MAX_DEVICE 31\n#define PCI_MAX_FUNC 7\n\n#pragma pack(1)\n\n///\n/// Common header region in PCI Configuration Space\n/// Section 6.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n UINT16 VendorId;\n UINT16 DeviceId;\n UINT16 Command;\n UINT16 Status;\n UINT8 RevisionID;\n UINT8 ClassCode[3];\n UINT8 CacheLineSize;\n UINT8 LatencyTimer;\n UINT8 HeaderType;\n UINT8 BIST;\n} PCI_DEVICE_INDEPENDENT_REGION;\n\n///\n/// PCI Device header region in PCI Configuration Space\n/// Section 6.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n UINT32 Bar[6];\n UINT32 CISPtr;\n UINT16 SubsystemVendorID;\n UINT16 SubsystemID;\n UINT32 ExpansionRomBar;\n UINT8 CapabilityPtr;\n UINT8 Reserved1[3];\n UINT32 Reserved2;\n UINT8 InterruptLine;\n UINT8 InterruptPin;\n UINT8 MinGnt;\n UINT8 MaxLat;\n} PCI_DEVICE_HEADER_TYPE_REGION;\n\n///\n/// PCI Device Configuration Space\n/// Section 6.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n PCI_DEVICE_INDEPENDENT_REGION Hdr;\n PCI_DEVICE_HEADER_TYPE_REGION Device;\n} PCI_TYPE00;\n\n///\n/// PCI-PCI Bridge header region in PCI Configuration Space\n/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\n///\ntypedef struct {\n UINT32 Bar[2];\n UINT8 PrimaryBus;\n UINT8 SecondaryBus;\n UINT8 SubordinateBus;\n UINT8 SecondaryLatencyTimer;\n UINT8 IoBase;\n UINT8 IoLimit;\n UINT16 SecondaryStatus;\n UINT16 MemoryBase;\n UINT16 MemoryLimit;\n UINT16 PrefetchableMemoryBase;\n UINT16 PrefetchableMemoryLimit;\n UINT32 PrefetchableBaseUpper32;\n UINT32 PrefetchableLimitUpper32;\n UINT16 IoBaseUpper16;\n UINT16 IoLimitUpper16;\n UINT8 CapabilityPtr;\n UINT8 Reserved[3];\n UINT32 ExpansionRomBAR;\n UINT8 InterruptLine;\n UINT8 InterruptPin;\n UINT16 BridgeControl;\n} PCI_BRIDGE_CONTROL_REGISTER;\n\n///\n/// PCI-to-PCI Bridge Configuration Space\n/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\n///\ntypedef struct {\n PCI_DEVICE_INDEPENDENT_REGION Hdr;\n PCI_BRIDGE_CONTROL_REGISTER Bridge;\n} PCI_TYPE01;\n\ntypedef union {\n PCI_TYPE00 Device;\n PCI_TYPE01 Bridge;\n} PCI_TYPE_GENERIC;\n\n///\n/// CardBus Controller Configuration Space,\n/// Section 4.5.1, PC Card Standard. 8.0\n///\ntypedef struct {\n UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\n UINT8 Cap_Ptr;\n UINT8 Reserved;\n UINT16 SecondaryStatus; ///< Secondary Status\n UINT8 PciBusNumber; ///< PCI Bus Number\n UINT8 CardBusBusNumber; ///< CardBus Bus Number\n UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\n UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\n UINT32 MemoryBase0; ///< Memory Base Register 0\n UINT32 MemoryLimit0; ///< Memory Limit Register 0\n UINT32 MemoryBase1;\n UINT32 MemoryLimit1;\n UINT32 IoBase0;\n UINT32 IoLimit0; ///< I/O Base Register 0\n UINT32 IoBase1; ///< I/O Limit Register 0\n UINT32 IoLimit1;\n UINT8 InterruptLine; ///< Interrupt Line\n UINT8 InterruptPin; ///< Interrupt Pin\n UINT16 BridgeControl; ///< Bridge Control\n} PCI_CARDBUS_CONTROL_REGISTER;\n\n//\n// Definitions of PCI class bytes and manipulation macros.\n//\n#define PCI_CLASS_OLD 0x00\n#define PCI_CLASS_OLD_OTHER 0x00\n#define PCI_CLASS_OLD_VGA 0x01\n\n#define PCI_CLASS_MASS_STORAGE 0x01\n#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\n#define PCI_CLASS_MASS_STORAGE_IDE 0x01\n#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\n#define PCI_CLASS_MASS_STORAGE_IPI 0x03\n#define PCI_CLASS_MASS_STORAGE_RAID 0x04\n#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\n\n#define PCI_CLASS_NETWORK 0x02\n#define PCI_CLASS_NETWORK_ETHERNET 0x00\n#define PCI_CLASS_NETWORK_TOKENRING 0x01\n#define PCI_CLASS_NETWORK_FDDI 0x02\n#define PCI_CLASS_NETWORK_ATM 0x03\n#define PCI_CLASS_NETWORK_ISDN 0x04\n#define PCI_CLASS_NETWORK_OTHER 0x80\n\n#define PCI_CLASS_DISPLAY 0x03\n#define PCI_CLASS_DISPLAY_VGA 0x00\n#define PCI_IF_VGA_VGA 0x00\n#define PCI_IF_VGA_8514 0x01\n#define PCI_CLASS_DISPLAY_XGA 0x01\n#define PCI_CLASS_DISPLAY_3D 0x02\n#define PCI_CLASS_DISPLAY_OTHER 0x80\n\n#define PCI_CLASS_MEDIA 0x04\n#define PCI_CLASS_MEDIA_VIDEO 0x00\n#define PCI_CLASS_MEDIA_AUDIO 0x01\n#define PCI_CLASS_MEDIA_TELEPHONE 0x02\n#define PCI_CLASS_MEDIA_OTHER 0x80\n\n#define PCI_CLASS_MEMORY_CONTROLLER 0x05\n#define PCI_CLASS_MEMORY_RAM 0x00\n#define PCI_CLASS_MEMORY_FLASH 0x01\n#define PCI_CLASS_MEMORY_OTHER 0x80\n\n#define PCI_CLASS_BRIDGE 0x06\n#define PCI_CLASS_BRIDGE_HOST 0x00\n#define PCI_CLASS_BRIDGE_ISA 0x01\n#define PCI_CLASS_BRIDGE_EISA 0x02\n#define PCI_CLASS_BRIDGE_MCA 0x03\n#define PCI_CLASS_BRIDGE_P2P 0x04\n#define PCI_IF_BRIDGE_P2P 0x00\n#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\n#define PCI_CLASS_BRIDGE_PCMCIA 0x05\n#define PCI_CLASS_BRIDGE_NUBUS 0x06\n#define PCI_CLASS_BRIDGE_CARDBUS 0x07\n#define PCI_CLASS_BRIDGE_RACEWAY 0x08\n#define PCI_CLASS_BRIDGE_OTHER 0x80\n#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\n\n#define PCI_CLASS_SCC 0x07///< Simple communications controllers\n#define PCI_SUBCLASS_SERIAL 0x00\n#define PCI_IF_GENERIC_XT 0x00\n#define PCI_IF_16450 0x01\n#define PCI_IF_16550 0x02\n#define PCI_IF_16650 0x03\n#define PCI_IF_16750 0x04\n#define PCI_IF_16850 0x05\n#define PCI_IF_16950 0x06\n#define PCI_SUBCLASS_PARALLEL 0x01\n#define PCI_IF_PARALLEL_PORT 0x00\n#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\n#define PCI_IF_ECP_PARALLEL_PORT 0x02\n#define PCI_IF_1284_CONTROLLER 0x03\n#define PCI_IF_1284_DEVICE 0xFE\n#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\n#define PCI_SUBCLASS_MODEM 0x03\n#define PCI_IF_GENERIC_MODEM 0x00\n#define PCI_IF_16450_MODEM 0x01\n#define PCI_IF_16550_MODEM 0x02\n#define PCI_IF_16650_MODEM 0x03\n#define PCI_IF_16750_MODEM 0x04\n#define PCI_SUBCLASS_SCC_OTHER 0x80\n\n#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\n#define PCI_SUBCLASS_PIC 0x00\n#define PCI_IF_8259_PIC 0x00\n#define PCI_IF_ISA_PIC 0x01\n#define PCI_IF_EISA_PIC 0x02\n#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\n#define PCI_IF_APIC_CONTROLLER2 0x20\n#define PCI_SUBCLASS_DMA 0x01\n#define PCI_IF_8237_DMA 0x00\n#define PCI_IF_ISA_DMA 0x01\n#define PCI_IF_EISA_DMA 0x02\n#define PCI_SUBCLASS_TIMER 0x02\n#define PCI_IF_8254_TIMER 0x00\n#define PCI_IF_ISA_TIMER 0x01\n#define PCI_IF_EISA_TIMER 0x02\n#define PCI_SUBCLASS_RTC 0x03\n#define PCI_IF_GENERIC_RTC 0x00\n#define PCI_IF_ISA_RTC 0x01\n#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\n#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\n\n#define PCI_CLASS_INPUT_DEVICE 0x09\n#define PCI_SUBCLASS_KEYBOARD 0x00\n#define PCI_SUBCLASS_PEN 0x01\n#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\n#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\n#define PCI_SUBCLASS_GAMEPORT 0x04\n#define PCI_IF_GAMEPORT 0x00\n#define PCI_IF_GAMEPORT1 0x10\n#define PCI_SUBCLASS_INPUT_OTHER 0x80\n\n#define PCI_CLASS_DOCKING_STATION 0x0A\n#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\n#define PCI_SUBCLASS_DOCKING_OTHER 0x80\n\n#define PCI_CLASS_PROCESSOR 0x0B\n#define PCI_SUBCLASS_PROC_386 0x00\n#define PCI_SUBCLASS_PROC_486 0x01\n#define PCI_SUBCLASS_PROC_PENTIUM 0x02\n#define PCI_SUBCLASS_PROC_ALPHA 0x10\n#define PCI_SUBCLASS_PROC_POWERPC 0x20\n#define PCI_SUBCLASS_PROC_MIPS 0x30\n#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\n\n#define PCI_CLASS_SERIAL 0x0C\n#define PCI_CLASS_SERIAL_FIREWIRE 0x00\n#define PCI_IF_1394 0x00\n#define PCI_IF_1394_OPEN_HCI 0x10\n#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\n#define PCI_CLASS_SERIAL_SSA 0x02\n#define PCI_CLASS_SERIAL_USB 0x03\n#define PCI_IF_UHCI 0x00\n#define PCI_IF_OHCI 0x10\n#define PCI_IF_USB_OTHER 0x80\n#define PCI_IF_USB_DEVICE 0xFE\n#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\n#define PCI_CLASS_SERIAL_SMB 0x05\n\n#define PCI_CLASS_WIRELESS 0x0D\n#define PCI_SUBCLASS_IRDA 0x00\n#define PCI_SUBCLASS_IR 0x01\n#define PCI_SUBCLASS_RF 0x10\n#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\n\n#define PCI_CLASS_INTELLIGENT_IO 0x0E\n\n#define PCI_CLASS_SATELLITE 0x0F\n#define PCI_SUBCLASS_TV 0x01\n#define PCI_SUBCLASS_AUDIO 0x02\n#define PCI_SUBCLASS_VOICE 0x03\n#define PCI_SUBCLASS_DATA 0x04\n\n#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\n#define PCI_SUBCLASS_NET_COMPUT 0x00\n#define PCI_SUBCLASS_ENTERTAINMENT 0x10\n#define PCI_SUBCLASS_SECURITY_OTHER 0x80\n\n#define PCI_CLASS_DPIO 0x11\n#define PCI_SUBCLASS_DPIO 0x00\n#define PCI_SUBCLASS_DPIO_OTHER 0x80\n\n/**\n Macro that checks whether the Base Class code of device matched.\n\n @param _p Specified device.\n @param c Base Class code needs matching.\n\n @retval TRUE Base Class code matches the specified device.\n @retval FALSE Base Class code doesn't match the specified device.\n\n**/\n#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\n\n/**\n Macro that checks whether the Base Class code and Sub-Class code of device matched.\n\n @param _p Specified device.\n @param c Base Class code needs matching.\n @param s Sub-Class code needs matching.\n\n @retval TRUE Base Class code and Sub-Class code match the specified device.\n @retval FALSE Base Class code and Sub-Class code don't match the specified device.\n\n**/\n#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\n\n/**\n Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\n\n @param _p Specified device.\n @param c Base Class code needs matching.\n @param s Sub-Class code needs matching.\n @param p Interface code needs matching.\n\n @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\n @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\n\n**/\n#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\n\n/**\n Macro that checks whether device is a display controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a display controller.\n @retval FALSE Device is not a display controller.\n\n**/\n#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\n\n/**\n Macro that checks whether device is a VGA-compatible controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a VGA-compatible controller.\n @retval FALSE Device is not a VGA-compatible controller.\n\n**/\n#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\n\n/**\n Macro that checks whether device is an 8514-compatible controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is an 8514-compatible controller.\n @retval FALSE Device is not an 8514-compatible controller.\n\n**/\n#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\n\n/**\n Macro that checks whether device is built before the Class Code field was defined.\n\n @param _p Specified device.\n\n @retval TRUE Device is an old device.\n @retval FALSE Device is not an old device.\n\n**/\n#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\n\n/**\n Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\n\n @param _p Specified device.\n\n @retval TRUE Device is an old VGA-compatible device.\n @retval FALSE Device is not an old VGA-compatible device.\n\n**/\n#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\n\n/**\n Macro that checks whether device is an IDE controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is an IDE controller.\n @retval FALSE Device is not an IDE controller.\n\n**/\n#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\n\n/**\n Macro that checks whether device is a SCSI bus controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a SCSI bus controller.\n @retval FALSE Device is not a SCSI bus controller.\n\n**/\n#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\n\n/**\n Macro that checks whether device is a RAID controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a RAID controller.\n @retval FALSE Device is not a RAID controller.\n\n**/\n#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\n\n/**\n Macro that checks whether device is an ISA bridge.\n\n @param _p Specified device.\n\n @retval TRUE Device is an ISA bridge.\n @retval FALSE Device is not an ISA bridge.\n\n**/\n#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\n\n/**\n Macro that checks whether device is a PCI-to-PCI bridge.\n\n @param _p Specified device.\n\n @retval TRUE Device is a PCI-to-PCI bridge.\n @retval FALSE Device is not a PCI-to-PCI bridge.\n\n**/\n#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\n\n/**\n Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\n\n @param _p Specified device.\n\n @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\n @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\n\n**/\n#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\n\n/**\n Macro that checks whether device is a 16550-compatible serial controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a 16550-compatible serial controller.\n @retval FALSE Device is not a 16550-compatible serial controller.\n\n**/\n#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\n\n/**\n Macro that checks whether device is a Universal Serial Bus controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a Universal Serial Bus controller.\n @retval FALSE Device is not a Universal Serial Bus controller.\n\n**/\n#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\n\n//\n// the definition of Header Type\n//\n#define HEADER_TYPE_DEVICE 0x00\n#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\n#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\n#define HEADER_TYPE_MULTI_FUNCTION 0x80\n//\n// Mask of Header type\n//\n#define HEADER_LAYOUT_CODE 0x7f\n\n/**\n Macro that checks whether device is a PCI-PCI bridge.\n\n @param _p Specified device.\n\n @retval TRUE Device is a PCI-PCI bridge.\n @retval FALSE Device is not a PCI-PCI bridge.\n\n**/\n#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\n\n/**\n Macro that checks whether device is a CardBus bridge.\n\n @param _p Specified device.\n\n @retval TRUE Device is a CardBus bridge.\n @retval FALSE Device is not a CardBus bridge.\n\n**/\n#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\n\n/**\n Macro that checks whether device is a multiple functions device.\n\n @param _p Specified device.\n\n @retval TRUE Device is a multiple functions device.\n @retval FALSE Device is not a multiple functions device.\n\n**/\n#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\n\n///\n/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\n///\n#define PCI_BRIDGE_ROMBAR 0x38\n\n#define PCI_MAX_BAR 0x0006\n#define PCI_MAX_CONFIG_OFFSET 0x0100\n\n#define PCI_VENDOR_ID_OFFSET 0x00\n#define PCI_DEVICE_ID_OFFSET 0x02\n#define PCI_COMMAND_OFFSET 0x04\n#define PCI_PRIMARY_STATUS_OFFSET 0x06\n#define PCI_REVISION_ID_OFFSET 0x08\n#define PCI_CLASSCODE_OFFSET 0x09\n#define PCI_CACHELINE_SIZE_OFFSET 0x0C\n#define PCI_LATENCY_TIMER_OFFSET 0x0D\n#define PCI_HEADER_TYPE_OFFSET 0x0E\n#define PCI_BIST_OFFSET 0x0F\n#define PCI_BASE_ADDRESSREG_OFFSET 0x10\n#define PCI_CARDBUS_CIS_OFFSET 0x28\n#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\n#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\n#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\n#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\n#define PCI_EXPANSION_ROM_BASE 0x30\n#define PCI_CAPBILITY_POINTER_OFFSET 0x34\n#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\n#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\n#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\n#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\n\n//\n// defined in PCI-to-PCI Bridge Architecture Specification\n//\n#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\n#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\n#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\n#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\n#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\n#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\n\n///\n/// Interrupt Line \"Unknown\" or \"No connection\" value defined for x86 based system\n///\n#define PCI_INT_LINE_UNKNOWN 0xFF\n\n///\n/// PCI Access Data Format\n///\ntypedef union {\n struct {\n UINT32 Reg : 8;\n UINT32 Func : 3;\n UINT32 Dev : 5;\n UINT32 Bus : 8;\n UINT32 Reserved : 7;\n UINT32 Enable : 1;\n } Bits;\n UINT32 Uint32;\n} PCI_CONFIG_ACCESS_CF8;\n\n#pragma pack()\n\n#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\n#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\n#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\n#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\n#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\n#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\n#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\n#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\n#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\n#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\n\n//\n// defined in PCI-to-PCI Bridge Architecture Specification\n//\n#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\n#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\n#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\n#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\n#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\n#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\n#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\n#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\n#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\n#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\n#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\n#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\n\n//\n// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\n//\n#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\n#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\n#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\n#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\n\n//\n// Following are the PCI status control bit\n//\n#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\n#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\n#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\n#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\n\n///\n/// defined in PC Card Standard\n///\n#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\n\n#pragma pack(1)\n//\n// PCI Capability List IDs and records\n//\n#define EFI_PCI_CAPABILITY_ID_PMI 0x01\n#define EFI_PCI_CAPABILITY_ID_AGP 0x02\n#define EFI_PCI_CAPABILITY_ID_VPD 0x03\n#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\n#define EFI_PCI_CAPABILITY_ID_MSI 0x05\n#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\n#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\n\n///\n/// Capabilities List Header\n/// Section 6.7, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n UINT8 CapabilityID;\n UINT8 NextItemPtr;\n} EFI_PCI_CAPABILITY_HDR;\n\n///\n/// PMC - Power Management Capabilities\n/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\n///\ntypedef union {\n struct {\n UINT16 Version : 3;\n UINT16 PmeClock : 1;\n UINT16 Reserved : 1;\n UINT16 DeviceSpecificInitialization : 1;\n UINT16 AuxCurrent : 3;\n UINT16 D1Support : 1;\n UINT16 D2Support : 1;\n UINT16 PmeSupport : 5;\n } Bits;\n UINT16 Data;\n} EFI_PCI_PMC;\n\n#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\n\n///\n/// PMCSR - Power Management Control/Status\n/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\n///\ntypedef union {\n struct {\n UINT16 PowerState : 2;\n UINT16 ReservedForPciExpress : 1;\n UINT16 NoSoftReset : 1;\n UINT16 Reserved : 4;\n UINT16 PmeEnable : 1;\n UINT16 DataSelect : 4;\n UINT16 DataScale : 2;\n UINT16 PmeStatus : 1;\n } Bits;\n UINT16 Data;\n} EFI_PCI_PMCSR;\n\n#define PCI_POWER_STATE_D0 0\n#define PCI_POWER_STATE_D1 1\n#define PCI_POWER_STATE_D2 2\n#define PCI_POWER_STATE_D3_HOT 3\n\n///\n/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\n/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\n///\ntypedef union {\n struct {\n UINT8 Reserved : 6;\n UINT8 B2B3 : 1;\n UINT8 BusPowerClockControl : 1;\n } Bits;\n UINT8 Uint8;\n} EFI_PCI_PMCSR_BSE;\n\n///\n/// Power Management Register Block Definition\n/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n EFI_PCI_PMC PMC;\n EFI_PCI_PMCSR PMCSR;\n EFI_PCI_PMCSR_BSE BridgeExtention;\n UINT8 Data;\n} EFI_PCI_CAPABILITY_PMI;\n\n///\n/// A.G.P Capability\n/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT8 Rev;\n UINT8 Reserved;\n UINT32 Status;\n UINT32 Command;\n} EFI_PCI_CAPABILITY_AGP;\n\n///\n/// VPD Capability Structure\n/// Appendix I, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT16 AddrReg;\n UINT32 DataReg;\n} EFI_PCI_CAPABILITY_VPD;\n\n///\n/// Slot Numbering Capabilities Register\n/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT8 ExpnsSlotReg;\n UINT8 ChassisNo;\n} EFI_PCI_CAPABILITY_SLOTID;\n\n///\n/// Message Capability Structure for 32-bit Message Address\n/// Section 6.8.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT16 MsgCtrlReg;\n UINT32 MsgAddrReg;\n UINT16 MsgDataReg;\n} EFI_PCI_CAPABILITY_MSI32;\n\n///\n/// Message Capability Structure for 64-bit Message Address\n/// Section 6.8.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT16 MsgCtrlReg;\n UINT32 MsgAddrRegLsdw;\n UINT32 MsgAddrRegMsdw;\n UINT16 MsgDataReg;\n} EFI_PCI_CAPABILITY_MSI64;\n\n///\n/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,\n/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n ///\n /// not finished - fields need to go here\n ///\n} EFI_PCI_CAPABILITY_HOTPLUG;\n\n#define PCI_BAR_IDX0 0x00\n#define PCI_BAR_IDX1 0x01\n#define PCI_BAR_IDX2 0x02\n#define PCI_BAR_IDX3 0x03\n#define PCI_BAR_IDX4 0x04\n#define PCI_BAR_IDX5 0x05\n\n///\n/// EFI PCI Option ROM definitions\n///\n#define EFI_ROOT_BRIDGE_LIST 'eprb'\n#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\n\n#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\n#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\n#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\n#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\n\n///\n/// Standard PCI Expansion ROM Header\n/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\n///\ntypedef struct {\n UINT16 Signature; ///< 0xaa55\n UINT8 Reserved[0x16];\n UINT16 PcirOffset;\n} PCI_EXPANSION_ROM_HEADER;\n\n///\n/// Legacy ROM Header Extensions\n/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n UINT16 Signature; ///< 0xaa55\n UINT8 Size512;\n UINT8 InitEntryPoint[3];\n UINT8 Reserved[0x12];\n UINT16 PcirOffset;\n} EFI_LEGACY_EXPANSION_ROM_HEADER;\n\n///\n/// PCI Data Structure Format\n/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\n///\ntypedef struct {\n UINT32 Signature; ///< \"PCIR\"\n UINT16 VendorId;\n UINT16 DeviceId;\n UINT16 Reserved0;\n UINT16 Length;\n UINT8 Revision;\n UINT8 ClassCode[3];\n UINT16 ImageLength;\n UINT16 CodeRevision;\n UINT8 CodeType;\n UINT8 Indicator;\n UINT16 Reserved1;\n} PCI_DATA_STRUCTURE;\n\n///\n/// EFI PCI Expansion ROM Header\n/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\n///\ntypedef struct {\n UINT16 Signature; ///< 0xaa55\n UINT16 InitializationSize;\n UINT32 EfiSignature; ///< 0x0EF1\n UINT16 EfiSubsystem;\n UINT16 EfiMachineType;\n UINT16 CompressionType;\n UINT8 Reserved[8];\n UINT16 EfiImageHeaderOffset;\n UINT16 PcirOffset;\n} EFI_PCI_EXPANSION_ROM_HEADER;\n\ntypedef union {\n UINT8 *Raw;\n PCI_EXPANSION_ROM_HEADER *Generic;\n EFI_PCI_EXPANSION_ROM_HEADER *Efi;\n EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\n} EFI_PCI_ROM_HEADER;\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/Pci23.h", "content": "/** @file\n Support for PCI 2.3 standard.\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCI23_H_\n#define _PCI23_H_\n\n#include \"Pci22.h\"\n\n///\n/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\n///\n///@{\n#define PCI_CLASS_MASS_STORAGE_ATA 0x05\n#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\n#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\n///@}\n\n///\n/// PCI_CLASS_NETWORK, Base Class 02h.\n///\n///@{\n#define PCI_CLASS_NETWORK_WORLDFIP 0x05\n#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\n///@}\n\n///\n/// PCI_CLASS_BRIDGE, Base Class 06h.\n///\n///@{\n#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\n#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\n#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\n#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\n///@}\n\n///\n/// PCI_CLASS_SCC, Base Class 07h.\n///\n///@{\n#define PCI_SUBCLASS_GPIB 0x04\n#define PCI_SUBCLASS_SMART_CARD 0x05\n///@}\n\n///\n/// PCI_CLASS_SERIAL, Base Class 0Ch.\n///\n///@{\n#define PCI_IF_EHCI 0x20\n#define PCI_CLASS_SERIAL_IB 0x06\n#define PCI_CLASS_SERIAL_IPMI 0x07\n#define PCI_IF_IPMI_SMIC 0x00\n#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\n#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\n#define PCI_CLASS_SERIAL_SERCOS 0x08\n#define PCI_CLASS_SERIAL_CANBUS 0x09\n///@}\n\n///\n/// PCI_CLASS_WIRELESS, Base Class 0Dh.\n///\n///@{\n#define PCI_SUBCLASS_BLUETOOTH 0x11\n#define PCI_SUBCLASS_BROADBAND 0x12\n///@}\n\n///\n/// PCI_CLASS_DPIO, Base Class 11h.\n///\n///@{\n#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01\n#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10\n#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20\n///@}\n\n///\n/// defined in PCI Express Spec.\n///\n#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\n\n///\n/// PCI Capability List IDs and records.\n///\n#define EFI_PCI_CAPABILITY_ID_PCIX 0x07\n#define EFI_PCI_CAPABILITY_ID_VENDOR 0x09\n\n#pragma pack(1)\n///\n/// PCI-X Capabilities List,\n/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT16 CommandReg;\n UINT32 StatusReg;\n} EFI_PCI_CAPABILITY_PCIX;\n\n///\n/// PCI-X Bridge Capabilities List,\n/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT16 SecStatusReg;\n UINT32 StatusReg;\n UINT32 SplitTransCtrlRegUp;\n UINT32 SplitTransCtrlRegDn;\n} EFI_PCI_CAPABILITY_PCIX_BRDG;\n\n///\n/// Vendor Specific Capability Header\n/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3\n///\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n UINT8 Length;\n} EFI_PCI_CAPABILITY_VENDOR_HDR;\n\n#pragma pack()\n\n#define PCI_CODE_TYPE_EFI_IMAGE 0x03\n\n#endif\n" }, { "path": "src/edk2/Pci30.h", "content": "/** @file\n Support for PCI 3.0 standard.\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef __PCI30_H__\n#define __PCI30_H__\n\n#include \"Pci23.h\"\n\n///\n/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\n///\n///@{\n#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\n#define PCI_IF_MASS_STORAGE_SATA 0x00\n#define PCI_IF_MASS_STORAGE_AHCI 0x01\n///@}\n\n///\n/// PCI_CLASS_WIRELESS, Base Class 0Dh.\n///\n///@{\n#define PCI_SUBCLASS_ETHERNET_80211A 0x20\n#define PCI_SUBCLASS_ETHERNET_80211B 0x21\n///@}\n\n/**\n Macro that checks whether device is a SATA controller.\n\n @param _p Specified device.\n\n @retval TRUE Device is a SATA controller.\n @retval FALSE Device is not a SATA controller.\n\n**/\n#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\n\n///\n/// PCI Capability List IDs and records\n///\n#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\n\n#pragma pack(1)\n\n///\n/// PCI Data Structure Format\n/// Section 5.1.2, PCI Firmware Specification, Revision 3.0\n///\ntypedef struct {\n UINT32 Signature; ///< \"PCIR\"\n UINT16 VendorId;\n UINT16 DeviceId;\n UINT16 DeviceListOffset;\n UINT16 Length;\n UINT8 Revision;\n UINT8 ClassCode[3];\n UINT16 ImageLength;\n UINT16 CodeRevision;\n UINT8 CodeType;\n UINT8 Indicator;\n UINT16 MaxRuntimeImageLength;\n UINT16 ConfigUtilityCodeHeaderOffset;\n UINT16 DMTFCLPEntryPointOffset;\n} PCI_3_0_DATA_STRUCTURE;\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciCodeId.h", "content": "/** @file\n The file lists the PCI class codes only defined in PCI code and ID assignment specification\n revision 1.3.\n\n Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef __PCI_CODE_ID_H__\n#define __PCI_CODE_ID_H__\n\n///\n/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\n///\n///@{\n#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00\n#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11\n#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12\n#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13\n#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21\n#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02\n#define PCI_CLASS_MASS_STORAGE_SAS 0x07\n#define PCI_IF_MASS_STORAGE_SAS 0x00\n#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01\n#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08\n#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00\n#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01\n#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02\n///@}\n\n///\n/// PCI_CLASS_NETWORK, Base Class 02h.\n///\n///@{\n#define PCI_CLASS_NETWORK_INFINIBAND 0x07\n///@}\n\n///\n/// PCI_CLASS_MEDIA, Base Class 04h.\n///\n///@{\n#define PCI_CLASS_MEDIA_MIXED_MODE 0x03\n///@}\n\n///\n/// PCI_CLASS_BRIDGE, Base Class 06h.\n///\n///@{\n#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B\n#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00\n#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01\n///@}\n\n///\n/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.\n///\n///@{\n#define PCI_IF_HPET 0x03\n#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\n#define PCI_SUBCLASS_IOMMU 0x06\n///@}\n\n///\n/// PCI_CLASS_PROCESSOR, Base Class 0Bh.\n///\n///@{\n#define PCI_SUBCLASS_PROC_OTHER 0x80\n///@}\n\n///\n/// PCI_CLASS_SERIAL, Base Class 0Ch.\n///\n///@{\n#define PCI_IF_XHCI 0x30\n#define PCI_CLASS_SERIAL_OTHER 0x80\n///@}\n\n///\n/// PCI_CLASS_SATELLITE, Base Class 0Fh.\n///\n///@{\n#define PCI_SUBCLASS_SATELLITE_OTHER 0x80\n///@}\n\n///\n/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.\n///\n///@{\n#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12\n///@}\n\n#endif\n" }, { "path": "src/edk2/PciExpress21.h", "content": "/** @file\n Support for the latest PCI standard.\n\n Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
\n (C) Copyright 2016 Hewlett Packard Enterprise Development LP
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCIEXPRESS21_H_\n#define _PCIEXPRESS21_H_\n\n#include \"Pci30.h\"\n\n/**\n Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\n ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits\n of Bus, Device, Function and Register are stripped prior to the generation of\n the address.\n\n @param Bus PCI Bus number. Range 0..255.\n @param Device PCI Device number. Range 0..31.\n @param Function PCI Function number. Range 0..7.\n @param Register PCI Register number. Range 0..4095.\n\n @return The encode ECAM address.\n\n**/\n#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \\\n (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\n\n#pragma pack(1)\n///\n/// PCI Express Capability Structure\n///\ntypedef union {\n struct {\n UINT16 Version : 4;\n UINT16 DevicePortType : 4;\n UINT16 SlotImplemented : 1;\n UINT16 InterruptMessageNumber : 5;\n UINT16 Undefined : 1;\n UINT16 FlitModeSupported : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_CAPABILITY;\n\n#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\n#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\n#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\n#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\n#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\n#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\n#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\n#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\n#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\n\ntypedef union {\n struct {\n UINT32 MaxPayloadSize : 3;\n UINT32 PhantomFunctions : 2;\n UINT32 ExtendedTagField : 1;\n UINT32 EndpointL0sAcceptableLatency : 3;\n UINT32 EndpointL1AcceptableLatency : 3;\n UINT32 Undefined : 3;\n UINT32 RoleBasedErrorReporting : 1;\n UINT32 ErrCorSubclassCapable : 1;\n UINT32 RxMpsFixed : 1;\n UINT32 CapturedSlotPowerLimitValue : 8;\n UINT32 CapturedSlotPowerLimitScale : 2;\n UINT32 FunctionLevelReset : 1;\n UINT32 MixedMpsSupported : 1;\n UINT32 Reserved2 : 2;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_DEVICE_CAPABILITY;\n\ntypedef union {\n struct {\n UINT16 CorrectableError : 1;\n UINT16 NonFatalError : 1;\n UINT16 FatalError : 1;\n UINT16 UnsupportedRequest : 1;\n UINT16 RelaxedOrdering : 1;\n UINT16 MaxPayloadSize : 3;\n UINT16 ExtendedTagField : 1;\n UINT16 PhantomFunctions : 1;\n UINT16 AuxPower : 1;\n UINT16 NoSnoop : 1;\n UINT16 MaxReadRequestSize : 3;\n UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_DEVICE_CONTROL;\n\n#define PCIE_MAX_PAYLOAD_SIZE_128B 0\n#define PCIE_MAX_PAYLOAD_SIZE_256B 1\n#define PCIE_MAX_PAYLOAD_SIZE_512B 2\n#define PCIE_MAX_PAYLOAD_SIZE_1024B 3\n#define PCIE_MAX_PAYLOAD_SIZE_2048B 4\n#define PCIE_MAX_PAYLOAD_SIZE_4096B 5\n#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6\n#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7\n\n#define PCIE_MAX_READ_REQ_SIZE_128B 0\n#define PCIE_MAX_READ_REQ_SIZE_256B 1\n#define PCIE_MAX_READ_REQ_SIZE_512B 2\n#define PCIE_MAX_READ_REQ_SIZE_1024B 3\n#define PCIE_MAX_READ_REQ_SIZE_2048B 4\n#define PCIE_MAX_READ_REQ_SIZE_4096B 5\n#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\n#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\n\ntypedef union {\n struct {\n UINT16 CorrectableError : 1;\n UINT16 NonFatalError : 1;\n UINT16 FatalError : 1;\n UINT16 UnsupportedRequest : 1;\n UINT16 AuxPower : 1;\n UINT16 TransactionsPending : 1;\n UINT16 EmergencyPowerReductionDetected : 1;\n UINT16 Reserved : 9;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_DEVICE_STATUS;\n\ntypedef union {\n struct {\n UINT32 MaxLinkSpeed : 4;\n UINT32 MaxLinkWidth : 6;\n UINT32 Aspm : 2;\n UINT32 L0sExitLatency : 3;\n UINT32 L1ExitLatency : 3;\n UINT32 ClockPowerManagement : 1;\n UINT32 SurpriseDownError : 1;\n UINT32 DataLinkLayerLinkActive : 1;\n UINT32 LinkBandwidthNotification : 1;\n UINT32 AspmOptionalityCompliance : 1;\n UINT32 Reserved : 1;\n UINT32 PortNumber : 8;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_LINK_CAPABILITY;\n\n#define PCIE_LINK_ASPM_L0S BIT0\n#define PCIE_LINK_ASPM_L1 BIT1\n\ntypedef union {\n struct {\n UINT16 AspmControl : 2;\n UINT16 PtmPropagationDelayB : 1;\n UINT16 ReadCompletionBoundary : 1;\n UINT16 LinkDisable : 1;\n UINT16 RetrainLink : 1;\n UINT16 CommonClockConfiguration : 1;\n UINT16 ExtendedSynch : 1;\n UINT16 ClockPowerManagement : 1;\n UINT16 HardwareAutonomousWidthDisable : 1;\n UINT16 LinkBandwidthManagementInterrupt : 1;\n UINT16 LinkAutonomousBandwidthInterrupt : 1;\n UINT16 SrisClocking : 1;\n UINT16 FlitModeDisable : 1;\n UINT16 DrsSignalingControl : 2;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_LINK_CONTROL;\n\ntypedef union {\n struct {\n UINT16 CurrentLinkSpeed : 4;\n UINT16 NegotiatedLinkWidth : 6;\n UINT16 Undefined : 1;\n UINT16 LinkTraining : 1;\n UINT16 SlotClockConfiguration : 1;\n UINT16 DataLinkLayerLinkActive : 1;\n UINT16 LinkBandwidthManagement : 1;\n UINT16 LinkAutonomousBandwidth : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_LINK_STATUS;\n\ntypedef union {\n struct {\n UINT32 AttentionButton : 1;\n UINT32 PowerController : 1;\n UINT32 MrlSensor : 1;\n UINT32 AttentionIndicator : 1;\n UINT32 PowerIndicator : 1;\n UINT32 HotPlugSurprise : 1;\n UINT32 HotPlugCapable : 1;\n UINT32 SlotPowerLimitValue : 8;\n UINT32 SlotPowerLimitScale : 2;\n UINT32 ElectromechanicalInterlock : 1;\n UINT32 NoCommandCompleted : 1;\n UINT32 PhysicalSlotNumber : 13;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_SLOT_CAPABILITY;\n\ntypedef union {\n struct {\n UINT16 AttentionButtonPressed : 1;\n UINT16 PowerFaultDetected : 1;\n UINT16 MrlSensorChanged : 1;\n UINT16 PresenceDetectChanged : 1;\n UINT16 CommandCompletedInterrupt : 1;\n UINT16 HotPlugInterrupt : 1;\n UINT16 AttentionIndicator : 2;\n UINT16 PowerIndicator : 2;\n UINT16 PowerController : 1;\n UINT16 ElectromechanicalInterlock : 1;\n UINT16 DataLinkLayerStateChanged : 1;\n UINT16 AutoSlotPowerLimitDisable : 1;\n UINT16 InbandPdDisable : 1;\n UINT16 Reserved : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_SLOT_CONTROL;\n\ntypedef union {\n struct {\n UINT16 AttentionButtonPressed : 1;\n UINT16 PowerFaultDetected : 1;\n UINT16 MrlSensorChanged : 1;\n UINT16 PresenceDetectChanged : 1;\n UINT16 CommandCompleted : 1;\n UINT16 MrlSensor : 1;\n UINT16 PresenceDetect : 1;\n UINT16 ElectromechanicalInterlock : 1;\n UINT16 DataLinkLayerStateChanged : 1;\n UINT16 Reserved : 7;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_SLOT_STATUS;\n\ntypedef union {\n struct {\n UINT16 SystemErrorOnCorrectableError : 1;\n UINT16 SystemErrorOnNonFatalError : 1;\n UINT16 SystemErrorOnFatalError : 1;\n UINT16 PmeInterrupt : 1;\n UINT16 CrsSoftwareVisibility : 1;\n UINT16 NoNfmSubtree : 1;\n UINT16 Reserved : 10;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_ROOT_CONTROL;\n\ntypedef union {\n struct {\n UINT16 CrsSoftwareVisibility : 1;\n UINT16 Reserved : 15;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_ROOT_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 PmeRequesterId : 16;\n UINT32 PmeStatus : 1;\n UINT32 PmePending : 1;\n UINT32 Reserved : 14;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_ROOT_STATUS;\n\ntypedef union {\n struct {\n UINT32 CompletionTimeoutRanges : 4;\n UINT32 CompletionTimeoutDisable : 1;\n UINT32 AriForwarding : 1;\n UINT32 AtomicOpRouting : 1;\n UINT32 AtomicOp32Completer : 1;\n UINT32 AtomicOp64Completer : 1;\n UINT32 Cas128Completer : 1;\n UINT32 NoRoEnabledPrPrPassing : 1;\n UINT32 LtrMechanism : 1;\n UINT32 TphCompleter : 2;\n UINT32 Reserved : 2;\n UINT32 TenBitTagCompleterSupported : 1;\n UINT32 TenBitTagRequesterSupported : 1;\n UINT32 Obff : 2;\n UINT32 ExtendedFmtField : 1;\n UINT32 EndEndTlpPrefix : 1;\n UINT32 MaxEndEndTlpPrefixes : 2;\n UINT32 EmergencyPowerReductionSupported : 2;\n UINT32 EmergencyPowerReductionInitializationRequired : 1;\n UINT32 Reserved2 : 1;\n UINT32 DmwrCompleter : 1;\n UINT32 DmwrLengths : 2;\n UINT32 FrsSupported : 1;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_DEVICE_CAPABILITY2;\n\n#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\n#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\n#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\n#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\n#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\n#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\n#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\n#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\n\n#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\n#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\n\ntypedef union {\n struct {\n UINT16 CompletionTimeoutValue : 4;\n UINT16 CompletionTimeoutDisable : 1;\n UINT16 AriForwarding : 1;\n UINT16 AtomicOpRequester : 1;\n UINT16 AtomicOpEgressBlocking : 1;\n UINT16 IdoRequest : 1;\n UINT16 IdoCompletion : 1;\n UINT16 LtrMechanism : 1;\n UINT16 EmergencyPowerReductionRequest : 1;\n UINT16 TenBitTagRequesterEnable : 1;\n UINT16 Obff : 2;\n UINT16 EndEndTlpPrefixBlocking : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_DEVICE_CONTROL2;\n\n#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\n#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\n#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\n#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\n#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\n#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\n#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\n#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\n#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\n\n#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\n#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\n#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\n#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\n\ntypedef union {\n struct {\n UINT32 Reserved : 1;\n UINT32 LinkSpeedsVector : 7;\n UINT32 Crosslink : 1;\n UINT32 LowerSkpOsGeneration : 7;\n UINT32 LowerSkpOsReception : 7;\n UINT32 RetimerPresenceDetect : 1;\n UINT32 TwoRetimersPresenceDetect : 1;\n UINT32 Reserved2 : 6;\n UINT32 DrsSupported : 1;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_LINK_CAPABILITY2;\n\ntypedef union {\n struct {\n UINT16 TargetLinkSpeed : 4;\n UINT16 EnterCompliance : 1;\n UINT16 HardwareAutonomousSpeedDisable : 1;\n UINT16 SelectableDeemphasis : 1;\n UINT16 TransmitMargin : 3;\n UINT16 EnterModifiedCompliance : 1;\n UINT16 ComplianceSos : 1;\n UINT16 CompliancePresetDeemphasis : 4;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_LINK_CONTROL2;\n\ntypedef union {\n struct {\n UINT16 CurrentDeemphasisLevel : 1;\n UINT16 EqualizationComplete : 1;\n UINT16 EqualizationPhase1Successful : 1;\n UINT16 EqualizationPhase2Successful : 1;\n UINT16 EqualizationPhase3Successful : 1;\n UINT16 LinkEqualizationRequest : 1;\n UINT16 RetimerPresence : 1;\n UINT16 TwoRetimersPresence : 1;\n UINT16 CrosslinkResolution : 2;\n UINT16 FlitModeStatus : 1;\n UINT16 Reserved : 1;\n UINT16 DownstreamComponentPresence : 3;\n UINT16 DRSMessageReceived : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_REG_PCIE_LINK_STATUS2;\n\ntypedef union {\n struct {\n UINT32 InbandPdDisable : 1;\n UINT32 Reserved : 30;\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_SLOT_CAPABILITY2;\n\ntypedef struct {\n EFI_PCI_CAPABILITY_HDR Hdr;\n PCI_REG_PCIE_CAPABILITY Capability;\n PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\n PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\n PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\n PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\n PCI_REG_PCIE_LINK_CONTROL LinkControl;\n PCI_REG_PCIE_LINK_STATUS LinkStatus;\n PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\n PCI_REG_PCIE_SLOT_CONTROL SlotControl;\n PCI_REG_PCIE_SLOT_STATUS SlotStatus;\n PCI_REG_PCIE_ROOT_CONTROL RootControl;\n PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\n PCI_REG_PCIE_ROOT_STATUS RootStatus;\n PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\n PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\n UINT16 DeviceStatus2;\n PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\n PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\n PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\n PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;\n UINT16 SlotControl2;\n UINT16 SlotStatus2;\n} PCI_CAPABILITY_PCIEXP;\n\n#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\n#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\n#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\n#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\n#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\n\n//\n// for SR-IOV\n//\n#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\n#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\n#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\n#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_ID 0x0010\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SRIOV_VER1 0x1\n\ntypedef struct {\n UINT32 CapabilityHeader;\n UINT32 Capability;\n UINT16 Control;\n UINT16 Status;\n UINT16 InitialVFs;\n UINT16 TotalVFs;\n UINT16 NumVFs;\n UINT8 FunctionDependencyLink;\n UINT8 Reserved0;\n UINT16 FirstVFOffset;\n UINT16 VFStride;\n UINT16 Reserved1;\n UINT16 VFDeviceID;\n UINT32 SupportedPageSize;\n UINT32 SystemPageSize;\n UINT32 VFBar[6];\n UINT32 VFMigrationStateArrayOffset;\n} SR_IOV_CAPABILITY_REGISTER;\n\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\n#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\n\ntypedef struct {\n UINT32 CapabilityId : 16;\n UINT32 CapabilityVersion : 4;\n UINT32 NextCapabilityOffset : 12;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\n\n#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\n\ntypedef union {\n struct {\n UINT32 Undefined : 1;\n UINT32 Reserved : 3;\n UINT32 DataLinkProtocolError : 1;\n UINT32 SurpriseDownError : 1;\n UINT32 Reserved2 : 6;\n UINT32 PoisonedTlp : 1;\n UINT32 FlowControlProtocolError : 1;\n UINT32 CompletionTimeout : 1;\n UINT32 CompleterAbort : 1;\n UINT32 UnexpectedCompletion : 1;\n UINT32 ReceiverOverflow : 1;\n UINT32 MalformedTlp : 1;\n UINT32 EcrcError : 1;\n UINT32 UnsupportedRequestError : 1;\n UINT32 AcsVoilation : 1;\n UINT32 UncorrectableInternalError : 1;\n UINT32 McBlockedTlp : 1;\n UINT32 AtomicOpEgressBlocked : 1;\n UINT32 TlpPrefixBlockedError : 1;\n UINT32 Reserved3 : 6;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\n PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\n PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\n UINT32 CorrectableErrorStatus;\n UINT32 CorrectableErrorMask;\n UINT32 AdvancedErrorCapabilitiesAndControl;\n UINT32 HeaderLog[4];\n UINT32 RootErrorCommand;\n UINT32 RootErrorStatus;\n UINT16 ErrorSourceIdentification;\n UINT16 CorrectableErrorSourceIdentification;\n UINT32 TlpPrefixLog[4];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\n\ntypedef struct {\n UINT32 VcResourceCapability : 24;\n UINT32 PortArbTableOffset : 8;\n UINT32 VcResourceControl;\n UINT16 Reserved1;\n UINT16 VcResourceStatus;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 ExtendedVcCount : 3;\n UINT32 PortVcCapability1 : 29;\n UINT32 PortVcCapability2 : 24;\n UINT32 VcArbTableOffset : 8;\n UINT16 PortVcControl;\n UINT16 PortVcStatus;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT64 SerialNumber;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 ElementSelfDescription;\n UINT32 Reserved;\n UINT32 LinkEntry[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 RootComplexLinkCapabilities;\n UINT16 RootComplexLinkControl;\n UINT16 RootComplexLinkStatus;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 DataSelect : 8;\n UINT32 Reserved : 24;\n UINT32 Data;\n UINT32 PowerBudgetCapability : 1;\n UINT32 Reserved2 : 7;\n UINT32 Reserved3 : 24;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT16 AcsCapability;\n UINT16 AcsControl;\n UINT8 EgressControlVectorArray[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 AssociationBitmap;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\n\ntypedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 VendorSpecificHeader;\n UINT8 VendorSpecific[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT16 VendorId;\n UINT16 DeviceId;\n UINT32 RcrbCapabilities;\n UINT32 RcrbControl;\n UINT32 Reserved;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT16 MultiCastCapability;\n UINT16 MulticastControl;\n UINT64 McBaseAddress;\n UINT64 McReceiveAddress;\n UINT64 McBlockAll;\n UINT64 McBlockUntranslated;\n UINT64 McOverlayBar;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 Reserved : 4;\n UINT32 BarSizeCapability : 28;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 BarIndex : 3;\n UINT32 Reserved : 2;\n UINT32 ResizableBarNumber : 3;\n UINT32 BarSize : 6;\n UINT32 Reserved2 : 2;\n UINT32 BarSizeCapability : 16;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\n\n#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT16 AriCapability;\n UINT16 AriControl;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 DpaCapability;\n UINT32 DpaLatencyIndicator;\n UINT16 DpaStatus;\n UINT16 DpaControl;\n UINT8 DpaPowerAllocationArray[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT32)(((POWER->DpaCapability)&0x0000000F))\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT16 MaxSnoopLatency;\n UINT16 MaxNoSnoopLatency;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 TphRequesterCapability;\n UINT32 TphRequesterControl;\n UINT16 TphStTable[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\n\n#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\n\n/// Address Translation Services Extended Capability Structure\n///\n/// Based on section 5.1 of PCI Express Address Translation Services Specification 1.1\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_ID 0x000F\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ATS_VER1 0x1\n\ntypedef union {\n struct {\n UINT16 InvalidateQueueDepth : 5;\n UINT16 Reserved : 9;\n UINT16 GlobalInvalidateSupported : 1;\n UINT16 Reserved2 : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY;\n\ntypedef union {\n struct {\n UINT16 EnableATS : 1;\n UINT16 GlobalInvalidate : 1;\n UINT16 Reserved : 14;\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY Capability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL Control;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciExpress30.h", "content": "/** @file\n Support for the PCI Express 3.0 standard.\n\n This header file may not define all structures. Please extend as required.\n\n Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
\n SPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCIEXPRESS30_H_\n#define _PCIEXPRESS30_H_\n\n#include \"PciExpress21.h\"\n\n#pragma pack(1)\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 PerformEqualization : 1;\n UINT32 LinkEqualizationRequestInterruptEnable : 1;\n UINT32 Reserved : 30;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_LINK_CONTROL3;\n\ntypedef union {\n struct {\n UINT16 DownstreamPortTransmitterPreset : 4;\n UINT16 DownstreamPortReceiverPresetHint : 3;\n UINT16 Reserved : 1;\n UINT16 UpstreamPortTransmitterPreset : 4;\n UINT16 UpstreamPortReceiverPresetHint : 3;\n UINT16 Reserved2 : 1;\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\n UINT32 LaneErrorStatus;\n PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;\n\n/// VF Resizable BAR Extended Capability Structure\n///\n/// Based on section 7.22 of PCI Express Base Specification 3.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VF_RESIZABLE_BAR_ID 0x0024\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_VF_RESIZABLE_BAR_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 Reserved : 4;\n UINT32 VfBarSizeCapability : 28;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 VfBarIndex : 3;\n UINT32 Reserved : 2;\n UINT32 VfResizableBarNumber : 3;\n UINT32 VfBarSize : 6;\n UINT32 Reserved2 : 2;\n UINT32 VfBarSizeCapability : 16;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CAPABILITY VfResizableBarCapability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CONTROL VfResizableBarControl;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_ENTRY;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_ENTRY Capability[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciExpress31.h", "content": "/** @file\nSupport for the PCI Express 3.1 standard.\n\nThis header file may not define all structures. Please extend as required.\n\nCopyright (c) 2016, Intel Corporation. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCIEXPRESS31_H_\n#define _PCIEXPRESS31_H_\n\n#include \"PciExpress30.h\"\n\n#pragma pack(1)\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 PciPmL12 : 1;\n UINT32 PciPmL11 : 1;\n UINT32 AspmL12 : 1;\n UINT32 AspmL11 : 1;\n UINT32 L1PmSubstates : 1;\n UINT32 Reserved : 3;\n UINT32 CommonModeRestoreTime : 8;\n UINT32 TPowerOnScale : 2;\n UINT32 Reserved2 : 1;\n UINT32 TPowerOnValue : 5;\n UINT32 Reserved3 : 8;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 PciPmL12 : 1;\n UINT32 PciPmL11 : 1;\n UINT32 AspmL12 : 1;\n UINT32 AspmL11 : 1;\n UINT32 Reserved : 4;\n UINT32 CommonModeRestoreTime : 8;\n UINT32 LtrL12ThresholdValue : 10;\n UINT32 Reserved2 : 3;\n UINT32 LtrL12ThresholdScale : 3;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;\n\ntypedef union {\n struct {\n UINT32 TPowerOnScale : 2;\n UINT32 Reserved : 1;\n UINT32 TPowerOnValue : 5;\n UINT32 Reserved2 : 24;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\n PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\n PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;\n\n/// Process Address Space ID Extended Capability Structure\n///\n/// Based on section 7.29 of PCI Express Base Specification 3.1\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_ID 0x001B\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PASID_VER1 0x1\n\ntypedef union {\n struct {\n UINT16 PasidSupport : 1;\n UINT16 ExecutePermissionSupport : 1;\n UINT16 PrivilegedModeSupport : 1;\n UINT16 Reserved1 : 5;\n UINT16 MaxPasidWidth : 5;\n UINT16 Reserved2 : 3;\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY;\n\ntypedef union {\n struct {\n UINT16 PasidEnable : 1;\n UINT16 ExecutePermissionEnable : 1;\n UINT16 PrivilegedModeEnable : 1;\n UINT16 Reserved : 13;\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY Capability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL Control;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciExpress40.h", "content": "/** @file\nSupport for the PCI Express 4.0 standard.\n\nThis header file may not define all structures. Please extend as required.\n\nCopyright (c) 2018, American Megatrends, Inc. All rights reserved.
\nCopyright (c) 2020, Intel Corporation. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCIEXPRESS40_H_\n#define _PCIEXPRESS40_H_\n\n#include \"PciExpress31.h\"\n\n#pragma pack(1)\n\n/// The Physical Layer PCI Express Extended Capability definitions.\n///\n/// Based on section 7.7.5 of PCI Express Base Specification 4.0.\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1\n\n// Register offsets from Physical Layer PCI-E Ext Cap Header\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\n\ntypedef union {\n struct {\n UINT32 Reserved : 32; // Reserved bit 0:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\n\ntypedef union {\n struct {\n UINT32 Reserved : 32; // Reserved bit 0:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\n\ntypedef union {\n struct {\n UINT32 EqualizationComplete : 1; // bit 0\n UINT32 EqualizationPhase1Success : 1; // bit 1\n UINT32 EqualizationPhase2Success : 1; // bit 2\n UINT32 EqualizationPhase3Success : 1; // bit 3\n UINT32 LinkEqualizationRequest : 1; // bit 4\n UINT32 Reserved : 27; // Reserved bit 5:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\n\ntypedef union {\n struct {\n UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\n UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\n UINT32 LocalDataParityMismatchStatus;\n UINT32 FirstRetimerDataParityMismatchStatus;\n UINT32 SecondRetimerDataParityMismatchStatus;\n UINT32 Reserved;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\n///@}\n\n/// The Designated Vendor Specific Capability definitions\n///\n/// Based on section 7.9.6 of PCI Express Base Specification 4.0.\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID 0x0023\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 DvsecVendorId : 16; // bit 0..15\n UINT32 DvsecRevision : 4; // bit 16..19\n UINT32 DvsecLength : 12; // bit 20..31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\n\ntypedef union {\n struct {\n UINT16 DvsecId : 16; // bit 0..15\n } Bits;\n UINT16 Uint16;\n} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;\n PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;\n UINT8 DesignatedVendorSpecific[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\n///@}\n\n/// Data Link Feature Extended Capability Structure\n///\n/// Based on section 7.7.4 of PCI Express Base Specification 4.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DATA_LINK_FEATURE_ID 0x0025\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DATA_LINK_FEATURE_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 Reserved1 : 1;\n UINT32 ScrambleDisableSupported : 1;\n UINT32 Reserved2 : 30;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 Reserved1 : 1;\n UINT32 ScrambleDisable : 1;\n UINT32 Reserved2 : 30;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CAPABILITY Capability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CONTROL Control;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE;\n///@}\n\n/// Lane Margining at Receiver Extended Capability Structure\n///\n/// Based on section 7.7.6 of PCI Express Base Specification 4.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LANE_MARGINING_AT_RECEIVER_ID 0x0027\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_LANE_MARGINING_AT_RECEIVER_VER1 0x1\n\ntypedef union {\n struct {\n UINT8 MaxLaneNumber : 5;\n UINT8 Reserved : 3;\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CAPABILITY;\n\ntypedef union {\n struct {\n UINT8 LaneNumber : 5;\n UINT8 RcvErrorCounterSelect : 2;\n UINT8 LaneMarginStepSelect : 1;\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CONTROL;\n\ntypedef union {\n struct {\n UINT8 MaxLanesReceivingTestPattern : 5;\n UINT8 Reserved : 3;\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_STATUS;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CAPABILITY Capability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CONTROL Control;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_STATUS Status;\n UINT32 ErrorCounter;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_AT_RECEIVER;\n///@}\n\n/// Page Request Interface Extended Capability Structure\n///\n/// Based on section 10.5.2 of PCI Express Base Specification 4.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PRI_ID 0x0013\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PRI_VER1 0x1\n\ntypedef union {\n struct {\n UINT32 PriRequestCapable : 1;\n UINT32 PriCompletionCapable : 1;\n UINT32 Page256RequestCapable : 1;\n UINT32 Page512RequestCapable : 1;\n UINT32 Page1KRequestCapable : 1;\n UINT32 Page2KRequestCapable : 1;\n UINT32 Page4KRequestCapable : 1;\n UINT32 Page8KRequestCapable : 1;\n UINT32 Reserved : 24;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CAPABILITY;\n\ntypedef union {\n struct {\n UINT32 PriEnable : 1;\n UINT32 PriReset : 1;\n UINT32 Reserved : 30;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CONTROL;\n\ntypedef union {\n struct {\n UINT32 OutstandingPageRequest : 1;\n UINT32 ResponseFailure : 1;\n UINT32 Stopped : 1;\n UINT32 PpRqIdParity : 1;\n UINT32 Reserved : 28;\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_STATUS;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CAPABILITY Capability;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CONTROL Control;\n PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_STATUS Status;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciExpress50.h", "content": "/** @file\nSupport for the PCI Express 5.0 standard.\n\nThis header file may not define all structures. Please extend as required.\n\nCopyright (c) 2020, American Megatrends International LLC. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef _PCIEXPRESS50_H_\n#define _PCIEXPRESS50_H_\n\n#include \"PciExpress40.h\"\n\n#pragma pack(1)\n\n/// The Physical Layer PCI Express Extended Capability definitions.\n///\n/// Based on section 7.7.6 of PCI Express Base Specification 5.0.\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1\n\n// Register offsets from Physical Layer PCI-E Ext Cap Header\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\n\ntypedef union {\n struct {\n UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0\n UINT32 NoEqualizationNeededSupport : 1; // bit 1\n UINT32 Reserved1 : 6; // Reserved bit 2:7\n UINT32 ModifiedTSUsageMode0Support : 1; // bit 8\n UINT32 ModifiedTSUsageMode1Support : 1; // bit 9\n UINT32 ModifiedTSUsageMode2Support : 1; // bit 10\n UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15\n UINT32 Reserved2 : 16; // Reserved bit 16:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;\n\ntypedef union {\n struct {\n UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0\n UINT32 NoEqualizationNeededDisable : 1; // bit 1\n UINT32 Reserved1 : 6; // Reserved bit 2:7\n UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10\n UINT32 Reserved2 : 21; // Reserved bit 11:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;\n\ntypedef union {\n struct {\n UINT32 EqualizationComplete : 1; // bit 0\n UINT32 EqualizationPhase1Success : 1; // bit 1\n UINT32 EqualizationPhase2Success : 1; // bit 2\n UINT32 EqualizationPhase3Success : 1; // bit 3\n UINT32 LinkEqualizationRequest : 1; // bit 4\n UINT32 ModifiedTSRcvd : 1; // bit 5\n UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7\n UINT32 TransmitterPrecodingOn : 1; // bit 8\n UINT32 TransmitterPrecodeRequest : 1; // bit 9\n UINT32 NoEqualizationNeededRcvd : 1; // bit 10\n UINT32 Reserved : 21; // Reserved bit 11:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;\n\ntypedef union {\n struct {\n UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2\n UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15\n UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;\n\ntypedef union {\n struct {\n UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23\n UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\n UINT32 Reserved : 6; // Reserved bit 26:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;\n\ntypedef union {\n struct {\n UINT32 TransModifiedTSUsageMode : 3; // bit 0:2\n UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15\n UINT32 TransModifiedTSVendorId : 16; // bit 16:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;\n\ntypedef union {\n struct {\n UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23\n UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\n UINT32 Reserved : 6; // Reserved bit 26:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;\n\ntypedef union {\n struct {\n UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\n UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;\n///@}\n\n/// Alternate Protocol Negotiation Extended Capability Structure\n///\n/// Based on section 7.9.21 of PCI Express Base Specification 5.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ALTERNATE_PROTOCOL_ID 0x002B\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_ALTERNATE_PROTOCOL_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 AltProtocolCapability;\n UINT32 AltProtocolStatus;\n UINT32 AltProtocolControl;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_ALTERNATE_PROTOCOL;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/edk2/PciExpress60.h", "content": "/** @file\nSupport for the PCI Express 6.0 standard.\n\nThis header file may not define all structures. Please extend as required.\n\nCopyright (c) 2024, American Megatrends International LLC. All rights reserved.
\nSPDX-License-Identifier: BSD-2-Clause-Patent\n\n**/\n\n#ifndef PCIEXPRESS60_H_\n#define PCIEXPRESS60_H_\n\n#include \"PciExpress50.h\"\n\n/// The Physical Layer PCI Express Extended Capability definitions.\n///\n/// Based on section 7.7.7 of PCI Express Base Specification 6.0.\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1\n\n// Register offsets from Physical Layer PCI-E Ext Cap Header\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C\n#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10\n\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1\n\n#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04\n#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08\n#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C\n\n#pragma pack(1)\n\ntypedef union {\n struct {\n UINT32 Reserved : 32; // Reserved bit 0:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;\n\ntypedef union {\n struct {\n UINT32 Reserved : 32; // Reserved bit 0:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;\n\ntypedef union {\n struct {\n UINT32 EqualizationComplete : 1; // bit 0\n UINT32 EqualizationPhase1Success : 1; // bit 1\n UINT32 EqualizationPhase2Success : 1; // bit 2\n UINT32 EqualizationPhase3Success : 1; // bit 3\n UINT32 LinkEqualizationRequest : 1; // bit 4\n UINT32 TransmitterPrecodingOn : 1; // bit 5\n UINT32 TransmitterPrecodeRequest : 1; // bit 6\n UINT32 NoEqualizationNeededRcvd : 1; // bit 7\n UINT32 Reserved : 24; // Reserved bit 8:31\n } Bits;\n UINT32 Uint32;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;\n\ntypedef union {\n struct {\n UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\n UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\n } Bits;\n UINT8 Uint8;\n} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;\n PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;\n///@}\n\ntypedef union {\n struct {\n UINT32 DmwrRequestRouting : 1; // bit 0\n UINT32 FourteenBitTagCompleter : 1; // bit 1\n UINT32 FourteenBitTagRequester : 1; // bit 2\n UINT32 ReceiverL0p : 1; // bit 3\n UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6\n UINT32 RetimerL0pExit : 3; // bit 7..9\n UINT32 Reserved : 22; // bit 10..31\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_DEVICE_CAPABILITY3;\n\ntypedef union {\n struct {\n UINT32 DmwrRequesterEnable : 1; // bit 0\n UINT32 DmwrEgressBlocking : 1; // bit 1\n UINT32 FourteenBitTagRequesterEnable : 1; // bit 2\n UINT32 L0pEnable : 1; // bit 3\n UINT32 TargetLinkWidth : 3; // bit 4..6\n UINT32 Reserved : 25; // bit 7..31\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_DEVICE_CONTROL3;\n\ntypedef union {\n struct {\n UINT32 InitialLinkWidth : 3; // bit 0..2\n UINT32 SegmentCaptured : 1; // bit 3\n UINT32 RemoteL0pSupported : 1; // bit 4\n UINT32 Reserved : 27; // bit 5..31\n } Bits;\n UINT32 Uint32;\n} PCI_REG_PCIE_DEVICE_STATUS3;\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n PCI_REG_PCIE_DEVICE_CAPABILITY3 Capabilities;\n PCI_REG_PCIE_DEVICE_CONTROL3 Control;\n PCI_REG_PCIE_DEVICE_STATUS3 Status;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DEVICE3;\n\n/// Flit Logging Extended Capability Structure\n///\n/// Based on section 7.7.8 of PCI Express Base Specification 6.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_FLIT_LOGGING_ID 0x0032\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_FLIT_LOGGING_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 FlitLoggingCapabilities;\n UINT32 FlitLoggingControl;\n UINT32 FlitLoggingStatus;\n UINT32 FlitMask;\n UINT32 FlitErrorData1;\n UINT32 FlitErrorData2;\n UINT32 FlitErrorData3;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_FLIT_LOGGING;\n///@}\n\n/// Data Object Exchange Extended Capability Structure\n///\n/// Based on section 7.9.24 of PCI Express Base Specification 6.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DATA_OBJECT_EXCHANGE_ID 0x002E\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_DATA_OBJECT_EXCHANGE_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 DoeCapabilities;\n UINT16 DoeControl;\n UINT16 DoeStatus;\n UINT32 UncorrectableErrorMask;\n UINT32 UncorrectableErrorSeverity;\n UINT32 CorrectableErrorMask;\n UINT32 DoeSendObjectControl;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_OBJECT_EXCHANGE;\n///@}\n\n/// Integrity Data Encryption Extended Capability Structure\n///\n/// Based on section 7.9.26 of PCI Express Base Specification 6.0\n///@{\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_INTEGRITY_DATA_ENCRYPTION_ID 0x0030\n#define PCI_EXPRESS_EXTENDED_CAPABILITY_INTEGRITY_DATA_ENCRYPTION_VER1 0x1\n\ntypedef struct {\n PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\n UINT32 IdeCapabilities;\n UINT32 IdeControl;\n UINT32 IdeStatus;\n UINT32 IdeSendMcCapabilities;\n UINT32 IdeSendMcControl;\n UINT32 IdeSendMcStatus;\n} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTEGRITY_DATA_ENCRYPTION;\n///@}\n\n#pragma pack()\n\n#endif\n" }, { "path": "src/intel_workarounds.c", "content": "#include \n#include \"csmwrap.h\"\n\n#include \"io.h\"\n\n#define PCI_DEVICE_NUMBER_PCH_P2SB 31\n#define PCI_FUNCTION_NUMBER_PCH_P2SB 1\n\n#define\tSBREG_BAR\t\t0x10\n#define SBREG_BARH 0x14\n\n/* PCH sideband parameters vary by CPU generation - detected via CPUID */\nstruct pch_info {\n uintptr_t sbreg_bar;\n uint8_t pid_itss;\n};\n\n/* Intel CPU model numbers (Family 6) */\n#define INTEL_SKYLAKE_L 0x4E\n#define INTEL_SKYLAKE 0x5E\n#define INTEL_SKYLAKE_X 0x55\n#define INTEL_KABYLAKE_L 0x8E\n#define INTEL_KABYLAKE 0x9E\n#define INTEL_COMETLAKE 0xA5\n#define INTEL_COMETLAKE_L 0xA6\n#define INTEL_ICELAKE_L 0x7E\n#define INTEL_TIGERLAKE_L 0x8C\n#define INTEL_TIGERLAKE 0x8D\n#define INTEL_ALDERLAKE 0x97\n#define INTEL_ALDERLAKE_L 0x9A\n#define INTEL_RAPTORLAKE 0xB7\n#define INTEL_RAPTORLAKE_P 0xBA\n#define INTEL_RAPTORLAKE_S 0xBF\n#define INTEL_METEORLAKE 0xAC\n#define INTEL_METEORLAKE_L 0xAA\n#define INTEL_ARROWLAKE 0xC6\n#define INTEL_ARROWLAKE_H 0xC5\n#define INTEL_ARROWLAKE_U 0xB5\n#define INTEL_LUNARLAKE 0xBD\n#define INTEL_PANTHERLAKE_L 0xCC\n\nstatic bool get_pch_info(struct pch_info *info)\n{\n uint32_t eax, ebx, ecx, edx;\n asm volatile(\"cpuid\" : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx) : \"a\"(1), \"c\"(0));\n\n uint8_t family = (eax >> 8) & 0xF;\n uint8_t model = (eax >> 4) & 0xF;\n if (family == 6 || family == 15)\n model |= ((eax >> 16) & 0xF) << 4;\n\n if (family != 6)\n return false;\n\n switch (model) {\n /* Meteor Lake / Arrow Lake / Panther Lake: SBREG=0xE0000000 */\n case INTEL_METEORLAKE:\n case INTEL_METEORLAKE_L:\n case INTEL_ARROWLAKE:\n case INTEL_ARROWLAKE_H:\n case INTEL_ARROWLAKE_U:\n case INTEL_LUNARLAKE:\n info->sbreg_bar = 0xE0000000;\n info->pid_itss = 0xCA;\n return true;\n case INTEL_PANTHERLAKE_L:\n info->sbreg_bar = 0xE0000000;\n info->pid_itss = 0x69;\n return true;\n /* Alder Lake / Raptor Lake Desktop (S-series, PCH-S): SBREG=0xE0000000 */\n case INTEL_ALDERLAKE:\n case INTEL_RAPTORLAKE:\n case INTEL_RAPTORLAKE_S:\n info->sbreg_bar = 0xE0000000;\n info->pid_itss = 0xC4;\n return true;\n /* Alder Lake / Raptor Lake Mobile (P-series, PCH-P): SBREG=0xFD000000 */\n case INTEL_ALDERLAKE_L:\n case INTEL_RAPTORLAKE_P:\n info->sbreg_bar = 0xFD000000;\n info->pid_itss = 0xC4;\n return true;\n /* Skylake through Tiger Lake: SBREG=0xFD000000 */\n case INTEL_SKYLAKE_L:\n case INTEL_SKYLAKE:\n case INTEL_SKYLAKE_X:\n case INTEL_KABYLAKE_L:\n case INTEL_KABYLAKE:\n case INTEL_COMETLAKE:\n case INTEL_COMETLAKE_L:\n case INTEL_ICELAKE_L:\n case INTEL_TIGERLAKE_L:\n case INTEL_TIGERLAKE:\n info->sbreg_bar = 0xFD000000;\n info->pid_itss = 0xC4;\n return true;\n default:\n return false;\n }\n}\n\n#define R_PCH_PCR_ITSS_ITSSPRC 0x3300\n#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE (1 << 2)\n\n#define PCH_PCR_ADDRESS(Base, Pid, Offset) ((void *)(Base | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF)))\n\n#define R_P2SB_CFG_P2SBC 0xE0\n#define B_P2SB_CFG_P2SBC_HIDE (1 << 8)\n\nstatic int pit_8254cge_workaround(void)\n{\n struct pch_info pch;\n uint32_t reg;\n uintptr_t base;\n bool p2sb_hide = false;\n int pch_pci_bus = 0;\n\n if (!get_pch_info(&pch)) {\n printf(\"Unknown CPU model, skipping PIT workaround\\n\");\n return 0;\n }\n\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n 0x0);\n\n /* P2SB maybe hidden, try unhide it first */\n if ((reg & 0xFFFF) == 0xffff) {\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC);\n reg &= ~B_P2SB_CFG_P2SBC_HIDE;\n pciConfigWriteDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC, reg);\n p2sb_hide = true;\n }\n\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n 0x0);\n\n if ((reg & 0xFFFF) != 0x8086) {\n /* P2SB locked hidden - use CPUID-determined SBREG_BAR */\n base = pch.sbreg_bar;\n } else {\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n SBREG_BAR);\n base = reg & ~0x0F;\n\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n SBREG_BARH);\n#ifdef __LP64__\n base |= ((uint64_t)reg & 0xFFFFFFFF) << 32;\n#else\n if (reg) {\n printf(\"Invalid P2SB BARH\\n\");\n goto hide_and_return;\n }\n#endif\n /* Hide P2SB again */\n if (p2sb_hide) {\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC);\n reg |= B_P2SB_CFG_P2SBC_HIDE;\n pciConfigWriteDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC, reg);\n }\n }\n\n reg = readl(PCH_PCR_ADDRESS(base, pch.pid_itss, R_PCH_PCR_ITSS_ITSSPRC));\n printf(\"ITSSPRC = %x, ITSSPRC.8254CGE= %x\\n\", reg, !!(reg & B_PCH_PCR_ITSS_ITSSPRC_8254CGE));\n /* Disable 8254CGE */\n reg &= ~B_PCH_PCR_ITSS_ITSSPRC_8254CGE;\n writel(PCH_PCR_ADDRESS(base, pch.pid_itss, R_PCH_PCR_ITSS_ITSSPRC), reg);\n\n return 0;\n\n#ifndef __LP64__\nhide_and_return:\n if (p2sb_hide) {\n reg = pciConfigReadDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC);\n reg |= B_P2SB_CFG_P2SBC_HIDE;\n pciConfigWriteDWord(pch_pci_bus, PCI_DEVICE_NUMBER_PCH_P2SB,\n PCI_FUNCTION_NUMBER_PCH_P2SB,\n R_P2SB_CFG_P2SBC, reg);\n }\n return 0;\n#endif\n}\n\nint apply_intel_platform_workarounds(void)\n{\n uint16_t vendor_id;\n\n vendor_id = pciConfigReadWord(0, 0, 0, 0x0);\n\n if (vendor_id != 0x8086) {\n return 0;\n }\n\n pit_8254cge_workaround();\n\n return 0;\n}\n" }, { "path": "src/io.h", "content": "#ifndef _IO_H\n#define _IO_H\n\n#include \n#include \n#include \n\n#define barrier() __asm__ __volatile__(\"\": : :\"memory\")\n\nstatic inline void clflush(void *addr) {\n // Cache CPUID.01H:EDX[19] (CLFLUSH support) to avoid repeated CPUID calls\n static int has_clflush = -1;\n if (has_clflush == -1) {\n uint32_t eax, ebx, ecx, edx;\n asm volatile (\"cpuid\" : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx) : \"a\"(1) : \"memory\");\n has_clflush = (edx >> 19) & 1;\n }\n if (has_clflush) {\n asm volatile (\"clflush (%0)\" :: \"r\"(addr) : \"memory\");\n } else {\n // Fall back to wbinvd (flushes entire cache, requires ring 0)\n asm volatile (\"wbinvd\" ::: \"memory\");\n }\n}\n\nstatic inline void writel(void *addr, uint32_t val) {\n barrier();\n *(volatile uint32_t *)addr = val;\n}\nstatic inline void writew(void *addr, uint16_t val) {\n barrier();\n *(volatile uint16_t *)addr = val;\n}\nstatic inline void writeb(void *addr, uint8_t val) {\n barrier();\n *(volatile uint8_t *)addr = val;\n}\nstatic inline uint64_t readq(const void *addr) {\n uint64_t val = *(volatile const uint64_t *)addr;\n barrier();\n return val;\n}\nstatic inline uint32_t readl(const void *addr) {\n uint32_t val = *(volatile const uint32_t *)addr;\n barrier();\n return val;\n}\nstatic inline uint16_t readw(const void *addr) {\n uint16_t val = *(volatile const uint16_t *)addr;\n barrier();\n return val;\n}\nstatic inline uint8_t readb(const void *addr) {\n uint8_t val = *(volatile const uint8_t *)addr;\n barrier();\n return val;\n}\n\n#ifdef __OPTIMIZE__\n\n#define\t__use_immediate_port(port) \\\n\t(__builtin_constant_p(((int)port)) && ((int)port) < 0x100)\n\n#else\n\n#define\t__use_immediate_port(port)\t0\n\n#endif\n\n\n#define\tinb(port) \\\n\t(__use_immediate_port((int)port) ? __inbc((int)port) : __inb((int)port))\n\nstatic inline uint8_t\n__inbc(int port)\n{\n\tuint8_t data;\n\tasm volatile(\"inb %w1,%0\" : \"=a\" (data) : \"id\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline uint8_t\n__inb(int port)\n{\n\tuint8_t data;\n\tasm volatile(\"inb %w1,%0\" : \"=a\" (data) : \"d\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline void\ninsb(int port, void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\tinsb\"\n\t : \"+D\" (addr), \"+c\" (cnt) : \"d\" (port) : \"memory\", \"cc\");\n}\n\n#define\tinw(port) \\\n\t(__use_immediate_port((int)port) ? __inwc((int)port) : __inw((int)port))\n\nstatic inline uint16_t\n__inwc(int port)\n{\n\tuint16_t data;\n\tasm volatile(\"inw %w1,%0\" : \"=a\" (data) : \"id\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline uint16_t\n__inw(int port)\n{\n\tuint16_t data;\n\tasm volatile(\"inw %w1,%0\" : \"=a\" (data) : \"d\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline void\ninsw(int port, void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\tinsw\"\n\t : \"+D\" (addr), \"+c\" (cnt) : \"d\" (port) : \"memory\", \"cc\");\n}\n\n#define\tinl(port) \\\n\t(__use_immediate_port(port) ? __inlc((int)port) : __inl((int)port))\n\nstatic inline uint32_t\n__inlc(int port)\n{\n\tuint32_t data;\n\tasm volatile(\"inl %w1,%0\" : \"=a\" (data) : \"id\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline uint32_t\n__inl(int port)\n{\n\tuint32_t data;\n\tasm volatile(\"inl %w1,%0\" : \"=a\" (data) : \"d\" (port) : \"memory\");\n\treturn data;\n}\n\nstatic inline void\ninsl(int port, void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\tinsl\"\n\t : \"+D\" (addr), \"+c\" (cnt) : \"d\" (port) : \"memory\", \"cc\");\n}\n\n#define\toutb(port, data) \\\n\t(__use_immediate_port(port) ? __outbc((int)port, data) : __outb((int)port, data))\n\nstatic inline void\n__outbc(int port, uint8_t data)\n{\n\tasm volatile(\"outb %0,%w1\" : : \"a\" (data), \"id\" (port) : \"memory\");\n}\n\nstatic inline void\n__outb(int port, uint8_t data)\n{\n\tasm volatile(\"outb %0,%w1\" : : \"a\" (data), \"d\" (port) : \"memory\");\n}\n\nstatic inline void\noutsb(int port, const void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\toutsb\"\n\t : \"+S\" (addr), \"+c\" (cnt) : \"d\" (port) : \"cc\", \"memory\");\n}\n\n#define\toutw(port, data) \\\n\t(__use_immediate_port(port) ? __outwc((int)port, data) : __outw((int)port, data))\n\nstatic inline void\n__outwc(int port, uint16_t data)\n{\n\tasm volatile(\"outw %0,%w1\" : : \"a\" (data), \"id\" (port) : \"memory\");\n}\n\nstatic inline void\n__outw(int port, uint16_t data)\n{\n\tasm volatile(\"outw %0,%w1\" : : \"a\" (data), \"d\" (port) : \"memory\");\n}\n\nstatic inline void\noutsw(int port, const void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\toutsw\"\n\t : \"+S\" (addr), \"+c\" (cnt) : \"d\" (port) : \"cc\", \"memory\");\n}\n\n#define\toutl(port, data) \\\n\t(__use_immediate_port(port) ? __outlc((int)port, data) : __outl((int)port, data))\n\nstatic inline void\n__outlc(int port, uint32_t data)\n{\n\tasm volatile(\"outl %0,%w1\" : : \"a\" (data), \"id\" (port) : \"memory\");\n}\n\nstatic inline void\n__outl(int port, uint32_t data)\n{\n\tasm volatile(\"outl %0,%w1\" : : \"a\" (data), \"d\" (port) : \"memory\");\n}\n\nstatic inline void\noutsl(int port, const void *addr, int cnt)\n{\n\tasm volatile(\"cld\\n\\trepne\\n\\toutsl\"\n\t : \"+S\" (addr), \"+c\" (cnt) : \"d\" (port) : \"cc\", \"memory\");\n}\n\n#define PCI_CONFIG_ADDRESS 0xcf8\n#define PCI_CONFIG_DATA 0xcfc\n\nstatic inline void pciSetAddress(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset)\n{\n uint32_t address;\n\n /* Address bits (inclusive):\n * 31 Enable bit (must be 1 for it to work)\n * 30 - 24 Reserved\n * 23 - 16 Bus number\n * 15 - 11 Slot number\n * 10 - 8 Function number (for multifunction devices)\n * 7 - 2 Register number (offset / 4)\n * 1 - 0 Must always be 00 */\n address = 0x80000000 | ((unsigned long) (bus & 0xff) << 16)\n | ((unsigned long) (slot & 0x1f) << 11)\n | ((unsigned long) (function & 0x7) << 8)\n | ((unsigned long) offset & 0xfc);\n /* Full DWORD write to port must be used for PCI to detect new address. */\n outl(PCI_CONFIG_ADDRESS, address);\n}\n\nstatic inline uint8_t pciConfigReadByte(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset)\n{\n pciSetAddress(bus, slot, function, offset);\n /* The PCI registers are little endian,\n * so the last byte of DWORD is read\n * when offset is 0. */\n return (inb(PCI_CONFIG_DATA + (offset & 3)));\n}\n\nstatic inline uint16_t pciConfigReadWord(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset)\n{\n pciSetAddress(bus, slot, function, offset);\n /* The PCI registers are little endian,\n * so the last word of DWORD is read\n * when offset is 0. */\n return (inw(PCI_CONFIG_DATA + (offset & 2)));\n}\n\nstatic inline uint32_t pciConfigReadDWord(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset)\n{\n pciSetAddress(bus, slot, function, offset);\n return (inl(PCI_CONFIG_DATA));\n}\n\nstatic inline void pciConfigWriteByte(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset,\n uint8_t data)\n{\n pciSetAddress(bus, slot, function, offset);\n /* The PCI registers are little endian,\n * so the last byte of DWORD is written\n * when offset is 0. */\n outb(PCI_CONFIG_DATA + (offset & 3), data);\n}\n\nstatic inline void pciConfigWriteWord(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset,\n uint16_t data)\n{\n pciSetAddress(bus, slot, function, offset);\n /* The PCI registers are little endian,\n * so the last word of DWORD is written\n * when offset is 0. */\n outw(PCI_CONFIG_DATA + (offset & 2), data);\n}\n\nstatic inline void pciConfigWriteDWord(unsigned int bus, unsigned int slot,\n unsigned int function, unsigned int offset,\n uint32_t data)\n{\n pciSetAddress(bus, slot, function, offset);\n outl(PCI_CONFIG_DATA, data);\n}\n\nstatic inline uint64_t rdmsr(uint32_t index) {\n uint32_t edx, eax;\n asm volatile (\"rdmsr\" : \"=a\"(eax), \"=d\"(edx) : \"c\"(index) : \"memory\");\n return ((uint64_t)edx << 32) | eax;\n}\n\nstatic inline void wrmsr(uint32_t index, uint64_t val) {\n asm volatile (\"wrmsr\" :: \"a\"((uint32_t)val), \"d\"((uint32_t)(val >> 32)), \"c\"(index) : \"memory\");\n}\n\nstatic inline uint64_t rdtsc(void) {\n uint32_t edx, eax;\n asm volatile (\"rdtsc\" : \"=a\" (eax), \"=d\" (edx) :: \"memory\");\n return ((uint64_t)edx << 32) | eax;\n}\n\n#endif\n" }, { "path": "src/iommu.c", "content": "#include \n#include \n\n#include \"csmwrap.h\"\n#include \"io.h\"\n#include \"iommu.h\"\n\n#include \n#include \n\n/*\n * IOMMU Disabling for Legacy OS Handoff\n *\n * Disables Intel VT-d and AMD-Vi IOMMUs before legacy OS boot.\n * This is necessary because UEFI-configured IOMMU translation tables\n * become stale after PCI BAR relocation.\n */\n\n/*\n * Intel VT-d DMAR Table Structures\n * Reference: Intel VT-d Architecture Specification\n */\n\n#define ACPI_DMAR_SIGNATURE \"DMAR\"\n\n#define DMAR_TYPE_DRHD 0 /* DMA Remapping Hardware Unit Definition */\n\nstruct dmar_header {\n uint16_t type;\n uint16_t length;\n} __attribute__((packed));\n\nstruct dmar_drhd {\n struct dmar_header header;\n uint8_t flags;\n uint8_t reserved;\n uint16_t segment;\n uint64_t register_base;\n} __attribute__((packed));\n\n/*\n * Intel VT-d Register Offsets\n */\n#define VTD_GCMD_REG 0x18\n#define VTD_GSTS_REG 0x1C\n\n#define VTD_GCMD_TE (1U << 31)\n#define VTD_GCMD_IRE (1U << 25)\n#define VTD_GCMD_QIE (1U << 26)\n#define VTD_GSTS_TES (1U << 31)\n#define VTD_GSTS_IRES (1U << 25)\n#define VTD_GSTS_QIES (1U << 26)\n\n/*\n * Mask to clear one-shot command bits when reading GSTS to write to GCMD.\n * One-shot bits (30, 29, 27, 24) trigger hardware operations when set:\n * - Bit 30: SRTP (Set Root Table Pointer)\n * - Bit 29: SFL (Set Fault Log)\n * - Bit 27: WBF (Write Buffer Flush)\n * - Bit 24: SIRTP (Set Interrupt Remap Table Pointer)\n * Reference: EDK2 IntelSiliconPkg/VTd and Intel VT-d Specification\n */\n#define VTD_GSTS_ONESHOT_MASK 0x96FFFFFF\n\n/*\n * AMD IOMMU (AMD-Vi) IVRS Table Structures\n * Reference: AMD I/O Virtualization Technology (IOMMU) Specification\n */\n\n#define ACPI_IVRS_SIGNATURE \"IVRS\"\n\n#define IVRS_TYPE_IVHD_10 0x10\n#define IVRS_TYPE_IVHD_11 0x11\n#define IVRS_TYPE_IVHD_40 0x40\n\nstruct acpi_ivrs {\n struct acpi_sdt_hdr hdr;\n uint32_t iv_info;\n uint64_t reserved;\n} __attribute__((packed));\n\nstruct ivrs_header {\n uint8_t type;\n uint8_t flags;\n uint16_t length;\n uint16_t device_id;\n uint16_t capability_offset;\n uint64_t iommu_base;\n} __attribute__((packed));\n\n/*\n * AMD IOMMU Register Offsets\n *\n * The control register is 64-bit at offset 0x18, but every bit we touch lives\n * in the low 32 bits, so we read/write the low half only and leave the upper\n * half untouched.\n */\n#define AMD_IOMMU_CTRL_REG 0x18\n#define AMD_IOMMU_CTRL_EN (1ULL << 0)\n#define AMD_IOMMU_CTRL_EVT_LOG (1ULL << 2)\n#define AMD_IOMMU_CTRL_EVT_INT (1ULL << 3)\n#define AMD_IOMMU_CTRL_CMDBUF (1ULL << 12)\n#define AMD_IOMMU_CTRL_PPR_LOG (1ULL << 13)\n#define AMD_IOMMU_CTRL_PPR_INT (1ULL << 14)\n#define AMD_IOMMU_CTRL_PPR (1ULL << 15)\n#define AMD_IOMMU_CTRL_GA_LOG (1ULL << 28)\n#define AMD_IOMMU_CTRL_GA_INT (1ULL << 29)\n\n#define AMD_IOMMU_STATUS_REG 0x2020\n#define AMD_IOMMU_STATUS_EVTLOG_RUN (1ULL << 3)\n#define AMD_IOMMU_STATUS_CMDBUF_RUN (1ULL << 4)\n#define AMD_IOMMU_STATUS_PPRLOG_RUN (1ULL << 7)\n#define AMD_IOMMU_STATUS_GALOG_RUN (1ULL << 8)\n\n/*\n * Disable a single Intel VT-d IOMMU unit\n */\nstatic bool vtd_disable_unit(uint64_t reg_base) {\n void *base = (void *)(uintptr_t)reg_base;\n uint32_t gsts, gcmd;\n\n gsts = readl(base + VTD_GSTS_REG);\n printf(\" VT-d unit at 0x%llx: GSTS=0x%08x (TE=%d, IRE=%d, QIE=%d)\\n\",\n reg_base, gsts,\n !!(gsts & VTD_GSTS_TES),\n !!(gsts & VTD_GSTS_IRES),\n !!(gsts & VTD_GSTS_QIES));\n\n if (!(gsts & (VTD_GSTS_TES | VTD_GSTS_IRES | VTD_GSTS_QIES))) {\n printf(\" Already fully disabled\\n\");\n return true;\n }\n\n /* Disable translation (TE) */\n if (gsts & VTD_GSTS_TES) {\n gcmd = gsts & VTD_GSTS_ONESHOT_MASK;\n gcmd &= ~VTD_GCMD_TE;\n writel(base + VTD_GCMD_REG, gcmd);\n\n while ((gsts = readl(base + VTD_GSTS_REG)) & VTD_GSTS_TES)\n asm volatile(\"pause\");\n printf(\" Translation disabled\\n\");\n }\n\n /* Disable interrupt remapping (IRE) */\n if (gsts & VTD_GSTS_IRES) {\n gcmd = gsts & VTD_GSTS_ONESHOT_MASK;\n gcmd &= ~(VTD_GCMD_TE | VTD_GCMD_IRE);\n writel(base + VTD_GCMD_REG, gcmd);\n\n while ((gsts = readl(base + VTD_GSTS_REG)) & VTD_GSTS_IRES)\n asm volatile(\"pause\");\n printf(\" Interrupt remapping disabled\\n\");\n }\n\n /* Disable queued invalidation (QIE) - must be after TE and IRE */\n if (gsts & VTD_GSTS_QIES) {\n gcmd = gsts & VTD_GSTS_ONESHOT_MASK;\n gcmd &= ~(VTD_GCMD_TE | VTD_GCMD_IRE | VTD_GCMD_QIE);\n writel(base + VTD_GCMD_REG, gcmd);\n\n while ((gsts = readl(base + VTD_GSTS_REG)) & VTD_GSTS_QIES)\n asm volatile(\"pause\");\n printf(\" Queued invalidation disabled\\n\");\n }\n\n return true;\n}\n\n/*\n * Parse DMAR table and disable all Intel VT-d IOMMUs\n */\nstatic int vtd_disable_all(void) {\n uacpi_table tbl;\n uacpi_status status;\n struct acpi_dmar *dmar;\n uint8_t *ptr, *end;\n int disabled = 0;\n\n status = uacpi_table_find_by_signature(ACPI_DMAR_SIGNATURE, &tbl);\n if (status != UACPI_STATUS_OK) {\n return 0; /* No DMAR table, no Intel VT-d */\n }\n\n dmar = (struct acpi_dmar *)tbl.hdr;\n printf(\"DMAR: found table, host_address_width=%d, flags=0x%02x\\n\",\n dmar->haw, dmar->flags);\n\n ptr = (uint8_t *)dmar + sizeof(struct acpi_dmar);\n end = (uint8_t *)dmar + dmar->hdr.length;\n\n while (ptr + sizeof(struct dmar_header) <= end) {\n struct dmar_header *hdr = (struct dmar_header *)ptr;\n\n if (hdr->length < sizeof(struct dmar_header) || ptr + hdr->length > end) {\n printf(\"DMAR: invalid structure length\\n\");\n break;\n }\n\n if (hdr->type == DMAR_TYPE_DRHD) {\n struct dmar_drhd *drhd = (struct dmar_drhd *)ptr;\n printf(\"DMAR: DRHD segment=%d flags=0x%02x base=0x%llx\\n\",\n drhd->segment, drhd->flags, drhd->register_base);\n\n if (vtd_disable_unit(drhd->register_base)) {\n disabled++;\n }\n }\n\n ptr += hdr->length;\n }\n\n uacpi_table_unref(&tbl);\n return disabled;\n}\n\n/*\n * Disable a single AMD IOMMU unit\n */\nstatic bool amd_iommu_disable_unit(uint64_t iommu_base) {\n void *base = (void *)(uintptr_t)iommu_base;\n uint32_t ctrl;\n\n ctrl = readl(base + AMD_IOMMU_CTRL_REG);\n printf(\" AMD IOMMU at 0x%llx: CTRL=0x%08x (En=%d)\\n\",\n iommu_base, ctrl, !!(ctrl & AMD_IOMMU_CTRL_EN));\n\n if (!(ctrl & AMD_IOMMU_CTRL_EN)) {\n printf(\" IOMMU already disabled\\n\");\n return true;\n }\n\n /* Disable command buffer, logs and their interrupts before clearing the\n * master enable. Clearing IommuEn while sub-features are still live can\n * leave queued descriptors and in-flight DMA in an undefined state. */\n ctrl &= ~(AMD_IOMMU_CTRL_CMDBUF |\n AMD_IOMMU_CTRL_EVT_LOG | AMD_IOMMU_CTRL_EVT_INT |\n AMD_IOMMU_CTRL_GA_LOG | AMD_IOMMU_CTRL_GA_INT |\n AMD_IOMMU_CTRL_PPR_LOG | AMD_IOMMU_CTRL_PPR_INT |\n AMD_IOMMU_CTRL_PPR);\n writel(base + AMD_IOMMU_CTRL_REG, ctrl);\n\n /* The *Run bits are level-sensitive and only drop to 0 once the engine\n * has actually drained, so wait for them before continuing. */\n const uint32_t run_mask = AMD_IOMMU_STATUS_CMDBUF_RUN | AMD_IOMMU_STATUS_EVTLOG_RUN |\n AMD_IOMMU_STATUS_PPRLOG_RUN | AMD_IOMMU_STATUS_GALOG_RUN;\n while (readl(base + AMD_IOMMU_STATUS_REG) & run_mask)\n asm volatile(\"pause\");\n\n ctrl &= ~AMD_IOMMU_CTRL_EN;\n writel(base + AMD_IOMMU_CTRL_REG, ctrl);\n\n printf(\" IOMMU disabled successfully\\n\");\n return true;\n}\n\n/*\n * Parse IVRS table and disable all AMD IOMMUs\n */\nstatic int amd_iommu_disable_all(void) {\n uacpi_table tbl;\n uacpi_status status;\n struct acpi_ivrs *ivrs;\n uint8_t *ptr, *end;\n int disabled = 0;\n\n status = uacpi_table_find_by_signature(ACPI_IVRS_SIGNATURE, &tbl);\n if (status != UACPI_STATUS_OK) {\n return 0; /* No IVRS table, no AMD IOMMU */\n }\n\n ivrs = (struct acpi_ivrs *)tbl.hdr;\n printf(\"IVRS: found table, iv_info=0x%08x\\n\", ivrs->iv_info);\n\n ptr = (uint8_t *)ivrs + sizeof(struct acpi_ivrs);\n end = (uint8_t *)ivrs + ivrs->hdr.length;\n\n while (ptr + sizeof(struct ivrs_header) <= end) {\n struct ivrs_header *hdr = (struct ivrs_header *)ptr;\n\n if (hdr->length < sizeof(struct ivrs_header) || ptr + hdr->length > end) {\n printf(\"IVRS: invalid block length\\n\");\n break;\n }\n\n if (hdr->type == IVRS_TYPE_IVHD_10 ||\n hdr->type == IVRS_TYPE_IVHD_11 ||\n hdr->type == IVRS_TYPE_IVHD_40) {\n printf(\"IVRS: IVHD type=0x%02x device_id=0x%04x base=0x%llx\\n\",\n hdr->type, hdr->device_id, hdr->iommu_base);\n\n if (amd_iommu_disable_unit(hdr->iommu_base)) {\n disabled++;\n }\n }\n\n ptr += hdr->length;\n }\n\n uacpi_table_unref(&tbl);\n return disabled;\n}\n\n/*\n * Main entry point: disable all IOMMUs\n */\nbool iommu_disable(void) {\n int vtd_count = 0;\n int amd_count = 0;\n\n printf(\"Disabling IOMMUs for legacy OS compatibility...\\n\");\n\n vtd_count = vtd_disable_all();\n if (vtd_count > 0) {\n printf(\"Disabled %d Intel VT-d IOMMU unit(s)\\n\", vtd_count);\n }\n\n amd_count = amd_iommu_disable_all();\n if (amd_count > 0) {\n printf(\"Disabled %d AMD IOMMU unit(s)\\n\", amd_count);\n }\n\n if (vtd_count == 0 && amd_count == 0) {\n printf(\"No IOMMUs found or all already disabled\\n\");\n return false;\n }\n\n return true;\n}\n" }, { "path": "src/iommu.h", "content": "#ifndef IOMMU_H\n#define IOMMU_H\n\n#include \n\n/*\n * Disable all IOMMUs (Intel VT-d and AMD-Vi) to allow legacy OS booting.\n *\n * This is called after ExitBootServices but before CSM initialization.\n * UEFI may have configured IOMMU translation tables, but after PCI BAR\n * relocation, those tables reference stale addresses. Disabling the IOMMU\n * prevents DMA failures in the legacy OS.\n *\n * Returns true if IOMMUs were found and disabled, false otherwise.\n */\nbool iommu_disable(void);\n\n#endif\n" }, { "path": "src/libc.c", "content": "#include \n#include \n#include \n\n#ifdef memcpy\n# undef memcpy\n#endif\nvoid *memcpy(void *restrict dest, const void *restrict src, size_t n) {\n uint8_t *restrict pdest = (uint8_t *restrict)dest;\n const uint8_t *restrict psrc = (const uint8_t *restrict)src;\n\n for (size_t i = 0; i < n; i++) {\n pdest[i] = psrc[i];\n }\n\n return dest;\n}\n\n#ifdef memset\n# undef memset\n#endif\nvoid *memset(void *s, int c, size_t n) {\n uint8_t *p = (uint8_t *)s;\n\n for (size_t i = 0; i < n; i++) {\n p[i] = (uint8_t)c;\n }\n\n return s;\n}\n\n#ifdef memmove\n# undef memmove\n#endif\nvoid *memmove(void *dest, const void *src, size_t n) {\n uint8_t *pdest = (uint8_t *)dest;\n const uint8_t *psrc = (const uint8_t *)src;\n\n if ((uintptr_t)src > (uintptr_t)dest) {\n for (size_t i = 0; i < n; i++) {\n pdest[i] = psrc[i];\n }\n } else if ((uintptr_t)src < (uintptr_t)dest) {\n for (size_t i = n; i > 0; i--) {\n pdest[i-1] = psrc[i-1];\n }\n }\n\n return dest;\n}\n\n#ifdef memcmp\n# undef memcmp\n#endif\nint memcmp(const void *s1, const void *s2, size_t n) {\n const uint8_t *p1 = (const uint8_t *)s1;\n const uint8_t *p2 = (const uint8_t *)s2;\n\n for (size_t i = 0; i < n; i++) {\n if (p1[i] != p2[i]) {\n return p1[i] < p2[i] ? -1 : 1;\n }\n }\n\n return 0;\n}\n" }, { "path": "src/libc.h", "content": "#ifndef LIBC_H\n#define LIBC_H\n\n#include \n\nvoid *memcpy(void *restrict dest, const void *restrict src, size_t n);\nvoid *memset(void *s, int c, size_t n);\nvoid *memmove(void *dest, const void *src, size_t n);\nint memcmp(const void *s1, const void *s2, size_t n);\n\n/* Access builtin version by default. */\n#define memcpy __builtin_memcpy\n#define memset __builtin_memset\n#define memmove __builtin_memmove\n#define memcmp __builtin_memcmp\n\n#endif\n" }, { "path": "src/mptable.c", "content": "/*\n * MP Table Generation from ACPI\n *\n * Generates Intel MultiProcessor Specification tables from ACPI MADT\n * for legacy BIOS compatibility. The helper core reserved for BIOS proxy\n * is excluded from the generated tables.\n */\n\n#include \n#include \n#include \"csmwrap.h\"\n#include \"config.h\"\n#include \"mptable.h\"\n#include \"bios_proxy.h\"\n#include \"io.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n/* MP Table Signatures */\n#define MPTABLE_SIGNATURE 0x5f504d5f /* \"_MP_\" */\n#define MPCONFIG_SIGNATURE 0x504d4350 /* \"PCMP\" */\n\n/* IA32_APIC_BASE physical-address bits [51:12]. */\n#define APIC_BASE_ADDR_MASK 0xFFFFFFFFFFFFF000ULL\n\n/* MP Table Entry Types */\n#define MPT_TYPE_CPU 0\n#define MPT_TYPE_BUS 1\n#define MPT_TYPE_IOAPIC 2\n#define MPT_TYPE_INTSRC 3\n#define MPT_TYPE_LOCAL_INT 4\n\n/* Interrupt types for mpt_intsrc.irqtype */\n#define MP_INT_TYPE_INT 0 /* Vectored interrupt */\n#define MP_INT_TYPE_NMI 1 /* Non-maskable interrupt */\n#define MP_INT_TYPE_SMI 2 /* System management interrupt */\n#define MP_INT_TYPE_EXTINT 3 /* External interrupt (8259) */\n\n/* Interrupt flags (polarity and trigger mode) */\n#define MP_IRQFLAG_CONFORM 0x0000 /* Conforms to bus specification */\n#define MP_IRQFLAG_ACTIVE_HIGH 0x0001 /* Active high polarity */\n#define MP_IRQFLAG_ACTIVE_LOW 0x0003 /* Active low polarity */\n#define MP_IRQFLAG_EDGE 0x0004 /* Edge triggered */\n#define MP_IRQFLAG_LEVEL 0x000C /* Level triggered */\n\n/* Maximum entries */\n#define MAX_CPUS 256\n#define MAX_IOAPICS 8\n#define MAX_OVERRIDES 24\n#define MAX_BUS_ENTRIES 256\n#define MAX_PCI_BUSES 32\n\n/* Discovered PCI bus information */\nstruct pci_bus_info {\n uacpi_namespace_node *node; /* ACPI namespace node for the bus/bridge */\n uint8_t bus_num; /* PCI bus number (from _BBN or _ADR) */\n uint8_t mp_bus_id; /* MP table bus ID (assigned sequentially) */\n bool is_secondary; /* True if this is a secondary bus behind a bridge */\n};\n\nstatic struct {\n struct pci_bus_info buses[MAX_PCI_BUSES];\n size_t count;\n} discovered_pci_buses;\n\n/* Forward declaration for recursive walk */\nstatic void discover_secondary_buses(uacpi_namespace_node *parent, uint8_t parent_bus);\n\n/* Check if a PCI device exists by reading vendor ID via legacy PIO */\nstatic bool pci_device_exists(uint8_t bus, uint8_t dev, uint8_t func)\n{\n uint32_t addr = 0x80000000 | (bus << 16) | (dev << 11) | (func << 8);\n outl(0xCF8, addr);\n uint16_t vendor = inw(0xCFC);\n return vendor != 0xFFFF;\n}\n\n#pragma pack(1)\n\nstruct mptable_floating {\n uint32_t signature; /* \"_MP_\" */\n uint32_t physaddr; /* Physical address of MP config table */\n uint8_t length; /* Length in 16-byte units (1) */\n uint8_t spec_rev; /* MP spec revision (4 = 1.4) */\n uint8_t checksum; /* Checksum */\n uint8_t feature1; /* Feature byte 1 (0 = config table present) */\n uint8_t feature2; /* Feature byte 2 */\n uint8_t reserved[3];\n};\n\nstruct mptable_config {\n uint32_t signature; /* \"PCMP\" */\n uint16_t length; /* Base table length */\n uint8_t spec; /* MP spec revision */\n uint8_t checksum; /* Checksum */\n char oemid[8]; /* OEM ID */\n char productid[12]; /* Product ID */\n uint32_t oemptr; /* OEM table pointer */\n uint16_t oemsize; /* OEM table size */\n uint16_t entrycount; /* Number of entries */\n uint32_t lapic; /* Local APIC address */\n uint16_t exttable_length;\n uint8_t exttable_checksum;\n uint8_t reserved;\n};\n\nstruct mpt_cpu {\n uint8_t type; /* MPT_TYPE_CPU (0) */\n uint8_t apicid; /* Local APIC ID */\n uint8_t apicver; /* Local APIC version */\n uint8_t cpuflag; /* CPU flags: bit 0=enabled, bit 1=BSP */\n uint32_t cpusignature; /* CPU signature (from CPUID) */\n uint32_t featureflag; /* CPU feature flags (from CPUID) */\n uint32_t reserved[2];\n};\n\nstruct mpt_bus {\n uint8_t type; /* MPT_TYPE_BUS (1) */\n uint8_t busid; /* Bus ID */\n char bustype[6]; /* Bus type string: \"PCI \" or \"ISA \" */\n};\n\nstruct mpt_ioapic {\n uint8_t type; /* MPT_TYPE_IOAPIC (2) */\n uint8_t apicid; /* I/O APIC ID */\n uint8_t apicver; /* I/O APIC version */\n uint8_t flags; /* Flags: bit 0=enabled */\n uint32_t apicaddr; /* I/O APIC base address */\n};\n\nstruct mpt_intsrc {\n uint8_t type; /* MPT_TYPE_INTSRC (3) or MPT_TYPE_LOCAL_INT (4) */\n uint8_t irqtype; /* Interrupt type */\n uint16_t irqflag; /* Polarity and trigger mode */\n uint8_t srcbus; /* Source bus ID */\n uint8_t srcbusirq; /* Source bus IRQ */\n uint8_t dstapic; /* Destination I/O APIC ID */\n uint8_t dstirq; /* Destination I/O APIC input */\n};\n\n#pragma pack()\n\n/* Forward declaration */\nstatic uint8_t get_ioapic_input_count(uint32_t ioapic_addr);\n\n/* Parsed MADT data */\nstruct madt_data {\n struct {\n uint32_t apic_id;\n uint8_t enabled;\n uint8_t is_bsp;\n } cpus[MAX_CPUS];\n size_t cpu_count;\n\n struct {\n uint8_t id;\n uint32_t address;\n uint32_t gsi_base;\n uint8_t input_count; /* Number of interrupt inputs (from hardware) */\n } ioapics[MAX_IOAPICS];\n size_t ioapic_count;\n\n struct {\n uint8_t source_irq;\n uint32_t gsi;\n uint16_t flags;\n } overrides[MAX_OVERRIDES];\n size_t override_count;\n\n /* Local APIC NMI - we assume all CPUs use the same LINT for NMI */\n uint8_t nmi_lint; /* Which LINT pin receives NMI (0 or 1) */\n uint16_t nmi_flags;\n uint8_t has_nmi_info;\n};\n\n/* Compute checksum (sum of all bytes must be 0) */\nstatic uint8_t compute_checksum(void *data, size_t len)\n{\n uint8_t sum = 0;\n uint8_t *p = (uint8_t *)data;\n for (size_t i = 0; i < len; i++) {\n sum += p[i];\n }\n return sum;\n}\n\n/* Read BSP APIC ID from the running CPU's LAPIC ID register. */\nstatic uint32_t get_bsp_apic_id(void)\n{\n uint64_t apic_base = rdmsr(0x1b);\n if (apic_base & (1 << 10))\n return (uint32_t)rdmsr(0x802); /* x2APIC: IA32_X2APIC_APICID */\n uintptr_t lapic_addr = (uintptr_t)(apic_base & APIC_BASE_ADDR_MASK);\n volatile uint32_t *id_reg = (volatile uint32_t *)(lapic_addr + 0x20);\n return (*id_reg) >> 24;\n}\n\n/* Get CPU signature and features from CPUID */\nstatic void get_cpu_info(uint32_t *signature, uint32_t *features)\n{\n uint32_t eax, ebx, ecx, edx;\n __asm__ volatile (\"cpuid\" : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx) : \"a\"(1));\n *signature = eax;\n *features = edx;\n}\n\n/* Get Local APIC version */\nstatic uint8_t get_lapic_version(void)\n{\n uint64_t apic_base = rdmsr(0x1b);\n if (apic_base & (1 << 10)) /* x2APIC mode: use MSR 0x803 */\n return rdmsr(0x803) & 0xFF;\n uintptr_t lapic_addr = (uintptr_t)(apic_base & APIC_BASE_ADDR_MASK);\n volatile uint32_t *ver_reg = (volatile uint32_t *)(lapic_addr + 0x30);\n return (*ver_reg) & 0xFF;\n}\n\n/* Convert ACPI MADT flags to MP table flags */\nstatic uint16_t madt_flags_to_mp(uint16_t madt_flags)\n{\n uint16_t mp_flags = 0;\n\n /* Polarity */\n switch (madt_flags & ACPI_MADT_POLARITY_MASK) {\n case ACPI_MADT_POLARITY_ACTIVE_HIGH:\n mp_flags |= MP_IRQFLAG_ACTIVE_HIGH;\n break;\n case ACPI_MADT_POLARITY_ACTIVE_LOW:\n mp_flags |= MP_IRQFLAG_ACTIVE_LOW;\n break;\n default:\n /* Conforming - use bus default */\n mp_flags |= MP_IRQFLAG_CONFORM;\n break;\n }\n\n /* Trigger mode */\n switch (madt_flags & ACPI_MADT_TRIGGERING_MASK) {\n case ACPI_MADT_TRIGGERING_EDGE:\n mp_flags |= MP_IRQFLAG_EDGE;\n break;\n case ACPI_MADT_TRIGGERING_LEVEL:\n mp_flags |= MP_IRQFLAG_LEVEL;\n break;\n default:\n /* Conforming - use bus default */\n break;\n }\n\n return mp_flags;\n}\n\n/* Parse MADT and extract relevant information */\nstatic bool parse_madt(struct madt_data *data, int helper_apic_id)\n{\n struct uacpi_table madt_table;\n\n memset(data, 0, sizeof(*data));\n data->nmi_lint = 1; /* Default: LINT1 for NMI */\n\n if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table) != UACPI_STATUS_OK) {\n printf(\"mptable: MADT not found\\n\");\n return false;\n }\n\n struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;\n uint8_t *entry = (uint8_t *)(madt + 1);\n uint8_t *end = (uint8_t *)madt + madt->hdr.length;\n uint32_t bsp_id = get_bsp_apic_id();\n\n while (entry < end) {\n struct acpi_entry_hdr *hdr = (struct acpi_entry_hdr *)entry;\n if (hdr->length < 2) break;\n\n switch (hdr->type) {\n case ACPI_MADT_ENTRY_TYPE_LAPIC: {\n struct acpi_madt_lapic *lapic = (struct acpi_madt_lapic *)entry;\n\n /* Skip helper core */\n if ((int)lapic->id == helper_apic_id) {\n entry += hdr->length;\n continue;\n }\n\n /* Apply user allow/block list (BSP is always kept) */\n if (lapic->id != bsp_id && !config_cpu_in_filter(lapic->id)) {\n entry += hdr->length;\n continue;\n }\n\n if (data->cpu_count < MAX_CPUS && (lapic->flags & ACPI_PIC_ENABLED)) {\n data->cpus[data->cpu_count].apic_id = lapic->id;\n data->cpus[data->cpu_count].enabled = 1;\n data->cpus[data->cpu_count].is_bsp = (lapic->id == bsp_id) ? 1 : 0;\n data->cpu_count++;\n }\n break;\n }\n\n case ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC: {\n struct acpi_madt_x2apic *x2apic = (struct acpi_madt_x2apic *)entry;\n\n /* Skip helper core */\n if ((int)x2apic->id == helper_apic_id) {\n entry += hdr->length;\n continue;\n }\n\n /* MP table only supports 8-bit APIC IDs */\n if (x2apic->id > 255) {\n entry += hdr->length;\n continue;\n }\n\n /* Apply user allow/block list (BSP is always kept) */\n if (x2apic->id != bsp_id && !config_cpu_in_filter(x2apic->id)) {\n entry += hdr->length;\n continue;\n }\n\n if (data->cpu_count < MAX_CPUS && (x2apic->flags & ACPI_PIC_ENABLED)) {\n data->cpus[data->cpu_count].apic_id = x2apic->id;\n data->cpus[data->cpu_count].enabled = 1;\n data->cpus[data->cpu_count].is_bsp = (x2apic->id == bsp_id) ? 1 : 0;\n data->cpu_count++;\n }\n break;\n }\n\n case ACPI_MADT_ENTRY_TYPE_IOAPIC: {\n struct acpi_madt_ioapic *ioapic = (struct acpi_madt_ioapic *)entry;\n\n if (data->ioapic_count < MAX_IOAPICS) {\n data->ioapics[data->ioapic_count].id = ioapic->id;\n data->ioapics[data->ioapic_count].address = ioapic->address;\n data->ioapics[data->ioapic_count].gsi_base = ioapic->gsi_base;\n /* Read actual input count from hardware */\n data->ioapics[data->ioapic_count].input_count =\n get_ioapic_input_count(ioapic->address);\n data->ioapic_count++;\n }\n break;\n }\n\n case ACPI_MADT_ENTRY_TYPE_INTERRUPT_SOURCE_OVERRIDE: {\n struct acpi_madt_interrupt_source_override *iso =\n (struct acpi_madt_interrupt_source_override *)entry;\n\n if (data->override_count < MAX_OVERRIDES) {\n data->overrides[data->override_count].source_irq = iso->source;\n data->overrides[data->override_count].gsi = iso->gsi;\n data->overrides[data->override_count].flags = iso->flags;\n data->override_count++;\n }\n break;\n }\n\n case ACPI_MADT_ENTRY_TYPE_LAPIC_NMI: {\n struct acpi_madt_lapic_nmi *nmi = (struct acpi_madt_lapic_nmi *)entry;\n\n /* Use the first NMI entry we find (usually applies to all CPUs) */\n if (!data->has_nmi_info) {\n data->nmi_lint = nmi->lint & 1;\n data->nmi_flags = nmi->flags;\n data->has_nmi_info = 1;\n }\n break;\n }\n\n default:\n break;\n }\n\n entry += hdr->length;\n }\n\n uacpi_table_unref(&madt_table);\n\n /* Compute total GSI count */\n uint32_t total_gsis = 0;\n for (size_t i = 0; i < data->ioapic_count; i++) {\n total_gsis += data->ioapics[i].input_count;\n }\n\n printf(\"mptable: %zu CPUs, %zu I/O APIC(s) (%u GSIs), %zu overrides\\n\",\n data->cpu_count, data->ioapic_count, total_gsis, data->override_count);\n\n return data->cpu_count > 0 && data->ioapic_count > 0;\n}\n\n/* Find which I/O APIC handles a given GSI */\nstatic int find_ioapic_for_gsi(struct madt_data *data, uint32_t gsi, uint8_t *dstirq)\n{\n for (size_t i = 0; i < data->ioapic_count; i++) {\n /* Use actual input count read from hardware */\n if (gsi >= data->ioapics[i].gsi_base &&\n gsi < data->ioapics[i].gsi_base + data->ioapics[i].input_count) {\n *dstirq = gsi - data->ioapics[i].gsi_base;\n return data->ioapics[i].id;\n }\n }\n return -1;\n}\n\n/* Read I/O APIC register */\nstatic uint32_t ioapic_read(uint32_t ioapic_addr, uint8_t reg)\n{\n volatile uint32_t *ioregsel = (volatile uint32_t *)(uintptr_t)ioapic_addr;\n volatile uint32_t *iowin = (volatile uint32_t *)(uintptr_t)(ioapic_addr + 0x10);\n\n *ioregsel = reg;\n return *iowin;\n}\n\n/* Get I/O APIC version from its registers */\nstatic uint8_t get_ioapic_version(uint32_t ioapic_addr)\n{\n return ioapic_read(ioapic_addr, 0x01) & 0xFF;\n}\n\n/* Get I/O APIC input count from its registers */\nstatic uint8_t get_ioapic_input_count(uint32_t ioapic_addr)\n{\n /* IOAPICVER register (0x01): bits [23:16] = max redirection entry */\n uint32_t ver = ioapic_read(ioapic_addr, 0x01);\n uint8_t max_redir = (ver >> 16) & 0xFF;\n return max_redir + 1; /* Input count = max redirection entry + 1 */\n}\n\n/* Context for IRQ resource iteration */\nstruct irq_find_ctx {\n int32_t gsi; /* Output: found GSI, or -1 if not found */\n uint16_t flags; /* Output: ACPI interrupt flags */\n};\n\n/* Convert uACPI resource flags to ACPI MADT interrupt flags format */\nstatic uint16_t uacpi_flags_to_madt(uint8_t triggering, uint8_t polarity)\n{\n uint16_t flags = 0;\n flags |= polarity ? ACPI_MADT_POLARITY_ACTIVE_LOW : ACPI_MADT_POLARITY_ACTIVE_HIGH;\n flags |= triggering ? ACPI_MADT_TRIGGERING_EDGE : ACPI_MADT_TRIGGERING_LEVEL;\n return flags;\n}\n\n/* Callback to find IRQ in resource list */\nstatic uacpi_iteration_decision find_irq_callback(void *user, uacpi_resource *resource)\n{\n struct irq_find_ctx *ctx = (struct irq_find_ctx *)user;\n\n if (resource->type == UACPI_RESOURCE_TYPE_IRQ) {\n if (resource->irq.num_irqs > 0) {\n ctx->gsi = resource->irq.irqs[0];\n ctx->flags = uacpi_flags_to_madt(resource->irq.triggering, resource->irq.polarity);\n return UACPI_ITERATION_DECISION_BREAK;\n }\n } else if (resource->type == UACPI_RESOURCE_TYPE_EXTENDED_IRQ) {\n if (resource->extended_irq.num_irqs > 0) {\n ctx->gsi = resource->extended_irq.irqs[0];\n ctx->flags = uacpi_flags_to_madt(resource->extended_irq.triggering, resource->extended_irq.polarity);\n return UACPI_ITERATION_DECISION_BREAK;\n }\n }\n\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\n/* Get GSI from a PCI interrupt link device by evaluating _CRS */\nstatic int32_t get_link_device_gsi(uacpi_namespace_node *link, uint16_t *out_flags)\n{\n struct irq_find_ctx ctx = { .gsi = -1, .flags = 0 };\n\n uacpi_status status = uacpi_for_each_device_resource(\n link, \"_CRS\", find_irq_callback, &ctx);\n\n if (status != UACPI_STATUS_OK && status != UACPI_STATUS_NOT_FOUND) {\n return -1;\n }\n\n if (out_flags && ctx.gsi >= 0) {\n *out_flags = ctx.flags;\n }\n\n return ctx.gsi;\n}\n\n/* Callback for discovering PCI root bridges */\nstatic uacpi_iteration_decision discover_pci_bus_callback(\n void *user, uacpi_namespace_node *node, uacpi_u32 depth)\n{\n (void)user;\n (void)depth;\n\n if (discovered_pci_buses.count >= MAX_PCI_BUSES) {\n printf(\"mptable: too many PCI buses, skipping additional bridges\\n\");\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n /* Get bus number from _BBN (Base Bus Number), defaults to 0 if not present */\n uacpi_u64 bus_num = 0;\n uacpi_eval_integer(node, \"_BBN\", UACPI_NULL, &bus_num);\n\n /* Check if we already have this bus number (some systems have duplicate entries) */\n for (size_t i = 0; i < discovered_pci_buses.count; i++) {\n if (discovered_pci_buses.buses[i].bus_num == (uint8_t)bus_num) {\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n }\n\n discovered_pci_buses.buses[discovered_pci_buses.count].node = node;\n discovered_pci_buses.buses[discovered_pci_buses.count].bus_num = (uint8_t)bus_num;\n /* mp_bus_id will be assigned later when creating bus entries */\n discovered_pci_buses.count++;\n\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\n/* Callback for finding secondary buses with _PRT under a bridge */\nstatic uacpi_iteration_decision discover_secondary_callback(\n void *user, uacpi_namespace_node *node, uacpi_u32 node_depth)\n{\n (void)node_depth;\n uint8_t parent_bus = *(uint8_t *)user;\n\n if (discovered_pci_buses.count >= MAX_PCI_BUSES) {\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n /* Check if this node has a _PRT method (indicates it routes interrupts for a bus) */\n uacpi_namespace_node *prt_node = UACPI_NULL;\n uacpi_status st = uacpi_namespace_node_find(node, \"_PRT\", &prt_node);\n if (st != UACPI_STATUS_OK || !prt_node) {\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n /* Get _ADR to check if this is a PCI device */\n uacpi_u64 adr = 0;\n if (uacpi_eval_integer(node, \"_ADR\", UACPI_NULL, &adr) != UACPI_STATUS_OK) {\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n /* _ADR format: high word = device, low word = function */\n uint8_t dev = (adr >> 16) & 0x1F;\n uint8_t func = adr & 0x7;\n\n /* Verify device actually exists in PCI config space */\n if (!pci_device_exists(parent_bus, dev, func)) {\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n /* This is a PCI bridge with its own _PRT - add as secondary bus */\n discovered_pci_buses.buses[discovered_pci_buses.count].node = node;\n /* Secondary bus number isn't directly available, but we can use a placeholder\n * since what matters for interrupt routing is the MP bus ID mapping */\n discovered_pci_buses.buses[discovered_pci_buses.count].bus_num = 0xFF; /* Unknown */\n discovered_pci_buses.buses[discovered_pci_buses.count].is_secondary = true;\n discovered_pci_buses.count++;\n\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\n/* Walk namespace under a root bridge to find secondary buses */\nstatic void discover_secondary_buses(uacpi_namespace_node *root_bridge, uint8_t parent_bus)\n{\n /* Walk children looking for bridges with _PRT */\n uacpi_namespace_for_each_child(\n root_bridge,\n discover_secondary_callback, /* descending callback */\n UACPI_NULL, /* ascending callback (not needed) */\n UACPI_OBJECT_DEVICE_BIT, /* type mask - only devices */\n 3, /* Max depth - look 3 levels deep for nested bridges */\n &parent_bus /* user data */\n );\n}\n\n/* Discover all PCI root bridges via ACPI */\nstatic void discover_pci_buses(void)\n{\n discovered_pci_buses.count = 0;\n\n uacpi_namespace_node *sb_node = uacpi_namespace_get_predefined(UACPI_PREDEFINED_NAMESPACE_SB);\n if (!sb_node) {\n printf(\"mptable: _SB not found, cannot discover PCI buses\\n\");\n return;\n }\n\n /* Search for PCI and PCIe root bridges */\n const uacpi_char *hids[] = { \"PNP0A03\", \"PNP0A08\", UACPI_NULL };\n uacpi_find_devices_at(sb_node, hids, discover_pci_bus_callback, UACPI_NULL);\n\n size_t root_count = discovered_pci_buses.count;\n\n /* Walk each root bridge to find secondary buses with their own _PRT */\n for (size_t i = 0; i < root_count; i++) {\n discover_secondary_buses(\n discovered_pci_buses.buses[i].node,\n discovered_pci_buses.buses[i].bus_num\n );\n }\n\n size_t secondary_count = discovered_pci_buses.count - root_count;\n if (secondary_count > 0) {\n printf(\"mptable: discovered %zu root + %zu secondary PCI buses\\n\",\n root_count, secondary_count);\n } else {\n printf(\"mptable: discovered %zu PCI root bridge(s)\\n\", root_count);\n }\n}\n\n/* Build the MP table */\nbool mptable_init(struct csmwrap_priv *priv)\n{\n struct madt_data madt;\n int helper_apic_id = bios_proxy_get_helper_apic_id();\n\n printf(\"mptable: building MP table (excluding helper core APIC ID %d)\\n\", helper_apic_id);\n\n /* MP spec 1.4 fields are 8-bit; an unrepresentable BSP makes the whole\n * table malformed (no BSP marker, misrouted local interrupts). */\n uint32_t bsp_id = get_bsp_apic_id();\n if (bsp_id > 255) {\n printf(\"mptable: BSP APIC ID %u exceeds 8-bit limit, skipping MP table\\n\", bsp_id);\n return false;\n }\n\n /* config->lapic is a 32-bit field. */\n uint64_t lapic_phys_base = rdmsr(0x1b) & APIC_BASE_ADDR_MASK;\n if (lapic_phys_base > 0xFFFFFFFF) {\n printf(\"mptable: LAPIC base 0x%llx exceeds 32-bit MP table field, skipping MP table\\n\",\n (unsigned long long)lapic_phys_base);\n return false;\n }\n\n if (!parse_madt(&madt, helper_apic_id)) {\n printf(\"mptable: failed to parse MADT, skipping MP table\\n\");\n return false;\n }\n\n /* Discover PCI root bridges via ACPI */\n discover_pci_buses();\n\n /* Get CPU info from CPUID */\n uint32_t cpu_signature, cpu_features;\n get_cpu_info(&cpu_signature, &cpu_features);\n uint8_t lapic_version = get_lapic_version();\n\n /* Ensure at least one PCI bus for backwards compatibility */\n size_t pci_bus_count = discovered_pci_buses.count > 0 ? discovered_pci_buses.count : 1;\n\n /*\n * Calculate table size:\n * - Config header\n * - CPU entries\n * - Bus entries (N PCI buses + 1 ISA)\n * - I/O APIC entries\n * - ISA interrupt entries (16)\n * - PCI interrupt entries (up to 128 per bus * N buses)\n * - Local interrupt entries (2: ExtINT + NMI)\n */\n size_t table_size = sizeof(struct mptable_config) +\n madt.cpu_count * sizeof(struct mpt_cpu) +\n (pci_bus_count + 1) * sizeof(struct mpt_bus) +\n madt.ioapic_count * sizeof(struct mpt_ioapic) +\n (16 + 128 * pci_bus_count + 2) * sizeof(struct mpt_intsrc);\n\n /* Allocate table anywhere below 4GB - SeaBIOS will relocate it to F-segment */\n size_t total_size = sizeof(struct mptable_floating) + table_size;\n EFI_PHYSICAL_ADDRESS table_addr = 0xFFFFFFFF;\n\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress,\n EfiLoaderCode,\n (total_size + 4095) / 4096,\n &table_addr\n );\n\n if (EFI_ERROR(status)) {\n printf(\"mptable: failed to allocate memory\\n\");\n return false;\n }\n\n /* Pass address to SeaBIOS via boot table */\n priv->low_stub->boot_table.MpTable = (uint32_t)table_addr;\n\n memset((void *)(uintptr_t)table_addr, 0, total_size);\n\n /* Build config table first, then floating pointer */\n struct mptable_config *config = (struct mptable_config *)(uintptr_t)(table_addr + sizeof(struct mptable_floating));\n uint8_t *entry_ptr = (uint8_t *)(config + 1);\n uint8_t *entry_end = (uint8_t *)(uintptr_t)(table_addr + total_size);\n uint16_t entry_count = 0;\n\n /* Config header */\n config->signature = MPCONFIG_SIGNATURE;\n config->spec = 4; /* MP spec 1.4 */\n memcpy(config->oemid, \"CSMWRAP \", 8);\n memcpy(config->productid, \"MP TABLE \", 12);\n config->lapic = (uint32_t)lapic_phys_base;\n\n /* CPU entries */\n for (size_t i = 0; i < madt.cpu_count; i++) {\n struct mpt_cpu *cpu = (struct mpt_cpu *)entry_ptr;\n cpu->type = MPT_TYPE_CPU;\n cpu->apicid = madt.cpus[i].apic_id;\n cpu->apicver = lapic_version;\n cpu->cpuflag = madt.cpus[i].enabled ? 0x01 : 0x00;\n if (madt.cpus[i].is_bsp) cpu->cpuflag |= 0x02;\n cpu->cpusignature = cpu_signature;\n cpu->featureflag = cpu_features;\n entry_ptr += sizeof(struct mpt_cpu);\n entry_count++;\n }\n\n /* Bus entries: PCI buses */\n uint8_t next_bus_id = 0;\n\n if (discovered_pci_buses.count > 0) {\n /* Create bus entries for all discovered PCI buses */\n for (size_t i = 0; i < discovered_pci_buses.count; i++) {\n struct mpt_bus *pci_bus = (struct mpt_bus *)entry_ptr;\n pci_bus->type = MPT_TYPE_BUS;\n pci_bus->busid = next_bus_id;\n memcpy(pci_bus->bustype, \"PCI \", 6);\n entry_ptr += sizeof(struct mpt_bus);\n entry_count++;\n\n /* Store the MP bus ID for _PRT processing later */\n discovered_pci_buses.buses[i].mp_bus_id = next_bus_id;\n next_bus_id++;\n }\n } else {\n /* Fallback: create at least one PCI bus entry */\n struct mpt_bus *pci_bus = (struct mpt_bus *)entry_ptr;\n pci_bus->type = MPT_TYPE_BUS;\n pci_bus->busid = next_bus_id;\n memcpy(pci_bus->bustype, \"PCI \", 6);\n entry_ptr += sizeof(struct mpt_bus);\n entry_count++;\n next_bus_id++;\n }\n\n /* Bus entries: ISA bus (always last) */\n uint8_t isa_bus_id = next_bus_id;\n struct mpt_bus *isa_bus = (struct mpt_bus *)entry_ptr;\n isa_bus->type = MPT_TYPE_BUS;\n isa_bus->busid = isa_bus_id;\n memcpy(isa_bus->bustype, \"ISA \", 6);\n entry_ptr += sizeof(struct mpt_bus);\n entry_count++;\n\n /* I/O APIC entries */\n for (size_t i = 0; i < madt.ioapic_count; i++) {\n struct mpt_ioapic *ioapic = (struct mpt_ioapic *)entry_ptr;\n ioapic->type = MPT_TYPE_IOAPIC;\n ioapic->apicid = madt.ioapics[i].id;\n ioapic->apicver = get_ioapic_version(madt.ioapics[i].address);\n ioapic->flags = 0x01; /* Enabled */\n ioapic->apicaddr = madt.ioapics[i].address;\n entry_ptr += sizeof(struct mpt_ioapic);\n entry_count++;\n }\n\n /* ISA interrupt entries (IRQ 0-15) */\n for (int irq = 0; irq < 16; irq++) {\n uint32_t gsi = irq; /* Default: identity mapping */\n uint16_t flags = MP_IRQFLAG_CONFORM; /* Default: conforms to bus spec */\n\n /* Check for override */\n for (size_t j = 0; j < madt.override_count; j++) {\n if (madt.overrides[j].source_irq == irq) {\n gsi = madt.overrides[j].gsi;\n flags = madt_flags_to_mp(madt.overrides[j].flags);\n break;\n }\n }\n\n uint8_t dstirq;\n int ioapic_id = find_ioapic_for_gsi(&madt, gsi, &dstirq);\n if (ioapic_id < 0) continue;\n\n struct mpt_intsrc *intsrc = (struct mpt_intsrc *)entry_ptr;\n intsrc->type = MPT_TYPE_INTSRC;\n intsrc->irqtype = MP_INT_TYPE_INT;\n intsrc->irqflag = flags;\n intsrc->srcbus = isa_bus_id;\n intsrc->srcbusirq = irq;\n intsrc->dstapic = ioapic_id;\n intsrc->dstirq = dstirq;\n entry_ptr += sizeof(struct mpt_intsrc);\n entry_count++;\n }\n\n /* PCI interrupt entries - from ACPI _PRT (PCI Routing Table) */\n /* Process _PRT for each discovered PCI root bridge */\n for (size_t bus_idx = 0; bus_idx < discovered_pci_buses.count; bus_idx++) {\n struct pci_bus_info *bus_info = &discovered_pci_buses.buses[bus_idx];\n\n uacpi_pci_routing_table *prt = NULL;\n uacpi_status prt_status = uacpi_get_pci_routing_table(bus_info->node, &prt);\n if (prt_status != UACPI_STATUS_OK || !prt) continue;\n\n for (size_t i = 0; i < prt->num_entries; i++) {\n if (entry_ptr + sizeof(struct mpt_intsrc) > entry_end) {\n printf(\"mptable: table full, truncating PCI interrupt entries\\n\");\n goto prt_done;\n }\n uacpi_pci_routing_table_entry *e = &prt->entries[i];\n int32_t gsi;\n uint16_t acpi_flags = 0;\n\n if (e->source == NULL) {\n /* Static routing: index is the GSI directly */\n gsi = e->index;\n } else {\n /* Dynamic routing: evaluate link device's _CRS */\n gsi = get_link_device_gsi(e->source, &acpi_flags);\n if (gsi < 0) continue;\n }\n\n /* Find which I/O APIC handles this GSI */\n uint8_t dstirq;\n int ioapic_id = find_ioapic_for_gsi(&madt, gsi, &dstirq);\n if (ioapic_id < 0) continue;\n\n /* _PRT address format: high word = device, low word = function (0xFFFF = any) */\n uint8_t dev = (e->address >> 16) & 0x1F;\n\n /* Convert ACPI flags to MP flags, default to PCI standard if not specified */\n uint16_t mp_flags;\n if (acpi_flags) {\n mp_flags = madt_flags_to_mp(acpi_flags);\n } else {\n mp_flags = MP_IRQFLAG_ACTIVE_LOW | MP_IRQFLAG_LEVEL; /* PCI default */\n }\n\n struct mpt_intsrc *intsrc = (struct mpt_intsrc *)entry_ptr;\n intsrc->type = MPT_TYPE_INTSRC;\n intsrc->irqtype = MP_INT_TYPE_INT;\n intsrc->irqflag = mp_flags;\n intsrc->srcbus = bus_info->mp_bus_id; /* Use the correct MP bus ID */\n intsrc->srcbusirq = (dev << 2) | e->pin; /* MP spec: (dev << 2) | pin */\n intsrc->dstapic = ioapic_id;\n intsrc->dstirq = dstirq;\n entry_ptr += sizeof(struct mpt_intsrc);\n entry_count++;\n }\n\n uacpi_free_pci_routing_table(prt);\n }\nprt_done:\n\n /* Local interrupt entries */\n /* ExtINT on the LINT pin opposite NMI, BSP only (8259 wired to BSP). */\n uint8_t bsp_apic_id = (uint8_t)bsp_id; /* range-checked at function entry */\n uint8_t extint_lint = madt.nmi_lint ^ 1;\n struct mpt_intsrc *extint = (struct mpt_intsrc *)entry_ptr;\n extint->type = MPT_TYPE_LOCAL_INT;\n extint->irqtype = MP_INT_TYPE_EXTINT;\n extint->irqflag = MP_IRQFLAG_CONFORM;\n extint->srcbus = isa_bus_id;\n extint->srcbusirq = 0;\n extint->dstapic = bsp_apic_id;\n extint->dstirq = extint_lint;\n entry_ptr += sizeof(struct mpt_intsrc);\n entry_count++;\n\n /* NMI on LINT1 (or whatever MADT specified) */\n struct mpt_intsrc *nmi = (struct mpt_intsrc *)entry_ptr;\n nmi->type = MPT_TYPE_LOCAL_INT;\n nmi->irqtype = MP_INT_TYPE_NMI;\n nmi->irqflag = madt.has_nmi_info ? madt_flags_to_mp(madt.nmi_flags) : MP_IRQFLAG_CONFORM;\n nmi->srcbus = isa_bus_id;\n nmi->srcbusirq = 0;\n nmi->dstapic = 0xFF; /* All local APICs */\n nmi->dstirq = madt.nmi_lint;\n entry_ptr += sizeof(struct mpt_intsrc);\n entry_count++;\n\n /* Finalize config table */\n config->entrycount = entry_count;\n config->length = (uint16_t)((uintptr_t)entry_ptr - (uintptr_t)config);\n config->checksum = 0;\n config->checksum = -compute_checksum(config, config->length);\n\n /* Build floating pointer structure */\n struct mptable_floating *floating = (struct mptable_floating *)(uintptr_t)table_addr;\n floating->signature = MPTABLE_SIGNATURE;\n floating->physaddr = (uint32_t)(uintptr_t)config;\n floating->length = 1; /* 16 bytes */\n floating->spec_rev = 4; /* MP spec 1.4 */\n floating->feature1 = 0; /* Config table present */\n floating->feature2 = 0;\n floating->checksum = 0;\n floating->checksum = -compute_checksum(floating, sizeof(*floating));\n\n printf(\"mptable: built at 0x%lx, %u entries, %u bytes\\n\",\n (unsigned long)table_addr, entry_count, config->length);\n\n return true;\n}\n" }, { "path": "src/mptable.h", "content": "/*\n * MP Table Generation from ACPI\n *\n * Generates Intel MultiProcessor Specification tables from ACPI MADT\n * for legacy BIOS compatibility.\n */\n\n#ifndef _MPTABLE_H\n#define _MPTABLE_H\n\n#include \n#include \n\nstruct csmwrap_priv;\n\n/*\n * Initialize and build MP tables from ACPI MADT.\n *\n * @param priv CSMWrap private data structure\n * @return true on success, false on failure\n */\nbool mptable_init(struct csmwrap_priv *priv);\n\n#endif /* _MPTABLE_H */\n" }, { "path": "src/oprom.c", "content": "#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Option ROM alignment - must match SeaBIOS OPTION_ROM_ALIGN (2048) */\n#define OPTION_ROM_ALIGN 2048\n\nEFI_STATUS\nGetPciLegacyRom(\n IN UINT16 Csm16Revision,\n IN UINT16 VendorId,\n IN UINT16 DeviceId,\n IN OUT VOID **Rom,\n IN OUT UINTN *ImageSize,\n OUT UINTN *MaxRuntimeImageLength, OPTIONAL\n OUT UINT8 *OpRomRevision, OPTIONAL\n OUT VOID **ConfigUtilityCodeHeader OPTIONAL\n)\n{\n BOOLEAN Match;\n UINT16 *DeviceIdList;\n EFI_PCI_ROM_HEADER RomHeader;\n PCI_3_0_DATA_STRUCTURE *Pcir;\n VOID *BackupImage;\n VOID *BestImage;\n\n if (*ImageSize < sizeof(EFI_PCI_ROM_HEADER)) {\n return EFI_NOT_FOUND;\n }\n\n BestImage = NULL;\n BackupImage = NULL;\n RomHeader.Raw = *Rom;\n while (RomHeader.Generic->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\n if (RomHeader.Generic->PcirOffset == 0 ||\n (RomHeader.Generic->PcirOffset & 3) != 0 ||\n *ImageSize < RomHeader.Raw - (UINT8 *)*Rom + RomHeader.Generic->PcirOffset + sizeof(PCI_DATA_STRUCTURE)) {\n break;\n }\n\n Pcir = (PCI_3_0_DATA_STRUCTURE *)(RomHeader.Raw + RomHeader.Generic->PcirOffset);\n if (Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {\n break;\n }\n\n if (((UINTN)RomHeader.Raw - (UINTN)*Rom) + Pcir->ImageLength * 512 > *ImageSize) {\n break;\n }\n\n if (Pcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {\n Match = FALSE;\n if (Pcir->VendorId == VendorId) {\n if (Pcir->DeviceId == DeviceId) {\n Match = TRUE;\n } else if ((Pcir->Revision >= 3) && (Pcir->DeviceListOffset != 0)) {\n DeviceIdList = (UINT16 *)(((UINT8 *)Pcir) + Pcir->DeviceListOffset);\n while (*DeviceIdList != 0) {\n if (*DeviceIdList == DeviceId) {\n Match = TRUE;\n break;\n }\n DeviceIdList++;\n }\n }\n }\n\n if (Match) {\n if (Csm16Revision >= 0x0300) {\n if (Pcir->Revision >= 3) {\n BestImage = RomHeader.Raw;\n break;\n } else {\n BackupImage = RomHeader.Raw;\n }\n } else {\n if (Pcir->Revision >= 3) {\n BackupImage = RomHeader.Raw;\n } else {\n BestImage = RomHeader.Raw;\n break;\n }\n }\n }\n }\n\n if ((Pcir->Indicator & 0x80) == 0x80) {\n break;\n } else {\n RomHeader.Raw += 512 * Pcir->ImageLength;\n }\n }\n\n if (BestImage == NULL) {\n if (BackupImage == NULL) {\n return EFI_NOT_FOUND;\n }\n BestImage = BackupImage;\n }\n\n RomHeader.Raw = BestImage;\n Pcir = (PCI_3_0_DATA_STRUCTURE *)(RomHeader.Raw + RomHeader.Generic->PcirOffset);\n *Rom = BestImage;\n *ImageSize = Pcir->ImageLength * 512;\n\n if (MaxRuntimeImageLength != NULL) {\n if (Pcir->Revision < 3) {\n *MaxRuntimeImageLength = 0;\n } else {\n *MaxRuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;\n }\n }\n\n if (OpRomRevision != NULL) {\n if (Pcir->Length >= 0x1C) {\n *OpRomRevision = Pcir->Revision;\n } else {\n *OpRomRevision = 0;\n }\n }\n\n if (ConfigUtilityCodeHeader != NULL) {\n if ((Pcir->Revision < 3) || (Pcir->ConfigUtilityCodeHeaderOffset == 0)) {\n *ConfigUtilityCodeHeader = NULL;\n } else {\n *ConfigUtilityCodeHeader = RomHeader.Raw + Pcir->ConfigUtilityCodeHeaderOffset;\n }\n }\n\n return EFI_SUCCESS;\n}\n\nvoid oprom_enumerate(struct csmwrap_priv *priv, struct pci_oprom_list *list)\n{\n EFI_STATUS Status;\n EFI_HANDLE *HandleBuffer;\n UINTN HandleCount;\n EFI_GUID PciIoGuid = EFI_PCI_IO_PROTOCOL_GUID;\n\n list->count = 0;\n\n Status = gBS->LocateHandleBuffer(ByProtocol, &PciIoGuid, NULL,\n &HandleCount, &HandleBuffer);\n if (EFI_ERROR(Status))\n return;\n\n for (UINTN i = 0; i < HandleCount && list->count < MAX_PCI_OPROMS; i++) {\n EFI_PCI_IO_PROTOCOL *PciIo;\n Status = gBS->HandleProtocol(HandleBuffer[i], &PciIoGuid, (VOID **)&PciIo);\n if (EFI_ERROR(Status))\n continue;\n\n /* Skip devices without option ROMs */\n if (!PciIo->RomImage || !PciIo->RomSize)\n continue;\n\n /* Read PCI config header */\n PCI_TYPE00 PciConfig;\n Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0,\n sizeof(PciConfig) / sizeof(UINT32), &PciConfig);\n if (EFI_ERROR(Status))\n continue;\n\n /* Skip VGA devices - handled separately by the video path */\n if (PciConfig.Hdr.ClassCode[2] == PCI_CLASS_DISPLAY)\n continue;\n\n /* Skip the VGA device explicitly by BDF too, in case class doesn't match */\n UINTN Seg, Bus, Device, Function;\n PciIo->GetLocation(PciIo, &Seg, &Bus, &Device, &Function);\n uint8_t devfn = (uint8_t)((Device << 3) | Function);\n if ((uint8_t)Bus == priv->vga_pci_bus && devfn == priv->vga_pci_devfn)\n continue;\n\n /* Try to extract an x86 PC-AT legacy ROM image */\n VOID *RomImage = PciIo->RomImage;\n UINTN RomSize = (UINTN)PciIo->RomSize;\n Status = GetPciLegacyRom(0x0300,\n PciConfig.Hdr.VendorId,\n PciConfig.Hdr.DeviceId,\n &RomImage, &RomSize,\n NULL, NULL, NULL);\n if (EFI_ERROR(Status))\n continue;\n\n struct pci_oprom_info *entry = &list->entries[list->count];\n entry->bus = (uint8_t)Bus;\n entry->devfn = devfn;\n entry->vendor_id = PciConfig.Hdr.VendorId;\n entry->device_id = PciConfig.Hdr.DeviceId;\n entry->class_code = PciConfig.Hdr.ClassCode[2];\n entry->rom_image = RomImage;\n entry->rom_size = RomSize;\n list->count++;\n\n printf(\"OpROM: %02x:%02x.%x %04x:%04x class %02x (%u bytes)\\n\",\n (uint8_t)Bus, (uint8_t)Device, (uint8_t)Function,\n PciConfig.Hdr.VendorId, PciConfig.Hdr.DeviceId,\n PciConfig.Hdr.ClassCode[2], (unsigned)RomSize);\n }\n\n gBS->FreePool(HandleBuffer);\n\n if (list->count > 0)\n printf(\"Found %zu non-VGA option ROM(s)\\n\", list->count);\n else\n printf(\"No non-VGA option ROMs found\\n\");\n}\n\nvoid oprom_dispatch_all(struct csmwrap_priv *priv, struct pci_oprom_list *list)\n{\n if (list->count == 0)\n return;\n\n /*\n * ROM placement watermark. With a VBIOS, non-VGA ROMs start just past it.\n * With no VBIOS (e.g. headless system), skip the canonical VGA region so\n * non-VGA ROMs never land at 0xC0000 where firmware expects a VGA OpROM.\n */\n uintptr_t rom_watermark = VGABIOS_END;\n if (vbios_loc != NULL)\n rom_watermark = ALIGN_UP(VGABIOS_START + vbios_size, OPTION_ROM_ALIGN);\n\n for (size_t i = 0; i < list->count; i++) {\n struct pci_oprom_info *info = &list->entries[i];\n uintptr_t rom_size_aligned = ALIGN_UP(info->rom_size, OPTION_ROM_ALIGN);\n\n /* Check available space (must not collide with SeaBIOS CSM binary) */\n if (rom_watermark + rom_size_aligned > priv->csm_bin_base) {\n printf(\"OpROM: no space for %04x:%04x (need 0x%x, have 0x%x)\\n\",\n info->vendor_id, info->device_id,\n (unsigned)rom_size_aligned,\n (unsigned)(priv->csm_bin_base - rom_watermark));\n continue;\n }\n\n /* Copy ROM image to shadow RAM */\n memcpy((void *)rom_watermark, info->rom_image, info->rom_size);\n /* Zero-pad to alignment boundary */\n if (info->rom_size < rom_size_aligned)\n memset((void *)(rom_watermark + info->rom_size), 0,\n rom_size_aligned - info->rom_size);\n\n /* Fill the dispatch table */\n EFI_DISPATCH_OPROM_TABLE *table = &priv->low_stub->oprom_table;\n memset(table, 0, sizeof(*table));\n table->OpromSegment = (UINT16)(rom_watermark >> 4);\n table->PciBus = info->bus;\n table->PciDeviceFunction = info->devfn;\n table->NumberBbsEntries = (UINT8)priv->low_stub->bbs_entry_count;\n table->BbsTablePointer = (UINT32)(uintptr_t)priv->low_stub->bbs_entries;\n\n printf(\"OpROM: dispatching %04x:%04x at seg %04x (%u bytes)\\n\",\n info->vendor_id, info->device_id,\n table->OpromSegment, (unsigned)info->rom_size);\n\n pci_enable_for_oprom(info->bus, info->devfn);\n\n EFI_IA32_REGISTER_SET Regs;\n memset(&Regs, 0, sizeof(Regs));\n Regs.X.AX = Legacy16DispatchOprom;\n Regs.X.ES = EFI_SEGMENT(table);\n Regs.X.BX = EFI_OFFSET(table);\n LegacyBiosFarCall86(priv->csm_efi_table->Compatibility16CallSegment,\n priv->csm_efi_table->Compatibility16CallOffset,\n &Regs, NULL, 0);\n\n printf(\"OpROM: dispatch returned AX=%04x BX=%04x\\n\",\n Regs.X.AX, Regs.X.BX);\n\n rom_watermark += rom_size_aligned;\n }\n}\n" }, { "path": "src/oprom.h", "content": "#ifndef OPROM_H\n#define OPROM_H\n\n#include \n#include \n#include \n#include \n\n#define MAX_PCI_OPROMS 16\n\nstruct pci_oprom_info {\n uint8_t bus;\n uint8_t devfn; /* (device << 3) | function */\n uint16_t vendor_id;\n uint16_t device_id;\n uint8_t class_code; /* PCI base class */\n void *rom_image; /* Pointer to x86 PC-AT ROM image */\n size_t rom_size; /* Size of the x86 image in bytes */\n};\n\nstruct pci_oprom_list {\n size_t count;\n struct pci_oprom_info entries[MAX_PCI_OPROMS];\n};\n\n/*\n * Enumerate all PCI devices with legacy x86 option ROMs (excluding VGA).\n * Must be called before ExitBootServices (requires EFI_PCI_IO_PROTOCOL).\n */\nvoid oprom_enumerate(struct csmwrap_priv *priv, struct pci_oprom_list *list);\n\n/*\n * Dispatch all enumerated option ROMs via Legacy16DispatchOprom.\n * Must be called after Legacy16InitializeYourself and after the VGA oprom\n * dispatch, but before Legacy16UpdateBbs.\n */\nvoid oprom_dispatch_all(struct csmwrap_priv *priv, struct pci_oprom_list *list);\n\n/*\n * Extract the x86 PC-AT legacy ROM image from a PCI ROM bundle.\n * The ROM bundle may contain multiple images (x86, EFI, OpenFirmware).\n * On success, *Rom and *ImageSize are updated to point to the x86 image.\n */\nEFI_STATUS GetPciLegacyRom(\n UINT16 Csm16Revision,\n UINT16 VendorId,\n UINT16 DeviceId,\n VOID **Rom,\n UINTN *ImageSize,\n UINTN *MaxRuntimeImageLength,\n UINT8 *OpRomRevision,\n VOID **ConfigUtilityCodeHeader\n);\n\n#endif\n" }, { "path": "src/pci.c", "content": "#define FLANTERM_IN_FLANTERM\n\n#include \n#include \n#include \n#include \n#include \n#include \n\nextern struct flanterm_context *flanterm_ctx;\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n// ECAM (Enhanced Configuration Access Mechanism) support\n// ECAM maps PCI config space to memory: base + (bus << 20) + (dev << 15) + (func << 12) + offset\n\n#define ECAM_MAX_REGIONS 16\n\nstruct ecam_region {\n uint64_t base; // MMIO base address\n uint16_t segment; // PCI segment\n uint8_t start_bus; // First bus number covered\n uint8_t end_bus; // Last bus number covered\n};\n\nstatic struct ecam_region ecam_regions[ECAM_MAX_REGIONS];\nstatic size_t ecam_region_count = 0;\n\n// Find ECAM region for a given segment and bus\nstatic struct ecam_region *find_ecam_region(uint16_t segment, uint8_t bus) {\n for (size_t i = 0; i < ecam_region_count; i++) {\n struct ecam_region *region = &ecam_regions[i];\n if (region->segment == segment &&\n bus >= region->start_bus &&\n bus <= region->end_bus) {\n return region;\n }\n }\n return NULL;\n}\n\n// Calculate ECAM address for a given PCI address and offset\n// Note: Per ACPI spec, the MCFG base address always corresponds to bus 0,\n// regardless of what start_bus is. The start_bus is only for validation.\nstatic inline void *ecam_address(struct ecam_region *region, struct pci_address *address, uint32_t offset) {\n uint64_t addr = region->base;\n addr += (uint64_t)(address->bus) << 20;\n addr += (uint64_t)(address->slot) << 15;\n addr += (uint64_t)(address->function) << 12;\n addr += offset;\n return (void *)(uintptr_t)addr;\n}\n\nstatic uint32_t pci_read_pio(struct pci_address *address, uint32_t offset, uint32_t size) {\n // CF8/CFC has no segment field and only ever reaches segment 0; refuse\n // any other segment so we don't silently access a same-B:D.F device on\n // segment 0 instead.\n if (address->segment != 0 || offset >= 0x100) {\n return 0xFFFFFFFF;\n }\n switch (size) {\n case 1: return pciConfigReadByte(address->bus, address->slot, address->function, offset);\n case 2: return pciConfigReadWord(address->bus, address->slot, address->function, offset);\n default: return pciConfigReadDWord(address->bus, address->slot, address->function, offset);\n }\n}\n\nstatic void pci_write_pio(struct pci_address *address, uint32_t offset, uint32_t size, uint32_t value) {\n if (address->segment != 0 || offset >= 0x100) {\n return;\n }\n switch (size) {\n case 1: pciConfigWriteByte(address->bus, address->slot, address->function, offset, value); break;\n case 2: pciConfigWriteWord(address->bus, address->slot, address->function, offset, value); break;\n default: pciConfigWriteDWord(address->bus, address->slot, address->function, offset, value); break;\n }\n}\n\nstatic uint32_t pci_read_ecam(struct pci_address *address, uint32_t offset, uint32_t size) {\n struct ecam_region *region = find_ecam_region(address->segment, address->bus);\n if (region == NULL) {\n // Fall back to PIO if no ECAM region covers this bus.\n return pci_read_pio(address, offset, size);\n }\n void *addr = ecam_address(region, address, offset);\n switch (size) {\n case 1: return readb(addr);\n case 2: return readw(addr);\n default: return readl(addr);\n }\n}\n\nstatic void pci_write_ecam(struct pci_address *address, uint32_t offset, uint32_t size, uint32_t value) {\n struct ecam_region *region = find_ecam_region(address->segment, address->bus);\n if (region == NULL) {\n // Fall back to PIO if no ECAM region covers this bus.\n pci_write_pio(address, offset, size, value);\n return;\n }\n void *addr = ecam_address(region, address, offset);\n switch (size) {\n case 1: writeb(addr, value); break;\n case 2: writew(addr, value); break;\n default: writel(addr, value); break;\n }\n}\n\ntypedef uint32_t(*pci_read_t)(struct pci_address *address, uint32_t offset, uint32_t size);\ntypedef void (*pci_write_t)(struct pci_address *address, uint32_t offset, uint32_t size, uint32_t value);\n\nstatic pci_read_t pci_read = pci_read_pio;\nstatic pci_write_t pci_write = pci_write_pio;\n\nuint32_t pci_read_config_space(struct pci_address *address, uint32_t offset, uint32_t size) {\n return pci_read(address, offset & ~(size - 1), size);\n}\n\nvoid pci_write_config_space(struct pci_address *address, uint32_t offset, uint32_t size, uint32_t value) {\n pci_write(address, offset & ~(size - 1), size, value);\n}\n\nvoid pci_enable_for_oprom(uint8_t bus, uint8_t devfn) {\n struct pci_address address = {\n .segment = 0,\n .bus = bus,\n .slot = devfn >> 3,\n .function = devfn & 0x7,\n };\n uint16_t cmd = pci_read16(&address, 0x04);\n pci_write16(&address, 0x04, cmd | (1 << 0) | (1 << 1) | (1 << 2));\n}\n\n// Parse MCFG table and populate ECAM regions\nstatic bool parse_mcfg_table(void) {\n uacpi_table tbl;\n uacpi_status status;\n\n status = uacpi_table_find_by_signature(ACPI_MCFG_SIGNATURE, &tbl);\n if (status != UACPI_STATUS_OK) {\n printf(\"MCFG table not found, using legacy PIO for config access\\n\");\n return false;\n }\n\n struct acpi_mcfg *mcfg = (struct acpi_mcfg *)tbl.hdr;\n\n // Calculate number of entries: (table_length - header_size) / entry_size\n size_t entries_size = mcfg->hdr.length - sizeof(struct acpi_mcfg);\n size_t num_entries = entries_size / sizeof(struct acpi_mcfg_allocation);\n\n printf(\"MCFG: found %zu ECAM region(s)\\n\", num_entries);\n\n for (size_t i = 0; i < num_entries && ecam_region_count < ECAM_MAX_REGIONS; i++) {\n struct acpi_mcfg_allocation *alloc = &mcfg->entries[i];\n\n ecam_regions[ecam_region_count].base = alloc->address;\n ecam_regions[ecam_region_count].segment = alloc->segment;\n ecam_regions[ecam_region_count].start_bus = alloc->start_bus;\n ecam_regions[ecam_region_count].end_bus = alloc->end_bus;\n\n printf(\" ECAM region %zu: base=0x%llx segment=%u buses=%u-%u\\n\",\n ecam_region_count, alloc->address, alloc->segment,\n alloc->start_bus, alloc->end_bus);\n\n ecam_region_count++;\n }\n\n if (ecam_region_count > 0) {\n // Switch to ECAM access (with PIO fallback built into the functions)\n pci_read = pci_read_ecam;\n pci_write = pci_write_ecam;\n printf(\"ECAM: enabled memory-mapped config access\\n\");\n return true;\n }\n\n return false;\n}\n\n// ============================================================================\n// PCIe Resizable BAR Support\n// ============================================================================\n\n#define PCI_EXT_CAP_ID_REBAR 0x15 // Resizable BAR capability ID\n\n// Find a PCIe extended capability by ID\n// Returns the offset in config space, or 0 if not found\nstatic uint16_t pci_find_ext_capability(struct pci_address *address, uint16_t cap_id) {\n // Extended capabilities start at offset 0x100\n uint16_t offset = 0x100;\n\n // Walk the extended capability list\n for (int i = 0; i < 48 && offset != 0; i++) { // Max 48 iterations to prevent infinite loop\n uint32_t header = pci_read32(address, offset);\n\n // Check for invalid header (all 1s or all 0s)\n if (header == 0xFFFFFFFF || header == 0) {\n return 0;\n }\n\n uint16_t id = header & 0xFFFF;\n uint16_t next = (header >> 20) & 0xFFC; // Next pointer is bits [31:20], 4-byte aligned\n\n if (id == cap_id) {\n return offset;\n }\n\n offset = next;\n }\n\n return 0;\n}\n\n// Patch the Supported Sizes bitmap for cards that ship a malformed REBAR\n// capability. The bitmap is post-shift: bit N means size 2^(N+20) bytes.\nstatic uint32_t pci_rebar_apply_quirks(uint16_t vendor, uint16_t device,\n uint16_t subsystem_vendor, uint8_t revision,\n uint8_t bar, uint32_t supported_sizes) {\n // Sapphire Radeon RX 5600 XT Pulse (1002:731f, ssvid 1da2, rev C1)\n // advertises only the 256/512/1024 MB bits for BAR 0, while the silicon\n // actually decodes up to 8 GB. Mirrors Linux's quirk in\n // drivers/pci/rebar.c, including the subsystem vendor and revision\n // restrictions that keep it from misfiring on other 5600 XT boards.\n if (vendor == 0x1002 && device == 0x731f && subsystem_vendor == 0x1da2\n && revision == 0xC1 && bar == 0 && supported_sizes == 0x700) {\n return 0x3f00;\n }\n return supported_sizes;\n}\n\n// Try to resize a BAR to fit within max_size bytes\n// Returns the new size if successful, or 0 if resize not possible\nstatic uint64_t pci_try_resize_bar(struct pci_address *address, uint8_t bar_index, uint64_t max_size) {\n uint16_t rebar_offset = pci_find_ext_capability(address, PCI_EXT_CAP_ID_REBAR);\n if (rebar_offset == 0) {\n return 0; // No Resizable BAR capability\n }\n\n // Read number of resizable BARs from first control register\n uint32_t ctrl0 = pci_read32(address, rebar_offset + 0x08);\n uint8_t num_bars = (ctrl0 >> 5) & 0x7;\n\n if (num_bars == 0) {\n return 0;\n }\n\n\n // Search for the entry corresponding to our BAR\n for (uint8_t i = 0; i < num_bars; i++) {\n uint16_t entry_offset = rebar_offset + 0x04 + (i * 8);\n uint32_t cap = pci_read32(address, entry_offset);\n uint32_t ctrl = pci_read32(address, entry_offset + 4);\n\n uint8_t this_bar = ctrl & 0x7; // BAR index in bits [2:0]\n\n if (this_bar != bar_index) {\n continue;\n }\n\n // Found the entry for our BAR\n // Supported sizes are in cap bits [31:4], each bit N represents size 2^(N+20)\n uint32_t supported_sizes = (cap >> 4) & 0x0FFFFFFF;\n\n uint16_t vendor = pci_read16(address, 0x00);\n uint16_t device = pci_read16(address, 0x02);\n uint16_t subsystem_vendor = pci_read16(address, 0x2c);\n uint8_t revision = pci_read8(address, 0x08);\n supported_sizes = pci_rebar_apply_quirks(vendor, device, subsystem_vendor,\n revision, bar_index, supported_sizes);\n\n\n // Find the largest size that fits within max_size\n // Sizes: bit 0 = 1MB (2^20), bit 1 = 2MB (2^21), etc.\n int best_size_bit = -1;\n for (int bit = 27; bit >= 0; bit--) { // Check from largest to smallest\n if (!(supported_sizes & (1 << bit))) {\n continue;\n }\n\n uint64_t size = 1ULL << (bit + 20);\n if (size <= max_size) {\n best_size_bit = bit;\n break;\n }\n }\n\n if (best_size_bit < 0) {\n return 0;\n }\n\n uint64_t new_size = 1ULL << (best_size_bit + 20);\n\n // Save original BAR(s) - PCIe spec: contents are unspecified after resize\n uint32_t bar_offset = 0x10 + bar_index * 4;\n uint32_t orig_bar_lo = pci_read32(address, bar_offset);\n bool bar_is_64 = (orig_bar_lo & 0x6) == 0x4;\n uint32_t orig_bar_hi = bar_is_64 ? pci_read32(address, bar_offset + 4) : 0;\n\n // Disable memory decode before resizing\n uint16_t cmd = pci_read16(address, 0x04);\n pci_write16(address, 0x04, cmd & ~0x06); // Clear memory space + bus master\n\n // Read-modify-write only the BAR Size field (bits [12:8]); other\n // bits include RsvdP that must be preserved per PCIe spec.\n uint32_t new_ctrl = (ctrl & ~0x1F00) | ((best_size_bit & 0x1F) << 8);\n pci_write32(address, entry_offset + 4, new_ctrl);\n\n // Restore BAR address clobbered by resize\n pci_write32(address, bar_offset, orig_bar_lo);\n if (bar_is_64) {\n pci_write32(address, bar_offset + 4, orig_bar_hi);\n }\n\n // Re-enable memory decode\n pci_write16(address, 0x04, cmd);\n\n return new_size;\n }\n\n return 0;\n}\n\n#define ROOT_BUSES_MAX 64\n\nstatic struct pci_bus *root_buses[ROOT_BUSES_MAX];\nstatic size_t root_bus_count = 0;\n\n#define BUS_STRUCT_POOL_COUNT 128\n\nstatic struct pci_bus *bus_struct_pool = NULL;\nstatic size_t bus_struct_pool_ptr = 0;\n\nstatic struct pci_bus *allocate_bus(void) {\n if (bus_struct_pool_ptr == BUS_STRUCT_POOL_COUNT) {\n return NULL;\n }\n return &bus_struct_pool[bus_struct_pool_ptr++];\n}\n\n#define DEVICE_STRUCT_POOL_COUNT 1024\n\nstatic struct pci_device *device_struct_pool = NULL;\nstatic size_t device_struct_pool_ptr = 0;\n\nstatic struct pci_device *allocate_device(void) {\n if (device_struct_pool_ptr == DEVICE_STRUCT_POOL_COUNT) {\n return NULL;\n }\n return &device_struct_pool[device_struct_pool_ptr++];\n}\n\n#define BAR_STRUCT_POOL_COUNT 2048\n\nstatic struct pci_bar *bar_struct_pool = NULL;\nstatic size_t bar_struct_pool_ptr = 0;\n\nstatic struct pci_bar *allocate_bar(void) {\n if (bar_struct_pool_ptr == BAR_STRUCT_POOL_COUNT) {\n return NULL;\n }\n return &bar_struct_pool[bar_struct_pool_ptr++];\n}\n\nstatic bool add_root_bus(struct pci_bus *bus) {\n if (root_bus_count == ROOT_BUSES_MAX) {\n return false;\n }\n\n root_buses[root_bus_count++] = bus;\n\n return true;\n}\n\nstatic struct pci_range *add_range(struct pci_bus *bus, uint64_t base, uint64_t length, bool prefetchable) {\n // For root buses, filter out ranges above 4GB (can't be used by legacy BIOS)\n // For secondary buses, keep >4GB ranges so we can create bridge window pseudo-BARs\n // (the bridge windows will be relocated to <4GB, updating the range)\n if (bus->root) {\n if (base + length > 0x100000000) {\n if (base >= 0x100000000) {\n return NULL;\n }\n length -= (base + length) - 0x100000000;\n }\n }\n\n // Low memory ranges are special\n if (base < 0x100000) {\n return NULL;\n }\n\n if (bus->range_count == PCI_MAX_RANGES_PER_BUS) {\n return NULL;\n }\n\n bus->ranges[bus->range_count].base = base;\n bus->ranges[bus->range_count].length = length;\n bus->ranges[bus->range_count].prefetchable = prefetchable;\n\n bus->range_count++;\n\n return &bus->ranges[bus->range_count - 1];\n}\n\n// Tombstone the range in place rather than shifting later entries down,\n// since bridge pseudo-BARs cache raw pointers into bus->ranges[].\nstatic bool drop_range(struct pci_bus *bus, struct pci_range *range) {\n (void)bus;\n range->length = 0;\n return true;\n}\n\nstatic bool add_device(struct pci_bus *bus, struct pci_device *device) {\n if (bus->device_count == PCI_MAX_DEVICES_PER_BUS) {\n return false;\n }\n\n bus->devices[bus->device_count++] = device;\n\n return true;\n}\n\nstatic bool add_bar(struct pci_bus *bus, struct pci_bar *bar) {\n // Non-bridge BARs >4GB are hopeless\n if (bar->range == NULL && bar->length >= 0x100000000) {\n return true;\n }\n\n // Likewise for BARs originally below 1MiB\n if (bar->base < 0x100000) {\n return true;\n }\n\n if (bus->bar_count == PCI_MAX_BARS_PER_BUS) {\n return false;\n }\n\n bus->bars[bus->bar_count++] = bar;\n\n return true;\n}\n\nstatic bool drop_bar(struct pci_bus *bus, struct pci_bar *bar) {\n for (size_t i = 0; i < bus->bar_count; i++) {\n if (bus->bars[i] != bar) {\n continue;\n }\n if (i + 1 < bus->bar_count) {\n memmove(&bus->bars[i], &bus->bars[i + 1], (bus->bar_count - i - 1) * sizeof(struct pci_bar *));\n }\n bus->bar_count--;\n break;\n }\n\n return true;\n}\n\n// Check if firmware placed this address within a prefetchable range.\n// This is used to determine if a non-prefetchable BAR can safely be\n// relocated to a prefetchable range (firmware already deemed it safe).\nstatic bool is_address_in_prefetchable_range(struct pci_bus *bus, uint64_t address) {\n for (size_t i = 0; i < bus->range_count; i++) {\n struct pci_range *range = &bus->ranges[i];\n if (range->length == 0) {\n continue;\n }\n if (address >= range->base && address < range->base + range->length) {\n return range->prefetchable;\n }\n }\n return false;\n}\n\nstatic int compare_bars(const void *a, const void *b) {\n const struct pci_bar *bar_a = *(const struct pci_bar **)a;\n const struct pci_bar *bar_b = *(const struct pci_bar **)b;\n\n // Sort by length descending (largest first)\n if (bar_a->length > bar_b->length) return -1;\n if (bar_a->length < bar_b->length) return 1;\n return 0;\n}\n\nstatic void sort_bars(struct pci_bus *bus) {\n qsort(bus->bars, bus->bar_count, sizeof(struct pci_bar *), compare_bars);\n for (size_t i = 0; i < bus->bar_count; i++) {\n if (bus->bars[i]->range == NULL) {\n continue;\n }\n\n struct pci_bar *bar = bus->bars[i];\n struct pci_device *device = bar->device;\n struct pci_bus *bridge_bus = device->bridge_bus;\n\n sort_bars(bridge_bus);\n }\n}\n\nstatic void reallocate_bars(struct pci_bus *bus);\n\nstatic bool fb_relocated = false;\n\nstatic void reallocate_single_bar(struct pci_bus *bus, struct pci_bar *bar) {\n bool tried_all_prefetchable = false;\n\nagain:\n for (size_t i = 0; i < bus->range_count; i++) {\n struct pci_range *range = &bus->ranges[i];\n\n if (range->length == 0) {\n continue;\n }\n\n if (tried_all_prefetchable == false && bar->prefetchable != range->prefetchable) {\n continue;\n }\n\n // Skip ranges above 4GB - they can't be used by legacy BIOS\n // (Bridge window pseudo-BARs will relocate these ranges to <4GB first)\n if (range->base >= 0x100000000ULL) {\n continue;\n }\n\n // BARs must be naturally aligned to their size.\n // Compute alignment on the absolute address since the range base\n // (from ACPI for root buses) may not be aligned to large BAR sizes.\n // For bridge windows, align to largest child BAR, not window size.\n uint64_t alignment = bar->length;\n if (bar->bar_number == 0xff && bar->device->bridge_bus != NULL) {\n // Find largest child BAR with matching prefetchability\n uint64_t largest_child = 0x100000; // 1MB minimum for bridge windows\n struct pci_bus *child_bus = bar->device->bridge_bus;\n for (size_t j = 0; j < child_bus->bar_count; j++) {\n struct pci_bar *child = child_bus->bars[j];\n if (child->prefetchable == bar->prefetchable && child->length > largest_child) {\n largest_child = child->length;\n }\n }\n alignment = largest_child;\n }\n uint64_t current_absolute = range->base + range->reloc_ptr;\n uint64_t aligned_absolute = ALIGN_UP(current_absolute, alignment);\n\n if (aligned_absolute + bar->length > range->base + range->length) {\n continue;\n }\n\n uint64_t orig_base = bar->base;\n bar->base = aligned_absolute;\n range->reloc_ptr = (aligned_absolute - range->base) + bar->length;\n\n struct pci_device *device = bar->device;\n\n struct pci_address address;\n address.segment = device->root_bus->segment;\n address.bus = device->root_bus->bus;\n address.slot = device->slot;\n address.function = device->function;\n\n printf(\"reallocating BAR %u of device %04x:%02x:%02x.%02x from 0x%llx to 0x%llx\\n\",\n bar->bar_number, bus->segment, bus->bus, bar->device->slot, bar->device->function,\n orig_base, bar->base);\n\n // Track the framebuffer via the actual device BAR, not bridge window\n // pseudo-BARs: a window's relocation only preserves the FB offset if\n // the BAR layout within the window is unchanged, which compaction\n // does not guarantee. The fb_relocated flag still guards against a\n // post-adjustment FBA falling within another regular BAR's old range.\n if (!fb_relocated\n && bar->bar_number != 0xff\n && priv.cb_fb.physical_address >= orig_base\n && priv.cb_fb.physical_address < orig_base + bar->length) {\n printf(\"BAR contains the EFI framebuffer. Modifying cb_fb.physical_address accordingly...\\n\");\n printf(\" 0x%llx => \", priv.cb_fb.physical_address);\n priv.cb_fb.physical_address -= orig_base;\n priv.cb_fb.physical_address += bar->base;\n printf(\"0x%llx\\n\", priv.cb_fb.physical_address);\n fb_relocated = true;\n }\n\n // Disable memory decode while updating BAR to prevent device from\n // responding to partially-updated or stale addresses\n uint16_t cmd = pci_read16(&address, 0x04);\n pci_write16(&address, 0x04, cmd & ~(1 << 1));\n\n if (bar->bar_number != 0xff) {\n uint64_t new_base = bar->base | (pci_read32(&address, 0x10 + bar->bar_number * 4) & 0xf);\n\n pci_write32(&address, 0x10 + bar->bar_number * 4, new_base);\n\n if (bar->is_64) {\n pci_write32(&address, 0x10 + bar->bar_number * 4 + 4, new_base >> 32);\n }\n } else {\n // Bridge window - need to update BOTH base AND limit registers\n // Limit is an absolute address: base + length - 1\n uint8_t base_reg = bar->prefetchable ? 0x24 : 0x20;\n uint8_t limit_reg = bar->prefetchable ? 0x26 : 0x22;\n\n // Calculate new limit address\n uint64_t new_limit = bar->base + bar->length - 1;\n\n // Write base register (preserve type bits in low nibble)\n pci_write16(&address, base_reg,\n ((bar->base >> 16) & 0xfff0) | (pci_read16(&address, base_reg) & 0xf));\n\n // Write limit register (preserve type bits in low nibble)\n pci_write16(&address, limit_reg,\n ((new_limit >> 16) & 0xfff0) | (pci_read16(&address, limit_reg) & 0xf));\n\n if (bar->prefetchable && bar->is_64) {\n pci_write32(&address, 0x28, bar->base >> 32);\n pci_write32(&address, 0x2c, new_limit >> 32);\n }\n\n bar->range->base = bar->base;\n\n bar->device->reallocated_windows++;\n\n // Count total bridge window bars for this device\n int total_bridge_windows = 0;\n for (size_t j = 0; j < bus->bar_count; j++) {\n if (bus->bars[j]->device == bar->device && bus->bars[j]->bar_number == 0xff) {\n total_bridge_windows++;\n }\n }\n\n // Re-enable memory decode BEFORE recursing - child devices need the bridge to forward transactions\n cmd |= (1 << 0) | (1 << 1) | (1 << 2);\n pci_write16(&address, 0x04, cmd);\n\n // Only recurse once all bridge windows for this device are done\n if (bar->device->reallocated_windows == total_bridge_windows) {\n reallocate_bars(bar->device->bridge_bus);\n }\n\n return;\n }\n\n // Restore the device's original command register; we only cleared\n // MEM_EN above, so writing the saved value back puts I/O space and\n // bus master back to whatever the firmware had set them to.\n // Devices with associated option ROMs are force-enabled separately\n // via pci_enable_for_oprom before dispatch.\n pci_write16(&address, 0x04, cmd);\n\n return;\n }\n\n // Allow fallback to mismatched prefetchability if:\n // 1. BAR is prefetchable (can always use non-prefetchable range safely), or\n // 2. Firmware originally placed this non-prefetchable BAR in a prefetchable range\n // (trusting that firmware knew this device is safe in prefetchable memory)\n if ((bar->prefetchable || bar->firmware_in_prefetchable) && tried_all_prefetchable == false) {\n tried_all_prefetchable = true;\n goto again;\n }\n\n printf(\"failed to reallocate BAR %u for device %04x:%02x:%02x.%02x\\n\",\n bar->bar_number, bus->segment, bus->bus, bar->device->slot, bar->device->function);\n\n // Even if this bridge window failed, we still need to track it for recursion purposes.\n // Otherwise, if one window fails, we'll never recurse into the secondary bus.\n if (bar->bar_number == 0xff && bar->device->bridge_bus != NULL) {\n bar->device->reallocated_windows++;\n\n int total_bridge_windows = 0;\n for (size_t j = 0; j < bus->bar_count; j++) {\n if (bus->bars[j]->device == bar->device && bus->bars[j]->bar_number == 0xff) {\n total_bridge_windows++;\n }\n }\n\n if (bar->device->reallocated_windows == total_bridge_windows) {\n reallocate_bars(bar->device->bridge_bus);\n }\n }\n}\n\nstatic void reallocate_bars(struct pci_bus *bus) {\n for (size_t i = 0; i < bus->bar_count; i++) {\n reallocate_single_bar(bus, bus->bars[i]);\n }\n}\n\nstatic bool scan_bars(struct pci_device *device) {\n uint8_t max_bars = device->type == PCI_DEVICE_BRIDGE ? 2 : 6;\n\n struct pci_address address;\n address.segment = device->root_bus->segment;\n address.bus = device->root_bus->bus;\n address.slot = device->slot;\n address.function = device->function;\n\n if (device->type == PCI_DEVICE_BRIDGE) {\n // Non-prefetchable memory window. Bits [3:0] of the 16-bit base and\n // limit registers are reserved-zero, so we can use them as-is.\n uint64_t non_prefetchable_base = (uint64_t)pci_read16(&address, 0x20) << 16;\n uint64_t non_prefetchable_limit = ((uint64_t)pci_read16(&address, 0x22) << 16) | 0xfffff;\n\n // A window is enabled iff limit >= base; otherwise it is closed\n // (firmware convention is base = 0xFFF0, limit = 0x0000).\n if (non_prefetchable_limit >= non_prefetchable_base) {\n uint64_t non_prefetchable_length = non_prefetchable_limit - non_prefetchable_base + 1;\n\n struct pci_range *range = add_range(device->bridge_bus, non_prefetchable_base, non_prefetchable_length, false);\n if (range == NULL) {\n // Range not usable (above 4G, below 1M, or pool exhausted) - skip\n goto no_non_prefetch_range;\n }\n\n struct pci_bar *bar = allocate_bar();\n if (bar == NULL) {\n printf(\"allocate_bar() failed for bridge non-prefetchable window\\n\");\n goto no_non_prefetch_range;\n }\n bar->range = range;\n bar->base = non_prefetchable_base;\n bar->length = non_prefetchable_length;\n bar->bar_number = 0xff;\n bar->device = device;\n bar->prefetchable = false;\n bar->is_64 = false;\n // Check if firmware placed this non-prefetchable window in a prefetchable region\n bar->firmware_in_prefetchable = is_address_in_prefetchable_range(device->root_bus, non_prefetchable_base);\n\n if (!add_bar(device->root_bus, bar)) {\n printf(\"add_bar() failed for bridge non-prefetchable window\\n\");\n goto no_non_prefetch_range;\n }\n }\nno_non_prefetch_range:;\n\n // Prefetchable memory window. Bits [3:0] of base/limit indicate\n // 32-bit (0x0) vs 64-bit (0x1) decoding; mask them off before use.\n uint16_t prefetchable_base_reg = pci_read16(&address, 0x24);\n uint16_t prefetchable_limit_reg = pci_read16(&address, 0x26);\n bool is_64 = (prefetchable_base_reg & 0xf) == 0x1;\n\n uint64_t prefetchable_base = (uint64_t)(prefetchable_base_reg & 0xfff0) << 16;\n uint64_t prefetchable_limit = ((uint64_t)(prefetchable_limit_reg & 0xfff0) << 16) | 0xfffff;\n\n // For 64-bit windows, fold in the upper-32 registers before doing\n // the limit-vs-base test: a window that crosses 4 GB legitimately\n // has lower-16 limit < lower-16 base.\n if (is_64) {\n prefetchable_base |= (uint64_t)pci_read32(&address, 0x28) << 32;\n prefetchable_limit |= (uint64_t)pci_read32(&address, 0x2c) << 32;\n }\n\n if (prefetchable_limit >= prefetchable_base) {\n uint64_t prefetchable_length = prefetchable_limit - prefetchable_base + 1;\n\n struct pci_range *range = add_range(device->bridge_bus, prefetchable_base, prefetchable_length, true);\n if (range == NULL) {\n // Range not usable (above 4G, below 1M, or pool exhausted) - skip\n goto no_prefetch_range;\n }\n\n struct pci_bar *bar = allocate_bar();\n if (bar == NULL) {\n printf(\"allocate_bar() failed for bridge prefetchable window\\n\");\n goto no_prefetch_range;\n }\n bar->range = range;\n bar->base = prefetchable_base;\n bar->length = prefetchable_length;\n bar->bar_number = 0xff;\n bar->device = device;\n bar->prefetchable = true;\n bar->is_64 = is_64;\n // Check if firmware placed this window in a prefetchable region (should always be true for prefetchable windows)\n bar->firmware_in_prefetchable = is_address_in_prefetchable_range(device->root_bus, prefetchable_base);\n\n if (!add_bar(device->root_bus, bar)) {\n printf(\"add_bar() failed for bridge prefetchable window\\n\");\n goto no_prefetch_range;\n }\n }\nno_prefetch_range:;\n }\n\n for (uint8_t bar = 0; bar < max_bars; ) {\n uint32_t bar_offset = 0x10 + bar * 4;\n uint32_t bar_value = pci_read32(&address, bar_offset);\n\n // Memory bar layout is as follows:\n // - bit 0: always 0\n // - bit 1-2: bar type (0 is 32-bit, 1 is reserved, 2 is 64-bit)\n // - bit 3: prefetchable\n // - bit 4-31: base address\n\n bool is_64bit = false;\n bool prefetchable = false;\n\n if ((bar_value & (1 << 0)) != 0) {\n bar += 1;\n continue;\n }\n\n // Check the bar type to figure out whether it's a 64-bit bar\n is_64bit = (bar_value & 0x6) == 0x4;\n prefetchable = (bar_value & (1 << 3)) != 0;\n\n // Mask out the flag bits to get the bar address\n uint64_t base = bar_value & 0xFFFFFFF0;\n\n // If the bar is 64-bit then read the next bar's base address\n // and OR that into our current bar's base address - 64-bit bars\n // are made up of two consecutive bars to form a 64-bit address\n if (bar != max_bars - 1 && is_64bit) {\n uint32_t next_bar = pci_read32(&address, bar_offset + 0x4);\n base |= (uint64_t)next_bar << 32;\n }\n\n // Disable bus master, memory and IO decoding to prevent the device\n // from mistakenly responding to our PCI config space accesses\n uint8_t cmd = pci_read8(&address, 0x4);\n uint8_t new_cmd = cmd;\n\n new_cmd &= ~(1 << 0); // IO space decoding\n new_cmd &= ~(1 << 1); // Memory space decoding\n new_cmd &= ~(1 << 2); // Bus master\n\n pci_write8(&address, 0x4, new_cmd);\n\n // Discover the bar length\n pci_write32(&address, bar_offset, 0xFFFFFFFF);\n uint32_t response = pci_read32(&address, bar_offset);\n pci_write32(&address, bar_offset, bar_value);\n uint64_t length = response & 0xFFFFFFF0;\n\n if (bar != max_bars - 1 && is_64bit) {\n uint32_t next_bar = pci_read32(&address, bar_offset + 0x4);\n pci_write32(&address, bar_offset + 0x4, 0xFFFFFFFF);\n uint32_t response_hi = pci_read32(&address, bar_offset + 0x4);\n pci_write32(&address, bar_offset + 0x4, next_bar);\n length |= (uint64_t)response_hi << 32;\n } else {\n length |= 0xffffffff00000000;\n }\n\n length = ~length + 1;\n\n // Restore command register\n pci_write8(&address, 0x4, cmd);\n\n // Skip unimplemented BARs. For 64-bit BARs, lower-half response==0\n // is legitimate when size >= 4GB (size bits live in the upper half).\n if (length == 0 || (!is_64bit && response == 0)) {\n goto next_bar;\n }\n\n // If BAR is larger than the classic 256MB limit, try to resize it\n // 256MB was the standard GPU framebuffer BAR size before Resizable BAR\n if (length > 256 * 1024 * 1024) {\n uint64_t max_resize = 256 * 1024 * 1024; // 256 MB - classic pre-ReBAR size\n\n uint64_t new_length = pci_try_resize_bar(&address, bar, max_resize);\n\n if (new_length > 0 && new_length < length) {\n printf(\"Resized BAR%d from %llu MB to %llu MB\\n\", bar,\n length / (1024 * 1024), new_length / (1024 * 1024));\n length = new_length;\n } else {\n printf(\"BAR%d too large (%llu MB) and resize failed, skipping\\n\",\n bar, length / (1024 * 1024));\n goto next_bar;\n }\n }\n\n if (base != 0) {\n struct pci_bar *bar_info = allocate_bar();\n if (bar_info == NULL) {\n printf(\"allocate_bar() failed for device %04x:%02x:%02x.%02x BAR%d\\n\",\n device->root_bus->segment, device->root_bus->bus, device->slot, device->function, bar);\n goto next_bar;\n }\n\n bar_info->device = device;\n bar_info->bar_number = bar;\n bar_info->base = base;\n bar_info->length = length;\n bar_info->prefetchable = prefetchable;\n bar_info->is_64 = is_64bit;\n // Check if firmware placed this BAR in a prefetchable region\n bar_info->firmware_in_prefetchable = is_address_in_prefetchable_range(device->root_bus, base);\n\n if (!add_bar(device->root_bus, bar_info)) {\n printf(\"add_bar() failure\\n\");\n }\n\n if (prefetchable) {\n device->root_bus->required_prefetchable_size += length;\n } else {\n device->root_bus->required_non_prefetchable_size += length;\n }\n }\nnext_bar:\n\n if (is_64bit) {\n bar += 2;\n } else {\n bar += 1;\n }\n }\n\n return true;\n}\n\nstatic bool scan_bus(struct pci_bus *bus);\n\nstatic bool scan_function(struct pci_bus *bus, struct pci_address *address) {\n uint8_t subclass = pci_read8(address, 0xA);\n uint8_t class = pci_read8(address, 0xB);\n\n struct pci_device *device = allocate_device();\n if (device == NULL) {\n printf(\"allocate_device() failed for %04x:%02x:%02x.%02x\\n\",\n address->segment, address->bus, address->slot, address->function);\n return false;\n }\n\n device->root_bus = bus;\n device->slot = address->slot;\n device->function = address->function;\n\n struct pci_bus *bridge_bus = NULL;\n\n if (class == 0x6 && subclass == 0x4) {\n bridge_bus = allocate_bus();\n if (bridge_bus == NULL) {\n printf(\"allocate_bus() failed for bridge %04x:%02x:%02x.%02x\\n\",\n address->segment, address->bus, address->slot, address->function);\n // Continue without scanning behind this bridge\n goto not_a_bridge;\n }\n\n uint8_t secondary_bus = pci_read8(address, 0x19);\n\n bridge_bus->segment = address->segment;\n bridge_bus->bus = secondary_bus;\n\n if (!scan_bus(bridge_bus)) {\n printf(\"scan_bus() failure\\n\");\n }\n\n // Propagate required sizes from child bus to parent bus\n // This ensures nested bridge windows are sized correctly\n bus->required_prefetchable_size += bridge_bus->required_prefetchable_size;\n bus->required_non_prefetchable_size += bridge_bus->required_non_prefetchable_size;\n\n device->type = PCI_DEVICE_BRIDGE;\n device->bridge_bus = bridge_bus;\n } else {\nnot_a_bridge:\n device->type = PCI_DEVICE_REGULAR;\n device->bridge_bus = NULL;\n }\n\n if (!scan_bars(device)) {\n printf(\"scan_bars() failure\\n\");\n }\n\n if (bridge_bus != NULL && bridge_bus->range_count == 0) {\n device->bridge_bus = NULL;\n }\n\n if (!add_device(bus, device)) {\n printf(\"add_device() failure\\n\");\n }\n\n return true;\n}\n\nstatic bool scan_slot(struct pci_bus *bus, struct pci_address *address) {\n uint16_t vendor_id = pci_read16(address, 0x0);\n\n // No device on this slot, return\n if (vendor_id == 0xFFFF) {\n return true;\n }\n\n if (!scan_function(bus, address)) {\n printf(\"scan_function() failure\\n\");\n }\n\n // Check if device is multi-function\n uint8_t header_type = pci_read8(address, 0xE);\n if (!(header_type & 0x80)) {\n return true;\n }\n\n for (uint8_t func = 1; func < 8; func++) {\n struct pci_address func_addr = *address;\n func_addr.function = func;\n\n vendor_id = pci_read16(&func_addr, 0x0);\n if (vendor_id == 0xFFFF){\n continue;\n }\n\n if (!scan_function(bus, &func_addr)) {\n printf(\"scan_function() failure\\n\");\n }\n }\n\n return true;\n}\n\nstatic bool scan_bus(struct pci_bus *bus) {\n for (uint8_t slot = 0; slot < 32; slot++) {\n struct pci_address address;\n address.segment = bus->segment;\n address.bus = bus->bus;\n address.slot = slot;\n address.function = 0;\n\n if (!scan_slot(bus, &address)) {\n printf(\"scan_slot() failure\\n\");\n }\n }\n\n return true;\n}\n\nstatic void pretty_print_bus(struct pci_bus *bus, int indent) {\n printf(\"%-*s%s, segment=%d, bus=%d, range_count=%zu, device_count=%zu, bar_count=%zu\\n\",\n (int)(indent * 2), \"\", bus->root ? \"root bus\" : \"bridge bus\",\n bus->segment, bus->bus, bus->range_count, bus->device_count, bus->bar_count);\n\n printf(\"%-*srequired prefetchable size=0x%llx\\n\", (int)(indent * 2), \"\", bus->required_prefetchable_size);\n printf(\"%-*srequired non-prefetchable size=0x%llx\\n\", (int)(indent * 2), \"\", bus->required_non_prefetchable_size);\n\n for (size_t i = 0; i < bus->range_count; i++) {\n struct pci_range *range = &bus->ranges[i];\n\n if (range->length == 0) {\n continue;\n }\n\n printf(\"%-*srange %zu: base=0x%llx, length=0x%llx [%llx-%llx] (%sprefetchable)\\n\",\n (int)((indent + 1) * 2), \"\", i, range->base, range->length, range->base, range->base + range->length - 1,\n range->prefetchable ? \"\" : \"non-\");\n }\n\n for (size_t i = 0; i < bus->device_count; i++) {\n struct pci_device *device = bus->devices[i];\n\n struct pci_address address;\n address.segment = device->root_bus->segment;\n address.bus = device->root_bus->bus;\n address.slot = device->slot;\n address.function = device->function;\n\n uint16_t vendor = pci_read16(&address, 0x0);\n uint16_t product = pci_read16(&address, 0x2);\n\n uint8_t subclass = pci_read8(&address, 0xA);\n uint8_t class = pci_read8(&address, 0xB);\n\n printf(\"%-*sdevice %zu: type=%s, address=%04x:%02x:%02x.%02x, vendor=%04x, product=%04x, subclass=%d, class=%d\\n\",\n (int)((indent + 1) * 2), \"\", i, device->type == PCI_DEVICE_BRIDGE ? \"bridge\" : \"device\",\n bus->segment, bus->bus, device->slot, device->function, vendor, product, subclass, class);\n\n if (device->bridge_bus != NULL) {\n pretty_print_bus(device->bridge_bus, indent + 2);\n }\n }\n\n for (size_t j = 0; j < bus->bar_count; j++) {\n struct pci_bar *bar = bus->bars[j];\n\n printf(\"%-*sbar%d: device_address=%04x:%02x:%02x.%02x, base=0x%llx, length=0x%llx\\n\",\n (int)((indent + 1) * 2), \"\", bar->bar_number, bus->segment, bus->bus, bar->device->slot, bar->device->function, bar->base, bar->length);\n printf(\"%-*s\\t [%llx-%llx] (%sprefetchable, %s-bit)\\n\",\n (int)((indent + 1) * 2), \"\", bar->base, bar->base + bar->length - 1, bar->prefetchable ? \"\" : \"non-\", bar->is_64 ? \"64\" : \"32\");\n }\n}\n\nstatic uacpi_iteration_decision uacpi_discover_root_bus(void *user, uacpi_namespace_node *node, uacpi_u32 node_depth) {\n (void)node_depth;\n\n uacpi_resources *resources = NULL;\n uacpi_iteration_decision decision = UACPI_ITERATION_DECISION_CONTINUE;\n uacpi_status status = UACPI_STATUS_OK;\n\n status = uacpi_get_current_resources(node, &resources);\n if (status != UACPI_STATUS_OK) {\n printf(\"Failed to get node resources: %s\\n\", uacpi_status_to_string(status));\n goto cleanup;\n }\n\n struct pci_bus *root_bus = allocate_bus();\n if (root_bus == NULL) {\n printf(\"allocate_bus() failure\\n\");\n goto cleanup;\n }\n\n uint64_t segment = 0, bus_number = 0;\n\n uacpi_eval_simple_integer(node, \"_SEG\", &segment);\n uacpi_eval_simple_integer(node, \"_BBN\", &bus_number);\n\n root_bus->root = true;\n root_bus->segment = segment;\n root_bus->bus = bus_number;\n\n uacpi_resource *res = resources->entries;\n while ((void *)res < (void *)resources->entries + resources->length) {\n if (res->type == UACPI_RESOURCE_TYPE_END_TAG) {\n break;\n }\n\n switch (res->type) {\n case UACPI_RESOURCE_TYPE_IO:\n case UACPI_RESOURCE_TYPE_FIXED_IO:\n // We don't care about IO regions\n break;\n case UACPI_RESOURCE_TYPE_ADDRESS16:\n if (res->address16.common.type != UACPI_RANGE_MEMORY || res->address16.address_length < 0x1000)\n break;\n if (!add_range(root_bus, res->address16.minimum, res->address16.address_length,\n res->address16.common.attribute.memory.caching != UACPI_NON_CACHEABLE)) {\n printf(\"add_range() failure\\n\");\n }\n break;\n case UACPI_RESOURCE_TYPE_ADDRESS32:\n if (res->address32.common.type != UACPI_RANGE_MEMORY || res->address32.address_length < 0x1000)\n break;\n if (!add_range(root_bus, res->address32.minimum, res->address32.address_length,\n res->address32.common.attribute.memory.caching != UACPI_NON_CACHEABLE)) {\n printf(\"add_range() failure\\n\");\n }\n break;\n case UACPI_RESOURCE_TYPE_ADDRESS64:\n if (res->address64.common.type != UACPI_RANGE_MEMORY || res->address64.address_length < 0x1000)\n break;\n if (!add_range(root_bus, res->address64.minimum, res->address64.address_length,\n res->address64.common.attribute.memory.caching != UACPI_NON_CACHEABLE)) {\n printf(\"add_range() failure\\n\");\n }\n break;\n default:\n printf(\"Unknown PCI root bus resource type %u\\n\", res->type);\n break;\n }\n\n res = UACPI_NEXT_RESOURCE(res);\n }\n\n if (!add_root_bus(root_bus)) {\n goto cleanup;\n }\n\n goto out;\n\ncleanup:\n decision = UACPI_ITERATION_DECISION_BREAK;\n\nout:\n if (resources != NULL) {\n uacpi_free_resources(resources);\n }\n\n *(uacpi_status *)user = status;\n return decision;\n}\n\nstatic bool uacpi_discover_root_bridges(void) {\n uacpi_status status;\n uacpi_status iter_status = UACPI_STATUS_OK;\n\n status = uacpi_find_devices_at(\n uacpi_namespace_get_predefined(UACPI_PREDEFINED_NAMESPACE_SB),\n (const char *[]){\"PNP0A03\", \"PNP0A08\", NULL}, uacpi_discover_root_bus, &iter_status);\n\n if (iter_status != UACPI_STATUS_OK) {\n status = iter_status;\n }\n\n if (status != UACPI_STATUS_OK) {\n printf(\"uACPI find devices failed: %s\\n\", uacpi_status_to_string(status));\n return false;\n }\n\n return true;\n}\n\nsize_t pci_get_extra_root_buses(uint8_t *out, size_t cap) {\n size_t written = 0;\n for (size_t i = 0; i < root_bus_count; i++) {\n struct pci_bus *bus = root_buses[i];\n // SeaBIOS only enumerates segment 0 in real-mode CSM; segment != 0\n // roots can't be reached via legacy CF8/CFC anyway.\n if (bus->segment != 0)\n continue;\n if (bus->bus == 0)\n continue;\n if (written >= cap)\n return 0;\n out[written++] = bus->bus;\n }\n return written;\n}\n\nbool pci_early_initialize(void) {\n if (gBS->AllocatePool(EfiLoaderData, sizeof(struct pci_bus) * BUS_STRUCT_POOL_COUNT, (void *)&bus_struct_pool) != EFI_SUCCESS) {\n return false;\n }\n memset(bus_struct_pool, 0, sizeof(struct pci_bus) * BUS_STRUCT_POOL_COUNT);\n\n if (gBS->AllocatePool(EfiLoaderData, sizeof(struct pci_device) * DEVICE_STRUCT_POOL_COUNT, (void *)&device_struct_pool) != EFI_SUCCESS) {\n return false;\n }\n memset(device_struct_pool, 0, sizeof(struct pci_device) * DEVICE_STRUCT_POOL_COUNT);\n\n if (gBS->AllocatePool(EfiLoaderData, sizeof(struct pci_bar) * BAR_STRUCT_POOL_COUNT, (void *)&bar_struct_pool) != EFI_SUCCESS) {\n return false;\n }\n memset(bar_struct_pool, 0, sizeof(struct pci_bar) * BAR_STRUCT_POOL_COUNT);\n\n if (!acpi_namespace_init()) {\n return false;\n }\n\n // Parse MCFG table to enable ECAM config access (optional, falls back to PIO)\n parse_mcfg_table();\n\n if (!uacpi_discover_root_bridges()) {\n return false;\n }\n\n printf(\"discovered %zu root buses\\n\", root_bus_count);\n\n return true;\n}\n\n// Check if any BAR on this bus or its child buses is above 4GB\nstatic bool has_bars_above_4g(struct pci_bus *bus) {\n // Check BARs on this bus\n for (size_t i = 0; i < bus->bar_count; i++) {\n if (bus->bars[i]->base >= 0x100000000ULL) {\n return true;\n }\n }\n\n // Recursively check child buses (bridges)\n for (size_t i = 0; i < bus->device_count; i++) {\n struct pci_device *device = bus->devices[i];\n if (device->bridge_bus != NULL) {\n if (has_bars_above_4g(device->bridge_bus)) {\n return true;\n }\n }\n }\n\n return false;\n}\n\nstatic bool resize_bridge_windows(struct pci_bus *bus) {\n // First, recursively resize all child bridge windows (bottom-up order).\n // This ensures that when we size this level's windows, child windows\n // have already been resized and we can use their actual sizes.\n for (size_t i = 0; i < bus->bar_count; i++) {\n if (bus->bars[i]->range == NULL) {\n continue;\n }\n struct pci_device *device = bus->bars[i]->device;\n if (device->bridge_bus != NULL) {\n resize_bridge_windows(device->bridge_bus);\n }\n }\n\n // Now resize this level's bridge windows\nagain:\n for (size_t i = 0; i < bus->bar_count; i++) {\n if (bus->bars[i]->range == NULL) {\n continue;\n }\n\n struct pci_bar *bar = bus->bars[i];\n struct pci_device *device = bar->device;\n struct pci_range *range = bar->range;\n struct pci_bus *bridge_bus = device->bridge_bus;\n\n // Compute required size: sum of regular BARs + sum of (already resized) child bridge windows\n uint64_t new_size = 0;\n for (size_t j = 0; j < bridge_bus->bar_count; j++) {\n struct pci_bar *child_bar = bridge_bus->bars[j];\n if (child_bar->prefetchable != range->prefetchable) {\n continue;\n }\n new_size += child_bar->length;\n }\n\n struct pci_address address;\n address.segment = device->root_bus->segment;\n address.bus = device->root_bus->bus;\n address.slot = device->slot;\n address.function = device->function;\n\n // Read from correct registers based on window type\n uint8_t base_reg = range->prefetchable ? 0x24 : 0x20;\n uint8_t limit_reg = range->prefetchable ? 0x26 : 0x22;\n uint64_t raw_base = pci_read16(&address, base_reg);\n uint64_t raw_limit = pci_read16(&address, limit_reg);\n\n // Only prefetchable windows have the 64-bit type field (bits 0-3)\n bool is_64 = range->prefetchable && ((raw_base & 0xf) == 0x1);\n\n printf(\"new_size=%llx\\n\", new_size);\n\n if (new_size == 0) {\n printf(\"dropping %sprefetchable window of bridge device %04x:%02x:%02x.%02x\\n\",\n range->prefetchable ? \"\" : \"non-\", bus->segment, bus->bus, device->slot, device->function);\n pci_write16(&address, base_reg, 0x10 | (raw_base & 0xf));\n pci_write16(&address, limit_reg, raw_limit & 0xf);\n if (is_64) {\n pci_write32(&address, 0x28, 0);\n pci_write32(&address, 0x2c, 0);\n }\n drop_range(bridge_bus, range);\n drop_bar(bus, bar);\n goto again;\n }\n\n // Round up window size to 1MB (bridge window granularity).\n // The window will be aligned to largest child BAR during relocation,\n // so children will naturally land on aligned addresses.\n new_size = ALIGN_UP(new_size, 0x100000);\n\n printf(\"resizing %sprefetchable window of bridge device %04x:%02x:%02x.%02x from %llx to %llx\\n\",\n range->prefetchable ? \"\" : \"non-\", bus->segment, bus->bus, device->slot, device->function, bar->length, new_size);\n\n uint64_t new_limit = range->base + new_size - 1;\n\n pci_write16(&address, limit_reg,\n ((new_limit >> 16) & 0xfff0) | (raw_limit & 0x000f));\n\n if (is_64) {\n pci_write32(&address, 0x2c, new_limit >> 32);\n }\n\n range->length = new_size;\n bar->length = new_size;\n }\n\n return true;\n}\n\nbool pci_late_initialize(void) {\n for (size_t i = 0; i < root_bus_count; i++) {\n if (!scan_bus(root_buses[i])) {\n printf(\"scan_bus() failure\\n\");\n }\n }\n\n // Save and disable Flanterm during relocation.\n // When we relocate bridge windows, the address range the bridge forwards changes,\n // so accessing the framebuffer at the old address will fail even before we\n // relocate the VGA BAR itself. Disabling Flanterm prevents crashes during this phase.\n uint64_t old_fb_addr = priv.cb_fb.physical_address;\n struct flanterm_context *saved_flanterm_ctx = flanterm_ctx;\n flanterm_ctx = NULL;\n\n for (size_t i = 0; i < root_bus_count; i++) {\n struct pci_bus *bus = root_buses[i];\n\n // Check if this root bus needs relocation\n if (!has_bars_above_4g(bus)) {\n printf(\"Root bus %u: all BARs below 4GB, skipping relocation\\n\", bus->bus);\n continue;\n }\n\n printf(\"Root bus %u: found BARs above 4GB, performing relocation...\\n\", bus->bus);\n\n pretty_print_bus(bus, 0);\n printf(\"---------------\\n\");\n\n resize_bridge_windows(bus);\n sort_bars(bus);\n reallocate_bars(bus);\n\n printf(\"---------------\\n\");\n pretty_print_bus(bus, 0);\n }\n\n // Update Flanterm's framebuffer pointer if it was relocated\n if (saved_flanterm_ctx != NULL && priv.cb_fb.physical_address != old_fb_addr) {\n ((struct flanterm_fb_context *)saved_flanterm_ctx)->framebuffer =\n (void *)(uintptr_t)priv.cb_fb.physical_address;\n }\n\n // Re-enable Flanterm\n flanterm_ctx = saved_flanterm_ctx;\n\n if (priv.cb_fb.physical_address >= 0x100000000ULL) {\n panic(\"Framebuffer at 0x%llx is above 4GB and could not be relocated\\n\",\n priv.cb_fb.physical_address);\n }\n\n return true;\n}\n" }, { "path": "src/pci.h", "content": "#ifndef PCI_H\n#define PCI_H\n\n#include \n#include \n#include \n\nstruct pci_address {\n uint16_t segment;\n uint8_t bus;\n uint8_t slot;\n uint8_t function;\n};\n\nstruct pci_range {\n uint64_t base;\n uint64_t length;\n uint64_t reloc_ptr;\n bool prefetchable;\n};\n\nenum pci_device_type {\n PCI_DEVICE_REGULAR,\n PCI_DEVICE_BRIDGE,\n};\n\nstruct pci_device {\n // Type of the device\n enum pci_device_type type;\n\n // The root bus that this device is on\n struct pci_bus *root_bus;\n\n // A bus if a device is a bridge.\n struct pci_bus *bridge_bus;\n\n // Address of the device on the bus\n uint8_t slot;\n uint8_t function;\n\n int reallocated_windows;\n};\n\nstruct pci_bar {\n // The PCI device that this bar belongs to\n struct pci_device *device;\n\n // The bar number in context of the device\n uint8_t bar_number;\n\n bool is_64;\n bool prefetchable;\n\n // If true, firmware originally placed this BAR in a prefetchable region.\n // This allows non-prefetchable BARs to be relocated to prefetchable ranges\n // if the firmware deemed it safe for this particular device.\n bool firmware_in_prefetchable;\n\n // Base address and size of the bar\n uint64_t base;\n uint64_t length;\n\n // Range associated with bridge window pseudo-BARs.\n struct pci_range *range;\n};\n\n#define PCI_MAX_RANGES_PER_BUS 32\n#define PCI_MAX_DEVICES_PER_BUS 256\n#define PCI_MAX_BARS_PER_BUS 512\n\nstruct pci_bus {\n bool root;\n\n uint32_t segment;\n uint8_t bus;\n\n // Sorted list of address ranges this root bus decodes\n size_t range_count;\n struct pci_range ranges[PCI_MAX_RANGES_PER_BUS];\n\n // List of devices associated with this root bus\n size_t device_count;\n struct pci_device *devices[PCI_MAX_DEVICES_PER_BUS];\n\n // Sorted list of allocated bars associated with this root bus\n size_t bar_count;\n struct pci_bar *bars[PCI_MAX_BARS_PER_BUS];\n\n uint64_t required_prefetchable_size;\n uint64_t required_non_prefetchable_size;\n};\n\n#define pci_read8(address, offset) ((uint8_t)pci_read_config_space((address), (offset), 1))\n#define pci_read16(address, offset) ((uint16_t)pci_read_config_space((address), (offset), 2))\n#define pci_read32(address, offset) pci_read_config_space((address), (offset), 4)\n\n#define pci_write8(address, offset, value) pci_write_config_space((address), (offset), 1, (value))\n#define pci_write16(address, offset, value) pci_write_config_space((address), (offset), 2, (value))\n#define pci_write32(address, offset, value) pci_write_config_space((address), (offset), 4, (value))\n\n// Read `size` bytes (1, 2 or 4) from PCI config space. The access goes through\n// at the requested width so that dword-only RMW does not silently clobber\n// RW1C bits sharing the same dword (e.g. Status next to Command).\nuint32_t pci_read_config_space(struct pci_address *address, uint32_t offset, uint32_t size);\n\n// Write `size` bytes (1, 2 or 4) to PCI config space.\nvoid pci_write_config_space(struct pci_address *address, uint32_t offset, uint32_t size, uint32_t value);\n\n// Discover PCI root buses and devices behind them.\nbool pci_early_initialize(void);\nbool pci_late_initialize(void);\n\n// Force I/O space, memory space, and bus master enable on a device whose\n// option ROM is about to be dispatched. Legacy oproms expect their device\n// fully usable; UEFI may have left bus master off (or even MEM/IO off if\n// the device was inactive in UEFI).\nvoid pci_enable_for_oprom(uint8_t bus, uint8_t devfn);\n\n// Copy the bus numbers of every discovered root bus other than bus 0 into\n// `out` (capacity `cap` bytes). Returns the number of entries written; if\n// the buffer is too small, returns 0 without writing anything.\nsize_t pci_get_extra_root_buses(uint8_t *out, size_t cap);\n\n#endif\n" }, { "path": "src/pir.c", "content": "/*\n * $PIR (PCI IRQ Routing) Table Generation\n *\n * Synthesizes a PCI BIOS Specification 2.1 $PIR table from ACPI _PRT\n * (PCI Routing Table) and _PRS (Possible Resource Settings) evaluations,\n * allocates it below 4 GiB, and points the CSM's IrqRoutingTablePointer at\n * it. SeaBIOS picks up the pointer in handle_csm_0002 and serves it back to\n * legacy callers via INT 1Ah AX=B406h (\"Get PCI IRQ Routing Options\").\n */\n\n#include \n#include \n#include \"csmwrap.h\"\n#include \"pir.h\"\n#include \"io.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define PIR_SIGNATURE 0x52495024 /* \"$PIR\" */\n#define PIR_VERSION 0x0100\n\n/*\n * Per-pin \"any free legacy IRQ\" bitmap used when the actual routing isn't\n * representable in 8259 IRQ space (e.g. a static GSI >= 16, or a link\n * device with no _PRS). Bits 3,4,5,7,9,10,11,12,14,15 - the IRQs\n * traditionally available for PCI assignment on a PC/AT.\n */\n#define LEGACY_PCI_IRQ_BITMAP 0xDEB8\n\n#define MAX_PIR_SLOTS 256\n#define MAX_PCI_BUSES 32\n#define MAX_LINK_DEVICES 32\n\n#pragma pack(1)\nstruct pir_link_info {\n uint8_t link;\n uint16_t bitmap;\n};\n\nstruct pir_slot {\n uint8_t bus;\n uint8_t dev; /* PCI device number << 3 */\n struct pir_link_info pins[4]; /* INTA, INTB, INTC, INTD */\n uint8_t slot_nr;\n uint8_t reserved;\n};\n\nstruct pir_header {\n uint32_t signature;\n uint16_t version;\n uint16_t size;\n uint8_t router_bus;\n uint8_t router_devfunc;\n uint16_t exclusive_irqs;\n uint32_t compatible_devid;\n uint32_t miniport_data;\n uint8_t reserved[11];\n uint8_t checksum;\n};\n#pragma pack()\n\nstruct pci_bus_info {\n uacpi_namespace_node *node;\n uint8_t bus_num;\n};\n\nstatic struct {\n struct pci_bus_info buses[MAX_PCI_BUSES];\n size_t count;\n} pir_buses;\n\nstatic struct pir_slot slots[MAX_PIR_SLOTS];\nstatic size_t slot_count;\n\nstruct link_device_entry {\n uacpi_namespace_node *node;\n uint8_t link_id;\n uint16_t bitmap;\n};\n\nstatic struct {\n struct link_device_entry entries[MAX_LINK_DEVICES];\n size_t count;\n} pir_link_devices;\n\n/* Read PCI vendor ID via legacy PIO; matches the helper in mptable.c. */\nstatic bool pci_device_exists(uint8_t bus, uint8_t dev, uint8_t func)\n{\n uint32_t addr = 0x80000000 | (bus << 16) | (dev << 11) | (func << 8);\n outl(0xCF8, addr);\n uint16_t vendor = inw(0xCFC);\n return vendor != 0xFFFF;\n}\n\n/* Callback for root bridge discovery (PNP0A03 / PNP0A08). */\nstatic uacpi_iteration_decision discover_root_bus_callback(\n void *user, uacpi_namespace_node *node, uacpi_u32 depth)\n{\n (void)user;\n (void)depth;\n\n if (pir_buses.count >= MAX_PCI_BUSES)\n return UACPI_ITERATION_DECISION_CONTINUE;\n\n uacpi_u64 bus_num = 0;\n uacpi_eval_integer(node, \"_BBN\", UACPI_NULL, &bus_num);\n\n /* Skip duplicates (some firmware lists the same bus more than once). */\n for (size_t i = 0; i < pir_buses.count; i++) {\n if (pir_buses.buses[i].bus_num == (uint8_t)bus_num)\n return UACPI_ITERATION_DECISION_CONTINUE;\n }\n\n pir_buses.buses[pir_buses.count].node = node;\n pir_buses.buses[pir_buses.count].bus_num = (uint8_t)bus_num;\n pir_buses.count++;\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\n/* Callback for secondary buses with their own _PRT under a root bridge. */\nstatic uacpi_iteration_decision discover_secondary_callback(\n void *user, uacpi_namespace_node *node, uacpi_u32 node_depth)\n{\n (void)node_depth;\n uint8_t parent_bus = *(uint8_t *)user;\n\n if (pir_buses.count >= MAX_PCI_BUSES)\n return UACPI_ITERATION_DECISION_CONTINUE;\n\n /* Only interested in nodes with their own _PRT (i.e. PCI-PCI bridges). */\n uacpi_namespace_node *prt_node = UACPI_NULL;\n uacpi_status st = uacpi_namespace_node_find(node, \"_PRT\", &prt_node);\n if (st != UACPI_STATUS_OK || !prt_node)\n return UACPI_ITERATION_DECISION_CONTINUE;\n\n uacpi_u64 adr = 0;\n if (uacpi_eval_integer(node, \"_ADR\", UACPI_NULL, &adr) != UACPI_STATUS_OK)\n return UACPI_ITERATION_DECISION_CONTINUE;\n\n uint8_t dev = (adr >> 16) & 0x1F;\n uint8_t func = adr & 0x7;\n if (!pci_device_exists(parent_bus, dev, func))\n return UACPI_ITERATION_DECISION_CONTINUE;\n\n /* Read secondary bus number from PCI bridge config (offset 0x19). */\n uint8_t secondary_bus = pciConfigReadByte(parent_bus, dev, func, 0x19);\n\n pir_buses.buses[pir_buses.count].node = node;\n pir_buses.buses[pir_buses.count].bus_num = secondary_bus;\n pir_buses.count++;\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\nstatic void discover_secondary_buses(uacpi_namespace_node *root_bridge,\n uint8_t parent_bus)\n{\n uacpi_namespace_for_each_child(\n root_bridge,\n discover_secondary_callback,\n UACPI_NULL,\n UACPI_OBJECT_DEVICE_BIT,\n 3,\n &parent_bus);\n}\n\nstatic void discover_pci_buses(void)\n{\n pir_buses.count = 0;\n\n uacpi_namespace_node *sb_node =\n uacpi_namespace_get_predefined(UACPI_PREDEFINED_NAMESPACE_SB);\n if (!sb_node) {\n printf(\"pir: _SB not found, cannot discover PCI buses\\n\");\n return;\n }\n\n const uacpi_char *hids[] = { \"PNP0A03\", \"PNP0A08\", UACPI_NULL };\n uacpi_find_devices_at(sb_node, hids, discover_root_bus_callback, UACPI_NULL);\n\n size_t root_count = pir_buses.count;\n for (size_t i = 0; i < root_count; i++) {\n discover_secondary_buses(pir_buses.buses[i].node,\n pir_buses.buses[i].bus_num);\n }\n}\n\n/* Find the first PCI ISA bridge (class 0x06, subclass 0x01) to use as\n * router. Falls back to (0, 0, 0) - the host bridge - if none found. */\nstatic bool find_isa_bridge(uint8_t *out_bus, uint8_t *out_devfn)\n{\n for (size_t b = 0; b < pir_buses.count; b++) {\n uint8_t bus = pir_buses.buses[b].bus_num;\n for (uint8_t dev = 0; dev < 32; dev++) {\n for (uint8_t func = 0; func < 8; func++) {\n if (!pci_device_exists(bus, dev, func)) {\n if (func == 0) break;\n continue;\n }\n uint8_t class_code = pciConfigReadByte(bus, dev, func, 0x0B);\n uint8_t subclass = pciConfigReadByte(bus, dev, func, 0x0A);\n if (class_code == 0x06 && subclass == 0x01) {\n *out_bus = bus;\n *out_devfn = (uint8_t)((dev << 3) | func);\n return true;\n }\n if (func == 0) {\n uint8_t header = pciConfigReadByte(bus, dev, func, 0x0E);\n if (!(header & 0x80)) break;\n }\n }\n }\n }\n return false;\n}\n\n/* Get an existing slot for (bus, dev) or create a new one. dev is already\n * shifted left by 3 to match the $PIR encoding. */\nstatic struct pir_slot *get_or_create_slot(uint8_t bus, uint8_t dev_shifted)\n{\n for (size_t i = 0; i < slot_count; i++) {\n if (slots[i].bus == bus && slots[i].dev == dev_shifted)\n return &slots[i];\n }\n if (slot_count >= MAX_PIR_SLOTS)\n return NULL;\n\n struct pir_slot *s = &slots[slot_count++];\n memset(s, 0, sizeof(*s));\n s->bus = bus;\n s->dev = dev_shifted;\n return s;\n}\n\n/* Accumulate possible IRQs (< 16) into a 16-bit bitmap from a link\n * device's _PRS. */\nstruct prs_ctx {\n uint16_t bitmap;\n};\n\nstatic uacpi_iteration_decision link_prs_callback(void *user,\n uacpi_resource *resource)\n{\n struct prs_ctx *ctx = user;\n\n if (resource->type == UACPI_RESOURCE_TYPE_IRQ) {\n for (uint8_t i = 0; i < resource->irq.num_irqs; i++) {\n if (resource->irq.irqs[i] < 16)\n ctx->bitmap |= (uint16_t)(1u << resource->irq.irqs[i]);\n }\n } else if (resource->type == UACPI_RESOURCE_TYPE_EXTENDED_IRQ) {\n for (uint8_t i = 0; i < resource->extended_irq.num_irqs; i++) {\n if (resource->extended_irq.irqs[i] < 16)\n ctx->bitmap |= (uint16_t)(1u << resource->extended_irq.irqs[i]);\n }\n }\n return UACPI_ITERATION_DECISION_CONTINUE;\n}\n\n/* Look up an existing link device or assign a new link ID and evaluate _PRS\n * for its possible-IRQ bitmap. Link IDs start at 0x80 to leave the lower\n * range for static-GSI link IDs. */\nstatic uint8_t get_link_id(uacpi_namespace_node *link, uint16_t *bitmap_out)\n{\n for (size_t i = 0; i < pir_link_devices.count; i++) {\n if (pir_link_devices.entries[i].node == link) {\n *bitmap_out = pir_link_devices.entries[i].bitmap;\n return pir_link_devices.entries[i].link_id;\n }\n }\n if (pir_link_devices.count >= MAX_LINK_DEVICES) {\n *bitmap_out = LEGACY_PCI_IRQ_BITMAP;\n return 0;\n }\n\n struct prs_ctx ctx = { .bitmap = 0 };\n uacpi_for_each_device_resource(link, \"_PRS\", link_prs_callback, &ctx);\n if (ctx.bitmap == 0)\n ctx.bitmap = LEGACY_PCI_IRQ_BITMAP;\n\n uint8_t link_id = (uint8_t)(0x80 + pir_link_devices.count);\n pir_link_devices.entries[pir_link_devices.count].node = link;\n pir_link_devices.entries[pir_link_devices.count].link_id = link_id;\n pir_link_devices.entries[pir_link_devices.count].bitmap = ctx.bitmap;\n pir_link_devices.count++;\n\n *bitmap_out = ctx.bitmap;\n return link_id;\n}\n\nbool pir_init(struct csmwrap_priv *priv)\n{\n printf(\"pir: building $PIR table\\n\");\n\n slot_count = 0;\n pir_link_devices.count = 0;\n\n discover_pci_buses();\n if (pir_buses.count == 0) {\n printf(\"pir: no PCI buses discovered, skipping $PIR\\n\");\n return false;\n }\n\n uint8_t router_bus = 0, router_devfunc = 0;\n if (!find_isa_bridge(&router_bus, &router_devfunc)) {\n printf(\"pir: no ISA bridge found, using host bridge as router\\n\");\n }\n\n /* Walk _PRT for each bus; group entries by (bus, dev) into slots. */\n for (size_t bi = 0; bi < pir_buses.count; bi++) {\n struct pci_bus_info *binfo = &pir_buses.buses[bi];\n uacpi_pci_routing_table *prt = NULL;\n if (uacpi_get_pci_routing_table(binfo->node, &prt) != UACPI_STATUS_OK\n || !prt)\n continue;\n\n for (size_t i = 0; i < prt->num_entries; i++) {\n uacpi_pci_routing_table_entry *e = &prt->entries[i];\n uint8_t dev = (uint8_t)((e->address >> 16) & 0x1F);\n uint8_t pin = (uint8_t)e->pin;\n if (pin > 3)\n continue;\n\n struct pir_slot *slot =\n get_or_create_slot(binfo->bus_num, (uint8_t)(dev << 3));\n if (!slot) {\n printf(\"pir: too many slots, truncating\\n\");\n uacpi_free_pci_routing_table(prt);\n goto prt_done;\n }\n\n uint8_t link;\n uint16_t bitmap;\n if (e->source == NULL) {\n /* Static GSI: link ID = GSI (truncated to 8 bits, fine for\n * the typical < 256 GSI range), bitmap reflects the actual\n * IRQ when representable. */\n link = (uint8_t)e->index;\n bitmap = (e->index < 16) ? (uint16_t)(1u << e->index)\n : LEGACY_PCI_IRQ_BITMAP;\n } else {\n link = get_link_id(e->source, &bitmap);\n }\n\n slot->pins[pin].link = link;\n slot->pins[pin].bitmap = bitmap;\n }\n\n uacpi_free_pci_routing_table(prt);\n }\nprt_done:\n\n if (slot_count == 0) {\n printf(\"pir: no _PRT entries found, skipping $PIR\\n\");\n return false;\n }\n\n size_t table_size = sizeof(struct pir_header)\n + slot_count * sizeof(struct pir_slot);\n\n /* Allocate below 4 GiB - IrqRoutingTablePointer is 32 bits.\n * EfiRuntimeServicesData becomes E820 RESERVED so the OS won't reclaim\n * it; SeaBIOS dereferences PirAddr on demand from INT 1Ah callers. */\n EFI_PHYSICAL_ADDRESS table_addr = 0xFFFFFFFF;\n EFI_STATUS status = gBS->AllocatePages(\n AllocateMaxAddress, EfiRuntimeServicesData,\n (table_size + 4095) / 4096, &table_addr);\n if (EFI_ERROR(status)) {\n printf(\"pir: failed to allocate memory for $PIR\\n\");\n return false;\n }\n\n memset((void *)(uintptr_t)table_addr, 0, table_size);\n\n struct pir_header *hdr = (struct pir_header *)(uintptr_t)table_addr;\n hdr->signature = PIR_SIGNATURE;\n hdr->version = PIR_VERSION;\n hdr->size = (uint16_t)table_size;\n hdr->router_bus = router_bus;\n hdr->router_devfunc = router_devfunc;\n hdr->exclusive_irqs = 0;\n hdr->compatible_devid = 0;\n hdr->miniport_data = 0;\n\n struct pir_slot *out_slots = (struct pir_slot *)(hdr + 1);\n memcpy(out_slots, slots, slot_count * sizeof(struct pir_slot));\n\n /* Checksum: sum of all bytes (including checksum field) must be 0. */\n uint8_t sum = 0;\n uint8_t *bytes = (uint8_t *)hdr;\n for (size_t i = 0; i < table_size; i++)\n sum += bytes[i];\n hdr->checksum = (uint8_t)(-sum);\n\n priv->csm_efi_table->IrqRoutingTablePointer = (uint32_t)table_addr;\n priv->csm_efi_table->IrqRoutingTableLength = (uint32_t)table_size;\n\n printf(\"pir: $PIR built at 0x%lx, %zu slots, %zu bytes \"\n \"(router %02x:%02x.%x, %zu link device(s))\\n\",\n (unsigned long)table_addr, slot_count, table_size,\n router_bus, router_devfunc >> 3, router_devfunc & 7,\n pir_link_devices.count);\n\n return true;\n}\n" }, { "path": "src/pir.h", "content": "#ifndef _PIR_H\n#define _PIR_H\n\n#include \n\n#include \"csmwrap.h\"\n\n/*\n * Build a $PIR (PCI IRQ Routing) table from ACPI _PRT and _PRS evaluations,\n * allocate it below 4 GiB, and write the address/length into the CSM's\n * EFI_COMPATIBILITY16_TABLE so SeaBIOS can hand it out via INT 1Ah AX=B406h.\n *\n * Must be called before ExitBootServices (uses gBS->AllocatePages and uACPI).\n * Returns true on success, false if no _PRT entries were found or allocation\n * failed - in which case the field stays zero and SeaBIOS reports the\n * function as unsupported.\n */\nbool pir_init(struct csmwrap_priv *priv);\n\n#endif /* _PIR_H */\n" }, { "path": "src/printf.c", "content": "#include \n#include \n#include \n#include \n\n#define NANOPRINTF_IMPLEMENTATION\n#define NANOPRINTF_USE_FIELD_WIDTH_FORMAT_SPECIFIERS 1\n#define NANOPRINTF_USE_PRECISION_FORMAT_SPECIFIERS 0\n#define NANOPRINTF_USE_FLOAT_FORMAT_SPECIFIERS 0\n#define NANOPRINTF_USE_LARGE_FORMAT_SPECIFIERS 1\n#define NANOPRINTF_USE_SMALL_FORMAT_SPECIFIERS 1\n#define NANOPRINTF_USE_BINARY_FORMAT_SPECIFIERS 1\n#define NANOPRINTF_USE_WRITEBACK_FORMAT_SPECIFIERS 1\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\nstruct flanterm_context *flanterm_ctx = NULL;\n\nstatic EFI_SERIAL_IO_PROTOCOL *serial_protocol = NULL;\nstatic bool serial_protocol_init_done = false;\nstatic bool direct_io_initialised = false;\n\nstatic void serial_protocol_initialise(void) {\n if (serial_protocol_init_done) {\n return;\n }\n serial_protocol_init_done = true;\n\n EFI_GUID serial_guid = EFI_SERIAL_IO_PROTOCOL_GUID;\n if (gBS->LocateProtocol(&serial_guid, NULL, (void **)&serial_protocol)) {\n serial_protocol = NULL;\n return;\n }\n\n serial_protocol->Reset(serial_protocol);\n serial_protocol->SetAttributes(\n serial_protocol,\n gConfig.serial_baud,\n 0, /* ReceiveFifoDepth (default) */\n 0, /* Timeout (default) */\n NoParity, /* Parity */\n 8, /* DataBits */\n OneStopBit /* StopBits */\n );\n}\n\nstatic void serial_direct_io_initialise(void) {\n if (direct_io_initialised) {\n return;\n }\n\n uint16_t port = gConfig.serial_port;\n\n outb(port + 3, 0x00);\n outb(port + 1, 0x00);\n outb(port + 3, 0x80);\n\n uint16_t divisor = (uint16_t)(115200 / gConfig.serial_baud);\n if (divisor == 0) divisor = 1;\n outb(port + 0, divisor & 0xff);\n outb(port + 1, (divisor >> 8) & 0xff);\n\n /* port+1 is DLM while DLAB=1; clear DLAB before treating it as IER. */\n outb(port + 3, 0x03);\n outb(port + 2, 0xc7);\n outb(port + 4, 0x0b);\n\n direct_io_initialised = true;\n}\n\nstatic void serial_out(uint8_t b) {\n if (gBootServicesExited) {\n serial_direct_io_initialise();\n\n uint16_t port = gConfig.serial_port;\n while ((inb(port + 5) & 0x20) == 0);\n outb(port, b);\n return;\n }\n\n serial_protocol_initialise();\n if (serial_protocol == NULL) {\n return;\n }\n\n UINTN buf_size = 1;\n serial_protocol->Write(serial_protocol, &buf_size, &b);\n}\n\nstatic void _putchar(int character, void *extra_arg) {\n (void)extra_arg;\n\n if (character == '\\n') {\n _putchar('\\r', NULL);\n }\n\n if (gConfig.serial_debug) {\n serial_out((uint8_t)character);\n }\n\n if (gConfig.verbose && flanterm_ctx != NULL) {\n flanterm_write(flanterm_ctx, (const char *)&character, 1);\n }\n}\n\nint printf(const char *restrict fmt, ...) {\n va_list l;\n va_start(l, fmt);\n int ret = npf_vpprintf(_putchar, NULL, fmt, l);\n va_end(l);\n return ret;\n}\n\nint vprintf(const char *restrict fmt, va_list l) {\n return npf_vpprintf(_putchar, NULL, fmt, l);\n}\n\nint snprintf(char *buffer, size_t bufsz, const char *restrict fmt, ...) {\n va_list l;\n va_start(l, fmt);\n int ret = npf_vsnprintf(buffer, bufsz, fmt, l);\n va_end(l);\n return ret;\n}\n" }, { "path": "src/printf.h", "content": "#ifndef PRINTF_H\n#define PRINTF_H\n\n#include \n#include \n#include \n\nextern struct flanterm_context *flanterm_ctx;\n\nint printf(const char *restrict fmt, ...);\nint vprintf(const char *restrict fmt, va_list l);\nint snprintf(char *buffer, size_t bufsz, const char *restrict fmt, ...);\n\n#endif\n" }, { "path": "src/qsort.c", "content": "#include \n\n// Function to swap two elements\nstatic void swap(void* a, void* b, size_t size) {\n char buf[16];\n char *ca = a, *cb = b;\n while (size > 0) {\n size_t chunk = size < sizeof(buf) ? size : sizeof(buf);\n memcpy(buf, ca, chunk);\n memcpy(ca, cb, chunk);\n memcpy(cb, buf, chunk);\n ca += chunk;\n cb += chunk;\n size -= chunk;\n }\n}\n\n// Partition function\nstatic int partition(void* base, size_t size, int (*cmp)(const void*, const void*), int low, int high) {\n char* arr = (char*)base;\n void* pivot = arr + high * size; // Choosing the last element as pivot\n int i = low - 1; // Index of smaller element\n\n for (int j = low; j < high; j++) {\n if (cmp(arr + j * size, pivot) <= 0) {\n i++;\n swap(arr + i * size, arr + j * size, size);\n }\n }\n swap(arr + (i + 1) * size, arr + high * size, size);\n return (i + 1);\n}\n\n// Quick Sort function\nstatic void quick_sort(void* base, size_t size, int (*cmp)(const void*, const void*), int low, int high) {\n if (low < high) {\n int pi = partition(base, size, cmp, low, high);\n quick_sort(base, size, cmp, low, pi - 1);\n quick_sort(base, size, cmp, pi + 1, high);\n }\n}\n\n// Public interface function\nvoid qsort(void* ptr, size_t count, size_t size, int (*comp)(const void*, const void*)) {\n if (count < 2) {\n return;\n }\n quick_sort(ptr, size, comp, 0, (int)(count - 1));\n}\n" }, { "path": "src/qsort.h", "content": "#ifndef QSORT_H\n#define QSORT_H\n\n#include \n\nvoid qsort(void *ptr, size_t count, size_t size, int (*comp)(const void *, const void *));\n\n#endif\n" }, { "path": "src/time.c", "content": "#include \n#include \n#include \n#include \n\nuint64_t tsc_freq; /* TSC ticks per second */\nstatic uint64_t tsc_boot; /* TSC value at calibration time */\n\n/*\n * Try to determine TSC frequency from CPUID leaves.\n * Returns frequency in Hz, or 0 if not available.\n */\nstatic uint64_t tsc_freq_from_cpuid(void) {\n uint32_t eax, ebx, ecx, edx;\n\n /* Check max CPUID leaf */\n asm volatile(\"cpuid\" : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx) : \"a\"(0), \"c\"(0));\n uint32_t max_leaf = eax;\n\n /* CPUID leaf 0x15: TSC/Crystal ratio and crystal frequency */\n if (max_leaf >= 0x15) {\n asm volatile(\"cpuid\" : \"=a\"(eax), \"=b\"(ebx), \"=c\"(ecx), \"=d\"(edx) : \"a\"(0x15), \"c\"(0));\n if (eax != 0 && ebx != 0 && ecx != 0) {\n return (uint64_t)ecx * ebx / eax;\n }\n }\n\n return 0;\n}\n\n/*\n * Calibrate TSC frequency.\n * Prefers CPUID-based detection; falls back to gBS->Stall() calibration.\n * Must be called before ExitBootServices.\n */\nvoid calibrate_tsc(void) {\n tsc_freq = tsc_freq_from_cpuid();\n\n if (tsc_freq == 0) {\n uint64_t start = rdtsc();\n gBS->Stall(1000); /* 1ms */\n uint64_t end = rdtsc();\n tsc_freq = (end - start) * 1000;\n }\n\n tsc_boot = rdtsc();\n}\n\nuint64_t get_nanoseconds_since_boot(void) {\n if (tsc_freq == 0)\n return 0;\n uint64_t elapsed = rdtsc() - tsc_boot;\n uint64_t usec = elapsed / tsc_freq * 1000000\n + elapsed % tsc_freq * 1000000 / tsc_freq;\n return usec * 1000;\n}\n\nvoid stall(uint64_t us) {\n uint64_t next_stop = rdtsc() + (tsc_freq * us + 999999) / 1000000;\n while (rdtsc() < next_stop);\n}\n" }, { "path": "src/time.h", "content": "#ifndef _TIME_H\n#define _TIME_H\n\n#include \n\nextern uint64_t tsc_freq;\n\nvoid calibrate_tsc(void);\nuint64_t get_nanoseconds_since_boot(void);\nvoid stall(uint64_t us);\n\n#endif\n" }, { "path": "src/uacpi_config.h", "content": "#pragma once\n\n#include \n#include \n\n\n#define UACPI_DEFAULT_LOG_LEVEL UACPI_LOG_INFO\n#define UACPI_DEFAULT_LOOP_TIMEOUT_SECONDS 30\n#define UACPI_DEFAULT_MAX_CALL_STACK_DEPTH 256\n\n#define UACPI_USE_BUILTIN_STRING\n#ifndef __LP64__\n#define UACPI_PHYS_ADDR_IS_32BITS\n#endif\n#define UACPI_PLAIN_LOG_BUFFER_SIZE 128\n#define UACPI_STATIC_TABLE_ARRAY_LEN 128\n" }, { "path": "src/unlock_region.c", "content": "/*\n * legacy_region_unlock.c\n *\n * Implementation of BIOS region unlocking using the UEFI Legacy Region 2 Protocol\n * with fallback to direct PCI configuration space access for specific chipsets.\n */\n\n#include \n#include \n#include \"csmwrap.h\"\n#include \"edk2/LegacyRegion2.h\"\n#include \"io.h\"\n\nstatic EFI_GUID gEfiLegacyRegion2ProtocolGuid = EFI_LEGACY_REGION2_PROTOCOL_GUID;\n\n/*\n* Intel chipset PCI configuration register addresses for PAM \n* (Programmable Attribute Map) controls\n*/\n#define PAM0_REGISTER 0x90 /* Q35 chipset */\n#define PAM_LOCK_BIT 0x01 /* Bit indicating PAM registers are locked */\n#define PAM_LOCK_REG 0x80 /* Register containing PAM lock bit on newer Intel chipsets */\n#define PAM_ENABLE 0x33 /* bits[1:0]=11 (LOENABLE R+W), bits[5:4]=11 (HIENABLE R+W) */\n#define PAM0_ENABLE 0x30 /* PAM0 only has HIENABLE; bits[3:0] are reserved/lock */\n\n\n/*\n * AMD MTRRs for Legacy Region\n * This is already here since AMD64\n */\n#define AMD_AP_MTRR_VARIABLE_BASE0 0x200\n#define AMD_AP_MTRR_VARIABLE_BASE6 0x20C\n#define AMD_AP_MTRR_FIX64k_00000 0x250\n#define AMD_AP_MTRR_FIX16k_80000 0x258\n#define AMD_AP_MTRR_FIX16k_A0000 0x259\n#define AMD_AP_MTRR_FIX4k_C0000 0x268\n#define AMD_AP_MTRR_FIX4k_C8000 0x269\n#define AMD_AP_MTRR_FIX4k_D0000 0x26A\n#define AMD_AP_MTRR_FIX4k_D8000 0x26B\n#define AMD_AP_MTRR_FIX4k_E0000 0x26C\n#define AMD_AP_MTRR_FIX4k_E8000 0x26D\n#define AMD_AP_MTRR_FIX4k_F0000 0x26E\n#define AMD_AP_MTRR_FIX4k_F8000 0x26F\n\n#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull\n#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull\n#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull\n#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull\n#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull\n#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull\n#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull\n#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull\n#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull\n\n#define MSR_SYS_CFG 0xC0010010ul\n#define SYS_CFG_MTRR_FIX_DRAM_EN (1 << 18) ///< Core::X86::Msr::SYS_CFG::MtrrFixDramEn.\n ///< MTRR fixed RdDram and WrDram attributes enable.\n#define SYS_CFG_MTRR_FIX_DRAM_MOD_EN (1 << 19) ///< Core::X86::Msr::SYS_CFG::MtrrFixDramModEn.\n ///< MTRR fixed RdDram and WrDram modification enable.\n#define SYS_CFG_MTRR_VAR_DRAM_EN (1 << 20) ///< Core::X86::Msr::SYS_CFG::MtrrVarDramEn.\n ///< MTRR variable DRAM enable.\n#define SYS_CFG_MTRR_TOM2_EN (1 << 21) ///< Core::X86::Msr::SYS_CFG::MtrrTom2En. MTRR\n ///< top of memory 2 enable.\n#define SYS_CFG_TOM2_FORCE_MEM_TYPE_WB (1 << 22) ///< Core::X86::Msr::SYS_CFG::Tom2ForceMemTypeWB.\n ///< top of memory 2 memory type write back.\n\n/* Intel PCI Vendor ID */\n#define INTEL_VENDOR_ID 0x8086\n\n/* AMD Vendor ID */\n#define AMD_VENDOR_ID 0x1022\n\n/**\n * Unlock BIOS memory region using the Legacy Region 2 Protocol\n *\n * @return EFI_SUCCESS on success, or an error status code on failure\n */\nEFI_STATUS unlock_legacy_region_protocol(void)\n{\n EFI_LEGACY_REGION2_PROTOCOL *legacy_region = NULL;\n EFI_STATUS status;\n uint32_t granularity;\n\n /* Look for the Legacy Region 2 Protocol */\n status = gBS->LocateProtocol(\n &gEfiLegacyRegion2ProtocolGuid,\n NULL,\n (void **)&legacy_region\n );\n\n if (EFI_ERROR(status)) {\n printf(\"Legacy Region 2 Protocol not found (status: %lx)\\n\", status);\n return status;\n }\n\n /*\n * Unlock the entire legacy BIOS region (0xC0000 to 0xFFFFF)\n * Each region covers 64KB\n */\n\n /* First enable memory reads in the region */\n bool on = TRUE;\n status = legacy_region->Decode(\n legacy_region,\n 0xC0000, /* Start address */\n 0x40000, /* Length (256KB) */\n &granularity,\n &on\n );\n \n if (EFI_ERROR(status)) {\n printf(\"Failed to enable memory reads in legacy region (status: %lx)\\n\", status);\n return status;\n }\n\n /* Then enable memory writes in the region */\n status = legacy_region->UnLock(\n legacy_region,\n 0xC0000, /* Start address */\n 0x40000, /* Length (256KB) */\n &granularity\n );\n\n if (EFI_ERROR(status)) {\n printf(\"Failed to enable memory writes in legacy region (status: %lx)\\n\", status);\n return status;\n }\n \n printf(\"Successfully unlocked legacy region 0xC0000-0xFFFFF using UEFI protocol\\n\");\n printf(\"Granularity: 0x%x bytes\\n\", granularity);\n\n return EFI_SUCCESS;\n}\n\n/**\n * Unlock BIOS region using direct PCI configuration space access for piix4 chipset\n *\n * @return 0 on success, -1 on failure\n */\nint unlock_piix4_pam(void)\n{\n printf(\"Unlocking BIOS region with PIIX4 PAM\\n\");\n\n /* Enable read+write for PAM0-PAM6 (0x59-0x5F) */\n pciConfigWriteByte(0, 0, 0, 0x59, PAM0_ENABLE); /* PAM0: 0xF0000-0xFFFFF */\n pciConfigWriteByte(0, 0, 0, 0x5a, PAM_ENABLE); /* PAM1: 0xC0000-0xC7FFF */\n pciConfigWriteByte(0, 0, 0, 0x5b, PAM_ENABLE); /* PAM2: 0xC8000-0xCFFFF */\n pciConfigWriteByte(0, 0, 0, 0x5c, PAM_ENABLE); /* PAM3: 0xD0000-0xD7FFF */\n pciConfigWriteByte(0, 0, 0, 0x5d, PAM_ENABLE); /* PAM4: 0xD8000-0xDFFFF */\n pciConfigWriteByte(0, 0, 0, 0x5e, PAM_ENABLE); /* PAM5: 0xE0000-0xE7FFF */\n pciConfigWriteByte(0, 0, 0, 0x5f, PAM_ENABLE); /* PAM6: 0xE8000-0xEFFFF */\n\n return 0;\n}\n\n/**\n * Unlock BIOS region using direct PCI configuration space access for Q35 chipset\n *\n * @return 0 on success, -1 on failure\n */\nint unlock_q35_pam(void)\n{\n printf(\"Unlocking BIOS region with Q35 PAM\\n\");\n\n /* Enable read+write for PAM0-PAM6 (0x90-0x96) */\n pciConfigWriteByte(0, 0, 0, 0x90, PAM0_ENABLE); /* PAM0: 0xF0000-0xFFFFF */\n pciConfigWriteByte(0, 0, 0, 0x91, PAM_ENABLE); /* PAM1: 0xC0000-0xC7FFF */\n pciConfigWriteByte(0, 0, 0, 0x92, PAM_ENABLE); /* PAM2: 0xC8000-0xCFFFF */\n pciConfigWriteByte(0, 0, 0, 0x93, PAM_ENABLE); /* PAM3: 0xD0000-0xD7FFF */\n pciConfigWriteByte(0, 0, 0, 0x94, PAM_ENABLE); /* PAM4: 0xD8000-0xDFFFF */\n pciConfigWriteByte(0, 0, 0, 0x95, PAM_ENABLE); /* PAM5: 0xE0000-0xE7FFF */\n pciConfigWriteByte(0, 0, 0, 0x96, PAM_ENABLE); /* PAM6: 0xE8000-0xEFFFF */\n\n return 0;\n}\n\n/**\n * Unlock BIOS region using direct PCI configuration space access for Intel\n * Sandy Bridge and later host bridges (PAM at D0:F0 offsets 0x80-0x86,\n * with PAM-LCK at PAM0 bit 0).\n *\n * @return 0 on success, -1 on failure\n */\nint unlock_sandybridge_pam(void)\n{\n printf(\"Unlocking BIOS region with Intel Sandy Bridge+ PAM\\n\");\n\n /* Check if PAM is locked */\n if (pciConfigReadByte(0, 0, 0, PAM_LOCK_REG) & PAM_LOCK_BIT) {\n printf(\"PAM is locked on your platform\\n\");\n return -1;\n }\n\n /* Enable read+write for PAM0-PAM6 (0x80-0x86) */\n pciConfigWriteByte(0, 0, 0, 0x80, PAM0_ENABLE); /* PAM0: 0xF0000-0xFFFFF */\n pciConfigWriteByte(0, 0, 0, 0x81, PAM_ENABLE); /* PAM1: 0xC0000-0xC7FFF */\n pciConfigWriteByte(0, 0, 0, 0x82, PAM_ENABLE); /* PAM2: 0xC8000-0xCFFFF */\n pciConfigWriteByte(0, 0, 0, 0x83, PAM_ENABLE); /* PAM3: 0xD0000-0xD7FFF */\n pciConfigWriteByte(0, 0, 0, 0x84, PAM_ENABLE); /* PAM4: 0xD8000-0xDFFFF */\n pciConfigWriteByte(0, 0, 0, 0x85, PAM_ENABLE); /* PAM5: 0xE0000-0xE7FFF */\n pciConfigWriteByte(0, 0, 0, 0x86, PAM_ENABLE); /* PAM6: 0xE8000-0xEFFFF */\n\n return 0;\n}\n\n/**\n * Unlock BIOS region using fixed MTRR for AMD chipsets\n *\n * @return 0 on success, -1 on failure\n */\nint unlock_amd_mtrr(void)\n{\n uint64_t val;\n unsigned long flags, cr0, cr4;\n printf(\"Unlocking BIOS region with AMD MTRR\\n\");\n\n /* AMD APM Vol 2 §7.6.3: disable cache, flush, modify MTRRs, flush, restore.\n * Required so stale cache lines and TLB entries don't outlive the change. */\n asm volatile (\"pushf; pop %0; cli\" : \"=rm\"(flags) :: \"memory\");\n asm volatile (\"mov %%cr0, %0\" : \"=r\"(cr0));\n asm volatile (\"mov %0, %%cr0\" :: \"r\"(cr0 | (1UL << 30))); /* CD = 1 */\n asm volatile (\"wbinvd\");\n asm volatile (\"mov %%cr4, %0\" : \"=r\"(cr4));\n if (cr4 & (1UL << 7)) { /* PGE */\n asm volatile (\"mov %0, %%cr4\" :: \"r\"(cr4 & ~(1UL << 7)));\n }\n\n /* Enable MTRR modification: set SYS_CFG.MtrrFixDramModEn (bit 19) */\n val = rdmsr(MSR_SYS_CFG);\n val |= SYS_CFG_MTRR_FIX_DRAM_MOD_EN;\n wrmsr(MSR_SYS_CFG, val);\n\n /* Set all to WB */\n wrmsr(AMD_AP_MTRR_FIX64k_00000, AMD_MTRR_FIX64K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX16k_80000, AMD_MTRR_FIX16K_WB_DRAM);\n /* A0000 map to UC IO */\n wrmsr(AMD_AP_MTRR_FIX16k_A0000, 0x0);\n wrmsr(AMD_AP_MTRR_FIX4k_C0000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_C8000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_D0000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_D8000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_E0000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_E8000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_F0000, AMD_MTRR_FIX4K_WB_DRAM);\n wrmsr(AMD_AP_MTRR_FIX4k_F8000, AMD_MTRR_FIX4K_WB_DRAM);\n\n val = rdmsr(MSR_SYS_CFG);\n val &= ~SYS_CFG_MTRR_FIX_DRAM_MOD_EN;\n val |= SYS_CFG_MTRR_FIX_DRAM_EN;\n wrmsr(MSR_SYS_CFG, val);\n\n asm volatile (\"wbinvd\");\n asm volatile (\"mov %0, %%cr0\" :: \"r\"(cr0));\n asm volatile (\"mov %0, %%cr4\" :: \"r\"(cr4));\n asm volatile (\"push %0; popf\" :: \"rm\"(flags) : \"memory\", \"cc\");\n\n return 0;\n}\n\n/**\n * Get information about the legacy region and display it\n *\n * @param legacy_region Legacy Region 2 Protocol instance\n * @return EFI_SUCCESS on success, or an error status code on failure\n */\nEFI_STATUS print_legacy_region_info(EFI_LEGACY_REGION2_PROTOCOL *legacy_region)\n{\n EFI_STATUS status;\n uint32_t descriptor_count = 0;\n EFI_LEGACY_REGION_DESCRIPTOR *descriptors = NULL;\n \n status = legacy_region->GetInfo(\n legacy_region,\n &descriptor_count,\n &descriptors\n );\n \n if (EFI_ERROR(status)) {\n printf(\"Failed to get legacy region information (status: %lx)\\n\", status);\n return status;\n }\n\n printf(\"Legacy Region Information:\\n\");\n printf(\"Found %u region descriptors\\n\", descriptor_count);\n\n for (uint32_t i = 0; i < descriptor_count; i++) {\n printf(\"Region %u: 0x%08x-0x%08x, Granularity: 0x%x bytes\\n\",\n i,\n descriptors[i].Start,\n descriptors[i].Start + descriptors[i].Length - 1,\n descriptors[i].Granularity);\n\n printf(\" Attribute: \");\n switch (descriptors[i].Attribute) {\n case LegacyRegionDecoded:\n printf(\"Read Enabled\\n\");\n break;\n case LegacyRegionNotDecoded:\n printf(\"Read Disabled\\n\");\n break;\n case LegacyRegionWriteEnabled:\n printf(\"Write Enabled\\n\");\n break;\n case LegacyRegionWriteDisabled:\n printf(\"Write Disabled\\n\");\n break;\n case LegacyRegionBootLocked:\n printf(\"Boot Locked\\n\");\n break;\n case LegacyRegionNotLocked:\n printf(\"Not Locked\\n\");\n break;\n default:\n printf(\"Unknown\\n\");\n break;\n }\n }\n\n return EFI_SUCCESS;\n}\n\nstatic bool test_bios_region_rw(void) {\n uint32_t *bios_region = (uint32_t *)BIOSROM_START;\n uint32_t *bios_region_end = (uint32_t *)BIOSROM_END;\n uint32_t *ptr = bios_region;\n\n while (ptr < bios_region_end) {\n clflush(ptr);\n uint32_t val = readl(ptr);\n\n writel(ptr, ~val);\n clflush(ptr);\n\n if (readl(ptr) != ~val) {\n printf(\"Unable to write to BIOS region\\n\");\n return false;\n }\n\n writel(ptr, val);\n ptr++;\n }\n\n return true;\n}\n\n/**\n * Main function to unlock the BIOS region\n * Tries to use the UEFI protocol first, then falls back to chipset-specific methods\n *\n * @return 0 on success, non-zero on failure\n */\nint unlock_bios_region(void)\n{\n EFI_LEGACY_REGION2_PROTOCOL *legacy_region = NULL;\n EFI_STATUS status;\n\n // No need to do anything if the region is already unlocked and working.\n if (test_bios_region_rw()) {\n return 0;\n }\n\n /* First, try to use the Legacy Region 2 Protocol */\n status = gBS->LocateProtocol(\n &gEfiLegacyRegion2ProtocolGuid,\n NULL,\n (void **)&legacy_region\n );\n\n if (!EFI_ERROR(status)) {\n /* If we have the protocol, print region information for debugging */\n print_legacy_region_info(legacy_region);\n \n /* Try to unlock using the protocol */\n status = unlock_legacy_region_protocol();\n if (!EFI_ERROR(status) && test_bios_region_rw()) {\n return 0; /* Success */\n }\n\n /* Protocol method failed, fall back to chipset-specific methods */\n printf(\"Protocol method failed, trying chipset-specific methods\\n\");\n } else {\n printf(\"Legacy Region 2 Protocol not found, trying chipset-specific methods\\n\");\n }\n\n /* Check for known chipsets and use appropriate method */\n uint32_t host_bridge_id = pciConfigReadDWord(0, 0, 0, 0x0);\n printf(\"Host Bridge ID: 0x%08x\\n\", host_bridge_id);\n uint16_t vendor_id = (host_bridge_id & 0xFFFF);\n uint16_t device_id = (host_bridge_id >> 16) & 0xFFFF;\n\n switch (vendor_id) {\n case INTEL_VENDOR_ID:\n switch (device_id) {\n case 0x1237: /* 440FX (QEMU) */\n case 0x7190: /* 440BX/ZX/DX (VMware) */\n case 0x71A0: /* 440GX */\n case 0x7194: /* 440MX */\n case 0x7180: /* 440LX/EX */\n status = unlock_piix4_pam();\n break;\n case 0x29C0: /* Q35 (QEMU) */\n case 0x29E0: /* X38/X48 (VirtualBox) */\n status = unlock_q35_pam();\n break;\n default:\n status = unlock_sandybridge_pam();\n break;\n }\n break;\n case AMD_VENDOR_ID:\n /* AMD chipsets */\n status = unlock_amd_mtrr();\n break;\n default:\n status = EFI_UNSUPPORTED;\n printf(\"Unknown chipset, unable to unlock BIOS region\\n\");\n break;\n }\n\n return (status == 0 && test_bios_region_rw()) ? 0 : -1;\n}\n" }, { "path": "src/video.c", "content": "#include \n#include \n#include \n#include \n#include \n#include \n\n// Generated by: xxd -i vgabios.bin >> vgabios.h\n#include \n\nvoid *vbios_loc = NULL;\nuintptr_t vbios_size;\n\n/* Forward declaration */\nstatic bool is_amd_rdna_or_newer(uint16_t vendor_id, uint16_t device_id);\n\n/*\n * Calculate bits per pixel from linear pixel masks.\n * Ported from Limine.\n */\nstatic uint16_t linear_masks_to_bpp(uint32_t red_mask, uint32_t green_mask,\n uint32_t blue_mask, uint32_t alpha_mask)\n{\n uint32_t compound_mask = red_mask | green_mask | blue_mask | alpha_mask;\n if (compound_mask == 0)\n return 0;\n uint16_t ret = 32;\n while ((compound_mask & (1U << 31)) == 0) {\n ret--;\n compound_mask <<= 1;\n }\n return ret;\n}\n\n/* True if Gop->Mode points at a directly-usable linear framebuffer. Checks\n * are run against the current Gop->Mode without calling SetMode, so this is\n * safe to call before deciding whether to disturb the firmware's mode. */\nstatic bool gop_mode_usable(EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop)\n{\n if (Gop->Mode == NULL || Gop->Mode->Info == NULL)\n return false;\n if (Gop->Mode->FrameBufferBase == 0)\n return false;\n\n EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *mi = Gop->Mode->Info;\n\n if (mi->PixelFormat >= PixelBltOnly)\n return false;\n\n if (mi->PixelFormat == PixelBitMask\n && (mi->PixelInformation.RedMask\n | mi->PixelInformation.GreenMask\n | mi->PixelInformation.BlueMask\n | mi->PixelInformation.ReservedMask) == 0)\n return false;\n\n if (mi->PixelsPerScanLine < mi->HorizontalResolution)\n return false;\n\n return true;\n}\n\n/*\n * Find a GOP with a valid framebuffer and set its mode.\n * This is needed for Flanterm and SeaVGABIOS framebuffer access.\n */\nstatic EFI_STATUS FindGop(struct csmwrap_priv *priv)\n{\n EFI_STATUS Status;\n EFI_HANDLE *HandleBuffer;\n UINTN HandleCount;\n EFI_GUID gopGuid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID;\n EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop;\n\n Status = gBS->LocateHandleBuffer(\n ByProtocol,\n &gopGuid,\n NULL,\n &HandleCount,\n &HandleBuffer\n );\n if (EFI_ERROR(Status)) {\n printf(\"Failed to locate GOP handles: %d\\n\", Status);\n return Status;\n }\n\n // Iterate through each GOP handle, find one with valid FrameBufferBase\n for (UINTN i = 0; i < HandleCount; i++) {\n Status = gBS->HandleProtocol(\n HandleBuffer[i],\n &gopGuid,\n (VOID**)&Gop\n );\n if (EFI_ERROR(Status)) {\n continue;\n }\n\n // Initialize GOP if not started (Limine pattern: QueryMode may return\n // EFI_NOT_STARTED, kick it with SetMode(0) and re-query).\n EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *modeInfo;\n UINTN modeInfoSize;\n UINTN currentMode = Gop->Mode == NULL ? 0 : Gop->Mode->Mode;\n\n Status = Gop->QueryMode(Gop, currentMode, &modeInfoSize, &modeInfo);\n if (Status == EFI_NOT_STARTED) {\n Status = Gop->SetMode(Gop, 0);\n if (EFI_ERROR(Status)) {\n continue;\n }\n currentMode = Gop->Mode == NULL ? 0 : Gop->Mode->Mode;\n Status = Gop->QueryMode(Gop, currentMode, &modeInfoSize, &modeInfo);\n }\n if (EFI_ERROR(Status)) {\n continue;\n }\n\n /* Prefer the firmware's current mode to avoid blanking and resizing\n * the user's display. Only enumerate-and-SetMode if it isn't usable. */\n bool found = gop_mode_usable(Gop);\n if (!found) {\n UINTN maxMode = Gop->Mode->MaxMode;\n for (UINTN mode = 0; mode < maxMode; mode++) {\n Status = Gop->SetMode(Gop, mode);\n if (EFI_ERROR(Status))\n continue;\n if (gop_mode_usable(Gop)) {\n found = true;\n break;\n }\n }\n }\n\n if (!found) {\n continue;\n }\n\n priv->gop = Gop;\n priv->gop_handle = HandleBuffer[i];\n break;\n }\n\n gBS->FreePool(HandleBuffer);\n\n if (priv->gop == NULL) {\n printf(\"No GOP with valid framebuffer found\\n\");\n return EFI_NOT_FOUND;\n }\n\n return EFI_SUCCESS;\n}\n\n/*\n * Populate priv VGA PCI fields from a PCI I/O protocol handle.\n */\nstatic void PopulateVgaPciInfo(struct csmwrap_priv *priv, EFI_PCI_IO_PROTOCOL *PciIo)\n{\n UINT16 VendorId, DeviceId;\n UINTN Seg, Bus, Device, Function;\n\n priv->vga_pci_io = PciIo;\n\n PciIo->GetLocation(PciIo, &Seg, &Bus, &Device, &Function);\n\n priv->vga_pci_bus = (UINT8)Bus;\n priv->vga_pci_devfn = (UINT8)(Device << 3 | Function);\n\n PciIo->Pci.Read(PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId);\n PciIo->Pci.Read(PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId);\n\n priv->vga_vendor_id = VendorId;\n priv->vga_device_id = DeviceId;\n\n printf(\"VGA PCI: %04x:%02x:%02x.%x %04x:%04x\\n\",\n Seg, (UINT8)Bus, (UINT8)Device, (UINT8)Function,\n VendorId, DeviceId);\n}\n\n/*\n * Find a PCI device by bus/device/function and return its PCI I/O protocol.\n */\nstatic EFI_STATUS FindPciDevice(uint8_t bus, uint8_t device, uint8_t function,\n EFI_PCI_IO_PROTOCOL **OutPciIo)\n{\n EFI_STATUS Status;\n EFI_HANDLE *HandleBuffer;\n UINTN HandleCount;\n EFI_GUID PciIoGuid = EFI_PCI_IO_PROTOCOL_GUID;\n\n Status = gBS->LocateHandleBuffer(ByProtocol, &PciIoGuid, NULL,\n &HandleCount, &HandleBuffer);\n if (EFI_ERROR(Status))\n return Status;\n\n for (UINTN i = 0; i < HandleCount; i++) {\n EFI_PCI_IO_PROTOCOL *PciIo;\n Status = gBS->HandleProtocol(HandleBuffer[i], &PciIoGuid, (VOID **)&PciIo);\n if (EFI_ERROR(Status))\n continue;\n\n UINTN Seg, Bus, Device, Function;\n PciIo->GetLocation(PciIo, &Seg, &Bus, &Device, &Function);\n\n if ((uint8_t)Bus == bus &&\n (uint8_t)Device == device &&\n (uint8_t)Function == function) {\n *OutPciIo = PciIo;\n gBS->FreePool(HandleBuffer);\n return EFI_SUCCESS;\n }\n }\n\n gBS->FreePool(HandleBuffer);\n return EFI_NOT_FOUND;\n}\n\n/*\n * Find PCI device info for VGA output.\n *\n * If a specific VGA device is configured, locate it by PCI address.\n * Otherwise, derive it from the GOP handle's device path.\n *\n * This is needed for OpROM loading, VGA arbitration, and legacy handoff.\n */\nstatic EFI_STATUS FindVgaPciInfo(struct csmwrap_priv *priv)\n{\n EFI_STATUS Status;\n EFI_PCI_IO_PROTOCOL *PciIo;\n\n /* If user specified a VGA device, find it directly by PCI address */\n if (gConfig.vga_specified) {\n Status = FindPciDevice(gConfig.vga_bus, gConfig.vga_device,\n gConfig.vga_function, &PciIo);\n if (EFI_ERROR(Status)) {\n printf(\"VGA: configured device %02x:%02x.%x not found\\n\",\n gConfig.vga_bus, gConfig.vga_device, gConfig.vga_function);\n return Status;\n }\n\n PopulateVgaPciInfo(priv, PciIo);\n return EFI_SUCCESS;\n }\n\n /* Default: derive from GOP handle's device path */\n EFI_GUID DevicePathGuid = EFI_DEVICE_PATH_PROTOCOL_GUID;\n EFI_GUID PciIoGuid = EFI_PCI_IO_PROTOCOL_GUID;\n EFI_DEVICE_PATH_PROTOCOL *DevicePath;\n EFI_HANDLE Handle;\n\n if (priv->gop_handle == NULL)\n return EFI_NOT_FOUND;\n\n Status = gBS->HandleProtocol(priv->gop_handle, &DevicePathGuid,\n (VOID **)&DevicePath);\n if (EFI_ERROR(Status))\n return Status;\n\n Status = gBS->LocateDevicePath(&PciIoGuid, &DevicePath, &Handle);\n if (EFI_ERROR(Status))\n return Status;\n\n Status = gBS->HandleProtocol(Handle, &PciIoGuid, (VOID **)&PciIo);\n if (EFI_ERROR(Status))\n return Status;\n\n PopulateVgaPciInfo(priv, PciIo);\n return EFI_SUCCESS;\n}\n\nstatic EFI_STATUS csmwrap_pci_vgaarb(EFI_PCI_IO_PROTOCOL *PciIo)\n{\n EFI_STATUS Status;\n UINT64 Attributes = 0;\n UINT64 Supported = 0;\n BOOLEAN unsupported = FALSE;\n\n if (!PciIo) {\n return EFI_INVALID_PARAMETER;\n }\n\n Status = PciIo->Attributes(PciIo, EfiPciIoAttributeOperationSupported,\n 0, &Supported);\n\n if (EFI_ERROR(Status)) {\n printf(\"%s: Failed to get supported attributes: %d\\n\", __func__, Status);\n return Status;\n }\n\n /* Prefer aliased VGA I/O for legacy OS compatibility (ISA-style decoding);\n * fall back to strict 16-bit if that's all the bridge supports. */\n if (Supported & EFI_PCI_IO_ATTRIBUTE_VGA_IO) {\n Attributes = EFI_PCI_IO_ATTRIBUTE_VGA_IO;\n } else if (Supported & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) {\n Attributes = EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;\n } else {\n printf(\"%s: No VGA IO attributes support\\n\", __func__);\n unsupported = TRUE;\n }\n\n if (Supported & EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY) {\n Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;\n } else {\n printf(\"%s: No VGA memory attributes support\\n\", __func__);\n unsupported = TRUE;\n }\n\n if (unsupported) {\n printf(\"%s: Unable to select attribute\\n\", __func__);\n return EFI_UNSUPPORTED;\n }\n\n Status = PciIo->Attributes(PciIo, EfiPciIoAttributeOperationEnable,\n Attributes, NULL);\n if (EFI_ERROR(Status)) {\n printf(\"%s: Failed to set attributes: %d\\n\", __func__, Status);\n return Status;\n }\n\n printf(\"%s: Success! Attributes: %llx\\n\", __func__, Attributes);\n\n return EFI_SUCCESS;\n}\n\n/*\n * Try to use a specific PCI device's OpROM for VGA.\n * Checks VGA arbitration, OpROM extraction, and size constraints.\n * On success, populates priv VGA fields and sets vbios_loc/vbios_size.\n */\nstatic EFI_STATUS try_gpu_oprom(struct csmwrap_priv *priv, EFI_PCI_IO_PROTOCOL *PciIo)\n{\n EFI_STATUS Status;\n PCI_TYPE00 PciConfigHeader;\n UINTN LocalRomSize;\n VOID *LocalRomImage;\n\n if (!PciIo->RomImage || !PciIo->RomSize)\n return EFI_UNSUPPORTED;\n\n /* Populate priv with this device's info for VGA arbitration and dispatch */\n PopulateVgaPciInfo(priv, PciIo);\n\n /* Try to claim VGA I/O and memory routing for this device */\n Status = csmwrap_pci_vgaarb(PciIo);\n if (Status != EFI_SUCCESS) {\n printf(\" VGA arbitration failed, skipping\\n\");\n return EFI_UNSUPPORTED;\n }\n\n LocalRomSize = (UINTN) PciIo->RomSize;\n LocalRomImage = PciIo->RomImage;\n\n PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0,\n sizeof(PciConfigHeader) / sizeof(UINT32),\n &PciConfigHeader);\n\n if (is_amd_rdna_or_newer(PciConfigHeader.Hdr.VendorId,\n PciConfigHeader.Hdr.DeviceId)) {\n printf(\" AMD RDNA+ GPU detected (device %04x), skipping OpROM\\n\",\n PciConfigHeader.Hdr.DeviceId);\n return EFI_UNSUPPORTED;\n }\n\n Status = GetPciLegacyRom(\n 0x0300,\n PciConfigHeader.Hdr.VendorId,\n PciConfigHeader.Hdr.DeviceId,\n &LocalRomImage,\n &LocalRomSize,\n NULL, NULL, NULL);\n\n if (EFI_ERROR(Status)) {\n printf(\" No legacy ROM image found\\n\");\n return Status;\n }\n\n /* Reject OpROM if it won't fit below the CSM binary */\n uintptr_t max_vbios_size = priv->csm_bin_base - VGABIOS_START;\n if (LocalRomSize > max_vbios_size) {\n printf(\" OpROM too large (%u bytes, max %u), skipping\\n\",\n (unsigned)LocalRomSize, (unsigned)max_vbios_size);\n return EFI_UNSUPPORTED;\n }\n\n vbios_loc = LocalRomImage;\n vbios_size = LocalRomSize;\n priv->video_type = CSMWRAP_VIDEO_OPROM;\n\n printf(\"Video Initialisation Succeed with OpROM\\n\");\n return EFI_SUCCESS;\n}\n\nstatic EFI_STATUS csmwrap_video_oprom_init(struct csmwrap_priv *priv)\n{\n EFI_STATUS Status;\n\n /*\n * If the user specified a GPU with vga=, only try that device.\n */\n if (gConfig.vga_specified) {\n EFI_PCI_IO_PROTOCOL *PciIo;\n Status = FindPciDevice(gConfig.vga_bus, gConfig.vga_device,\n gConfig.vga_function, &PciIo);\n if (EFI_ERROR(Status)) {\n printf(\"VGA: configured device %02x:%02x.%x not found\\n\",\n gConfig.vga_bus, gConfig.vga_device, gConfig.vga_function);\n return EFI_UNSUPPORTED;\n }\n Status = try_gpu_oprom(priv, PciIo);\n if (Status == EFI_SUCCESS)\n return EFI_SUCCESS;\n goto clear_and_fail;\n }\n\n /*\n * Auto-select: try the GOP device first (most likely to be the active\n * display), then fall through to other GPUs if it fails.\n */\n FindVgaPciInfo(priv);\n if (priv->vga_pci_io) {\n Status = try_gpu_oprom(priv, priv->vga_pci_io);\n if (Status == EFI_SUCCESS)\n return EFI_SUCCESS;\n }\n\n /*\n * GOP device didn't work — enumerate all display-class PCI devices\n * and try each one until we find a working OpROM with VGA arbitration.\n */\n EFI_HANDLE *HandleBuffer;\n UINTN HandleCount;\n EFI_GUID PciIoGuid = EFI_PCI_IO_PROTOCOL_GUID;\n\n Status = gBS->LocateHandleBuffer(ByProtocol, &PciIoGuid, NULL,\n &HandleCount, &HandleBuffer);\n if (EFI_ERROR(Status))\n goto clear_and_fail;\n\n for (UINTN i = 0; i < HandleCount; i++) {\n EFI_PCI_IO_PROTOCOL *PciIo;\n PCI_TYPE00 PciConfig;\n\n if (gBS->HandleProtocol(HandleBuffer[i], &PciIoGuid, (VOID **)&PciIo))\n continue;\n\n PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, 0,\n sizeof(PciConfig) / sizeof(UINT32), &PciConfig);\n\n if (PciConfig.Hdr.ClassCode[2] != PCI_CLASS_DISPLAY)\n continue;\n\n /* Skip the GOP device we already tried */\n if (PciIo == priv->vga_pci_io)\n continue;\n\n printf(\"VGA: trying alternate GPU %04x:%04x\\n\",\n PciConfig.Hdr.VendorId, PciConfig.Hdr.DeviceId);\n\n Status = try_gpu_oprom(priv, PciIo);\n if (Status == EFI_SUCCESS) {\n gBS->FreePool(HandleBuffer);\n return EFI_SUCCESS;\n }\n }\n\n gBS->FreePool(HandleBuffer);\n\nclear_and_fail:\n /* Reset VGA priv fields populated by failed try_gpu_oprom calls so the\n * SeaVGABIOS fallback and later oprom_dispatch_all see no stale state. */\n priv->vga_pci_io = NULL;\n priv->vga_pci_bus = 0;\n priv->vga_pci_devfn = 0;\n priv->vga_vendor_id = 0;\n priv->vga_device_id = 0;\n return EFI_UNSUPPORTED;\n}\n\nstatic EFI_STATUS csmwrap_video_seavgabios_init(struct csmwrap_priv *priv)\n{\n struct cb_framebuffer *cb_fb = &priv->cb_fb;\n unsigned long fb_addr = 0;\n EFI_STATUS status;\n EFI_GRAPHICS_OUTPUT_PROTOCOL *gop = priv->gop;\n EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *info = NULL;\n UINTN isiz = sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), currentMode;\n\n if (!gop) {\n return EFI_UNSUPPORTED;\n }\n\n /* Mode already set by FindGopPciDevice, just query info */\n currentMode = gop->Mode->Mode;\n status = gop->QueryMode(gop, currentMode, &isiz, &info);\n if (EFI_ERROR(status)) {\n printf(\"unable to get current video mode\\n\");\n return -1;\n }\n\n printf(\"%c %3d. %4d x%4d (pitch %4d fmt %d r:%06x g:%06x b:%06x)\\n\",\n '*', currentMode,\n info->HorizontalResolution, info->VerticalResolution, info->PixelsPerScanLine, info->PixelFormat,\n info->PixelFormat==PixelRedGreenBlueReserved8BitPerColor?0xff:(\n info->PixelFormat==PixelBlueGreenRedReserved8BitPerColor?0xff0000:(\n info->PixelFormat==PixelBitMask?info->PixelInformation.RedMask:0)),\n info->PixelFormat==PixelRedGreenBlueReserved8BitPerColor ||\n info->PixelFormat==PixelBlueGreenRedReserved8BitPerColor?0xff00:(\n info->PixelFormat==PixelBitMask?info->PixelInformation.GreenMask:0),\n info->PixelFormat==PixelRedGreenBlueReserved8BitPerColor?0xff0000:(\n info->PixelFormat==PixelBlueGreenRedReserved8BitPerColor?0xff:(\n info->PixelFormat==PixelBitMask?info->PixelInformation.BlueMask:0)));\n\n fb_addr = (unsigned long)gop->Mode->FrameBufferBase;\n\n printf(\"EFI Framebuffer: %lx\\n\", fb_addr);\n\n if (!fb_addr) {\n printf(\"Framebuffer invalid.\\n\");\n return EFI_UNSUPPORTED;\n }\n\n cb_fb->physical_address = fb_addr;\n cb_fb->x_resolution = info->HorizontalResolution;\n cb_fb->y_resolution = info->VerticalResolution;\n\n switch (info->PixelFormat) {\n case PixelRedGreenBlueReserved8BitPerColor:\n cb_fb->bits_per_pixel = 32;\n cb_fb->red_mask_pos = 0;\n cb_fb->red_mask_size = 8;\n cb_fb->green_mask_pos = 8;\n cb_fb->green_mask_size = 8;\n cb_fb->blue_mask_pos = 16;\n cb_fb->blue_mask_size = 8;\n cb_fb->reserved_mask_pos = 24;\n cb_fb->reserved_mask_size = 8;\n break;\n case PixelBlueGreenRedReserved8BitPerColor:\n cb_fb->bits_per_pixel = 32;\n cb_fb->blue_mask_pos = 0;\n cb_fb->blue_mask_size = 8;\n cb_fb->green_mask_pos = 8;\n cb_fb->green_mask_size = 8;\n cb_fb->red_mask_pos = 16;\n cb_fb->red_mask_size = 8;\n cb_fb->reserved_mask_pos = 24;\n cb_fb->reserved_mask_size = 8;\n break;\n case PixelBitMask:\n /* Reject modes with all-zero pixel masks */\n if ((info->PixelInformation.RedMask\n | info->PixelInformation.GreenMask\n | info->PixelInformation.BlueMask\n | info->PixelInformation.ReservedMask) == 0) {\n printf(\"PixelBitMask mode with all-zero masks\\n\");\n return EFI_UNSUPPORTED;\n }\n\n /* Calculate BPP from masks instead of assuming 32 */\n cb_fb->bits_per_pixel = linear_masks_to_bpp(\n info->PixelInformation.RedMask,\n info->PixelInformation.GreenMask,\n info->PixelInformation.BlueMask,\n info->PixelInformation.ReservedMask);\n\n // Calculate position (find first set bit, 0 if mask is empty)\n cb_fb->red_mask_pos = info->PixelInformation.RedMask ? __builtin_ffs(info->PixelInformation.RedMask) - 1 : 0;\n cb_fb->green_mask_pos = info->PixelInformation.GreenMask ? __builtin_ffs(info->PixelInformation.GreenMask) - 1 : 0;\n cb_fb->blue_mask_pos = info->PixelInformation.BlueMask ? __builtin_ffs(info->PixelInformation.BlueMask) - 1 : 0;\n cb_fb->reserved_mask_pos = info->PixelInformation.ReservedMask ? __builtin_ffs(info->PixelInformation.ReservedMask) - 1 : 0;\n\n // Calculate size (count set bits)\n cb_fb->red_mask_size = __builtin_popcount(info->PixelInformation.RedMask);\n cb_fb->green_mask_size = __builtin_popcount(info->PixelInformation.GreenMask);\n cb_fb->blue_mask_size = __builtin_popcount(info->PixelInformation.BlueMask);\n cb_fb->reserved_mask_size = __builtin_popcount(info->PixelInformation.ReservedMask);\n break;\n default:\n printf(\"Unsupported pixel format: %d\\n\", info->PixelFormat);\n return EFI_UNSUPPORTED;\n }\n\n /*\n * Recalculate pitch from gop->Mode->Info, as some firmware (e.g. Apple\n * Macs) report incorrect PixelsPerScanLine via QueryMode.\n */\n cb_fb->bytes_per_line = gop->Mode->Info->PixelsPerScanLine * (cb_fb->bits_per_pixel / 8);\n\n /* Validate pitch */\n {\n uint32_t bytes_per_pixel = cb_fb->bits_per_pixel / 8;\n if (bytes_per_pixel == 0\n || cb_fb->bytes_per_line % bytes_per_pixel != 0\n || cb_fb->bytes_per_line < cb_fb->x_resolution * bytes_per_pixel) {\n printf(\"Invalid pitch %u (width=%u, bpp=%u)\\n\",\n cb_fb->bytes_per_line, cb_fb->x_resolution, cb_fb->bits_per_pixel);\n return EFI_UNSUPPORTED;\n }\n }\n\n vbios_loc = vgabios_bin;\n vbios_size = sizeof(vgabios_bin);\n\n priv->video_type = CSMWRAP_VIDEO_SEAVGABIOS;\n\n printf(\"Video Initialisation Succeed with SeaVGABIOS GOP\\n\");\n\n return 0;\n\n}\n\nEFI_STATUS csmwrap_video_prepare_exitbs(struct csmwrap_priv *priv)\n{\n /*\n * Unlink Controller before ExitBS, it mat disable FB so we can't\n * do that for other video types.\n */\n if (priv->video_type == CSMWRAP_VIDEO_OPROM) {\n EFI_STATUS Status;\n\n if (!priv->gop_handle) {\n printf(\"No GOP handle found\\n\");\n return EFI_UNSUPPORTED;\n }\n\n if (gBS->Hdr.Revision < EFI_1_10_BOOT_SERVICES_REVISION && !gBS->DisconnectController) {\n printf(\"DisconnectController not supported\\n\");\n return EFI_UNSUPPORTED;\n }\n\n Status = gBS->DisconnectController(\n priv->gop_handle,\n NULL,\n NULL\n );\n\n if (EFI_ERROR(Status)) {\n printf(\"DisconnectController failed: %d\\n\", Status);\n return Status;\n }\n }\n\n return EFI_SUCCESS;\n}\n\n/*\n * Check if the GPU is AMD RDNA or newer architecture.\n *\n * AMD RDNA+ iGPUs have broken/non-functional legacy VGA BIOS (OpROM),\n * so we need to force SeaVGABIOS even if the GPU advertises an OpROM.\n *\n * Strategy: Instead of listing all RDNA+ device IDs (which requires constant\n * updates), we whitelist known-good pre-RDNA (Vega-based) APUs and assume\n * any other AMD iGPU in the typical APU device ID ranges is RDNA+.\n *\n * Device IDs sourced from Linux amdgpu driver and Folding@home GPU database.\n */\n#define AMD_VENDOR_ID 0x1002\n\nstatic bool is_amd_vega_apu(uint16_t device_id)\n{\n /*\n * Known Vega-based APUs with working legacy OpROM:\n * - Raven Ridge (Ryzen 2000 APU)\n * - Picasso (Ryzen 3000 APU)\n * - Renoir (Ryzen 4000 APU)\n * - Lucienne (Ryzen 5000 APU, Zen 2 refresh)\n * - Cezanne (Ryzen 5000 APU, Zen 3)\n * - Barcelo (Ryzen 5000 APU refresh)\n */\n switch (device_id) {\n case 0x15D8: /* Picasso */\n case 0x15DD: /* Raven Ridge */\n case 0x15E7: /* Barcelo */\n case 0x1636: /* Renoir */\n case 0x1638: /* Renoir/Cezanne */\n case 0x164C: /* Lucienne */\n return true;\n default:\n return false;\n }\n}\n\nstatic bool is_amd_rdna_or_newer(uint16_t vendor_id, uint16_t device_id)\n{\n if (vendor_id != AMD_VENDOR_ID)\n return false;\n\n /*\n * AMD RDNA 1/2/3/4 discrete GPUs (Navi series):\n * - 0x73xx: Navi 10/12/14 (RDNA 1), Navi 21/22/23 (RDNA 2)\n * - 0x74xx: Navi 24 (RDNA 2), Navi 31/32/33 (RDNA 3)\n * - 0x75xx: Navi 48/44 (RDNA 4)\n */\n if ((device_id & 0xFF00) == 0x7300 ||\n (device_id & 0xFF00) == 0x7400 ||\n (device_id & 0xFF00) == 0x7500)\n return true;\n\n /*\n * AMD APU/iGPU detection:\n * Device IDs in ranges 0x14xx, 0x15xx, 0x16xx, 0x19xx are typically iGPUs.\n * If it's not a known Vega APU, assume it's RDNA+ with broken OpROM.\n */\n if ((device_id & 0xFF00) == 0x1400 ||\n (device_id & 0xFF00) == 0x1500 ||\n (device_id & 0xFF00) == 0x1600 ||\n (device_id & 0xFF00) == 0x1900) {\n /* Check if it's a known-good Vega APU */\n if (is_amd_vega_apu(device_id))\n return false;\n /* Unknown APU in these ranges - assume RDNA+ */\n return true;\n }\n\n return false;\n}\n\nvoid csmwrap_video_early_init(struct csmwrap_priv *priv) {\n if (FindGop(priv) != EFI_SUCCESS) {\n priv->cb_fb.physical_address = 0;\n return;\n }\n\n if (csmwrap_video_seavgabios_init(priv) != EFI_SUCCESS) {\n priv->cb_fb.physical_address = 0;\n return;\n }\n\n /* Clear vbios_loc so csmwrap_video_init() doesn't skip OpROM init */\n vbios_loc = NULL;\n}\n\n/*\n * If a specific VGA device is configured, find its GOP handle and switch\n * priv->gop_handle so that DisconnectController targets the correct device\n * during exit-boot-services preparation.\n */\nstatic void FindVgaGop(struct csmwrap_priv *priv)\n{\n EFI_HANDLE *HandleBuffer;\n UINTN HandleCount;\n EFI_GUID gopGuid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID;\n EFI_GUID DevicePathGuid = EFI_DEVICE_PATH_PROTOCOL_GUID;\n EFI_GUID PciIoGuid = EFI_PCI_IO_PROTOCOL_GUID;\n\n if (gBS->LocateHandleBuffer(ByProtocol, &gopGuid, NULL,\n &HandleCount, &HandleBuffer))\n return;\n\n for (UINTN i = 0; i < HandleCount; i++) {\n EFI_DEVICE_PATH_PROTOCOL *DevicePath;\n if (gBS->HandleProtocol(HandleBuffer[i], &DevicePathGuid,\n (VOID **)&DevicePath))\n continue;\n\n EFI_HANDLE PciHandle;\n if (gBS->LocateDevicePath(&PciIoGuid, &DevicePath, &PciHandle))\n continue;\n\n EFI_PCI_IO_PROTOCOL *PciIo;\n if (gBS->HandleProtocol(PciHandle, &PciIoGuid, (VOID **)&PciIo))\n continue;\n\n UINTN Seg, Bus, Device, Function;\n PciIo->GetLocation(PciIo, &Seg, &Bus, &Device, &Function);\n\n if ((uint8_t)Bus != gConfig.vga_bus ||\n (uint8_t)Device != gConfig.vga_device ||\n (uint8_t)Function != gConfig.vga_function)\n continue;\n\n EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop;\n if (gBS->HandleProtocol(HandleBuffer[i], &gopGuid, (VOID **)&Gop))\n continue;\n\n priv->gop = Gop;\n priv->gop_handle = HandleBuffer[i];\n printf(\"VGA: switched GOP to configured device %02x:%02x.%x\\n\",\n gConfig.vga_bus, gConfig.vga_device, gConfig.vga_function);\n break;\n }\n\n gBS->FreePool(HandleBuffer);\n}\n\nEFI_STATUS csmwrap_video_init(struct csmwrap_priv *priv)\n{\n EFI_STATUS status;\n\n /* Find GOP if not already found by early init */\n if (!priv->gop) {\n status = FindGop(priv);\n if (EFI_ERROR(status)) {\n printf(\"Unable to get GOP service; continuing without video\\n\");\n return EFI_UNSUPPORTED;\n }\n }\n\n if (vbios_loc != NULL) {\n /*\n * User-provided VBIOS: still need PCI info and VGA arbitration\n * so the VBIOS is dispatched to the right device.\n */\n FindVgaPciInfo(priv);\n status = csmwrap_pci_vgaarb(priv->vga_pci_io);\n if (status != EFI_SUCCESS) {\n printf(\"VGA arbitration failed, cannot dispatch user VBIOS\\n\");\n vbios_loc = NULL;\n vbios_size = 0;\n /* Fall through to try SeaVGABIOS instead */\n goto try_seavga;\n }\n if (gConfig.vga_specified)\n FindVgaGop(priv);\n priv->video_type = CSMWRAP_VIDEO_OPROM;\n return 0;\n }\n\n /* Try OpROM: user-specified GPU, or auto-select from all GPUs */\n status = csmwrap_video_oprom_init(priv);\n if (status == EFI_SUCCESS) {\n /*\n * Switch gop_handle to the VGA device so DisconnectController\n * targets the right device during exit-boot-services preparation.\n */\n if (gConfig.vga_specified)\n FindVgaGop(priv);\n return 0;\n }\n\ntry_seavga:\n status = csmwrap_video_seavgabios_init(priv);\n if (status == EFI_SUCCESS) {\n return 0;\n }\n\n panic(\"No video initialization method available\\n\");\n}\n\n" }, { "path": "src/video.h", "content": "#ifndef VIDEO_H\n#define VIDEO_H\n\n#include \n#include \n#include \n\nextern void *vbios_loc;\nextern uintptr_t vbios_size;\n\nEFI_STATUS csmwrap_video_init(struct csmwrap_priv *priv);\nEFI_STATUS csmwrap_video_prepare_exitbs(struct csmwrap_priv *priv);\n\nvoid csmwrap_video_early_init(struct csmwrap_priv *priv);\n\n#endif\n" }, { "path": "src/x86thunk.c", "content": "/*\n * Real Mode Thunk Functions for IA32 and x64.\n *\n * Based on EDK2: MdePkg/Library/BaseLib/X86Thunk.c\n *\n * Which is:\n * Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n * SPDX-License-Identifier: BSD-2-Clause-Patent\n */\n\n#include \n#include \n#include \"csmwrap.h\"\n\n// FIXME: Are we going to implement it?\n#define ASSERT(x)\n\nextern const uint8_t m16Start;\nextern const uint16_t m16Size;\nextern const uint16_t mThunk16Attr;\nextern const uint16_t m16Gdt;\nextern const uint16_t m16GdtrBase;\nextern const uint16_t mTransition;\n\n/**\n Invokes 16-bit code in big real mode and returns the updated register set.\n\n This function transfers control to the 16-bit code specified by CS:EIP using\n the stack specified by SS:ESP in RegisterSet. The updated registers are saved\n on the real mode stack and the starting address of the save area is returned.\n\n @param RegisterSet Values of registers before invocation of 16-bit code.\n @param Transition The pointer to the transition code under 1MB.\n\n @return The pointer to a IA32_REGISTER_SET structure containing the updated\n register values.\n\n**/\n__attribute__((__ms_abi__))\nIA32_REGISTER_SET *InternalAsmThunk16(IA32_REGISTER_SET *RegisterSet, void *Transition);\n\n/**\n Retrieves the properties for 16-bit thunk functions.\n\n Computes the size of the buffer and stack below 1MB required to use the\n AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\n buffer size is returned in RealModeBufferSize, and the stack size is returned\n in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\n then the actual minimum stack size is ExtraStackSize plus the maximum number\n of bytes that need to be passed to the 16-bit real mode code.\n\n If RealModeBufferSize is NULL, then ASSERT().\n If ExtraStackSize is NULL, then ASSERT().\n\n @param RealModeBufferSize A pointer to the size of the buffer below 1MB\n required to use the 16-bit thunk functions.\n @param ExtraStackSize A pointer to the extra size of stack below 1MB\n that the 16-bit thunk functions require for\n temporary storage in the transition to and from\n 16-bit real mode.\n\n**/\nvoid AsmGetThunk16Properties (uint32_t *RealModeBufferSize, uint32_t *ExtraStackSize)\n{\n ASSERT (RealModeBufferSize != NULL);\n ASSERT (ExtraStackSize != NULL);\n\n *RealModeBufferSize = m16Size;\n\n //\n // Extra 4 bytes for return address, and another 4 bytes for mode transition\n //\n *ExtraStackSize = sizeof (IA32_DWORD_REGS) + 8;\n}\n\n/**\n Prepares all structures a code required to use AsmThunk16().\n\n Prepares all structures and code required to use AsmThunk16().\n\n This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\n virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\n\n If ThunkContext is NULL, then ASSERT().\n\n @param ThunkContext A pointer to the context structure that describes the\n 16-bit real mode code to call.\n\n**/\nvoid AsmPrepareThunk16 (THUNK_CONTEXT *ThunkContext)\n{\n IA32_SEGMENT_DESCRIPTOR *RealModeGdt;\n\n ASSERT (ThunkContext != NULL);\n ASSERT ((uintptr_t)ThunkContext->RealModeBuffer < 0x100000);\n ASSERT (ThunkContext->RealModeBufferSize >= m16Size);\n ASSERT ((uintptr_t)ThunkContext->RealModeBuffer + m16Size <= 0x100000);\n\n memcpy (ThunkContext->RealModeBuffer, &m16Start, m16Size);\n\n //\n // Point RealModeGdt to the GDT to be used in transition\n //\n // RealModeGdt[0]: Reserved as NULL descriptor\n // RealModeGdt[1]: Code Segment\n // RealModeGdt[2]: Data Segment\n // RealModeGdt[3]: Call Gate\n //\n RealModeGdt = (IA32_SEGMENT_DESCRIPTOR *)(\n (uintptr_t)ThunkContext->RealModeBuffer + m16Gdt);\n\n //\n // Update Code & Data Segment Descriptor\n //\n RealModeGdt[1].Bits.BaseLow =\n (uint32_t)(uintptr_t)ThunkContext->RealModeBuffer & ~0xf;\n RealModeGdt[1].Bits.BaseMid =\n (uint32_t)(uintptr_t)ThunkContext->RealModeBuffer >> 16;\n\n //\n // Update transition code entry point offset\n //\n *(uint32_t *)((uintptr_t)ThunkContext->RealModeBuffer + mTransition) +=\n (uint32_t)(uintptr_t)ThunkContext->RealModeBuffer & 0xf;\n\n //\n // Update Segment Limits for both Code and Data Segment Descriptors\n //\n if ((ThunkContext->ThunkAttributes & THUNK_ATTRIBUTE_BIG_REAL_MODE) == 0) {\n //\n // Set segment limits to 64KB\n //\n RealModeGdt[1].Bits.LimitHigh = 0;\n RealModeGdt[1].Bits.G = 0;\n RealModeGdt[2].Bits.LimitHigh = 0;\n RealModeGdt[2].Bits.G = 0;\n }\n\n //\n // Update GDTBASE for this thunk context\n //\n *(void **)((uintptr_t)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;\n\n //\n // Update Thunk Attributes\n //\n *(uint32_t *)((uintptr_t)ThunkContext->RealModeBuffer + mThunk16Attr) =\n ThunkContext->ThunkAttributes;\n}\n\n/**\n Transfers control to a 16-bit real mode entry point and returns the results.\n\n Transfers control to a 16-bit real mode entry point and returns the results.\n AsmPrepareThunk16() must be called with ThunkContext before this function is used.\n This function must be called with interrupts disabled.\n\n The register state from the RealModeState field of ThunkContext is restored just prior\n to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\n which is used to set the interrupt state when a 16-bit real mode entry point is called.\n Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\n The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\n the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\n The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\n so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\n and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\n point must exit with a RETF instruction. The register state is captured into RealModeState immediately\n after the RETF instruction is executed.\n\n If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\n or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\n the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\n\n If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\n then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\n This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\n\n If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\n is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\n\n If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\n ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\n disable the A20 mask.\n\n If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\n ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\n then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\n\n If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\n ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\n\n If ThunkContext is NULL, then ASSERT().\n If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\n If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\n ThunkAttributes, then ASSERT().\n\n This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\n virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\n\n @param ThunkContext A pointer to the context structure that describes the\n 16-bit real mode code to call.\n\n**/\nvoid AsmThunk16 (THUNK_CONTEXT *ThunkContext)\n{\n IA32_REGISTER_SET *UpdatedRegs;\n\n ASSERT (ThunkContext != NULL);\n ASSERT ((uintptr_t)ThunkContext->RealModeBuffer < 0x100000);\n ASSERT (ThunkContext->RealModeBufferSize >= m16Size);\n ASSERT ((uintptr_t)ThunkContext->RealModeBuffer + m16Size <= 0x100000);\n ASSERT (\n ((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \\\n (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL))\n );\n\n UpdatedRegs = InternalAsmThunk16 (\n ThunkContext->RealModeState,\n ThunkContext->RealModeBuffer\n );\n\n memcpy(ThunkContext->RealModeState, UpdatedRegs, sizeof (*UpdatedRegs));\n}\n\n/**\n Prepares all structures and code for a 16-bit real mode thunk, transfers\n control to a 16-bit real mode entry point, and returns the results.\n\n Prepares all structures and code for a 16-bit real mode thunk, transfers\n control to a 16-bit real mode entry point, and returns the results. If the\n caller only need to perform a single 16-bit real mode thunk, then this\n service should be used. If the caller intends to make more than one 16-bit\n real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\n once and AsmThunk16() can be called for each 16-bit real mode thunk.\n\n This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\n virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\n\n See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\n\n @param ThunkContext A pointer to the context structure that describes the\n 16-bit real mode code to call.\n\n**/\nvoid AsmPrepareAndThunk16 (THUNK_CONTEXT *ThunkContext)\n{\n AsmPrepareThunk16(ThunkContext);\n AsmThunk16(ThunkContext);\n}\n\nTHUNK_CONTEXT mThunkContext;\n\nbool InternalLegacyBiosFarCall (uint16_t Segment, uint16_t Offset, EFI_IA32_REGISTER_SET *Regs, void *Stack, uintptr_t StackSize)\n{\n// uintptr_t Status;\n uint16_t *Stack16;\n// EFI_TPL OriginalTpl;\n IA32_REGISTER_SET ThunkRegSet;\n// bool InterruptState;\n// uint64_t TimerPeriod;\n\n memset(&ThunkRegSet, 0, sizeof (ThunkRegSet));\n ThunkRegSet.X.DI = Regs->X.DI;\n ThunkRegSet.X.SI = Regs->X.SI;\n ThunkRegSet.X.BP = Regs->X.BP;\n ThunkRegSet.X.BX = Regs->X.BX;\n ThunkRegSet.X.DX = Regs->X.DX;\n //\n // Sometimes, ECX is used to pass in 32 bit data. For example, INT 1Ah, AX = B10Dh is\n // \"PCI BIOS v2.0c + Write Configuration DWORD\" and ECX has the dword to write.\n //\n ThunkRegSet.E.ECX = Regs->E.ECX;\n ThunkRegSet.X.AX = Regs->X.AX;\n ThunkRegSet.E.DS = Regs->X.DS;\n ThunkRegSet.E.ES = Regs->X.ES;\n\n memcpy (&(ThunkRegSet.E.EFLAGS.UintN), &(Regs->X.Flags), sizeof (Regs->X.Flags));\n\n //\n // Clear the error flag; thunk code may set it. Stack16 should be the high address\n // Make Statk16 address the low 16 bit must be not zero.\n //\n Stack16 = (uint16_t *)((uint8_t *)mThunkContext.RealModeBuffer + mThunkContext.RealModeBufferSize - sizeof (uint16_t));\n\n //\n // Save current rate of DXE Timer\n //\n // Private->Timer->GetTimerPeriod (Private->Timer, &TimerPeriod);\n\n //\n // Disable DXE Timer while executing in real mode\n //\n // Private->Timer->SetTimerPeriod (Private->Timer, 0);\n\n //\n // Save and disable interrupt of debug timer\n //\n // InterruptState = SaveAndSetDebugTimerInterrupt (FALSE);\n\n //\n // The call to Legacy16 is a critical section to EFI\n //\n // OriginalTpl = ggBS->RaiseTPL (TPL_HIGH_LEVEL);\n\n //\n // Check to see if there is more than one HW interrupt registers with the CPU AP.\n // If there is, then ASSERT() since that is not compatible with the CSM because\n // interupts other than the Timer interrupt that was disabled above can not be\n // handled properly from real mode.\n //\n #if 0\n DEBUG_CODE_BEGIN ();\n uintptr_t Vector;\n uintptr_t Count;\n\n for (Vector = 0x20, Count = 0; Vector < 0x100; Vector++) {\n Status = Private->Cpu->RegisterInterruptHandler (Private->Cpu, Vector, LegacyBiosNullInterruptHandler);\n if (Status == EFI_ALREADY_STARTED) {\n Count++;\n }\n\n if (Status == EFI_SUCCESS) {\n Private->Cpu->RegisterInterruptHandler (Private->Cpu, Vector, NULL);\n }\n }\n\n if (Count >= 2) {\n printf(\"ERROR: More than one HW interrupt active with CSM enabled\\n\");\n }\n\n ASSERT (Count < 2);\n DEBUG_CODE_END ();\n#endif\n\n //\n // If the Timer AP has enabled the 8254 timer IRQ and the current 8254 timer\n // period is less than the CSM required rate of 54.9254, then force the 8254\n // PIT counter to 0, which is the CSM required rate of 54.9254 ms\n //\n // if (Private->TimerUses8254 && (TimerPeriod < 549254)) {\n // SetPitCount (0);\n // }\n\n if ((Stack != NULL) && (StackSize != 0)) {\n //\n // Copy Stack to low memory stack\n //\n Stack16 -= StackSize / sizeof (uint16_t);\n memcpy (Stack16, Stack, StackSize);\n }\n\n ThunkRegSet.E.SS = (uint16_t)(((uintptr_t)Stack16 >> 16) << 12);\n ThunkRegSet.E.ESP = (uint16_t)(uintptr_t)Stack16;\n ThunkRegSet.E.CS = Segment;\n ThunkRegSet.E.Eip = Offset;\n\n mThunkContext.RealModeState = &ThunkRegSet;\n\n //\n // Set Legacy16 state. 0x08, 0x70 is legacy 8259 vector bases.\n //\n /* FIXME: DO we need to care 8259? */\n // Status = Private->Legacy8259->SetMode (Private->Legacy8259, Efi8259LegacyMode, NULL, NULL);\n // ASSERT_EFI_ERROR (Status);\n\n AsmThunk16 (&mThunkContext);\n\n if ((Stack != NULL) && (StackSize != 0)) {\n //\n // Copy low memory stack to Stack\n //\n memcpy (Stack, Stack16, StackSize);\n }\n\n //\n // Restore protected mode interrupt state\n //\n /* FIXME: DO we need to care 8259? */\n // Status = Private->Legacy8259->SetMode (Private->Legacy8259, Efi8259ProtectedMode, NULL, NULL);\n // ASSERT_EFI_ERROR (Status);\n\n mThunkContext.RealModeState = NULL;\n\n //\n // Enable and restore rate of DXE Timer\n //\n // Private->Timer->SetTimerPeriod (Private->Timer, TimerPeriod);\n\n //\n // End critical section\n //\n // ggBS->RestoreTPL (OriginalTpl);\n\n //\n // OPROM may allocate EBDA range by itself and change EBDA base and EBDA size.\n // Get the current EBDA base address, and compared with pre-allocate minimum\n // EBDA base address, if the current EBDA base address is smaller, it indicates\n // PcdEbdaReservedMemorySize should be adjusted to larger for more OPROMs.\n //\n#if 0\n DEBUG_CODE_BEGIN ();\n {\n uintptr_t EbdaBaseAddress;\n uintptr_t ReservedEbdaBaseAddress;\n\n ACCESS_PAGE0_CODE (\n EbdaBaseAddress = (*(uint16_t *)(uintptr_t)0x40E) << 4;\n ReservedEbdaBaseAddress = CONVENTIONAL_MEMORY_TOP\n - PcdGet32 (PcdEbdaReservedMemorySize);\n ASSERT (ReservedEbdaBaseAddress <= EbdaBaseAddress);\n );\n }\n DEBUG_CODE_END ();\n#endif\n\n //\n // Restore interrupt of debug timer\n //\n // SaveAndSetDebugTimerInterrupt (InterruptState);\n\n Regs->E.EDI = ThunkRegSet.E.EDI;\n Regs->E.ESI = ThunkRegSet.E.ESI;\n Regs->E.EBP = ThunkRegSet.E.EBP;\n Regs->E.EBX = ThunkRegSet.E.EBX;\n Regs->E.EDX = ThunkRegSet.E.EDX;\n Regs->E.ECX = ThunkRegSet.E.ECX;\n Regs->E.EAX = ThunkRegSet.E.EAX;\n Regs->X.SS = ThunkRegSet.E.SS;\n Regs->X.CS = ThunkRegSet.E.CS;\n Regs->X.DS = ThunkRegSet.E.DS;\n Regs->X.ES = ThunkRegSet.E.ES;\n\n memcpy (&(Regs->X.Flags), &(ThunkRegSet.E.EFLAGS.UintN), sizeof (Regs->X.Flags));\n\n return (bool)(Regs->X.Flags.CF == 1);\n}\n\n// Return final pointer\nuintptr_t LegacyBiosInitializeThunkAndTable(uintptr_t MemoryAddress, size_t data_size) {\n uintptr_t data_pages = (data_size + EFI_PAGE_SIZE - 1) / EFI_PAGE_SIZE;\n\n mThunkContext.RealModeBuffer = (void *)(uintptr_t)(MemoryAddress + (data_pages * EFI_PAGE_SIZE));\n mThunkContext.RealModeBufferSize = EFI_PAGE_SIZE;\n mThunkContext.ThunkAttributes = THUNK_ATTRIBUTE_BIG_REAL_MODE | THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15;\n\n memset(mThunkContext.RealModeBuffer, 0, mThunkContext.RealModeBufferSize);\n\n printf(\"RealmodeBuffer %lx\\n\", (uintptr_t)mThunkContext.RealModeBuffer);\n\n AsmPrepareThunk16 (&mThunkContext);\n\n return (uintptr_t)mThunkContext.RealModeBuffer + mThunkContext.RealModeBufferSize + EFI_PAGE_SIZE;\n}\n\nbool LegacyBiosInt86(uint8_t BiosInt, EFI_IA32_REGISTER_SET *Regs)\n{\n uint16_t Segment;\n uint16_t Offset;\n\n /* FIXME: Not working!!!!!!!!!!!! */\n\n Regs->X.Flags.Reserved1 = 1;\n Regs->X.Flags.Reserved2 = 0;\n Regs->X.Flags.Reserved3 = 0;\n Regs->X.Flags.Reserved4 = 0;\n Regs->X.Flags.IOPL = 3;\n Regs->X.Flags.NT = 0;\n Regs->X.Flags.IF = 0;\n Regs->X.Flags.TF = 0;\n Regs->X.Flags.CF = 0;\n\n\n //\n // The base address of legacy interrupt vector table is 0.\n // We use this base address to get the legacy interrupt handler.\n //\n ACCESS_PAGE0_CODE (\n Segment = (UINT16)(((UINT32 *)0)[BiosInt] >> 16);\n Offset = (UINT16)((UINT32 *)0)[BiosInt];\n );\n\n return InternalLegacyBiosFarCall (\n Segment,\n Offset,\n Regs,\n &Regs->X.Flags,\n sizeof (Regs->X.Flags)\n );\n}\n\n/**\n Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the\n 16-bit register context on entry and exit. Arguments can be passed on\n the Stack argument\n\n @param This Protocol instance pointer.\n @param Segment Segemnt of 16-bit mode call\n @param Offset Offset of 16-bit mdoe call\n @param Regs Register contexted passed into (and returned) from\n thunk to 16-bit mode\n @param Stack Caller allocated stack used to pass arguments\n @param StackSize Size of Stack in bytes\n\n @retval FALSE Thunk completed, and there were no BIOS errors in\n the target code. See Regs for status.\n @retval TRUE There was a BIOS erro in the target code.\n\n**/\nbool LegacyBiosFarCall86 (uint16_t Segment, uint16_t Offset, EFI_IA32_REGISTER_SET *Regs, void *Stack, uintptr_t StackSize)\n{\n Regs->X.Flags.Reserved1 = 1;\n Regs->X.Flags.Reserved2 = 0;\n Regs->X.Flags.Reserved3 = 0;\n Regs->X.Flags.Reserved4 = 0;\n Regs->X.Flags.IOPL = 3;\n Regs->X.Flags.NT = 0;\n Regs->X.Flags.IF = 1;\n Regs->X.Flags.TF = 0;\n Regs->X.Flags.CF = 0;\n\n return InternalLegacyBiosFarCall (Segment, Offset, Regs, Stack, StackSize);\n}\n" }, { "path": "src/x86thunk.h", "content": "/*\n * Real Mode Thunk Functions for IA32 and x64.\n *\n * Based on various EDK2 headers\n *\n * Which is:\n * Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
\n * SPDX-License-Identifier: BSD-2-Clause-Patent\n */\n\n#ifndef _X86_THUNK_H\n#define _X86_THUNK_H\n\n#include \n#include \n#include \n\n#pragma pack (1)\n///\n/// Byte packed structure for EFLAGS/RFLAGS.\n/// 32-bits on IA-32.\n/// 64-bits on x64. The upper 32-bits on x64 are reserved.\n///\ntypedef union {\n struct {\n uint32_t CF : 1; ///< Carry Flag.\n uint32_t Reserved_0 : 1; ///< Reserved.\n uint32_t PF : 1; ///< Parity Flag.\n uint32_t Reserved_1 : 1; ///< Reserved.\n uint32_t AF : 1; ///< Auxiliary Carry Flag.\n uint32_t Reserved_2 : 1; ///< Reserved.\n uint32_t ZF : 1; ///< Zero Flag.\n uint32_t SF : 1; ///< Sign Flag.\n uint32_t TF : 1; ///< Trap Flag.\n uint32_t IF : 1; ///< Interrupt Enable Flag.\n uint32_t DF : 1; ///< Direction Flag.\n uint32_t OF : 1; ///< Overflow Flag.\n uint32_t IOPL : 2; ///< I/O Privilege Level.\n uint32_t NT : 1; ///< Nested Task.\n uint32_t Reserved_3 : 1; ///< Reserved.\n uint32_t RF : 1; ///< Resume Flag.\n uint32_t VM : 1; ///< Virtual 8086 Mode.\n uint32_t AC : 1; ///< Alignment Check.\n uint32_t VIF : 1; ///< Virtual Interrupt Flag.\n uint32_t VIP : 1; ///< Virtual Interrupt Pending.\n uint32_t ID : 1; ///< ID Flag.\n uint32_t Reserved_4 : 10; ///< Reserved.\n } Bits;\n uintptr_t UintN;\n} IA32_EFLAGS32;\n\n///\n/// Byte packed structure for an x64 Interrupt Gate Descriptor.\n///\ntypedef union {\n struct {\n uint32_t OffsetLow : 16; ///< Offset bits 15..0.\n uint32_t Selector : 16; ///< Selector.\n uint32_t Reserved_0 : 8; ///< Reserved.\n uint32_t GateType : 8; ///< Gate Type. See #defines above.\n uint32_t OffsetHigh : 16; ///< Offset bits 31..16.\n uint32_t OffsetUpper : 32; ///< Offset bits 63..32.\n uint32_t Reserved_1 : 32; ///< Reserved.\n } Bits;\n struct {\n uint64_t Uint64;\n uint64_t Uint64_1;\n } Uint128;\n} IA32_IDT_GATE_DESCRIPTOR;\n\n\n//\n// IA32 Task-State Segment Definition\n//\ntypedef struct {\n uint32_t Reserved_0;\n uint64_t RSP0;\n uint64_t RSP1;\n uint64_t RSP2;\n uint64_t Reserved_28;\n uint64_t IST[7];\n uint64_t Reserved_92;\n uint16_t Reserved_100;\n uint16_t IOMapBaseAddress;\n} IA32_TASK_STATE_SEGMENT;\n\ntypedef union {\n struct {\n uint32_t LimitLow : 16; ///< Segment Limit 15..00\n uint32_t BaseLow : 16; ///< Base Address 15..00\n uint32_t BaseMidl : 8; ///< Base Address 23..16\n uint32_t Type : 4; ///< Type (1 0 B 1)\n uint32_t Reserved_43 : 1; ///< 0\n uint32_t DPL : 2; ///< Descriptor Privilege Level\n uint32_t P : 1; ///< Segment Present\n uint32_t LimitHigh : 4; ///< Segment Limit 19..16\n uint32_t AVL : 1; ///< Available for use by system software\n uint32_t Reserved_52 : 2; ///< 0 0\n uint32_t G : 1; ///< Granularity\n uint32_t BaseMidh : 8; ///< Base Address 31..24\n uint32_t BaseHigh : 32; ///< Base Address 63..32\n uint32_t Reserved_96 : 32; ///< Reserved\n } Bits;\n struct {\n uint64_t Uint64;\n uint64_t Uint64_1;\n } Uint128;\n} IA32_TSS_DESCRIPTOR;\n\n///\n/// Byte packed structure for an FP/SSE/SSE2 context.\n///\ntypedef struct {\n uint8_t Buffer[512];\n} IA32_FX_BUFFER;\n\n///\n/// Structures for the 16-bit real mode thunks.\n///\ntypedef struct {\n uint32_t Reserved1;\n uint32_t Reserved2;\n uint32_t Reserved3;\n uint32_t Reserved4;\n uint8_t BL;\n uint8_t BH;\n uint16_t Reserved5;\n uint8_t DL;\n uint8_t DH;\n uint16_t Reserved6;\n uint8_t CL;\n uint8_t CH;\n uint16_t Reserved7;\n uint8_t AL;\n uint8_t AH;\n uint16_t Reserved8;\n} IA32_BYTE_REGS;\n\ntypedef struct {\n uint16_t DI;\n uint16_t Reserved1;\n uint16_t SI;\n uint16_t Reserved2;\n uint16_t BP;\n uint16_t Reserved3;\n uint16_t SP;\n uint16_t Reserved4;\n uint16_t BX;\n uint16_t Reserved5;\n uint16_t DX;\n uint16_t Reserved6;\n uint16_t CX;\n uint16_t Reserved7;\n uint16_t AX;\n uint16_t Reserved8;\n} IA32_WORD_REGS;\n\ntypedef struct {\n uint32_t EDI;\n uint32_t ESI;\n uint32_t EBP;\n uint32_t ESP;\n uint32_t EBX;\n uint32_t EDX;\n uint32_t ECX;\n uint32_t EAX;\n uint16_t DS;\n uint16_t ES;\n uint16_t FS;\n uint16_t GS;\n IA32_EFLAGS32 EFLAGS;\n uint32_t Eip;\n uint16_t CS;\n uint16_t SS;\n} IA32_DWORD_REGS;\n\ntypedef union {\n IA32_DWORD_REGS E;\n IA32_WORD_REGS X;\n IA32_BYTE_REGS H;\n} IA32_REGISTER_SET;\n\ntypedef union {\n struct {\n uint32_t LimitLow : 16;\n uint32_t BaseLow : 16;\n uint32_t BaseMid : 8;\n uint32_t Type : 4;\n uint32_t S : 1;\n uint32_t DPL : 2;\n uint32_t P : 1;\n uint32_t LimitHigh : 4;\n uint32_t AVL : 1;\n uint32_t L : 1;\n uint32_t DB : 1;\n uint32_t G : 1;\n uint32_t BaseHigh : 8;\n } Bits;\n uint64_t Uint64;\n} IA32_SEGMENT_DESCRIPTOR;\n\n///\n/// Byte packed structure for an 16-bit real mode thunks.\n///\ntypedef struct {\n IA32_REGISTER_SET *RealModeState;\n void *RealModeBuffer;\n uint32_t RealModeBufferSize;\n uint32_t ThunkAttributes;\n} THUNK_CONTEXT;\n\n#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001\n#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\n#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\n\n#pragma pack(1)\n\n#define NUM_REAL_GDT_ENTRIES 8\n#define CONVENTIONAL_MEMORY_TOP 0xA0000 // 640 KB\n#define INITIAL_VALUE_BELOW_1K 0x0\n\n//\n// Define what a processor GDT looks like\n//\ntypedef struct {\n uint16_t LimitLow;\n uint16_t BaseLow;\n uint8_t BaseMid;\n uint8_t Attribute;\n uint8_t LimitHi;\n uint8_t BaseHi;\n} GDT64;\n\n//\n// Define what a processor descriptor looks like\n// This data structure must be kept in sync with ASM STRUCT in Thunk.inc\n//\ntypedef struct {\n uint16_t Limit;\n uint64_t Base;\n} DESCRIPTOR64;\n\ntypedef struct {\n uint16_t Limit;\n uint32_t Base;\n} DESCRIPTOR32;\n\n//\n// Low stub lay out\n//\n#define LOW_STACK_SIZE (8 * 1024) // 8k?\n#define EFI_MAX_E820_ENTRY 100\n#define FIRST_INSTANCE 1\n#define NOT_FIRST_INSTANCE 0\n\ntypedef struct {\n //\n // Space for the code\n // The address of Code is also the beginning of the relocated Thunk code\n //\n uint8_t Code[4096]; // ?\n\n //\n // Data for the code (cs releative)\n //\n DESCRIPTOR64 X64GdtDesc; // Protected mode GDT\n DESCRIPTOR64 X64IdtDesc; // Protected mode IDT\n uintptr_t X64Ss;\n uintptr_t X64Esp;\n\n uintptr_t RealStack;\n DESCRIPTOR32 RealModeIdtDesc;\n DESCRIPTOR32 RealModeGdtDesc;\n\n //\n // real-mode GDT (temporary GDT with two real mode segment descriptors)\n //\n GDT64 RealModeGdt[NUM_REAL_GDT_ENTRIES];\n uint64_t PageMapLevel4;\n\n //\n // A low memory stack\n //\n uint8_t Stack[LOW_STACK_SIZE];\n} LOW_MEMORY_THUNK;\n\n#pragma pack()\n\nextern uintptr_t LegacyBiosInitializeThunkAndTable(uintptr_t MemoryAddress, size_t data_size);\n\nextern bool LegacyBiosFarCall86 (uint16_t Segment, uint16_t Offset, EFI_IA32_REGISTER_SET *Regs, void *Stack, uintptr_t StackSize);\n\n#endif\n" } ]